<s> DEBUG ( dbgs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; dbgs ( ) << '\n' ) ; if ( Node -> isMachineOpcode ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; dbgs ( ) << '\n' ) ; return ; } switch ( Opcode ) { default : break ; case <STR_LIT> : { DebugLoc Empty ; const DebugLoc & DL = Node -> getDebugLoc ( ) ; if ( DL != Empty ) errs ( ) << <STR_LIT> << DL . getLine ( ) << <STR_LIT> ; else errs ( ) << <STR_LIT> ; errs ( ) << <STR_LIT> ; Node -> print ( errs ( ) , CurDAG ) ; errs ( ) << <STR_LIT> ; break ; } case <STR_LIT> : { unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDLoc DL ( Node ) ; SDValue Chain = Node -> getOperand ( <NUM_LIT> ) ; SDValue N1 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Skb = Node -> getOperand ( <NUM_LIT> ) ; SDValue N3 = Node -> getOperand ( <NUM_LIT> ) ; SDValue R6Reg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ; Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ; break ; } } break ; } case <STR_LIT> : { int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; unsigned Opc = <STR_LIT> ; if ( Node -> hasOneUse ( ) ) { CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI ) ; return ;


<s> if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , DL , <STR_LIT> ) ; return true ; } } Base = Addr ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; return true ;


<s> if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , DL , <STR_LIT> ) ;


<s> if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; else return false ; Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , DL , <STR_LIT> ) ; return true ; }


<s> if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; else return false ; Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , DL , <STR_LIT> ) ; return true ;


<s> computeRegisterProperties ( STI . getRegisterInfo ( ) ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; } setBooleanContents ( ZeroOrOneBooleanContent ) ; setMinFunctionAlignment ( <NUM_LIT> ) ; setPrefFunctionAlignment ( <NUM_LIT> ) ; MaxStoresPerMemset = MaxStoresPerMemsetOptSize = <NUM_LIT> ; MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = <NUM_LIT> ; MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = <NUM_LIT> ;


<s> static bool classof ( const DiagnosticInfo * DI ) {

return DI -> getKind ( ) == getKindID ( ) ;


<s> DiagnosticInfoUnsupported ( SDLoc DLoc , const Function & Fn , const Twine & Desc , SDValue Value ) : DiagnosticInfo ( getKindID ( ) , DS_Error ) , DLoc ( DLoc . getDebugLoc ( ) ) , Description ( Desc ) , Fn ( Fn ) , Value ( Value ) {


<s> case <STR_LIT> : BuildMI ( BB , DL , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( Copy1MBB ) ; break ; case <STR_LIT> : BuildMI ( BB , DL , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( Copy1MBB ) ; break ; case <STR_LIT> : BuildMI ( BB , DL , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( Copy1MBB ) ; break ; default : report_fatal_error ( <STR_LIT> + Twine ( CC ) ) ; } BB = Copy0MBB ; BB -> addSuccessor ( Copy1MBB ) ; BB = Copy1MBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII . get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( Copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( ThisMBB ) ;


<s> F -> insert ( I , Copy1MBB ) ; Copy1MBB -> splice ( Copy1MBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; Copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( Copy0MBB ) ; BB -> addSuccessor ( Copy1MBB ) ; unsigned LHS = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned RHS = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int CC = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; switch ( CC ) { case <STR_LIT> : BuildMI ( BB , DL , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( Copy1MBB ) ; break ; case <STR_LIT> : BuildMI ( BB , DL , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( Copy1MBB ) ;


if ( KindID == <NUM_LIT> ) KindID = llvm :: getNextAvailablePluginDiagnosticKind ( ) ;


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Chain , LHS , RHS , DAG . getConstant ( CC , DL , <STR_LIT> ) , Dest ) ;


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; NegateCC ( LHS , RHS , CC ) ;


<s> } auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getConstant ( NumBytes , CLI . DL , PtrVT , true ) , CLI . DL ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , CLI . DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , CLI . DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , CLI . DL , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; else llvm_unreachable ( <STR_LIT> ) ; } SDValue InFlag ; for ( auto & Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , CLI . DL , Reg . first , Reg . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , CLI . DL , PtrVT , G -> getOffset ( ) , <NUM_LIT> ) ; else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , PtrVT , <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( auto & Reg : RegsToPass ) Ops . push_back ( DAG . getRegister ( Reg . first , Reg . second . getValueType ( ) ) ) ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; Chain = DAG . getNode ( <STR_LIT> , CLI . DL , NodeTys , Ops ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ;

Chain = DAG . getCALLSEQ_END ( Chain , DAG . getConstant ( NumBytes , CLI . DL , PtrVT , true ) , DAG . getConstant ( <NUM_LIT> , CLI . DL , PtrVT , true ) , InFlag , CLI . DL ) ;


<s> for ( auto & VA : ArgLocs ) { if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { default : { errs ( ) << <STR_LIT> << RegVT . getSimpleVT ( ) . SimpleTy << '\n' ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } } else {

DiagnosticInfoUnsupported Err ( DL , * MF . getFunction ( ) , <STR_LIT> , SDValue ( ) ) ;


<s> const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ;

SDValue GA = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> ) ;


<s> switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> :

return LowerGlobalAddress ( Op , DAG ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; MachineFunction & MF = DAG . getMachineFunction ( ) ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , * DAG . getContext ( ) ) ; if ( MF . getFunction ( ) -> getReturnType ( ) -> isAggregateType ( ) ) { DiagnosticInfoUnsupported Err ( DL , * MF . getFunction ( ) , <STR_LIT> , SDValue ( ) ) ; DAG . getContext ( ) -> diagnose ( Err ) ; } CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>64 ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ;

for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) {


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue TrueV = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc DL ( Op ) ; NegateCC ( LHS , RHS , CC ) ;

SDValue TargetCC = DAG . getConstant ( CC , DL , <STR_LIT> ) ;


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc DL ( Op ) ; NegateCC ( LHS , RHS , CC ) ; SDValue TargetCC = DAG . getConstant ( CC , DL , <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ;

SDValue Ops [ ] = { LHS , RHS , TargetCC , TrueV , FalseV } ;


<s> switch ( CC ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ( CC ) ;


<s>
OS
<<
<STR_LIT>
<<
Fn
.
getName
(
)
<<
' '
<<
*
Fn
.
getFunctionType
(
)
<<
'\n'
<<
Description
;
if
(
Value
)
Value
->
print
(
OS
)
;
OS
<<
'\n'
;


<s>
unsigned
Line
=
DIL
->
getLine
(
)
;
unsigned
Column
=
DIL
->
getColumn
(
)
;
OS
<<
Filename
<<
':'
<<
Line
<<
':'
<<
Column
<<
' '
;
}
OS
<<
<STR_LIT>
<<
Fn
.
getName
(
)
<<
' '
<<
*
Fn
.
getFunctionType
(
)
<<
'\n'
<<
Description
;


<s> bool shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const override { return true ;


<s> report_fatal_error ( <STR_LIT> + Twine ( CC ) ) ; } if ( isSelectOp ) BuildMI ( BB , DL , TII . get ( NewCC ) ) . addReg ( LHS ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( Copy1MBB ) ; else { int64_t imm32 = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( isInt < <NUM_LIT> > ( imm32 ) ) ; BuildMI ( BB , DL , TII . get ( NewCC ) ) . addReg ( LHS ) . addImm ( imm32 ) . addMBB ( Copy1MBB ) ; } BB = Copy0MBB ; BB -> addSuccessor ( Copy1MBB ) ; BB = Copy1MBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( Copy0MBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( ThisMBB ) ;


<s> BB -> addSuccessor ( Copy0MBB ) ; BB -> addSuccessor ( Copy1MBB ) ; unsigned LHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int CC = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int NewCC ; switch ( CC ) { case <STR_LIT> : NewCC = isSelectOp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectOp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectOp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectOp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectOp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectOp ? <STR_LIT> : <STR_LIT> ; break ; default : report_fatal_error ( <STR_LIT> + Twine ( CC ) ) ; } if ( isSelectOp ) BuildMI ( BB , DL , TII . get ( NewCC ) ) . addReg ( LHS ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( Copy1MBB ) ; else { int64_t imm32 = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( isInt < <NUM_LIT> > ( imm32 ) ) ; BuildMI ( BB , DL , TII . get ( NewCC ) ) . addReg ( LHS ) . addImm ( imm32 ) . addMBB ( Copy1MBB ) ; } BB = Copy0MBB ; BB -> addSuccessor ( Copy1MBB ) ; BB = Copy1MBB ;

BuildMI ( * BB , BB -> begin ( ) , DL , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( Copy0MBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( ThisMBB ) ;


<s> std :: string Str ; raw_string_ostream OS ( Str ) ; OS << Msg ; Val -> print ( OS ) ;


<s> EVT getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const override { return Op . size ( ) >= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ;


<s> return Op . size ( ) >= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ;


<s> bool isIntDivCheap ( EVT VT , AttributeList Attr ) const override { return true ;


<s> bool isIntDivCheap ( EVT VT , AttributeList Attr ) const override {


<s> return DAG . getCopyFromReg ( Chain , DL , <NUM_LIT> , Ins [ <NUM_LIT> ] . VT , InFlag ) . getValue ( <NUM_LIT> ) ; } CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT>64 ) ; for ( auto & Val : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , DL , Val . getLocReg ( ) , Val . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; }


<s> SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ;


<s> Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back ( Flag ) ; return DAG . getNode ( Opc , DL , <STR_LIT> , RetOps ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , * DAG . getContext ( ) ) ; if ( MF . getFunction ( ) -> getReturnType ( ) -> isAggregateType ( ) ) { fail ( DL , DAG , <STR_LIT> ) ; return DAG . getNode ( Opc , DL , <STR_LIT> , Chain ) ; } CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>64 ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ;

Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ;


<s> bool shouldReduceLoadWidth ( SDNode * Load , <STR_LIT> ExtTy , EVT NewVT ) const override {


<s> bool shouldReduceLoadWidth ( SDNode * Load , <STR_LIT> ExtTy , EVT NewVT ) const override { return false ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ;


<s> } case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } } else { fail ( DL , DAG , <STR_LIT> ) ; InVals . push_back ( DAG . getConstant ( <NUM_LIT> , DL , VA . getLocVT ( ) ) ) ; } } if ( IsVarArg || MF . getFunction ( ) -> hasStructRetAttr ( ) ) { fail ( DL , DAG , <STR_LIT> ) ; }


<s> SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc DL ( Op ) ; if ( ! getHasJmpExt ( ) ) NegateCC ( LHS , RHS , CC ) ; SDValue TargetCC = DAG . getConstant ( CC , DL , <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { LHS , RHS , TargetCC , TrueV , FalseV } ; return DAG . getNode ( <STR_LIT> , DL , VTs , Ops ) ;


<s> SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc DL ( Op ) ; if ( ! getHasJmpExt ( ) ) NegateCC ( LHS , RHS , CC ) ;


<s> BuildMI ( BB , DL , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( Copy1MBB ) ; break ; case <STR_LIT> : BuildMI ( BB , DL , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( Copy1MBB ) ; break ; case <STR_LIT> : BuildMI ( BB , DL , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( Copy1MBB ) ; break ; default : report_fatal_error ( <STR_LIT> + Twine ( CC ) ) ; } BB = Copy0MBB ; BB -> addSuccessor ( Copy1MBB ) ; BB = Copy1MBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII . get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( Copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( ThisMBB ) ; MI -> eraseFromParent ( ) ; return BB ;


<s> return NULL ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ;


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ;

SDValue Dest = Op . getOperand ( <NUM_LIT> ) ;


<s> auto & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & IsTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool IsVarArg = CLI . IsVarArg ; MachineFunction & MF = DAG . getMachineFunction ( ) ; IsTailCall = false ; switch ( CallConv ) { default : report_fatal_error ( <STR_LIT> ) ; case CallingConv :: Fast : case CallingConv :: C : break ; } SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT>64 ) ; unsigned NumBytes = CCInfo . getNextStackOffset ( ) ; if ( Outs . size ( ) >= <NUM_LIT> ) { DiagnosticInfoUnsupported Err ( CLI . DL , * MF . getFunction ( ) , <STR_LIT> , Callee ) ; DAG . getContext ( ) -> diagnose ( Err ) ; } for ( auto & Arg : Outs ) { <STR_LIT> Flags = Arg . Flags ; if ( ! Flags . isByVal ( ) ) continue ; DiagnosticInfoUnsupported Err ( CLI . DL , * MF . getFunction ( ) , <STR_LIT> , Callee ) ; DAG . getContext ( ) -> diagnose ( Err ) ; } Chain = DAG . getCALLSEQ_START ( Chain , DAG . getConstant ( NumBytes , getPointerTy ( ) , true ) , CLI . DL ) ;

SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ;


<s> SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT>64 ) ; unsigned NumBytes = CCInfo . getNextStackOffset ( ) ; if ( Outs . size ( ) >= <NUM_LIT> ) { DiagnosticInfoUnsupported Err ( CLI . DL , * MF . getFunction ( ) , <STR_LIT> , Callee ) ; DAG . getContext ( ) -> diagnose ( Err ) ; } for ( auto & Arg : Outs ) { <STR_LIT> Flags = Arg . Flags ; if ( ! Flags . isByVal ( ) ) continue ; DiagnosticInfoUnsupported Err ( CLI . DL , * MF . getFunction ( ) , <STR_LIT> , Callee ) ; DAG . getContext ( ) -> diagnose ( Err ) ; } Chain = DAG . getCALLSEQ_START ( Chain , DAG . getConstant ( NumBytes , getPointerTy ( ) , true ) , CLI . DL ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ;


<s> SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc DL ( Op ) ; NegateCC ( LHS , RHS , CC ) ; SDValue TargetCC = DAG . getConstant ( CC , <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { LHS , RHS , TargetCC , TrueV , FalseV } ;

return DAG . getNode ( <STR_LIT> , DL , VTs , Ops ) ;


<s>
raw_string_ostream
OS
(
Str
)
;
if
(
DLoc
.
isUnknown
(
)
==
false
)
{
DILocation
DIL
(
DLoc
.
getAsMDNode
(
Fn
.
getContext
(
)
)
)
;
StringRef
Filename
=
DIL
.
getFilename
(
)
;
unsigned
Line
=
DIL
.
getLineNumber
(
)
;
unsigned
Column
=
DIL
.
getColumnNumber
(
)
;
OS
<<
Filename
<<
':'
<<
Line
<<
':'
<<
Column
<<
' '
;
}

OS
<<
<STR_LIT>
<<
Fn
.
getName
(
)
<<
' '
<<
*
Fn
.
getFunctionType
(
)
<<
'\n'
<<
Description
;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; }

setBooleanContents ( ZeroOrOneBooleanContent ) ;


<s>
OS
<<
<STR_LIT>
<<
Fn
.
getName
(
)
<<
' '
<<
*
Fn
.
getFunctionType
(
)
<<
'\n'
<<
Description
;
if
(
Value
)
Value
->
print
(
OS
)
;
OS
<<
'\n'
;
OS
.
flush
(
)
;
DP
<<
Str
;


<s>
std
::
string
Str
;
raw_string_ostream
OS
(
Str
)
;
if
(
DLoc
)
{
DILocation
DIL
(
DLoc
.
getAsMDNode
(
)
)
;
StringRef
Filename
=
DIL
.
getFilename
(
)
;
unsigned
Line
=
DIL
.
getLineNumber
(
)
;
unsigned
Column
=
DIL
.
getColumnNumber
(
)
;
OS
<<
Filename
<<
':'
<<
Line
<<
':'
<<
Column
<<
' '
;


<s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * ThisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * Copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * Copy1MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , Copy0MBB ) ; F -> insert ( I , Copy1MBB ) ; Copy1MBB -> splice ( Copy1MBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; Copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( Copy0MBB ) ; BB -> addSuccessor ( Copy1MBB ) ; unsigned LHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int CC = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int NewCC ; switch ( CC ) { case <STR_LIT> : NewCC = isSelectOp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectOp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectOp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectOp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectOp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectOp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> :


<s> else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } } else { fail ( DL , DAG , <STR_LIT> ) ; InVals . push_back ( DAG . getConstant ( <NUM_LIT> , DL , VA . getLocVT ( ) ) ) ; } }

if ( IsVarArg || MF . getFunction ( ) . hasStructRetAttr ( ) ) {


<s> if ( ! getHasJmpExt ( ) ) NegateCC ( LHS , RHS , CC ) ; SDValue TargetCC = DAG . getConstant ( CC , DL , <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; if ( isa < ConstantSDNode > ( LHS . getNode ( ) ) ) std :: swap ( LHS , RHS ) ;


<s> <STR_LIT> SimpleTy = RegVT . getSimpleVT ( ) . SimpleTy ; switch ( SimpleTy ) { default : { errs ( ) << <STR_LIT> << RegVT . getEVTString ( ) << '\n' ; llvm_unreachable ( nullptr ) ; } case <STR_LIT> : case <STR_LIT> : Register VReg = RegInfo . createVirtualRegister ( SimpleTy == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; break ; } } else { fail ( DL , DAG , <STR_LIT> ) ;

InVals . push_back ( DAG . getConstant ( <NUM_LIT> , DL , VA . getLocVT ( ) ) ) ;


<s> report_fatal_error ( <STR_LIT> + Twine ( CC ) ) ; } Register LHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isSignedCmp = ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ; if ( is32BitCmp && ! HasJmp32 ) LHS = EmitSubregExt ( MI , BB , LHS , isSignedCmp ) ; if ( isSelectRROp ) { Register RHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( is32BitCmp && ! HasJmp32 ) RHS = EmitSubregExt ( MI , BB , RHS , isSignedCmp ) ; BuildMI ( BB , DL , TII . get ( NewCC ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( Copy1MBB ) ; } else { int64_t imm32 = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( isInt < <NUM_LIT> > ( imm32 ) ) ; BuildMI ( BB , DL , TII . get ( NewCC ) ) . addReg ( LHS ) . addImm ( imm32 ) . addMBB ( Copy1MBB ) ; } BB = Copy0MBB ; BB -> addSuccessor ( Copy1MBB ) ; BB = Copy1MBB ;


<s> SET_NEWCC ( SETNE , JNE ) ; SET_NEWCC ( SETLT , JSLT ) ; SET_NEWCC ( SETULT , JULT ) ; SET_NEWCC ( SETLE , JSLE ) ; SET_NEWCC ( SETULE , JULE ) ; default : report_fatal_error ( <STR_LIT> + Twine ( CC ) ) ; } Register LHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isSignedCmp = ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ; if ( is32BitCmp && ! HasJmp32 ) LHS = EmitSubregExt ( MI , BB , LHS , isSignedCmp ) ; if ( isSelectRROp ) { Register RHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( is32BitCmp && ! HasJmp32 ) RHS = EmitSubregExt ( MI , BB , RHS , isSignedCmp ) ; BuildMI ( BB , DL , TII . get ( NewCC ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( Copy1MBB ) ; } else { int64_t imm32 = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( isInt < <NUM_LIT> > ( imm32 ) ) ; BuildMI ( BB , DL , TII . get ( NewCC ) ) . addReg ( LHS ) . addImm ( imm32 ) . addMBB ( Copy1MBB ) ;


<s> Register PromotedReg2 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , DL , TII . get ( <STR_LIT> ) , PromotedReg0 ) . addReg ( Reg ) ; BuildMI ( BB , DL , TII . get ( <STR_LIT> ) , PromotedReg1 ) . addReg ( PromotedReg0 ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII . get ( RShiftOp ) , PromotedReg2 ) . addReg ( PromotedReg1 ) . addImm ( <NUM_LIT> ) ; return PromotedReg2 ;


<s> DebugLoc DL = MI . getDebugLoc ( ) ; MachineRegisterInfo & RegInfo = F -> getRegInfo ( ) ; if ( ! isSigned ) { Register PromotedReg0 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , DL , TII . get ( <STR_LIT> ) , PromotedReg0 ) . addReg ( Reg ) ; return PromotedReg0 ; } Register PromotedReg0 = RegInfo . createVirtualRegister ( RC ) ; Register PromotedReg1 = RegInfo . createVirtualRegister ( RC ) ; Register PromotedReg2 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , DL , TII . get ( <STR_LIT> ) , PromotedReg0 ) . addReg ( Reg ) ;

BuildMI ( BB , DL , TII . get ( <STR_LIT> ) , PromotedReg1 ) . addReg ( PromotedReg0 ) . addImm ( <NUM_LIT> ) ;


<s> <ISA_LIT>TargetLowering :: ConstraintType <ISA_LIT>TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'w' : return C_RegisterClass ; }


<s> case 'r' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'w' : if ( HasAlu32 ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; default : break ;


<s> switch ( AM . Scale ) { case <NUM_LIT> : break ; case <NUM_LIT> : if ( ! AM . HasBaseReg ) break ; return false ; default :


<s> bool <ISA_LIT>TargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ;

unsigned NumBits1 = VT1 . getSizeInBits ( ) ;


<s> bool <ISA_LIT>TargetLowering :: isZExtFree ( EVT VT1 , EVT VT2 ) const { if ( ! getHasAlu32 ( ) || ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ; unsigned NumBits1 = VT1 . getSizeInBits ( ) ; unsigned NumBits2 = VT2 . getSizeInBits ( ) ; return NumBits1 == <NUM_LIT> && NumBits2 == <NUM_LIT> ;


<s> if ( ! getHasAlu32 ( ) || ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ; unsigned NumBits1 = VT1 . getSizeInBits ( ) ; unsigned NumBits2 = VT2 . getSizeInBits ( ) ;


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; if ( ! getHasJmpExt ( ) ) NegateCC ( LHS , RHS , CC ) ;

return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Chain , LHS , RHS , DAG . getConstant ( CC , DL , LHS . getValueType ( ) ) , Dest ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerBR_CC ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { switch ( CallConv ) { default : report_fatal_error ( <STR_LIT> ) ; case CallingConv :: C : case CallingConv :: Fast : break ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , getHasAlu32 ( ) ? CC_<ISA_LIT>32 : CC_<ISA_LIT>64 ) ; for ( auto & VA : ArgLocs ) { if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; <STR_LIT> SimpleTy = RegVT . getSimpleVT ( ) . SimpleTy ; switch ( SimpleTy ) { default : { errs ( ) << <STR_LIT> << RegVT . getEVTString ( ) << '\n' ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : Register VReg = RegInfo . createVirtualRegister ( SimpleTy == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ) ;

RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ;


<s> case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> :


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( HasAlu32 || Opcode == <STR_LIT> ) err_msg = <STR_LIT> ; else err_msg = <STR_LIT> ; break ; } SDLoc DL ( N ) ;


<s> setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } if ( STI . getHasAlu32 ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; } setBooleanContents ( ZeroOrOneBooleanContent ) ; setMinFunctionAlignment ( <NUM_LIT> ) ;

setPrefFunctionAlignment ( <NUM_LIT> ) ;


<s> } unsigned LHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isSignedCmp = ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ; if ( is32BitCmp ) LHS = EmitSubregExt ( MI , BB , LHS , isSignedCmp ) ; if ( isSelectRROp ) { unsigned RHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( is32BitCmp ) RHS = EmitSubregExt ( MI , BB , RHS , isSignedCmp ) ; BuildMI ( BB , DL , TII . get ( NewCC ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( Copy1MBB ) ; } else { int64_t imm32 = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( isInt < <NUM_LIT> > ( imm32 ) ) ; BuildMI ( BB , DL , TII . get ( NewCC ) ) . addReg ( LHS ) . addImm ( imm32 ) . addMBB ( Copy1MBB ) ; } BB = Copy0MBB ; BB -> addSuccessor ( Copy1MBB ) ; BB = Copy1MBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( Copy0MBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( ThisMBB ) ;


<s> SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc DL ( Op ) ; if ( ! getHasJmpExt ( ) ) NegateCC ( LHS , RHS , CC ) ; SDValue TargetCC = DAG . getConstant ( CC , DL , LHS . getValueType ( ) ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; if ( isa < ConstantSDNode > ( LHS . getNode ( ) ) ) std :: swap ( LHS , RHS ) ;


<s> Copy1MBB -> splice ( Copy1MBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; Copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( Copy0MBB ) ; BB -> addSuccessor ( Copy1MBB ) ; unsigned LHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned RHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int CC = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; switch ( CC ) { case <STR_LIT> : BuildMI ( BB , DL , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( Copy1MBB ) ; break ; case <STR_LIT> : BuildMI ( BB , DL , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( Copy1MBB ) ; break ; case <STR_LIT> : BuildMI ( BB , DL , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( Copy1MBB ) ; break ;


<s> EVT getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , const AttributeList & FuncAttributes ) const override {


<s> CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT>64 ) ; unsigned NumBytes = CCInfo . getNextStackOffset ( ) ; if ( Outs . size ( ) > MaxArgs ) fail ( CLI . DL , DAG , <STR_LIT> , Callee ) ; for ( auto & Arg : Outs ) { <STR_LIT> Flags = Arg . Flags ; if ( ! Flags . isByVal ( ) ) continue ; fail ( CLI . DL , DAG , <STR_LIT> , Callee ) ; } auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getConstant ( NumBytes , CLI . DL , PtrVT , true ) , CLI . DL ) ; SmallVector < std :: pair < unsigned , SDValue > , MaxArgs > RegsToPass ; for ( unsigned i = <NUM_LIT> , e = std :: min ( static_cast < unsigned > ( ArgLocs . size ( ) ) , MaxArgs ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , CLI . DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , CLI . DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , CLI . DL , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; else llvm_unreachable ( <STR_LIT> ) ; } SDValue InFlag ; for ( auto & Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , CLI . DL , Reg . first , Reg . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) {


<s> computeRegisterProperties ( STI . getRegisterInfo ( ) ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto VT : { <STR_LIT> , <STR_LIT> } ) { if ( VT == <STR_LIT> && ! STI . getHasAlu32 ( ) ) continue ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; }


<s> std :: string Str ; raw_string_ostream OS ( Str ) ; OS << Msg ; Val -> print ( OS ) ; OS . flush ( ) ;

DAG . getContext ( ) -> diagnose ( DiagnosticInfoUnsupported ( * MF . getFunction ( ) , Str , DL . getDebugLoc ( ) ) ) ;


<s> static void fail ( SDLoc DL , SelectionDAG & DAG , const char * Msg , SDValue Val ) { MachineFunction & MF = DAG . getMachineFunction ( ) ;


<s> fail ( CLI . DL , DAG , <STR_LIT> , Callee ) ; } auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getConstant ( NumBytes , CLI . DL , PtrVT , true ) , CLI . DL ) ; SmallVector < std :: pair < unsigned , SDValue > , MaxArgs > RegsToPass ; for ( unsigned i = <NUM_LIT> , e = std :: min ( static_cast < unsigned > ( ArgLocs . size ( ) ) , MaxArgs ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , CLI . DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , CLI . DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , CLI . DL , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; else llvm_unreachable ( <STR_LIT> ) ; } SDValue InFlag ; for ( auto & Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , CLI . DL , Reg . first , Reg . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , * DAG . getContext ( ) ) ; if ( Ins . size ( ) >= <NUM_LIT> ) { fail ( DL , DAG , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i != e ; ++ i ) InVals . push_back ( DAG . getConstant ( <NUM_LIT> , DL , Ins [ i ] . VT ) ) ; return DAG . getCopyFromReg ( Chain , DL , <NUM_LIT> , Ins [ <NUM_LIT> ] . VT , InFlag ) . getValue ( <NUM_LIT> ) ; } CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT>64 ) ; for ( auto & Val : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , DL , Val . getLocReg ( ) , Val . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ;


<s> CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>64 ) ; for ( auto & VA : ArgLocs ) { if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { default : { errs ( ) << <STR_LIT> << RegVT . getEVTString ( ) << '\n' ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } } else { fail ( DL , DAG , <STR_LIT> ) ; InVals . push_back ( DAG . getConstant ( <NUM_LIT> , DL , VA . getLocVT ( ) ) ) ; } } if ( IsVarArg || MF . getFunction ( ) -> hasStructRetAttr ( ) ) { fail ( DL , DAG , <STR_LIT> ) ; }


<s> SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back ( Flag ) ;

return DAG . getNode ( Opc , DL , <STR_LIT> , RetOps ) ;


<s> setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } if ( STI . getHasAlu32 ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , STI . getHasJmp32 ( ) ? Custom : Promote ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; } setBooleanContents ( ZeroOrOneBooleanContent ) ;

setMinFunctionAlignment ( llvm :: Align ( <NUM_LIT> ) ) ;


<s> BuildMI ( BB , DL , TII . get ( <STR_LIT> ) , PromotedReg0 ) . addReg ( Reg ) ; BuildMI ( BB , DL , TII . get ( <STR_LIT> ) , PromotedReg1 ) . addReg ( PromotedReg0 ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII . get ( RShiftOp ) , PromotedReg2 ) . addReg ( PromotedReg1 ) . addImm ( <NUM_LIT> ) ;


<s> Register PromotedReg1 = RegInfo . createVirtualRegister ( RC ) ; Register PromotedReg2 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , DL , TII . get ( <STR_LIT> ) , PromotedReg0 ) . addReg ( Reg ) ; BuildMI ( BB , DL , TII . get ( <STR_LIT> ) , PromotedReg1 ) . addReg ( PromotedReg0 ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII . get ( RShiftOp ) , PromotedReg2 ) . addReg ( PromotedReg1 ) . addImm ( <NUM_LIT> ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto VT : { <STR_LIT> , <STR_LIT> } ) { if ( VT == <STR_LIT> && ! STI . getHasAlu32 ( ) ) continue ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } if ( STI . getHasAlu32 ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ;


<s> setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } if ( STI . getHasAlu32 ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; } setBooleanContents ( ZeroOrOneBooleanContent ) ; setMinFunctionAlignment ( <NUM_LIT> ) ; setPrefFunctionAlignment ( <NUM_LIT> ) ; MaxStoresPerMemset = MaxStoresPerMemsetOptSize = <NUM_LIT> ; MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = <NUM_LIT> ; MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = <NUM_LIT> ; HasAlu32 = STI . getHasAlu32 ( ) ;


<s> static void fail ( const SDLoc & DL , SelectionDAG & DAG , const char * Msg ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; DAG . getContext ( ) -> diagnose ( DiagnosticInfoUnsupported ( * MF . getFunction ( ) , Msg , DL . getDebugLoc ( ) ) ) ;


<s> switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , CLI . DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , CLI . DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , CLI . DL , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; else llvm_unreachable ( <STR_LIT> ) ; } SDValue InFlag ; for ( auto & Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , CLI . DL , Reg . first , Reg . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , CLI . DL , getPointerTy ( ) , G -> getOffset ( ) , <NUM_LIT> ) ; else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , getPointerTy ( ) , <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( auto & Reg : RegsToPass ) Ops . push_back ( DAG . getRegister ( Reg . first , Reg . second . getValueType ( ) ) ) ;

if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setMinFunctionAlignment ( <NUM_LIT> ) ; setPrefFunctionAlignment ( <NUM_LIT> ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ;


<s> MachineFunction :: iterator I = BB ; ++ I ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * copy1MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , copy0MBB ) ; F -> insert ( I , copy1MBB ) ; copy1MBB -> splice ( copy1MBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( copy1MBB ) ; unsigned LHS = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned RHS = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int CC = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; switch ( CC ) { case <STR_LIT> : BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( copy1MBB ) ; break ; case <STR_LIT> : BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( copy1MBB ) ; break ; case <STR_LIT> : BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( copy1MBB ) ; break ; case <STR_LIT> : BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( copy1MBB ) ; break ; case <STR_LIT> : BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( copy1MBB ) ; break ; case <STR_LIT> : BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( copy1MBB ) ; break ; default :

report_fatal_error ( <STR_LIT> + Twine ( CC ) ) ;


<s> switch ( CC ) { case <STR_LIT> : BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( copy1MBB ) ; break ; case <STR_LIT> : BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( copy1MBB ) ; break ; case <STR_LIT> : BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( copy1MBB ) ; break ; case <STR_LIT> : BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( copy1MBB ) ; break ; case <STR_LIT> : BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( copy1MBB ) ; break ; case <STR_LIT> : BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( copy1MBB ) ; break ; default : report_fatal_error ( <STR_LIT> + Twine ( CC ) ) ; } BB = copy0MBB ; BB -> addSuccessor ( copy1MBB ) ; BB = copy1MBB ; BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ;


<s> default : return NULL ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; NegateCC ( LHS , RHS , CC ) ;

return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Chain , LHS , RHS , DAG . getConstant ( CC , <STR_LIT> ) , Dest ) ;


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; DebugLoc dl = Op . getDebugLoc ( ) ;


<s> CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; <STR_LIT> Flags = Outs [ i ] . Flags ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , CLI . DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , CLI . DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , CLI . DL , VA . getLocVT ( ) , Arg ) ; break ; } if ( Flags . isByVal ( ) ) Arg = ByValArgs [ j ++ ] ; if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } } SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , CLI . DL , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , CLI . DL , getPointerTy ( ) , G -> getOffset ( ) , <NUM_LIT> ) ; } else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , getPointerTy ( ) , <NUM_LIT> ) ; } SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ;

SmallVector < SDValue , <NUM_LIT> > Ops ;


<s> CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT>64 ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; }


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; } return Chain ;


<s> CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>64 ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { default : { errs ( ) << <STR_LIT> << RegVT . getSimpleVT ( ) . SimpleTy << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } } else {


<s> SDLoc dl ( Op ) ; DebugLoc dl = Op . getDebugLoc ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA ) ;


<s> case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ;


<s> case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { errs ( ) << <STR_LIT> << DAG . getMachineFunction ( ) . getName ( ) << <STR_LIT> ; DAG . getMachineFunction ( ) . getFunction ( ) -> getFunctionType ( ) -> dump ( ) ; errs ( ) << <STR_LIT> ;


<s> SDValue TrueV = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc dl ( Op ) ; DebugLoc dl = Op . getDebugLoc ( ) ; NegateCC ( LHS , RHS , CC ) ; SDValue TargetCC = DAG . getConstant ( CC , <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ;


<s> SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( LHS ) ; Ops . push_back ( RHS ) ; Ops . push_back ( TargetCC ) ; Ops . push_back ( TrueV ) ; Ops . push_back ( FalseV ) ; SDValue sel = DAG . getNode ( <STR_LIT> , dl , VTs , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ;

DEBUG ( errs ( ) << <STR_LIT> ; sel . dumpr ( ) ; errs ( ) << <STR_LIT> ) ;


<s> std :: swap ( LHS , RHS ) ; return true ; case <STR_LIT> : CC = <STR_LIT> ; std :: swap ( LHS , RHS ) ; return true ; case <STR_LIT> : CC = <STR_LIT> ;


<s> return true ; case <STR_LIT> : CC = <STR_LIT> ; std :: swap ( LHS , RHS ) ; return true ; case <STR_LIT> : CC = <STR_LIT> ; std :: swap ( LHS , RHS ) ;


<s> case <STR_LIT> : NewCC = isSelectOp ? <STR_LIT> : <STR_LIT> ; break ; default : report_fatal_error ( <STR_LIT> + Twine ( CC ) ) ; } if ( isSelectOp ) BuildMI ( BB , DL , TII . get ( NewCC ) ) . addReg ( LHS ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( Copy1MBB ) ; else BuildMI ( BB , DL , TII . get ( NewCC ) ) . addReg ( LHS ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) . addMBB ( Copy1MBB ) ; BB = Copy0MBB ; BB -> addSuccessor ( Copy1MBB ) ; BB = Copy1MBB ;

BuildMI ( * BB , BB -> begin ( ) , DL , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( Copy0MBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( ThisMBB ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto VT : { <STR_LIT> , <STR_LIT> } ) { if ( VT == <STR_LIT> && ! STI . getHasAlu32 ( ) ) continue ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } if ( STI . getHasAlu32 ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , STI . getHasJmp32 ( ) ? Custom : Promote ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , * DAG . getContext ( ) ) ; if ( Ins . size ( ) >= <NUM_LIT> ) {


<s> Chain = DAG . getCopyFromReg ( Chain , DL , Val . getLocReg ( ) , Val . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; } return Chain ;


<s> if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { default : { errs ( ) << <STR_LIT> << RegVT . getSimpleVT ( ) . SimpleTy << '\n' ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } } else { fail ( DL , DAG , <STR_LIT> ) ; } } if ( IsVarArg || MF . getFunction ( ) -> hasStructRetAttr ( ) ) { fail ( DL , DAG , <STR_LIT> ) ; } return Chain ;


<s> fail ( DL , DAG , <STR_LIT> ) ; } CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>64 ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ;


<s> setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } if ( STI . getHasAlu32 ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; } setBooleanContents ( ZeroOrOneBooleanContent ) ; setMinFunctionAlignment ( <NUM_LIT> ) ; setPrefFunctionAlignment ( <NUM_LIT> ) ; if ( <ISA_LIT>ExpandMemcpyInOrder ) { MaxStoresPerMemset = MaxStoresPerMemsetOptSize = <NUM_LIT> ; MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = <NUM_LIT> ; MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = <NUM_LIT> ; } else { unsigned CommonMaxStores = STI . getSelectionDAGInfo ( ) -> getCommonMaxStoresPerMemFunc ( ) ; MaxStoresPerMemset = MaxStoresPerMemsetOptSize = CommonMaxStores ; MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = CommonMaxStores ; MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = CommonMaxStores ;


<s> Copy1MBB -> splice ( Copy1MBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; Copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( Copy0MBB ) ; BB -> addSuccessor ( Copy1MBB ) ; int CC = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int NewCC ; switch ( CC ) { case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; default : report_fatal_error ( <STR_LIT> + Twine ( CC ) ) ; } unsigned LHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isSignedCmp = ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ; if ( is32BitCmp ) LHS = EmitSubregExt ( MI , BB , LHS , isSignedCmp ) ; if ( isSelectRROp ) { unsigned RHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( is32BitCmp ) RHS = EmitSubregExt ( MI , BB , RHS , isSignedCmp ) ;

BuildMI ( BB , DL , TII . get ( NewCC ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( Copy1MBB ) ;


<s> DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Opc = MI . getOpcode ( ) ; bool isSelectRROp = ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ; bool isMemcpyOp = Opc == <STR_LIT> ; bool isSelectRIOp = ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ; assert ( ( isSelectRROp || isSelectRIOp || isMemcpyOp ) && <STR_LIT> ) ; if ( isMemcpyOp ) return EmitInstrWithCustomInserterMemcpy ( MI , BB ) ; bool is32BitCmp = ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * ThisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * Copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * Copy1MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , Copy0MBB ) ; F -> insert ( I , Copy1MBB ) ; Copy1MBB -> splice ( Copy1MBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; Copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( Copy0MBB ) ; BB -> addSuccessor ( Copy1MBB ) ; int CC = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int NewCC ; switch ( CC ) { case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; default : report_fatal_error ( <STR_LIT> + Twine ( CC ) ) ; } unsigned LHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;

bool isSignedCmp = ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ;


<s> unsigned ScratchReg ; ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ;

MIB . addReg ( ScratchReg , RegState :: Define | RegState :: Dead | RegState :: EarlyClobber ) ;


<s> const TargetRegisterClass * RC = getRegClassFor ( <STR_LIT> ) ; int RShiftOp = isSigned ? <STR_LIT> : <STR_LIT> ; MachineFunction * F = BB -> getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineRegisterInfo & RegInfo = F -> getRegInfo ( ) ; unsigned PromotedReg0 = RegInfo . createVirtualRegister ( RC ) ; unsigned PromotedReg1 = RegInfo . createVirtualRegister ( RC ) ;

unsigned PromotedReg2 = RegInfo . createVirtualRegister ( RC ) ;


<s> std :: string Str ; raw_string_ostream OS ( Str ) ; OS << Msg ; Val -> print ( OS ) ;


<s> case 'r' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; default : break ; } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ;


<s> return ( getHasAlu32 ( ) && VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ;


<s> MVT <ISA_LIT>TargetLowering :: getScalarShiftAmountTy ( const DataLayout & DL , EVT VT ) const {

return ( getHasAlu32 ( ) && VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ;


<s> break ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const {


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; if ( ! getHasJmpExt ( ) ) NegateCC ( LHS , RHS , CC ) ;

return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Chain , LHS , RHS , DAG . getConstant ( CC , DL , <STR_LIT> ) , Dest ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerBR_CC ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ;

SDValue Dest = Op . getOperand ( <NUM_LIT> ) ;


<s> switch ( CallConv ) { default : report_fatal_error ( <STR_LIT> ) ; case CallingConv :: Fast : case CallingConv :: C : break ; } SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallOperands ( Outs , getHasAlu32 ( ) ? CC_<ISA_LIT>32 : CC_<ISA_LIT>64 ) ; unsigned NumBytes = CCInfo . getNextStackOffset ( ) ; if ( Outs . size ( ) > MaxArgs ) fail ( CLI . DL , DAG , <STR_LIT> , Callee ) ; for ( auto & Arg : Outs ) { <STR_LIT> Flags = Arg . Flags ; if ( ! Flags . isByVal ( ) ) continue ; fail ( CLI . DL , DAG , <STR_LIT> , Callee ) ; } auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; Chain = DAG . getCALLSEQ_START ( Chain , NumBytes , <NUM_LIT> , CLI . DL ) ; SmallVector < std :: pair < unsigned , SDValue > , MaxArgs > RegsToPass ; for ( unsigned i = <NUM_LIT> , e = std :: min ( static_cast < unsigned > ( ArgLocs . size ( ) ) , MaxArgs ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , CLI . DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , CLI . DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , CLI . DL , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; else llvm_unreachable ( <STR_LIT> ) ; } SDValue InFlag ; for ( auto & Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , CLI . DL , Reg . first , Reg . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; }

if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) {


<s> for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i != e ; ++ i ) InVals . push_back ( DAG . getConstant ( <NUM_LIT> , DL , Ins [ i ] . VT ) ) ; return DAG . getCopyFromReg ( Chain , DL , <NUM_LIT> , Ins [ <NUM_LIT> ] . VT , InFlag ) . getValue ( <NUM_LIT> ) ; } CCInfo . AnalyzeCallResult ( Ins , getHasAlu32 ( ) ? RetCC_<ISA_LIT>32 : RetCC_<ISA_LIT>64 ) ; for ( auto & Val : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , DL , Val . getLocReg ( ) , Val . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ;


<s> MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , getHasAlu32 ( ) ? CC_<ISA_LIT>32 : CC_<ISA_LIT>64 ) ; for ( auto & VA : ArgLocs ) { if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; <STR_LIT> SimpleTy = RegVT . getSimpleVT ( ) . SimpleTy ; switch ( SimpleTy ) { default : { errs ( ) << <STR_LIT> << RegVT . getEVTString ( ) << '\n' ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( SimpleTy == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; break ; } } else { fail ( DL , DAG , <STR_LIT> ) ; InVals . push_back ( DAG . getConstant ( <NUM_LIT> , DL , VA . getLocVT ( ) ) ) ; } } if ( IsVarArg || MF . getFunction ( ) . hasStructRetAttr ( ) ) { fail ( DL , DAG , <STR_LIT> ) ; } return Chain ;


<s> assert ( N -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; SDLoc DL ( Op ) ; const GlobalValue * GV = N -> getGlobal ( ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , GA ) ;


<s> auto N = cast < GlobalAddressSDNode > ( Op ) ; assert ( N -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; SDLoc DL ( Op ) ;

const GlobalValue * GV = N -> getGlobal ( ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & DL , SelectionDAG & DAG ) const { unsigned Opc = <STR_LIT> ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; MachineFunction & MF = DAG . getMachineFunction ( ) ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , * DAG . getContext ( ) ) ; if ( MF . getFunction ( ) . getReturnType ( ) -> isAggregateType ( ) ) { fail ( DL , DAG , <STR_LIT> ) ; return DAG . getNode ( Opc , DL , <STR_LIT> , Chain ) ; } CCInfo . AnalyzeReturn ( Outs , getHasAlu32 ( ) ? RetCC_<ISA_LIT>32 : RetCC_<ISA_LIT>64 ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ;

for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) {


<s> SDValue TargetCC = DAG . getConstant ( CC , DL , LHS . getValueType ( ) ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { LHS , RHS , TargetCC , TrueV , FalseV } ; return DAG . getNode ( <STR_LIT> , DL , VTs , Ops ) ;


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue TrueV = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc DL ( Op ) ;

if ( ! getHasJmpExt ( ) ) NegateCC ( LHS , RHS , CC ) ;


<s> explicit <ISA_LIT>MCAsmInfo ( const Triple & TT ) { if ( TT . getArch ( ) == Triple :: bpfeb ) IsLittleEndian = false ; PrivateGlobalPrefix = <STR_LIT> ;


<s> WeakRefDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; HasSingleParameterDotFile = false ;


<s> explicit <ISA_LIT>MCAsmInfo ( const Triple & TT ) { if ( TT . getArch ( ) == Triple :: bpfeb ) IsLittleEndian = false ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; HasSingleParameterDotFile = false ;


<s> explicit <ISA_LIT>MCAsmInfo ( StringRef TT ) { PrivateGlobalPrefix = <STR_LIT> ;


<s> HasSingleParameterDotFile = false ; HasDotTypeDotSizeDirective = false ;


<s> UsesELFSectionDirectiveForBSS = true ; HasSingleParameterDotFile = false ;


<s> WeakRefDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; HasSingleParameterDotFile = true ; HasDotTypeDotSizeDirective = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; MinInstAlignment = <NUM_LIT> ; CodePointerSize = <NUM_LIT> ; UseIntegratedAssembler = false ;


<s> explicit <ISA_LIT>MCAsmInfo ( const Triple & TT , const MCTargetOptions & Options ) { if ( TT . getArch ( ) == Triple :: bpfeb ) IsLittleEndian = false ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; HasSingleParameterDotFile = true ; HasDotTypeDotSizeDirective = true ;


<s> if ( TT . getArch ( ) == Triple :: bpfeb ) IsLittleEndian = false ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; HasSingleParameterDotFile = false ; HasDotTypeDotSizeDirective = false ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; MinInstAlignment = <NUM_LIT> ; PointerSize = <NUM_LIT> ;


<s> if ( TT . getArch ( ) == Triple :: bpfeb ) IsLittleEndian = false ;


<s> PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; HasSingleParameterDotFile = false ; HasDotTypeDotSizeDirective = false ; SupportsDebugInformation = true ;

ExceptionsType = ExceptionHandling :: DwarfCFI ;


<s> void setDwarfUsesRelocationsAcrossSections ( bool enable ) { DwarfUsesRelocationsAcrossSections = enable ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , const MCRegisterInfo & mri , bool IsLittleEndian ) : MCII ( mcii ) , MRI ( mri ) , IsLittleEndian ( IsLittleEndian ) {


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , MRI , false ) ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , MRI , true ) ;


<s> void <ISA_LIT>MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; unsigned Opcode = MI . getOpcode ( ) ; <STR_LIT> :: Writer OSE ( OS , IsLittleEndian ? <STR_LIT> : <STR_LIT> ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { uint64_t Value = getBinaryCodeForInstr ( MI , Fixups , STI ) ; OS << char ( Value >> <NUM_LIT> ) ; if ( IsLittleEndian ) OS << char ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ; else OS << char ( SwapBits ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ) ; OSE . write < uint16_t > ( <NUM_LIT> ) ; OSE . write < uint32_t > ( Value & <NUM_LIT> ) ; const MCOperand & MO = MI . getOperand ( <NUM_LIT> ) ; uint64_t Imm = MO . isImm ( ) ? MO . getImm ( ) : <NUM_LIT> ; OSE . write < uint8_t > ( <NUM_LIT> ) ; OSE . write < uint8_t > ( <NUM_LIT> ) ; OSE . write < uint16_t > ( <NUM_LIT> ) ; OSE . write < uint32_t > ( Imm >> <NUM_LIT> ) ; } else { uint64_t Value = getBinaryCodeForInstr ( MI , Fixups , STI ) ; OS << char ( Value >> <NUM_LIT> ) ;


<s> OSE . write < uint32_t > ( Imm >> <NUM_LIT> ) ; } else { uint64_t Value = getBinaryCodeForInstr ( MI , Fixups , STI ) ; OS << char ( Value >> <NUM_LIT> ) ; if ( IsLittleEndian ) OS << char ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ; else OS << char ( SwapBits ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ) ; OSE . write < uint16_t > ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ; OSE . write < uint32_t > ( Value & <NUM_LIT> ) ; }


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) return MRI . getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; assert ( MO . isExpr ( ) ) ; const MCExpr * Expr = MO . getExpr ( ) ; assert ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) ;

if ( MI . getOpcode ( ) == <STR_LIT> ) Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , FK_PCRel_4 ) ) ;


<s> const MCOperand Op1 = MI . getOperand ( <NUM_LIT> ) ; assert ( Op1 . isReg ( ) && <STR_LIT> ) ; Encoding = MRI . getEncodingValue ( Op1 . getReg ( ) ) ; Encoding <<= <NUM_LIT> ;

MCOperand Op2 = MI . getOperand ( <NUM_LIT> ) ;


<s> return ( Val & <NUM_LIT> ) << <NUM_LIT> | ( Val & <NUM_LIT> ) >> <NUM_LIT> ;


<s> LE . write < uint8_t > ( Value >> <NUM_LIT> ) ; if ( IsLittleEndian ) LE . write < uint8_t > ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ; else LE . write < uint8_t > ( SwapBits ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ) ; LE . write < uint16_t > ( <NUM_LIT> ) ; if ( IsLittleEndian ) LE . write < uint32_t > ( Value & <NUM_LIT> ) ; else BE . write < uint32_t > ( Value & <NUM_LIT> ) ; const MCOperand & MO = MI . getOperand ( <NUM_LIT> ) ; uint64_t Imm = MO . isImm ( ) ? MO . getImm ( ) : <NUM_LIT> ; LE . write < uint8_t > ( <NUM_LIT> ) ; LE . write < uint8_t > ( <NUM_LIT> ) ; LE . write < uint16_t > ( <NUM_LIT> ) ; if ( IsLittleEndian ) LE . write < uint32_t > ( Imm >> <NUM_LIT> ) ; else BE . write < uint32_t > ( Imm >> <NUM_LIT> ) ; } else { uint64_t Value = getBinaryCodeForInstr ( MI , Fixups , STI ) ; LE . write < uint8_t > ( Value >> <NUM_LIT> ) ; if ( IsLittleEndian ) { LE . write < uint8_t > ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ;

LE . write < uint16_t > ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , const MCSubtargetInfo & sti , MCContext & ctx ) : MCII ( mcii ) , STI ( sti ) , Ctx ( ctx ) {


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) {

return new <ISA_LIT>MCCodeEmitter ( MCII , STI , Ctx ) ;


<s> for ( int i = ( Size - <NUM_LIT> ) * <NUM_LIT> ; i >= <NUM_LIT> ; i -= <NUM_LIT> ) EmitByte ( ( Val >> i ) & <NUM_LIT> , CurByte , OS ) ;


<s> void EmitBEConstant ( uint64_t Val , unsigned Size , unsigned & CurByte , raw_ostream & OS ) { assert ( Size <= <NUM_LIT> && <STR_LIT> ) ; for ( int i = ( Size - <NUM_LIT> ) * <NUM_LIT> ; i >= <NUM_LIT> ; i -= <NUM_LIT> ) EmitByte ( ( Val >> i ) & <NUM_LIT> , CurByte , OS ) ;


<s> EmitByte ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) , CurByte , OS ) ; EmitLEConstant ( <NUM_LIT> , <NUM_LIT> , CurByte , OS ) ; EmitLEConstant ( Value & <NUM_LIT> , <NUM_LIT> , CurByte , OS ) ; const MCOperand & MO = MI . getOperand ( <NUM_LIT> ) ; uint64_t Imm = MO . isImm ( ) ? MO . getImm ( ) : <NUM_LIT> ; EmitByte ( <NUM_LIT> , CurByte , OS ) ; EmitByte ( <NUM_LIT> , CurByte , OS ) ; EmitLEConstant ( <NUM_LIT> , <NUM_LIT> , CurByte , OS ) ; EmitLEConstant ( Imm >> <NUM_LIT> , <NUM_LIT> , CurByte , OS ) ; } else {

uint64_t Value = getBinaryCodeForInstr ( MI , Fixups ) ;


<s> if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; assert ( MO . isExpr ( ) ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; assert ( Kind == MCExpr :: SymbolRef ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , FK_SecRel_4 ) ) ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , FK_SecRel_8 ) ) ;


<s> uint64_t encoding ; const MCOperand op1 = MI . getOperand ( <NUM_LIT> ) ; assert ( op1 . isReg ( ) && <STR_LIT> ) ; encoding = get<ISA_LIT>RegisterNumbering ( op1 . getReg ( ) ) ; encoding <<= <NUM_LIT> ; MCOperand op2 = MI . getOperand ( <NUM_LIT> ) ; assert ( op2 . isImm ( ) && <STR_LIT> ) ;

encoding |= op2 . getImm ( ) & <NUM_LIT> ;


<s> encoding = get<ISA_LIT>RegisterNumbering ( op1 . getReg ( ) ) ; encoding <<= <NUM_LIT> ; MCOperand op2 = MI . getOperand ( <NUM_LIT> ) ;

assert ( op2 . isImm ( ) && <STR_LIT> ) ;


<s> <ISA_LIT>MCCodeEmitter ( const MCRegisterInfo & mri ) : MRI ( mri ) {


<s> void EmitBEConstant ( uint64_t Val , unsigned Size , unsigned & CurByte , raw_ostream & OS ) {

assert ( Size <= <NUM_LIT> && <STR_LIT> ) ;


<s> assert ( Size <= <NUM_LIT> && <STR_LIT> ) ; for ( int i = ( Size - <NUM_LIT> ) * <NUM_LIT> ; i >= <NUM_LIT> ; i -= <NUM_LIT> ) EmitByte ( ( Val >> i ) & <NUM_LIT> , CurByte , OS ) ;


<s> void EmitByte ( unsigned char C , unsigned & CurByte , raw_ostream & OS ) { OS << ( char ) C ; ++ CurByte ;


<s> void EmitLEConstant ( uint64_t Val , unsigned Size , unsigned & CurByte , raw_ostream & OS ) { assert ( Size <= <NUM_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { EmitByte ( Val & <NUM_LIT> , CurByte , OS ) ; Val >>= <NUM_LIT> ; }