<s> unsigned CurByte = <NUM_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { uint64_t Value = getBinaryCodeForInstr ( MI , Fixups , STI ) ; EmitByte ( Value >> <NUM_LIT> , CurByte , OS ) ; EmitByte ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) , CurByte , OS ) ; EmitLEConstant ( <NUM_LIT> , <NUM_LIT> , CurByte , OS ) ; EmitLEConstant ( Value & <NUM_LIT> , <NUM_LIT> , CurByte , OS ) ; const MCOperand & MO = MI . getOperand ( <NUM_LIT> ) ; uint64_t Imm = MO . isImm ( ) ? MO . getImm ( ) : <NUM_LIT> ; EmitByte ( <NUM_LIT> , CurByte , OS ) ; EmitByte ( <NUM_LIT> , CurByte , OS ) ; EmitLEConstant ( <NUM_LIT> , <NUM_LIT> , CurByte , OS ) ; EmitLEConstant ( Imm >> <NUM_LIT> , <NUM_LIT> , CurByte , OS ) ; } else { uint64_t Value = getBinaryCodeForInstr ( MI , Fixups , STI ) ; EmitByte ( Value >> <NUM_LIT> , CurByte , OS ) ;

EmitByte ( ( Value >> <NUM_LIT> ) & <NUM_LIT> , CurByte , OS ) ;


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { uint64_t Value = getBinaryCodeForInstr ( MI , Fixups , STI ) ; EmitByte ( Value >> <NUM_LIT> , CurByte , OS ) ; EmitByte ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) , CurByte , OS ) ; EmitLEConstant ( <NUM_LIT> , <NUM_LIT> , CurByte , OS ) ; EmitLEConstant ( Value & <NUM_LIT> , <NUM_LIT> , CurByte , OS ) ; const MCOperand & MO = MI . getOperand ( <NUM_LIT> ) ; uint64_t Imm = MO . isImm ( ) ? MO . getImm ( ) : <NUM_LIT> ; EmitByte ( <NUM_LIT> , CurByte , OS ) ; EmitByte ( <NUM_LIT> , CurByte , OS ) ; EmitLEConstant ( <NUM_LIT> , <NUM_LIT> , CurByte , OS ) ; EmitLEConstant ( Imm >> <NUM_LIT> , <NUM_LIT> , CurByte , OS ) ; } else { uint64_t Value = getBinaryCodeForInstr ( MI , Fixups , STI ) ; EmitByte ( Value >> <NUM_LIT> , CurByte , OS ) ; EmitByte ( ( Value >> <NUM_LIT> ) & <NUM_LIT> , CurByte , OS ) ; EmitLEConstant ( ( Value >> <NUM_LIT> ) & <NUM_LIT> , <NUM_LIT> , CurByte , OS ) ; EmitLEConstant ( Value & <NUM_LIT> , <NUM_LIT> , CurByte , OS ) ;


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , FK_SecRel_4 ) ) ; else if ( MI . getOpcode ( ) == <STR_LIT> ) Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , FK_SecRel_8 ) ) ;

else Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , FK_PCRel_2 ) ) ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MRI ) ;


<s> EmitByte ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) , CurByte , OS ) ; EmitLEConstant ( <NUM_LIT> , <NUM_LIT> , CurByte , OS ) ; EmitLEConstant ( Value & <NUM_LIT> , <NUM_LIT> , CurByte , OS ) ; const MCOperand & MO = MI . getOperand ( <NUM_LIT> ) ; uint64_t Imm = MO . isImm ( ) ? MO . getImm ( ) : <NUM_LIT> ; EmitByte ( <NUM_LIT> , CurByte , OS ) ; EmitByte ( <NUM_LIT> , CurByte , OS ) ; EmitLEConstant ( <NUM_LIT> , <NUM_LIT> , CurByte , OS ) ; EmitLEConstant ( Imm >> <NUM_LIT> , <NUM_LIT> , CurByte , OS ) ; } else { uint64_t Value = getBinaryCodeForInstr ( MI , Fixups , STI ) ; EmitByte ( Value >> <NUM_LIT> , CurByte , OS ) ; EmitByte ( ( Value >> <NUM_LIT> ) & <NUM_LIT> , CurByte , OS ) ;

EmitLEConstant ( ( Value >> <NUM_LIT> ) & <NUM_LIT> , <NUM_LIT> , CurByte , OS ) ;


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , FK_SecRel_4 ) ) ; else if ( MI . getOpcode ( ) == <STR_LIT> ) Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , FK_SecRel_8 ) ) ; else Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , FK_PCRel_2 ) ) ; return <NUM_LIT> ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>beMCCodeEmitter ( const MCInstrInfo & MCII , MCContext & Ctx ) {

return new <ISA_LIT>MCCodeEmitter ( MCII , * Ctx . getRegisterInfo ( ) , false ) ;


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , * Ctx . getRegisterInfo ( ) , false ) ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , MCContext & Ctx ) {

return new <ISA_LIT>MCCodeEmitter ( MCII , * Ctx . getRegisterInfo ( ) , true ) ;


<s> Encoding = MRI . getEncodingValue ( Op1 . getReg ( ) ) ; Encoding <<= <NUM_LIT> ; MCOperand Op2 = MI . getOperand ( MemOpStartIndex + <NUM_LIT> ) ; assert ( Op2 . isImm ( ) && <STR_LIT> ) ; Encoding |= Op2 . getImm ( ) & <NUM_LIT> ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , const MCSubtargetInfo & sti , MCContext & ctx ) : MCII ( mcii ) , STI ( sti ) , Ctx ( ctx ) { Strtab = new std :: string ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>beMCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MRI , false ) ;


<s> return new <ISA_LIT>MCCodeEmitter ( MRI , false ) ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MRI , true ) ;


<s> return new <ISA_LIT>MCCodeEmitter ( MRI , true ) ;


<s> LE . write < uint8_t > ( <NUM_LIT> ) ; LE . write < uint8_t > ( <NUM_LIT> ) ; LE . write < uint16_t > ( <NUM_LIT> ) ; if ( IsLittleEndian ) LE . write < uint32_t > ( Imm >> <NUM_LIT> ) ; else BE . write < uint32_t > ( Imm >> <NUM_LIT> ) ; } else { uint64_t Value = getBinaryCodeForInstr ( MI , Fixups , STI ) ; LE . write < uint8_t > ( Value >> <NUM_LIT> ) ; if ( IsLittleEndian ) { LE . write < uint8_t > ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ; LE . write < uint16_t > ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ; LE . write < uint32_t > ( Value & <NUM_LIT> ) ;


<s> if ( MO . isReg ( ) ) return MRI . getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; assert ( MO . isExpr ( ) ) ; const MCExpr * Expr = MO . getExpr ( ) ; assert ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , FK_SecRel_4 ) ) ;

else if ( MI . getOpcode ( ) == <STR_LIT> ) Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , FK_SecRel_8 ) ) ;


<s> if ( MO . isReg ( ) ) return MRI . getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; assert ( MO . isExpr ( ) ) ;

const MCExpr * Expr = MO . getExpr ( ) ;


<s> Sym . push_back ( '\0' ) ; std :: string :: size_type pos = Strtab -> find ( Sym ) ; if ( pos == std :: string :: npos ) { Strtab -> append ( Sym ) ; pos = Strtab -> find ( Sym ) ;

assert ( pos != std :: string :: npos ) ;


<s> ~ <ISA_LIT>MCCodeEmitter ( ) { delete Strtab ;


<s> MCSymbol * <ISA_LIT>MCInstLower :: GetGlobalAddressSymbol ( const MachineOperand & MO ) const { return Printer . getSymbol ( MO . getGlobal ( ) ) ;

return Printer . Mang -> getSymbol ( MO . getGlobal ( ) ) ;


<s> return Printer . Mang -> getSymbol ( MO . getGlobal ( ) ) ;


<s> break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , Ctx ) ) ; break ; case MachineOperand :: MO_RegisterMask : continue ; case MachineOperand :: MO_GlobalAddress : MCOp = LowerSymbolOperand ( MO , GetGlobalAddressSymbol ( MO ) ) ; break ; }


<s> const MCExpr * Expr = MCSymbolRefExpr :: Create ( Sym , Ctx ) ;

if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) llvm_unreachable ( <STR_LIT> ) ;


<s> const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp ; switch ( MO . getType ( ) ) { default : MI -> dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) continue ; MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ;


<s> MCOp = MCOperand :: CreateReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , Ctx ) ) ; break ; case MachineOperand :: MO_RegisterMask : continue ; case MachineOperand :: MO_GlobalAddress : MCOp = LowerSymbolOperand ( MO , GetGlobalAddressSymbol ( MO ) ) ; break ; } OutMI . addOperand ( MCOp ) ; }


<s> llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) continue ; MCOp = MCOperand :: CreateReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , Ctx ) ) ; break ; case MachineOperand :: MO_RegisterMask : continue ;

case MachineOperand :: MO_GlobalAddress :


<s> MCOperand <ISA_LIT>MCInstLower :: LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const { const MCExpr * Expr = MCSymbolRefExpr :: Create ( Sym , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) llvm_unreachable ( <STR_LIT> ) ; return MCOperand :: CreateExpr ( Expr ) ;


<s> } void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ;

MCOperand LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const ;


<s> AsmPrinter & Printer ; public : <ISA_LIT>MCInstLower ( MCContext & ctx , AsmPrinter & printer ) : Ctx ( ctx ) , Printer ( printer ) { }

void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ;


<s> public : <ISA_LIT>MCInstLower ( MCContext & ctx , Mangler & mang , AsmPrinter & printer ) : Ctx ( ctx ) , Mang ( mang ) , Printer ( printer ) { }


<s> MCContext & Ctx ; Mangler & Mang ; AsmPrinter & Printer ; public : <ISA_LIT>MCInstLower ( MCContext & ctx , Mangler & mang , AsmPrinter & printer ) : Ctx ( ctx ) , Mang ( mang ) , Printer ( printer ) { } void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCOperand LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const ;

MCSymbol * GetGlobalAddressSymbol ( const MachineOperand & MO ) const ;


<s> MCSymbol * <ISA_LIT>MCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { return Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ;


<s> void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCOperand LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const ; MCSymbol * GetGlobalAddressSymbol ( const MachineOperand & MO ) const ;

MCSymbol * GetExternalSymbolSymbol ( const MachineOperand & MO ) const ;


<s> public : <ISA_LIT>MCInstLower ( MCContext & ctx , AsmPrinter & printer ) : Ctx ( ctx ) , Printer ( printer ) { } void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCOperand LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const ; MCSymbol * GetGlobalAddressSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetExternalSymbolSymbol ( const MachineOperand & MO ) const ;


<s> if ( MO . isImplicit ( ) ) continue ; MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , Ctx ) ) ; break ; case MachineOperand :: MO_RegisterMask : continue ; case MachineOperand :: MO_ExternalSymbol : MCOp = LowerSymbolOperand ( MO , GetExternalSymbolSymbol ( MO ) ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = LowerSymbolOperand ( MO , GetGlobalAddressSymbol ( MO ) ) ; break ; } OutMI . addOperand ( MCOp ) ; }


<s> MCCodeGenInfo * X = new MCCodeGenInfo ( ) ;

X -> InitMCCodeGenInfo ( RM , CM , OL ) ;


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ; return <NUM_LIT> ;


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( StringRef TT ) {

MCRegisterInfo * X = new MCRegisterInfo ( ) ;


<s> static MCStreamer * create<ISA_LIT>MCStreamer ( const Target & T , StringRef TT , MCContext & Ctx , MCAsmBackend & MAB , raw_ostream & _OS , MCCodeEmitter * _Emitter , const MCSubtargetInfo & STI , bool RelaxAll ) { return createELFStreamer ( Ctx , MAB , _OS , _Emitter , RelaxAll ) ;


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( StringRef TT , StringRef CPU , StringRef FS ) { MCSubtargetInfo * X = new MCSubtargetInfo ( ) ; Init<ISA_LIT>MCSubtargetInfo ( X , TT , CPU , FS ) ; return X ;


<s> TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , llvm :: create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>Target , create<ISA_LIT>MCStreamer ) ;

TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ;


<s> RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > X ( The<ISA_LIT>Target ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , llvm :: create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>Target , create<ISA_LIT>MCStreamer ) ;


<s> explicit <ISA_LIT>MCInstrAnalysis ( const MCInstrInfo * Info ) : MCInstrAnalysis ( Info ) {


<s> static MCInstrAnalysis * create<ISA_LIT>InstrAnalysis ( const MCInstrInfo * Info ) {

return new <ISA_LIT>MCInstrAnalysis ( Info ) ;


<s> return createELFStreamer ( Ctx , std :: move ( MAB ) , std :: move ( OW ) , std :: move ( Emitter ) , RelaxAll ) ;


<s> static MCStreamer * create<ISA_LIT>MCStreamer ( const Triple & T , MCContext & Ctx , std :: unique_ptr < MCAsmBackend > && MAB , std :: unique_ptr < MCObjectWriter > && OW , std :: unique_ptr < MCCodeEmitter > && Emitter , bool RelaxAll ) {

return createELFStreamer ( Ctx , std :: move ( MAB ) , std :: move ( OW ) , std :: move ( Emitter ) , RelaxAll ) ;


<s> if ( isConditionalBranch ( Inst ) ) { Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; } else if ( isUnconditionalBranch ( Inst ) ) Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; else return false ;


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { int16_t Imm ; if ( isConditionalBranch ( Inst ) ) { Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; } else if ( isUnconditionalBranch ( Inst ) ) Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; else return false ; Target = Addr + Size + Imm * Size ;


<s> TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>beTarget ( ) , create<ISA_LIT>beMCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>leTarget ( ) , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>beTarget ( ) , create<ISA_LIT>beAsmBackend ) ; if ( sys :: IsLittleEndianHost ) { TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>AsmBackend ) ;


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT , const MCTargetOptions & Options ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X ;


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , CPU , FS ) ;


<s> TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>leTarget ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>beTarget ( ) , create<ISA_LIT>beMCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>leTarget ( ) , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>beTarget ( ) , create<ISA_LIT>beAsmBackend ) ; if ( sys :: IsLittleEndianHost ) { TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>AsmBackend ) ; } else { TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>beMCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>beAsmBackend ) ; }


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; X -> initMCCodeGenInfo ( RM , CM , OL ) ; return X ;


<s> MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; X -> initMCCodeGenInfo ( RM , CM , OL ) ; return X ;


<s> TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterELFStreamer ( * T , create<ISA_LIT>MCStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; } TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>leTarget , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>beTarget , create<ISA_LIT>beMCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>leTarget , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>beTarget , create<ISA_LIT>beAsmBackend ) ; if ( sys :: IsLittleEndianHost ) { TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ; } else { TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>beMCCodeEmitter ) ;

TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>beAsmBackend ) ;


<s> TargetRegistry :: RegisterMCCodeGenInfo ( * T , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterELFStreamer ( * T , create<ISA_LIT>MCStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ;


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > X ( The<ISA_LIT>Target ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , llvm :: create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterELFStreamer ( The<ISA_LIT>Target , create<ISA_LIT>MCStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ;


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ; return nullptr ;


<s> TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>leTarget ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>beTarget ( ) , create<ISA_LIT>beMCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>leTarget ( ) , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>beTarget ( ) , create<ISA_LIT>beAsmBackend ) ; if ( sys :: IsLittleEndianHost ) { TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ;

TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>AsmBackend ) ;


<s> TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; } TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>leTarget ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>beTarget ( ) , create<ISA_LIT>beMCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>leTarget ( ) , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>beTarget ( ) , create<ISA_LIT>beAsmBackend ) ; if ( sys :: IsLittleEndianHost ) { TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X ;


<s> return createELFStreamer ( Ctx , <NUM_LIT> , MAB , _OS , _Emitter , RelaxAll , NoExecStack ) ; return createELFStreamer ( Ctx , MAB , _OS , _Emitter , RelaxAll , NoExecStack ) ;


<s> static MCStreamer * create<ISA_LIT>MCStreamer ( const Target & T , StringRef TT , MCContext & Ctx , MCAsmBackend & MAB , raw_ostream & _OS , MCCodeEmitter * _Emitter , bool RelaxAll , bool NoExecStack ) { return createELFStreamer ( Ctx , <NUM_LIT> , MAB , _OS , _Emitter , RelaxAll , NoExecStack ) ;

return createELFStreamer ( Ctx , MAB , _OS , _Emitter , RelaxAll , NoExecStack ) ;


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( const Triple & TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; X -> initMCCodeGenInfo ( RM , CM , OL ) ;


<s> static MCStreamer * create<ISA_LIT>MCStreamer ( const Triple & T , MCContext & Ctx , MCAsmBackend & MAB , raw_ostream & OS , MCCodeEmitter * Emitter , bool RelaxAll ) { return createELFStreamer ( Ctx , MAB , OS , Emitter , RelaxAll ) ;


<s> return createELFStreamer ( Ctx , std :: move ( MAB ) , OS , std :: move ( Emitter ) , RelaxAll ) ;


<s> static MCStreamer * create<ISA_LIT>MCStreamer ( const Triple & T , MCContext & Ctx , std :: unique_ptr < MCAsmBackend > && MAB , raw_pwrite_stream & OS , std :: unique_ptr < MCCodeEmitter > && Emitter , bool RelaxAll ) {

return createELFStreamer ( Ctx , std :: move ( MAB ) , OS , std :: move ( Emitter ) , RelaxAll ) ;


<s> MCInstrInfo * X = new MCInstrInfo ( ) ;


<s> return createELFStreamer ( Ctx , MAB , OS , Emitter , RelaxAll ) ;


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) {

return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , FS ) ;


<s> TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>beTarget , create<ISA_LIT>beMCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>leTarget , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>beTarget , create<ISA_LIT>beAsmBackend ) ; if ( sys :: IsLittleEndianHost ) { TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ; } else { TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>beMCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>beAsmBackend ) ;


<s> TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterELFStreamer ( * T , create<ISA_LIT>MCStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; } TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>leTarget , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>beTarget , create<ISA_LIT>beMCCodeEmitter ) ;

TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>leTarget , create<ISA_LIT>AsmBackend ) ;


<s> const DebugLoc & DL = MI . getDebugLoc ( ) ; if ( DL != Empty ) report_fatal_error ( <STR_LIT> + std :: to_string ( DL . getLine ( ) ) + <STR_LIT> , false ) ; else report_fatal_error ( <STR_LIT> , false ) ; } } }


<s> if ( RegIsGPR64 ) return true ; GPR32LiveDefs . push_back ( MO . getReg ( ) ) ; continue ; } if ( RegIsGPR64 ) GPR64DeadDefs . push_back ( MO . getReg ( ) ) ; } if ( GPR32LiveDefs . empty ( ) ) return false ; if ( GPR64DeadDefs . empty ( ) ) return true ; std :: vector < unsigned > :: iterator search_begin = GPR64DeadDefs . begin ( ) ; std :: vector < unsigned > :: iterator search_end = GPR64DeadDefs . end ( ) ;

for ( auto I : GPR32LiveDefs ) for ( MCSuperRegIterator SR ( I , TRI ) ; SR . isValid ( ) ; ++ SR ) if ( std :: find ( search_begin , search_end , * SR ) == search_end ) return true ;


<s> std :: vector < unsigned > :: iterator search_begin = GPR64DeadDefs . begin ( ) ; std :: vector < unsigned > :: iterator search_end = GPR64DeadDefs . end ( ) ; for ( auto I : GPR32LiveDefs ) for ( MCSuperRegIterator SR ( I , TRI ) ; SR . isValid ( ) ; ++ SR ) if ( std :: find ( search_begin , search_end , * SR ) == search_end ) return true ;


<s> if ( ! MO . isReg ( ) || MO . isUse ( ) ) continue ; RegIsGPR64 = GPR64RegClass -> contains ( MO . getReg ( ) ) ; if ( ! MO . isDead ( ) ) { if ( RegIsGPR64 ) return true ; GPR32LiveDefs . push_back ( MO . getReg ( ) ) ; continue ; } if ( RegIsGPR64 ) GPR64DeadDefs . push_back ( MO . getReg ( ) ) ; } if ( GPR32LiveDefs . empty ( ) ) return false ; if ( GPR64DeadDefs . empty ( ) ) return true ; for ( auto I : GPR32LiveDefs ) for ( MCSuperRegIterator SR ( I , TRI ) ; SR . isValid ( ) ; ++ SR ) if ( ! llvm :: is_contained ( GPR64DeadDefs , * SR ) ) return true ; return false ;


<s> if ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) continue ; LLVM_DEBUG ( MI . dump ( ) ) ; if ( hasLiveDefs ( MI , TRI ) ) { DebugLoc Empty ; const DebugLoc & DL = MI . getDebugLoc ( ) ; if ( DL != Empty ) report_fatal_error ( Twine ( <STR_LIT> ) + std :: to_string ( DL . getLine ( ) ) + <STR_LIT> , false ) ; else report_fatal_error ( <STR_LIT> , false ) ; } } } MachineInstr * ToErase = nullptr ; bool Changed = false ; const <ISA_LIT>InstrInfo * TII = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; for ( MachineBasicBlock & MBB : * MF ) { for ( MachineInstr & MI : MBB ) { if ( ToErase ) { ToErase -> eraseFromParent ( ) ; ToErase = nullptr ; } if ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) continue ; if ( hasLiveDefs ( MI , TRI ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ) ; unsigned newOpcode ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : newOpcode = <STR_LIT> ; break ;


<s> if ( ! skipFunction ( MF . getFunction ( ) ) ) { initialize ( MF ) ; return processAtomicInsts ( ) ; }


<s> initialize ( MF ) ; return processAtomicInsts ( ) ; } return false ;


<s> const <ISA_LIT>InstrInfo * TII = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; for ( MachineBasicBlock & MBB : * MF ) { for ( MachineInstr & MI : MBB ) { if ( ToErase ) { ToErase -> eraseFromParent ( ) ; ToErase = nullptr ; } if ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) continue ; if ( hasLiveDefs ( MI , TRI ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ) ; unsigned newOpcode ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : newOpcode = <STR_LIT> ; break ;


<s> if ( ! MI . allDefsAreDead ( ) ) { DebugLoc Empty ; const DebugLoc & DL = MI . getDebugLoc ( ) ; if ( DL != Empty ) report_fatal_error ( <STR_LIT> + std :: to_string ( DL . getLine ( ) ) + <STR_LIT> , false ) ; else report_fatal_error ( <STR_LIT> , false ) ; }


<s> for ( MachineBasicBlock & MBB : * MF ) { for ( MachineInstr & MI : MBB ) { if ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) continue ; LLVM_DEBUG ( MI . dump ( ) ) ; if ( ! MI . allDefsAreDead ( ) ) { DebugLoc Empty ; const DebugLoc & DL = MI . getDebugLoc ( ) ; if ( DL != Empty ) report_fatal_error ( <STR_LIT> + std :: to_string ( DL . getLine ( ) ) + <STR_LIT> , false ) ;

else report_fatal_error ( <STR_LIT> , false ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>MIPreEmitCheckingPass ( ) {

return new <ISA_LIT>MIPreEmitChecking ( ) ;


<s> MF = & MFParm ; TRI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> void <ISA_LIT>MIPreEmitChecking :: initialize ( MachineFunction & MFParm ) {


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( ! skipFunction ( MF . getFunction ( ) ) ) { initialize ( MF ) ; checkingIllegalXADD ( ) ; } return false ;


<s> unsigned dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned dst_sub = TRI -> getSubReg ( dst , <STR_LIT> ) ; unsigned src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> ToErase = nullptr ; } if ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ShfReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * SllMI = MRI -> getVRegDef ( ShfReg ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI . dump ( ) ) ; if ( ! SllMI || SllMI -> isPHI ( ) || SllMI -> getOpcode ( ) != <STR_LIT> || SllMI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( SllMI -> dump ( ) ) ; MachineInstr * MovMI = MRI -> getVRegDef ( SllMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( ! MovMI || MovMI -> isPHI ( ) || MovMI -> getOpcode ( ) != <STR_LIT> ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MovMI -> dump ( ) ) ; unsigned SubReg = MovMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! isMovFrom32Def ( MovMI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( SubReg ) . addImm ( <STR_LIT> ) ; SllMI -> eraseFromParent ( ) ; MovMI -> eraseFromParent ( ) ; ToErase = & MI ; ZExtElemNum ++ ; Eliminated = true ; } } } return Eliminated ;


<s> if ( ToErase ) { ToErase -> eraseFromParent ( ) ; ToErase = nullptr ; } if ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ShfReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * SllMI = MRI -> getVRegDef ( ShfReg ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI . dump ( ) ) ; if ( ! SllMI || SllMI -> isPHI ( ) || SllMI -> getOpcode ( ) != <STR_LIT> || SllMI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( SllMI -> dump ( ) ) ; MachineInstr * MovMI = MRI -> getVRegDef ( SllMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( ! MovMI || MovMI -> isPHI ( ) || MovMI -> getOpcode ( ) != <STR_LIT> ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MovMI -> dump ( ) ) ; unsigned SubReg = MovMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> MF = & MFParm ; TRI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> ToErase = nullptr ; } unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> ) { Register dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( dst != src ) continue ; ToErase = & MI ; RedundantMovElemNum ++ ; Eliminated = true ;


<s> if ( ToErase ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( ToErase -> dump ( ) ) ; ToErase -> eraseFromParent ( ) ; ToErase = nullptr ; } unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> ) { Register dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( dst != src ) continue ; ToErase = & MI ; RedundantMovElemNum ++ ; Eliminated = true ; }


<s> bool <ISA_LIT>MIPeepholeTruncElim :: eliminateTruncSeq ( ) { MachineInstr * ToErase = nullptr ; bool Eliminated = false ; for ( MachineBasicBlock & MBB : * MF ) { for ( MachineInstr & MI : MBB ) { MachineInstr * MI2 = nullptr ; Register DstReg , SrcReg ; MachineInstr * DefMI ; int TruncSize = - <NUM_LIT> ; if ( ToErase ) { ToErase -> eraseFromParent ( ) ; ToErase = nullptr ; } if ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MRI -> hasOneNonDBGUse ( SrcReg ) ) continue ; MI2 = MRI -> getVRegDef ( SrcReg ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MI2 || MI2 -> getOpcode ( ) != <STR_LIT> || MI2 -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) continue ; SrcReg = MI2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; DefMI = MRI -> getVRegDef ( SrcReg ) ; if ( DefMI ) TruncSize = <NUM_LIT> ; } else if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DefMI = MRI -> getVRegDef ( SrcReg ) ; if ( ! DefMI ) continue ; int64_t imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( imm == <NUM_LIT> ) TruncSize = <NUM_LIT> ; else if ( imm == <NUM_LIT> ) TruncSize = <NUM_LIT> ; } if ( TruncSize == - <NUM_LIT> ) continue ;


<s> bool Eliminated = false ; for ( MachineBasicBlock & MBB : * MF ) { for ( MachineInstr & MI : MBB ) { if ( ToErase ) { ToErase -> eraseFromParent ( ) ; ToErase = nullptr ; } if ( MI . getOpcode ( ) != <STR_LIT> ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI . dump ( ) ) ; if ( ! isMovFrom32Def ( & MI ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Register dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;

Register src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> Register src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , dst ) . addImm ( <NUM_LIT> ) . addReg ( src ) . addImm ( <STR_LIT> ) ; ToErase = & MI ; Eliminated = true ; } }


<s> if ( ! MovMI || MovMI -> isPHI ( ) || MovMI -> getOpcode ( ) != <STR_LIT> ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MovMI -> dump ( ) ) ; Register SubReg = MovMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! isMovFrom32Def ( MovMI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( SubReg ) . addImm ( <STR_LIT> ) ; SllMI -> eraseFromParent ( ) ; MovMI -> eraseFromParent ( ) ; ToErase = & MI ; ZExtElemNum ++ ; Eliminated = true ; } } }


<s> LLVM_DEBUG ( MI . dump ( ) ) ; if ( ! SllMI || SllMI -> isPHI ( ) || SllMI -> getOpcode ( ) != <STR_LIT> || SllMI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( SllMI -> dump ( ) ) ; MachineInstr * MovMI = MRI -> getVRegDef ( SllMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( ! MovMI || MovMI -> isPHI ( ) || MovMI -> getOpcode ( ) != <STR_LIT> ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MovMI -> dump ( ) ) ; Register SubReg = MovMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! isMovFrom32Def ( MovMI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( SubReg ) . addImm ( <STR_LIT> ) ; SllMI -> eraseFromParent ( ) ;


<s> initialize ( MF ) ; bool ZExtSeqExist , ZExtExist ;


<s> if ( skipFunction ( MF . getFunction ( ) ) ) return false ; initialize ( MF ) ; bool ZExtSeqExist , ZExtExist ;


<s> bool <ISA_LIT>MIPeephole :: isMovFrom32Def ( MachineInstr * MovMI ) { MachineInstr * DefInsn = MRI -> getVRegDef ( MovMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( DefInsn -> dump ( ) ) ; if ( ! DefInsn ) return false ; if ( DefInsn -> isPHI ( ) ) { for ( unsigned i = <NUM_LIT> , e = DefInsn -> getNumOperands ( ) ; i < e ; i += <NUM_LIT> ) { MachineOperand & opnd = DefInsn -> getOperand ( i ) ; if ( ! opnd . isReg ( ) ) return false ; MachineInstr * PhiDef = MRI -> getVRegDef ( opnd . getReg ( ) ) ; if ( ! PhiDef || PhiDef -> isPHI ( ) || PhiDef -> getOpcode ( ) == <STR_LIT> ) return false ; } } if ( DefInsn -> getOpcode ( ) == <STR_LIT> ) {

MachineOperand & opnd = DefInsn -> getOperand ( <NUM_LIT> ) ;


<s> if ( ! opnd . isReg ( ) ) return false ; MachineInstr * PhiDef = MRI -> getVRegDef ( opnd . getReg ( ) ) ; if ( ! PhiDef || PhiDef -> isPHI ( ) || PhiDef -> getOpcode ( ) == <STR_LIT> ) return false ; } } if ( DefInsn -> getOpcode ( ) == <STR_LIT> ) {


<s> LLVM_DEBUG ( ToErase -> dump ( ) ) ; ToErase -> eraseFromParent ( ) ; ToErase = nullptr ; } unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> ) {

Register dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( ToErase -> dump ( ) ) ; ToErase -> eraseFromParent ( ) ; ToErase = nullptr ; } unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> ) { Register dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( dst != src ) continue ; ToErase = & MI ; RedundantMovElemNum ++ ;


<s> bool <ISA_LIT>MIPeephole :: eliminateZExt ( void ) { MachineInstr * ToErase = nullptr ; bool Eliminated = false ; for ( MachineBasicBlock & MBB : * MF ) { for ( MachineInstr & MI : MBB ) { if ( ToErase ) { ToErase -> eraseFromParent ( ) ; ToErase = nullptr ; } if ( MI . getOpcode ( ) != <STR_LIT> ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI . dump ( ) ) ; if ( ! isMovFrom32Def ( & MI ) ) continue ;


<s> Register dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register dst_sub = TRI -> getSubReg ( dst , <STR_LIT> ) ; Register src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( dst_sub != src ) continue ; ToErase = & MI ; RedundantMovElemNum ++ ; Eliminated = true ; } }


<s> unsigned dst_sub = TRI -> getSubReg ( dst , <STR_LIT> ) ; unsigned src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( dst_sub != src ) continue ; ToErase = & MI ; RedundantMovElemNum ++ ; Eliminated = true ; }


<s> if ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ShfReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * SllMI = MRI -> getVRegDef ( ShfReg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI . dump ( ) ) ; if ( ! SllMI || SllMI -> isPHI ( ) || SllMI -> getOpcode ( ) != <STR_LIT> || SllMI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( SllMI -> dump ( ) ) ; MachineInstr * MovMI = MRI -> getVRegDef ( SllMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( ! MovMI || MovMI -> isPHI ( ) || MovMI -> getOpcode ( ) != <STR_LIT> ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MovMI -> dump ( ) ) ; unsigned SubReg = MovMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! isMovFrom32Def ( MovMI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( SubReg ) . addImm ( <STR_LIT> ) ; SllMI -> eraseFromParent ( ) ; MovMI -> eraseFromParent ( ) ; ToErase = & MI ; ZExtElemNum ++ ; Eliminated = true ; }


<s> if ( ! SllMI || SllMI -> isPHI ( ) || SllMI -> getOpcode ( ) != <STR_LIT> || SllMI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( SllMI -> dump ( ) ) ; MachineInstr * MovMI = MRI -> getVRegDef ( SllMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( ! MovMI || MovMI -> isPHI ( ) || MovMI -> getOpcode ( ) != <STR_LIT> ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MovMI -> dump ( ) ) ; unsigned SubReg = MovMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! isMovFrom32Def ( MovMI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( SubReg ) . addImm ( <STR_LIT> ) ; SllMI -> eraseFromParent ( ) ;


<s> MF = & MFParm ; MRI = & MF -> getRegInfo ( ) ;

TII = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ;


<s> LLVM_DEBUG ( DefInsn -> dump ( ) ) ; if ( ! DefInsn ) return false ; if ( DefInsn -> isPHI ( ) ) { for ( unsigned i = <NUM_LIT> , e = DefInsn -> getNumOperands ( ) ; i < e ; i += <NUM_LIT> ) { MachineOperand & opnd = DefInsn -> getOperand ( i ) ; if ( ! opnd . isReg ( ) ) return false ; MachineInstr * PhiDef = MRI -> getVRegDef ( opnd . getReg ( ) ) ; if ( ! PhiDef || PhiDef -> isPHI ( ) || PhiDef -> getOpcode ( ) == <STR_LIT> ) return false ; }


<s> DefMI = MRI -> getVRegDef ( SrcReg ) ; if ( DefMI ) TruncSize = <NUM_LIT> ; } else if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DefMI = MRI -> getVRegDef ( SrcReg ) ; if ( ! DefMI ) continue ; int64_t imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( imm == <NUM_LIT> ) TruncSize = <NUM_LIT> ; else if ( imm == <NUM_LIT> ) TruncSize = <NUM_LIT> ; } if ( TruncSize == - <NUM_LIT> ) continue ; if ( DefMI -> isPHI ( ) ) { bool CheckFail = false ; for ( unsigned i = <NUM_LIT> , e = DefMI -> getNumOperands ( ) ; i < e ; i += <NUM_LIT> ) { MachineOperand & opnd = DefMI -> getOperand ( i ) ; if ( ! opnd . isReg ( ) ) { CheckFail = true ; break ; } MachineInstr * PhiDef = MRI -> getVRegDef ( opnd . getReg ( ) ) ; if ( ! PhiDef || PhiDef -> isPHI ( ) || ! TruncSizeCompatible ( TruncSize , PhiDef -> getOpcode ( ) ) ) { CheckFail = true ; break ;


<s> } if ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MRI -> hasOneNonDBGUse ( SrcReg ) ) continue ; MI2 = MRI -> getVRegDef ( SrcReg ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MI2 || MI2 -> getOpcode ( ) != <STR_LIT> || MI2 -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) continue ; SrcReg = MI2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; DefMI = MRI -> getVRegDef ( SrcReg ) ; if ( DefMI ) TruncSize = <NUM_LIT> ; } else if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DefMI = MRI -> getVRegDef ( SrcReg ) ; if ( ! DefMI ) continue ; int64_t imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( imm == <NUM_LIT> ) TruncSize = <NUM_LIT> ; else if ( imm == <NUM_LIT> ) TruncSize = <NUM_LIT> ; } if ( TruncSize == - <NUM_LIT> ) continue ;


<s> return new <ISA_LIT>MIPeephole ( ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>MIPeepholeTruncElimPass ( ) {

return new <ISA_LIT>MIPeepholeTruncElim ( ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>MIPreEmitPeepholePass ( ) {

return new <ISA_LIT>MIPreEmitPeephole ( ) ;


<s> for ( MachineBasicBlock & MBB : * MF ) { for ( MachineInstr & MI : MBB ) { if ( ToErase ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( ToErase -> dump ( ) ) ; ToErase -> eraseFromParent ( ) ; ToErase = nullptr ; } unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { Register dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Opcode == <STR_LIT> ) dst = TRI -> getSubReg ( dst , <STR_LIT> ) ; if ( dst != src ) continue ; ToErase = & MI ; RedundantMovElemNum ++ ; Eliminated = true ;


<s> SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DefMI = MRI -> getVRegDef ( SrcReg ) ; if ( ! DefMI ) continue ; int64_t imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( imm == <NUM_LIT> ) TruncSize = <NUM_LIT> ; else if ( imm == <NUM_LIT> ) TruncSize = <NUM_LIT> ; } if ( TruncSize == - <NUM_LIT> ) continue ; if ( DefMI -> isPHI ( ) ) { bool CheckFail = false ; for ( unsigned i = <NUM_LIT> , e = DefMI -> getNumOperands ( ) ; i < e ; i += <NUM_LIT> ) { MachineOperand & opnd = DefMI -> getOperand ( i ) ; if ( ! opnd . isReg ( ) ) { CheckFail = true ; break ; } MachineInstr * PhiDef = MRI -> getVRegDef ( opnd . getReg ( ) ) ;

if ( ! PhiDef || PhiDef -> isPHI ( ) || ! TruncSizeCompatible ( TruncSize , PhiDef -> getOpcode ( ) ) ) {


<s> LLVM_DEBUG ( SllMI -> dump ( ) ) ; MachineInstr * MovMI = MRI -> getVRegDef ( SllMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( ! MovMI || MovMI -> isPHI ( ) || MovMI -> getOpcode ( ) != <STR_LIT> ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MovMI -> dump ( ) ) ; Register SubReg = MovMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! isMovFrom32Def ( MovMI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( SubReg ) . addImm ( <STR_LIT> ) ; SllMI -> eraseFromParent ( ) ; MovMI -> eraseFromParent ( ) ; ToErase = & MI ; ZExtElemNum ++ ;


<s> MRI = & MF -> getRegInfo ( ) ; TII = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> MRI = & MF -> getRegInfo ( ) ; TII = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ;


<s> if ( ! Register :: isVirtualRegister ( Reg ) ) return false ; if ( MRI -> getRegClass ( Reg ) == & <STR_LIT> ) return false ; MachineInstr * DefInsn = MRI -> getVRegDef ( Reg ) ;

if ( ! isInsnFrom32Def ( DefInsn ) ) return false ;


<s> MachineOperand & opnd = CopyMI -> getOperand ( <NUM_LIT> ) ; if ( ! opnd . isReg ( ) ) return false ; Register Reg = opnd . getReg ( ) ; if ( ! Register :: isVirtualRegister ( Reg ) ) return false ; if ( MRI -> getRegClass ( Reg ) == & <STR_LIT> ) return false ; MachineInstr * DefInsn = MRI -> getVRegDef ( Reg ) ;


<s> PhiInsns . insert ( DefInsn ) ; if ( ! isPhiFrom32Def ( DefInsn ) ) return false ; } else if ( DefInsn -> getOpcode ( ) == <STR_LIT> ) { if ( ! isCopyFrom32Def ( DefInsn ) ) return false ; } return true ;


<s> if ( ! isPhiFrom32Def ( DefInsn ) ) return false ; } else if ( DefInsn -> getOpcode ( ) == <STR_LIT> ) { if ( ! isCopyFrom32Def ( DefInsn ) ) return false ; }


<s> MachineInstr * DefInsn = MRI -> getVRegDef ( MovMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( DefInsn -> dump ( ) ) ; PhiInsns . clear ( ) ; if ( ! isInsnFrom32Def ( DefInsn ) ) return false ;


<s> if ( ! isInsnFrom32Def ( DefInsn ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ;


<s> if ( ! PhiDef ) return false ; if ( PhiDef -> isPHI ( ) ) { if ( PhiInsns . find ( PhiDef ) != PhiInsns . end ( ) ) return false ; PhiInsns . insert ( PhiDef ) ; if ( ! isPhiFrom32Def ( PhiDef ) ) return false ; }

if ( PhiDef -> getOpcode ( ) == <STR_LIT> && ! isCopyFrom32Def ( PhiDef ) ) return false ;


<s> if ( ! opnd . isReg ( ) ) return false ; MachineInstr * PhiDef = MRI -> getVRegDef ( opnd . getReg ( ) ) ; if ( ! PhiDef ) return false ; if ( PhiDef -> isPHI ( ) ) {

if ( PhiInsns . find ( PhiDef ) != PhiInsns . end ( ) ) return false ;


<s> if ( skipFunction ( MF . getFunction ( ) ) ) return false ; initialize ( MF ) ; return eliminateTruncSeq ( ) ;


<s> if ( TruncSize == <NUM_LIT> ) return opcode == <STR_LIT> || opcode == <STR_LIT> ;


<s> const MachineInstr * Inst = RelocOp -> getParent ( ) ; const MachineOperand * Op1 = & Inst -> getOperand ( <NUM_LIT> ) ; const MachineOperand * Op2 = & Inst -> getOperand ( <NUM_LIT> ) ; const MachineOperand * BaseOp = ( RelocOp == Op1 ) ? Op2 : Op1 ; const MachineOperand Op0 = Inst -> getOperand ( <NUM_LIT> ) ; auto Begin = MRI -> use_begin ( Op0 . getReg ( ) ) , End = MRI -> use_end ( ) ; decltype ( End ) NextI ; for ( auto I = Begin ; I != End ; I = NextI ) { NextI = std :: next ( I ) ; if ( ! MRI -> getUniqueVRegDef ( I -> getReg ( ) ) ) continue ; MachineInstr * DefInst = I -> getParent ( ) ; unsigned Opcode = DefInst -> getOpcode ( ) ; unsigned COREOp ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) COREOp = <STR_LIT> ; else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) COREOp = <STR_LIT> ; else continue ; const MachineOperand & ImmOp = DefInst -> getOperand ( <NUM_LIT> ) ; if ( ! ImmOp . isImm ( ) || ImmOp . getImm ( ) != <NUM_LIT> ) continue ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { const MachineOperand & Opnd = DefInst -> getOperand ( <NUM_LIT> ) ; if ( Opnd . isReg ( ) && Opnd . getReg ( ) == I -> getReg ( ) ) continue ; } BuildMI ( * DefInst -> getParent ( ) , * DefInst , DefInst -> getDebugLoc ( ) , TII -> get ( COREOp ) ) . add ( DefInst -> getOperand ( <NUM_LIT> ) ) . addImm ( Opcode ) . add ( * BaseOp ) . addGlobalAddress ( GVal ) ;


<s> const MachineOperand * Op1 = & Inst -> getOperand ( <NUM_LIT> ) ; const MachineOperand * Op2 = & Inst -> getOperand ( <NUM_LIT> ) ; const MachineOperand * BaseOp = ( RelocOp == Op1 ) ? Op2 : Op1 ; const MachineOperand Op0 = Inst -> getOperand ( <NUM_LIT> ) ; auto Begin = MRI -> use_begin ( Op0 . getReg ( ) ) , End = MRI -> use_end ( ) ; decltype ( End ) NextI ; for ( auto I = Begin ; I != End ; I = NextI ) { NextI = std :: next ( I ) ; if ( ! MRI -> getUniqueVRegDef ( I -> getReg ( ) ) ) continue ; MachineInstr * DefInst = I -> getParent ( ) ;

unsigned Opcode = DefInst -> getOpcode ( ) ;


<s> const MachineOperand & MO = DefInst -> getOperand ( <NUM_LIT> ) ; if ( MO . isGlobal ( ) ) { const GlobalValue * GVal = MO . getGlobal ( ) ; auto * GVar = dyn_cast < GlobalVariable > ( GVal ) ; if ( GVar ) { if ( GVar -> hasAttribute ( <STR_LIT> ) ) { assert ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ; IsCandidate = true ; } } } } if ( ! IsCandidate ) continue ; auto Begin = MRI -> use_begin ( DstReg ) , End = MRI -> use_end ( ) ; decltype ( End ) NextI ; for ( auto I = Begin ; I != End ; I = NextI ) { NextI = std :: next ( I ) ; I -> setReg ( SrcReg ) ; }


<s> MachineInstr * DefInst = MRI -> getUniqueVRegDef ( SrcReg ) ; if ( ! DefInst ) continue ; bool IsCandidate = false ; if ( DefInst -> getOpcode ( ) == <STR_LIT> ) { const MachineOperand & MO = DefInst -> getOperand ( <NUM_LIT> ) ; if ( MO . isGlobal ( ) ) { const GlobalValue * GVal = MO . getGlobal ( ) ; auto * GVar = dyn_cast < GlobalVariable > ( GVal ) ; if ( GVar ) { if ( GVar -> hasAttribute ( <STR_LIT> ) ) { assert ( ImmVal == <NUM_LIT> ) ; IsCandidate = true ; } else if ( ! GVar -> hasInitializer ( ) && GVar -> hasExternalLinkage ( ) && GVar -> getSection ( ) == <STR_LIT> ) { if ( ImmVal == <NUM_LIT> ) IsCandidate = true ; else errs ( ) << <STR_LIT> << GVar -> getName ( ) << <STR_LIT> << ImmVal << <STR_LIT> ; } } } } if ( ! IsCandidate ) continue ; auto Begin = MRI -> use_begin ( DstReg ) , End = MRI -> use_end ( ) ; decltype ( End ) NextI ; for ( auto I = Begin ; I != End ; I = NextI ) {


<s> bool <ISA_LIT>MISimplifyPatchable :: removeLD ( ) { MachineRegisterInfo * MRI = & MF -> getRegInfo ( ) ; MachineInstr * ToErase = nullptr ; bool Changed = false ; for ( MachineBasicBlock & MBB : * MF ) { for ( MachineInstr & MI : MBB ) { if ( ToErase ) { ToErase -> eraseFromParent ( ) ; ToErase = nullptr ; } if ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) continue ; if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) continue ; if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) || MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) continue ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DefInst = MRI -> getUniqueVRegDef ( SrcReg ) ; if ( ! DefInst ) continue ; bool IsCandidate = false ; if ( DefInst -> getOpcode ( ) == <STR_LIT> ) { const MachineOperand & MO = DefInst -> getOperand ( <NUM_LIT> ) ; if ( MO . isGlobal ( ) ) { const GlobalValue * GVal = MO . getGlobal ( ) ; auto * GVar = dyn_cast < GlobalVariable > ( GVal ) ; if ( GVar ) { if ( GVar -> hasAttribute ( <STR_LIT> ) ) { assert ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ; IsCandidate = true ; } } } } if ( ! IsCandidate ) continue ; if ( MRI -> getRegClass ( DstReg ) == & <STR_LIT> ) { BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , <NUM_LIT> , <STR_LIT> ) ; } else { auto Begin = MRI -> use_begin ( DstReg ) , End = MRI -> use_end ( ) ; decltype ( End ) NextI ; for ( auto I = Begin ; I != End ; I = NextI ) { NextI = std :: next ( I ) ; I -> setReg ( SrcReg ) ; }


<s> const MachineOperand & MO = DefInst -> getOperand ( <NUM_LIT> ) ; if ( MO . isGlobal ( ) ) { const GlobalValue * GVal = MO . getGlobal ( ) ; auto * GVar = dyn_cast < GlobalVariable > ( GVal ) ; if ( GVar ) { if ( GVar -> hasAttribute ( <STR_LIT> ) ) { assert ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ; IsCandidate = true ; } } } } if ( ! IsCandidate ) continue ; if ( MRI -> getRegClass ( DstReg ) == & <STR_LIT> ) { BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , <NUM_LIT> , <STR_LIT> ) ; } else { auto Begin = MRI -> use_begin ( DstReg ) , End = MRI -> use_end ( ) ; decltype ( End ) NextI ; for ( auto I = Begin ; I != End ; I = NextI ) { NextI = std :: next ( I ) ; I -> setReg ( SrcReg ) ; } } ToErase = & MI ; Changed = true ;


<s> else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) COREOp = <STR_LIT> ; else continue ; const MachineOperand & ImmOp = DefInst -> getOperand ( <NUM_LIT> ) ; if ( ! ImmOp . isImm ( ) || ImmOp . getImm ( ) != <NUM_LIT> ) continue ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { const MachineOperand & Opnd = DefInst -> getOperand ( <NUM_LIT> ) ; if ( Opnd . isReg ( ) && Opnd . getReg ( ) == MO . getReg ( ) ) continue ; }

BuildMI ( * DefInst -> getParent ( ) , * DefInst , DefInst -> getDebugLoc ( ) , TII -> get ( COREOp ) ) . add ( DefInst -> getOperand ( <NUM_LIT> ) ) . addImm ( Opcode ) . add ( * BaseOp ) . addGlobalAddress ( GVal ) ;


<s> void <ISA_LIT>MISimplifyPatchable :: processDstReg ( MachineRegisterInfo * MRI , Register & DstReg , Register & SrcReg , const GlobalValue * GVal , bool doSrcRegProp , bool IsAma ) { auto Begin = MRI -> use_begin ( DstReg ) , End = MRI -> use_end ( ) ; decltype ( End ) NextI ; for ( auto I = Begin ; I != End ; I = NextI ) {


<s> if ( ToErase ) { ToErase -> eraseFromParent ( ) ; ToErase = nullptr ; } if ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) continue ; if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) continue ; if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) || MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) continue ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DefInst = MRI -> getUniqueVRegDef ( SrcReg ) ; if ( ! DefInst ) continue ; if ( DefInst -> getOpcode ( ) != <STR_LIT> ) continue ;

const MachineOperand & MO = DefInst -> getOperand ( <NUM_LIT> ) ;


<s> if ( ! DefInst ) continue ; if ( DefInst -> getOpcode ( ) != <STR_LIT> ) continue ; const MachineOperand & MO = DefInst -> getOperand ( <NUM_LIT> ) ; if ( ! MO . isGlobal ( ) ) continue ; const GlobalValue * GVal = MO . getGlobal ( ) ; auto * GVar = dyn_cast < GlobalVariable > ( GVal ) ; if ( ! GVar ) continue ; bool IsAma = false ; if ( GVar -> hasAttribute ( <STR_LIT> ) ) IsAma = true ; else if ( ! GVar -> hasAttribute ( <STR_LIT> ) ) continue ;

processCandidate ( MRI , MBB , MI , SrcReg , DstReg , GVal , IsAma ) ;


<s> if ( skipFunction ( MF . getFunction ( ) ) ) return false ; initialize ( MF ) ;


<s> bool <ISA_LIT>MISimplifyPatchable :: isLoadInst ( unsigned Opcode ) { return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> return ; } if ( Opcode == <STR_LIT> ) checkADDrr ( MRI , RelocOp , GVal ) ; else if ( Opcode == <STR_LIT> ) checkShift ( MRI , * Inst -> getParent ( ) , RelocOp , GVal , <STR_LIT> ) ; else if ( Opcode == <STR_LIT> ) checkShift ( MRI , * Inst -> getParent ( ) , RelocOp , GVal , <STR_LIT> ) ; else if ( Opcode == <STR_LIT> ) checkShift ( MRI , * Inst -> getParent ( ) , RelocOp , GVal , <STR_LIT> ) ;


<s> else if ( Opcode == <STR_LIT> ) checkShift ( MRI , * Inst -> getParent ( ) , RelocOp , GVal , <STR_LIT> ) ;


<s> MachineInstr * ToErase = nullptr ; bool Changed = false ; for ( MachineBasicBlock & MBB : * MF ) { for ( MachineInstr & MI : MBB ) { if ( ToErase ) { ToErase -> eraseFromParent ( ) ; ToErase = nullptr ; } if ( ! isLoadInst ( MI . getOpcode ( ) ) ) continue ; if ( SkipInsts . find ( & MI ) != SkipInsts . end ( ) ) continue ; if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) continue ; if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) || MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) continue ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;

MachineInstr * DefInst = MRI -> getUniqueVRegDef ( SrcReg ) ;


<s> if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) || MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) continue ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DefInst = MRI -> getUniqueVRegDef ( SrcReg ) ; if ( ! DefInst ) continue ; if ( DefInst -> getOpcode ( ) != <STR_LIT> ) continue ; const MachineOperand & MO = DefInst -> getOperand ( <NUM_LIT> ) ; if ( ! MO . isGlobal ( ) ) continue ; const GlobalValue * GVal = MO . getGlobal ( ) ; auto * GVar = dyn_cast < GlobalVariable > ( GVal ) ; if ( ! GVar ) continue ; bool IsAma = false ; if ( GVar -> hasAttribute ( <STR_LIT> ) ) IsAma = true ; else if ( ! GVar -> hasAttribute ( <STR_LIT> ) ) continue ; processCandidate ( MRI , MBB , MI , SrcReg , DstReg , GVal , IsAma ) ; ToErase = & MI ; Changed = true ;


<s> MachineInstr * DefInst = MRI -> getUniqueVRegDef ( SrcReg ) ; if ( ! DefInst ) continue ; bool IsCandidate = false ; if ( DefInst -> getOpcode ( ) == <STR_LIT> ) { const MachineOperand & MO = DefInst -> getOperand ( <NUM_LIT> ) ; if ( MO . isGlobal ( ) ) { const GlobalValue * GVal = MO . getGlobal ( ) ; auto * GVar = dyn_cast < GlobalVariable > ( GVal ) ; if ( GVar ) { if ( GVar -> hasAttribute ( <STR_LIT> ) ) { assert ( ImmVal == <NUM_LIT> ) ; IsCandidate = true ; } else if ( ! GVar -> hasInitializer ( ) && GVar -> hasExternalLinkage ( ) && GVar -> getSection ( ) == <STR_LIT> ) { if ( ImmVal == <NUM_LIT> ) IsCandidate = true ; else errs ( ) << <STR_LIT> << GVar -> getName ( ) << <STR_LIT> << ImmVal << <STR_LIT> ; } } } } if ( ! IsCandidate ) continue ; auto Begin = MRI -> use_begin ( DstReg ) , End = MRI -> use_end ( ) ; decltype ( End ) NextI ; for ( auto I = Begin ; I != End ; I = NextI ) { NextI = std :: next ( I ) ; I -> setReg ( SrcReg ) ; }


<s> } if ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) continue ; if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) continue ; if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) || MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) continue ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmVal = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineInstr * DefInst = MRI -> getUniqueVRegDef ( SrcReg ) ; if ( ! DefInst ) continue ; bool IsCandidate = false ; if ( DefInst -> getOpcode ( ) == <STR_LIT> ) { const MachineOperand & MO = DefInst -> getOperand ( <NUM_LIT> ) ; if ( MO . isGlobal ( ) ) { const GlobalValue * GVal = MO . getGlobal ( ) ; auto * GVar = dyn_cast < GlobalVariable > ( GVal ) ; if ( GVar ) { if ( GVar -> hasAttribute ( <STR_LIT> ) ) { assert ( ImmVal == <NUM_LIT> ) ; IsCandidate = true ; } else if ( ! GVar -> hasInitializer ( ) && GVar -> hasExternalLinkage ( ) && GVar -> getSection ( ) == <STR_LIT> ) { if ( ImmVal == <NUM_LIT> ) IsCandidate = true ; else errs ( ) << <STR_LIT> << GVar -> getName ( ) << <STR_LIT> << ImmVal << <STR_LIT> ; } } } } if ( ! IsCandidate ) continue ; auto Begin = MRI -> use_begin ( DstReg ) , End = MRI -> use_end ( ) ;


<s> else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) COREOp = <STR_LIT> ; else continue ; const MachineOperand & ImmOp = DefInst -> getOperand ( <NUM_LIT> ) ; if ( ! ImmOp . isImm ( ) || ImmOp . getImm ( ) != <NUM_LIT> ) continue ; BuildMI ( * DefInst -> getParent ( ) , * DefInst , DefInst -> getDebugLoc ( ) , TII -> get ( COREOp ) ) . add ( DefInst -> getOperand ( <NUM_LIT> ) ) . addImm ( Opcode ) . add ( * BaseOp ) . addGlobalAddress ( GVal ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>MISimplifyPatchablePass ( ) {

return new <ISA_LIT>MISimplifyPatchable ( ) ;


<s> MF = & MFParm ; TII = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ;


<s> if ( Opcode == <STR_LIT> ) { Register TmpReg = I -> getParent ( ) -> getOperand ( <NUM_LIT> ) . getReg ( ) ; processDstReg ( MRI , TmpReg , DstReg , GVal , false ) ; } } BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , <NUM_LIT> , <STR_LIT> ) ; return ; }

processDstReg ( MRI , DstReg , SrcReg , GVal , true ) ;


<s> for ( auto I = Begin ; I != End ; I = NextI ) { NextI = std :: next ( I ) ; if ( ! MRI -> getUniqueVRegDef ( I -> getReg ( ) ) ) continue ; unsigned Opcode = I -> getParent ( ) -> getOpcode ( ) ; if ( Opcode == <STR_LIT> ) { Register TmpReg = I -> getParent ( ) -> getOperand ( <NUM_LIT> ) . getReg ( ) ; processDstReg ( MRI , TmpReg , DstReg , GVal , false ) ; } } BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , <NUM_LIT> , <STR_LIT> ) ; return ; }


<s> if ( doSrcRegProp ) I -> setReg ( SrcReg ) ;

if ( MRI -> getUniqueVRegDef ( I -> getReg ( ) ) ) processInst ( MRI , I -> getParent ( ) , & * I , GVal ) ;


<s> unsigned Opcode = Inst -> getOpcode ( ) ; if ( Opcode == <STR_LIT> ) checkADDrr ( MRI , RelocOp , GVal ) ; else if ( Opcode == <STR_LIT> ) checkShift ( MRI , * Inst -> getParent ( ) , RelocOp , GVal , <STR_LIT> ) ; else if ( Opcode == <STR_LIT> ) checkShift ( MRI , * Inst -> getParent ( ) , RelocOp , GVal , <STR_LIT> ) ;


<s> if ( Opcode == <STR_LIT> ) checkADDrr ( MRI , RelocOp , GVal ) ; else if ( Opcode == <STR_LIT> ) checkShift ( MRI , * Inst -> getParent ( ) , RelocOp , GVal , <STR_LIT> ) ; else if ( Opcode == <STR_LIT> ) checkShift ( MRI , * Inst -> getParent ( ) , RelocOp , GVal , <STR_LIT> ) ;


<s> ToErase -> eraseFromParent ( ) ; ToErase = nullptr ; } if ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) continue ; if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) continue ; if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) || MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) continue ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DefInst = MRI -> getUniqueVRegDef ( SrcReg ) ; if ( ! DefInst ) continue ; bool IsCandidate = false ; const GlobalValue * GVal = nullptr ; if ( DefInst -> getOpcode ( ) == <STR_LIT> ) { const MachineOperand & MO = DefInst -> getOperand ( <NUM_LIT> ) ; if ( MO . isGlobal ( ) ) { GVal = MO . getGlobal ( ) ; auto * GVar = dyn_cast < GlobalVariable > ( GVal ) ;


<s> if ( ! skipFunction ( MF . getFunction ( ) ) ) {


<s> if ( ! Call -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ) report_fatal_error ( <STR_LIT> ) ; PreserveDITypeCalls . push_back ( Call ) ; } } } if ( PreserveDITypeCalls . empty ( ) ) return false ; std :: string BaseName = <STR_LIT> ; static int Count = <NUM_LIT> ; for ( auto Call : PreserveDITypeCalls ) { const ConstantInt * Flag = dyn_cast < ConstantInt > ( Call -> getArgOperand ( <NUM_LIT> ) ) ; assert ( Flag ) ; uint64_t FlagValue = Flag -> getValue ( ) . getZExtValue ( ) ; if ( FlagValue >= <STR_LIT> ) report_fatal_error ( <STR_LIT> ) ; MDNode * MD = Call -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ; uint32_t Reloc ; if ( FlagValue == <STR_LIT> ) { Reloc = <STR_LIT> ; } else { Reloc = <STR_LIT> ; DIType * Ty = cast < DIType > ( MD ) ; while ( auto * DTy = dyn_cast < DIDerivedType > ( Ty ) ) { unsigned Tag = DTy -> getTag ( ) ; if ( Tag != dwarf :: DW_TAG_const_type && Tag != dwarf :: DW_TAG_volatile_type ) break ; Ty = DTy -> getBaseType ( ) ; }


<s> if ( ! Call -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ) report_fatal_error ( <STR_LIT> ) ; PreserveDITypeCalls . push_back ( Call ) ; } } } if ( PreserveDITypeCalls . empty ( ) ) return false ; std :: string BaseName = <STR_LIT> ; static int Count = <NUM_LIT> ; for ( auto Call : PreserveDITypeCalls ) { const ConstantInt * Flag = dyn_cast < ConstantInt > ( Call -> getArgOperand ( <NUM_LIT> ) ) ; assert ( Flag ) ; uint64_t FlagValue = Flag -> getValue ( ) . getZExtValue ( ) ; if ( FlagValue >= <STR_LIT> ) report_fatal_error ( <STR_LIT> ) ; MDNode * MD = Call -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ; uint32_t Reloc ; if ( FlagValue == <STR_LIT> ) { Reloc = <STR_LIT> ; } else { Reloc = <STR_LIT> ; DIType * Ty = cast < DIType > ( MD ) ; while ( auto * DTy = dyn_cast < DIDerivedType > ( Ty ) ) { unsigned Tag = DTy -> getTag ( ) ; if ( Tag != dwarf :: DW_TAG_const_type && Tag != dwarf :: DW_TAG_volatile_type ) break ; Ty = DTy -> getBaseType ( ) ; } if ( Ty -> getName ( ) . empty ( ) ) { if ( isa < DISubroutineType > ( Ty ) ) report_fatal_error ( <STR_LIT> ) ; else report_fatal_error ( <STR_LIT> ) ; } MD = Ty ; } BasicBlock * BB = Call -> getParent ( ) ; IntegerType * VarType = Type :: getInt64Ty ( BB -> getContext ( ) ) ;

std :: string GVName = BaseName + std :: to_string ( Count ) + <STR_LIT> + std :: to_string ( Reloc ) ;


<s> if ( M -> debug_compile_units ( ) . empty ( ) ) return false ; std :: vector < CallInst * > PreserveDITypeCalls ; for ( auto & BB : F ) { for ( auto & I : BB ) { auto * Call = dyn_cast < CallInst > ( & I ) ; if ( ! Call ) continue ; const auto * GV = dyn_cast < GlobalValue > ( Call -> getCalledOperand ( ) ) ; if ( ! GV ) continue ; if ( GV -> getName ( ) . startswith ( <STR_LIT> ) ) { if ( ! Call -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ) report_fatal_error ( <STR_LIT> ) ; PreserveDITypeCalls . push_back ( Call ) ; } } } if ( PreserveDITypeCalls . empty ( ) ) return false ; std :: string BaseName = <STR_LIT> ; static int Count = <NUM_LIT> ; for ( auto Call : PreserveDITypeCalls ) { const ConstantInt * Flag = dyn_cast < ConstantInt > ( Call -> getArgOperand ( <NUM_LIT> ) ) ; assert ( Flag ) ;

uint64_t FlagValue = Flag -> getValue ( ) . getZExtValue ( ) ;


<s> uint64_t FlagValue = Flag -> getValue ( ) . getZExtValue ( ) ; if ( FlagValue >= <STR_LIT> ) report_fatal_error ( <STR_LIT> ) ; MDNode * MD = Call -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ; uint32_t Reloc ; if ( FlagValue == <STR_LIT> ) { Reloc = <STR_LIT> ; } else { Reloc = <STR_LIT> ; DIType * Ty = cast < DIType > ( MD ) ; if ( Ty -> getName ( ) . empty ( ) ) report_fatal_error ( <STR_LIT> ) ; } BasicBlock * BB = Call -> getParent ( ) ; IntegerType * VarType = Type :: getInt64Ty ( BB -> getContext ( ) ) ; std :: string GVName = BaseName + std :: to_string ( Count ) + <STR_LIT> + std :: to_string ( Reloc ) ; GlobalVariable * GV = new GlobalVariable ( * M , VarType , false , GlobalVariable :: ExternalLinkage , NULL , GVName ) ; GV -> addAttribute ( <STR_LIT> ) ; GV -> setMetadata ( LLVMContext :: MD_preserve_access_index , MD ) ; auto * LDInst = new LoadInst ( Type :: getInt64Ty ( BB -> getContext ( ) ) , GV , <STR_LIT> , Call ) ;

Instruction * PassThroughInst = <STR_LIT> ( M , BB , LDInst , Call ) ;


<s> <ISA_LIT>PreserveDIType ( ) : ModulePass ( ID ) {


<s> std :: vector < CallInst * > PreserveDITypeCalls ; for ( auto & F : M ) { for ( auto & BB : F ) { for ( auto & I : BB ) { auto * Call = dyn_cast < CallInst > ( & I ) ; if ( ! Call ) continue ; const auto * GV = dyn_cast < GlobalValue > ( Call -> getCalledOperand ( ) ) ; if ( ! GV ) continue ; if ( GV -> getName ( ) . startswith ( <STR_LIT> ) ) { if ( ! Call -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ) report_fatal_error ( <STR_LIT> ) ; PreserveDITypeCalls . push_back ( Call ) ; } } } } if ( PreserveDITypeCalls . empty ( ) ) return false ; std :: string BaseName = <STR_LIT> ; int Count = <NUM_LIT> ; for ( auto Call : PreserveDITypeCalls ) { const ConstantInt * Flag = dyn_cast < ConstantInt > ( Call -> getArgOperand ( <NUM_LIT> ) ) ; assert ( Flag ) ;


<s> uint32_t Reloc ; if ( FlagValue == <STR_LIT> ) Reloc = <STR_LIT> ; else Reloc = <STR_LIT> ; BasicBlock * BB = Call -> getParent ( ) ; IntegerType * VarType = Type :: getInt32Ty ( BB -> getContext ( ) ) ; std :: string GVName = BaseName + std :: to_string ( Count ) + <STR_LIT> + std :: to_string ( Reloc ) ; GlobalVariable * GV = new GlobalVariable ( M , VarType , false , GlobalVariable :: ExternalLinkage , NULL , GVName ) ; GV -> addAttribute ( <STR_LIT> ) ; MDNode * MD = Call -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ;

GV -> setMetadata ( LLVMContext :: MD_preserve_access_index , MD ) ;


<s> StringRef getPassName ( ) const override {


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( M . debug_compile_units ( ) . empty ( ) ) return false ; return doTransformation ( M ) ;


<s> uint32_t Reloc ; if ( FlagValue == <STR_LIT> ) { Reloc = <STR_LIT> ; } else { Reloc = <STR_LIT> ; DIType * Ty = cast < DIType > ( MD ) ; if ( Ty -> getName ( ) . empty ( ) ) report_fatal_error ( <STR_LIT> ) ; } BasicBlock * BB = Call -> getParent ( ) ; IntegerType * VarType = Type :: getInt32Ty ( BB -> getContext ( ) ) ; std :: string GVName = BaseName + std :: to_string ( Count ) + <STR_LIT> + std :: to_string ( Reloc ) ; GlobalVariable * GV = new GlobalVariable ( M , VarType , false , GlobalVariable :: ExternalLinkage , NULL , GVName ) ; GV -> addAttribute ( <STR_LIT> ) ;


<s> if ( GV -> getName ( ) . startswith ( <STR_LIT> ) ) { if ( ! Call -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ) report_fatal_error ( <STR_LIT> ) ; PreserveDITypeCalls . push_back ( Call ) ; } } } if ( PreserveDITypeCalls . empty ( ) ) return false ; std :: string BaseName = <STR_LIT> ; static int Count = <NUM_LIT> ; for ( auto Call : PreserveDITypeCalls ) { const ConstantInt * Flag = dyn_cast < ConstantInt > ( Call -> getArgOperand ( <NUM_LIT> ) ) ; assert ( Flag ) ; uint64_t FlagValue = Flag -> getValue ( ) . getZExtValue ( ) ; if ( FlagValue >= <STR_LIT> ) report_fatal_error ( <STR_LIT> ) ; MDNode * MD = Call -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ; uint32_t Reloc ; if ( FlagValue == <STR_LIT> ) { Reloc = <STR_LIT> ; } else { Reloc = <STR_LIT> ; DIType * Ty = cast < DIType > ( MD ) ; while ( auto * DTy = dyn_cast < DIDerivedType > ( Ty ) ) { unsigned Tag = DTy -> getTag ( ) ; if ( Tag != dwarf :: DW_TAG_const_type && Tag != dwarf :: DW_TAG_volatile_type ) break ; Ty = DTy -> getBaseType ( ) ; } if ( Ty -> getName ( ) . empty ( ) ) report_fatal_error ( <STR_LIT> ) ; MD = Ty ; } BasicBlock * BB = Call -> getParent ( ) ; IntegerType * VarType = Type :: getInt64Ty ( BB -> getContext ( ) ) ; std :: string GVName = BaseName + std :: to_string ( Count ) + <STR_LIT> + std :: to_string ( Reloc ) ; GlobalVariable * GV = new GlobalVariable ( * M , VarType , false , GlobalVariable :: ExternalLinkage , NULL , GVName ) ; GV -> addAttribute ( <STR_LIT> ) ; GV -> setMetadata ( LLVMContext :: MD_preserve_access_index , MD ) ; auto * LDInst = new LoadInst ( Type :: getInt64Ty ( BB -> getContext ( ) ) , GV , <STR_LIT> , Call ) ; Instruction * PassThroughInst = <STR_LIT> ( M , BB , LDInst , Call ) ; Call -> replaceAllUsesWith ( PassThroughInst ) ; Call -> eraseFromParent ( ) ; Count ++ ; } return true ;


<s> if ( PreserveDITypeCalls . empty ( ) ) return false ; std :: string BaseName = <STR_LIT> ; int Count = <NUM_LIT> ; for ( auto Call : PreserveDITypeCalls ) { const ConstantInt * Flag = dyn_cast < ConstantInt > ( Call -> getArgOperand ( <NUM_LIT> ) ) ; assert ( Flag ) ; uint64_t FlagValue = Flag -> getValue ( ) . getZExtValue ( ) ; if ( FlagValue >= <STR_LIT> ) report_fatal_error ( <STR_LIT> ) ; MDNode * MD = Call -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ; uint32_t Reloc ; if ( FlagValue == <STR_LIT> ) { Reloc = <STR_LIT> ; } else { Reloc = <STR_LIT> ; DIType * Ty = cast < DIType > ( MD ) ; if ( Ty -> getName ( ) . empty ( ) ) report_fatal_error ( <STR_LIT> ) ; } BasicBlock * BB = Call -> getParent ( ) ; IntegerType * VarType = Type :: getInt32Ty ( BB -> getContext ( ) ) ; std :: string GVName = BaseName + std :: to_string ( Count ) + <STR_LIT> + std :: to_string ( Reloc ) ; GlobalVariable * GV = new GlobalVariable ( * M , VarType , false , GlobalVariable :: ExternalLinkage , NULL , GVName ) ; GV -> addAttribute ( <STR_LIT> ) ; GV -> setMetadata ( LLVMContext :: MD_preserve_access_index , MD ) ; auto * LDInst = new LoadInst ( Type :: getInt32Ty ( BB -> getContext ( ) ) , GV , <STR_LIT> , Call ) ; Instruction * PassThroughInst = <STR_LIT> ( M , BB , LDInst , Call ) ; Call -> replaceAllUsesWith ( PassThroughInst ) ; Call -> eraseFromParent ( ) ; Count ++ ; }


<s> } else { Reloc = <STR_LIT> ; DIType * Ty = cast < DIType > ( MD ) ; if ( Ty -> getName ( ) . empty ( ) ) report_fatal_error ( <STR_LIT> ) ; } BasicBlock * BB = Call -> getParent ( ) ; IntegerType * VarType = Type :: getInt32Ty ( BB -> getContext ( ) ) ; std :: string GVName = BaseName + std :: to_string ( Count ) + <STR_LIT> + std :: to_string ( Reloc ) ; GlobalVariable * GV = new GlobalVariable ( * M , VarType , false , GlobalVariable :: ExternalLinkage , NULL , GVName ) ; GV -> addAttribute ( <STR_LIT> ) ; GV -> setMetadata ( LLVMContext :: MD_preserve_access_index , MD ) ; auto * LDInst = new LoadInst ( Type :: getInt32Ty ( BB -> getContext ( ) ) , GV , <STR_LIT> , Call ) ; Instruction * PassThroughInst = <STR_LIT> ( M , BB , LDInst , Call ) ; Call -> replaceAllUsesWith ( PassThroughInst ) ; Call -> eraseFromParent ( ) ; Count ++ ; } return true ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; M = F . getParent ( ) ; if ( ! M ) return false ; if ( M -> debug_compile_units ( ) . empty ( ) ) return false ; return doTransformation ( F ) ;


<s> <ISA_LIT>PreserveDIType ( ) : FunctionPass ( ID ) {


<s> uint64_t FlagValue = Flag -> getValue ( ) . getZExtValue ( ) ; if ( FlagValue >= <STR_LIT> ) report_fatal_error ( <STR_LIT> ) ; MDNode * MD = Call -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ; uint32_t Reloc ; if ( FlagValue == <STR_LIT> ) { Reloc = <STR_LIT> ; } else { Reloc = <STR_LIT> ; DIType * Ty = cast < DIType > ( MD ) ; if ( Ty -> getName ( ) . empty ( ) ) report_fatal_error ( <STR_LIT> ) ; } BasicBlock * BB = Call -> getParent ( ) ; IntegerType * VarType = Type :: getInt32Ty ( BB -> getContext ( ) ) ; std :: string GVName = BaseName + std :: to_string ( Count ) + <STR_LIT> + std :: to_string ( Reloc ) ; GlobalVariable * GV = new GlobalVariable ( * M , VarType , false , GlobalVariable :: ExternalLinkage , NULL , GVName ) ; GV -> addAttribute ( <STR_LIT> ) ;


<s> return new <ISA_LIT>PreserveDIType ( ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>PreserveDIType ( ) { return new <ISA_LIT>PreserveDIType ( ) ;


<s> return <ISA_LIT>PreserveDITypeImpl ( F ) ? PreservedAnalyses :: none ( ) : PreservedAnalyses :: all ( ) ;


<s> PreservedAnalyses <ISA_LIT>PreserveDITypePass :: run ( Function & F , FunctionAnalysisManager & AM ) {

return <ISA_LIT>PreserveDITypeImpl ( F ) ? PreservedAnalyses :: none ( ) : PreservedAnalyses :: all ( ) ;


<s> bool <ISA_LIT>PreserveDIType :: runOnFunction ( Function & F ) {

return <ISA_LIT>PreserveDITypeImpl ( F ) ;


<s> return <ISA_LIT>PreserveDITypeImpl ( F ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) {


<s> } unsigned FrameReg = getFrameRegister ( MF ) ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; unsigned reg = MI . getOperand ( i - <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , ++ II , DL , TII . get ( <STR_LIT> ) , reg ) . addReg ( reg ) . addImm ( Offset ) ; return ; }

int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ;


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SaveList ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return <STR_LIT> ;


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ;


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , <STR_LIT> ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const TargetInstrInfo & tii ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , TII ( tii ) {


<s> unsigned FrameReg = getFrameRegister ( MF ) ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; unsigned reg = MI . getOperand ( i - <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , ++ II , dl , TII . get ( <STR_LIT> ) , reg ) . addReg ( reg ) . addImm ( Offset ) ; return ; } int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { llvm_unreachable ( <STR_LIT> ) ; } MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ;


<s> <ISA_LIT>RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , RegScavenger * RS ) const { assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; unsigned i = <NUM_LIT> ; MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } unsigned FrameReg = getFrameRegister ( MF ) ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ;

if ( MI . getOpcode ( ) == <STR_LIT> ) {


<s> unsigned <ISA_LIT>RegisterInfo :: getBaseRegister ( ) const { llvm_unreachable ( <STR_LIT> ) ; return <NUM_LIT> ;


<s> const uint16_t * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SaveList ;


<s> unsigned <ISA_LIT>RegisterInfo :: getEHHandlerRegister ( ) const { llvm_unreachable ( <STR_LIT> ) ; return <NUM_LIT> ;


<s> bool <ISA_LIT>RegisterInfo :: hasBasePointer ( const MachineFunction & MF ) const {


processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const {


<s> bool <ISA_LIT>RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ;


<s> if ( Offset <= - <NUM_LIT> ) { auto F = MF . getFunction ( ) ; DiagnosticInfoUnsupported DiagStackSize ( * F , <STR_LIT> <STR_LIT> , DL ) ; F -> getContext ( ) . diagnose ( DiagStackSize ) ;


<s> static void WarnSize ( int Offset , MachineFunction & MF , DebugLoc & DL ) { if ( Offset <= - <NUM_LIT> ) { auto F = MF . getFunction ( ) ; DiagnosticInfoUnsupported DiagStackSize ( * F , <STR_LIT> <STR_LIT> , DL ) ;

F -> getContext ( ) . diagnose ( DiagStackSize ) ;


<s> Register <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const {


<s> while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } unsigned FrameReg = getFrameRegister ( MF ) ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) ; MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; unsigned reg = MI . getOperand ( i - <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , ++ II , DL , TII . get ( <STR_LIT> ) , reg ) . addReg ( reg ) . addImm ( Offset ) ; return ; } int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) + MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) llvm_unreachable ( <STR_LIT> ) ;


<s> assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; unsigned i = <NUM_LIT> ; MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } unsigned FrameReg = getFrameRegister ( MF ) ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) ; MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; unsigned reg = MI . getOperand ( i - <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , ++ II , DL , TII . get ( <STR_LIT> ) , reg ) . addReg ( reg ) . addImm ( Offset ) ; return ; } int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) + MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) llvm_unreachable ( <STR_LIT> ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { unsigned reg = MI . getOperand ( i - <NUM_LIT> ) . getReg ( ) ;

BuildMI ( MBB , ++ II , DL , TII . get ( <STR_LIT> ) , reg ) . addReg ( FrameReg ) ;


<s> unsigned FrameReg = getFrameRegister ( MF ) ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; unsigned reg = MI . getOperand ( i - <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , ++ II , DL , TII . get ( <STR_LIT> ) , reg ) . addReg ( reg ) . addImm ( Offset ) ; return ; } int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) llvm_unreachable ( <STR_LIT> ) ; MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ;


<s> bool enableMultipleCopyHints ( ) const override { return true ;


<s> if ( ! DL ) for ( auto & I : MBB ) if ( I . getDebugLoc ( ) ) { DL = I . getDebugLoc ( ) ; break ; } while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } Register FrameReg = getFrameRegister ( MF ) ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) ; WarnSize ( Offset , MF , DL ) ; MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; Register reg = MI . getOperand ( i - <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , ++ II , DL , TII . get ( <STR_LIT> ) , reg ) . addReg ( reg ) . addImm ( Offset ) ; return ; } int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) + MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) llvm_unreachable ( <STR_LIT> ) ; WarnSize ( Offset , MF , DL ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { Register reg = MI . getOperand ( i - <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , ++ II , DL , TII . get ( <STR_LIT> ) , reg ) . addReg ( FrameReg ) ; BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) , reg ) . addReg ( reg ) . addImm ( Offset ) ; MI . eraseFromParent ( ) ;


<s> int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) ; WarnSize ( Offset , MF , DL ) ; MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; Register reg = MI . getOperand ( i - <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , ++ II , DL , TII . get ( <STR_LIT> ) , reg ) . addReg ( reg ) . addImm ( Offset ) ; return ; } int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) + MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) llvm_unreachable ( <STR_LIT> ) ; WarnSize ( Offset , MF , DL ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { Register reg = MI . getOperand ( i - <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , ++ II , DL , TII . get ( <STR_LIT> ) , reg ) . addReg ( FrameReg ) ; BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) , reg ) . addReg ( reg ) . addImm ( Offset ) ; MI . eraseFromParent ( ) ;


<s> void eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const {


<s> void eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MBB . erase ( I ) ;


<s> } unsigned FrameReg = getFrameRegister ( MF ) ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) ; WarnSize ( Offset , MF , DL ) ; MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; unsigned reg = MI . getOperand ( i - <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , ++ II , DL , TII . get ( <STR_LIT> ) , reg ) . addReg ( reg ) . addImm ( Offset ) ; return ; } int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) + MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) llvm_unreachable ( <STR_LIT> ) ; WarnSize ( Offset , MF , DL ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { unsigned reg = MI . getOperand ( i - <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , ++ II , DL , TII . get ( <STR_LIT> ) , reg ) . addReg ( FrameReg ) ; BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) , reg ) . addReg ( reg ) . addImm ( Offset ) ; MI . eraseFromParent ( ) ; } else { MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ;


<s> if ( Offset <= - <NUM_LIT> ) { const Function & F = MF . getFunction ( ) ; DiagnosticInfoUnsupported DiagStackSize ( F , <STR_LIT> <STR_LIT> , DL ) ;

F . getContext ( ) . diagnose ( DiagStackSize ) ;


<s> unsigned StoresNumEstimate = alignTo ( CopyLen , Alignment ) >> Log2 ( Alignment ) ; if ( StoresNumEstimate > getCommonMaxStoresPerMemFunc ( ) ) return SDValue ( ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Dst = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Dst , Src , DAG . getConstant ( CopyLen , dl , <STR_LIT> ) , DAG . getConstant ( Alignment . value ( ) , dl , <STR_LIT> ) ) ;


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( ! ConstantSize ) return SDValue ( ) ; unsigned CopyLen = ConstantSize -> getZExtValue ( ) ; unsigned StoresNumEstimate = alignTo ( CopyLen , Alignment ) >> Log2 ( Alignment ) ;

if ( StoresNumEstimate > getCommonMaxStoresPerMemFunc ( ) ) return SDValue ( ) ;


<s> ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( ! ConstantSize ) return SDValue ( ) ; unsigned CopyLen = ConstantSize -> getZExtValue ( ) ; unsigned StoresNumEstimate = alignTo ( CopyLen , Alignment ) >> Log2 ( Alignment ) ;


<s> unsigned CopyLen = ConstantSize -> getZExtValue ( ) ; unsigned StoresNumEstimate = alignTo ( CopyLen , Align ) >> Log2_32 ( Align ) ; if ( StoresNumEstimate > getCommonMaxStoresPerMemFunc ( ) ) return SDValue ( ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Dst = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Dst , Src , DAG . getConstant ( CopyLen , dl , <STR_LIT> ) , DAG . getConstant ( Align , dl , <STR_LIT> ) ) ;


<s> const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const override {


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , InstrInfo ( ) , FrameLowering ( * this ) , TLInfo ( TM , * this ) {


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , InstrInfo ( ) , FrameLowering ( * this ) , TLInfo ( TM , * this ) , TSInfo ( TM . getDataLayout ( ) ) {


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) {


<s> std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ;


<s> HasJmpExt = true ; return ; } if ( CPU == <STR_LIT> ) { HasJmpExt = true ; HasJmp32 = true ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , FrameLowering ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) {


<s> HasJmp32 = false ; HasAlu32 = false ; UseDwarfRIS = false ;


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { initializeEnvironment ( ) ; initSubtargetFeatures ( CPU , FS ) ; ParseSubtargetFeatures ( CPU , CPU , FS ) ;


<s> initSubtargetFeatures ( CPU , FS ) ;

ParseSubtargetFeatures ( CPU , CPU , FS ) ;


<s> HasJmpExt = true ; return ; } if ( CPU == <STR_LIT> ) { HasJmpExt = true ; HasJmp32 = true ; HasAlu32 = true ; return ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , InstrInfo ( ) , FrameLowering ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) {


<s> void <ISA_LIT>Subtarget :: initializeEnvironment ( ) { HasJmpExt = false ;


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { initializeEnvironment ( ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , InstrInfo ( ) , FrameLowering ( * this ) , TLInfo ( TM ) , TSInfo ( TM . getDataLayout ( ) ) {


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , InstrInfo ( ) , FrameLowering ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) {


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override {


<s> return & InstrInfo . getRegisterInfo ( ) ;


<s> const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const override {


<s> ParseSubtargetFeatures ( CPU , FS ) ; return * this ;


<s> initializeEnvironment ( ) ; initSubtargetFeatures ( CPU , FS ) ; ParseSubtargetFeatures ( CPU , FS ) ;


<s> void <ISA_LIT>Subtarget :: initSubtargetFeatures ( StringRef CPU , StringRef FS ) { if ( CPU == <STR_LIT> ) CPU = sys :: detail :: getHostCPUNameFor<ISA_LIT> ( ) ; if ( CPU == <STR_LIT> || CPU == <STR_LIT> ) return ; if ( CPU == <STR_LIT> ) { HasJmpExt = true ;


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) {

RegisterTarget < Triple :: bpf > X ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT> ) ;


<s> RegisterTarget < Triple :: bpf > X ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT> ) ;


<s> TargetRegistry :: RegisterTarget ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , [ ] ( Triple :: ArchType ) { return false ; } , true ) ;

RegisterTarget < Triple :: bpfel , true > X ( getThe<ISA_LIT>leTarget ( ) , <STR_LIT> , <STR_LIT> ) ;


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: x86_64 > X ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT> ) ;


<s> static Target The<ISA_LIT>beTarget ; return The<ISA_LIT>beTarget ;


<s> Target & llvm :: getThe<ISA_LIT>leTarget ( ) {


<s> Target & llvm :: getThe<ISA_LIT>Target ( ) { static Target The<ISA_LIT>Target ; return The<ISA_LIT>Target ;


<s> static Target The<ISA_LIT>Target ; return The<ISA_LIT>Target ;


<s> RegisterTarget < Triple :: bpfel , true > X ( getThe<ISA_LIT>leTarget ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;

RegisterTarget < Triple :: bpfeb , true > Y ( getThe<ISA_LIT>beTarget ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: bpf , true > X ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT> ) ;


<s> RegisterTarget < Triple :: bpf , true > X ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT> ) ;


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { TargetRegistry :: RegisterTarget ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT> , [ ] ( Triple :: ArchType ) { return false ; } , true ) ;

RegisterTarget < Triple :: bpfel , true > X ( The<ISA_LIT>leTarget , <STR_LIT> , <STR_LIT> ) ;


<s> Target & getThe<ISA_LIT>beTarget ( ) { static Target The<ISA_LIT>beTarget ; return The<ISA_LIT>beTarget ;


<s> Target & getThe<ISA_LIT>leTarget ( ) {


<s> Target & getThe<ISA_LIT>Target ( ) { static Target The<ISA_LIT>Target ;


<s> TargetRegistry :: RegisterTarget ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> , [ ] ( Triple :: ArchType ) { return false ; } , true ) ;

RegisterTarget < Triple :: bpfel , true > X ( getThe<ISA_LIT>leTarget ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> if ( Subtarget -> getHasAlu32 ( ) && ! DisableMIPeephole ) addPass ( create<ISA_LIT>MIPeepholePass ( ) ) ;


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) {

const <ISA_LIT>Subtarget * Subtarget = get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl ( ) ;


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) if ( Subtarget -> getHasAlu32 ( ) && ! DisableMIPeephole ) addPass ( create<ISA_LIT>MIPreEmitPeepholePass ( ) ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> return new <ISA_LIT>PassConfig ( * this , PM ) ;


<s> if ( ! RM . hasValue ( ) ) return Reloc :: PIC_ ; return * RM ;


<s> static Reloc :: Model getEffectiveRelocModel ( Optional < Reloc :: Model > RM ) {

if ( ! RM . hasValue ( ) ) return Reloc :: PIC_ ;


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>leTarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( getThe<ISA_LIT>beTarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > Z ( getThe<ISA_LIT>Target ( ) ) ; PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ;

initialize<ISA_LIT>MIPeepholePass ( PR ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) , Subtarget ( TT , CPU , FS , * this ) {


<s> static std :: string computeDataLayout ( const Triple & TT ) { if ( TT . getArch ( ) == Triple :: bpfeb ) return <STR_LIT> ;