<s> RC = & <STR_LIT> ; break ; } const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I ; for ( I = BB -> getIterator ( ) ; I != F -> end ( ) && & ( * I ) != BB ; ++ I ) ; if ( I != F -> end ( ) ) ++ I ; MachineBasicBlock * LoopBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * RemBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , LoopBB ) ; F -> insert ( I , RemBB ) ; RemBB -> splice ( RemBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; RemBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( LoopBB ) ; BB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( LoopBB ) ; unsigned ShiftAmtReg = RI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ShiftAmtReg2 = RI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ShiftReg = RI . createVirtualRegister ( RC ) ; unsigned ShiftReg2 = RI . createVirtualRegister ( RC ) ; unsigned ShiftAmtSrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( ShiftAmtSrcReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( RemBB ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftReg ) . addReg ( SrcReg ) . addMBB ( BB ) . addReg ( ShiftReg2 ) . addMBB ( LoopBB ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg ) . addReg ( ShiftAmtSrcReg ) . addMBB ( BB ) . addReg ( ShiftAmtReg2 ) . addMBB ( LoopBB ) ; auto ShiftMI = BuildMI ( LoopBB , dl , TII . get ( Opc ) , ShiftReg2 ) . addReg ( ShiftReg ) ; if ( HasRepeatedOperand ) ShiftMI . addReg ( ShiftReg ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg2 ) . addReg ( ShiftAmtReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( LoopBB ) ; BuildMI ( * RemBB , RemBB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addMBB ( BB ) . addReg ( ShiftReg2 ) . addMBB ( LoopBB ) ; MI . eraseFromParent ( ) ; return RemBB ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerDivRem ( SDValue Op , SelectionDAG & DAG ) const { unsigned Opcode = Op -> getOpcode ( ) ; assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; bool IsSigned = ( Opcode == <STR_LIT> ) ; EVT VT = Op -> getValueType ( <NUM_LIT> ) ; Type * Ty = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; RTLIB :: Libcall LC ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : LC = IsSigned ? RTLIB :: SDIVREM_I8 : RTLIB :: UDIVREM_I8 ; break ; case <STR_LIT> : LC = IsSigned ? RTLIB :: SDIVREM_I16 : RTLIB :: UDIVREM_I16 ; break ; case <STR_LIT> : LC = IsSigned ? RTLIB :: SDIVREM_I32 : RTLIB :: UDIVREM_I32 ; break ; case <STR_LIT> : LC = IsSigned ? RTLIB :: SDIVREM_I64 : RTLIB :: UDIVREM_I64 ; break ; } SDValue InChain = DAG . getEntryNode ( ) ;


<s> assert ( ( LHS . getSimpleValueType ( ) == RHS . getSimpleValueType ( ) ) && <STR_LIT> ) ; assert ( ( ( LHS . getSimpleValueType ( ) == <STR_LIT> ) || ( LHS . getSimpleValueType ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Cmp ; if ( LHS . getSimpleValueType ( ) == <STR_LIT> && dyn_cast < ConstantSDNode > ( RHS ) ) { SDValue LHSlo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ;

SDValue LHShi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ;


<s> SDValue LHSlo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue LHShi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue RHSlo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RHS , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue RHShi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RHS , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; Cmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHSlo , RHSlo ) ; Cmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHShi , RHShi , Cmp ) ; } else {

Cmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , RHS ) ;


<s> case <STR_LIT> : Opc8 = <STR_LIT> ; ShiftAmount = ShiftAmount % VT . getSizeInBits ( ) ; break ; case <STR_LIT> : Opc8 = <STR_LIT> ; break ; case <STR_LIT> : Opc8 = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( Op . getOpcode ( ) == <STR_LIT> && <NUM_LIT> <= ShiftAmount && ShiftAmount < <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; ShiftAmount -= <NUM_LIT> ; } else if ( Op . getOpcode ( ) == <STR_LIT> && <NUM_LIT> <= ShiftAmount && ShiftAmount < <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; ShiftAmount -= <NUM_LIT> ; } else if ( Op . getOpcode ( ) == <STR_LIT> && ShiftAmount == <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; ShiftAmount = <NUM_LIT> ; } else if ( Op . getOpcode ( ) == <STR_LIT> && ShiftAmount == <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; ShiftAmount = <NUM_LIT> ; } else if ( Op . getOpcode ( ) == <STR_LIT> && ShiftAmount == <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; ShiftAmount = <NUM_LIT> ; } } while ( ShiftAmount -- ) { Victim = DAG . getNode ( Opc8 , dl , VT , Victim ) ; }


<s> Register Reg ; if ( VT == <STR_LIT> ) { Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; } else { Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; }


<s> if ( VT == <STR_LIT> ) { Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; } else { Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; } if ( Reg ) return Reg ; report_fatal_error ( <STR_LIT> ) ;


<s> SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & isTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI . IsVarArg ; MachineFunction & MF = DAG . getMachineFunction ( ) ; isTailCall = false ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; const Function * F = nullptr ; if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; F = cast < Function > ( GV ) ; Callee = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ; } else if ( const ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { Callee = DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; } if ( isVarArg ) { CCInfo . AnalyzeCallOperands ( Outs , ArgCC_<ISA_LIT>_Vararg ) ; } else { analyzeArguments ( & CLI , F , & DAG . getDataLayout ( ) , Outs , ArgLocs , CCInfo ) ; } unsigned NumBytes = CCInfo . getNextStackOffset ( ) ; Chain = DAG . getCALLSEQ_START ( Chain , NumBytes , <NUM_LIT> , DL ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; unsigned AI , AE ; bool HasStackArgs = false ; for ( AI = <NUM_LIT> , AE = ArgLocs . size ( ) ; AI != AE ; ++ AI ) { CCValAssign & VA = ArgLocs [ AI ] ; EVT RegVT = VA . getLocVT ( ) ; SDValue Arg = OutVals [ AI ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; case CCValAssign :: BCvt :


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto DL = DAG . getDataLayout ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; if ( isVarArg ) { CCInfo . AnalyzeFormalArguments ( Ins , ArgCC_<ISA_LIT>_Vararg ) ; } else { analyzeArguments ( nullptr , & MF . getFunction ( ) , & DL , Ins , ArgLocs , CCInfo ) ; } SDValue ArgValue ; for ( CCValAssign & VA : ArgLocs ) { if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) { RC = & <STR_LIT> ; } else if ( RegVT == <STR_LIT> ) { RC = & <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertShift ( MI , MBB ) ; case <STR_LIT> : case <STR_LIT> : return insertMul ( MI , MBB ) ; case <STR_LIT> : return insertCopyR1 ( MI , MBB ) ; } assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; const <ISA_LIT>InstrInfo & TII = ( const <ISA_LIT>InstrInfo & ) * MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const BasicBlock * LLVM_BB = MBB -> getBasicBlock ( ) ; MachineBasicBlock * FallThrough = MBB -> getFallThrough ( ) ; if ( FallThrough != nullptr ) { BuildMI ( MBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( FallThrough ) ; } MachineBasicBlock * trueMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * falseMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator I ; for ( I = MF -> begin ( ) ; I != MF -> end ( ) && & ( * I ) != MBB ; ++ I ) ; if ( I != MF -> end ( ) ) ++ I ; MF -> insert ( I , trueMBB ) ; MF -> insert ( I , falseMBB ) ; trueMBB -> splice ( trueMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ;

trueMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ;


<s> ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: ZExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; EVT LocVT = VA . getLocVT ( ) ; int FI = MFI . CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DL ) ) ; InVals . push_back ( DAG . getLoad ( LocVT , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ) ; } } if ( isVarArg ) { unsigned StackSize = CCInfo . getNextStackOffset ( ) ; <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; AFI -> setVarArgsFrameIndex ( MFI . CreateFixedObject ( <NUM_LIT> , StackSize , true ) ) ; }


<s> if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( Op . getOpcode ( ) == <STR_LIT> && <NUM_LIT> <= ShiftAmount && ShiftAmount < <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; ShiftAmount -= <NUM_LIT> ; } else if ( Op . getOpcode ( ) == <STR_LIT> && <NUM_LIT> <= ShiftAmount && ShiftAmount < <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; ShiftAmount -= <NUM_LIT> ; } else if ( Op . getOpcode ( ) == <STR_LIT> && ShiftAmount == <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; ShiftAmount = <NUM_LIT> ; } else if ( Op . getOpcode ( ) == <STR_LIT> && ShiftAmount == <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; ShiftAmount = <NUM_LIT> ; } else if ( Op . getOpcode ( ) == <STR_LIT> && ShiftAmount == <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; ShiftAmount = <NUM_LIT> ; } else if ( Op . getOpcode ( ) == <STR_LIT> && ShiftAmount == <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; ShiftAmount = <NUM_LIT> ; } } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( <NUM_LIT> <= ShiftAmount && ShiftAmount < <NUM_LIT> ) switch ( Op . getOpcode ( ) ) { case <STR_LIT> : Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; ShiftAmount -= <NUM_LIT> ; break ; case <STR_LIT> : Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; ShiftAmount -= <NUM_LIT> ; break ; default : break ; } else if ( <NUM_LIT> <= ShiftAmount && ShiftAmount < <NUM_LIT> ) switch ( Op . getOpcode ( ) ) { case <STR_LIT> : Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; ShiftAmount -= <NUM_LIT> ; Opc8 = <STR_LIT> ; break ; case <STR_LIT> :


<s> if ( IsCall ) { parseExternFuncCallArgs ( * Outs , Args ) ; } else { assert ( F != nullptr && <STR_LIT> ) ; parseFunctionArgs ( F , TD , Args ) ; } unsigned RegsLeft = array_lengthof ( RegList8 ) , ValNo = <NUM_LIT> ; bool UsesStack = false ; for ( unsigned i = <NUM_LIT> , pos = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i ) { unsigned Size = Args [ i ] ; MVT LocVT = ( IsCall ) ? ( * Outs ) [ pos ] . VT : ( * Ins ) [ pos ] . VT ; if ( ! UsesStack && ( Size <= RegsLeft ) ) { const MCPhysReg * RegList = ( LocVT == <STR_LIT> ) ? RegList16 : RegList8 ; for ( unsigned j = <NUM_LIT> ; j != Size ; ++ j ) { unsigned Reg = CCInfo . AllocateReg ( ArrayRef < MCPhysReg > ( RegList , array_lengthof ( RegList8 ) ) ) ; CCInfo . addLoc ( CCValAssign :: getReg ( ValNo ++ , LocVT , Reg , LocVT , CCValAssign :: Full ) ) ; -- RegsLeft ; } std :: reverse ( ArgLocs . begin ( ) + pos , ArgLocs . begin ( ) + pos + Size ) ; } else { UsesStack = true ; for ( unsigned j = <NUM_LIT> ; j != Size ; ++ j ) { unsigned Offset = CCInfo . AllocateStack ( TD -> getTypeAllocSize ( EVT ( LocVT ) . getTypeForEVT ( CCInfo . getContext ( ) ) ) , TD -> getABITypeAlignment ( EVT ( LocVT ) . getTypeForEVT ( CCInfo . getContext ( ) ) ) ) ;

CCInfo . addLoc ( CCValAssign :: getMem ( ValNo ++ , LocVT , Offset , LocVT , CCValAssign :: Full ) ) ;


<s> parseExternFuncCallArgs ( * Outs , Args ) ; } else { assert ( F != nullptr && <STR_LIT> ) ; parseFunctionArgs ( F , TD , Args ) ; } unsigned RegsLeft = array_lengthof ( RegList8 ) , ValNo = <NUM_LIT> ; bool UsesStack = false ; for ( unsigned i = <NUM_LIT> , pos = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i ) { unsigned Size = Args [ i ] ; MVT LocVT = ( IsCall ) ? ( * Outs ) [ pos ] . VT : ( * Ins ) [ pos ] . VT ; if ( ! UsesStack && ( Size <= RegsLeft ) ) { const MCPhysReg * RegList = ( LocVT == <STR_LIT> ) ? RegList16 : RegList8 ; for ( unsigned j = <NUM_LIT> ; j != Size ; ++ j ) { unsigned Reg = CCInfo . AllocateReg ( ArrayRef < MCPhysReg > ( RegList , array_lengthof ( RegList8 ) ) ) ; CCInfo . addLoc ( CCValAssign :: getReg ( ValNo ++ , LocVT , Reg , LocVT , CCValAssign :: Full ) ) ;


<s> break ; } const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I ; for ( I = F -> begin ( ) ; I != F -> end ( ) && & ( * I ) != BB ; ++ I ) ; if ( I != F -> end ( ) ) ++ I ; MachineBasicBlock * LoopBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * RemBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , LoopBB ) ; F -> insert ( I , RemBB ) ; RemBB -> splice ( RemBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; RemBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( LoopBB ) ; BB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( LoopBB ) ; unsigned ShiftAmtReg = RI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ShiftAmtReg2 = RI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ShiftReg = RI . createVirtualRegister ( RC ) ; unsigned ShiftReg2 = RI . createVirtualRegister ( RC ) ; unsigned ShiftAmtSrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( ShiftAmtSrcReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( RemBB ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftReg ) . addReg ( SrcReg ) . addMBB ( BB ) . addReg ( ShiftReg2 ) . addMBB ( LoopBB ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg ) . addReg ( ShiftAmtSrcReg ) . addMBB ( BB ) . addReg ( ShiftAmtReg2 ) . addMBB ( LoopBB ) ; BuildMI ( LoopBB , dl , TII . get ( Opc ) , ShiftReg2 ) . addReg ( ShiftReg ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg2 ) . addReg ( ShiftAmtReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( LoopBB ) ;

BuildMI ( * RemBB , RemBB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addMBB ( BB ) . addReg ( ShiftReg2 ) . addMBB ( LoopBB ) ;


<s> Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = ( Type * ) StructType :: get ( Ty , Ty , nullptr ) ; SDLoc dl ( Op ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setLibCallee ( getLibcallCallingConv ( LC ) , RetTy , Callee , std :: move ( Args ) ) . setInRegister ( ) . setSExtResult ( isSigned ) . setZExtResult ( ! isSigned ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ;


<s> analyzeBuiltinArguments ( * CLI , F , TD , Outs , Ins , CallConv , ArgLocs , CCInfo , IsCall , IsVarArg ) ; return ; } default : {

analyzeStandardArguments ( CLI , F , TD , Outs , Ins , CallConv , ArgLocs , CCInfo , IsCall , IsVarArg ) ;


<s> } return ; } SmallVector < unsigned , <NUM_LIT> > Args ; if ( IsCall ) { parseExternFuncCallArgs ( * Outs , Args ) ; } else { assert ( F != nullptr && <STR_LIT> ) ; parseFunctionArgs ( * Ins , Args ) ; } unsigned RegsLeft = array_lengthof ( RegList8 ) , ValNo = <NUM_LIT> ; bool UsesStack = false ; for ( unsigned i = <NUM_LIT> , pos = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i ) { unsigned Size = Args [ i ] ; if ( Size == <NUM_LIT> ) continue ; MVT LocVT = ( IsCall ) ? ( * Outs ) [ pos ] . VT : ( * Ins ) [ pos ] . VT ; if ( ! UsesStack && ( Size <= RegsLeft ) ) { const MCPhysReg * RegList = ( LocVT == <STR_LIT> ) ? RegList16 : RegList8 ; for ( unsigned j = <NUM_LIT> ; j != Size ; ++ j ) { unsigned Reg = CCInfo . AllocateReg ( ArrayRef < MCPhysReg > ( RegList , array_lengthof ( RegList8 ) ) ) ; CCInfo . addLoc ( CCValAssign :: getReg ( ValNo ++ , LocVT , Reg , LocVT , CCValAssign :: Full ) ) ; -- RegsLeft ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ;

auto CCFunction = CCAssignFnForReturn ( CallConv ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; auto CCFunction = CCAssignFnForReturn ( CallConv ) ; return CCInfo . CheckReturn ( Outs , CCFunction ) ;


<s> switch ( CC ) { case CallingConv :: <ISA_LIT>_BUILTIN : return RetCC_<ISA_LIT>_BUILTIN ; default :


<s> int Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertShift ( MI , MBB ) ; case <STR_LIT> : case <STR_LIT> : return insertMul ( MI , MBB ) ; } assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; const <ISA_LIT>InstrInfo & TII = ( const <ISA_LIT>InstrInfo & ) * MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const BasicBlock * LLVM_BB = MBB -> getBasicBlock ( ) ; MachineBasicBlock * FallThrough = MBB -> getFallThrough ( ) ; if ( FallThrough != nullptr ) { BuildMI ( MBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( FallThrough ) ; } MachineBasicBlock * trueMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * falseMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator I ; for ( I = MF -> begin ( ) ; I != MF -> end ( ) && & ( * I ) != MBB ; ++ I ) ; if ( I != MF -> end ( ) ) ++ I ; MF -> insert ( I , trueMBB ) ; MF -> insert ( I , falseMBB ) ; trueMBB -> splice ( trueMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; trueMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; <STR_LIT> CC = ( <STR_LIT> ) MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( MBB , dl , TII . getBrCond ( CC ) ) . addMBB ( trueMBB ) ; BuildMI ( MBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( falseMBB ) ; MBB -> addSuccessor ( falseMBB ) ; MBB -> addSuccessor ( trueMBB ) ; BuildMI ( falseMBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( trueMBB ) ; falseMBB -> addSuccessor ( trueMBB ) ; BuildMI ( * trueMBB , trueMBB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( MBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( falseMBB ) ; MI . eraseFromParent ( ) ;


<s> return insertShift ( MI , MBB ) ; case <STR_LIT> : case <STR_LIT> : return insertMul ( MI , MBB ) ; } assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; const <ISA_LIT>InstrInfo & TII = ( const <ISA_LIT>InstrInfo & ) * MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const BasicBlock * LLVM_BB = MBB -> getBasicBlock ( ) ; MachineBasicBlock * FallThrough = MBB -> getFallThrough ( ) ; if ( FallThrough != nullptr ) { BuildMI ( MBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( FallThrough ) ; } MachineBasicBlock * trueMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * falseMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ;


<s> SDValue LHS3 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS_1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue RHS_0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RHS , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue RHS_1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RHS , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue RHS0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RHS_0 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue RHS1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RHS_0 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue RHS2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RHS_1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue RHS3 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RHS_1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; if ( UseTest ) { SDValue Top = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS3 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; Cmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Top ) ; } else { Cmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS0 , RHS0 ) ; Cmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS1 , RHS1 , Cmp ) ; Cmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS2 , RHS2 , Cmp ) ; Cmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS3 , RHS3 , Cmp ) ; } } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { if ( UseTest ) { Cmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ( VT == <STR_LIT> ) ? LHS : DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ) ; } else { Cmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , RHS ) ; } } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ! UseTest ) {

<ISA_LIT>cc = DAG . getConstant ( intCCTo<ISA_LIT>CC ( CC ) , DL , <STR_LIT> ) ;


<s> SDValue Callee = CLI . Callee ; if ( const ExternalSymbolSDNode * G = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { return G -> getSymbol ( ) ; } if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { return G -> getGlobal ( ) -> getName ( ) ; }


<s> switch ( ConstraintCode [ <NUM_LIT> ] ) { case 'Q' : return InlineAsm :: Constraint_Q ; } return TargetLowering :: getInlineAsmMemConstraint ( ConstraintCode ) ;


<s> if ( Op -> getOpcode ( ) != <STR_LIT> && Op -> getOpcode ( ) != <STR_LIT> ) { return false ; } if ( const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ) { int RHSC = RHS -> getSExtValue ( ) ; if ( Op -> getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( ( VT == <STR_LIT> && RHSC != <NUM_LIT> ) || ( VT == <STR_LIT> && RHSC != <NUM_LIT> ) ) { return false ; } Base = Op -> getOperand ( <NUM_LIT> ) ; Offset = DAG . getConstant ( RHSC , DL , <STR_LIT> ) ; AM = <STR_LIT> ;


<s> if ( <STR_LIT> ( LD ) ) { return false ; } } else if ( const StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Op = ST -> getBasePtr ( ) . getNode ( ) ; if ( <STR_LIT> ( ST ) ) { return false ; } } else { return false ; } if ( VT != <STR_LIT> && VT != <STR_LIT> ) { return false ; } if ( Op -> getOpcode ( ) != <STR_LIT> && Op -> getOpcode ( ) != <STR_LIT> ) { return false ; } if ( const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ) { int RHSC = RHS -> getSExtValue ( ) ; if ( Op -> getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( ( VT == <STR_LIT> && RHSC != - <NUM_LIT> ) || ( VT == <STR_LIT> && RHSC != - <NUM_LIT> ) ) {


<s> case 'a' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'b' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'd' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'l' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'e' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'q' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'r' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 't' : return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; case 'w' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'x' : case 'X' : return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; case 'y' : case 'Y' : return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; case 'z' : case 'Z' : return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ;


<s> Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; } else { Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> assert ( ! VT . isVector ( ) && <STR_LIT> ) ;


<s> case 'e' : case 'q' : case 't' : case 'w' : case 'x' : case 'X' : case 'y' : case 'Y' : case 'z' : case 'Z' : weight = CW_SpecificReg ; break ; case 'G' : if ( const ConstantFP * C = dyn_cast < ConstantFP > ( CallOperandVal ) ) { if ( C -> isZero ( ) ) { weight = CW_Constant ; } } break ; case 'I' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) { weight = CW_Constant ; } } break ; case 'J' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getSExtValue ( ) >= - <NUM_LIT> ) && ( C -> getSExtValue ( ) <= <NUM_LIT> ) ) { weight = CW_Constant ; } } break ; case 'K' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) == <NUM_LIT> ) { weight = CW_Constant ; } } break ; case 'L' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) == <NUM_LIT> ) { weight = CW_Constant ; } } break ; case 'M' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) { weight = CW_Constant ; } } break ; case 'N' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getSExtValue ( ) == - <NUM_LIT> ) { weight = CW_Constant ; } } break ; case 'O' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) {

if ( ( C -> getZExtValue ( ) == <NUM_LIT> ) || ( C -> getZExtValue ( ) == <NUM_LIT> ) || ( C -> getZExtValue ( ) == <NUM_LIT> ) ) {


<s> weight = CW_Constant ; } } break ; case 'M' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) { weight = CW_Constant ; } } break ; case 'N' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getSExtValue ( ) == - <NUM_LIT> ) { weight = CW_Constant ; } } break ; case 'O' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getZExtValue ( ) == <NUM_LIT> ) || ( C -> getZExtValue ( ) == <NUM_LIT> ) || ( C -> getZExtValue ( ) == <NUM_LIT> ) ) { weight = CW_Constant ; } } break ; case 'P' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) == <NUM_LIT> ) { weight = CW_Constant ; } } break ; case 'R' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getSExtValue ( ) >= - <NUM_LIT> ) && ( C -> getSExtValue ( ) <= <NUM_LIT> ) ) { weight = CW_Constant ; } }


<s> NODE ( ROR ) ; NODE ( ASR ) ; NODE ( LSLLOOP ) ; NODE ( LSRLOOP ) ; NODE ( ASRLOOP ) ; NODE ( BRCOND ) ; NODE ( CMP ) ; NODE ( CMPC ) ; NODE ( TST ) ; NODE ( SELECT_CC ) ;


<s> if ( isCopyMulResult ( I ) ) ++ I ; BuildMI ( * BB , I , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; return BB ;


<s> Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; HasRepeatedOperand = true ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; } const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I ; for ( I = BB -> getIterator ( ) ; I != F -> end ( ) && & ( * I ) != BB ; ++ I ) ; if ( I != F -> end ( ) ) ++ I ; MachineBasicBlock * LoopBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * RemBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , LoopBB ) ; F -> insert ( I , RemBB ) ; RemBB -> splice ( RemBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; RemBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( LoopBB ) ; BB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( LoopBB ) ; unsigned ShiftAmtReg = RI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ShiftAmtReg2 = RI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ShiftReg = RI . createVirtualRegister ( RC ) ; unsigned ShiftReg2 = RI . createVirtualRegister ( RC ) ; unsigned ShiftAmtSrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( ShiftAmtSrcReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( RemBB ) ;

BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftReg ) . addReg ( SrcReg ) . addMBB ( BB ) . addReg ( ShiftReg2 ) . addMBB ( LoopBB ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> unsigned SrcReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) ; } return false ;


<s> if ( isa < PointerType > ( Ty ) && AS == <STR_LIT> ) { return false ; } if ( Offs < <NUM_LIT> ) Offs = - Offs ; if ( AM . BaseGV == <NUM_LIT> && AM . HasBaseReg && AM . Scale == <NUM_LIT> && isUInt < <NUM_LIT> > ( Offs ) ) { return true ; } return false ;


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return true ;


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const {


<s> case 'N' : if ( CVal64 != - <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CVal64 , DL , Ty ) ; break ; case 'O' : if ( CUVal64 != <NUM_LIT> && CUVal64 != <NUM_LIT> && CUVal64 != <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'P' : if ( CUVal64 != <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'R' : if ( CVal64 < - <NUM_LIT> || CVal64 > <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CVal64 , DL , Ty ) ; break ; } break ; } case 'G' : const ConstantFPSDNode * FC = dyn_cast < ConstantFPSDNode > ( Op ) ; if ( ! FC || ! FC -> isZero ( ) ) return ; Result = DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ;


<s> const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ;

SDValue Result = DAG . getTargetBlockAddress ( BA , getPointerTy ( DL ) ) ;


<s> const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDValue Result = DAG . getTargetBlockAddress ( BA , getPointerTy ( DL ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , getPointerTy ( DL ) , Result ) ;


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; SDValue TargetCC ;

SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , TargetCC , DAG , dl ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; isTailCall = false ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; const Function * F = nullptr ; if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; F = cast < Function > ( GV ) ; Callee = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ; } else if ( const ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { Callee = DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; } analyzeArguments ( & CLI , F , & DAG . getDataLayout ( ) , & Outs , <NUM_LIT> , CallConv , ArgLocs , CCInfo , true , isVarArg ) ; unsigned NumBytes = CCInfo . getNextStackOffset ( ) ; Chain = DAG . getCALLSEQ_START ( Chain , NumBytes , <NUM_LIT> , DL ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; unsigned AI , AE ; bool HasStackArgs = false ; for ( AI = <NUM_LIT> , AE = ArgLocs . size ( ) ; AI != AE ; ++ AI ) { CCValAssign & VA = ArgLocs [ AI ] ; EVT RegVT = VA . getLocVT ( ) ; SDValue Arg = OutVals [ AI ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; } if ( VA . isMemLoc ( ) ) { HasStackArgs = true ; break ; } RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } if ( HasStackArgs ) { for ( AE = AI , AI = ArgLocs . size ( ) ; AI != AE ; -- AI ) { unsigned Loc = AI - <NUM_LIT> ; CCValAssign & VA = ArgLocs [ Loc ] ; SDValue Arg = OutVals [ Loc ] ; assert ( VA . isMemLoc ( ) ) ;

SDValue PtrOff = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , DAG . getRegister ( <STR_LIT> , getPointerTy ( DAG . getDataLayout ( ) ) ) , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + <NUM_LIT> , DL ) ) ;


<s> Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; } if ( VA . isMemLoc ( ) ) { HasStackArgs = true ; break ; } RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } if ( HasStackArgs ) { for ( AE = AI , AI = ArgLocs . size ( ) ; AI != AE ; -- AI ) { unsigned Loc = AI - <NUM_LIT> ; CCValAssign & VA = ArgLocs [ Loc ] ; SDValue Arg = OutVals [ Loc ] ; assert ( VA . isMemLoc ( ) ) ; SDValue PtrOff = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , DAG . getRegister ( <STR_LIT> , getPointerTy ( DAG . getDataLayout ( ) ) ) , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + <NUM_LIT> , DL ) ) ; Chain = DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo :: getStack ( MF , VA . getLocMemOffset ( ) ) , <NUM_LIT> ) ; } } SDValue InFlag ; for ( auto Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , DL , Reg . first , Reg . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( auto Reg : RegsToPass ) { Ops . push_back ( DAG . getRegister ( Reg . first , Reg . second . getValueType ( ) ) ) ; } const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallConv ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; if ( InFlag . getNode ( ) ) { Ops . push_back ( InFlag ) ; } Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Ops ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , InFlag , DL ) ; if ( ! Ins . empty ( ) ) { InFlag = Chain . getValue ( <NUM_LIT> ) ; }

return LowerCallResult ( Chain , InFlag , CallConv , isVarArg , Ins , DL , DAG , InVals ) ;


<s> SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = ( Type * ) StructType :: get ( Ty , Ty ) ; SDLoc dl ( Op ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setLibCallee ( getLibcallCallingConv ( LC ) , RetTy , Callee , std :: move ( Args ) ) . setInRegister ( ) . setSExtResult ( IsSigned ) . setZExtResult ( ! IsSigned ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ; return CallInfo . first ;


<s> break ; case <STR_LIT> : LC = IsSigned ? RTLIB :: SDIVREM_I64 : RTLIB :: UDIVREM_I64 ; break ; case <STR_LIT> : LC = IsSigned ? RTLIB :: SDIVREM_I128 : RTLIB :: UDIVREM_I128 ; break ; } SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( SDValue const & Value : Op -> op_values ( ) ) { Entry . Node = Value ; Entry . Ty = Value . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . IsSExt = IsSigned ; Entry . IsZExt = ! IsSigned ; Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = ( Type * ) StructType :: get ( Ty , Ty ) ; SDLoc dl ( Op ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setLibCallee ( getLibcallCallingConv ( LC ) , RetTy , Callee , std :: move ( Args ) ) . setInRegister ( ) . setSExtResult ( IsSigned ) . setZExtResult ( ! IsSigned ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ;


<s> } else if ( RegVT == <STR_LIT> ) { RC = & <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: SExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: ZExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; }


<s> const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) { RC = & <STR_LIT> ; } else if ( RegVT == <STR_LIT> ) { RC = & <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: SExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: ZExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; EVT LocVT = VA . getLocVT ( ) ; int FI = MFI . CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DL ) ) ; InVals . push_back ( DAG . getLoad ( LocVT , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) , <NUM_LIT> ) ) ; } }


<s> const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ;

int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ;


<s> } SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) . getAttributes ( ) . hasAttribute ( AttributeList :: FunctionIndex , Attribute :: Naked ) ) { return Chain ; }

unsigned RetOpc = ( CallConv == CallingConv :: <ISA_LIT>_INTR || CallConv == CallingConv :: <ISA_LIT>_SIGNAL ) ? <STR_LIT> : <STR_LIT> ;


<s> CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) . getAttributes ( ) . hasAttribute ( AttributeList :: FunctionIndex , Attribute :: Naked ) ) { return Chain ; } unsigned RetOpc = ( CallConv == CallingConv :: <ISA_LIT>_INTR || CallConv == CallingConv :: <ISA_LIT>_SIGNAL ) ? <STR_LIT> : <STR_LIT> ; RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) { RetOps . push_back ( Flag ) ; } return DAG . getNode ( RetOpc , dl , <STR_LIT> , RetOps ) ;


<s> SDLoc dl ( Op ) ; SDValue TargetCC ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , TargetCC , DAG , dl ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { TrueV , FalseV , TargetCC , Cmp } ; return DAG . getNode ( <STR_LIT> , dl , VTs , Ops ) ;


<s> SDValue TargetCC ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , TargetCC , DAG , DL ) ; SDValue TrueV = DAG . getConstant ( <NUM_LIT> , DL , Op . getValueType ( ) ) ; SDValue FalseV = DAG . getConstant ( <NUM_LIT> , DL , Op . getValueType ( ) ) ;

SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ;


<s> SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , TargetCC , DAG , DL ) ; SDValue TrueV = DAG . getConstant ( <NUM_LIT> , DL , Op . getValueType ( ) ) ; SDValue FalseV = DAG . getConstant ( <NUM_LIT> , DL , Op . getValueType ( ) ) ;


<s> const SDNode * N = Op . getNode ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( N ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) { switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; }


<s> const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; auto DL = DAG . getDataLayout ( ) ; SDLoc dl ( Op ) ; SDValue FI = DAG . getFrameIndex ( AFI -> getVarArgsFrameIndex ( ) , getPointerTy ( DL ) ) ;

return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FI , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , <NUM_LIT> ) ;


<s> unsigned Size = <NUM_LIT> ; unsigned Offset = <NUM_LIT> ; while ( ( i != e ) && ( In [ i ] . PartOffset == Offset ) ) {

Offset += In [ i ] . VT . getStoreSize ( ) ;


<s> unsigned Size = <NUM_LIT> ; unsigned Offset = <NUM_LIT> ; while ( ( i != e ) && ( In [ i ] . PartOffset == Offset ) ) { Offset += In [ i ] . VT . getStoreSize ( ) ; ++ i ; ++ Size ; } Out . push_back ( Size ) ; }


<s> for ( const <STR_LIT> & Arg : Ins ) { if ( Arg . PartOffset > <NUM_LIT> ) continue ; unsigned Bytes = ( ( Arg . ArgVT . getSizeInBits ( ) ) + <NUM_LIT> ) / <NUM_LIT> ; Out . push_back ( ( Bytes + <NUM_LIT> ) / <NUM_LIT> ) ; }


<s> switch ( N -> getOpcode ( ) ) { case <STR_LIT> : { if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) { SDValue Sub = DAG . getNode ( <STR_LIT> , DL , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( - C -> getAPIntValue ( ) , DL , C -> getValueType ( <NUM_LIT> ) ) ) ;


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : HasSpills ( false ) , HasAllocas ( false ) , HasStackArgs ( false ) , CalleeSavedFrameSize ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) { unsigned CallConv = MF . getFunction ( ) . getCallingConv ( ) ; this -> IsInterruptHandler = CallConv == CallingConv :: <ISA_LIT>_INTR || MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; this -> IsSignalHandler = CallConv == CallingConv :: <ISA_LIT>_SIGNAL || MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ;


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : HasSpills ( false ) , HasAllocas ( false ) , HasStackArgs ( false ) , CalleeSavedFrameSize ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) {

unsigned CallConv = MF . getFunction ( ) . getCallingConv ( ) ;


<s> bool isInterruptHandler ( ) const { return IsInterruptHandler ;


<s> unsigned getCalleeSavedFrameSize ( ) const { return CalleeSavedFrameSize ;


<s> bool getHasSpills ( ) const { return HasSpills ;


<s> void setHasAllocas ( bool B ) { HasAllocas = B ;


<s> void setHasSpills ( bool B ) { HasSpills = B ;


<s> void setVarArgsFrameIndex ( int Idx ) {


<s> CodePointerSize = <NUM_LIT> ; CalleeSaveStackSlotSize = <NUM_LIT> ; CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; UseIntegratedAssembler = true ; SupportsDebugInformation = true ;


<s> CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; UseIntegratedAssembler = true ; SupportsDebugInformation = true ;


<s> PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ;


<s> CalleeSaveStackSlotSize = <NUM_LIT> ; CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; UseIntegratedAssembler = true ;


<s> PrivateLabelPrefix = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; UseIntegratedAssembler = true ;


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TT , const MCTargetOptions & Options ) { CodePointerSize = <NUM_LIT> ; CalleeSaveStackSlotSize = <NUM_LIT> ; CommentString = <STR_LIT> ;


<s> CalleeSaveStackSlotSize = <NUM_LIT> ; CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ;


<s> CalleeSaveStackSlotSize = <NUM_LIT> ; CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ;


<s> const uint16_t * Words = reinterpret_cast < uint16_t const * > ( & Val ) ; size_t WordCount = Size / <NUM_LIT> ; for ( int64_t i = WordCount - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) {


<s> return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ; } MCFixupKind FixupKind = static_cast < MCFixupKind > ( Fixup ) ;

Fixups . push_back ( MCFixup :: create ( Offset , MO . getExpr ( ) , FixupKind , MI . getLoc ( ) ) ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: encodeImm ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { auto MO = MI . getOperand ( OpNo ) ; if ( MO . isExpr ( ) ) { if ( isa < <ISA_LIT>MCExpr > ( MO . getExpr ( ) ) ) { return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ; } MCFixupKind FixupKind = static_cast < MCFixupKind > ( Fixup ) ; Fixups . push_back ( MCFixup :: create ( Offset , MO . getExpr ( ) , FixupKind , MI . getLoc ( ) ) ) ; return <NUM_LIT> ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: encodeLDSTPtrReg ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { auto MO = MI . getOperand ( OpNo ) ; assert ( MO . isReg ( ) ) ; switch ( MO . getReg ( ) ) { case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: encodeRelCondBrTarget ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isExpr ( ) ) { Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , MCFixupKind ( Fixup ) , MI . getLoc ( ) ) ) ; return <NUM_LIT> ; } assert ( MO . isImm ( ) ) ;


<s> Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , MCFixupKind ( Fixup ) , MI . getLoc ( ) ) ) ; return <NUM_LIT> ; } assert ( MO . isImm ( ) ) ; auto target = MO . getImm ( ) ; <STR_LIT> :: adjustBranchTarget ( target ) ;


<s> if ( MO . isFPImm ( ) ) return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( <NUM_LIT> ) . getLimitedValue ( ) ) ; assert ( MO . isExpr ( ) ) ;

return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ;


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx ) ;


<s> return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ; } MCFixupKind FixupKind = static_cast < MCFixupKind > ( Fixup ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , FixupKind , MI . getLoc ( ) ) ) ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , MCContext & Ctx ) : MCII ( MCII ) , Ctx ( Ctx ) {


<s> MCCodeEmitter * create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx ) ;


<s> MCCodeEmitter * create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) {

return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx ) ;


<s> void <ISA_LIT>MCCodeEmitter :: emitInstruction ( uint64_t Val , unsigned Size , const MCSubtargetInfo & STI , raw_ostream & OS ) const { size_t WordCount = Size / <NUM_LIT> ; for ( int64_t i = WordCount - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { uint16_t Word = ( Val >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ; <STR_LIT> :: write ( OS , Word , <STR_LIT> :: little ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: encodeCallTarget ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { auto MO = MI . getOperand ( OpNo ) ; if ( MO . isExpr ( ) ) { MCFixupKind FixupKind = static_cast < MCFixupKind > ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , FixupKind , MI . getLoc ( ) ) ) ;


<s> if ( MO . isExpr ( ) ) { MCFixupKind FixupKind = static_cast < MCFixupKind > ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , FixupKind , MI . getLoc ( ) ) ) ; return <NUM_LIT> ;


<s> assert ( MI . getOperand ( OpNo ) . isImm ( ) ) ; auto Imm = MI . getOperand ( OpNo ) . getImm ( ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: encodeComplement ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {

assert ( MI . getOperand ( OpNo ) . isImm ( ) ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: encodeImm ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { auto MO = MI . getOperand ( OpNo ) ; if ( MO . isExpr ( ) ) { if ( isa < <ISA_LIT>MCExpr > ( MO . getExpr ( ) ) ) { return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ; } MCFixupKind FixupKind = static_cast < MCFixupKind > ( Fixup ) ; Fixups . push_back ( MCFixup :: create ( Offset , MO . getExpr ( ) , FixupKind , MI . getLoc ( ) ) ) ;


<s> const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; unsigned Size = Desc . getSize ( ) ;

assert ( Size > <NUM_LIT> && <STR_LIT> ) ;


<s> const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; unsigned Size = Desc . getSize ( ) ; assert ( Size > <NUM_LIT> && <STR_LIT> ) ; uint64_t BinaryOpCode = getBinaryCodeForInstr ( MI , Fixups , STI ) ;

emitInstruction ( BinaryOpCode , Size , STI , OS ) ;


<s> assert ( MO . isReg ( ) ) ; switch ( MO . getReg ( ) ) { case <STR_LIT> : return <NUM_LIT> ;


<s> uint8_t RegBit = <NUM_LIT> ; switch ( RegOp . getReg ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : RegBit = <NUM_LIT> ; break ; case <STR_LIT> : RegBit = <NUM_LIT> ; break ; } int8_t OffsetBits ; if ( OffsetOp . isImm ( ) ) { OffsetBits = OffsetOp . getImm ( ) ; } else if ( OffsetOp . isExpr ( ) ) { OffsetBits = <NUM_LIT> ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , OffsetOp . getExpr ( ) , MCFixupKind ( <STR_LIT> ) , MI . getLoc ( ) ) ) ; } else {


<s> uint8_t RegBit = <NUM_LIT> ; switch ( RegOp . getReg ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : RegBit = <NUM_LIT> ; break ; case <STR_LIT> : RegBit = <NUM_LIT> ; break ; } int8_t OffsetBits ; if ( OffsetOp . isImm ( ) ) {


<s> unsigned <ISA_LIT>MCCodeEmitter :: encodeRelCondBrTarget ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isExpr ( ) ) { Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , MCFixupKind ( Fixup ) , MI . getLoc ( ) ) ) ; return <NUM_LIT> ; } assert ( MO . isImm ( ) ) ; auto target = MO . getImm ( ) ;

<STR_LIT> :: adjustBranchTarget ( target ) ;


Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , MCFixupKind ( Fixup ) , MI . getLoc ( ) ) ) ;


<s> Kind = Expr -> getKind ( ) ; } if ( Kind == MCExpr :: Target ) { <ISA_LIT>MCExpr const * <ISA_LIT>Expr = cast < <ISA_LIT>MCExpr > ( Expr ) ; int64_t Result ; if ( <ISA_LIT>Expr -> evaluateAsConstant ( Result ) ) { return Result ; }

MCFixupKind FixupKind = static_cast < MCFixupKind > ( <ISA_LIT>Expr -> getFixupKind ( ) ) ;


<s> if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; if ( MO . isDFPImm ( ) ) return static_cast < unsigned > ( bit_cast < double > ( MO . getDFPImm ( ) ) ) ; assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; if ( MO . isDFPImm ( ) ) return static_cast < unsigned > ( bit_cast < double > ( MO . getDFPImm ( ) ) ) ; assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: loadStorePostEncoder ( const MCInst & MI , unsigned EncodedValue , const MCSubtargetInfo & STI ) const { assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: loadStorePostEncoder ( const MCInst & MI , unsigned EncodedValue , const MCSubtargetInfo & STI ) const { assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; bool IsRegX = MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ; bool IsPredec = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; bool IsPostinc = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; if ( IsRegX || IsPredec || IsPostinc ) { EncodedValue |= ( <NUM_LIT> << <NUM_LIT> ) ; } return EncodedValue ;


<s> return new <ISA_LIT>MCELFStreamer ( Context , std :: move ( MAB ) , std :: move ( OW ) , std :: move ( CE ) ) ;


<s> void <ISA_LIT>MCELFStreamer :: emitValueForModiferKind ( const MCSymbol * Sym , unsigned SizeInBytes , SMLoc Loc , <ISA_LIT>MCExpr :: VariantKind ModifierKind ) { MCSymbolRefExpr :: VariantKind Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_NONE ; if ( ModifierKind == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) { Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_DIFF8 ;

if ( SizeInBytes == SIZE_LONG ) Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_DIFF32 ;


<s> else if ( SizeInBytes == SIZE_WORD ) Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_DIFF16 ; } else if ( ModifierKind == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO8 ) Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_LO8 ; else if ( ModifierKind == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI8 ) Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_HI8 ; else if ( ModifierKind == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HH8 ) Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_HLO8 ; MCELFStreamer :: emitValue ( MCSymbolRefExpr :: create ( Sym , Kind , getContext ( ) ) , SizeInBytes , Loc ) ;


<s> <ISA_LIT>MCELFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > TAB , raw_pwrite_stream & OS , std :: unique_ptr < MCCodeEmitter > Emitter , MCAssembler * Assembler ) : MCELFStreamer ( Context , std :: move ( TAB ) , OS , std :: move ( Emitter ) ) , MCII ( create<ISA_LIT>MCInstrInfo ( ) ) {


<s> <ISA_LIT>MCELFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > TAB , std :: unique_ptr < MCObjectWriter > OW , std :: unique_ptr < MCCodeEmitter > Emitter , MCAssembler * Assembler ) : MCELFStreamer ( Context , std :: move ( TAB ) , std :: move ( OW ) , std :: move ( Emitter ) ) , MCII ( create<ISA_LIT>MCInstrInfo ( ) ) {


<s> return new <ISA_LIT>MCELFStreamer ( Context , std :: move ( MAB ) , OS , std :: move ( CE ) ) ;


<s> MCSymbolRefExpr :: VariantKind Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_NONE ; if ( ModifierKind == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) { Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_DIFF8 ; if ( SizeInBytes == SIZE_LONG ) Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_DIFF32 ; else if ( SizeInBytes == SIZE_WORD ) Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_DIFF16 ; } else if ( ModifierKind == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO8 ) Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_LO8 ; else if ( ModifierKind == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI8 ) Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_HI8 ;

else if ( ModifierKind == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HH8 ) Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_HLO8 ;


<s> if ( ModifierKind == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) { Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_DIFF8 ; if ( SizeInBytes == SIZE_LONG ) Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_DIFF32 ; else if ( SizeInBytes == SIZE_WORD ) Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_DIFF16 ; } else if ( ModifierKind == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO8 ) Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_LO8 ; else if ( ModifierKind == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI8 ) Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_HI8 ; else if ( ModifierKind == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HH8 ) Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_HLO8 ; MCELFStreamer :: EmitValue ( MCSymbolRefExpr :: create ( Sym , Kind , getContext ( ) ) , SizeInBytes , Loc ) ;


<s> case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO8 : Value &= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI8 : Value &= <NUM_LIT> ; Value >>= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HH8 : Value &= <NUM_LIT> ; Value >>= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HHI8 : Value &= <NUM_LIT> ; Value >>= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PM_LO8 :


<s> break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PM_LO8 : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO8_GS : Value >>= <NUM_LIT> ; Value &= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PM_HI8 : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI8_GS : Value >>= <NUM_LIT> ; Value &= <NUM_LIT> ; Value >>= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PM_HH8 : Value >>= <NUM_LIT> ; Value &= <NUM_LIT> ; Value >>= <NUM_LIT> ;


<s> break ; case VK_<ISA_LIT>_HI8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>_HH8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>_HHI8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>_PM_LO8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>_PM_HI8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>_PM_HH8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ;


<s> Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>_PM_LO8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>_PM_HI8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>_PM_HH8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>_GS :


<s> Value >>= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PM_LO8 : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO8_GS : Value >>= <NUM_LIT> ; Value &= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PM_HI8 : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI8_GS : Value >>= <NUM_LIT> ; Value &= <NUM_LIT> ; Value >>= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PM_HH8 : Value >>= <NUM_LIT> ; Value &= <NUM_LIT> ; Value >>= <NUM_LIT> ;


<s> break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI8 : Value &= <NUM_LIT> ; Value >>= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HH8 : Value &= <NUM_LIT> ; Value >>= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HHI8 : Value &= <NUM_LIT> ; Value >>= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PM_LO8 :


<s> Result = MCValue :: get ( evaluateAsInt64 ( Value . getConstant ( ) ) ) ; } else { if ( ! Layout ) return false ; MCContext & Context = Layout -> getAssembler ( ) . getContext ( ) ; const MCSymbolRefExpr * Sym = Value . getSymA ( ) ; MCSymbolRefExpr :: VariantKind Modifier = Sym -> getKind ( ) ; if ( Modifier != MCSymbolRefExpr :: VK_None ) return false ; if ( Kind == VK_<ISA_LIT>_PM ) { Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_PM ;


<s> if ( ! Layout ) return false ; MCContext & Context = Layout -> getAssembler ( ) . getContext ( ) ; const MCSymbolRefExpr * Sym = Value . getSymA ( ) ; MCSymbolRefExpr :: VariantKind Modifier = Sym -> getKind ( ) ; if ( Modifier != MCSymbolRefExpr :: VK_None ) return false ; if ( Kind == VK_<ISA_LIT>_PM ) { Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_PM ; } Sym = MCSymbolRefExpr :: create ( & Sym -> getSymbol ( ) , Modifier , Context ) ; Result = MCValue :: get ( Sym , Value . getSymB ( ) , Value . getConstant ( ) ) ; } return true ;


<s> case VK_<ISA_LIT>_HI8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>_HH8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>_HHI8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>_PM_LO8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>_PM_HI8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>_PM_HH8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>_PM : case VK_<ISA_LIT>_GS : Kind = <STR_LIT> ; break ; case VK_<ISA_LIT>_LO8_GS : Kind = <STR_LIT> ; break ; case VK_<ISA_LIT>_HI8_GS : Kind = <STR_LIT> ;


<s> return Mod . Spelling == Name ; } ) ; if ( Modifier != std :: end ( ModifierNames ) ) { return Modifier -> VariantKind ; }


<s> return Mod . Spelling == Name ; } ) ; if ( Modifier != std :: end ( ModifierNames ) ) {


<s> return Mod . VariantKind == Kind ; } ) ; if ( Modifier != std :: end ( ModifierNames ) ) {


<s> const char * <ISA_LIT>MCExpr :: getName ( ) const { const auto & Modifier = llvm :: find_if ( ModifierNames , [ this ] ( ModifierEntry const & Mod ) { return Mod . VariantKind == Kind ;


<s> explicit <ISA_LIT>MCExpr ( VariantKind Kind , const MCExpr * Expr , bool Negated ) : Kind ( Kind ) , SubExpr ( Expr ) , Negated ( Negated ) {


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ;


<s> return new ( Ctx ) <ISA_LIT>MCExpr ( Kind , Expr , Negated ) ;


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: create ( VariantKind Kind , const MCExpr * Expr , bool Negated , MCContext & Ctx ) { return new ( Ctx ) <ISA_LIT>MCExpr ( Kind , Expr , Negated ) ;


<s> if ( ! isRelocatable ) return false ; if ( Value . isAbsolute ( ) ) { Result = evaluateAsInt64 ( Value . getConstant ( ) ) ; return true ;


<s> if ( ! isRelocatable ) return false ; if ( Value . isAbsolute ( ) ) {

Result = evaluateAsInt64 ( Value . getConstant ( ) ) ;


<s> case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HH8 : Value >>= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HHI8 : Value >>= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PM_LO8 : Value >>= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PM_HI8 : Value >>= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PM_HH8 : Value >>= <NUM_LIT> ;


<s> switch ( Kind ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO8 : break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI8 : Value >>= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HH8 : Value >>= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HHI8 : Value >>= <NUM_LIT> ; break ;


<s> MCValue Value ; bool isRelocatable = SubExpr -> evaluateAsRelocatable ( Value , Layout , Fixup ) ; if ( ! isRelocatable ) return false ; if ( Value . isAbsolute ( ) ) { Result = MCValue :: get ( evaluateAsInt64 ( Value . getConstant ( ) ) ) ; } else { if ( ! Layout ) return false ; MCContext & Context = Layout -> getAssembler ( ) . getContext ( ) ;

const MCSymbolRefExpr * Sym = Value . getSymA ( ) ;


<s> return getSubExpr ( ) -> findAssociatedFragment ( ) ;


<s> void fixELFSymbolsInTLSFixups ( MCAssembler & Asm ) const override {


<s> case VK_<ISA_LIT>_HI8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>_HH8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>_HHI8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>_PM_LO8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>_PM_HI8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>_PM_HH8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ;


<s> VariantKind getKind ( ) const { return Kind ;


<s> const char * <ISA_LIT>MCExpr :: getName ( ) const { const auto & Modifier = std :: find_if ( std :: begin ( ModifierNames ) , std :: end ( ModifierNames ) , [ this ] ( ModifierEntry const & Mod ) { return Mod . VariantKind == Kind ; } ) ; if ( Modifier != std :: end ( ModifierNames ) ) { return Modifier -> Spelling ;


<s> bool isNegated ( ) const { return Negated ;


<s> void setNegated ( bool negated = true ) { Negated = negated ;


<s> MI . dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) continue ; MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = lowerSymbolOperand ( MO , Printer . getSymbol ( MO . getGlobal ( ) ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = lowerSymbolOperand ( MO , Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , Ctx ) ) ; break ; case MachineOperand :: MO_RegisterMask : continue ; case MachineOperand :: MO_BlockAddress :

MCOp = lowerSymbolOperand ( MO , Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ) ;


<s> if ( TF & <STR_LIT> ) { Expr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO8 , Expr , IsNegated , Ctx ) ; } else if ( TF & <STR_LIT> ) { Expr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI8 , Expr , IsNegated , Ctx ) ; } else if ( TF != <NUM_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; }

return MCOperand :: createExpr ( Expr ) ;


<s> <ISA_LIT>MCInstLower ( MCContext & Ctx , AsmPrinter & Printer ) : Ctx ( Ctx ) , Printer ( Printer ) {


<s> break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , Ctx ) ) ; break ; case MachineOperand :: MO_RegisterMask : continue ; case MachineOperand :: MO_BlockAddress : MCOp = lowerSymbolOperand ( MO , Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = lowerSymbolOperand ( MO , Printer . GetJTISymbol ( MO . getIndex ( ) ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex :

MCOp = lowerSymbolOperand ( MO , Printer . GetCPISymbol ( MO . getIndex ( ) ) ) ;


<s> Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; } bool IsFunction = MO . isGlobal ( ) && isa < Function > ( MO . getGlobal ( ) ) ; if ( TF & <STR_LIT> ) { if ( IsFunction ) { Expr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PM_LO8 , Expr , IsNegated , Ctx ) ; } else { Expr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO8 , Expr , IsNegated , Ctx ) ; } } else if ( TF & <STR_LIT> ) { if ( IsFunction ) { Expr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PM_HI8 , Expr , IsNegated , Ctx ) ; } else { Expr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI8 , Expr , IsNegated , Ctx ) ; } } else if ( TF != <NUM_LIT> ) { llvm_unreachable ( <STR_LIT> ) ;


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) {


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return X ;


<s> static MCStreamer * createMCStreamer ( const Triple & T , MCContext & Context , std :: unique_ptr < MCAsmBackend > && MAB , std :: unique_ptr < MCObjectWriter > && OW , std :: unique_ptr < MCCodeEmitter > && Emitter , bool RelaxAll ) {

return createELFStreamer ( Context , std :: move ( MAB ) , std :: move ( OW ) , std :: move ( Emitter ) , RelaxAll ) ;


<s> return createELFStreamer ( Context , std :: move ( MAB ) , std :: move ( OW ) , std :: move ( Emitter ) , RelaxAll ) ;


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , CPU , FS ) ;


<s> return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , CPU , FS ) ;


<s> TargetRegistry :: RegisterELFStreamer ( getThe<ISA_LIT>Target ( ) , createMCStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( getThe<ISA_LIT>Target ( ) , createMCAsmTargetStreamer ) ;

TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>AsmBackend ) ;


<s> TargetRegistry :: RegisterMCInstPrinter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterELFStreamer ( getThe<ISA_LIT>Target ( ) , createMCStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( getThe<ISA_LIT>Target ( ) , createMCAsmTargetStreamer ) ;


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT , const MCTargetOptions & Options ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <NUM_LIT> ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { if ( SyntaxVariant == <NUM_LIT> ) {

return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { if ( SyntaxVariant == <NUM_LIT> ) { return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ;


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ;

Init<ISA_LIT>MCRegisterInfo ( X , <NUM_LIT> ) ;


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) {

return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , FS ) ;


<s> static MCTargetStreamer * create<ISA_LIT>ObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) {

return new <ISA_LIT>ELFStreamer ( S , STI ) ;


<s> static MCTargetStreamer * create<ISA_LIT>ObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) { return new <ISA_LIT>ELFStreamer ( S , STI ) ;


<s> static MCTargetStreamer * createMCAsmTargetStreamer ( MCStreamer & S , formatted_raw_ostream & OS , MCInstPrinter * InstPrint , bool isVerboseAsm ) { return new <ISA_LIT>TargetAsmStreamer ( S ) ;


<s> static MCStreamer * createMCStreamer ( const Triple & T , MCContext & Context , std :: unique_ptr < MCAsmBackend > && MAB , raw_pwrite_stream & OS , std :: unique_ptr < MCCodeEmitter > && Emitter , bool RelaxAll ) { return createELFStreamer ( Context , std :: move ( MAB ) , OS , std :: move ( Emitter ) , RelaxAll ) ;


<s> static MCStreamer * createMCStreamer ( const Triple & T , MCContext & Context , std :: unique_ptr < MCAsmBackend > && MAB , raw_pwrite_stream & OS , std :: unique_ptr < MCCodeEmitter > && Emitter , bool RelaxAll ) {

return createELFStreamer ( Context , std :: move ( MAB ) , OS , std :: move ( Emitter ) , RelaxAll ) ;


<s> TargetRegistry :: RegisterMCInstPrinter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterELFStreamer ( getThe<ISA_LIT>Target ( ) , createMCStreamer ) ;

TargetRegistry :: RegisterObjectTargetStreamer ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>ObjectTargetStreamer ) ;


<s> TargetRegistry :: RegisterMCSubtargetInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterELFStreamer ( getThe<ISA_LIT>Target ( ) , createMCStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( getThe<ISA_LIT>Target ( ) , createMCAsmTargetStreamer ) ;


<s> const <ISA_LIT>MachineFunctionInfo * AFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;

return AFI -> isInterruptOrSignalHandler ( ) ? CSR_Interrupts_SaveList : CSR_Normal_SaveList ;


<s> const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;

return AFI -> isInterruptOrSignalHandler ( ) ? CSR_Interrupts_RegMask : CSR_Normal_RegMask ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const {

const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;


<s> return false ; } return TargetRegisterInfo :: shouldCoalesce ( MI , SrcRC , SubReg , DstRC , DstSubReg , NewRC , LIS ) ;


<s> LoReg = getSubReg ( Reg , <STR_LIT> ) ; HiReg = getSubReg ( Reg , <STR_LIT> ) ;


<s> assert ( <STR_LIT> . contains ( Reg ) && <STR_LIT> ) ;


<s> bool <ISA_LIT>RegisterInfo :: shouldCoalesce ( MachineInstr * MI , const TargetRegisterClass * SrcRC , unsigned SubReg , const TargetRegisterClass * DstRC , unsigned DstSubReg , const TargetRegisterClass * NewRC , LiveIntervals & LIS ) const { if ( this -> getRegClass ( <STR_LIT> ) -> hasSubClassEq ( NewRC ) ) { return false ;


<s> const uint16_t * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { CallingConv :: ID CC = MF -> getFunction ( ) . getCallingConv ( ) ;

return ( ( CC == CallingConv :: <ISA_LIT>_INTR || CC == CallingConv :: <ISA_LIT>_SIGNAL ) ? CSR_Interrupts_SaveList : CSR_Normal_SaveList ) ;


<s> CallingConv :: ID CC = MF -> getFunction ( ) . getCallingConv ( ) ; return ( ( CC == CallingConv :: <ISA_LIT>_INTR || CC == CallingConv :: <ISA_LIT>_SIGNAL ) ? CSR_Interrupts_SaveList : CSR_Normal_SaveList ) ;


<s> int Opcode = MI . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) ) { return ; } if ( DstReg != MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) { return ; } switch ( Opcode ) { case <STR_LIT> : Offset += - MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; break ;


<s> } switch ( Opcode ) { case <STR_LIT> : Offset += - MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : Offset += MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; break ;


<s> const <ISA_LIT>TargetMachine & TM = ( const <ISA_LIT>TargetMachine & ) MF . getTarget ( ) ; const TargetInstrInfo & TII = * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetFrameLowering * TFI = TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; int Offset = MFI . getObjectOffset ( FrameIndex ) ; Offset += MFI . getStackSize ( ) - TFI -> getOffsetOfLocalArea ( ) + <NUM_LIT> ; Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( <STR_LIT> , false ) ; assert ( Offset > <NUM_LIT> && <STR_LIT> ) ; unsigned Opcode ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( DstReg != <STR_LIT> && <STR_LIT> ) ; II ++ ; if ( II != MBB . end ( ) ) foldFrameOffset ( II , Offset , DstReg ) ; switch ( DstReg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( isUInt < <NUM_LIT> > ( Offset ) ) { Opcode = <STR_LIT> ; break ; } LLVM_FALLTHROUGH ; } default : { Opcode = <STR_LIT> ; Offset = - Offset ; break ; } } MachineInstr * New = BuildMI ( MBB , II , dl , TII . get ( Opcode ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addImm ( Offset ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; return ; } if ( Offset > <NUM_LIT> ) { unsigned AddOpc = <STR_LIT> , SubOpc = <STR_LIT> ;

int AddOffset = Offset - <NUM_LIT> + <NUM_LIT> ;


<s> unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( DstReg != <STR_LIT> && <STR_LIT> ) ; II ++ ; if ( II != MBB . end ( ) ) foldFrameOffset ( II , Offset , DstReg ) ; switch ( DstReg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( isUInt < <NUM_LIT> > ( Offset ) ) { Opcode = <STR_LIT> ; break ; } LLVM_FALLTHROUGH ; } default : { Opcode = <STR_LIT> ; Offset = - Offset ; break ; } } MachineInstr * New = BuildMI ( MBB , II , dl , TII . get ( Opcode ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addImm ( Offset ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; return ; } if ( Offset > <NUM_LIT> ) { unsigned AddOpc = <STR_LIT> , SubOpc = <STR_LIT> ; int AddOffset = Offset - <NUM_LIT> + <NUM_LIT> ; if ( ( Offset - <NUM_LIT> + <NUM_LIT> ) > <NUM_LIT> ) { AddOpc = <STR_LIT> ; SubOpc = <STR_LIT> ; AddOffset = - AddOffset ; } BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstr * New = BuildMI ( MBB , II , dl , TII . get ( AddOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( AddOffset ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; New = BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( SubOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Offset - <NUM_LIT> + <NUM_LIT> ) ; Offset = <NUM_LIT> ;


<s> int AddOffset = Offset - <NUM_LIT> + <NUM_LIT> ; if ( ( Offset - <NUM_LIT> + <NUM_LIT> ) > <NUM_LIT> ) { AddOpc = <STR_LIT> ; SubOpc = <STR_LIT> ; AddOffset = - AddOffset ; } BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstr * New = BuildMI ( MBB , II , dl , TII . get ( AddOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( AddOffset ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( SubOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Offset - <NUM_LIT> + <NUM_LIT> ) ; Offset = <NUM_LIT> ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( <STR_LIT> , false ) ; assert ( isUInt < <NUM_LIT> > ( Offset ) && <STR_LIT> ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ;


<s> if ( Offset > <NUM_LIT> ) { unsigned AddOpc = <STR_LIT> , SubOpc = <STR_LIT> ; int AddOffset = Offset - <NUM_LIT> + <NUM_LIT> ; if ( ( Offset - <NUM_LIT> + <NUM_LIT> ) > <NUM_LIT> ) { AddOpc = <STR_LIT> ; SubOpc = <STR_LIT> ; AddOffset = - AddOffset ; } BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstr * New = BuildMI ( MBB , II , dl , TII . get ( AddOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( AddOffset ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; New = BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( SubOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Offset - <NUM_LIT> + <NUM_LIT> ) ; Offset = <NUM_LIT> ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( <STR_LIT> , false ) ;

assert ( isUInt < <NUM_LIT> > ( Offset ) && <STR_LIT> ) ;


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) { return & <STR_LIT> ;


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ;


<s> void <ISA_LIT>RegisterInfo :: splitReg ( unsigned Reg , unsigned & LoReg , unsigned & HiReg ) const { assert ( <STR_LIT> . contains ( Reg ) && <STR_LIT> ) ;


<s> LoReg = getSubReg ( Reg , <STR_LIT> ) ;


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & ) const override {


<s> assert ( DstReg != <STR_LIT> && <STR_LIT> ) ; foldFrameOffset ( * std :: next ( II ) , Offset , DstReg ) ; switch ( DstReg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( isUInt < <NUM_LIT> > ( Offset ) ) { Opcode = <STR_LIT> ; break ; } LLVM_FALLTHROUGH ; } default : { Opcode = <STR_LIT> ; Offset = - Offset ; break ; } } MachineInstr * New = BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( Opcode ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addImm ( Offset ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; return ; } if ( Offset >= <NUM_LIT> ) { unsigned AddOpc = <STR_LIT> , SubOpc = <STR_LIT> ; int AddOffset = Offset - <NUM_LIT> + <NUM_LIT> ; if ( ( Offset - <NUM_LIT> + <NUM_LIT> ) > <NUM_LIT> ) { AddOpc = <STR_LIT> ; SubOpc = <STR_LIT> ; AddOffset = - AddOffset ; } BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstr * New = BuildMI ( MBB , II , dl , TII . get ( AddOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( AddOffset ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ;

New = BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( SubOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Offset - <NUM_LIT> + <NUM_LIT> ) ;


<s> if ( ( Offset - <NUM_LIT> + <NUM_LIT> ) > <NUM_LIT> ) { AddOpc = <STR_LIT> ; SubOpc = <STR_LIT> ; AddOffset = - AddOffset ; } BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstr * New = BuildMI ( MBB , II , dl , TII . get ( AddOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( AddOffset ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; New = BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( SubOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Offset - <NUM_LIT> + <NUM_LIT> ) ; Offset = <NUM_LIT> ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( <STR_LIT> , false ) ; assert ( isUInt < <NUM_LIT> > ( Offset ) && <STR_LIT> ) ;

MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ;


<s> } default : { Opcode = <STR_LIT> ; Offset = - Offset ; break ; } } MachineInstr * New = BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( Opcode ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addImm ( Offset ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; return ; } if ( Offset >= <NUM_LIT> ) { unsigned AddOpc = <STR_LIT> , SubOpc = <STR_LIT> ; int AddOffset = Offset - <NUM_LIT> + <NUM_LIT> ; if ( ( Offset - <NUM_LIT> + <NUM_LIT> ) > <NUM_LIT> ) { AddOpc = <STR_LIT> ; SubOpc = <STR_LIT> ; AddOffset = - AddOffset ; } BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstr * New = BuildMI ( MBB , II , dl , TII . get ( AddOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( AddOffset ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; New = BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( SubOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Offset - <NUM_LIT> + <NUM_LIT> ) ; Offset = <NUM_LIT> ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CSR_Normal_RegMask ;


<s> break ; } } MachineInstr * New = BuildMI ( MBB , II , dl , TII . get ( Opcode ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addImm ( Offset ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; return ; } if ( Offset > <NUM_LIT> ) { unsigned AddOpc = <STR_LIT> , SubOpc = <STR_LIT> ; int AddOffset = Offset - <NUM_LIT> + <NUM_LIT> ; if ( ( Offset - <NUM_LIT> + <NUM_LIT> ) > <NUM_LIT> ) { AddOpc = <STR_LIT> ; SubOpc = <STR_LIT> ; AddOffset = - AddOffset ; } BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( STI . getIORegSREG ( ) ) ; MachineInstr * New = BuildMI ( MBB , II , dl , TII . get ( AddOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( AddOffset ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( <STR_LIT> ) ) . addImm ( STI . getIORegSREG ( ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( SubOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Offset - <NUM_LIT> + <NUM_LIT> ) ; Offset = <NUM_LIT> ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( <STR_LIT> , false ) ; assert ( isUInt < <NUM_LIT> > ( Offset ) && <STR_LIT> ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ;


<s> const <ISA_LIT>MachineFunctionInfo * AFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const <ISA_LIT>Subtarget & STI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ;

if ( STI . hasTinyEncoding ( ) ) return AFI -> isInterruptOrSignalHandler ( ) ? CSR_InterruptsTiny_SaveList : CSR_NormalTiny_SaveList ;


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; return STI . hasTinyEncoding ( ) ? CSR_NormalTiny_RegMask : CSR_Normal_RegMask ;


<s> Reserved . set ( <STR_LIT> ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasTinyEncoding ( ) ) { for ( unsigned Reg = <STR_LIT> ; Reg <= <STR_LIT> ; Reg ++ ) Reserved . set ( Reg ) ; for ( unsigned Reg = <STR_LIT> ; Reg <= <STR_LIT> ; Reg ++ ) Reserved . set ( Reg ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( ) : <ISA_LIT>GenRegisterInfo ( <NUM_LIT> ) {


<s> DebugLoc dl = MI . getDebugLoc ( ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; const MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>TargetMachine & TM = ( const <ISA_LIT>TargetMachine & ) MF . getTarget ( ) ; const TargetInstrInfo & TII = * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetFrameLowering * TFI = TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; int Offset = MFI . getObjectOffset ( FrameIndex ) ; Offset += MFI . getStackSize ( ) - TFI -> getOffsetOfLocalArea ( ) + <NUM_LIT> ; Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( <STR_LIT> , false ) ; assert ( Offset > <NUM_LIT> && <STR_LIT> ) ; unsigned Opcode ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( DstReg != <STR_LIT> && <STR_LIT> ) ; foldFrameOffset ( * std :: next ( II ) , Offset , DstReg ) ; switch ( DstReg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( isUInt < <NUM_LIT> > ( Offset ) ) { Opcode = <STR_LIT> ; break ; }