<s> buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ; auto MIRRC = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ; if ( ImpIsDead ) MIRRC -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;

MIRRC -> getOperand ( <NUM_LIT> ) . setIsKill ( ) ;


<s> buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define , getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) ; auto MIBHI = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) ; if ( ImpIsDead ) MIBHI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MI . eraseFromParent ( ) ; return true ;


<s> MachineInstr & MI = * MBBI ; Register DstLoReg , DstHiReg ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define , getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) ;

auto MIBHI = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) ;


<s> f ( MI ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addImm ( SREG_ADDR ) . addReg ( SCRATCH_REGISTER ) ; MI . eraseFromParent ( ) ; return true ;


<s> f ( MI ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addImm ( SREG_ADDR ) . addReg ( SCRATCH_REGISTER ) ; MI . eraseFromParent ( ) ;


<s> return expandAtomic ( MBB , MBBI , [ & ] ( MachineInstr & MI ) { auto DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto PtrOp = MI . getOperand ( <NUM_LIT> ) ; auto SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LoadOpcode = ( Width == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned StoreOpcode = ( Width == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; buildMI ( MBB , MBBI , LoadOpcode , DstReg ) . addReg ( PtrOp . getReg ( ) ) ; buildMI ( MBB , MBBI , ArithOpcode , DstReg ) . addReg ( DstReg ) . addReg ( SrcReg ) ; buildMI ( MBB , MBBI , StoreOpcode ) . add ( PtrOp ) . addReg ( DstReg ) ; } ) ;


<s> Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool SrcIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; TRI -> splitReg ( SrcReg , SrcLoReg , SrcHiReg ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; auto MIBLO = buildMI ( MBB , MBBI , Op ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addReg ( SrcLoReg , getKillRegState ( SrcIsKill ) ) ; MIBLO -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;

auto MIBHI = buildMI ( MBB , MBBI , Op ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addReg ( SrcHiReg , getKillRegState ( SrcIsKill ) ) ;


<s> unsigned Hi8 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; if ( ! isLogicImmOpRedundant ( Op , Lo8 ) ) { auto MIBLO = buildMI ( MBB , MBBI , Op ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( SrcIsKill ) ) . addImm ( Lo8 ) ; MIBLO -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; } if ( ! isLogicImmOpRedundant ( Op , Hi8 ) ) { auto MIBHI = buildMI ( MBB , MBBI , Op ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( SrcIsKill ) ) . addImm ( Hi8 ) ; if ( ImpIsDead ) MIBHI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; } MI . eraseFromParent ( ) ;


<s> buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) -> getOperand ( <NUM_LIT> ) . setIsUndef ( true ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ; auto MIRRC = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ; if ( ImpIsDead ) MIRRC -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MIRRC -> getOperand ( <NUM_LIT> ) . setIsKill ( ) ; MI . eraseFromParent ( ) ; return true ;


<s> bool <ISA_LIT>ExpandPseudo :: expandLSLB7Rd ( Block & MBB , BlockIt MBBI ) { MachineInstr & MI = * MBBI ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) -> getOperand ( <NUM_LIT> ) . setIsUndef ( true ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ; auto MIRRC = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ;

if ( ImpIsDead ) MIRRC -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;


<s> bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg ) ;

buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) ;


<s> bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) ; auto MI0 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addImm ( <NUM_LIT> ) ; MI0 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; auto MI1 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addReg ( DstLoReg ) ; MI1 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; auto MI2 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addImm ( <NUM_LIT> ) ;

MI2 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;


<s> TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) ; auto MI0 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addImm ( <NUM_LIT> ) ; MI0 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;

auto MI1 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addReg ( DstLoReg ) ;


<s> buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg ) ; auto MIBLO = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) ; if ( ImpIsDead ) MIBLO -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MI . eraseFromParent ( ) ;


<s> bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) -> getOperand ( <NUM_LIT> ) . setIsUndef ( true ) ;

buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ;


<s> TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) ; auto MI0 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addImm ( <NUM_LIT> ) ; MI0 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; auto MIBHI = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) ; if ( ImpIsDead ) MIBHI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MI . eraseFromParent ( ) ;


<s> MI1 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; auto MI2 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addImm ( <NUM_LIT> ) ; MI2 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; auto MI3 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addReg ( DstHiReg ) ; if ( ImpIsDead ) MI3 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;


<s> bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg ) ; auto MIBHI = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) ;

if ( ImpIsDead ) MIBHI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;


<s> EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; case <STR_LIT> : EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ;


<s> if ( Op == <STR_LIT> && ImmVal == <NUM_LIT> ) return true ; return false ;


<s> bool <ISA_LIT>ExpandPseudo :: isLogicImmOpRedundant ( unsigned Op , unsigned ImmVal ) const { if ( Op == <STR_LIT> && ImmVal == <NUM_LIT> ) return true ; if ( Op == <STR_LIT> && ImmVal == <NUM_LIT> ) return true ;


<s> BitVector Candidates = TRI -> getAllocatableSet ( * MBB . getParent ( ) , & <STR_LIT> ) ; for ( MachineOperand & MO : MI . operands ( ) ) { if ( MO . isReg ( ) && MO . getReg ( ) != <NUM_LIT> && ! MO . isDef ( ) && ! Register :: isVirtualRegister ( MO . getReg ( ) ) ) Candidates . reset ( MO . getReg ( ) ) ; }

BitVector Available = RS . getRegsAvailable ( & <STR_LIT> ) ;


<s> EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; case <STR_LIT> : EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ;


<s> buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ;

buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) . addImm ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) . setIsKill ( ) ;


<s> EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; case <STR_LIT> : EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ;


<s> EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; case <STR_LIT> : EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ;


<s> EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; case <STR_LIT> : EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ;


<s> buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ; auto MIRRC = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ; if ( ImpIsDead ) MIRRC -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MIRRC -> getOperand ( <NUM_LIT> ) . setIsKill ( ) ; MI . eraseFromParent ( ) ; return true ;


<s> Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) -> getOperand ( <NUM_LIT> ) . setIsUndef ( true ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ; auto MIRRC = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ;


<s> MachineInstr & MI = * MBBI ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) -> getOperand ( <NUM_LIT> ) . setIsUndef ( true ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ;

auto MIRRC = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ;


<s> EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; case <STR_LIT> : EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ;


<s> inline void adjustBranchTarget ( T & val ) { val >>= <NUM_LIT> ;


<s> <ISA_LIT>FrameAnalyzer ( ) : MachineFunctionPass ( ID ) {


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , Align ( <NUM_LIT> ) , - <NUM_LIT> ) {


<s> FunctionPass * create<ISA_LIT>FrameAnalyzerPass ( ) { return new <ISA_LIT>FrameAnalyzer ( ) ;


<s> if ( hasFP ( MF ) ) { SavedRegs . set ( <STR_LIT> ) ; SavedRegs . set ( <STR_LIT> ) ; }


<s> BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MachineInstr * New = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Amount ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; fixStackStores ( MBB , MI , TII ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; unsigned AddOpcode ;

if ( isUInt < <NUM_LIT> > ( Amount ) ) {


<s> assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; unsigned AddOpcode ; if ( isUInt < <NUM_LIT> > ( Amount ) ) { AddOpcode = <STR_LIT> ; } else { AddOpcode = <STR_LIT> ; Amount = - Amount ; } BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MachineInstr * New = BuildMI ( MBB , MI , DL , TII . get ( AddOpcode ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Amount ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; }


<s> const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; if ( ! FrameSize && ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) { restoreStatusRegister ( MF , MBB ) ; return ; } while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; int Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) { break ; } -- MBBI ; } if ( FrameSize ) { unsigned Opcode ; if ( isUInt < <NUM_LIT> > ( FrameSize ) ) {


<s> if ( AFI -> isInterruptOrSignalHandler ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( STI . getIORegSREG ( ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( ! HasFP ) { return ; } const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI . getStackSize ( ) - AFI -> getCalleeSavedFrameSize ( ) ; while ( ( MBBI != MBB . end ( ) ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) { ++ MBBI ; } BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ;

for ( MachineBasicBlock & MBBJ : llvm :: drop_begin ( MF ) ) {


<s> bool HasFP = hasFP ( MF ) ; if ( AFI -> isInterruptHandler ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( AFI -> isInterruptOrSignalHandler ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( STI . getIORegSREG ( ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( ! HasFP ) { return ; } const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI . getStackSize ( ) - AFI -> getCalleeSavedFrameSize ( ) ; while ( ( MBBI != MBB . end ( ) ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) { ++ MBBI ; } BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; for ( MachineBasicBlock & MBBJ : llvm :: drop_begin ( MF ) ) { MBBJ . addLiveIn ( <STR_LIT> ) ; } if ( ! FrameSize ) { return ; } unsigned Opcode = ( isUInt < <NUM_LIT> > ( FrameSize ) ) ? <STR_LIT> : <STR_LIT> ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opcode ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( FrameSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ;

MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;


<s> for ( MachineInstr & MI : llvm :: make_early_inc_range ( llvm :: make_range ( StartMI , MBB . end ( ) ) ) ) { if ( MI . isCall ( ) ) break ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) continue ; assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned STOpc = ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MI . setDesc ( TII . get ( STOpc ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; }


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;

return ( FuncInfo -> getHasSpills ( ) || FuncInfo -> getHasAllocas ( ) || FuncInfo -> getHasStackArgs ( ) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) ;


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; return ( FuncInfo -> getHasSpills ( ) || FuncInfo -> getHasAllocas ( ) || FuncInfo -> getHasStackArgs ( ) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) ;


<s> return hasFP ( MF ) && ! MFI . hasVarSizedObjects ( ) ;


<s> } DebugLoc DL = MBB . findDebugLoc ( MI ) ; const MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( const CalleeSavedInfo & CCSI : CSI ) { Register Reg = CCSI . getReg ( ) ; assert ( TRI -> getRegSizeInBits ( * TRI -> getMinimalPhysRegClass ( Reg ) ) == <NUM_LIT> && <STR_LIT> ) ;

BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) ;


<s> const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( const CalleeSavedInfo & CCSI : CSI ) { Register Reg = CCSI . getReg ( ) ; assert ( TRI -> getRegSizeInBits ( * TRI -> getMinimalPhysRegClass ( Reg ) ) == <NUM_LIT> && <STR_LIT> ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) ; } return true ;


<s> const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; if ( AFI -> isInterruptOrSignalHandler ( ) ) {

BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ;


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; if ( AFI -> isInterruptOrSignalHandler ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ;

BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( STI . getIORegSREG ( ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ;


<s> } for ( const MachineBasicBlock & BB : MF ) { for ( const MachineInstr & MI : BB ) { int Opcode = MI . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) ) { continue ; } for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isFI ( ) ) { continue ; }

if ( MFI . isFixedObjectIndex ( MO . getIndex ( ) ) ) {


<s> const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; for ( const CalleeSavedInfo & I : llvm :: reverse ( CSI ) ) { Register Reg = I . getReg ( ) ; bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ; assert ( TRI -> getRegSizeInBits ( * TRI -> getMinimalPhysRegClass ( Reg ) ) == <NUM_LIT> && <STR_LIT> ) ;


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , Align :: None ( ) , - <NUM_LIT> ) {


<s> return MBB . erase ( MI ) ; } DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned int Opcode = MI -> getOpcode ( ) ; int Amount = TII . getFrameSize ( * MI ) ; if ( Amount != <NUM_LIT> ) { assert ( getStackAlignment ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { fixStackStores ( MBB , MI , TII , true ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; unsigned addOpcode ; if ( isUInt < <NUM_LIT> > ( Amount ) ) {


<s> fixStackStores ( MBB , MI , TII , false ) ; return MBB . erase ( MI ) ; } DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned int Opcode = MI -> getOpcode ( ) ; int Amount = TII . getFrameSize ( * MI ) ; if ( Amount != <NUM_LIT> ) { assert ( getStackAlignment ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { fixStackStores ( MBB , MI , TII , true ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ;


<s> bool SrcIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( Opcode == <STR_LIT> ) { BuildMI ( MBB , I , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( TRI . getSubReg ( SrcReg , <STR_LIT> ) , getKillRegState ( SrcIsKill ) ) ; BuildMI ( MBB , I , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( TRI . getSubReg ( SrcReg , <STR_LIT> ) , getKillRegState ( SrcIsKill ) ) ; } else { BuildMI ( MBB , I , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( SrcIsKill ) ) ; } MI . eraseFromParent ( ) ; I = NextMI ; continue ; } unsigned STOpc = ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MI . setDesc ( TII . get ( STOpc ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; I = NextMI ;


<s> const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; for ( auto I = MI , E = MBB . end ( ) ; I != E && ! I -> isCall ( ) ; ) { MachineBasicBlock :: iterator NextMI = std :: next ( I ) ; MachineInstr & MI = * I ; unsigned Opcode = I -> getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) { I = NextMI ; continue ; } assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; if ( insertPushes ) { Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool SrcIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( Opcode == <STR_LIT> ) { BuildMI ( MBB , I , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( TRI . getSubReg ( SrcReg , <STR_LIT> ) , getKillRegState ( SrcIsKill ) ) ; BuildMI ( MBB , I , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( TRI . getSubReg ( SrcReg , <STR_LIT> ) , getKillRegState ( SrcIsKill ) ) ;


<s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( hasFP ( MF ) ) {


<s> TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( hasFP ( MF ) ) { SavedRegs . set ( <STR_LIT> ) ; SavedRegs . set ( <STR_LIT> ) ; SavedRegs . set ( <STR_LIT> ) ;


<s> Amount = - Amount ; } BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MachineInstr * New = BuildMI ( MBB , MI , DL , TII . get ( addOpcode ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Amount ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; } }


<s> BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ; } if ( ! FrameSize ) { return ; } while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; int Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) { break ; } -- MBBI ;


<s> BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( ! hasFP ( MF ) ) { return ; } const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned FrameSize = MFI . getStackSize ( ) - AFI -> getCalleeSavedFrameSize ( ) ; while ( ( MBBI != MBB . end ( ) ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) { ++ MBBI ; } BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; for ( MachineFunction :: iterator I = std :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) { I -> addLiveIn ( <STR_LIT> ) ; }


<s> bool <ISA_LIT>FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) { return false ; } DebugLoc DL = MBB . findDebugLoc ( MI ) ; const MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( const CalleeSavedInfo & CCSI : CSI ) {


<s> const MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( const CalleeSavedInfo & CCSI : CSI ) { unsigned Reg = CCSI . getReg ( ) ; assert ( TRI -> getMinimalPhysRegClass ( Reg ) -> getSize ( ) == <NUM_LIT> && <STR_LIT> ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) ; }


<s> bool <ISA_LIT>FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) { return false ; } unsigned CalleeFrameSize = <NUM_LIT> ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) {

unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ;


<s> if ( Amount != <NUM_LIT> ) { assert ( getStackAlign ( ) == Align ( <NUM_LIT> ) && <STR_LIT> ) ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MachineInstr * New = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Amount ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; fixStackStores ( MBB , MI , TII , <STR_LIT> ) ;


<s> } MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; assert ( MBBI -> getDesc ( ) . isReturn ( ) && <STR_LIT> ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI . getStackSize ( ) - AFI -> getCalleeSavedFrameSize ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; if ( ! FrameSize ) { restoreStatusRegister ( MF , MBB ) ; return ; } while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; int Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) { break ; } -- MBBI ; } unsigned Opcode ; if ( isUInt < <NUM_LIT> > ( FrameSize ) ) {


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool HasFP = hasFP ( MF ) ; if ( AFI -> isInterruptHandler ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( AFI -> isInterruptOrSignalHandler ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( ! HasFP ) { return ; } const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;

unsigned FrameSize = MFI . getStackSize ( ) - AFI -> getCalleeSavedFrameSize ( ) ;


<s> BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ; }


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineBasicBlock & EntryMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = EntryMBB . begin ( ) ; DebugLoc DL = EntryMBB . findDebugLoc ( MBBI ) ;

Register SPCopy = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ;


<s> Register SPCopy = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( EntryMBB , MBBI , DL , TII . get ( <STR_LIT> ) , SPCopy ) . addReg ( <STR_LIT> ) ; for ( MachineBasicBlock & MBB : MF ) { if ( ! MBB . empty ( ) && MBB . back ( ) . isReturn ( ) ) { MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SPCopy , RegState :: Kill ) ; } }


<s> assert ( MBBI -> getDesc ( ) . isReturn ( ) && <STR_LIT> ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned FrameSize = MFI . getStackSize ( ) - AFI -> getCalleeSavedFrameSize ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; if ( isHandler ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ; } if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ; if ( ! FrameSize ) { return ;


<s> bool isHandler = ( CallConv == CallingConv :: <ISA_LIT>_INTR || CallConv == CallingConv :: <ISA_LIT>_SIGNAL ) ; if ( ! hasFP ( MF ) && ! isHandler ) { return ; } MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; assert ( MBBI -> getDesc ( ) . isReturn ( ) && <STR_LIT> ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned FrameSize = MFI . getStackSize ( ) - AFI -> getCalleeSavedFrameSize ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; if ( isHandler ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ; } if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ; if ( ! FrameSize ) { return ; } while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; int Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) { break ; } -- MBBI ; } unsigned Opcode ; if ( isUInt < <NUM_LIT> > ( FrameSize ) ) { Opcode = <STR_LIT> ; } else { Opcode = <STR_LIT> ; FrameSize = - FrameSize ; } MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opcode ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( FrameSize ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ;


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; bool HasFP = hasFP ( MF ) ; if ( CallConv == CallingConv :: <ISA_LIT>_INTR ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( HasFP ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( CallConv == CallingConv :: <ISA_LIT>_INTR || CallConv == CallingConv :: <ISA_LIT>_SIGNAL ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( ! HasFP ) { return ; } const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned FrameSize = MFI . getStackSize ( ) - AFI -> getCalleeSavedFrameSize ( ) ; while ( ( MBBI != MBB . end ( ) ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) { ++ MBBI ; } BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; for ( MachineFunction :: iterator I = std :: next ( MF . begin ( ) ) , E = MF . end ( ) ;


<s> for ( const CalleeSavedInfo & CCSI : CSI ) { unsigned Reg = CCSI . getReg ( ) ; assert ( TRI -> getRegSizeInBits ( * TRI -> getMinimalPhysRegClass ( Reg ) ) == <NUM_LIT> && <STR_LIT> ) ;


<s> return MBB . erase ( MI ) ; } DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned int Opcode = MI -> getOpcode ( ) ; int Amount = TII . getFrameSize ( * MI ) ; if ( Amount != <NUM_LIT> ) { assert ( getStackAlign ( ) == Align ( <NUM_LIT> ) && <STR_LIT> ) ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MachineInstr * New = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Amount ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; fixStackStores ( MBB , MI , TII , <STR_LIT> ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; unsigned addOpcode ; if ( isUInt < <NUM_LIT> > ( Amount ) ) { addOpcode = <STR_LIT> ;


<s> BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( AFI -> isInterruptOrSignalHandler ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( ! HasFP ) { return ; } const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI . getStackSize ( ) - AFI -> getCalleeSavedFrameSize ( ) ; while ( ( MBBI != MBB . end ( ) ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) { ++ MBBI ; } BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; for ( MachineBasicBlock & MBBJ : llvm :: drop_begin ( MF ) ) { MBBJ . addLiveIn ( <STR_LIT> ) ; }


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool HasFP = hasFP ( MF ) ; if ( AFI -> isInterruptHandler ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( AFI -> isInterruptOrSignalHandler ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( ! HasFP ) {


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , <NUM_LIT> , - <NUM_LIT> ) {


<s> TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ;


<s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ;


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { CallingConv :: ID CallConv = MF . getFunction ( ) . getCallingConv ( ) ; bool isHandler = ( CallConv == CallingConv :: <ISA_LIT>_INTR || CallConv == CallingConv :: <ISA_LIT>_SIGNAL ) ; if ( ! hasFP ( MF ) && ! isHandler ) { return ; } MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; assert ( MBBI -> getDesc ( ) . isReturn ( ) && <STR_LIT> ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned FrameSize = MFI . getStackSize ( ) - AFI -> getCalleeSavedFrameSize ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; if ( isHandler ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ; } if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ; if ( ! FrameSize ) { return ; } while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; int Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) { break ; } -- MBBI ; } unsigned Opcode ; if ( isUInt < <NUM_LIT> > ( FrameSize ) ) { Opcode = <STR_LIT> ; } else { Opcode = <STR_LIT> ;


<s> MachineInstr & MI = * I ; unsigned Opcode = I -> getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) { I = NextMI ; continue ; } assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; if ( insertPushes ) { unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool SrcIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( Opcode == <STR_LIT> ) { BuildMI ( MBB , I , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( TRI . getSubReg ( SrcReg , <STR_LIT> ) , getKillRegState ( SrcIsKill ) ) ; BuildMI ( MBB , I , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( TRI . getSubReg ( SrcReg , <STR_LIT> ) , getKillRegState ( SrcIsKill ) ) ; } else { BuildMI ( MBB , I , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( SrcIsKill ) ) ; } MI . eraseFromParent ( ) ;


<s> } DebugLoc DL = MBB . findDebugLoc ( MI ) ; const MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( const CalleeSavedInfo & CCSI : CSI ) { unsigned Reg = CCSI . getReg ( ) ; assert ( TRI -> getRegSizeInBits ( * TRI -> getMinimalPhysRegClass ( Reg ) ) == <NUM_LIT> && <STR_LIT> ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) ; }


<s> MachineBasicBlock :: iterator MBBI = EntryMBB . begin ( ) ; DebugLoc DL = EntryMBB . findDebugLoc ( MBBI ) ; unsigned SPCopy = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( EntryMBB , MBBI , DL , TII . get ( <STR_LIT> ) , SPCopy ) . addReg ( <STR_LIT> ) ; for ( MachineBasicBlock & MBB : MF ) { if ( ! MBB . empty ( ) && MBB . back ( ) . isReturn ( ) ) { MBBI = MBB . getLastNonDebugInstr ( ) ;


<s> unsigned SPCopy = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( EntryMBB , MBBI , DL , TII . get ( <STR_LIT> ) , SPCopy ) . addReg ( <STR_LIT> ) ; for ( MachineBasicBlock & MBB : MF ) { if ( ! MBB . empty ( ) && MBB . back ( ) . isReturn ( ) ) { MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SPCopy , RegState :: Kill ) ;


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ; assert ( TRI -> getRegSizeInBits ( * TRI -> getMinimalPhysRegClass ( Reg ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( IsNotLiveIn ) {


<s> DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ;

bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


<s> } const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI . getStackSize ( ) - AFI -> getCalleeSavedFrameSize ( ) ; while ( ( MBBI != MBB . end ( ) ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) { ++ MBBI ; } BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; for ( MachineBasicBlock & MBBJ : llvm :: drop_begin ( MF ) ) { MBBJ . addLiveIn ( <STR_LIT> ) ; } if ( ! FrameSize ) { return ; } unsigned Opcode = ( isUInt < <NUM_LIT> > ( FrameSize ) ) ? <STR_LIT> : <STR_LIT> ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opcode ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( FrameSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;


<s> static void fixStackStores ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator StartMI , const TargetInstrInfo & TII , Register FP ) { for ( MachineInstr & MI :

llvm :: make_early_inc_range ( llvm :: make_range ( StartMI , MBB . end ( ) ) ) ) {


<s> static void fixStackStores ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator StartMI , const TargetInstrInfo & TII , Register FP ) { for ( MachineInstr & MI : llvm :: make_early_inc_range ( llvm :: make_range ( StartMI , MBB . end ( ) ) ) ) { if ( MI . isCall ( ) ) break ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) continue ; assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned STOpc = ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MI . setDesc ( TII . get ( STOpc ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( FP ) ; }


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; if ( hasReservedCallFrame ( MF ) ) { fixStackStores ( MBB , MI , TII , false ) ; return MBB . erase ( MI ) ; } DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned int Opcode = MI -> getOpcode ( ) ; int Amount = TII . getFrameSize ( * MI ) ; if ( Amount != <NUM_LIT> ) { assert ( getStackAlign ( ) == Align ( <NUM_LIT> ) && <STR_LIT> ) ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { fixStackStores ( MBB , MI , TII , true ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; unsigned addOpcode ; if ( isUInt < <NUM_LIT> > ( Amount ) ) { addOpcode = <STR_LIT> ; } else { addOpcode = <STR_LIT> ; Amount = - Amount ; } BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MachineInstr * New = BuildMI ( MBB , MI , DL , TII . get ( addOpcode ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Amount ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; } } return MBB . erase ( MI ) ;


<s> } if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ; if ( ! FrameSize ) { return ; } while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; int Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) { break ; } -- MBBI ; } unsigned Opcode ; if ( isUInt < <NUM_LIT> > ( FrameSize ) ) { Opcode = <STR_LIT> ; } else { Opcode = <STR_LIT> ; FrameSize = - FrameSize ; } MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opcode ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( FrameSize ) ;


<s> while ( ( MBBI != MBB . end ( ) ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) { ++ MBBI ; } BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; for ( MachineFunction :: iterator I = std :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) { I -> addLiveIn ( <STR_LIT> ) ; } if ( ! FrameSize ) { return ; } unsigned Opcode = ( isUInt < <NUM_LIT> > ( FrameSize ) ) ? <STR_LIT> : <STR_LIT> ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opcode ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( FrameSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


<s> } if ( AFI -> isInterruptOrSignalHandler ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( ! HasFP ) { return ; } const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI . getStackSize ( ) - AFI -> getCalleeSavedFrameSize ( ) ; while ( ( MBBI != MBB . end ( ) ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) { ++ MBBI ; } BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; for ( MachineFunction :: iterator I = std :: next ( MF . begin ( ) ) , E = MF . end ( ) ;


<s> for ( const CalleeSavedInfo & I : llvm :: reverse ( CSI ) ) { unsigned Reg = I . getReg ( ) ; bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ; assert ( TRI -> getRegSizeInBits ( * TRI -> getMinimalPhysRegClass ( Reg ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( IsNotLiveIn ) { MBB . addLiveIn ( Reg ) ; } BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; ++ CalleeFrameSize ; } <ISA_LIT>FI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ; return true ;


<s> if ( MI . isCall ( ) ) break ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) continue ;

assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ;


<s> BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MachineInstr * New = BuildMI ( MBB , MI , DL , TII . get ( addOpcode ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Amount ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; } }


<s> <ISA_LIT>DynAllocaSR ( ) : MachineFunctionPass ( ID ) {


<s> return new <ISA_LIT>DynAllocaSR ( ) ;


<s> FunctionPass * create<ISA_LIT>DynAllocaSRPass ( ) { return new <ISA_LIT>DynAllocaSR ( ) ;


<s> } DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned int Opcode = MI -> getOpcode ( ) ; int Amount = TII . getFrameSize ( * MI ) ; if ( Amount != <NUM_LIT> ) { assert ( getStackAlign ( ) == Align ( <NUM_LIT> ) && <STR_LIT> ) ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MachineInstr * New = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Amount ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; fixStackStores ( MBB , MI , TII , <STR_LIT> ) ; } else {

assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ;


<s> BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MachineInstr * New = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Amount ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; fixStackStores ( MBB , MI , TII , <STR_LIT> ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; unsigned addOpcode ; if ( isUInt < <NUM_LIT> > ( Amount ) ) { addOpcode = <STR_LIT> ; } else { addOpcode = <STR_LIT> ; Amount = - Amount ; }


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI . getStackSize ( ) - AFI -> getCalleeSavedFrameSize ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; if ( AFI -> isInterruptOrSignalHandler ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ; } if ( ! FrameSize ) { return ; } while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; int Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) { break ; } -- MBBI ; } unsigned Opcode ; if ( isUInt < <NUM_LIT> > ( FrameSize ) ) { Opcode = <STR_LIT> ; } else { Opcode = <STR_LIT> ;


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool HasFP = hasFP ( MF ) ; if ( AFI -> isInterruptHandler ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( AFI -> isInterruptOrSignalHandler ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


<s> } assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned STOpc = ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MI . setDesc ( TII . get ( STOpc ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( FP ) ;


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const {

const <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;


<s> return ( FuncInfo -> getHasSpills ( ) || FuncInfo -> getHasAllocas ( ) || FuncInfo -> getHasStackArgs ( ) ) ;


<s> if ( CSI . empty ( ) ) { return false ; } DebugLoc DL = MBB . findDebugLoc ( MI ) ; const MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( const CalleeSavedInfo & CCSI : CSI ) { unsigned Reg = CCSI . getReg ( ) ; assert ( TRI -> getRegSizeInBits ( * TRI -> getMinimalPhysRegClass ( Reg ) ) == <NUM_LIT> && <STR_LIT> ) ;


<s> if ( ! MBB . empty ( ) && MBB . back ( ) . isReturn ( ) ) { MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SPCopy , RegState :: Kill ) ; } } return true ;


<s> <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ; assert ( TRI -> getRegSizeInBits ( * TRI -> getMinimalPhysRegClass ( Reg ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( IsNotLiveIn ) { MBB . addLiveIn ( Reg ) ;


<s> for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ; assert ( TRI -> getRegSizeInBits ( * TRI -> getMinimalPhysRegClass ( Reg ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( IsNotLiveIn ) { MBB . addLiveIn ( Reg ) ; }

BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


<s> O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; break ; case <STR_LIT> : case <STR_LIT> : O << <STR_LIT> ; if ( Opcode == <STR_LIT> ) O << '-' ; printOperand ( MI , <NUM_LIT> , O ) ; if ( Opcode == <STR_LIT> ) O << '+' ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; break ; default : if ( ! printAliasInstr ( MI , O ) ) printInstruction ( MI , Address , O ) ; printAnnotation ( O , Annot ) ; break ;


<s> const MCOperandInfo & MOI = this -> MII . get ( MI -> getOpcode ( ) ) . OpInfo [ OpNo ] ; if ( Op . isReg ( ) ) { bool isPtrReg = ( MOI . RegClass == <STR_LIT> ) || ( MOI . RegClass == <STR_LIT> ) || ( MOI . RegClass == <STR_LIT> ) ; if ( isPtrReg ) { O << getRegisterName ( Op . getReg ( ) , <STR_LIT> ) ; } else {

O << getPrettyRegisterName ( Op . getReg ( ) , MRI ) ;


<s> const MCOperandInfo & MOI = this -> MII . get ( MI -> getOpcode ( ) ) . OpInfo [ OpNo ] ; if ( Op . isReg ( ) ) { bool isPtrReg = ( MOI . RegClass == <STR_LIT> ) || ( MOI . RegClass == <STR_LIT> ) || ( MOI . RegClass == <STR_LIT> ) ; if ( isPtrReg ) { O << getRegisterName ( Op . getReg ( ) , <STR_LIT> ) ; } else { O << getPrettyRegisterName ( Op . getReg ( ) , MRI ) ; } } else if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ;


<s> if ( Op . isReg ( ) ) { bool isPtrReg = ( MOI . RegClass == <STR_LIT> ) || ( MOI . RegClass == <STR_LIT> ) || ( MOI . RegClass == <STR_LIT> ) ; if ( isPtrReg ) { O << getRegisterName ( Op . getReg ( ) , <STR_LIT> ) ; } else { O << getPrettyRegisterName ( Op . getReg ( ) , MRI ) ; } } else if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ;


<s> if ( Op . isReg ( ) ) { bool isPtrReg = ( MOI . RegClass == <STR_LIT> ) || ( MOI . RegClass == <STR_LIT> ) || ( MOI . RegClass == <STR_LIT> ) ; if ( isPtrReg ) {

O << getRegisterName ( Op . getReg ( ) , <STR_LIT> ) ;


<s> if ( Opcode == <STR_LIT> ) O << '+' ; break ; case <STR_LIT> : O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; break ; case <STR_LIT> : case <STR_LIT> : O << <STR_LIT> ; if ( Opcode == <STR_LIT> ) O << '-' ; printOperand ( MI , <NUM_LIT> , O ) ; if ( Opcode == <STR_LIT> ) O << '+' ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; break ; default :

if ( ! printAliasInstr ( MI , O ) ) printInstruction ( MI , O ) ;


<s> void <ISA_LIT>InstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNo ) ; const MCOperandInfo & MOI = this -> MII . get ( MI -> getOpcode ( ) ) . OpInfo [ OpNo ] ; if ( Op . isReg ( ) ) {

bool isPtrReg = ( MOI . RegClass == <STR_LIT> ) || ( MOI . RegClass == <STR_LIT> ) || ( MOI . RegClass == <STR_LIT> ) ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> unsigned RegLoNum = MRI . getSubReg ( RegNum , <STR_LIT> ) ; RegNum = ( RegLoNum != <STR_LIT> ) ? RegLoNum : RegNum ;


<s> unsigned Opcode = MI -> getOpcode ( ) ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; if ( Opcode == <STR_LIT> ) O << '-' ; printOperand ( MI , <NUM_LIT> , O ) ; if ( Opcode == <STR_LIT> ) O << '+' ; break ; case <STR_LIT> : O << <STR_LIT> ;


<s> O << <STR_LIT> ; if ( Opcode == <STR_LIT> ) O << '-' ; printOperand ( MI , <NUM_LIT> , O ) ; if ( Opcode == <STR_LIT> ) O << '+' ; break ; case <STR_LIT> : O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; break ; case <STR_LIT> : case <STR_LIT> : O << <STR_LIT> ; if ( Opcode == <STR_LIT> ) O << '-' ; printOperand ( MI , <NUM_LIT> , O ) ;


<s> const MCOperand & OffsetOp = MI -> getOperand ( OpNo + <NUM_LIT> ) ; printOperand ( MI , OpNo , O ) ; if ( OffsetOp . isImm ( ) ) { int64_t Offset = OffsetOp . getImm ( ) ; if ( Offset >= <NUM_LIT> ) O << '+' ; O << Offset ; } else if ( OffsetOp . isExpr ( ) ) { O << * OffsetOp . getExpr ( ) ;


<s> if ( Op . isReg ( ) ) { bool isPtrReg = ( MOI . RegClass == <STR_LIT> ) || ( MOI . RegClass == <STR_LIT> ) || ( MOI . RegClass == <STR_LIT> ) ; if ( isPtrReg ) { O << getRegisterName ( Op . getReg ( ) , <STR_LIT> ) ; } else { O << getPrettyRegisterName ( Op . getReg ( ) , MRI ) ; } } else if ( Op . isImm ( ) ) { O << formatImm ( Op . getImm ( ) ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ;


<s> if ( OpNo >= MI -> size ( ) ) { O << <STR_LIT> ; return ; } const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isImm ( ) ) { int64_t Imm = Op . getImm ( ) ; O << '.' ; if ( Imm >= <NUM_LIT> ) O << '+' ; O << Imm ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; O << * Op . getExpr ( ) ; }


<s> BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { unsigned DestLo , DestHi , SrcLo , SrcHi ; TRI . splitReg ( DestReg , DestLo , DestHi ) ; TRI . splitReg ( SrcReg , SrcLo , SrcHi ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestLo ) . addReg ( SrcLo , getKillRegState ( KillSrc ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestHi ) . addReg ( SrcHi , getKillRegState ( KillSrc ) ) ; } } else { if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; } else if ( SrcReg == <STR_LIT> && <STR_LIT> . contains ( DestReg ) ) { Opc = <STR_LIT> ; } else if ( DestReg == <STR_LIT> && <STR_LIT> . contains ( SrcReg ) ) { Opc = <STR_LIT> ; } else {


<s> const MCInstrDesc & Desc = get ( Opcode ) ; return Desc . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; return TII . getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; }


<s> case TargetOpcode :: INLINEASM : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ;

const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> DL = MI -> getDebugLoc ( ) ; } MachineFunction & MF = * MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;

MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ;


<s> } const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; unsigned Opcode = <NUM_LIT> ; if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) { Opcode = <STR_LIT> ; } else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) { Opcode = <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } BuildMI ( MBB , MI , DL , get ( Opcode ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ;


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const DebugLoc & DL , MCRegister DestReg , MCRegister SrcReg , bool KillSrc ) const { const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo & TRI = * STI . getRegisterInfo ( ) ; unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { if ( STI . hasMOVW ( ) ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { Register DestLo , DestHi , SrcLo , SrcHi ; TRI . splitReg ( DestReg , DestLo , DestHi ) ; TRI . splitReg ( SrcReg , SrcLo , SrcHi ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestLo ) . addReg ( SrcLo , getKillRegState ( KillSrc ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestHi ) . addReg ( SrcHi , getKillRegState ( KillSrc ) ) ; } } else { if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; } else if ( SrcReg == <STR_LIT> && <STR_LIT> . contains ( DestReg ) ) { Opc = <STR_LIT> ; } else if ( DestReg == <STR_LIT> && <STR_LIT> . contains ( SrcReg ) ) { Opc = <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ;


<s> case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;

const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ;


<s> case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; return TII . getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } }


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , Register DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) { DL = MI -> getDebugLoc ( ) ; } MachineFunction & MF = * MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; unsigned Opcode = <NUM_LIT> ; if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) { Opcode = <STR_LIT> ;

} else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) {


<s> DL = MI -> getDebugLoc ( ) ; } const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; unsigned Opcode = <NUM_LIT> ; if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) {


<s> } else if ( DestReg == <STR_LIT> && <STR_LIT> . contains ( SrcReg ) ) { Opc = <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; }

BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF -> getTarget ( ) ) ; const TargetInstrInfo & TII = * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ; return TII . getInlineAsmLength ( MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; }


<s> const MCInstrDesc & Desc = get ( Opcode ) ; return Desc . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF -> getTarget ( ) ) ; const TargetInstrInfo & TII = * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ;

return TII . getInlineAsmLength ( MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ;


<s> if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; <STR_LIT> CC = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; BuildMI ( & MBB , DL , getBrCond ( CC ) ) . addMBB ( TBB ) ;


<s> BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; <STR_LIT> CC = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; BuildMI ( & MBB , DL , getBrCond ( CC ) ) . addMBB ( TBB ) ;


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : { if ( ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; } default : break ; } return <NUM_LIT> ;


<s> case <STR_LIT> : { if ( ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; } default : break ; }


<s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : { if ( ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; } default : break ; }


<s> if ( MI != MBB . end ( ) ) { DL = MI -> getDebugLoc ( ) ; } MachineFunction & MF = * MBB . getParent ( ) ; const MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ;


<s> } MachineFunction & MF = * MBB . getParent ( ) ; const MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; unsigned Opcode = <NUM_LIT> ;


<s> } const MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; unsigned Opcode = <NUM_LIT> ; if ( RC -> hasType ( <STR_LIT> ) ) { Opcode = <STR_LIT> ; } else if ( RC -> hasType ( <STR_LIT> ) ) { Opcode = <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; }

BuildMI ( MBB , MI , DL , get ( Opcode ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ;


<s> DL = MI -> getDebugLoc ( ) ; } const MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; unsigned Opcode = <NUM_LIT> ; if ( RC -> hasType ( <STR_LIT> ) ) { Opcode = <STR_LIT> ; } else if ( RC -> hasType ( <STR_LIT> ) ) { Opcode = <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ;


<s> } else { Register DestLo , DestHi , SrcLo , SrcHi ; TRI . splitReg ( DestReg , DestLo , DestHi ) ; TRI . splitReg ( SrcReg , SrcLo , SrcHi ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestLo ) . addReg ( SrcLo , getKillRegState ( KillSrc ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestHi ) . addReg ( SrcHi , getKillRegState ( KillSrc ) ) ; } } else { if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; } else if ( SrcReg == <STR_LIT> && <STR_LIT> . contains ( DestReg ) ) { Opc = <STR_LIT> ;

} else if ( DestReg == <STR_LIT> && <STR_LIT> . contains ( SrcReg ) ) {


<s> unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { if ( STI . hasMOVW ( ) ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { unsigned DestLo , DestHi , SrcLo , SrcHi ; TRI . splitReg ( DestReg , DestLo , DestHi ) ; TRI . splitReg ( SrcReg , SrcLo , SrcHi ) ;

BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestLo ) . addReg ( SrcLo , getKillRegState ( KillSrc ) ) ;


<s> unsigned <ISA_LIT>InstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const { assert ( ! BytesAdded && <STR_LIT> ) ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ;


<s> assert ( ! BytesAdded && <STR_LIT> ) ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; }


<s> } if ( I -> getOpcode ( ) != <STR_LIT> && getCondFromBranchOpc ( I -> getOpcode ( ) ) == <STR_LIT> ) { break ; } I -> eraseFromParent ( ) ; I = MBB . end ( ) ;


<s> if ( I -> isDebugValue ( ) ) { continue ; } if ( I -> getOpcode ( ) != <STR_LIT> && getCondFromBranchOpc ( I -> getOpcode ( ) ) == <STR_LIT> ) { break ;


<s> TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) { std :: next ( I ) -> eraseFromParent ( ) ; } Cond . clear ( ) ; FBB = <NUM_LIT> ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; UnCondBrIter = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = getCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) { return true ; } if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = getOppositeCondition ( BranchCode ) ; unsigned JNCC = getBrCond ( BranchCode ) . getOpcode ( ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) { return true ; } <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ;


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ;

} else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) {


<s> default : { const MCInstrDesc & Desc = get ( Opcode ) ; return Desc . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF -> getTarget ( ) ) ; const TargetInstrInfo & TII = * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ;


<s> const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF -> getTarget ( ) ) ; const TargetInstrInfo & TII = * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ; return TII . getInlineAsmLength ( MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; }


<s> } unsigned Count = <NUM_LIT> ; <STR_LIT> CC = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; BuildMI ( & MBB , DL , getBrCond ( CC ) ) . addMBB ( TBB ) ; ++ Count ; if ( FBB ) { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; ++ Count ;


<s> if ( RC -> hasType ( <STR_LIT> ) ) { Opcode = <STR_LIT> ; } else if ( RC -> hasType ( <STR_LIT> ) ) { Opcode = <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; }

BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> MachineBasicBlock :: iterator I = MBB . end ( ) ; unsigned Count = <NUM_LIT> ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) { continue ; } if ( I -> getOpcode ( ) != <STR_LIT> && getCondFromBranchOpc ( I -> getOpcode ( ) ) == <STR_LIT> ) { break ; } I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ;


<s> bool <ISA_LIT>InstrInfo :: ReverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; <STR_LIT> CC = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; Cond [ <NUM_LIT> ] . setImm ( getOppositeCondition ( CC ) ) ;


<s> assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; <STR_LIT> CC = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ;

Cond [ <NUM_LIT> ] . setImm ( getOppositeCondition ( CC ) ) ;


<s> if ( MI != MBB . end ( ) ) { DL = MI -> getDebugLoc ( ) ; } const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; unsigned Opcode = <NUM_LIT> ; if ( RC -> hasType ( <STR_LIT> ) ) { Opcode = <STR_LIT> ;

} else if ( RC -> hasType ( <STR_LIT> ) ) {


<s> } if ( I -> getOpcode ( ) != <STR_LIT> && getCondFromBranchOpc ( I -> getOpcode ( ) ) == <STR_LIT> ) { break ; } if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ;


<s> UnCondBrIter = I ; if ( ! AllowModify ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) { std :: next ( I ) -> eraseFromParent ( ) ; } Cond . clear ( ) ; FBB = nullptr ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = nullptr ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; UnCondBrIter = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = getCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) { return true ; } if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = getOppositeCondition ( BranchCode ) ; unsigned JNCC = getBrCond ( BranchCode ) . getOpcode ( ) ; MachineBasicBlock :: iterator OldInst = I ;

BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ;


<s> continue ; } while ( std :: next ( I ) != MBB . end ( ) ) { std :: next ( I ) -> eraseFromParent ( ) ; } Cond . clear ( ) ; FBB = nullptr ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = nullptr ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; UnCondBrIter = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = getCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) { return true ; } if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = getOppositeCondition ( BranchCode ) ; unsigned JNCC = getBrCond ( BranchCode ) . getOpcode ( ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ;


<s> BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( & NewDestBB ) ;


<s> } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF -> getTarget ( ) ) ; const TargetInstrInfo & TII = * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ; return TII . getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } }


<s> bool <ISA_LIT>InstrInfo :: isBranchOffsetInRange ( unsigned BranchOp , int64_t BrOffset ) const { switch ( BranchOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> :

assert ( BrOffset >= <NUM_LIT> && <STR_LIT> ) ;


<s> BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( & NewDestBB ) ; return ;


<s> void <ISA_LIT>InstrInfo :: insertIndirectBranch ( MachineBasicBlock & MBB , MachineBasicBlock & NewDestBB , MachineBasicBlock & RestoreBB , const DebugLoc & DL , int64_t BrOffset , RegScavenger * RS ) const { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( & NewDestBB ) ;


<s> BranchCode = getOppositeCondition ( BranchCode ) ; unsigned JNCC = getBrCond ( BranchCode ) . getOpcode ( ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) {


<s> } <STR_LIT> BranchCode = getCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) { return true ; } if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = getOppositeCondition ( BranchCode ) ; unsigned JNCC = getBrCond ( BranchCode ) . getOpcode ( ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) { return true ; } <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; if ( OldBranchCode == BranchCode ) { continue ; } return true ; }


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ) {


<s> const <ISA_LIT>RegisterInfo & TRI = * STI . getRegisterInfo ( ) ; unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { if ( STI . hasMOVW ( ) && <STR_LIT> . contains ( DestReg , SrcReg ) ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { Register DestLo , DestHi , SrcLo , SrcHi ; TRI . splitReg ( DestReg , DestLo , DestHi ) ; TRI . splitReg ( SrcReg , SrcLo , SrcHi ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestLo ) . addReg ( SrcLo , getKillRegState ( KillSrc ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestHi ) . addReg ( SrcHi , getKillRegState ( KillSrc ) ) ; } } else {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; case <STR_LIT> :


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; case <STR_LIT> : case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; }


<s> return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> :


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> unsigned <ISA_LIT>InstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { const MCInstrDesc & Desc = get ( Opcode ) ; return Desc . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ;

return TII . getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ;