<s> unsigned <ISA_LIT>InstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { const MCInstrDesc & Desc = get ( Opcode ) ; return Desc . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : {

const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


<s> switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> if ( BytesAdded ) * BytesAdded = <NUM_LIT> ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; auto & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( MI ) ; return <NUM_LIT> ;


<s> auto & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( & NewDestBB ) ;


<s> case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : return isIntN ( <NUM_LIT> , BrOffset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>InstrInfo :: isBranchOffsetInRange ( unsigned BranchOp , int64_t BrOffset ) const { switch ( BranchOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : return isIntN ( <NUM_LIT> , BrOffset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; }


<s> case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; }


if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) {


<s> if ( MI != MBB . end ( ) ) { DL = MI -> getDebugLoc ( ) ; } MachineFunction & MF = * MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlign ( FrameIndex ) ) ; unsigned Opcode = <NUM_LIT> ; if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) { Opcode = <STR_LIT> ; } else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) { Opcode = <STR_LIT> ; } else {


<s> unsigned <ISA_LIT>InstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { if ( BytesRemoved ) * BytesRemoved = <NUM_LIT> ; MachineBasicBlock :: iterator I = MBB . end ( ) ; unsigned Count = <NUM_LIT> ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugInstr ( ) ) {


<s> continue ; } if ( I -> getOpcode ( ) != <STR_LIT> && getCondFromBranchOpc ( I -> getOpcode ( ) ) == <STR_LIT> ) { break ; } if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ;


<s> <STR_LIT> CC = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; Cond [ <NUM_LIT> ] . setImm ( getOppositeCondition ( CC ) ) ;


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , Register SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; AFI -> setHasSpills ( true ) ; DebugLoc DL ; if ( MI != MBB . end ( ) ) { DL = MI -> getDebugLoc ( ) ; } const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlign ( FrameIndex ) ) ; unsigned Opcode = <NUM_LIT> ; if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) { Opcode = <STR_LIT> ; } else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) { Opcode = <STR_LIT> ;


<s> Constant * Fn = F . getParent ( ) -> getOrInsertFunction ( SymName , FnType ) ; Value * FunctionName = CreateStringPtr ( BB , F . getName ( ) ) ; Value * Args [ ] = { FunctionName , ConstantInt :: get ( I16 , F . arg_size ( ) ) } ; CallInst :: Create ( Fn , Args , <STR_LIT> , & BB ) ;


<s> Value * FunctionName = CreateStringPtr ( BB , F . getName ( ) ) ; Value * Args [ ] = { FunctionName , ConstantInt :: get ( I16 , F . arg_size ( ) ) } ; CallInst :: Create ( Fn , Args , <STR_LIT> , & BB ) ;


<s> <ISA_LIT>InstrumentFunctions ( ) : FunctionPass ( ID ) {


<s> Type * I8 = Type :: getInt8Ty ( Ctx ) ; FunctionType * FnType = FunctionType :: get ( Type :: getVoidTy ( Ctx ) , { Type :: getInt8PtrTy ( Ctx ) , I8 , Arg . getType ( ) } , false ) ; Constant * Fn = F . getParent ( ) -> getOrInsertFunction ( GetArgumentSymbolName ( Arg ) , FnType ) ; Value * ArgName = CreateStringPtr ( BB , Arg . getName ( ) ) ; Value * Args [ ] = { ArgName , ConstantInt :: get ( I8 , Arg . getArgNo ( ) ) , & Arg } ; CallInst :: Create ( Fn , Args , <STR_LIT> , & BB ) ;


<s> static void BuildBeginSignature ( BasicBlock & BB , Function & F ) { return BuildSignatureCall ( <STR_LIT> , BB , F ) ;


<s> return BuildSignatureCall ( <STR_LIT> , BB , F ) ;


<s> static void BuildEntryBlock ( Function & F ) { BasicBlock & EntryBlock = F . getEntryBlock ( ) ; BasicBlock * BB = BasicBlock :: Create ( F . getContext ( ) , <STR_LIT> , & F , & EntryBlock ) ; BuildSignature ( * BB , F ) ;

BranchInst :: Create ( & EntryBlock , BB ) ;


<s> Function & F = * I . getParent ( ) -> getParent ( ) ; LLVMContext & Ctx = F . getContext ( ) ; if ( auto * Ret = dyn_cast < ReturnInst > ( & I ) ) { Value * RetVal = Ret -> getReturnValue ( ) ; assert ( RetVal && <STR_LIT> ) ; FunctionType * FnType = FunctionType :: get ( Type :: getVoidTy ( Ctx ) , { RetVal -> getType ( ) } , false ) ; Constant * Fn = F . getParent ( ) -> getOrInsertFunction ( GetReturnSymbolName ( * RetVal ) , FnType ) ;

CallInst :: Create ( Fn , { RetVal } , <STR_LIT> , & I ) ;


<s> static void BuildExitHooks ( Function & F ) { for ( BasicBlock & BB : F ) { auto BBI = BB . begin ( ) , E = BB . end ( ) ; while ( BBI != E ) { auto NBBI = std :: next ( BBI ) ; BuildExitHook ( * BBI ) ; BBI = NBBI ;


<s> BuildBeginSignature ( BB , F ) ; for ( Argument & Arg : F . args ( ) ) {


<s> static void BuildSignature ( BasicBlock & BB , Function & F ) { BuildBeginSignature ( BB , F ) ; for ( Argument & Arg : F . args ( ) ) { BuildArgument ( BB , Arg ) ;


<s> static void BuildSignatureCall ( StringRef SymName , BasicBlock & BB , Function & F ) { LLVMContext & Ctx = F . getContext ( ) ; IntegerType * I16 = Type :: getInt16Ty ( Ctx ) ; FunctionType * FnType = FunctionType :: get ( Type :: getVoidTy ( Ctx ) , { Type :: getInt8PtrTy ( Ctx ) , I16 } , false ) ;

Constant * Fn = F . getParent ( ) -> getOrInsertFunction ( SymName , FnType ) ;


<s> Constant * Fn = F . getParent ( ) -> getOrInsertFunction ( SymName , FnType ) ; Value * FunctionName = CreateStringPtr ( BB , F . getName ( ) ) ; Value * Args [ ] = { FunctionName , ConstantInt :: get ( I16 , F . getArgumentList ( ) . size ( ) ) } ;

CallInst :: Create ( Fn , Args , <STR_LIT> , & BB ) ;


<s> FunctionPass * create<ISA_LIT>InstrumentFunctionsPass ( ) { return new <ISA_LIT>InstrumentFunctions ( ) ;


<s> Constant * ConstantStr = <STR_LIT> ( Ctx , Str ) ; GlobalVariable * GlobalStr = new GlobalVariable ( * BB . getParent ( ) -> getParent ( ) , ConstantStr -> getType ( ) , true , GlobalValue :: PrivateLinkage , ConstantStr ) ; return GetElementPtrInst :: CreateInBounds ( GlobalStr , { ConstantInt :: get ( I8 , <NUM_LIT> ) , ConstantInt :: get ( I8 , <NUM_LIT> ) } , <STR_LIT> , & BB ) ;


<s> return ( <STR_LIT> + <STR_LIT> + GetTypeName ( * Arg . getType ( ) ) ) . str ( ) ;


<s> StringRef getPassName ( ) const override { return <ISA_LIT>_INSTRUMENT_FUNCTIONS_NAME ;


<s> return ( <STR_LIT> + <STR_LIT> + GetTypeName ( * Val . getType ( ) ) ) . str ( ) ;


<s> if ( auto * IntTy = dyn_cast < IntegerType > ( & Ty ) ) { return std :: string ( <STR_LIT> ) + std :: to_string ( IntTy -> getBitWidth ( ) ) ; }


<s> static std :: string GetTypeName ( Type & Ty ) { if ( auto * IntTy = dyn_cast < IntegerType > ( & Ty ) ) { return std :: string ( <STR_LIT> ) + std :: to_string ( IntTy -> getBitWidth ( ) ) ;


<s> BuildEntryBlock ( F ) ; BuildExitHooks ( F ) ; } return true ;


<s> static bool ShouldInstrument ( Function & F ) {

return ! F . getReturnType ( ) -> isVoidTy ( ) ;


<s> unsigned Reg ; bool CanHandleRegImmOpt = ImmNode && ImmNode -> getAPIntValue ( ) . ult ( <NUM_LIT> ) ; if ( CopyFromRegOp -> getOpcode ( ) == <STR_LIT> ) { RegisterSDNode * RegNode = cast < RegisterSDNode > ( CopyFromRegOp -> getOperand ( <NUM_LIT> ) ) ; Reg = RegNode -> getReg ( ) ; CanHandleRegImmOpt &= ( Register :: isVirtualRegister ( Reg ) || <STR_LIT> . contains ( Reg ) ) ; } else { CanHandleRegImmOpt = false ; } if ( CanHandleRegImmOpt ) { SDValue Base , Disp ; if ( RI . getRegClass ( Reg ) != & <STR_LIT> ) { SDLoc dl ( CopyFromRegOp ) ; Register VReg = RI . createVirtualRegister ( & <STR_LIT> ) ; SDValue CopyToReg = CurDAG -> getCopyToReg ( CopyFromRegOp , dl , VReg , CopyFromRegOp ) ; SDValue NewCopyFromRegOp = CurDAG -> getCopyFromReg ( CopyToReg , dl , VReg , TL . getPointerTy ( DL ) ) ; Base = NewCopyFromRegOp ; } else {


<s> if ( Op -> getOpcode ( ) == <STR_LIT> ) { SDValue Base , Disp ; if ( SelectAddr ( Op . getNode ( ) , Op , Base , Disp ) ) { OutOps . push_back ( Base ) ; OutOps . push_back ( Disp ) ; return false ; } return true ; } if ( Op -> getOpcode ( ) == <STR_LIT> || Op -> getOpcode ( ) == <STR_LIT> ) { SDValue CopyFromRegOp = Op -> getOperand ( <NUM_LIT> ) ; SDValue ImmOp = Op -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * ImmNode = dyn_cast < ConstantSDNode > ( ImmOp ) ; unsigned Reg ; bool CanHandleRegImmOpt = ImmNode && ImmNode -> getAPIntValue ( ) . ult ( <NUM_LIT> ) ; if ( CopyFromRegOp -> getOpcode ( ) == <STR_LIT> ) { RegisterSDNode * RegNode = cast < RegisterSDNode > ( CopyFromRegOp -> getOperand ( <NUM_LIT> ) ) ; Reg = RegNode -> getReg ( ) ; CanHandleRegImmOpt &= ( Register :: isVirtualRegister ( Reg ) || <STR_LIT> . contains ( Reg ) ) ; } else { CanHandleRegImmOpt = false ; } if ( CanHandleRegImmOpt ) { SDValue Base , Disp ; if ( RI . getRegClass ( Reg ) != & <STR_LIT> ) { SDLoc dl ( CopyFromRegOp ) ; Register VReg = RI . createVirtualRegister ( & <STR_LIT> ) ; SDValue CopyToReg = CurDAG -> getCopyToReg ( CopyFromRegOp , dl , VReg , CopyFromRegOp ) ; SDValue NewCopyFromRegOp = CurDAG -> getCopyFromReg ( CopyToReg , dl , VReg , TL . getPointerTy ( DL ) ) ; Base = NewCopyFromRegOp ; } else { Base = CopyFromRegOp ; } if ( ImmNode -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) { Disp = CurDAG -> getTargetConstant ( ImmNode -> getAPIntValue ( ) . getZExtValue ( ) , dl , <STR_LIT> ) ; } else { Disp = ImmOp ; } OutOps . push_back ( Base ) ; OutOps . push_back ( Disp ) ;


<s> } if ( Op -> getOpcode ( ) == <STR_LIT> || Op -> getOpcode ( ) == <STR_LIT> ) { SDValue CopyFromRegOp = Op -> getOperand ( <NUM_LIT> ) ; SDValue ImmOp = Op -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * ImmNode = dyn_cast < ConstantSDNode > ( ImmOp ) ; unsigned Reg ; bool CanHandleRegImmOpt = true ; CanHandleRegImmOpt &= ImmNode != <NUM_LIT> ; CanHandleRegImmOpt &= ImmNode -> getAPIntValue ( ) . getZExtValue ( ) < <NUM_LIT> ; if ( CopyFromRegOp -> getOpcode ( ) == <STR_LIT> ) { RegisterSDNode * RegNode = cast < RegisterSDNode > ( CopyFromRegOp -> getOperand ( <NUM_LIT> ) ) ; Reg = RegNode -> getReg ( ) ; CanHandleRegImmOpt &= ( Register :: isVirtualRegister ( Reg ) || <STR_LIT> . contains ( Reg ) ) ; } else { CanHandleRegImmOpt = false ; } if ( CanHandleRegImmOpt ) { SDValue Base , Disp ; if ( RI . getRegClass ( Reg ) != & <STR_LIT> ) { SDLoc dl ( CopyFromRegOp ) ; unsigned VReg = RI . createVirtualRegister ( & <STR_LIT> ) ; SDValue CopyToReg = CurDAG -> getCopyToReg ( CopyFromRegOp , dl , VReg , CopyFromRegOp ) ; SDValue NewCopyFromRegOp = CurDAG -> getCopyFromReg ( CopyToReg , dl , VReg , TL . getPointerTy ( DL ) ) ; Base = NewCopyFromRegOp ; } else {


<s> case <STR_LIT> : if ( Offs == <NUM_LIT> ) Opcode = Bank > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( Offs == <NUM_LIT> ) Opcode = Bank > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; break ; default : break ; } return Opcode ;


<s> case <STR_LIT> : return select < <STR_LIT> > ( N ) ; case <STR_LIT> : return select < <STR_LIT> > ( N ) ; case <STR_LIT> : case <STR_LIT> : return selectMultiplication ( N ) ; case <STR_LIT> : return select < <STR_LIT> > ( N ) ;


<s> return selectMultiplication ( N ) ; case <STR_LIT> : return select < <STR_LIT> > ( N ) ; case <STR_LIT> : return select < <STR_LIT> > ( N ) ; case <STR_LIT> : return select < <STR_LIT> > ( N ) ; default :


<s> SDValue Base , Disp ; if ( SelectAddr ( Op . getNode ( ) , Op , Base , Disp ) ) { OutOps . push_back ( Base ) ; OutOps . push_back ( Disp ) ; return false ; } return true ; } if ( Op -> getOpcode ( ) == <STR_LIT> || Op -> getOpcode ( ) == <STR_LIT> ) { SDValue CopyFromRegOp = Op -> getOperand ( <NUM_LIT> ) ; SDValue ImmOp = Op -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * ImmNode = dyn_cast < ConstantSDNode > ( ImmOp ) ; unsigned Reg ; bool CanHandleRegImmOpt = true ; CanHandleRegImmOpt &= ImmNode != <NUM_LIT> ; CanHandleRegImmOpt &= ImmNode -> getAPIntValue ( ) . getZExtValue ( ) < <NUM_LIT> ; if ( CopyFromRegOp -> getOpcode ( ) == <STR_LIT> ) { RegisterSDNode * RegNode = cast < RegisterSDNode > ( CopyFromRegOp -> getOperand ( <NUM_LIT> ) ) ; Reg = RegNode -> getReg ( ) ; CanHandleRegImmOpt &= ( Register :: isVirtualRegister ( Reg ) || <STR_LIT> . contains ( Reg ) ) ; } else { CanHandleRegImmOpt = false ; } if ( CanHandleRegImmOpt ) { SDValue Base , Disp ; if ( RI . getRegClass ( Reg ) != & <STR_LIT> ) { SDLoc dl ( CopyFromRegOp ) ; Register VReg = RI . createVirtualRegister ( & <STR_LIT> ) ; SDValue CopyToReg = CurDAG -> getCopyToReg ( CopyFromRegOp , dl , VReg , CopyFromRegOp ) ; SDValue NewCopyFromRegOp = CurDAG -> getCopyFromReg ( CopyToReg , dl , VReg , TL . getPointerTy ( DL ) ) ; Base = NewCopyFromRegOp ; } else { Base = CopyFromRegOp ; } if ( ImmNode -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) {

Disp = CurDAG -> getTargetConstant ( ImmNode -> getAPIntValue ( ) . getZExtValue ( ) , dl , <STR_LIT> ) ;


<s> DEBUG ( errs ( ) << <STR_LIT> ; N -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ;


<s> void <ISA_LIT>DAGToDAGISel :: Select ( SDNode * N ) { DEBUG ( errs ( ) << <STR_LIT> ; N -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ;


<s> void <ISA_LIT>DAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) { DEBUG ( errs ( ) << <STR_LIT> ; N -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; N -> setNodeId ( - <NUM_LIT> ) ; return ;


<s> <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) , Subtarget ( nullptr ) {


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

return SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> N -> setNodeId ( - <NUM_LIT> ) ; return ; } if ( trySelect ( N ) ) return ;


<s> LLVM_DEBUG ( errs ( ) << <STR_LIT> ; N -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; N -> setNodeId ( - <NUM_LIT> ) ;


<s> } if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , PtrVT ) ; Disp = CurDAG -> getTargetConstant ( RHSC , dl , <STR_LIT> ) ; return true ; } MVT VT = cast < MemSDNode > ( Op ) -> getMemoryVT ( ) . getSimpleVT ( ) ; if ( isUInt < <NUM_LIT> > ( RHSC ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; Disp = CurDAG -> getTargetConstant ( RHSC , dl , <STR_LIT> ) ; return true ; } }


<s> return false ; } Opcode = ( isPre ) ? <STR_LIT> : <STR_LIT> ; break ; } case <STR_LIT> : { if ( ( ! isPre && Offs != <NUM_LIT> ) || ( isPre && Offs != - <NUM_LIT> ) ) { return false ; } Opcode = ( isPre ) ? <STR_LIT> : <STR_LIT> ; break ; } default : return false ; } SDNode * ResNode = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , VT , PtrVT , <STR_LIT> , LD -> getBasePtr ( ) , LD -> getChain ( ) ) ; ReplaceUses ( N , ResNode ) ; CurDAG -> RemoveDeadNode ( N ) ;


<s> bool isPre = ( AM == <STR_LIT> ) ; int Offs = cast < ConstantSDNode > ( LD -> getOffset ( ) ) -> getSExtValue ( ) ; switch ( VT . SimpleTy ) { case <STR_LIT> : { if ( ( ! isPre && Offs != <NUM_LIT> ) || ( isPre && Offs != - <NUM_LIT> ) ) { return false ; } Opcode = ( isPre ) ? <STR_LIT> : <STR_LIT> ; break ; } case <STR_LIT> : { if ( ( ! isPre && Offs != <NUM_LIT> ) || ( isPre && Offs != - <NUM_LIT> ) ) { return false ; } Opcode = ( isPre ) ? <STR_LIT> : <STR_LIT> ; break ; }


<s> } unsigned Opcode = <NUM_LIT> ; int Offs = cast < ConstantSDNode > ( LD -> getOffset ( ) ) -> getSExtValue ( ) ; switch ( VT . SimpleTy ) { case <STR_LIT> : { if ( Offs != <NUM_LIT> ) { return <NUM_LIT> ; } Opcode = <STR_LIT> ; break ;


<s> <STR_LIT> AM = LD -> getAddressingMode ( ) ; if ( LD -> getExtensionType ( ) != <STR_LIT> || AM != <STR_LIT> ) { return <NUM_LIT> ; } unsigned Opcode = <NUM_LIT> ; int Offs = cast < ConstantSDNode > ( LD -> getOffset ( ) ) -> getSExtValue ( ) ; switch ( VT . SimpleTy ) { case <STR_LIT> : { if ( Offs != <NUM_LIT> ) { return <NUM_LIT> ; } Opcode = <STR_LIT> ;


<s> Reg = RegNode -> getReg ( ) ; CanHandleRegImmOpt &= ( TargetRegisterInfo :: isVirtualRegister ( Reg ) || <STR_LIT> . contains ( Reg ) ) ; } else { CanHandleRegImmOpt = false ; } if ( CanHandleRegImmOpt ) { SDValue Base , Disp ; if ( RI . getRegClass ( Reg ) != & <STR_LIT> ) { SDLoc dl ( CopyFromRegOp ) ; unsigned VReg = RI . createVirtualRegister ( & <STR_LIT> ) ; SDValue CopyToReg = CurDAG -> getCopyToReg ( CopyFromRegOp , dl , VReg , CopyFromRegOp ) ; SDValue NewCopyFromRegOp = CurDAG -> getCopyFromReg ( CopyToReg , dl , VReg , TL . getPointerTy ( DL ) ) ; Base = NewCopyFromRegOp ; } else { Base = CopyFromRegOp ; } if ( ImmNode -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) { Disp = CurDAG -> getTargetConstant ( ImmNode -> getAPIntValue ( ) . getZExtValue ( ) , dl , <STR_LIT> ) ; } else { Disp = ImmOp ; }


<s> if ( Op -> getOpcode ( ) == <STR_LIT> ) { SDValue Base , Disp ; if ( SelectAddr ( Op . getNode ( ) , Op , Base , Disp ) ) { OutOps . push_back ( Base ) ; OutOps . push_back ( Disp ) ; return false ; } return true ; } if ( Op -> getOpcode ( ) == <STR_LIT> || Op -> getOpcode ( ) == <STR_LIT> ) { SDValue CopyFromRegOp = Op -> getOperand ( <NUM_LIT> ) ; SDValue ImmOp = Op -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * ImmNode = dyn_cast < ConstantSDNode > ( ImmOp ) ; unsigned Reg ; bool CanHandleRegImmOpt = true ; CanHandleRegImmOpt &= ImmNode != <NUM_LIT> ; CanHandleRegImmOpt &= ImmNode -> getAPIntValue ( ) . getZExtValue ( ) < <NUM_LIT> ; if ( CopyFromRegOp -> getOpcode ( ) == <STR_LIT> ) { RegisterSDNode * RegNode = cast < RegisterSDNode > ( CopyFromRegOp -> getOperand ( <NUM_LIT> ) ) ; Reg = RegNode -> getReg ( ) ; CanHandleRegImmOpt &= ( TargetRegisterInfo :: isVirtualRegister ( Reg ) || <STR_LIT> . contains ( Reg ) ) ; } else { CanHandleRegImmOpt = false ; } if ( CanHandleRegImmOpt ) { SDValue Base , Disp ; if ( RI . getRegClass ( Reg ) != & <STR_LIT> ) { SDLoc dl ( CopyFromRegOp ) ; unsigned VReg = RI . createVirtualRegister ( & <STR_LIT> ) ; SDValue CopyToReg = CurDAG -> getCopyToReg ( CopyFromRegOp , dl , VReg , CopyFromRegOp ) ; SDValue NewCopyFromRegOp = CurDAG -> getCopyFromReg ( CopyToReg , dl , VReg , TL . getPointerTy ( DL ) ) ; Base = NewCopyFromRegOp ; } else { Base = CopyFromRegOp ; } if ( ImmNode -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) { Disp = CurDAG -> getTargetConstant ( ImmNode -> getAPIntValue ( ) . getZExtValue ( ) , dl , <STR_LIT> ) ; } else { Disp = ImmOp ;


<s> MVT Type = N -> getSimpleValueType ( <NUM_LIT> ) ; assert ( Type == <STR_LIT> && <STR_LIT> ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> ; unsigned MachineOp = isSigned ? <STR_LIT> : <STR_LIT> ; SDValue Lhs = N -> getOperand ( <NUM_LIT> ) ; SDValue Rhs = N -> getOperand ( <NUM_LIT> ) ; SDNode * Mul = CurDAG -> getMachineNode ( MachineOp , DL , <STR_LIT> , Lhs , Rhs ) ; SDValue InChain = CurDAG -> getEntryNode ( ) ; SDValue InGlue = SDValue ( Mul , <NUM_LIT> ) ; if ( N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue CopyFromLo = CurDAG -> getCopyFromReg ( InChain , DL , <STR_LIT> , Type , InGlue ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , CopyFromLo ) ; InChain = CopyFromLo . getValue ( <NUM_LIT> ) ;

InGlue = CopyFromLo . getValue ( <NUM_LIT> ) ;


<s> unsigned Opcode = N -> getOpcode ( ) ; SDLoc DL ( N ) ; switch ( Opcode ) { case <STR_LIT> : return select < <STR_LIT> > ( N ) ; case <STR_LIT> : return select < <STR_LIT> > ( N ) ; case <STR_LIT> : case <STR_LIT> : return selectMultiplication ( N ) ;


<s> switch ( Opcode ) { case <STR_LIT> : return select < <STR_LIT> > ( N ) ; case <STR_LIT> : return select < <STR_LIT> > ( N ) ; case <STR_LIT> : case <STR_LIT> : return selectMultiplication ( N ) ; case <STR_LIT> : return select < <STR_LIT> > ( N ) ; case <STR_LIT> : return select < <STR_LIT> > ( N ) ; case <STR_LIT> : return select < <STR_LIT> > ( N ) ; default : return false ; }


<s> <STR_LIT> getCmpLibcallReturnType ( ) const override { return <STR_LIT> ;


<s> return insertShift ( MI , MBB ) ; case <STR_LIT> : case <STR_LIT> : return insertMul ( MI , MBB ) ; } assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; const <ISA_LIT>InstrInfo & TII = ( const <ISA_LIT>InstrInfo & ) * MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const BasicBlock * LLVM_BB = MBB -> getBasicBlock ( ) ; MachineBasicBlock * trueMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * falseMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator I ; for ( I = MF -> begin ( ) ; I != MF -> end ( ) && & ( * I ) != MBB ; ++ I ) ; if ( I != MF -> end ( ) ) ++ I ; MF -> insert ( I , trueMBB ) ; MF -> insert ( I , falseMBB ) ; trueMBB -> splice ( trueMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; trueMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ;

<STR_LIT> CC = ( <STR_LIT> ) MI . getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> case 'l' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'e' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'q' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'r' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 't' : return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; case 'w' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'x' : case 'X' : return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; case 'y' : case 'Y' : return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ;


<s> const <ISA_LIT>TargetMachine & TM = ( const <ISA_LIT>TargetMachine & ) getTargetMachine ( ) ; const TargetInstrInfo & TII = * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ; MachineBasicBlock :: iterator I ( MI ) ; ++ I ; if ( isCopyMulResult ( I ) ) ++ I ;


<s> case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; } const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I ; for ( I = BB -> getIterator ( ) ; I != F -> end ( ) && & ( * I ) != BB ; ++ I ) ; if ( I != F -> end ( ) ) ++ I ; MachineBasicBlock * LoopBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * RemBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , LoopBB ) ; F -> insert ( I , RemBB ) ; RemBB -> splice ( RemBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; RemBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( LoopBB ) ; BB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( LoopBB ) ; unsigned ShiftAmtReg = RI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ShiftAmtReg2 = RI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ShiftReg = RI . createVirtualRegister ( RC ) ; unsigned ShiftReg2 = RI . createVirtualRegister ( RC ) ; unsigned ShiftAmtSrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( ShiftAmtSrcReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( RemBB ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftReg ) . addReg ( SrcReg ) . addMBB ( BB ) . addReg ( ShiftReg2 ) . addMBB ( LoopBB ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg ) . addReg ( ShiftAmtSrcReg ) . addMBB ( BB ) . addReg ( ShiftAmtReg2 ) . addMBB ( LoopBB ) ;

BuildMI ( LoopBB , dl , TII . get ( Opc ) , ShiftReg2 ) . addReg ( ShiftReg ) ;


<s> } RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } if ( HasStackArgs ) { for ( AE = AI , AI = ArgLocs . size ( ) ; AI != AE ; -- AI ) { unsigned Loc = AI - <NUM_LIT> ; CCValAssign & VA = ArgLocs [ Loc ] ; SDValue Arg = OutVals [ Loc ] ; assert ( VA . isMemLoc ( ) ) ; SDValue PtrOff = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , DAG . getRegister ( <STR_LIT> , getPointerTy ( DAG . getDataLayout ( ) ) ) , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + <NUM_LIT> , DL ) ) ; Chain = DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo :: getStack ( MF , VA . getLocMemOffset ( ) ) , <NUM_LIT> ) ; } } SDValue InFlag ; for ( auto Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , DL , Reg . first , Reg . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( auto Reg : RegsToPass ) { Ops . push_back ( DAG . getRegister ( Reg . first , Reg . second . getValueType ( ) ) ) ; } const <ISA_LIT>TargetMachine & TM = ( const <ISA_LIT>TargetMachine & ) getTargetMachine ( ) ; const TargetRegisterInfo * TRI = TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallConv ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; if ( InFlag . getNode ( ) ) { Ops . push_back ( InFlag ) ; } Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Ops ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , InFlag , DL ) ;


<s> assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; bool IsSigned = ( Opcode == <STR_LIT> ) ; EVT VT = Op -> getValueType ( <NUM_LIT> ) ; Type * Ty = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; RTLIB :: Libcall LC ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : LC = IsSigned ? RTLIB :: SDIVREM_I8 : RTLIB :: UDIVREM_I8 ; break ; case <STR_LIT> : LC = IsSigned ? RTLIB :: SDIVREM_I16 : RTLIB :: UDIVREM_I16 ; break ; case <STR_LIT> : LC = IsSigned ? RTLIB :: SDIVREM_I32 : RTLIB :: UDIVREM_I32 ; break ; case <STR_LIT> : LC = IsSigned ? RTLIB :: SDIVREM_I64 : RTLIB :: UDIVREM_I64 ; break ; } SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ;

for ( SDValue const & Value : Op -> op_values ( ) ) {


<s> assert ( TotalBytes <= <NUM_LIT> && <STR_LIT> ) ; if ( TotalBytes > <NUM_LIT> ) { TotalBytes = <NUM_LIT> ; } else { TotalBytes = alignTo ( TotalBytes , <NUM_LIT> ) ; } int RegIdx = TotalBytes - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumArgs ; ++ i ) { MVT VT = Args [ i ] . VT ; unsigned Reg ; if ( VT == <STR_LIT> ) { Reg = CCInfo . AllocateReg ( RegList8 [ RegIdx ] ) ; } else if ( VT == <STR_LIT> ) { Reg = CCInfo . AllocateReg ( RegList16 [ RegIdx ] ) ; } else { llvm_unreachable ( <STR_LIT> ) ; }


<s> if ( TotalBytes > <NUM_LIT> ) { TotalBytes = <NUM_LIT> ; } else { TotalBytes = alignTo ( TotalBytes , <NUM_LIT> ) ; } int RegIdx = TotalBytes - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumArgs ; ++ i ) { MVT VT = Args [ i ] . VT ; unsigned Reg ;


<s> std :: pair < unsigned , const TargetRegisterClass * > <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'a' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'b' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'd' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'l' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'e' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'q' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'r' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 't' : if ( VT == <STR_LIT> ) return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; break ; case 'w' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'x' : case 'X' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; break ; case 'y' : case 'Y' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; break ;


<s> if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'd' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'l' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'e' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'q' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'r' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 't' : if ( VT == <STR_LIT> ) return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; break ; case 'w' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'x' : case 'X' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; break ; case 'y' : case 'Y' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; break ; case 'z' : case 'Z' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; break ; default : break ;


<s> Register Reg ; if ( VT == LLT :: scalar ( <NUM_LIT> ) ) { Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> Register <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , LLT VT , const MachineFunction & MF ) const { Register Reg ; if ( VT == LLT :: scalar ( <NUM_LIT> ) ) { Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; } else { Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; } if ( Reg ) return Reg ; report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ) ;


<s> for ( const ArgT & Arg : Args ) { TotalBytes += Arg . VT . getStoreSize ( ) ; } return TotalBytes ;


<s> RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; } const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I ; for ( I = BB -> getIterator ( ) ; I != F -> end ( ) && & ( * I ) != BB ; ++ I ) ; if ( I != F -> end ( ) ) ++ I ; MachineBasicBlock * LoopBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * CheckBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * RemBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , LoopBB ) ; F -> insert ( I , CheckBB ) ; F -> insert ( I , RemBB ) ; RemBB -> splice ( RemBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; RemBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( CheckBB ) ; LoopBB -> addSuccessor ( CheckBB ) ; CheckBB -> addSuccessor ( LoopBB ) ; CheckBB -> addSuccessor ( RemBB ) ; Register ShiftAmtReg = RI . createVirtualRegister ( & <STR_LIT> ) ; Register ShiftAmtReg2 = RI . createVirtualRegister ( & <STR_LIT> ) ; Register ShiftReg = RI . createVirtualRegister ( RC ) ; Register ShiftReg2 = RI . createVirtualRegister ( RC ) ; Register ShiftAmtSrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( CheckBB ) ; auto ShiftMI = BuildMI ( LoopBB , dl , TII . get ( Opc ) , ShiftReg2 ) . addReg ( ShiftReg ) ; if ( HasRepeatedOperand ) ShiftMI . addReg ( ShiftReg ) ; BuildMI ( CheckBB , dl , TII . get ( <STR_LIT> ) , ShiftReg ) . addReg ( SrcReg ) . addMBB ( BB ) . addReg ( ShiftReg2 ) . addMBB ( LoopBB ) ;

BuildMI ( CheckBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg ) . addReg ( ShiftAmtSrcReg ) . addMBB ( BB ) . addReg ( ShiftAmtReg2 ) . addMBB ( LoopBB ) ;


<s> Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( CheckBB ) ; auto ShiftMI = BuildMI ( LoopBB , dl , TII . get ( Opc ) , ShiftReg2 ) . addReg ( ShiftReg ) ; if ( HasRepeatedOperand ) ShiftMI . addReg ( ShiftReg ) ; BuildMI ( CheckBB , dl , TII . get ( <STR_LIT> ) , ShiftReg ) . addReg ( SrcReg ) . addMBB ( BB ) . addReg ( ShiftReg2 ) . addMBB ( LoopBB ) ; BuildMI ( CheckBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg ) . addReg ( ShiftAmtSrcReg ) . addMBB ( BB ) . addReg ( ShiftAmtReg2 ) . addMBB ( LoopBB ) ; BuildMI ( CheckBB , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addMBB ( BB ) . addReg ( ShiftReg2 ) . addMBB ( LoopBB ) ; BuildMI ( CheckBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg2 ) . addReg ( ShiftAmtReg ) ; BuildMI ( CheckBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( LoopBB ) ; MI . eraseFromParent ( ) ; return RemBB ;


<s> analyzeReturnValues ( Ins , CCInfo ) ; } for ( CCValAssign const & RVLoc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLoc . getLocReg ( ) , RVLoc . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; }


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto DL = DAG . getDataLayout ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; if ( isVarArg ) { CCInfo . AnalyzeFormalArguments ( Ins , ArgCC_<ISA_LIT>_Vararg ) ; } else { analyzeArguments ( nullptr , & MF . getFunction ( ) , & DL , Ins , ArgLocs , CCInfo ) ; } SDValue ArgValue ; for ( CCValAssign & VA : ArgLocs ) { if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) { RC = & <STR_LIT> ; } else if ( RegVT == <STR_LIT> ) { RC = & <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ;

ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ;


<s> Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) . getAttributes ( ) . hasFnAttr ( Attribute :: Naked ) ) { return Chain ; } const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned RetOpc = AFI -> isInterruptOrSignalHandler ( ) ? <STR_LIT> : <STR_LIT> ; RetOps [ <NUM_LIT> ] = Chain ;


<s> break ; case <STR_LIT> : Opc8 = <STR_LIT> ; ShiftAmount = ShiftAmount % VT . getSizeInBits ( ) ; break ; case <STR_LIT> : Opc8 = <STR_LIT> ; ShiftAmount = ShiftAmount % VT . getSizeInBits ( ) ; break ; case <STR_LIT> : Opc8 = <STR_LIT> ; break ; case <STR_LIT> : Opc8 = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( Op . getOpcode ( ) == <STR_LIT> && <NUM_LIT> <= ShiftAmount && ShiftAmount < <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; ShiftAmount -= <NUM_LIT> ; } else if ( Op . getOpcode ( ) == <STR_LIT> && <NUM_LIT> <= ShiftAmount && ShiftAmount < <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; ShiftAmount -= <NUM_LIT> ; } else if ( Op . getOpcode ( ) == <STR_LIT> && ShiftAmount == <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; ShiftAmount = <NUM_LIT> ; } else if ( Op . getOpcode ( ) == <STR_LIT> && ShiftAmount == <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; ShiftAmount = <NUM_LIT> ; } else if ( Op . getOpcode ( ) == <STR_LIT> && ShiftAmount == <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; ShiftAmount = <NUM_LIT> ; } } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( <NUM_LIT> <= ShiftAmount && ShiftAmount < <NUM_LIT> ) switch ( Op . getOpcode ( ) ) { case <STR_LIT> : Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; ShiftAmount -= <NUM_LIT> ; break ; case <STR_LIT> : Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; ShiftAmount -= <NUM_LIT> ; break ; default : break ; } else if ( <NUM_LIT> <= ShiftAmount && ShiftAmount < <NUM_LIT> ) switch ( Op . getOpcode ( ) ) { case <STR_LIT> : Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerVASTART ( SDValue Op , SelectionDAG & DAG ) const { const MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;


<s> const MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; auto DL = DAG . getDataLayout ( ) ; SDLoc dl ( Op ) ; SDValue FI = DAG . getFrameIndex ( AFI -> getVarArgsFrameIndex ( ) , getPointerTy ( DL ) ) ;

return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FI , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) ) ;


<s> bool UseStack = false ; for ( unsigned i = <NUM_LIT> ; i != NumArgs ; ) { MVT VT = Args [ i ] . VT ; unsigned ArgIndex = Args [ i ] . OrigArgIndex ; unsigned TotalBytes = VT . getStoreSize ( ) ; unsigned j = i + <NUM_LIT> ; for ( ; j != NumArgs ; ++ j ) { if ( Args [ j ] . OrigArgIndex != ArgIndex ) break ; TotalBytes += Args [ j ] . VT . getStoreSize ( ) ; } TotalBytes = alignTo ( TotalBytes , <NUM_LIT> ) ; if ( TotalBytes == <NUM_LIT> ) continue ; unsigned RegIdx = RegLastIdx + TotalBytes ; RegLastIdx = RegIdx ; if ( RegIdx >= RegList8 . size ( ) ) { UseStack = true ; } for ( ; i != j ; ++ i ) {


<s> TotalBytes = alignTo ( TotalBytes , <NUM_LIT> ) ; if ( TotalBytes == <NUM_LIT> ) continue ; unsigned RegIdx = RegLastIdx + TotalBytes ; RegLastIdx = RegIdx ; if ( RegIdx >= RegList8 . size ( ) ) { UseStack = true ; } for ( ; i != j ; ++ i ) { MVT VT = Args [ i ] . VT ; if ( UseStack ) { auto evt = EVT ( VT ) . getTypeForEVT ( CCInfo . getContext ( ) ) ; unsigned Offset = CCInfo . AllocateStack ( TD -> getTypeAllocSize ( evt ) , TD -> getABITypeAlign ( evt ) ) ; CCInfo . addLoc ( CCValAssign :: getMem ( i , VT , Offset , VT , CCValAssign :: Full ) ) ; } else { unsigned Reg ;


<s> } else { RegList8 = makeArrayRef ( RegList8<ISA_LIT> , array_lengthof ( RegList8<ISA_LIT> ) ) ; RegList16 = makeArrayRef ( RegList16<ISA_LIT> , array_lengthof ( RegList16<ISA_LIT> ) ) ; } if ( TotalBytes > <NUM_LIT> ) { TotalBytes = <NUM_LIT> ; } else { TotalBytes = alignTo ( TotalBytes , <NUM_LIT> ) ; } int RegIdx = TotalBytes - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumArgs ; ++ i ) {


<s> int RegIdx = TotalBytes - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumArgs ; ++ i ) { MVT VT = Args [ i ] . VT ; unsigned Reg ; if ( VT == <STR_LIT> ) { Reg = CCInfo . AllocateReg ( RegList8 [ RegIdx ] ) ; } else if ( VT == <STR_LIT> ) { Reg = CCInfo . AllocateReg ( RegList16 [ RegIdx ] ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } assert ( Reg && <STR_LIT> ) ; CCInfo . addLoc ( CCValAssign :: getReg ( i , VT , Reg , VT , CCValAssign :: Full ) ) ; RegIdx -= VT . getStoreSize ( ) ; }


<s> case 'G' : if ( const ConstantFP * C = dyn_cast < ConstantFP > ( CallOperandVal ) ) { if ( C -> isZero ( ) ) { weight = CW_Constant ; } } break ; case 'I' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) { weight = CW_Constant ; } } break ; case 'J' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getSExtValue ( ) >= - <NUM_LIT> ) && ( C -> getSExtValue ( ) <= <NUM_LIT> ) ) { weight = CW_Constant ; } } break ; case 'K' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) == <NUM_LIT> ) { weight = CW_Constant ; } } break ; case 'L' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) == <NUM_LIT> ) { weight = CW_Constant ; } }


<s> case 'Z' : weight = CW_SpecificReg ; break ; case 'G' : if ( const ConstantFP * C = dyn_cast < ConstantFP > ( CallOperandVal ) ) { if ( C -> isZero ( ) ) { weight = CW_Constant ; } } break ; case 'I' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) { weight = CW_Constant ; } } break ; case 'J' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getSExtValue ( ) >= - <NUM_LIT> ) && ( C -> getSExtValue ( ) <= <NUM_LIT> ) ) { weight = CW_Constant ; } } break ; case 'K' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) == <NUM_LIT> ) { weight = CW_Constant ; } } break ; case 'L' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) == <NUM_LIT> ) { weight = CW_Constant ; } } break ; case 'M' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) { weight = CW_Constant ; } } break ; case 'N' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getSExtValue ( ) == - <NUM_LIT> ) { weight = CW_Constant ; } } break ; case 'O' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getZExtValue ( ) == <NUM_LIT> ) || ( C -> getZExtValue ( ) == <NUM_LIT> ) || ( C -> getZExtValue ( ) == <NUM_LIT> ) ) { weight = CW_Constant ; } } break ; case 'P' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) == <NUM_LIT> ) { weight = CW_Constant ; } } break ; case 'R' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getSExtValue ( ) >= - <NUM_LIT> ) && ( C -> getSExtValue ( ) <= <NUM_LIT> ) ) { weight = CW_Constant ;


<s> unsigned TotalBytes = <NUM_LIT> ; for ( const ArgT & Arg : Args ) {

TotalBytes += Arg . VT . getStoreSize ( ) ;


<s> const TargetRegisterClass * RC = ( Width == <NUM_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned LoadOpcode = ( Width == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned StoreOpcode = ( Width == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , I , dl , TII . get ( <STR_LIT> ) , SCRATCH_REGISTER ) . addImm ( Subtarget . getIORegSREG ( ) ) ; BuildMI ( * BB , I , dl , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , I , dl , TII . get ( LoadOpcode ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; Register Result = MRI . createVirtualRegister ( RC ) ; BuildMI ( * BB , I , dl , TII . get ( Opcode ) , Result ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ;

BuildMI ( * BB , I , dl , TII . get ( StoreOpcode ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( Result ) ;


<s> const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; MachineBasicBlock :: iterator I ( MI ) ;

BuildMI ( * BB , I , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> ) ;


<s> const TargetRegisterClass * RC ; bool HasRepeatedOperand = false ; MachineFunction * F = BB -> getParent ( ) ; MachineRegisterInfo & RI = F -> getRegInfo ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; HasRepeatedOperand = true ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; } const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I ; for ( I = BB -> getIterator ( ) ; I != F -> end ( ) && & ( * I ) != BB ; ++ I ) ; if ( I != F -> end ( ) ) ++ I ; MachineBasicBlock * LoopBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * CheckBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * RemBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , LoopBB ) ; F -> insert ( I , CheckBB ) ; F -> insert ( I , RemBB ) ; RemBB -> splice ( RemBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; RemBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( CheckBB ) ; LoopBB -> addSuccessor ( CheckBB ) ; CheckBB -> addSuccessor ( LoopBB ) ; CheckBB -> addSuccessor ( RemBB ) ; Register ShiftAmtReg = RI . createVirtualRegister ( & <STR_LIT> ) ;

Register ShiftAmtReg2 = RI . createVirtualRegister ( & <STR_LIT> ) ;


<s> } if ( Offs < <NUM_LIT> ) Offs = - Offs ; if ( AM . BaseGV == nullptr && AM . HasBaseReg && AM . Scale == <NUM_LIT> && isUInt < <NUM_LIT> > ( Offs ) ) { return true ;


<s> return true ; } if ( isa < PointerType > ( Ty ) && AS == <STR_LIT> ) { return false ; } if ( Offs < <NUM_LIT> ) Offs = - Offs ; if ( AM . BaseGV == nullptr && AM . HasBaseReg && AM . Scale == <NUM_LIT> && isUInt < <NUM_LIT> > ( Offs ) ) { return true ; } return false ;


<s> case 'L' : case 'M' : case 'N' : case 'O' : case 'P' : case 'R' : { const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ; if ( ! C ) { return ; } int64_t CVal64 = C -> getSExtValue ( ) ; uint64_t CUVal64 = C -> getZExtValue ( ) ; switch ( ConstraintLetter ) { case 'I' : if ( ! isUInt < <NUM_LIT> > ( CUVal64 ) ) return ; Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'J' : if ( CVal64 < - <NUM_LIT> || CVal64 > <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CVal64 , DL , Ty ) ; break ; case 'K' : if ( CUVal64 != <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'L' : if ( CUVal64 != <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'M' : if ( ! isUInt < <NUM_LIT> > ( CUVal64 ) ) return ; if ( Ty . getSimpleVT ( ) == <STR_LIT> ) { Ty = <STR_LIT> ; } Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'N' : if ( CVal64 != - <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CVal64 , DL , Ty ) ; break ; case 'O' : if ( CUVal64 != <NUM_LIT> && CUVal64 != <NUM_LIT> && CUVal64 != <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ;


<s> switch ( ConstraintLetter ) { case 'I' : if ( ! isUInt < <NUM_LIT> > ( CUVal64 ) ) return ; Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'J' : if ( CVal64 < - <NUM_LIT> || CVal64 > <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CVal64 , DL , Ty ) ; break ; case 'K' : if ( CUVal64 != <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'L' : if ( CUVal64 != <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'M' : if ( ! isUInt < <NUM_LIT> > ( CUVal64 ) ) return ; if ( Ty . getSimpleVT ( ) == <STR_LIT> ) { Ty = <STR_LIT> ; } Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'N' : if ( CVal64 != - <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CVal64 , DL , Ty ) ; break ; case 'O' : if ( CUVal64 != <NUM_LIT> && CUVal64 != <NUM_LIT> && CUVal64 != <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'P' : if ( CUVal64 != <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ;


<s> Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; } if ( VA . isMemLoc ( ) ) { HasStackArgs = true ; break ; } RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } if ( HasStackArgs ) { SmallVector < SDValue , <NUM_LIT> > MemOpChains ; for ( ; AI != AE ; AI ++ ) { CCValAssign & VA = ArgLocs [ AI ] ; SDValue Arg = OutVals [ AI ] ; assert ( VA . isMemLoc ( ) ) ; SDValue PtrOff = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , DAG . getRegister ( <STR_LIT> , getPointerTy ( DAG . getDataLayout ( ) ) ) , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + <NUM_LIT> , DL ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo :: getStack ( MF , VA . getLocMemOffset ( ) ) ) ) ; } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MemOpChains ) ; } SDValue InFlag ; for ( auto Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , DL , Reg . first , Reg . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ;


<s> if ( CallConv == CallingConv :: <ISA_LIT>_BUILTIN ) { CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT>_BUILTIN ) ; } else { analyzeReturnValues ( Ins , CCInfo , Subtarget . hasTinyEncoding ( ) ) ; } for ( CCValAssign const & RVLoc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLoc . getLocReg ( ) , RVLoc . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ;

InFlag = Chain . getValue ( <NUM_LIT> ) ;


<s> RC = & <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } Register Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: SExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: ZExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; EVT LocVT = VA . getLocVT ( ) ; int FI = MFI . CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DL ) ) ; InVals . push_back ( DAG . getLoad ( LocVT , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ) ; }


<s> CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) . getAttributes ( ) . hasFnAttr ( Attribute :: Naked ) ) { return Chain ; } const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;

unsigned RetOpc = AFI -> isInterruptOrSignalHandler ( ) ? <STR_LIT> : <STR_LIT> ;


<s> CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; if ( CallConv == CallingConv :: <ISA_LIT>_BUILTIN ) { CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>_BUILTIN ) ; } else { analyzeReturnValues ( Outs , CCInfo , Subtarget . hasTinyEncoding ( ) ) ; } SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) . getAttributes ( ) . hasFnAttr ( Attribute :: Naked ) ) { return Chain ; } const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned RetOpc = AFI -> isInterruptOrSignalHandler ( ) ? <STR_LIT> : <STR_LIT> ; RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) { RetOps . push_back ( Flag ) ; } return DAG . getNode ( RetOpc , dl , <STR_LIT> , RetOps ) ;


<s> switch ( Constraint [ <NUM_LIT> ] ) { case 'a' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'b' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'd' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'l' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'e' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'q' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'r' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 't' : return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; case 'w' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'x' : case 'X' : return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; case 'y' : case 'Y' : return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; case 'z' : case 'Z' : return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; default : break ; } }

return TargetLowering :: getRegForInlineAsmConstraint ( Subtarget . getRegisterInfo ( ) , Constraint , VT ) ;


<s> SDValue Victim = N -> getOperand ( <NUM_LIT> ) ; switch ( Op . getOpcode ( ) ) { case <STR_LIT> : Opc8 = <STR_LIT> ; break ; case <STR_LIT> : Opc8 = <STR_LIT> ; ShiftAmount = ShiftAmount % VT . getSizeInBits ( ) ; break ; case <STR_LIT> : Opc8 = <STR_LIT> ; ShiftAmount = ShiftAmount % VT . getSizeInBits ( ) ; break ; case <STR_LIT> : Opc8 = <STR_LIT> ; break ; case <STR_LIT> : Opc8 = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( Op . getOpcode ( ) == <STR_LIT> && <NUM_LIT> <= ShiftAmount && ShiftAmount < <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; ShiftAmount -= <NUM_LIT> ; } else if ( Op . getOpcode ( ) == <STR_LIT> && <NUM_LIT> <= ShiftAmount && ShiftAmount < <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; ShiftAmount -= <NUM_LIT> ; } else if ( Op . getOpcode ( ) == <STR_LIT> && ShiftAmount == <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; ShiftAmount = <NUM_LIT> ; } else if ( Op . getOpcode ( ) == <STR_LIT> && ShiftAmount == <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; ShiftAmount = <NUM_LIT> ; } else if ( Op . getOpcode ( ) == <STR_LIT> && ShiftAmount == <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; ShiftAmount = <NUM_LIT> ; } } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( <NUM_LIT> <= ShiftAmount && ShiftAmount < <NUM_LIT> ) switch ( Op . getOpcode ( ) ) { case <STR_LIT> :


<s> CCInfo . AnalyzeFormalArguments ( * Ins , ArgCC_<ISA_LIT>_Vararg ) ; } return ; } SmallVector < unsigned , <NUM_LIT> > Args ; if ( IsCall ) { parseExternFuncCallArgs ( * Outs , Args ) ; } else { assert ( F != nullptr && <STR_LIT> ) ; parseFunctionArgs ( F , TD , Args ) ; } unsigned RegsLeft = array_lengthof ( RegList8 ) , ValNo = <NUM_LIT> ; bool UsesStack = false ; for ( unsigned i = <NUM_LIT> , pos = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i ) { unsigned Size = Args [ i ] ; if ( Size == <NUM_LIT> ) continue ; MVT LocVT = ( IsCall ) ? ( * Outs ) [ pos ] . VT : ( * Ins ) [ pos ] . VT ; if ( ! UsesStack && ( Size <= RegsLeft ) ) { const MCPhysReg * RegList = ( LocVT == <STR_LIT> ) ? RegList16 : RegList8 ; for ( unsigned j = <NUM_LIT> ; j != Size ; ++ j ) { unsigned Reg = CCInfo . AllocateReg ( ArrayRef < MCPhysReg > ( RegList , array_lengthof ( RegList8 ) ) ) ; CCInfo . addLoc ( CCValAssign :: getReg ( ValNo ++ , LocVT , Reg , LocVT , CCValAssign :: Full ) ) ; -- RegsLeft ; } std :: reverse ( ArgLocs . begin ( ) + pos , ArgLocs . begin ( ) + pos + Size ) ; } else { UsesStack = true ;


<s> ++ I ; MF -> insert ( I , trueMBB ) ; MF -> insert ( I , falseMBB ) ; trueMBB -> splice ( trueMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; trueMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; <STR_LIT> CC = ( <STR_LIT> ) MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( MBB , dl , TII . getBrCond ( CC ) ) . addMBB ( trueMBB ) ; BuildMI ( MBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( falseMBB ) ; MBB -> addSuccessor ( falseMBB ) ; MBB -> addSuccessor ( trueMBB ) ; BuildMI ( falseMBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( trueMBB ) ; falseMBB -> addSuccessor ( trueMBB ) ; BuildMI ( * trueMBB , trueMBB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( MBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( falseMBB ) ; MI . eraseFromParent ( ) ; return trueMBB ;


<s> MachineFunction :: iterator I = BB -> getParent ( ) -> begin ( ) ; ++ I ; MachineBasicBlock * LoopBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * RemBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , LoopBB ) ; F -> insert ( I , RemBB ) ; RemBB -> splice ( RemBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; RemBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( LoopBB ) ; BB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( LoopBB ) ; unsigned ShiftAmtReg = RI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ShiftAmtReg2 = RI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ShiftReg = RI . createVirtualRegister ( RC ) ; unsigned ShiftReg2 = RI . createVirtualRegister ( RC ) ; unsigned ShiftAmtSrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( ShiftAmtSrcReg ) . addReg ( <STR_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( RemBB ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftReg ) . addReg ( SrcReg ) . addMBB ( BB ) . addReg ( ShiftReg2 ) . addMBB ( LoopBB ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg ) . addReg ( ShiftAmtSrcReg ) . addMBB ( BB ) . addReg ( ShiftAmtReg2 ) . addMBB ( LoopBB ) ;


<s> int64_t Offs = AM . BaseOffs ; if ( AM . BaseGV && ! AM . HasBaseReg && AM . Scale == <NUM_LIT> && Offs == <NUM_LIT> ) { return true ; } if ( isa < PointerType > ( Ty ) && AS == <STR_LIT> ) { return false ; }


<s> return false ; } if ( Offs < <NUM_LIT> ) Offs = - Offs ; if ( AM . BaseGV == <NUM_LIT> && AM . HasBaseReg && AM . Scale == <NUM_LIT> && isUInt < <NUM_LIT> > ( Offs ) ) { return true ; }


<s> SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = ( Type * ) StructType :: get ( Ty , Ty , nullptr ) ; SDLoc dl ( Op ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setCallee ( getLibcallCallingConv ( LC ) , RetTy , Callee , std :: move ( Args ) ) . setInRegister ( ) . setSExtResult ( isSigned ) . setZExtResult ( ! isSigned ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ;


<s> analyzeArguments ( nullptr , MF . getFunction ( ) , & DL , <NUM_LIT> , & Ins , CallConv , ArgLocs , CCInfo , false , isVarArg ) ; SDValue ArgValue ; for ( CCValAssign & VA : ArgLocs ) { if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) { RC = & <STR_LIT> ; } else if ( RegVT == <STR_LIT> ) { RC = & <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: SExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: ZExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ;


<s> break ; case CCValAssign :: ZExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; EVT LocVT = VA . getLocVT ( ) ; int FI = MFI . CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DL ) ) ; InVals . push_back ( DAG . getLoad ( LocVT , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) , <NUM_LIT> ) ) ; } } if ( isVarArg ) { unsigned StackSize = CCInfo . getNextStackOffset ( ) ; <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; AFI -> setVarArgsFrameIndex ( MFI . CreateFixedObject ( <NUM_LIT> , StackSize , true ) ) ; } return Chain ;


<s> for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; }

if ( MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: Naked ) ) {


<s> case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; } } uint64_t ShiftAmount = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Victim = N -> getOperand ( <NUM_LIT> ) ; switch ( Op . getOpcode ( ) ) { case <STR_LIT> : Opc8 = <STR_LIT> ;


<s> for ( Argument const & Arg : F -> args ( ) ) { unsigned Bytes = ( TD -> getTypeSizeInBits ( Arg . getType ( ) ) + <NUM_LIT> ) / <NUM_LIT> ;

Out . push_back ( ( Bytes + <NUM_LIT> ) / <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertShift ( MI , MBB ) ; case <STR_LIT> : case <STR_LIT> : return insertMul ( MI , MBB ) ; } assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; const <ISA_LIT>InstrInfo & TII = ( const <ISA_LIT>InstrInfo & ) * MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const BasicBlock * LLVM_BB = MBB -> getBasicBlock ( ) ; MachineBasicBlock * FallThrough = MBB -> getFallThrough ( ) ; if ( FallThrough != nullptr ) { BuildMI ( MBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( FallThrough ) ; } MachineBasicBlock * trueMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * falseMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator I ;


<s> MF -> insert ( I , trueMBB ) ; MF -> insert ( I , falseMBB ) ; trueMBB -> splice ( trueMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; trueMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; <STR_LIT> CC = ( <STR_LIT> ) MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( MBB , dl , TII . getBrCond ( CC ) ) . addMBB ( trueMBB ) ; BuildMI ( MBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( falseMBB ) ; MBB -> addSuccessor ( falseMBB ) ; MBB -> addSuccessor ( trueMBB ) ; BuildMI ( falseMBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( trueMBB ) ; falseMBB -> addSuccessor ( trueMBB ) ;

BuildMI ( * trueMBB , trueMBB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( MBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( falseMBB ) ;


<s> CCValAssign & VA = ArgLocs [ AI ] ; SDValue Arg = OutVals [ AI ] ; assert ( VA . isMemLoc ( ) ) ; SDValue PtrOff = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , DAG . getRegister ( <STR_LIT> , getPointerTy ( DAG . getDataLayout ( ) ) ) , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + <NUM_LIT> , DL ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo :: getStack ( MF , VA . getLocMemOffset ( ) ) ) ) ; } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MemOpChains ) ; } SDValue InFlag ; for ( auto Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , DL , Reg . first , Reg . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( auto Reg : RegsToPass ) { Ops . push_back ( DAG . getRegister ( Reg . first , Reg . second . getValueType ( ) ) ) ; } const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallConv ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; if ( InFlag . getNode ( ) ) { Ops . push_back ( InFlag ) ; } Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Ops ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , InFlag , DL ) ; if ( ! Ins . empty ( ) ) { InFlag = Chain . getValue ( <NUM_LIT> ) ;


<s> Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; } if ( VA . isMemLoc ( ) ) { HasStackArgs = true ; break ; } RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } if ( HasStackArgs ) { SmallVector < SDValue , <NUM_LIT> > MemOpChains ; for ( ; AI != AE ; AI ++ ) { CCValAssign & VA = ArgLocs [ AI ] ; SDValue Arg = OutVals [ AI ] ; assert ( VA . isMemLoc ( ) ) ; SDValue PtrOff = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , DAG . getRegister ( <STR_LIT> , getPointerTy ( DAG . getDataLayout ( ) ) ) , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + <NUM_LIT> , DL ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo :: getStack ( MF , VA . getLocMemOffset ( ) ) ) ) ; } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MemOpChains ) ; } SDValue InFlag ; for ( auto Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , DL , Reg . first , Reg . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ;


<s> Entry . IsSExt = IsSigned ; Entry . IsZExt = ! IsSigned ; Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalFunctionSymbol ( getLibcallName ( LC ) ) ; Type * RetTy = ( Type * ) StructType :: get ( Ty , Ty ) ; SDLoc dl ( Op ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setLibCallee ( getLibcallCallingConv ( LC ) , RetTy , Callee , std :: move ( Args ) ) . setInRegister ( ) . setSExtResult ( IsSigned ) . setZExtResult ( ! IsSigned ) ;

std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ;


<s> setSupportsUnalignedAtomics ( true ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT VT : <STR_LIT> ( ) ) { for ( auto N : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) { setLoadExtAction ( N , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( N , VT , <STR_LIT> , Expand ) ; } } setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT VT : <STR_LIT> ( ) ) { setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setIndexedLoadAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setIndexedLoadAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setIndexedLoadAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setIndexedLoadAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setIndexedStoreAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setIndexedStoreAction ( <STR_LIT> , <STR_LIT> , Legal ) ;


<s> SmallVector < unsigned , <NUM_LIT> > Args ; if ( IsCall ) { parseExternFuncCallArgs ( * Outs , Args ) ; } else { assert ( F != nullptr && <STR_LIT> ) ; parseFunctionArgs ( * Ins , Args ) ; } unsigned RegsLeft = array_lengthof ( RegList8 ) , ValNo = <NUM_LIT> ; bool UsesStack = false ; for ( unsigned i = <NUM_LIT> , pos = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i ) { unsigned Size = Args [ i ] ; if ( Size == <NUM_LIT> ) continue ; MVT LocVT = ( IsCall ) ? ( * Outs ) [ pos ] . VT : ( * Ins ) [ pos ] . VT ; if ( ! UsesStack && ( Size <= RegsLeft ) ) { const MCPhysReg * RegList = ( LocVT == <STR_LIT> ) ? RegList16 : RegList8 ; for ( unsigned j = <NUM_LIT> ; j != Size ; ++ j ) { unsigned Reg = CCInfo . AllocateReg ( ArrayRef < MCPhysReg > ( RegList , array_lengthof ( RegList8 ) ) ) ; CCInfo . addLoc ( CCValAssign :: getReg ( ValNo ++ , LocVT , Reg , LocVT , CCValAssign :: Full ) ) ; -- RegsLeft ; } std :: reverse ( ArgLocs . begin ( ) + pos , ArgLocs . begin ( ) + pos + Size ) ; } else { UsesStack = true ; for ( unsigned j = <NUM_LIT> ; j != Size ; ++ j ) { unsigned Offset = CCInfo . AllocateStack ( TD -> getTypeAllocSize ( EVT ( LocVT ) . getTypeForEVT ( CCInfo . getContext ( ) ) ) , TD -> getABITypeAlign ( EVT ( LocVT ) . getTypeForEVT ( CCInfo . getContext ( ) ) ) ) ; CCInfo . addLoc ( CCValAssign :: getMem ( ValNo ++ , LocVT , Offset , LocVT , CCValAssign :: Full ) ) ;


<s> if ( IsCall ) { CCInfo . AnalyzeCallOperands ( * Outs , ArgCC_<ISA_LIT>_Vararg ) ; } else { CCInfo . AnalyzeFormalArguments ( * Ins , ArgCC_<ISA_LIT>_Vararg ) ; } return ; } SmallVector < unsigned , <NUM_LIT> > Args ; if ( IsCall ) { parseExternFuncCallArgs ( * Outs , Args ) ; } else { assert ( F != nullptr && <STR_LIT> ) ; parseFunctionArgs ( * Ins , Args ) ; } unsigned RegsLeft = array_lengthof ( RegList8 ) , ValNo = <NUM_LIT> ; bool UsesStack = false ; for ( unsigned i = <NUM_LIT> , pos = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i ) { unsigned Size = Args [ i ] ; if ( Size == <NUM_LIT> ) continue ; MVT LocVT = ( IsCall ) ? ( * Outs ) [ pos ] . VT : ( * Ins ) [ pos ] . VT ; if ( ! UsesStack && ( Size <= RegsLeft ) ) { const MCPhysReg * RegList = ( LocVT == <STR_LIT> ) ? RegList16 : RegList8 ; for ( unsigned j = <NUM_LIT> ; j != Size ; ++ j ) {

unsigned Reg = CCInfo . AllocateReg ( ArrayRef < MCPhysReg > ( RegList , array_lengthof ( RegList8 ) ) ) ;


<s> return C_Register ; case 'Q' : return C_Memory ; case 'G' : case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'O' : case 'P' : case 'R' : return C_Immediate ; }


<s> Register Reg ; if ( VT == LLT :: scalar ( <NUM_LIT> ) ) { Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; } else { Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; } if ( Reg ) return Reg ;


<s> NODE ( RET_FLAG ) ; NODE ( RETI_FLAG ) ; NODE ( CALL ) ; NODE ( WRAPPER ) ; NODE ( LSL ) ; NODE ( LSR ) ; NODE ( ROL ) ; NODE ( ROR ) ; NODE ( ASR ) ; NODE ( LSLLOOP ) ; NODE ( LSRLOOP ) ;


<s> NODE ( RET_FLAG ) ; NODE ( RETI_FLAG ) ; NODE ( CALL ) ; NODE ( WRAPPER ) ; NODE ( LSL ) ; NODE ( LSR ) ; NODE ( ROL ) ;


<s> RemBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( LoopBB ) ; BB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( LoopBB ) ; Register ShiftAmtReg = RI . createVirtualRegister ( & <STR_LIT> ) ; Register ShiftAmtReg2 = RI . createVirtualRegister ( & <STR_LIT> ) ; Register ShiftReg = RI . createVirtualRegister ( RC ) ; Register ShiftReg2 = RI . createVirtualRegister ( RC ) ; Register ShiftAmtSrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( ShiftAmtSrcReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( RemBB ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftReg ) . addReg ( SrcReg ) . addMBB ( BB ) . addReg ( ShiftReg2 ) . addMBB ( LoopBB ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg ) . addReg ( ShiftAmtSrcReg ) . addMBB ( BB ) . addReg ( ShiftAmtReg2 ) . addMBB ( LoopBB ) ; auto ShiftMI = BuildMI ( LoopBB , dl , TII . get ( Opc ) , ShiftReg2 ) . addReg ( ShiftReg ) ;

if ( HasRepeatedOperand ) ShiftMI . addReg ( ShiftReg ) ;


<s> Opc = <STR_LIT> ; RC = & <STR_LIT> ; HasRepeatedOperand = true ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; } const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I ; for ( I = BB -> getIterator ( ) ; I != F -> end ( ) && & ( * I ) != BB ; ++ I ) ; if ( I != F -> end ( ) ) ++ I ; MachineBasicBlock * LoopBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * RemBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , LoopBB ) ; F -> insert ( I , RemBB ) ; RemBB -> splice ( RemBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; RemBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( LoopBB ) ; BB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( LoopBB ) ;

Register ShiftAmtReg = RI . createVirtualRegister ( & <STR_LIT> ) ;


<s> static bool isCopyMulResult ( MachineBasicBlock :: iterator const & I ) {

if ( I -> getOpcode ( ) == <STR_LIT> ) {


<s> static bool isCopyMulResult ( MachineBasicBlock :: iterator const & I ) { if ( I -> getOpcode ( ) == <STR_LIT> ) { Register SrcReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) ; }


<s> LC = IsSigned ? RTLIB :: SDIVREM_I32 : RTLIB :: UDIVREM_I32 ; break ; } SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( SDValue const & Value : Op -> op_values ( ) ) { Entry . Node = Value ; Entry . Ty = Value . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . IsSExt = IsSigned ; Entry . IsZExt = ! IsSigned ; Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = ( Type * ) StructType :: get ( Ty , Ty ) ; SDLoc dl ( Op ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setLibCallee ( getLibcallCallingConv ( LC ) , RetTy , Callee , std :: move ( Args ) ) . setInRegister ( ) . setSExtResult ( IsSigned ) . setZExtResult ( ! IsSigned ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ; return CallInfo . first ;


<s> unsigned Opcode = Op -> getOpcode ( ) ; assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; bool IsSigned = ( Opcode == <STR_LIT> ) ; EVT VT = Op -> getValueType ( <NUM_LIT> ) ; Type * Ty = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; RTLIB :: Libcall LC ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : LC = IsSigned ? RTLIB :: SDIVREM_I8 : RTLIB :: UDIVREM_I8 ; break ; case <STR_LIT> : LC = IsSigned ? RTLIB :: SDIVREM_I16 : RTLIB :: UDIVREM_I16 ; break ; case <STR_LIT> : LC = IsSigned ? RTLIB :: SDIVREM_I32 : RTLIB :: UDIVREM_I32 ; break ; } SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( SDValue const & Value : Op -> op_values ( ) ) { Entry . Node = Value ; Entry . Ty = Value . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & dl , SelectionDAG & DAG ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; auto CCFunction = CCAssignFnForReturn ( CallConv ) ; CCInfo . AnalyzeReturn ( Outs , CCFunction ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned e = RVLocs . size ( ) ; if ( e > <NUM_LIT> ) { std :: reverse ( RVLocs . begin ( ) , RVLocs . end ( ) ) ; } SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ;

RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ;


<s> unsigned Opc8 ; const SDNode * N = Op . getNode ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( N ) ; assert ( isPowerOf2_32 ( VT . getSizeInBits ( ) ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) { switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : { SDValue Amt = N -> getOperand ( <NUM_LIT> ) ; EVT AmtVT = Amt . getValueType ( ) ; Amt = DAG . getNode ( <STR_LIT> , dl , AmtVT , Amt , DAG . getConstant ( VT . getSizeInBits ( ) - <NUM_LIT> , dl , AmtVT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , Amt ) ; } case <STR_LIT> : { SDValue Amt = N -> getOperand ( <NUM_LIT> ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned e = RVLocs . size ( ) ; if ( e > <NUM_LIT> ) { std :: reverse ( RVLocs . begin ( ) , RVLocs . end ( ) ) ; } SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeList :: FunctionIndex , Attribute :: Naked ) ) { return Chain ; } unsigned RetOpc = ( CallConv == CallingConv :: <ISA_LIT>_INTR || CallConv == CallingConv :: <ISA_LIT>_SIGNAL ) ? <STR_LIT> : <STR_LIT> ; RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) { RetOps . push_back ( Flag ) ;


<s> Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; } const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I = BB -> getParent ( ) -> begin ( ) ; ++ I ; MachineBasicBlock * LoopBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * RemBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , LoopBB ) ; F -> insert ( I , RemBB ) ; RemBB -> splice ( RemBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; RemBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( LoopBB ) ; BB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( LoopBB ) ; unsigned ShiftAmtReg = RI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ShiftAmtReg2 = RI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ShiftReg = RI . createVirtualRegister ( RC ) ; unsigned ShiftReg2 = RI . createVirtualRegister ( RC ) ; unsigned ShiftAmtSrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( ShiftAmtSrcReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( RemBB ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftReg ) . addReg ( SrcReg ) . addMBB ( BB ) . addReg ( ShiftReg2 ) . addMBB ( LoopBB ) ;

BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg ) . addReg ( ShiftAmtSrcReg ) . addMBB ( BB ) . addReg ( ShiftAmtReg2 ) . addMBB ( LoopBB ) ;


<s> } const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I ; for ( I = BB -> getIterator ( ) ; I != F -> end ( ) && & ( * I ) != BB ; ++ I ) ; if ( I != F -> end ( ) ) ++ I ; MachineBasicBlock * LoopBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * RemBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , LoopBB ) ; F -> insert ( I , RemBB ) ; RemBB -> splice ( RemBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; RemBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( LoopBB ) ; BB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( LoopBB ) ; unsigned ShiftAmtReg = RI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ShiftAmtReg2 = RI . createVirtualRegister ( & <STR_LIT> ) ; Register ShiftReg = RI . createVirtualRegister ( RC ) ; Register ShiftReg2 = RI . createVirtualRegister ( RC ) ; Register ShiftAmtSrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( ShiftAmtSrcReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( RemBB ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftReg ) . addReg ( SrcReg ) . addMBB ( BB ) . addReg ( ShiftReg2 ) . addMBB ( LoopBB ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg ) . addReg ( ShiftAmtSrcReg ) . addMBB ( BB ) . addReg ( ShiftAmtReg2 ) . addMBB ( LoopBB ) ; auto ShiftMI = BuildMI ( LoopBB , dl , TII . get ( Opc ) , ShiftReg2 ) . addReg ( ShiftReg ) ; if ( HasRepeatedOperand ) ShiftMI . addReg ( ShiftReg ) ;

BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg2 ) . addReg ( ShiftAmtReg ) . addImm ( <NUM_LIT> ) ;


<s> Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; } const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I ; for ( I = BB -> getIterator ( ) ; I != F -> end ( ) && & ( * I ) != BB ; ++ I ) ; if ( I != F -> end ( ) ) ++ I ; MachineBasicBlock * LoopBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * RemBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , LoopBB ) ; F -> insert ( I , RemBB ) ; RemBB -> splice ( RemBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; RemBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( LoopBB ) ; BB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( LoopBB ) ; unsigned ShiftAmtReg = RI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ShiftAmtReg2 = RI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ShiftReg = RI . createVirtualRegister ( RC ) ; unsigned ShiftReg2 = RI . createVirtualRegister ( RC ) ; unsigned ShiftAmtSrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( ShiftAmtSrcReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( RemBB ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftReg ) . addReg ( SrcReg ) . addMBB ( BB ) . addReg ( ShiftReg2 ) . addMBB ( LoopBB ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg ) . addReg ( ShiftAmtSrcReg ) . addMBB ( BB ) . addReg ( ShiftAmtReg2 ) . addMBB ( LoopBB ) ; auto ShiftMI = BuildMI ( LoopBB , dl , TII . get ( Opc ) , ShiftReg2 ) . addReg ( ShiftReg ) ; if ( HasRepeatedOperand ) ShiftMI . addReg ( ShiftReg ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg2 ) . addReg ( ShiftAmtReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( LoopBB ) ;

BuildMI ( * RemBB , RemBB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addMBB ( BB ) . addReg ( ShiftReg2 ) . addMBB ( LoopBB ) ;


<s> MachineBasicBlock :: iterator I ( MI ) ; ++ I ; if ( isCopyMulResult ( I ) ) ++ I ; if ( isCopyMulResult ( I ) ) ++ I ; BuildMI ( * BB , I , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; return BB ;


<s> unsigned Opc ; const TargetRegisterClass * RC ; bool HasRepeatedOperand = false ; MachineFunction * F = BB -> getParent ( ) ; MachineRegisterInfo & RI = F -> getRegInfo ( ) ; const <ISA_LIT>TargetMachine & TM = ( const <ISA_LIT>TargetMachine & ) getTargetMachine ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; HasRepeatedOperand = true ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; HasRepeatedOperand = true ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; } const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I ; for ( I = BB -> getIterator ( ) ; I != F -> end ( ) && & ( * I ) != BB ; ++ I ) ; if ( I != F -> end ( ) ) ++ I ; MachineBasicBlock * LoopBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * RemBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , LoopBB ) ; F -> insert ( I , RemBB ) ; RemBB -> splice ( RemBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; RemBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( LoopBB ) ;