<s> CurArgIdx = Ins [ VA . getValNo ( ) ] . OrigArgIndex ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue ArgValue1 = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; VA = ArgLocs [ ++ i ] ; SDValue ArgValue2 ; if ( VA . isMemLoc ( ) ) { int FI = MFI -> CreateFixedObject ( <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ; } else { ArgValue2 = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; } ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue2 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else ArgValue = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; } else { const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = AFI -> isThumb1OnlyFunction ( ) ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ;


<s> EVT VT = Op . getValueType ( ) ; if ( VT . isVector ( ) ) return LowerVectorFP_TO_INT ( Op , DAG ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Opc ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } Op = DAG . getNode ( Opc , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ;


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( Subtarget -> useMovt ( ) && RelocM != Reloc :: Static ) { ++ NumMovwMovt ; if ( RelocM == Reloc :: Static ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; unsigned Wrapper = ( RelocM == Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; SDValue Result = DAG . getNode ( Wrapper , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ; return Result ; } unsigned <ISA_LIT>PCLabelIndex = <NUM_LIT> ;


<s> unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * DAG . getContext ( ) , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ;

SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ;


<s> CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; if ( RelocM == Reloc :: PIC_ ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ;

Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ;


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ;

return DAG . getNode ( Opc , dl , VT , Op ) ;


<s> unsigned isLS = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; bool isOnlyStoreBarrier = ( isLL == <NUM_LIT> && isLS == <NUM_LIT> ) ; <STR_LIT> DMBOpt ; if ( isDeviceBarrier ) DMBOpt = isOnlyStoreBarrier ? <STR_LIT> : <STR_LIT> ; else DMBOpt = isOnlyStoreBarrier ? <STR_LIT> : <STR_LIT> ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( DMBOpt , <STR_LIT> ) ) ;


<s> static SDValue LowerMEMBARRIER ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { DebugLoc dl = Op . getDebugLoc ( ) ; if ( ! Subtarget -> hasDataBarrier ( ) ) { assert ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isThumb ( ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } SDValue Op5 = Op . getOperand ( <NUM_LIT> ) ; bool isDeviceBarrier = cast < ConstantSDNode > ( Op5 ) -> getZExtValue ( ) != <NUM_LIT> ;

unsigned isLL = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerMemOpCallTo ( SDValue Chain , SDValue StackPtr , SDValue Arg , DebugLoc dl , SelectionDAG & DAG , const CCValAssign & VA , <STR_LIT> Flags ) const { unsigned LocMemOffset = VA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ;

return DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo :: getStack ( LocMemOffset ) , false , false , <NUM_LIT> ) ;


<s> unsigned LocMemOffset = VA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset ) ;

PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ;


<s> } } if ( ! NewOpc ) { if ( VT == <STR_LIT> ) return SDValue ( ) ; else return Op ; } } DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Op0 ; SDValue Op1 = SkipExtension ( N1 , DAG ) ; if ( ! isMLA ) { Op0 = SkipExtension ( N0 , DAG ) ; assert ( Op0 . getValueType ( ) . is64BitVector ( ) && Op1 . getValueType ( ) . is64BitVector ( ) && <STR_LIT> ) ; return DAG . getNode ( NewOpc , DL , VT , Op0 , Op1 ) ; } SDValue N00 = SkipExtension ( N0 -> getOperand ( <NUM_LIT> ) . getNode ( ) , DAG ) ; SDValue N01 = SkipExtension ( N0 -> getOperand ( <NUM_LIT> ) . getNode ( ) , DAG ) ; EVT Op1VT = Op1 . getValueType ( ) ; return DAG . getNode ( N0 -> getOpcode ( ) , DL , VT , DAG . getNode ( NewOpc , DL , VT , DAG . getNode ( <STR_LIT> , DL , Op1VT , N00 ) , Op1 ) , DAG . getNode ( NewOpc , DL , VT , DAG . getNode ( <STR_LIT> , DL , Op1VT , N01 ) , Op1 ) ) ;


<s> case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return LowerSDIV ( Op , DAG ) ; case <STR_LIT> : return LowerUDIV ( Op , DAG ) ;


<s> case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return LowerSDIV ( Op , DAG ) ; case <STR_LIT> : return LowerUDIV ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerAtomicLoadStore ( Op , DAG ) ; }


<s> DebugLoc dl = Op . getDebugLoc ( ) ; unsigned isRead = ~ cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) & <NUM_LIT> ; if ( ! isRead && ( ! Subtarget -> hasV7Ops ( ) || ! Subtarget -> hasMPExtension ( ) ) ) return Op . getOperand ( <NUM_LIT> ) ; unsigned isData = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Subtarget -> isThumb ( ) ) { isRead = ~ isRead & <NUM_LIT> ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MFI -> setReturnAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } unsigned Reg = MF . addLiveIn ( <STR_LIT> , getRegClassFor ( <STR_LIT> ) ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , Reg , VT ) ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ;

N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ;


<s> if ( VT == <STR_LIT> ) { N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N0 = LowerSDIV_v4i8 ( N0 , N1 , dl , DAG ) ; N2 = LowerSDIV_v4i8 ( N2 , N3 , dl , DAG ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = LowerCONCAT_VECTORS ( N0 , DAG ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; return N0 ;


<s> N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N1 , N1 , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ;


<s> N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N1 , N1 , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ;


<s> const ConstantSDNode * CMOVTrue = dyn_cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ; const ConstantSDNode * CMOVFalse = dyn_cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ; if ( CMOVTrue && CMOVFalse ) { unsigned CMOVTrueVal = CMOVTrue -> getZExtValue ( ) ; unsigned CMOVFalseVal = CMOVFalse -> getZExtValue ( ) ; SDValue True ; SDValue False ; if ( CMOVTrueVal == <NUM_LIT> && CMOVFalseVal == <NUM_LIT> ) { True = SelectTrue ; False = SelectFalse ; } else if ( CMOVTrueVal == <NUM_LIT> && CMOVFalseVal == <NUM_LIT> ) { True = SelectFalse ; False = SelectTrue ; } if ( True . getNode ( ) && False . getNode ( ) ) { EVT VT = Op . getValueType ( ) ; SDValue <ISA_LIT>cc = Cond . getOperand ( <NUM_LIT> ) ; SDValue CCR = Cond . getOperand ( <NUM_LIT> ) ; SDValue Cmp = duplicateCmp ( Cond . getOperand ( <NUM_LIT> ) , DAG ) ; assert ( True . getValueType ( ) == VT ) ; return DAG . getNode ( <STR_LIT> , dl , VT , True , False , <ISA_LIT>cc , CCR , Cmp ) ;


<s> SDValue CCR = Cond . getOperand ( <NUM_LIT> ) ; SDValue Cmp = duplicateCmp ( Cond . getOperand ( <NUM_LIT> ) , DAG ) ; assert ( True . getValueType ( ) == VT ) ; return DAG . getNode ( <STR_LIT> , dl , VT , True , False , <ISA_LIT>cc , CCR , Cmp ) ; } } } Cond = DAG . getNode ( <STR_LIT> , dl , Cond . getValueType ( ) , Cond , DAG . getConstant ( <NUM_LIT> , Cond . getValueType ( ) ) ) ; return DAG . getSelectCC ( dl , Cond , DAG . getConstant ( <NUM_LIT> , Cond . getValueType ( ) ) , SelectTrue , SelectFalse , <STR_LIT> ) ;


<s> if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp ) ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , <STR_LIT> ) ;

SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ;


<s> if ( ! VT . isVector ( ) ) return SDValue ( ) ; assert ( ST -> hasNEON ( ) && <STR_LIT> ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; EVT ShiftVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ;

SDValue NegatedCount = DAG . getNode ( <STR_LIT> , dl , ShiftVT , getZeroVector ( ShiftVT , DAG , dl ) , N -> getOperand ( <NUM_LIT> ) ) ;


<s> DebugLoc dl = N -> getDebugLoc ( ) ; if ( ! VT . isVector ( ) ) return SDValue ( ) ; assert ( ST -> hasNEON ( ) && <STR_LIT> ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; EVT ShiftVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue NegatedCount = DAG . getNode ( <STR_LIT> , dl , ShiftVT , getZeroVector ( ShiftVT , DAG , dl ) , N -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> vshiftInt = ( N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( vshiftInt , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , NegatedCount ) ;


<s> SDValue <ISA_LIT>cc ; assert ( Op . getOpcode ( ) == <STR_LIT> ) ; SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , RevShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ExtraShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> , <ISA_LIT>cc , DAG , dl ) ;

SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ;


<s> SDValue <ISA_LIT>cc ; unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; assert ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) ; SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , RevShAmt ) ;

SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ;


<s> SDValue Chain = DAG . getEntryNode ( ) ; EVT PtrVT = getPointerTy ( ) ; SDValue ThreadPointer = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; if ( model == TLSModel :: InitialExec ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; Chain = Offset . getValue ( <NUM_LIT> ) ;

SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ;


<s> unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; Chain = Offset . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT , Offset , PICLabel ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; } else {

assert ( model == TLSModel :: LocalExec ) ;


<s> DebugLoc dl = GA -> getDebugLoc ( ) ; EVT PtrVT = getPointerTy ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ;

Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ;


<s> if ( VT == <STR_LIT> ) { N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N0 = LowerSDIV_v4i16 ( N0 , N1 , dl , DAG ) ; N2 = LowerSDIV_v4i16 ( N2 , N3 , dl , DAG ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = LowerCONCAT_VECTORS ( N0 , DAG ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , N0 ) ; return N0 ; } N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; SDValue BN1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , BN1 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , BN1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , BN1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ;

N1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ;


<s> SDValue BN1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , BN1 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , BN1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , BN1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N1 , N1 , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ;


<s> <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ;


<s> const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ;


<s> } assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( VT != <STR_LIT> ) return DAG . UnrollVectorOp ( Op . getNode ( ) ) ; unsigned CastOpc ; unsigned Opc ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : CastOpc = <STR_LIT> ; Opc = <STR_LIT> ; break ; case <STR_LIT> :


<s> if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) { if ( VT . getVectorElementType ( ) == <STR_LIT> ) return Op ; return DAG . UnrollVectorOp ( Op . getNode ( ) ) ; } assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( VT != <STR_LIT> ) return DAG . UnrollVectorOp ( Op . getNode ( ) ) ; unsigned CastOpc ; unsigned Opc ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ;


<s> for ( ArrayRef < int > :: iterator I = ShuffleMask . begin ( ) , E = ShuffleMask . end ( ) ; I != E ; ++ I ) VTBLMask . push_back ( DAG . getConstant ( * I , <STR_LIT> ) ) ; if ( V2 . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , & VTBLMask [ <NUM_LIT> ] , <NUM_LIT> ) ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , & VTBLMask [ <NUM_LIT> ] , <NUM_LIT> ) ) ;


<s> break ; case <STR_LIT> : Invert = true ; case <STR_LIT> : TmpOp0 = Op0 ; TmpOp1 = Op1 ; Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , VT , TmpOp1 , TmpOp0 ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , VT , TmpOp0 , TmpOp1 ) ; break ; } } else { switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Invert = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } if ( Opc == <STR_LIT> ) { SDValue AndOp ; if ( <STR_LIT> ( Op1 . getNode ( ) ) ) AndOp = Op0 ; else if ( <STR_LIT> ( Op0 . getNode ( ) ) ) AndOp = Op1 ; if ( AndOp . getNode ( ) && AndOp . getOpcode ( ) == <STR_LIT> ) AndOp = AndOp . getOperand ( <NUM_LIT> ) ; if ( AndOp . getNode ( ) && AndOp . getOpcode ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , VT , AndOp . getOperand ( <NUM_LIT> ) ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , VT , AndOp . getOperand ( <NUM_LIT> ) ) ; Invert = ! Invert ; } } } if ( Swap ) std :: swap ( Op0 , Op1 ) ; SDValue SingleOp ; if ( <STR_LIT> ( Op1 . getNode ( ) ) ) SingleOp = Op0 ; else if ( <STR_LIT> ( Op0 . getNode ( ) ) ) { if ( Opc == <STR_LIT> ) Opc = <STR_LIT> ; else if ( Opc == <STR_LIT> ) Opc = <STR_LIT> ; SingleOp = Op1 ; } SDValue Result ; if ( SingleOp . getNode ( ) ) { switch ( Opc ) { case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , SingleOp ) ; break ; case <STR_LIT> :


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; } if ( Opc == <STR_LIT> ) { SDValue AndOp ; if ( <STR_LIT> ( Op1 . getNode ( ) ) ) AndOp = Op0 ; else if ( <STR_LIT> ( Op0 . getNode ( ) ) ) AndOp = Op1 ; if ( AndOp . getNode ( ) && AndOp . getOpcode ( ) == <STR_LIT> ) AndOp = AndOp . getOperand ( <NUM_LIT> ) ; if ( AndOp . getNode ( ) && AndOp . getOpcode ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , VT , AndOp . getOperand ( <NUM_LIT> ) ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , VT , AndOp . getOperand ( <NUM_LIT> ) ) ; Invert = ! Invert ; } } } if ( Swap ) std :: swap ( Op0 , Op1 ) ; SDValue SingleOp ; if ( <STR_LIT> ( Op1 . getNode ( ) ) ) SingleOp = Op0 ; else if ( <STR_LIT> ( Op0 . getNode ( ) ) ) { if ( Opc == <STR_LIT> ) Opc = <STR_LIT> ; else if ( Opc == <STR_LIT> ) Opc = <STR_LIT> ; SingleOp = Op1 ; } SDValue Result ; if ( SingleOp . getNode ( ) ) { switch ( Opc ) { case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , SingleOp ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , SingleOp ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , SingleOp ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , SingleOp ) ; break ;


<s> RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , bitcastf32Toi32 ( RHS , DAG ) , Mask ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } SDValue LHS1 , LHS2 ; SDValue RHS1 , RHS2 ; expandf64Toi32 ( LHS , DAG , LHS1 , LHS2 ) ; expandf64Toi32 ( RHS , DAG , RHS1 , RHS2 ) ; LHS2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS2 , Mask ) ; RHS2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS2 , Mask ) ; <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; <ISA_LIT>cc = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , <ISA_LIT>cc , LHS1 , LHS2 , RHS1 , RHS2 , Dest } ; return DAG . getNode ( <STR_LIT> , dl , VTList , Ops , <NUM_LIT> ) ; }


<s> else { assert ( NextVA . isMemLoc ( ) ) ; if ( StackPtr . getNode ( ) == <NUM_LIT> ) StackPtr = DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , getPointerTy ( ) ) ;

MemOpChains . push_back ( LowerMemOpCallTo ( Chain , StackPtr , fmrrd . getValue ( <NUM_LIT> ) , dl , DAG , NextVA , Flags ) ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SelectionDAG & DAG = DCI . DAG ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN && BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize <= <NUM_LIT> ) { EVT VbicVT ; SDValue Val = isNEONModifiedImm ( ( ~ SplatBits ) . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , VbicVT , VT . is128BitVector ( ) , OtherModImm ) ; if ( Val . getNode ( ) ) {

SDValue Input = DAG . getNode ( <STR_LIT> , dl , VbicVT , N -> getOperand ( <NUM_LIT> ) ) ;


<s> static SDValue PerformBFICombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI ) { SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N1 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * N11C = dyn_cast < ConstantSDNode > ( N1 . getOperand ( <NUM_LIT> ) ) ; if ( ! N11C ) return SDValue ( ) ; unsigned InvMask = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned LSB = CountTrailingZeros_32 ( ~ InvMask ) ; unsigned Width = ( <NUM_LIT> - CountLeadingZeros_32 ( ~ InvMask ) ) - LSB ; unsigned Mask = ( <NUM_LIT> << Width ) - <NUM_LIT> ; unsigned Mask2 = N11C -> getZExtValue ( ) ;

if ( ( Mask & ( ~ Mask2 ) ) == <NUM_LIT> ) return DCI . DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N1 . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ;


<s> if ( RV . getNode ( ) ) return RV ; } EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . getVectorElementType ( ) != <STR_LIT> || ! hasNormalLoadOperand ( N ) ) return SDValue ( ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned NumElts = VT . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) {

SDValue V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( i ) ) ;


<s> if ( Res . getNode ( ) ) { APInt KnownZero , KnownOne ; DAG . ComputeMaskedBits ( SDValue ( N , <NUM_LIT> ) , KnownZero , KnownOne ) ; if ( KnownZero == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getValueType ( <STR_LIT> ) ) ; else if ( KnownZero == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getValueType ( <STR_LIT> ) ) ; else if ( KnownZero == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getValueType ( <STR_LIT> ) ) ; }


<s> case <STR_LIT> : return PerformADDCCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformADDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformSUBCombine ( N , DCI ) ; case <STR_LIT> : return PerformMULCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformXORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformANDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformBFICombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVRRDCombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVDRRCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformSTORECombine ( N , DCI ) ; case <STR_LIT> : return PerformBUILD_VECTORCombine ( N , DCI ) ; case <STR_LIT> : return PerformInsertEltCombine ( N , DCI ) ;

case <STR_LIT> : return PerformVECTOR_SHUFFLECombine ( N , DCI . DAG ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDNode * Elt = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( VT . getVectorElementType ( ) != <STR_LIT> || ! <STR_LIT> ( Elt ) || cast < LoadSDNode > ( Elt ) -> isVolatile ( ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; DebugLoc dl = N -> getDebugLoc ( ) ; EVT FloatVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; SDValue Vec = DAG . getNode ( <STR_LIT> , dl , FloatVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; DCI . AddToWorklist ( Vec . getNode ( ) ) ; DCI . AddToWorklist ( V . getNode ( ) ) ; SDValue InsElt = DAG . getNode ( <STR_LIT> , dl , FloatVT , Vec , V , N -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , InsElt ) ;


<s> switch ( IntNo ) { case <STR_LIT> : case <STR_LIT> : if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , Cnt ) ) { VShiftOpc = <STR_LIT> ; break ; } if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , true , Cnt ) ) { VShiftOpc = ( IntNo == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; break ; } return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , true , Cnt ) ) break ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , true , Cnt ) ) break ; return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , Cnt ) ) break ; return SDValue ( ) ; case <STR_LIT> : if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , Cnt ) ) break ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , true , true , Cnt ) ) break ; llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; } switch ( IntNo ) { case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : if ( Cnt == VT . getVectorElementType ( ) . getSizeInBits ( ) ) VShiftOpc = <STR_LIT> ; else VShiftOpc = ( IntNo == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> :


<s> int64_t MulAmt = C -> getSExtValue ( ) ; unsigned ShiftAmt = CountTrailingZeros_64 ( MulAmt ) ; ShiftAmt = ShiftAmt & ( <NUM_LIT> - <NUM_LIT> ) ; SDValue V = N -> getOperand ( <NUM_LIT> ) ; DebugLoc DL = N -> getDebugLoc ( ) ; SDValue Res ; MulAmt >>= ShiftAmt ; if ( MulAmt >= <NUM_LIT> ) { if ( isPowerOf2_32 ( MulAmt - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt - <NUM_LIT> ) , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmt + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt + <NUM_LIT> ) , <STR_LIT> ) ) , V ) ; } else return SDValue ( ) ; } else { uint64_t MulAmtAbs = - MulAmt ; if ( isPowerOf2_32 ( MulAmtAbs + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs + <NUM_LIT> ) , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmtAbs - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs - <NUM_LIT> ) , <STR_LIT> ) ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , Res ) ; } else return SDValue ( ) ; } if ( ShiftAmt != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getConstant ( ShiftAmt , <STR_LIT> ) ) ;


<s> } } if ( ! Subtarget -> isThumb1Only ( ) ) { SDValue Result = combineSelectAndUseCommutative ( N , false , DCI ) ; if ( Result . getNode ( ) ) return Result ; } SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) ) return SDValue ( ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget -> hasNEON ( ) && N1 . getOpcode ( ) == <STR_LIT> && VT . isVector ( ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) { APInt SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; BuildVectorSDNode * BVN0 = dyn_cast < BuildVectorSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; APInt SplatBits0 ; if ( BVN0 && BVN0 -> isConstantSplat ( SplatBits0 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { BuildVectorSDNode * BVN1 = dyn_cast < BuildVectorSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ; APInt SplatBits1 ; if ( BVN1 && BVN1 -> isConstantSplat ( SplatBits1 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs && SplatBits0 == ~ SplatBits1 ) { EVT CanonicalVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , CanonicalVT , N0 -> getOperand ( <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> ) , N1 -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Result ) ; } } } if ( Subtarget -> isThumb1Only ( ) || ! Subtarget -> hasV6T2Ops ( ) ) return SDValue ( ) ; DebugLoc DL = N -> getDebugLoc ( ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue MaskOp = N0 . getOperand ( <NUM_LIT> ) ; ConstantSDNode * MaskC = dyn_cast < ConstantSDNode > ( MaskOp ) ; if ( ! MaskC ) return SDValue ( ) ; unsigned Mask = MaskC -> getZExtValue ( ) ; if ( Mask == <NUM_LIT> ) return SDValue ( ) ;


<s> if ( N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) ) return SDValue ( ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget -> hasNEON ( ) && N1 . getOpcode ( ) == <STR_LIT> && VT . isVector ( ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) { APInt SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; BuildVectorSDNode * BVN0 = dyn_cast < BuildVectorSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; APInt SplatBits0 ; if ( BVN0 && BVN0 -> isConstantSplat ( SplatBits0 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { BuildVectorSDNode * BVN1 = dyn_cast < BuildVectorSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ; APInt SplatBits1 ; if ( BVN1 && BVN1 -> isConstantSplat ( SplatBits1 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs && SplatBits0 == ~ SplatBits1 ) { EVT CanonicalVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , CanonicalVT , N0 -> getOperand ( <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> ) , N1 -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Result ) ; } } } if ( Subtarget -> isThumb1Only ( ) || ! Subtarget -> hasV6T2Ops ( ) ) return SDValue ( ) ; DebugLoc DL = N -> getDebugLoc ( ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue MaskOp = N0 . getOperand ( <NUM_LIT> ) ; ConstantSDNode * MaskC = dyn_cast < ConstantSDNode > ( MaskOp ) ; if ( ! MaskC ) return SDValue ( ) ; unsigned Mask = MaskC -> getZExtValue ( ) ; if ( Mask == <NUM_LIT> ) return SDValue ( ) ; SDValue Res ; ConstantSDNode * N1C = dyn_cast < ConstantSDNode > ( N1 ) ; if ( N1C ) { unsigned Val = N1C -> getZExtValue ( ) ; if ( ( Val & ~ Mask ) != Val ) return SDValue ( ) ; if ( <STR_LIT> ( Mask ) ) { Val >>= CountTrailingZeros_32 ( ~ Mask ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N00 , DAG . getConstant ( Val , <STR_LIT> ) , DAG . getConstant ( Mask , <STR_LIT> ) ) ; DCI . CombineTo ( N , Res , false ) ; return SDValue ( ) ;


<s> if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , Cnt ) ) return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , <STR_LIT> ) ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , false , Cnt ) ) { unsigned VShiftOpc = ( N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; return DAG . getNode ( VShiftOpc , N -> getDebugLoc ( ) , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , <STR_LIT> ) ) ; }


<s> unsigned E = ( ToEltSz * NumElems ) / StoreType . getSizeInBits ( ) ; for ( unsigned I = <NUM_LIT> ; I < E ; I ++ ) { SDValue SubVec = DAG . getNode ( <STR_LIT> , DL , StoreType , ShuffWide , DAG . getIntPtrConstant ( I ) ) ; SDValue Ch = DAG . getStore ( St -> getChain ( ) , DL , SubVec , BasePtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , St -> getAlignment ( ) ) ; BasePtr = DAG . getNode ( <STR_LIT> , DL , BasePtr . getValueType ( ) , BasePtr , Increment ) ; Chains . push_back ( Ch ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , & Chains [ <NUM_LIT> ] , Chains . size ( ) ) ; } if ( ! <STR_LIT> ( St ) ) return SDValue ( ) ; if ( StVal . getNode ( ) -> getOpcode ( ) == <STR_LIT> && StVal . getNode ( ) -> hasOneUse ( ) ) { SelectionDAG & DAG = DCI . DAG ; DebugLoc DL = St -> getDebugLoc ( ) ; SDValue BasePtr = St -> getBasePtr ( ) ; SDValue NewST1 = DAG . getStore ( St -> getChain ( ) , DL , StVal . getNode ( ) -> getOperand ( <NUM_LIT> ) , BasePtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , St -> getAlignment ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getStore ( NewST1 . getValue ( <NUM_LIT> ) , DL , StVal . getNode ( ) -> getOperand ( <NUM_LIT> ) , OffsetPtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , std :: min ( <NUM_LIT> , St -> getAlignment ( ) / <NUM_LIT> ) ) ; } if ( StVal . getValueType ( ) != <STR_LIT> || StVal . getNode ( ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ;


<s> if ( ConstVec . getOpcode ( ) != <STR_LIT> || ! isConstVecPow2 ( ConstVec , isSigned , C ) ) return SDValue ( ) ; unsigned IntrinsicOpcode = isSigned ? <STR_LIT> : <STR_LIT> ;

return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , N -> getValueType ( <NUM_LIT> ) , DAG . getConstant ( IntrinsicOpcode , <STR_LIT> ) , N0 , DAG . getConstant ( Log2_64 ( C ) , <STR_LIT> ) ) ;


<s> SelectionDAG & DAG = DCI . DAG ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; unsigned OpOpcode = Op . getNode ( ) -> getOpcode ( ) ; if ( ! Subtarget -> hasNEON ( ) || ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) || ( OpOpcode != <STR_LIT> && OpOpcode != <STR_LIT> ) ) return SDValue ( ) ; uint64_t C ; SDValue ConstVec = N -> getOperand ( <NUM_LIT> ) ;


<s> while ( Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getOpcode ( ) != <STR_LIT> && Op . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned EltSize = Op . getValueType ( ) . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned Imm = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned EltBits ; if ( <STR_LIT> ( Imm , EltBits ) == <NUM_LIT> ) EltSize = <NUM_LIT> ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( EltSize > VT . getVectorElementType ( ) . getSizeInBits ( ) ) return SDValue ( ) ; return DCI . DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , VT , Op ) ;


<s> unsigned Imm = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned EltBits ; if ( <STR_LIT> ( Imm , EltBits ) == <NUM_LIT> ) EltSize = <NUM_LIT> ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( EltSize > VT . getVectorElementType ( ) . getSizeInBits ( ) ) return SDValue ( ) ; return DCI . DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , VT , Op ) ;


<s> if ( Op0 . getOpcode ( ) != <STR_LIT> || Op1 . getOpcode ( ) != <STR_LIT> || Op0 . getNumOperands ( ) != <NUM_LIT> || Op1 . getNumOperands ( ) != <NUM_LIT> ) return SDValue ( ) ; SDValue Concat0Op1 = Op0 . getOperand ( <NUM_LIT> ) ; SDValue Concat1Op1 = Op1 . getOperand ( <NUM_LIT> ) ; if ( Concat0Op1 . getOpcode ( ) != <STR_LIT> || Concat1Op1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! TLI . isTypeLegal ( VT ) || ! TLI . isTypeLegal ( Concat0Op1 . getValueType ( ) ) || ! TLI . isTypeLegal ( Concat1Op1 . getValueType ( ) ) ) return SDValue ( ) ; SDValue NewConcat = DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , VT , Op0 . getOperand ( <NUM_LIT> ) , Op1 . getOperand ( <NUM_LIT> ) ) ; SmallVector < int , <NUM_LIT> > NewMask ;

unsigned NumElts = VT . getVectorNumElements ( ) ;


<s> SDValue NewConcat = DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , VT , Op0 . getOperand ( <NUM_LIT> ) , Op1 . getOperand ( <NUM_LIT> ) ) ; SmallVector < int , <NUM_LIT> > NewMask ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned HalfElts = NumElts / <NUM_LIT> ; ShuffleVectorSDNode * SVN = cast < ShuffleVectorSDNode > ( N ) ; for ( unsigned n = <NUM_LIT> ; n < NumElts ; ++ n ) { int MaskElt = SVN -> getMaskElt ( n ) ; int NewElt = - <NUM_LIT> ;

if ( MaskElt < ( int ) HalfElts ) NewElt = MaskElt ;


<s> static SDValue PerformVMOVDRRCombine ( SDNode * N , SelectionDAG & DAG ) { SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) Op0 = Op0 . getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) Op1 = Op1 . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getNode ( ) == Op1 . getNode ( ) && Op0 . getResNo ( ) == <NUM_LIT> && Op1 . getResNo ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , N -> getValueType ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ;


<s> static SDValue PerformVMOVRRDCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI ) { SDValue InDouble = N -> getOperand ( <NUM_LIT> ) ; if ( InDouble . getOpcode ( ) == <STR_LIT> ) return DCI . CombineTo ( N , InDouble . getOperand ( <NUM_LIT> ) , InDouble . getOperand ( <NUM_LIT> ) ) ; SDNode * InNode = InDouble . getNode ( ) ;

if ( <STR_LIT> ( InNode ) && InNode -> hasOneUse ( ) && InNode -> getValueType ( <NUM_LIT> ) == <STR_LIT> && InNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && ! cast < LoadSDNode > ( InNode ) -> isVolatile ( ) ) {


<s> DebugLoc DL = LD -> getDebugLoc ( ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; SDValue NewLD1 = DAG . getLoad ( <STR_LIT> , DL , LD -> getChain ( ) , BasePtr , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue NewLD2 = DAG . getLoad ( <STR_LIT> , DL , NewLD1 . getValue ( <NUM_LIT> ) , OffsetPtr , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , std :: min ( <NUM_LIT> , LD -> getAlignment ( ) / <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , NewLD2 . getValue ( <NUM_LIT> ) ) ;

SDValue Result = DCI . CombineTo ( N , NewLD1 , NewLD2 ) ;


<s> } SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getMemIntrinsicNode ( NewOp , dl , Tys , Ops . data ( ) , Ops . size ( ) , <STR_LIT> , cast < MemSDNode > ( Node ) -> getMemOperand ( ) ) ; SDValue OpsF [ ] = { Result . getValue ( <NUM_LIT> ) , Result . getValue ( <NUM_LIT> ) } ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OpsF , <NUM_LIT> ) ) ; Results . push_back ( Result . getValue ( <NUM_LIT> ) ) ;


<s> static void ReplaceATOMIC_OP_64 ( SDNode * Node , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG , unsigned NewOp ) { DebugLoc dl = Node -> getDebugLoc ( ) ; assert ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ;

Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ;


<s> case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ;


<s> return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ;


<s> static SDValue SkipExtension ( SDNode * N , SelectionDAG & DAG ) { if ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) return N -> getOperand ( <NUM_LIT> ) ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) return DAG . getLoad ( LD -> getMemoryVT ( ) , N -> getDebugLoc ( ) , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) { SDNode * BVN = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; assert ( BVN -> getOpcode ( ) == <STR_LIT> && BVN -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; unsigned LowElt = DAG . getTargetLoweringInfo ( ) . isBigEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , <STR_LIT> , BVN -> getOperand ( LowElt ) , BVN -> getOperand ( LowElt + <NUM_LIT> ) ) ;


<s> if ( AFI -> isThumb1OnlyFunction ( ) ) RC = & <STR_LIT> ; else RC = & <STR_LIT> ; unsigned VReg = MF . addLiveIn ( GPRArgRegs [ firstRegToSaveIndex ] , RC ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( OrigArg , OffsetFromOrigArg + <NUM_LIT> * i ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FIN , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ) ; } if ( ! MemOps . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOps [ <NUM_LIT> ] , MemOps . size ( ) ) ;

} else AFI -> setVarArgsFrameIndex ( MFI -> CreateFixedObject ( <NUM_LIT> , ArgOffset , ! ForceMutable ) ) ;


<s> SDValue MULOp = findMUL_LOHI ( AddeOp0 ) ; if ( MULOp == SDValue ( ) ) MULOp = findMUL_LOHI ( AddeOp1 ) ; else IsLeftOperandMUL = true ; if ( MULOp == SDValue ( ) ) return SDValue ( ) ; unsigned Opc = MULOp -> getOpcode ( ) ; unsigned FinalOpc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue * HiAdd = nullptr ; SDValue * LoMul = nullptr ; SDValue * LowAdd = nullptr ; if ( ( AddeOp0 != MULOp . getValue ( <NUM_LIT> ) ) && ( AddeOp1 != MULOp . getValue ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( IsLeftOperandMUL ) HiAdd = & AddeOp1 ; else HiAdd = & AddeOp0 ; if ( AddcOp0 == MULOp . getValue ( <NUM_LIT> ) ) { LoMul = & AddcOp0 ; LowAdd = & AddcOp1 ; } if ( AddcOp1 == MULOp . getValue ( <NUM_LIT> ) ) { LoMul = & AddcOp1 ; LowAdd = & AddcOp0 ; } if ( ! LoMul ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( * LowAdd ) ; Ops . push_back ( * HiAdd ) ; SDValue MLALNode = DAG . getNode ( FinalOpc , SDLoc ( AddcNode ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; SDValue HiMLALResult ( MLALNode . getNode ( ) , <NUM_LIT> ) ;

DAG . ReplaceAllUsesOfValueWith ( SDValue ( AddeNode , <NUM_LIT> ) , HiMLALResult ) ;


<s> if ( IsLeftOperandMUL ) HiAdd = & AddeOp1 ; else HiAdd = & AddeOp0 ; if ( AddcOp0 == MULOp . getValue ( <NUM_LIT> ) ) { LoMul = & AddcOp0 ; LowAdd = & AddcOp1 ; } if ( AddcOp1 == MULOp . getValue ( <NUM_LIT> ) ) { LoMul = & AddcOp1 ; LowAdd = & AddcOp0 ; } if ( ! LoMul ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( * LowAdd ) ; Ops . push_back ( * HiAdd ) ; SDValue MLALNode = DAG . getNode ( FinalOpc , SDLoc ( AddcNode ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; SDValue HiMLALResult ( MLALNode . getNode ( ) , <NUM_LIT> ) ;


<s> <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : case <STR_LIT> : { EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } } case <STR_LIT> : { DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Known , Depth + <NUM_LIT> ) ; ConstantSDNode * CI = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; const APInt & Mask = CI -> getAPIntValue ( ) ; Known . Zero &= Mask ; Known . One &= Mask ; return ; } }


<s> case AtomicOrdering :: Unordered : llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : case AtomicOrdering :: Acquire : return nullptr ; case AtomicOrdering :: SequentiallyConsistent : if ( ! Inst -> hasAtomicStore ( ) ) return nullptr ; case AtomicOrdering :: Release : case AtomicOrdering :: AcquireRelease : if ( Subtarget -> preferISHSTBarriers ( ) ) return makeDMB ( Builder , <STR_LIT> ) ; else return makeDMB ( Builder , <STR_LIT> ) ;


<s> return nullptr ; case AtomicOrdering :: SequentiallyConsistent : if ( ! Inst -> hasAtomicStore ( ) ) return nullptr ; case AtomicOrdering :: Release : case AtomicOrdering :: AcquireRelease :

if ( Subtarget -> preferISHSTBarriers ( ) ) return makeDMB ( Builder , <STR_LIT> ) ;


<s> if ( Size >= <NUM_LIT> && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , & Fast ) && Fast ) ) ) { return <STR_LIT> ; } else if ( Size >= <NUM_LIT> && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , & Fast ) && Fast ) ) ) { return <STR_LIT> ; } } return <STR_LIT> ;


<s> if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; case 'h' : if ( Subtarget -> isThumb ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'r' : if ( Subtarget -> isThumb1Only ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; case 'w' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ;


<s> case 'l' : if ( Subtarget -> isThumb ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; case 'h' : if ( Subtarget -> isThumb ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'r' : if ( Subtarget -> isThumb1Only ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; case 'w' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'x' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ;


<s> Info . opc = <STR_LIT> ; auto & DL = I . getCalledFunction ( ) -> getParent ( ) -> getDataLayout ( ) ; unsigned NumElts = <NUM_LIT> ; for ( unsigned ArgI = <NUM_LIT> , ArgE = I . getNumArgOperands ( ) ; ArgI < ArgE ; ++ ArgI ) { Type * ArgTy = I . getArgOperand ( ArgI ) -> getType ( ) ; if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += DL . getTypeSizeInBits ( ArgTy ) / <NUM_LIT> ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Value * AlignArg = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . align = cast < ConstantInt > ( AlignArg ) -> getZExtValue ( ) ; Info . vol = false ; Info . readMem = false ; Info . writeMem = true ; return true ; } case <STR_LIT> : case <STR_LIT> : { auto & DL = I . getCalledFunction ( ) -> getParent ( ) -> getDataLayout ( ) ; PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = DL . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; Info . vol = true ; Info . readMem = true ; Info . writeMem = false ; return true ; } case <STR_LIT> : case <STR_LIT> : { auto & DL = I . getCalledFunction ( ) -> getParent ( ) -> getDataLayout ( ) ; PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ;


<s> assert ( Entry -> getParent ( ) -> getFunction ( ) -> hasFnAttribute ( Attribute :: NoUnwind ) && <STR_LIT> ) ; Entry -> addLiveIn ( * I ) ; BuildMI ( * Entry , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , NewVR ) . addReg ( * I ) ; for ( auto * Exit : Exits ) BuildMI ( * Exit , Exit -> getFirstTerminator ( ) , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , * I ) . addReg ( NewVR ) ;


<s> if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , CCAssignFnForReturn ( CalleeCC , isVarArg ) , CCAssignFnForReturn ( CallerCC , isVarArg ) ) ) return false ; const <ISA_LIT>BaseRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( CalleeCC != CallerCC ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } const <ISA_LIT>FunctionInfo * AFI_Caller = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI_Caller -> getArgRegsSaveSize ( ) ) return false ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , isVarArg ) ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , realArgIdx = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i , ++ realArgIdx ) { CCValAssign & VA = ArgLocs [ i ] ; EVT RegVT = VA . getLocVT ( ) ; SDValue Arg = OutVals [ realArgIdx ] ; <STR_LIT> Flags = Outs [ realArgIdx ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( VA . needsCustom ( ) ) { if ( ! VA . isRegLoc ( ) ) return false ; if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; if ( RegVT == <STR_LIT> ) { if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; } } else if ( ! VA . isRegLoc ( ) ) { if ( ! MatchingStackOffset ( Arg , VA . getLocMemOffset ( ) , Flags , MFI , MRI , TII ) ) return false ; } } } const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( ! parametersInCSRMatch ( MRI , CallerPreserved , ArgLocs , OutVals ) ) return false ;


<s> const SDValue * LowerCheckOp = isLowerSaturate ( LHS1 , RHS1 , TrueVal1 , FalseVal1 , CC1 , * K1 ) ? & Op : isLowerSaturate ( LHS2 , RHS2 , TrueVal2 , FalseVal2 , CC2 , * K2 ) ? & Op2 : nullptr ; const SDValue * UpperCheckOp = isUpperSaturate ( LHS1 , RHS1 , TrueVal1 , FalseVal1 , CC1 , * K1 ) ? & Op : isUpperSaturate ( LHS2 , RHS2 , TrueVal2 , FalseVal2 , CC2 , * K2 ) ? & Op2 : nullptr ; if ( ! UpperCheckOp || ! LowerCheckOp || LowerCheckOp == UpperCheckOp ) return false ; int64_t Val1 = cast < ConstantSDNode > ( * K1 ) -> getSExtValue ( ) ; int64_t Val2 = cast < ConstantSDNode > ( * K2 ) -> getSExtValue ( ) ; int64_t PosVal = std :: max ( Val1 , Val2 ) ; if ( ( ( Val1 > Val2 && UpperCheckOp == & Op ) || ( Val1 < Val2 && UpperCheckOp == & Op2 ) ) && Val1 == ~ Val2 && isPowerOf2_64 ( PosVal + <NUM_LIT> ) ) {


<s> SDValue FalseVal1 = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC1 = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; const SDValue Op2 = isa < ConstantSDNode > ( TrueVal1 ) ? FalseVal1 : TrueVal1 ; if ( Op2 . getOpcode ( ) != <STR_LIT> ) return false ; SDValue LHS2 = Op2 . getOperand ( <NUM_LIT> ) ; SDValue RHS2 = Op2 . getOperand ( <NUM_LIT> ) ; SDValue TrueVal2 = Op2 . getOperand ( <NUM_LIT> ) ; SDValue FalseVal2 = Op2 . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC2 = cast < CondCodeSDNode > ( Op2 . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue * K1 = isa < ConstantSDNode > ( LHS1 ) ? & LHS1 : isa < ConstantSDNode > ( RHS1 ) ? & RHS1 : nullptr ; SDValue * K2 = isa < ConstantSDNode > ( LHS2 ) ? & LHS2 : isa < ConstantSDNode > ( RHS2 ) ? & RHS2 : nullptr ; SDValue K2Tmp = isa < ConstantSDNode > ( TrueVal2 ) ? TrueVal2 : FalseVal2 ; SDValue V1Tmp = ( K1 && * K1 == LHS1 ) ? RHS1 : LHS1 ; SDValue V2Tmp = ( K2 && * K2 == LHS2 ) ? RHS2 : LHS2 ; SDValue V2 = ( K2Tmp == TrueVal2 ) ? FalseVal2 : TrueVal2 ; SDValue V2TmpReg = V2Tmp ; if ( V2Tmp -> getOpcode ( ) == <STR_LIT> ) V2TmpReg = V2Tmp -> getOperand ( <NUM_LIT> ) ;


<s> SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; if ( Subtarget -> isFPOnlySP ( ) && LHS . getValueType ( ) == <STR_LIT> ) { DAG . getTargetLoweringInfo ( ) . softenSetCCOperands ( DAG , <STR_LIT> , LHS , RHS , CC , dl ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; if ( getTargetMachine ( ) . Options . UnsafeFPMath && ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue Result = OptimizeVFPBrcond ( Op , DAG ) ) return Result ; } <STR_LIT> CondCode , CondCode2 ; bool InvalidOnQNaN ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 , InvalidOnQNaN ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl , InvalidOnQNaN ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ;

SDValue Ops [ ] = { Chain , Dest , <ISA_LIT>cc , CCR , Cmp } ;


<s> SDValue NewVal = DAG . getTargetConstant ( ImmVal , DL , <STR_LIT> ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewVal ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } if ( ! ST -> hasNEON ( ) || ( ! IsDouble && ! ST -> useNEONForSinglePrecisionFP ( ) ) ) return SDValue ( ) ; EVT VMovVT ; uint64_t iVal = FPVal . bitcastToAPInt ( ) . getZExtValue ( ) ; if ( IsDouble && ( iVal & <NUM_LIT> ) != ( iVal >> <NUM_LIT> ) ) return SDValue ( ) ; SDValue NewVal = isNEONModifiedImm ( iVal & <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , DAG , SDLoc ( Op ) , VMovVT , false , VMOVModImm ) ; if ( NewVal != SDValue ( ) ) { SDLoc DL ( Op ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , VMovVT , NewVal ) ; if ( IsDouble ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant ) ; SDValue VecFConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecFConstant , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> auto AFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; auto T = const_cast < Type * > ( CP -> getType ( ) ) ; auto C = const_cast < Constant * > ( CP -> getConstVal ( ) ) ; auto M = const_cast < Module * > ( DAG . getMachineFunction ( ) . getFunction ( ) -> getParent ( ) ) ; auto GV = new GlobalVariable ( * M , T , true , GlobalVariable :: InternalLinkage , C , Twine ( DAG . getDataLayout ( ) . getPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine ( DAG . getMachineFunction ( ) . getFunctionNumber ( ) ) + <STR_LIT> + Twine ( AFI -> createPICLabelUId ( ) ) ) ; SDValue GA = DAG . getTargetGlobalAddress ( dyn_cast < GlobalValue > ( GV ) , dl , PtrVT ) ; return LowerGlobalAddress ( GA , DAG ) ; } if ( CP -> isMachineConstantPoolEntry ( ) ) Res = DAG . getTargetConstantPool ( CP -> getMachineCPVal ( ) , PtrVT , CP -> getAlignment ( ) ) ; else Res = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlignment ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res ) ;


<s> auto AFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; auto T = const_cast < Type * > ( CP -> getType ( ) ) ; auto C = const_cast < Constant * > ( CP -> getConstVal ( ) ) ; auto M = const_cast < Module * > ( DAG . getMachineFunction ( ) . getFunction ( ) -> getParent ( ) ) ; auto GV = new GlobalVariable ( * M , T , true , GlobalVariable :: InternalLinkage , C , Twine ( DAG . getDataLayout ( ) . getPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine ( DAG . getMachineFunction ( ) . getFunctionNumber ( ) ) + <STR_LIT> + Twine ( AFI -> createPICLabelUId ( ) ) ) ; SDValue GA = DAG . getTargetGlobalAddress ( dyn_cast < GlobalValue > ( GV ) , dl , PtrVT ) ; return LowerGlobalAddress ( GA , DAG ) ;


<s> if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue ArgValue1 = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; VA = ArgLocs [ ++ i ] ; SDValue ArgValue2 ; if ( VA . isMemLoc ( ) ) { int FI = MFI . CreateFixedObject ( <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ; } else { ArgValue2 = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; } ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue1 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue2 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } else ArgValue = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; } else { const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = AFI -> isThumb1OnlyFunction ( ) ? & <STR_LIT> : & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: SExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: ZExt :


<s> TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Val ; Entry . Ty = Val . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . IsZExt = true ; Args . push_back ( Entry ) ; Entry . Node = Exponent ; Entry . Ty = Exponent . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . IsZExt = true ; Args . push_back ( Entry ) ; Type * LCRTy = Val . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; SDValue InChain = DAG . getEntryNode ( ) ; SDValue TCChain = InChain ; const auto * F = DAG . getMachineFunction ( ) . getFunction ( ) ; bool IsTC = TLI . isInTailCallPosition ( DAG , Op . getNode ( ) , TCChain ) && F -> getReturnType ( ) == LCRTy ; if ( IsTC ) InChain = TCChain ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setCallee ( CallingConv :: <ISA_LIT>_AAPCS_VFP , LCRTy , Callee , std :: move ( Args ) ) . setTailCall ( IsTC ) ; std :: pair < SDValue , SDValue > CI = TLI . LowerCallTo ( CLI ) ;

return ! CI . second . getNode ( ) ? DAG . getRoot ( ) : CI . first ;


<s> Entry . Node = SRet ; Entry . Ty = RetTy -> getPointerTo ( ) ; Entry . IsSExt = false ; Entry . IsZExt = false ; Entry . IsSRet = true ; Args . push_back ( Entry ) ; RetTy = Type :: getVoidTy ( * DAG . getContext ( ) ) ; } ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . IsSExt = false ; Entry . IsZExt = false ; Args . push_back ( Entry ) ; const char * LibcallName = ( ArgVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RTLIB :: Libcall LC = ( ArgVT == <STR_LIT> ) ? RTLIB :: SINCOS_F64 : RTLIB :: SINCOS_F32 ; CallingConv :: ID CC = getLibcallCallingConv ( LC ) ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , getPointerTy ( DL ) ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CC , RetTy , Callee , std :: move ( Args ) ) . setDiscardResult ( ShouldUseSRet ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; if ( ! ShouldUseSRet ) return CallResult . first ; SDValue LoadSin = DAG . getLoad ( ArgVT , dl , CallResult . second , SRet , MachinePointerInfo ( ) ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , PtrVT , SRet , DAG . getIntPtrConstant ( ArgVT . getStoreSize ( ) , dl ) ) ;

SDValue LoadCos = DAG . getLoad ( ArgVT , dl , LoadSin . getValue ( <NUM_LIT> ) , Add , MachinePointerInfo ( ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const { if ( Subtarget -> isTargetDarwin ( ) ) return LowerGlobalTLSAddressDarwin ( Op , DAG ) ; if ( Subtarget -> isTargetWindows ( ) ) return LowerGlobalTLSAddressWindows ( Op , DAG ) ; assert ( Subtarget -> isTargetELF ( ) && <STR_LIT> ) ; GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( Op ) ; if ( DAG . getTarget ( ) . Options . EmulatedTLS ) return LowerToTLSEmulatedModel ( GA , DAG ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GA -> getGlobal ( ) ) ;


<s> if ( Subtarget -> isTargetDarwin ( ) ) return LowerGlobalTLSAddressDarwin ( Op , DAG ) ; if ( Subtarget -> isTargetWindows ( ) ) return LowerGlobalTLSAddressWindows ( Op , DAG ) ; assert ( Subtarget -> isTargetELF ( ) && <STR_LIT> ) ; GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( Op ) ; if ( DAG . getTarget ( ) . Options . EmulatedTLS ) return LowerToTLSEmulatedModel ( GA , DAG ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GA -> getGlobal ( ) ) ;


<s> SDValue DescAddr = LowerGlobalAddressDarwin ( Op , DAG ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue FuncTLVGet = DAG . getLoad ( <STR_LIT> , DL , Chain , DescAddr , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , <NUM_LIT> , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; MachineFunction & F = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = F . getFrameInfo ( ) ; MFI . setAdjustsStack ( true ) ; auto TRI = getTargetMachine ( ) . getSubtargetImpl ( * F . getFunction ( ) ) -> getRegisterInfo ( ) ; auto ARI = static_cast < const <ISA_LIT>RegisterInfo * > ( TRI ) ; const uint32_t * Mask = ARI -> getTLSCallPreservedMask ( DAG . getMachineFunction ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , DescAddr , SDValue ( ) ) ; Chain = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , FuncTLVGet , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getRegisterMask ( Mask ) , Chain . getValue ( <NUM_LIT> ) ) ;

return DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ;


<s> SDValue FuncTLVGet = DAG . getLoad ( <STR_LIT> , DL , Chain , DescAddr , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , <NUM_LIT> , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; MachineFunction & F = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = F . getFrameInfo ( ) ; MFI . setAdjustsStack ( true ) ; auto TRI = getTargetMachine ( ) . getSubtargetImpl ( * F . getFunction ( ) ) -> getRegisterInfo ( ) ;

auto ARI = static_cast < const <ISA_LIT>RegisterInfo * > ( TRI ) ;


<s> const MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * F = MF . getFunction ( ) ; StringRef IntKind = F -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; int64_t LROffset ; if ( IntKind == <STR_LIT> || IntKind == <STR_LIT> || IntKind == <STR_LIT> || IntKind == <STR_LIT> ) LROffset = <NUM_LIT> ; else if ( IntKind == <STR_LIT> || IntKind == <STR_LIT> ) LROffset = <NUM_LIT> ; else report_fatal_error ( <STR_LIT> <STR_LIT> ) ; RetOps . insert ( RetOps . begin ( ) + <NUM_LIT> , DAG . getConstant ( LROffset , DL , <STR_LIT> , false ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RetOps ) ;


<s> unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { if ( Op . getValueType ( ) . isFloatingPoint ( ) ) return SDValue ( ) ; unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { if ( ! Op . getValueType ( ) . isFloatingPoint ( ) ) { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; }


<s> unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue CPAddr ; bool IsPositionIndependent = isPositionIndependent ( ) ; unsigned PCAdj = IsPositionIndependent ? ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; if ( IsPositionIndependent ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; } return Result ; } case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; }


<s> case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCE ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , true ) ; return LowerSDIV ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , false ) ; return LowerUDIV ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerAtomicLoadStore ( Op , DAG ) ; case <STR_LIT> : return LowerFSINCOS ( Op , DAG ) ;


<s> case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCE ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , true ) ; return LowerSDIV ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , false ) ; return LowerUDIV ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ;


<s> SDValue HalfGPRs = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Half ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Arg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } SDValue fmrrd = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Arg ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; } else Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ;


<s> SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; bool InvalidOnQNaN ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 , InvalidOnQNaN ) ; if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { bool swpCmpOps = false ; bool swpVselOps = false ; checkVSELConstraints ( CC , CondCode , swpCmpOps , swpVselOps ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { if ( swpCmpOps ) std :: swap ( LHS , RHS ) ; if ( swpVselOps ) std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl , InvalidOnQNaN ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Result = getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ;


<s> } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; bool InvalidOnQNaN ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 , InvalidOnQNaN ) ; if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { bool swpCmpOps = false ; bool swpVselOps = false ; checkVSELConstraints ( CC , CondCode , swpCmpOps , swpVselOps ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { if ( swpCmpOps ) std :: swap ( LHS , RHS ) ; if ( swpVselOps ) std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl , InvalidOnQNaN ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Result = getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; if ( CondCode2 != <STR_LIT> ) {

SDValue <ISA_LIT>cc2 = DAG . getConstant ( CondCode2 , dl , <STR_LIT> ) ;


<s> SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; assert ( LHS . getSimpleValueType ( ) . isInteger ( ) && <STR_LIT> ) ; assert ( Carry . getOpcode ( ) != <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( LHS . getValueType ( ) , <STR_LIT> ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , DL , VTs , LHS , RHS , Carry ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue TVal = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ;

SDValue <ISA_LIT>cc = DAG . getConstant ( IntCCTo<ISA_LIT>CC ( cast < CondCodeSDNode > ( Cond ) -> get ( ) ) , DL , <STR_LIT> ) ;


<s> assert ( Carry . getOpcode ( ) != <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( LHS . getValueType ( ) , <STR_LIT> ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , DL , VTs , LHS , RHS , Carry ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue TVal = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( IntCCTo<ISA_LIT>CC ( cast < CondCodeSDNode > ( Cond ) -> get ( ) ) , DL , <STR_LIT> ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ;

SDValue Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , Cmp . getValue ( <NUM_LIT> ) , SDValue ( ) ) ;


<s> SDLoc DL ( N ) ; RHS = DAG . getConstant ( - imm , DL , <STR_LIT> ) ; unsigned Opcode = ( N -> getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opcode , DL , N -> getVTList ( ) , N -> getOperand ( <NUM_LIT> ) , RHS ) ; } } } return SDValue ( ) ;


<s> SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( RHS ) ) { int32_t imm = C -> getSExtValue ( ) ; if ( imm < <NUM_LIT> && imm > std :: numeric_limits < int > :: min ( ) ) { SDLoc DL ( N ) ; RHS = DAG . getConstant ( - imm , DL , <STR_LIT> ) ; unsigned Opcode = ( N -> getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opcode , DL , N -> getVTList ( ) , N -> getOperand ( <NUM_LIT> ) , RHS ) ; }


<s> if ( Subtarget -> isThumb1Only ( ) ) return PerformAddeSubeCombine ( N , DCI . DAG , Subtarget ) ; if ( DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; return AddCombineTo64bitUMAAL ( N , DCI , Subtarget ) ;


<s> unsigned Opcode = ( N -> getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ;

return DAG . getNode ( Opcode , DL , N -> getVTList ( ) , N -> getOperand ( <NUM_LIT> ) , RHS , N -> getOperand ( <NUM_LIT> ) ) ;


<s> if ( SplatBitSize <= <NUM_LIT> ) { EVT VbicVT ; SDValue Val = isNEONModifiedImm ( ( ~ SplatBits ) . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , dl , VbicVT , VT . is128BitVector ( ) , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VbicVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Vbic = DAG . getNode ( <STR_LIT> , dl , VbicVT , Input , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vbic ) ; } } } if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , true , DCI ) ) return Result ; if ( SDValue Result = PerformSHLSimplify ( N , DCI , Subtarget ) ) return Result ;


<s> BuildVectorSDNode * BVN = dyn_cast < BuildVectorSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SelectionDAG & DAG = DCI . DAG ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN && BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize <= <NUM_LIT> ) { EVT VbicVT ; SDValue Val = isNEONModifiedImm ( ( ~ SplatBits ) . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , dl , VbicVT , VT . is128BitVector ( ) , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VbicVT , N -> getOperand ( <NUM_LIT> ) ) ;

SDValue Vbic = DAG . getNode ( <STR_LIT> , dl , VbicVT , Input , Val ) ;


<s> SDValue <ISA_LIT>cc ; SDValue NewCmp = get<ISA_LIT>Cmp ( LHS , RHS , <STR_LIT> , <ISA_LIT>cc , DAG , dl ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , LHS , FalseVal , <ISA_LIT>cc , N -> getOperand ( <NUM_LIT> ) , NewCmp ) ; } if ( CC == <STR_LIT> && LHS . getOpcode ( ) == <STR_LIT> && LHS -> hasOneUse ( ) ) { auto * LHS0C = dyn_cast < ConstantSDNode > ( LHS -> getOperand ( <NUM_LIT> ) ) ; auto * LHS1C = dyn_cast < ConstantSDNode > ( LHS -> getOperand ( <NUM_LIT> ) ) ; auto * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ; if ( ( LHS0C && LHS0C -> getZExtValue ( ) == <NUM_LIT> ) && ( LHS1C && LHS1C -> getZExtValue ( ) == <NUM_LIT> ) && ( RHSC && RHSC -> getZExtValue ( ) == <NUM_LIT> ) ) { return DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , LHS -> getOperand ( <NUM_LIT> ) , LHS -> getOperand ( <NUM_LIT> ) , LHS -> getOperand ( <NUM_LIT> ) ) ; } } if ( Res . getNode ( ) ) { KnownBits Known ; DAG . computeKnownBits ( SDValue ( N , <NUM_LIT> ) , Known ) ; if ( Known . Zero == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getValueType ( <STR_LIT> ) ) ; else if ( Known . Zero == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getValueType ( <STR_LIT> ) ) ; else if ( Known . Zero == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getValueType ( <STR_LIT> ) ) ;


<s> return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; break ; } } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue SHL = N -> getOperand ( <NUM_LIT> ) ; auto * C1ShlC2 = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; auto * C2 = dyn_cast < ConstantSDNode > ( SHL . getOperand ( <NUM_LIT> ) ) ; if ( ! C1ShlC2 || ! C2 ) return SDValue ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; N -> dump ( ) ) ; APInt C2Int = C2 -> getAPIntValue ( ) ; APInt C1Int = C1ShlC2 -> getAPIntValue ( ) ; APInt Mask = APInt :: getHighBitsSet ( C2Int . getBitWidth ( ) , C2Int . getBitWidth ( ) - C2 -> getZExtValue ( ) ) ; if ( ( C1Int & Mask ) != C1Int ) return SDValue ( ) ; C1Int . lshrInPlace ( C2Int ) ; unsigned Zeros = C1Int . countLeadingZeros ( ) + C1Int . countTrailingZeros ( ) ; if ( C1Int . getBitWidth ( ) - Zeros > <NUM_LIT> ) return SDValue ( ) ;

Zeros = C2Int . countLeadingZeros ( ) + C2Int . countTrailingZeros ( ) ;


<s> if ( U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; break ; } } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue SHL = N -> getOperand ( <NUM_LIT> ) ; auto * C1ShlC2 = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; auto * C2 = dyn_cast < ConstantSDNode > ( SHL . getOperand ( <NUM_LIT> ) ) ; if ( ! C1ShlC2 || ! C2 ) return SDValue ( ) ;

DEBUG ( dbgs ( ) << <STR_LIT> ; N -> dump ( ) ) ;


<s> unsigned PaddedSize = Size + ( ( RequiredPadding == <NUM_LIT> ) ? <NUM_LIT> : RequiredPadding ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! AFI -> getGlobalsPromotedToConstantPool ( ) . count ( GVar ) && Size > <NUM_LIT> ) if ( AFI -> getPromotedConstpoolIncrease ( ) + PaddedSize - <NUM_LIT> >= ConstpoolPromotionMaxTotal ) return SDValue ( ) ; if ( ! allUsersAreInFunction ( GVar , F ) && ! ( Size <= <NUM_LIT> && allUsersAreInFunctions ( GVar ) ) ) return SDValue ( ) ; if ( RequiredPadding != <NUM_LIT> ) { StringRef S = CDAInit -> getAsString ( ) ; SmallVector < uint8_t , <NUM_LIT> > V ( S . size ( ) ) ; std :: copy ( S . bytes_begin ( ) , S . bytes_end ( ) , V . begin ( ) ) ; while ( RequiredPadding -- ) V . push_back ( <NUM_LIT> ) ; Init = ConstantDataArray :: get ( * DAG . getContext ( ) , V ) ; } auto CPVal = <ISA_LIT>ConstantPoolConstant :: Create ( GVar , Init ) ;

SDValue CPAddr = DAG . getTargetConstantPool ( CPVal , PtrVT , <NUM_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: ReconstructShuffle ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; struct ShuffleSourceInfo { SDValue Vec ; unsigned MinElt = std :: numeric_limits < unsigned > :: max ( ) ; unsigned MaxElt = <NUM_LIT> ; SDValue ShuffleVec ; int WindowBase = <NUM_LIT> ; int WindowScale = <NUM_LIT> ; ShuffleSourceInfo ( SDValue Vec ) : Vec ( Vec ) , ShuffleVec ( Vec ) { } bool operator == ( SDValue OtherVec ) { return Vec == OtherVec ; } } ; SmallVector < ShuffleSourceInfo , <NUM_LIT> > Sources ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = Op . getOperand ( i ) ; if ( V . isUndef ( ) ) continue ; else if ( V . getOpcode ( ) != <STR_LIT> ) { return SDValue ( ) ; } else if ( ! isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { return SDValue ( ) ; } SDValue SourceVec = V . getOperand ( <NUM_LIT> ) ; auto Source = llvm :: find ( Sources , SourceVec ) ; if ( Source == Sources . end ( ) ) Source = Sources . insert ( Sources . end ( ) , ShuffleSourceInfo ( SourceVec ) ) ; unsigned EltNo = cast < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Source -> MinElt = std :: min ( Source -> MinElt , EltNo ) ; Source -> MaxElt = std :: max ( Source -> MaxElt , EltNo ) ; } if ( Sources . size ( ) > <NUM_LIT> ) return SDValue ( ) ; EVT SmallestEltTy = VT . getVectorElementType ( ) ; for ( auto & Source : Sources ) { EVT SrcEltTy = Source . Vec . getValueType ( ) . getVectorElementType ( ) ; if ( SrcEltTy . bitsLT ( SmallestEltTy ) ) SmallestEltTy = SrcEltTy ; } unsigned ResMultiplier = VT . getScalarSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; NumElts = VT . getSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; EVT ShuffleVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SmallestEltTy , NumElts ) ; for ( auto & Src : Sources ) { EVT SrcVT = Src . ShuffleVec . getValueType ( ) ; if ( SrcVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) continue ; EVT EltVT = SrcVT . getVectorElementType ( ) ; unsigned NumSrcElts = VT . getSizeInBits ( ) / EltVT . getSizeInBits ( ) ;

EVT DestVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumSrcElts ) ;