<s> Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Strex , { Lo , Hi , Addr } ) ; } <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Strex = <STR_LIT> ( M , Int , Tys ) ; return Builder . CreateCall ( Strex , { Builder . CreateZExtOrBitCast ( Val , Strex -> getFunctionType ( ) -> getParamType ( <NUM_LIT> ) ) , Addr } ) ;


<s> if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Function * Strex = <STR_LIT> ( M , Int ) ; Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , <STR_LIT> ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , <NUM_LIT> ) , Int32Ty , <STR_LIT> ) ;

if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ;


<s> case Unordered : llvm_unreachable ( <STR_LIT> ) ; case Monotonic : case Release : return nullptr ; case Acquire : case AcquireRelease : case SequentiallyConsistent : return makeDMB ( Builder , <STR_LIT> ) ;


<s> assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( ! isOneConstant ( N -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( ST -> isThumb1Only ( ) ) return SDValue ( ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; unsigned Opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ;

Hi = DAG . getNode ( Opc , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Hi ) ;


<s> static SDValue Expand64BitShift ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * ST ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( N ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( ! isOneConstant ( N -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( ST -> isThumb1Only ( ) ) return SDValue ( ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; unsigned Opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Hi = DAG . getNode ( Opc , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Hi ) ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi . getValue ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ;


<s> SDValue DBZCHK = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getEntryNode ( ) , Or ) ; SDValue Result = LowerWindowsDIVLibCall ( Op , DAG , Signed , DBZCHK ) ; SDValue Lower = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result ) ; SDValue Upper = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , dl , TLI . getPointerTy ( DL ) ) ) ; Upper = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Upper ) ; Results . push_back ( Lower ) ; Results . push_back ( Upper ) ;


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; SDValue DBZCHK = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getEntryNode ( ) , Or ) ; SDValue Result = LowerWindowsDIVLibCall ( Op , DAG , Signed , DBZCHK ) ; SDValue Lower = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result ) ; SDValue Upper = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , dl , TLI . getPointerTy ( DL ) ) ) ; Upper = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Upper ) ; Results . push_back ( Lower ) ; Results . push_back ( Upper ) ;


<s> SDValue Read = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Read . getValue ( <NUM_LIT> ) , Read . getValue ( <NUM_LIT> ) ) ) ; Results . push_back ( Read . getOperand ( <NUM_LIT> ) ) ;


<s> if ( NewFrom != From ) { CombinedToMask |= NewToMask ; V = V . getOperand ( <NUM_LIT> ) ; continue ; } if ( ( NewToMask & CombinedToMask ) . getBoolValue ( ) ) return SDValue ( ) ; if ( BitsProperlyConcatenate ( ToMask , NewToMask ) && BitsProperlyConcatenate ( FromMask , NewFromMask ) ) return V ; if ( BitsProperlyConcatenate ( NewToMask , ToMask ) && BitsProperlyConcatenate ( NewFromMask , FromMask ) ) return V ; CombinedToMask |= NewToMask ; V = V . getOperand ( <NUM_LIT> ) ; }


<s> CombinedToMask |= NewToMask ; V = V . getOperand ( <NUM_LIT> ) ; continue ; } if ( ( NewToMask & CombinedToMask ) . getBoolValue ( ) ) return SDValue ( ) ; if ( BitsProperlyConcatenate ( ToMask , NewToMask ) && BitsProperlyConcatenate ( FromMask , NewFromMask ) ) return V ; if ( BitsProperlyConcatenate ( NewToMask , ToMask ) && BitsProperlyConcatenate ( NewFromMask , FromMask ) ) return V ; CombinedToMask |= NewToMask ; V = V . getOperand ( <NUM_LIT> ) ; }


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RRC = & <STR_LIT> ; if ( Subtarget -> useNEONForSinglePrecisionFP ( ) ) Cost = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RRC = & <STR_LIT> ; Cost = <NUM_LIT> ; break ; case <STR_LIT> : RRC = & <STR_LIT> ; Cost = <NUM_LIT> ; break ; case <STR_LIT> : RRC = & <STR_LIT> ; Cost = <NUM_LIT> ; break ; } return std :: make_pair ( RRC , Cost ) ;


<s> RRC = & <STR_LIT> ; if ( Subtarget -> useNEONForSinglePrecisionFP ( ) ) Cost = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RRC = & <STR_LIT> ; Cost = <NUM_LIT> ; break ; case <STR_LIT> : RRC = & <STR_LIT> ; Cost = <NUM_LIT> ; break ; case <STR_LIT> : RRC = & <STR_LIT> ; Cost = <NUM_LIT> ;


if ( getEffectiveCallingConv ( CallConv , isVarArg ) != CallingConv :: <ISA_LIT>_AAPCS_VFP ) return false ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> << IsHA << <STR_LIT> ; Ty -> dump ( ) ) ; bool IsIntArray = Ty -> isArrayTy ( ) && Ty -> getArrayElementType ( ) -> isIntegerTy ( ) ; return IsHA || IsIntArray ;


<s> if ( LHSID == ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) return LHS ; assert ( LHSID == ( ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> && <STR_LIT> ) ; return RHS ; } SDValue OpLHS , OpRHS ; OpLHS = GeneratePerfectShuffle ( PerfectShuffleTable [ LHSID ] , LHS , RHS , DAG , dl ) ; OpRHS = GeneratePerfectShuffle ( PerfectShuffleTable [ RHSID ] , LHS , RHS , DAG , dl ) ; EVT VT = OpLHS . getValueType ( ) ; switch ( OpNum ) { default : llvm_unreachable ( <STR_LIT> ) ; case OP_VREV : if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; case OP_VDUP0 : case OP_VDUP1 : case OP_VDUP2 : case OP_VDUP3 : return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS , DAG . getConstant ( OpNum - OP_VDUP0 , dl , <STR_LIT> ) ) ; case OP_VEXT1 : case OP_VEXT2 : case OP_VEXT3 : return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS , OpRHS , DAG . getConstant ( OpNum - OP_VEXT1 + <NUM_LIT> , dl , <STR_LIT> ) ) ; case OP_VUZPL : case OP_VUZPR :

return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , OpLHS , OpRHS ) . getValue ( OpNum - OP_VUZPL ) ;


<s> unsigned OpNum = ( PFEntry >> <NUM_LIT> ) & <NUM_LIT> ; unsigned LHSID = ( PFEntry >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned RHSID = ( PFEntry >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; enum { OP_COPY = <NUM_LIT> , OP_VREV , OP_VDUP0 , OP_VDUP1 , OP_VDUP2 , OP_VDUP3 , OP_VEXT1 , OP_VEXT2 , OP_VEXT3 , OP_VUZPL , OP_VUZPR , OP_VZIPL , OP_VZIPR , OP_VTRNL , OP_VTRNR } ; if ( OpNum == OP_COPY ) { if ( LHSID == ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) return LHS ; assert ( LHSID == ( ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> && <STR_LIT> ) ; return RHS ; } SDValue OpLHS , OpRHS ; OpLHS = GeneratePerfectShuffle ( PerfectShuffleTable [ LHSID ] , LHS , RHS , DAG , dl ) ; OpRHS = GeneratePerfectShuffle ( PerfectShuffleTable [ RHSID ] , LHS , RHS , DAG , dl ) ; EVT VT = OpLHS . getValueType ( ) ; switch ( OpNum ) { default : llvm_unreachable ( <STR_LIT> ) ; case OP_VREV : if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; case OP_VDUP0 : case OP_VDUP1 : case OP_VDUP2 :


<s> default : break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C - <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C - <NUM_LIT> , dl , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C - <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C - <NUM_LIT> , dl , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C + <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , dl , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C + <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , dl , <STR_LIT> ) ; } break ; } } } <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; <STR_LIT> CompareType ; switch ( CondCode ) { default : CompareType = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CompareType = <STR_LIT> ; break ; } <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; return DAG . getNode ( CompareType , dl , <STR_LIT> , LHS , RHS ) ;


<s> isInc = false ; Offset = DAG . getConstant ( - RHSC , SDLoc ( Ptr ) , RHS -> getValueType ( <NUM_LIT> ) ) ; return true ; } } isInc = ( Ptr -> getOpcode ( ) == <STR_LIT> ) ; Offset = Ptr -> getOperand ( <NUM_LIT> ) ; return true ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Ptr -> getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( RHSC < <NUM_LIT> && RHSC > - <NUM_LIT> ) { assert ( Ptr -> getOpcode ( ) == <STR_LIT> ) ; isInc = false ; Offset = DAG . getConstant ( - RHSC , SDLoc ( Ptr ) , RHS -> getValueType ( <NUM_LIT> ) ) ;

Base = Ptr -> getOperand ( <NUM_LIT> ) ;


<s> case <STR_LIT> : <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS ) ; OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , LHS ) ; break ; case <STR_LIT> : <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS ) ; OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , LHS ) ; break ; case <STR_LIT> : <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS ) ; OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ;


<s> SDValue FalseHigh = FalseVal . getValue ( <NUM_LIT> ) ; SDValue Low = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FalseLow , TrueLow , <ISA_LIT>cc , CCR , Cmp ) ; SDValue High = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FalseHigh , TrueHigh , <ISA_LIT>cc , CCR , duplicateCmp ( Cmp , DAG ) ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Low , High ) ;


<s> case 'l' : return C_RegisterClass ; case 'w' : return C_RegisterClass ; case 'h' : return C_RegisterClass ; case 'x' : return C_RegisterClass ; case 't' : return C_RegisterClass ; case 'j' : return C_Other ; case 'Q' : return C_Memory ;


<s> bool isSigned = N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = N -> getOperand ( i ) . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * Context ) ; Entry . Node = N -> getOperand ( i ) ; Entry . Ty = ArgTy ; Entry . isSExt = isSigned ; Entry . isZExt = ! isSigned ; Args . push_back ( Entry ) ; } return Args ;


<s> assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ; RTLIB :: Libcall LC ;


<s> unsigned <ISA_LIT>TargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const {

return Subtarget -> useSjLjEH ( ) ? <STR_LIT> : <STR_LIT> ;


<s> unsigned <ISA_LIT>TargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const {


<s> const Function * F = MF . getFunction ( ) ; if ( ( ! IsMemset || ZeroMemset ) && Subtarget -> hasNEON ( ) && ! F -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Size >= <NUM_LIT> && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , & Fast ) && Fast ) ) ) { return <STR_LIT> ; } else if ( Size >= <NUM_LIT> && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , & Fast ) && Fast ) ) ) { return <STR_LIT> ; } }

if ( Size >= <NUM_LIT> ) return <STR_LIT> ;


<s> if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'x' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 't' :


<s> if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'x' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ;


<s> unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> } if ( ! N -> isMachineOpcode ( ) ) return Sched :: RegPressure ; const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; const MCInstrDesc & MCID = TII -> get ( N -> getMachineOpcode ( ) ) ;

if ( MCID . getNumDefs ( ) == <NUM_LIT> ) return Sched :: RegPressure ;


<s> static Constant * getSequentialMask ( IRBuilder < > & Builder , unsigned Start , unsigned NumElts ) { SmallVector < Constant * , <NUM_LIT> > Mask ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; i ++ ) Mask . push_back ( Builder . getInt32 ( Start + i ) ) ; return ConstantVector :: get ( Mask ) ;


<s> for ( unsigned i = <NUM_LIT> ; i < NumElts ; i ++ ) Mask . push_back ( Builder . getInt32 ( Start + i ) ) ;


<s> if ( ! VT . isVector ( ) ) return getPointerTy ( DL ) ; return VT . changeVectorElementTypeToInteger ( ) ;


<s> if ( Ptr -> getOpcode ( ) != <STR_LIT> && Ptr -> getOpcode ( ) != <STR_LIT> ) return false ; Base = Ptr -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Ptr -> getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( RHSC < <NUM_LIT> && RHSC > - <NUM_LIT> ) { assert ( Ptr -> getOpcode ( ) == <STR_LIT> ) ; isInc = false ; Offset = DAG . getConstant ( - RHSC , SDLoc ( Ptr ) , RHS -> getValueType ( <NUM_LIT> ) ) ; return true ; } else if ( RHSC > <NUM_LIT> && RHSC < <NUM_LIT> ) { isInc = Ptr -> getOpcode ( ) == <STR_LIT> ;

Offset = DAG . getConstant ( RHSC , SDLoc ( Ptr ) , RHS -> getValueType ( <NUM_LIT> ) ) ;


<s> SDValue Cmp ; if ( ! isFloatingPointZero ( RHS ) ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ;

else Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ;


<s> SDValue Cmp ; if ( ! isFloatingPointZero ( RHS ) ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; else Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ;


<s> EVT VmovVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Vmov = DAG . getNode ( <STR_LIT> , dl , VmovVT , EncodedVal ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , Vmov ) ;


<s> EVT VmovVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Vmov = DAG . getNode ( <STR_LIT> , dl , VmovVT , EncodedVal ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vmov ) ;


<s> bool <STR_LIT> ( unsigned v ) { if ( v == <NUM_LIT> ) return false ;


<s> bool <STR_LIT> ( unsigned v ) { if ( v == <NUM_LIT> ) return false ; return isShiftedMask_32 ( ~ v ) ;


<s> bool <ISA_LIT>TargetLowering :: isCheapToSpeculateCtlz ( ) const { return Subtarget -> hasV6T2Ops ( ) ;


<s> bool <ISA_LIT>TargetLowering :: isCheapToSpeculateCtlz ( ) const {


<s> bool <ISA_LIT>TargetLowering :: isCheapToSpeculateCttz ( ) const {


<s> return true ; } if ( isZeroOrAllOnes ( N2 , AllOnes ) ) { Invert = true ; OtherOp = N1 ; return true ; } return false ; } case <STR_LIT> : if ( AllOnes ) return false ; case <STR_LIT> : { SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; CC = N -> getOperand ( <NUM_LIT> ) ; if ( CC . getValueType ( ) != <STR_LIT> ) return false ; Invert = ! AllOnes ; if ( AllOnes ) OtherOp = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; else if ( N -> getOpcode ( ) == <STR_LIT> ) OtherOp = DAG . getConstant ( <NUM_LIT> , dl , VT ) ;

else OtherOp = DAG . getConstant ( APInt :: getAllOnesValue ( VT . getSizeInBits ( ) ) , dl , VT ) ;


<s> ConstantSDNode * Lo1 = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( LoElt + <NUM_LIT> ) ) ; ConstantSDNode * Hi1 = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( HiElt + <NUM_LIT> ) ) ; if ( ! Lo0 || ! Hi0 || ! Lo1 || ! Hi1 ) return false ; if ( isSigned ) { if ( Hi0 -> getSExtValue ( ) == Lo0 -> getSExtValue ( ) >> <NUM_LIT> && Hi1 -> getSExtValue ( ) == Lo1 -> getSExtValue ( ) >> <NUM_LIT> ) return true ; } else { if ( Hi0 -> isNullValue ( ) && Hi1 -> isNullValue ( ) ) return true ; } return false ; } if ( N -> getOpcode ( ) != <STR_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { SDNode * Elt = N -> getOperand ( i ) . getNode ( ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Elt ) ) {

unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ;


<s> if ( Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue WrapperOp = Op . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ;

if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( WrapperOp ) ) if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( CP -> getConstVal ( ) ) ) return CFP -> getValueAPF ( ) . isPosZero ( ) ;


<s> else if ( <STR_LIT> ( Op . getNode ( ) ) || <STR_LIT> ( Op . getNode ( ) ) ) { if ( Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue WrapperOp = Op . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( WrapperOp ) ) if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( CP -> getConstVal ( ) ) ) return CFP -> getValueAPF ( ) . isPosZero ( ) ; } } else if ( Op -> getOpcode ( ) == <STR_LIT> && Op -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDValue BitcastOp = Op -> getOperand ( <NUM_LIT> ) ; if ( BitcastOp -> getOpcode ( ) == <STR_LIT> && isNullConstant ( BitcastOp -> getOperand ( <NUM_LIT> ) ) ) return true ; } return false ;


<s> if ( ! Subtarget -> hasVFP3 ( ) ) return false ; if ( VT == <STR_LIT> ) return <STR_LIT> ( Imm ) != - <NUM_LIT> ; if ( VT == <STR_LIT> && ! Subtarget -> isFPOnlySP ( ) ) return <STR_LIT> ( Imm ) != - <NUM_LIT> ;


<s> if ( ! isHomogeneousAggregate ( AT -> getElementType ( ) , Base , SubMembers ) ) return false ; Members += SubMembers * AT -> getNumElements ( ) ; } else if ( Ty -> isFloatTy ( ) ) { if ( Base != HA_UNKNOWN && Base != HA_FLOAT ) return false ; Members = <NUM_LIT> ; Base = HA_FLOAT ; } else if ( Ty -> isDoubleTy ( ) ) { if ( Base != HA_UNKNOWN && Base != HA_DOUBLE ) return false ; Members = <NUM_LIT> ; Base = HA_DOUBLE ; } else if ( auto * VT = dyn_cast < VectorType > ( Ty ) ) { Members = <NUM_LIT> ; switch ( Base ) { case HA_FLOAT : case HA_DOUBLE : return false ;


<s> uint64_t SubMembers = <NUM_LIT> ; if ( ! isHomogeneousAggregate ( AT -> getElementType ( ) , Base , SubMembers ) ) return false ; Members += SubMembers * AT -> getNumElements ( ) ; } else if ( Ty -> isFloatTy ( ) ) { if ( Base != HA_UNKNOWN && Base != HA_FLOAT ) return false ; Members = <NUM_LIT> ; Base = HA_FLOAT ; } else if ( Ty -> isDoubleTy ( ) ) { if ( Base != HA_UNKNOWN && Base != HA_DOUBLE ) return false ; Members = <NUM_LIT> ; Base = HA_DOUBLE ; } else if ( auto * VT = dyn_cast < VectorType > ( Ty ) ) {


<s> if ( ! Subtarget -> isThumb ( ) ) return <STR_LIT> ( AbsImm ) != - <NUM_LIT> ;

if ( Subtarget -> isThumb2 ( ) ) return <STR_LIT> ( AbsImm ) != - <NUM_LIT> ;


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { EVT VT = getValueType ( DL , Ty , true ) ; if ( ! isLegalAddressImmediate ( AM . BaseOffs , VT , Subtarget ) ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case <NUM_LIT> : break ; case <NUM_LIT> : if ( Subtarget -> isThumb1Only ( ) ) return false ; default : if ( AM . BaseOffs ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( Subtarget -> isThumb2 ( ) ) return isLegalT2ScaledAddressingMode ( AM , VT ) ;


<s> bool <ISA_LIT>TargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { if ( ! Subtarget -> isThumb ( ) ) return <STR_LIT> ( std :: abs ( Imm ) ) != - <NUM_LIT> ; if ( Subtarget -> isThumb2 ( ) ) return <STR_LIT> ( std :: abs ( Imm ) ) != - <NUM_LIT> ; return Imm >= <NUM_LIT> && Imm <= <NUM_LIT> ;


<s> if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } return SDValue ( ) ; case <NUM_LIT> : VT = is128Bits ? <STR_LIT> : <STR_LIT> ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( type == OtherModImm ) return SDValue ( ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) {


<s> if ( isVZIPMask ( ShuffleMask , VT , WhichResult ) ) return <STR_LIT> ; isV_UNDEF = true ; if ( isVTRN_v_undef_Mask ( ShuffleMask , VT , WhichResult ) ) return <STR_LIT> ;

if ( isVUZP_v_undef_Mask ( ShuffleMask , VT , WhichResult ) ) return <STR_LIT> ;


<s> unsigned Imm , WhichResult ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ; return ( EltSize >= <NUM_LIT> || ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF ) || ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && isReverseMask ( M , VT ) ) ) ;


<s> if ( VT . getVectorNumElements ( ) == <NUM_LIT> && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( M [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ;

unsigned Cost = ( PFEntry >> <NUM_LIT> ) ;


<s> if ( Val <= <NUM_LIT> || ~ Val <= <NUM_LIT> ) return DAG . getConstant ( Val , dl , <STR_LIT> ) ; } else { if ( <STR_LIT> ( Val ) != - <NUM_LIT> || <STR_LIT> ( ~ Val ) != - <NUM_LIT> ) return DAG . getConstant ( Val , dl , <STR_LIT> ) ; }


<s> EVT VT = ExtVal . getValueType ( ) ; if ( ! isTypeLegal ( VT ) ) return false ; if ( ExtVal -> use_empty ( ) || ! ExtVal -> use_begin ( ) -> isOnlyUserOf ( ExtVal . getNode ( ) ) ) return true ; SDNode * U = * ExtVal -> use_begin ( ) ; if ( ( U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT> ) ) return false ;


<s> if ( ExtVal -> use_empty ( ) || ! ExtVal -> use_begin ( ) -> isOnlyUserOf ( ExtVal . getNode ( ) ) ) return true ;

SDNode * U = * ExtVal -> use_begin ( ) ;


<s> int64_t ElementBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ! getVShiftImm ( Op , ElementBits , Cnt ) ) return false ; return ( Cnt >= <NUM_LIT> && ( isLong ? Cnt - <NUM_LIT> : Cnt ) < ElementBits ) ;


<s> assert ( VT . isVector ( ) && <STR_LIT> ) ;

int64_t ElementBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ;


<s> static bool isVShiftRImm ( SDValue Op , EVT VT , bool isNarrow , bool isIntrinsic , int64_t & Cnt ) { assert ( VT . isVector ( ) && <STR_LIT> ) ;


<s> if ( ! getVShiftImm ( Op , ElementBits , Cnt ) ) return false ; if ( ! isIntrinsic ) return ( Cnt >= <NUM_LIT> && Cnt <= ( isNarrow ? ElementBits / <NUM_LIT> : ElementBits ) ) ; if ( Cnt >= - ( isNarrow ? ElementBits / <NUM_LIT> : ElementBits ) && Cnt <= - <NUM_LIT> ) { Cnt = - Cnt ; return true ; } return false ;


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; if ( M . size ( ) != NumElts && M . size ( ) != NumElts * <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) {

if ( M . size ( ) == NumElts * <NUM_LIT> ) WhichResult = i / NumElts ;


<s> else WhichResult = M [ i ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; j += <NUM_LIT> ) { if ( ( M [ i + j ] >= <NUM_LIT> && ( unsigned ) M [ i + j ] != j + WhichResult ) || ( M [ i + j + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i + j + <NUM_LIT> ] != j + NumElts + WhichResult ) ) return false ; } }

if ( M . size ( ) == NumElts * <NUM_LIT> ) WhichResult = <NUM_LIT> ;


<s> for ( unsigned j = <NUM_LIT> ; j < NumElts ; j += <NUM_LIT> ) { if ( ( M [ i + j ] >= <NUM_LIT> && ( unsigned ) M [ i + j ] != j + WhichResult ) || ( M [ i + j + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i + j + <NUM_LIT> ] != j + WhichResult ) ) return false ; } } if ( M . size ( ) == NumElts * <NUM_LIT> ) WhichResult = <NUM_LIT> ;


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; if ( M . size ( ) != NumElts && M . size ( ) != NumElts * <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) { WhichResult = M [ i ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; ++ j ) { if ( M [ i + j ] >= <NUM_LIT> && ( unsigned ) M [ i + j ] != <NUM_LIT> * j + WhichResult ) return false ; }


<s> for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) { WhichResult = M [ i ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; ++ j ) {

if ( M [ i + j ] >= <NUM_LIT> && ( unsigned ) M [ i + j ] != <NUM_LIT> * j + WhichResult ) return false ;


<s> int MIdx = M [ i + j + k ] ; if ( MIdx >= <NUM_LIT> && ( unsigned ) MIdx != Idx ) return false ; Idx += <NUM_LIT> ; } } } if ( M . size ( ) == NumElts * <NUM_LIT> ) WhichResult = <NUM_LIT> ; if ( VT . is64BitVector ( ) && EltSz == <NUM_LIT> ) return false ; return true ;


<s> WhichResult = M [ i ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; j += Half ) { unsigned Idx = WhichResult ; for ( unsigned k = <NUM_LIT> ; k < Half ; ++ k ) { int MIdx = M [ i + j + k ] ; if ( MIdx >= <NUM_LIT> && ( unsigned ) MIdx != Idx ) return false ; Idx += <NUM_LIT> ; } } } if ( M . size ( ) == NumElts * <NUM_LIT> ) WhichResult = <NUM_LIT> ;

if ( VT . is64BitVector ( ) && EltSz == <NUM_LIT> ) return false ;


<s> static bool isVZIPMask ( ArrayRef < int > M , EVT VT , unsigned & WhichResult ) { unsigned EltSz = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( EltSz == <NUM_LIT> ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( M . size ( ) != NumElts && M . size ( ) != NumElts * <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) {

WhichResult = M [ i ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ;


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; if ( M . size ( ) != NumElts && M . size ( ) != NumElts * <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) { WhichResult = M [ i ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; unsigned Idx = WhichResult * NumElts / <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; j += <NUM_LIT> ) { if ( ( M [ i + j ] >= <NUM_LIT> && ( unsigned ) M [ i + j ] != Idx ) || ( M [ i + j + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i + j + <NUM_LIT> ] != Idx ) ) return false ; Idx += <NUM_LIT> ; } }


<s> static inline bool isZeroOrAllOnes ( SDValue N , bool AllOnes ) { return AllOnes ? isAllOnesConstant ( N ) : isNullConstant ( N ) ;


<s> } return ; case 'L' : if ( Subtarget -> isThumb1Only ( ) ) { if ( CVal >= - <NUM_LIT> && CVal < <NUM_LIT> ) break ; } else if ( Subtarget -> isThumb2 ( ) ) { if ( <STR_LIT> ( - CVal ) != - <NUM_LIT> ) break ; } else { if ( <STR_LIT> ( - CVal ) != - <NUM_LIT> ) break ; } return ; case 'M' : if ( Subtarget -> isThumb ( ) ) { if ( ( CVal >= <NUM_LIT> && CVal <= <NUM_LIT> ) && ( ( CVal & <NUM_LIT> ) == <NUM_LIT> ) ) break ; } else { if ( ( CVal >= <NUM_LIT> && CVal <= <NUM_LIT> ) || ( ( CVal & ( CVal - <NUM_LIT> ) ) == <NUM_LIT> ) ) break ; } return ; case 'N' : if ( Subtarget -> isThumb ( ) ) { if ( CVal >= <NUM_LIT> && CVal <= <NUM_LIT> ) break ; } return ; case 'O' : if ( Subtarget -> isThumb ( ) ) { if ( ( CVal >= - <NUM_LIT> && CVal <= <NUM_LIT> ) && ( ( CVal & <NUM_LIT> ) == <NUM_LIT> ) ) break ; } return ; } Result = DAG . getTargetConstant ( CVal , SDLoc ( Op ) , Op . getValueType ( ) ) ;


<s> if ( ! Subtarget -> hasDataBarrier ( ) ) { assert ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isThumb ( ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } ConstantSDNode * OrdN = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; AtomicOrdering Ord = static_cast < AtomicOrdering > ( OrdN -> getZExtValue ( ) ) ; <STR_LIT> Domain = <STR_LIT> ; if ( Subtarget -> isMClass ( ) ) { Domain = <STR_LIT> ; } else if ( Subtarget -> isSwift ( ) && Ord == Release ) { Domain = <STR_LIT> ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , DAG . getConstant ( Domain , dl , <STR_LIT> ) ) ;


<s> Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; if ( RelocM == Reloc :: Static ) { CPAddr = DAG . getTargetConstantPool ( BA , PtrVT , <NUM_LIT> ) ; } else { unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( BA , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; if ( RelocM == Reloc :: Static ) return Result ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , DL , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , PtrVT , Result , PICLabel ) ;


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; if ( Subtarget -> isFPOnlySP ( ) && LHS . getValueType ( ) == <STR_LIT> ) { DAG . getTargetLoweringInfo ( ) . softenSetCCOperands ( DAG , <STR_LIT> , LHS , RHS , CC , dl ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; if ( getTargetMachine ( ) . Options . UnsafeFPMath && ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ) { SDValue Result = OptimizeVFPBrcond ( Op , DAG ) ; if ( Result . getNode ( ) ) return Result ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ;

SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ;


<s> EVT PTy = getPointerTy ( DAG . getDataLayout ( ) ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Table ) ; SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PTy ) ; Table = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , JTI ) ; Index = DAG . getNode ( <STR_LIT> , dl , PTy , Index , DAG . getConstant ( <NUM_LIT> , dl , PTy ) ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Index , Table ) ; if ( Subtarget -> isThumb2 ( ) ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , Op . getOperand ( <NUM_LIT> ) , JTI ) ; } if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { Addr = DAG . getLoad ( ( EVT ) <STR_LIT> , dl , Chain , Addr , MachinePointerInfo :: getJumpTable ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Addr , Table ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , JTI ) ;


<s> if ( Subtarget -> isThumb2 ( ) ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , Op . getOperand ( <NUM_LIT> ) , JTI ) ; } if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { Addr = DAG . getLoad ( ( EVT ) <STR_LIT> , dl , Chain , Addr , MachinePointerInfo :: getJumpTable ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Addr , Table ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , JTI ) ; } else { Addr = DAG . getLoad ( PTy , dl , Chain , Addr , MachinePointerInfo :: getJumpTable ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , JTI ) ;


<s> InVals . push_back ( ThisVal ) ; continue ; } SDValue Val ; if ( VA . needsCustom ( ) ) { SDValue Lo = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Lo . getValue ( <NUM_LIT> ) ; InFlag = Lo . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; SDValue Hi = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Hi . getValue ( <NUM_LIT> ) ; InFlag = Hi . getValue ( <NUM_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; VA = RVLocs [ ++ i ] ; Lo = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Lo . getValue ( <NUM_LIT> ) ; InFlag = Lo . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Hi = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Hi . getValue ( <NUM_LIT> ) ; InFlag = Hi . getValue ( <NUM_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } } else { Val = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; } switch ( VA . getLocInfo ( ) ) {

default : llvm_unreachable ( <STR_LIT> ) ;


<s> Lo = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Lo . getValue ( <NUM_LIT> ) ; InFlag = Lo . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Hi = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Hi . getValue ( <NUM_LIT> ) ; InFlag = Hi . getValue ( <NUM_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } } else { Val = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val ) ; break ; } InVals . push_back ( Val ) ; }


<s> SDValue Val = DAG . getUNDEF ( <STR_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ;

if ( Op0 . getOpcode ( ) != <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ;


<s> if ( VT . is64BitVector ( ) ) { SDValue Extended = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BitCounts ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Extended , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ;


<s> SDValue Counts16 = lowerCTPOP16BitElements ( Bitcast . getNode ( ) , DAG ) ; SDValue N0 = DAG . getNode ( <STR_LIT> , DL , VT16Bit , Counts16 ) ; SDValue N1 = DAG . getNode ( <STR_LIT> , DL , VT16Bit , Counts16 , N0 ) ; SDValue N2 = DAG . getNode ( <STR_LIT> , DL , VT16Bit , N1 , N1 ) ; if ( VT . is64BitVector ( ) ) { SDValue Extended = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N2 ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Extended , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ;


<s> static SDValue LowerCTTZ ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * ST ) { SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . isVector ( ) ) { assert ( ST -> hasNEON ( ) ) ; SDValue X = N -> getOperand ( <NUM_LIT> ) ; SDValue NX = DAG . getNode ( <STR_LIT> , dl , VT , getZeroVector ( VT , DAG , dl ) , X ) ; SDValue LSB = DAG . getNode ( <STR_LIT> , dl , VT , X , NX ) ; EVT ElemTy = VT . getVectorElementType ( ) ; if ( ElemTy == <STR_LIT> ) { SDValue One = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant ( <NUM_LIT> , dl , ElemTy ) ) ; SDValue Bits = DAG . getNode ( <STR_LIT> , dl , VT , LSB , One ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Bits ) ; } if ( ( ElemTy == <STR_LIT> || ElemTy == <STR_LIT> ) && ( N -> getOpcode ( ) == <STR_LIT> ) ) { unsigned NumBits = ElemTy . getSizeInBits ( ) ; SDValue WidthMinus1 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant ( NumBits - <NUM_LIT> , dl , ElemTy ) ) ; SDValue CTLZ = DAG . getNode ( <STR_LIT> , dl , VT , LSB ) ; return DAG . getNode ( <STR_LIT> , dl , VT , WidthMinus1 , CTLZ ) ; } SDValue Bits ; if ( ElemTy == <STR_LIT> ) { SDValue FF = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Bits = DAG . getNode ( <STR_LIT> , dl , VT , LSB , FF ) ; } else {


<s> assert ( ( Subtarget -> isTargetAEABI ( ) || Subtarget -> isTargetAndroid ( ) ) && <STR_LIT> ) ; unsigned Opcode = Op -> getOpcode ( ) ; assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; bool isSigned = ( Opcode == <STR_LIT> ) ; EVT VT = Op -> getValueType ( <NUM_LIT> ) ; Type * Ty = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; RTLIB :: Libcall LC = getDivRemLibcall ( Op . getNode ( ) , VT . getSimpleVT ( ) . SimpleTy ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args = getDivRemArgList ( Op . getNode ( ) , DAG . getContext ( ) ) ; SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = ( Type * ) StructType :: get ( Ty , Ty , nullptr ) ;


<s> SDValue DBZCHK = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getEntryNode ( ) , Op . getOperand ( <NUM_LIT> ) ) ; return LowerWindowsDIVLibCall ( Op , DAG , Signed , DBZCHK ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerDIV_Windows ( SDValue Op , SelectionDAG & DAG , bool Signed ) const { assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue DBZCHK = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getEntryNode ( ) , Op . getOperand ( <NUM_LIT> ) ) ; return LowerWindowsDIVLibCall ( Op , DAG , Signed , DBZCHK ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerDYNAMIC_STACKALLOC ( SDValue Op , SelectionDAG & DAG ) const { assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; SDValue Words = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Size , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Flag ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , Words , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Chain , Flag ) ; SDValue NewSP = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> ) ;

Chain = NewSP . getValue ( <NUM_LIT> ) ;


<s> Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Chain , Flag ) ; SDValue NewSP = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> ) ; Chain = NewSP . getValue ( <NUM_LIT> ) ;

SDValue Ops [ <NUM_LIT> ] = { NewSP , Chain } ;


<s> SDLoc dl ( Op ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerEH_SJLJ_SETJMP ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; SDValue Val = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Val ) ;


return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ;


<s> return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ;


<s> SDValue RMODE = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FltRounds , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RMODE , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;


<s> } if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue ArgValue1 = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; VA = ArgLocs [ ++ i ] ; SDValue ArgValue2 ; if ( VA . isMemLoc ( ) ) { int FI = MFI -> CreateFixedObject ( <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) , false , false , false , <NUM_LIT> ) ; } else { ArgValue2 = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; } ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue1 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue2 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } else ArgValue = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; } else { const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = AFI -> isThumb1OnlyFunction ( ) ? & <STR_LIT> : & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: SExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: ZExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; }


<s> SDValue SrcVal = Op . getOperand ( <NUM_LIT> ) ; return makeLibCall ( DAG , LC , Op . getValueType ( ) , SrcVal , false , SDLoc ( Op ) ) . first ;


<s> assert ( Op . getValueType ( ) == <STR_LIT> && Subtarget -> isFPOnlySP ( ) && <STR_LIT> ) ; RTLIB :: Libcall LC ; LC = RTLIB :: getFPEXT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; SDValue SrcVal = Op . getOperand ( <NUM_LIT> ) ; return makeLibCall ( DAG , LC , Op . getValueType ( ) , SrcVal , false , SDLoc ( Op ) ) . first ;


<s> LC = RTLIB :: getFPROUND ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; SDValue SrcVal = Op . getOperand ( <NUM_LIT> ) ; return makeLibCall ( DAG , LC , Op . getValueType ( ) , SrcVal , false , SDLoc ( Op ) ) . first ;


<s> if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ;

else LC = RTLIB :: getFPTOUINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ;


<s> SDValue Arg = Op . getOperand ( <NUM_LIT> ) ; EVT ArgVT = Arg . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; Type * RetTy = StructType :: get ( ArgTy , ArgTy , nullptr ) ; auto & DL = DAG . getDataLayout ( ) ; ArgListTy Args ; bool ShouldUseSRet = Subtarget -> isAPCS_ABI ( ) ; SDValue SRet ; if ( ShouldUseSRet ) { const uint64_t ByteSize = DL . getTypeAllocSize ( RetTy ) ; const unsigned StackAlign = DL . getPrefTypeAlignment ( RetTy ) ; int FrameIdx = FrameInfo -> CreateStackObject ( ByteSize , StackAlign , false ) ; SRet = DAG . getFrameIndex ( FrameIdx , TLI . getPointerTy ( DL ) ) ; ArgListEntry Entry ; Entry . Node = SRet ; Entry . Ty = RetTy -> getPointerTo ( ) ; Entry . isSExt = false ; Entry . isZExt = false ; Entry . isSRet = true ; Args . push_back ( Entry ) ; RetTy = Type :: getVoidTy ( * DAG . getContext ( ) ) ; } ArgListEntry Entry ; Entry . Node = Arg ;


<s> const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; if ( Subtarget -> useMovt ( DAG . getMachineFunction ( ) ) ) ++ NumMovwMovt ; unsigned Wrapper = RelocM == Reloc :: PIC_ ? <STR_LIT> : <STR_LIT> ; SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getNode ( Wrapper , dl , PtrVT , G ) ;

if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc dl ( Op ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , UseGOT_PREL ? <STR_LIT> : <STR_LIT> , UseGOT_PREL ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; if ( UseGOT_PREL ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; return Result ;


<s> EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc dl ( Op ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { bool UseGOT_PREL = ! ( GV -> hasHiddenVisibility ( ) || GV -> hasLocalLinkage ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc dl ( Op ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , UseGOT_PREL ? <STR_LIT> : <STR_LIT> , UseGOT_PREL ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; if ( UseGOT_PREL ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; return Result ; } if ( Subtarget -> useMovt ( DAG . getMachineFunction ( ) ) ) { ++ NumMovwMovt ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ;


<s> assert ( Subtarget -> useMovt ( DAG . getMachineFunction ( ) ) && <STR_LIT> ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; const <STR_LIT> TargetFlags = ( GV -> hasDLLImportStorageClass ( ) ? <STR_LIT> : <STR_LIT> ) ;

EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const { assert ( Subtarget -> isTargetELF ( ) && <STR_LIT> ) ; GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( Op ) ; if ( DAG . getTarget ( ) . Options . EmulatedTLS ) return LowerToTLSEmulatedModel ( GA , DAG ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GA -> getGlobal ( ) ) ; switch ( model ) { case TLSModel :: GeneralDynamic : case TLSModel :: LocalDynamic : return LowerToTLSGeneralDynamicModel ( GA , DAG ) ; case TLSModel :: InitialExec : case TLSModel :: LocalExec :

return LowerToTLSExecModels ( GA , DAG , model ) ;


<s> if ( EltTy -> isPointerTy ( ) ) VecTy = VectorType :: get ( DL . getIntPtrType ( EltTy ) , VecTy -> getVectorNumElements ( ) ) ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; IRBuilder < > Builder ( LI ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Type * Int8Ptr = Builder . getInt8PtrTy ( LI -> getPointerAddressSpace ( ) ) ; Ops . push_back ( Builder . CreateBitCast ( LI -> getPointerOperand ( ) , Int8Ptr ) ) ; Ops . push_back ( Builder . getInt32 ( LI -> getAlignment ( ) ) ) ; Type * Tys [ ] = { VecTy , Int8Ptr } ; Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; CallInst * VldN = Builder . CreateCall ( VldnFunc , Ops , <STR_LIT> ) ;

for ( unsigned i = <NUM_LIT> ; i < Shuffles . size ( ) ; i ++ ) {


<s> Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( SI ) ; if ( EltTy -> isPointerTy ( ) ) { Type * IntTy = DL . getIntPtrType ( EltTy ) ; Type * IntVecTy = VectorType :: get ( IntTy , Op0 -> getType ( ) -> getVectorNumElements ( ) ) ; Op0 = Builder . CreatePtrToInt ( Op0 , IntVecTy ) ; Op1 = Builder . CreatePtrToInt ( Op1 , IntVecTy ) ; SubVecTy = VectorType :: get ( IntTy , NumSubElts ) ; } static const <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ;

SmallVector < Value * , <NUM_LIT> > Ops ;


<s> else if ( IntKind == <STR_LIT> || IntKind == <STR_LIT> ) LROffset = <NUM_LIT> ; else report_fatal_error ( <STR_LIT> <STR_LIT> ) ; RetOps . insert ( RetOps . begin ( ) + <NUM_LIT> , DAG . getConstant ( LROffset , DL , <STR_LIT> , false ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RetOps ) ;


<s> EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } case <STR_LIT> : { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; if ( RelocM == Reloc :: PIC_ ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; } return Result ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> :


<s> if ( VT . isVector ( ) ) return LowerVectorINT_TO_FP ( Op , DAG ) ; if ( Subtarget -> isFPOnlySP ( ) && Op . getValueType ( ) == <STR_LIT> ) { RTLIB :: Libcall LC ;

if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getSINTTOFP ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ;


<s> PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , PtrOff ) ; return DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo :: getStack ( DAG . getMachineFunction ( ) , LocMemOffset ) , false , false , <NUM_LIT> ) ;


<s> unsigned LocMemOffset = VA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset , dl ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , PtrOff ) ; return DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo :: getStack ( DAG . getMachineFunction ( ) , LocMemOffset ) , false , false , <NUM_LIT> ) ;


<s> } case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return LowerSDIV ( Op , DAG ) ; case <STR_LIT> : return LowerUDIV ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> static SDValue LowerPREFETCH ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { if ( ! ( Subtarget -> isThumb2 ( ) || ( ! Subtarget -> isThumb1Only ( ) && Subtarget -> hasV5TEOps ( ) ) ) ) return Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; unsigned isRead = ~ cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) & <NUM_LIT> ; if ( ! isRead && ( ! Subtarget -> hasV7Ops ( ) || ! Subtarget -> hasMPExtension ( ) ) ) return Op . getOperand ( <NUM_LIT> ) ; unsigned isData = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Subtarget -> isThumb ( ) ) { isRead = ~ isRead & <NUM_LIT> ; isData = ~ isData & <NUM_LIT> ;


<s> TargetLowering :: ArgListTy Args = getDivRemArgList ( N , DAG . getContext ( ) ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> ; SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; CallLoweringInfo CLI ( DAG ) ; CLI . setChain ( InChain ) . setCallee ( CallingConv :: <ISA_LIT>_AAPCS , RetTy , Callee , std :: move ( Args ) , <NUM_LIT> ) . setSExtResult ( isSigned ) . setZExtResult ( ! isSigned ) . setDebugLoc ( SDLoc ( N ) ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; SDNode * ResNode = CallResult . first . getNode ( ) ; assert ( ResNode -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ;

return ResNode -> getOperand ( <NUM_LIT> ) ;


<s> AFI -> setReturnRegsCount ( RVLocs . size ( ) ) ; for ( unsigned i = <NUM_LIT> , realRVLocIdx = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i , ++ realRVLocIdx ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = OutVals [ realRVLocIdx ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Half = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue HalfGPRs = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Half ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Arg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } SDValue fmrrd = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Arg ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ;

} else Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Arg , Flag ) ;


<s> if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Half = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue HalfGPRs = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Half ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Arg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } SDValue fmrrd = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Arg ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ;


<s> EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; }

unsigned Reg = MF . addLiveIn ( <STR_LIT> , getRegClassFor ( <STR_LIT> ) ) ;


<s> if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ;

SDValue Offset = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ;


<s> static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16 ( SDValue Op , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; SDValue OpLHS = Op . getOperand ( <NUM_LIT> ) ;


<s> SDValue N2 ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , N1 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , N1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ;

N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ;


<s> Y = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Y ) ; Y = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Y ) ; X = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , X , Y ) ; X = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , X ) ; Y = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ;

Y = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Y , Y , Y , Y ) ;


<s> SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { bool swpCmpOps = false ; bool swpVselOps = false ; checkVSELConstraints ( CC , CondCode , swpCmpOps , swpVselOps ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { if ( swpCmpOps ) std :: swap ( LHS , RHS ) ; if ( swpVselOps ) std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Result = getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; if ( CondCode2 != <STR_LIT> ) { SDValue <ISA_LIT>cc2 = DAG . getConstant ( CondCode2 , dl , <STR_LIT> ) ; SDValue Cmp2 = getVFPCmp ( LHS , RHS , DAG , dl ) ;

Result = getCMOV ( dl , VT , Result , TrueVal , <ISA_LIT>cc2 , CCR , Cmp2 , DAG ) ;


<s> } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { bool swpCmpOps = false ; bool swpVselOps = false ; checkVSELConstraints ( CC , CondCode , swpCmpOps , swpVselOps ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { if ( swpCmpOps ) std :: swap ( LHS , RHS ) ; if ( swpVselOps ) std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Result = getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; if ( CondCode2 != <STR_LIT> ) { SDValue <ISA_LIT>cc2 = DAG . getConstant ( CondCode2 , dl , <STR_LIT> ) ; SDValue Cmp2 = getVFPCmp ( LHS , RHS , DAG , dl ) ; Result = getCMOV ( dl , VT , Result , TrueVal , <ISA_LIT>cc2 , CCR , Cmp2 , DAG ) ; }


<s> assert ( Op . getOpcode ( ) == <STR_LIT> ) ; SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , dl , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , RevShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , dl , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ;

SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ExtraShAmt ) ;


<s> SDValue ShAmt = Op . getOperand ( <NUM_LIT> ) ; SDValue <ISA_LIT>cc ; unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; assert ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) ; SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , dl , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , dl , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , RevShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue TrueVal = DAG . getNode ( Opc , dl , VT , ShOpHi , ExtraShAmt ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> , <ISA_LIT>cc , DAG , dl ) ; SDValue Hi = DAG . getNode ( Opc , dl , VT , ShOpHi , ShAmt ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ;

return DAG . getMergeValues ( Ops , dl ) ;


<s> const GlobalValue * GV = GA -> getGlobal ( ) ; SDLoc dl ( GA ) ; SDValue Offset ; SDValue Chain = DAG . getEntryNode ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue ThreadPointer = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; if ( model == TLSModel :: InitialExec ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; Chain = Offset . getValue ( <NUM_LIT> ) ;

SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerToTLSGeneralDynamicModel ( GlobalAddressSDNode * GA , SelectionDAG & DAG ) const { SDLoc dl ( GA ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ;

Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ;


<s> unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ; ArgListTy Args ; ArgListEntry Entry ;


<s> SDLoc dl ( Op ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; SDValue N2 , N3 ; if ( VT == <STR_LIT> ) { N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; N3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; N0 = LowerSDIV_v4i16 ( N0 , N1 , dl , DAG ) ; N2 = LowerSDIV_v4i16 ( N2 , N3 , dl , DAG ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ;


<s> EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ;


<s> SDLoc dl ( Op ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ;


<s> } unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == <NUM_LIT> ) { unsigned PFIndexes [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ; else PFIndexes [ i ] = ShuffleMask [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; } if ( EltSize >= <NUM_LIT> ) { EVT EltVT = EVT :: getFloatingPointVT ( EltSize ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumElts ) ; V1 = DAG . getNode ( <STR_LIT> , dl , VecVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , VecVT , V2 ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) Ops . push_back ( DAG . getUNDEF ( EltVT ) ) ; else Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , ShuffleMask [ i ] < ( int ) NumElts ? V1 : V2 , DAG . getConstant ( ShuffleMask [ i ] & ( NumElts - <NUM_LIT> ) , dl , <STR_LIT> ) ) ) ; } SDValue Val = DAG . getNode ( <STR_LIT> , dl , VecVT , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Val ) ; } if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && isReverseMask ( ShuffleMask , VT ) ) return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16 ( Op , DAG ) ; if ( VT == <STR_LIT> ) { SDValue NewOp = LowerVECTOR_SHUFFLEv8i8 ( Op , ShuffleMask , DAG ) ;

if ( NewOp . getNode ( ) ) return NewOp ;


<s> if ( V2 . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VTBLMask ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VTBLMask ) ) ;


<s> TmpOp0 = Op0 ; TmpOp1 = Op1 ; Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , CmpVT , TmpOp1 , TmpOp0 ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , CmpVT , TmpOp0 , TmpOp1 ) ; break ; case <STR_LIT> : Invert = true ; case <STR_LIT> : TmpOp0 = Op0 ; TmpOp1 = Op1 ; Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , CmpVT , TmpOp1 , TmpOp0 ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , CmpVT , TmpOp0 , TmpOp1 ) ; break ; } } else { switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Invert = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } if ( Opc == <STR_LIT> ) { SDValue AndOp ; if ( <STR_LIT> ( Op1 . getNode ( ) ) ) AndOp = Op0 ; else if ( <STR_LIT> ( Op0 . getNode ( ) ) ) AndOp = Op1 ; if ( AndOp . getNode ( ) && AndOp . getOpcode ( ) == <STR_LIT> ) AndOp = AndOp . getOperand ( <NUM_LIT> ) ; if ( AndOp . getNode ( ) && AndOp . getOpcode ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , CmpVT , AndOp . getOperand ( <NUM_LIT> ) ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , CmpVT , AndOp . getOperand ( <NUM_LIT> ) ) ; Invert = ! Invert ; } } } if ( Swap ) std :: swap ( Op0 , Op1 ) ; SDValue SingleOp ; if ( <STR_LIT> ( Op1 . getNode ( ) ) ) SingleOp = Op0 ; else if ( <STR_LIT> ( Op0 . getNode ( ) ) ) { if ( Opc == <STR_LIT> ) Opc = <STR_LIT> ; else if ( Opc == <STR_LIT> ) Opc = <STR_LIT> ; SingleOp = Op1 ; } SDValue Result ; if ( SingleOp . getNode ( ) ) { switch ( Opc ) { case <STR_LIT> :

Result = DAG . getNode ( <STR_LIT> , dl , CmpVT , SingleOp ) ; break ;


<s> SDLoc dl ( Op ) ; const auto & DL = DAG . getDataLayout ( ) ; const auto & TLI = DAG . getTargetLoweringInfo ( ) ; const char * Name = nullptr ; if ( Signed ) Name = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Name = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue ES = DAG . getExternalSymbol ( Name , TLI . getPointerTy ( DL ) ) ; <ISA_LIT>TargetLowering :: ArgListTy Args ; for ( auto AI : { <NUM_LIT> , <NUM_LIT> } ) { ArgListEntry Arg ; Arg . Node = Op . getOperand ( AI ) ;

Arg . Ty = Arg . Node . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ;


<s> static SDValue LowerWRITE_REGISTER ( SDValue Op , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; SDValue WriteValue = Op -> getOperand ( <NUM_LIT> ) ; assert ( WriteValue . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , WriteValue , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , WriteValue , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Ops [ ] = { Op -> getOperand ( <NUM_LIT> ) , Op -> getOperand ( <NUM_LIT> ) , Lo , Hi } ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ops ) ;


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , WriteValue , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , WriteValue , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;

SDValue Ops [ ] = { Op -> getOperand ( <NUM_LIT> ) , Op -> getOperand ( <NUM_LIT> ) , Lo , Hi } ;


<s> SDValue FVal = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; EVT VT = Op . getValueType ( ) ; SDValue Overflow = DAG . getNode ( <STR_LIT> , dl , VT , TVal , FVal , <ISA_LIT>cc , CCR , OverflowCmp ) ;

SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ;


<s> if ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isThumb ( ) ) { Function * MCR = llvm :: <STR_LIT> ( M , <STR_LIT> ) ; Value * args [ <NUM_LIT> ] = { Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) } ; return Builder . CreateCall ( MCR , args ) ;


<s> Function * MCR = llvm :: <STR_LIT> ( M , <STR_LIT> ) ; Value * args [ <NUM_LIT> ] = { Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) } ; return Builder . CreateCall ( MCR , args ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } } else { Function * DMB = llvm :: <STR_LIT> ( M , <STR_LIT> ) ;

Domain = Subtarget -> isMClass ( ) ? <STR_LIT> : Domain ;


<s> if ( ! Subtarget -> supportsTailCall ( ) ) return false ; auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( <STR_LIT> ) ;

if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == <STR_LIT> ) return false ;


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! Subtarget -> supportsTailCall ( ) ) return false ; auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( <STR_LIT> ) ; if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == <STR_LIT> ) return false ;


<s> bool RHSSeenZero = false ; bool RHSOk = canChangeToInt ( RHS , RHSSeenZero , Subtarget ) ; if ( LHSOk && RHSOk && ( LHSSeenZero || RHSSeenZero ) ) { if ( CC == <STR_LIT> ) CC = <STR_LIT> ; else if ( CC == <STR_LIT> ) CC = <STR_LIT> ; SDValue Mask = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue <ISA_LIT>cc ; if ( LHS . getValueType ( ) == <STR_LIT> ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , bitcastf32Toi32 ( LHS , DAG ) , Mask ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , bitcastf32Toi32 ( RHS , DAG ) , Mask ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } SDValue LHS1 , LHS2 ; SDValue RHS1 , RHS2 ; expandf64Toi32 ( LHS , DAG , LHS1 , LHS2 ) ;

expandf64Toi32 ( RHS , DAG , RHS1 , RHS2 ) ;


<s> FromMask = APInt :: getLowBitsSet ( ToMask . getBitWidth ( ) , ToMask . countPopulation ( ) ) ; if ( From -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( From -> getOperand ( <NUM_LIT> ) ) ) { APInt Shift = cast < ConstantSDNode > ( From -> getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; assert ( Shift . getLimitedValue ( ) < <NUM_LIT> && <STR_LIT> ) ;

FromMask <<= Shift . getLimitedValue ( <NUM_LIT> ) ;


<s> static SDValue ParseBFI ( SDNode * N , APInt & ToMask , APInt & FromMask ) { assert ( N -> getOpcode ( ) == <STR_LIT> ) ; SDValue From = N -> getOperand ( <NUM_LIT> ) ; ToMask = ~ cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; FromMask = APInt :: getLowBitsSet ( ToMask . getBitWidth ( ) , ToMask . countPopulation ( ) ) ; if ( From -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( From -> getOperand ( <NUM_LIT> ) ) ) { APInt Shift = cast < ConstantSDNode > ( From -> getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; assert ( Shift . getLimitedValue ( ) < <NUM_LIT> && <STR_LIT> ) ; FromMask <<= Shift . getLimitedValue ( <NUM_LIT> ) ; From = From -> getOperand ( <NUM_LIT> ) ; } return From ;


<s> SDValue fmrrd = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Arg ) ; unsigned id = Subtarget -> isLittle ( ) ? <NUM_LIT> : <NUM_LIT> ; RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , fmrrd . getValue ( id ) ) ) ; if ( NextVA . isRegLoc ( ) ) RegsToPass . push_back ( std :: make_pair ( NextVA . getLocReg ( ) , fmrrd . getValue ( <NUM_LIT> - id ) ) ) ; else { assert ( NextVA . isMemLoc ( ) ) ; if ( ! StackPtr . getNode ( ) ) StackPtr = DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , getPointerTy ( DAG . getDataLayout ( ) ) ) ; MemOpChains . push_back ( LowerMemOpCallTo ( Chain , StackPtr , fmrrd . getValue ( <NUM_LIT> - id ) , dl , DAG , NextVA , Flags ) ) ;


<s> SelectionDAG & DAG = DCI . DAG ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN && BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize <= <NUM_LIT> ) { EVT VbicVT ; SDValue Val = isNEONModifiedImm ( ( ~ SplatBits ) . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , dl , VbicVT , VT . is128BitVector ( ) , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VbicVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Vbic = DAG . getNode ( <STR_LIT> , dl , VbicVT , Input , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vbic ) ; } } } if ( ! Subtarget -> isThumb1Only ( ) ) {

SDValue Result = combineSelectAndUseCommutative ( N , true , DCI ) ;


<s> if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN && BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize <= <NUM_LIT> ) { EVT VbicVT ; SDValue Val = isNEONModifiedImm ( ( ~ SplatBits ) . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , dl , VbicVT , VT . is128BitVector ( ) , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VbicVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Vbic = DAG . getNode ( <STR_LIT> , dl , VbicVT , Input , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vbic ) ; } } } if ( ! Subtarget -> isThumb1Only ( ) ) { SDValue Result = combineSelectAndUseCommutative ( N , true , DCI ) ; if ( Result . getNode ( ) ) return Result ;


<s> SDValue V = N -> getOperand ( Idx ) ; if ( V . getOpcode ( ) == <STR_LIT> ) continue ; if ( V . getOpcode ( ) == <STR_LIT> && V -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ; else { V = DAG . getNode ( <STR_LIT> , SDLoc ( V ) , <STR_LIT> , V ) ; DCI . AddToWorklist ( V . getNode ( ) ) ; } SDValue LaneIdx = DAG . getConstant ( Idx , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , VecVT , Vec , V , LaneIdx ) ; } Vec = DAG . getNode ( <STR_LIT> , dl , VT , Vec ) ; DCI . AddToWorklist ( Vec . getNode ( ) ) ;


<s> unsigned Mask2 = N11C -> getZExtValue ( ) ; if ( ( Mask & ( ~ Mask2 ) ) == <NUM_LIT> ) return DCI . DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N1 . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; } else if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue CombineBFI = FindBFIToCombineWith ( N ) ; if ( CombineBFI == SDValue ( ) ) return SDValue ( ) ; APInt ToMask1 , FromMask1 ; SDValue From1 = ParseBFI ( N , ToMask1 , FromMask1 ) ; APInt ToMask2 , FromMask2 ; SDValue From2 = ParseBFI ( CombineBFI . getNode ( ) , ToMask2 , FromMask2 ) ; assert ( From1 == From2 ) ; ( void ) From2 ; DCI . DAG . ReplaceAllUsesWith ( CombineBFI , CombineBFI . getOperand ( <NUM_LIT> ) ) ; APInt NewFromMask = FromMask1 | FromMask2 ;


<s> static SDValue PerformBUILD_VECTORCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { SelectionDAG & DAG = DCI . DAG ; if ( N -> getNumOperands ( ) == <NUM_LIT> ) { SDValue RV = PerformVMOVDRRCombine ( N , DAG ) ; if ( RV . getNode ( ) ) return RV ; } EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . getVectorElementType ( ) != <STR_LIT> || ! hasNormalLoadOperand ( N ) ) return SDValue ( ) ; SDLoc dl ( N ) ;

SmallVector < SDValue , <NUM_LIT> > Ops ;


<s> if ( R ) return R ; } SDValue Res ; if ( CC == <STR_LIT> && FalseVal == RHS && FalseVal != LHS ) { Res = DAG . getNode ( <STR_LIT> , dl , VT , LHS , TrueVal , <ISA_LIT>cc , N -> getOperand ( <NUM_LIT> ) , Cmp ) ; } else if ( CC == <STR_LIT> && TrueVal == RHS ) { SDValue <ISA_LIT>cc ; SDValue NewCmp = get<ISA_LIT>Cmp ( LHS , RHS , <STR_LIT> , <ISA_LIT>cc , DAG , dl ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , LHS , FalseVal , <ISA_LIT>cc , N -> getOperand ( <NUM_LIT> ) , NewCmp ) ; } if ( Res . getNode ( ) ) { APInt KnownZero , KnownOne ; DAG . computeKnownBits ( SDValue ( N , <NUM_LIT> ) , KnownZero , KnownOne ) ;

if ( KnownZero == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getValueType ( <STR_LIT> ) ) ;


<s> SDValue Op0 = CMOV -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = CMOV -> getOperand ( <NUM_LIT> ) ; auto CCNode = cast < ConstantSDNode > ( CMOV -> getOperand ( <NUM_LIT> ) ) ; auto CC = CCNode -> getAPIntValue ( ) . getLimitedValue ( ) ; SDValue CmpZ = CMOV -> getOperand ( <NUM_LIT> ) ; if ( ! isNullConstant ( CmpZ -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; assert ( CmpZ -> getOpcode ( ) == <STR_LIT> ) ; SDValue And = CmpZ -> getOperand ( <NUM_LIT> ) ; if ( And -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * AndC = dyn_cast < ConstantSDNode > ( And -> getOperand ( <NUM_LIT> ) ) ; if ( ! AndC || ! AndC -> getAPIntValue ( ) . isPowerOf2 ( ) ) return SDValue ( ) ; SDValue X = And -> getOperand ( <NUM_LIT> ) ; if ( CC == <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; } else { assert ( CC == <STR_LIT> && <STR_LIT> ) ; } if ( Op1 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * OrC = dyn_cast < ConstantSDNode > ( Op1 -> getOperand ( <NUM_LIT> ) ) ; if ( ! OrC ) return SDValue ( ) ; SDValue Y = Op1 -> getOperand ( <NUM_LIT> ) ; if ( Op0 != Y ) return SDValue ( ) ; APInt OrCI = OrC -> getAPIntValue ( ) ; unsigned Heuristic = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( OrCI . countPopulation ( ) > Heuristic ) return SDValue ( ) ; APInt KnownZero , KnownOne ; computeKnownBits ( DAG , Y , KnownZero , KnownOne ) ; if ( ( OrCI & KnownZero ) != OrCI ) return SDValue ( ) ; SDValue V = Y ; SDLoc dl ( X ) ; EVT VT = X . getValueType ( ) ; unsigned BitInX = AndC -> getAPIntValue ( ) . logBase2 ( ) ; if ( BitInX != <NUM_LIT> ) { X = DAG . getNode ( <STR_LIT> , dl , VT , X , DAG . getConstant ( BitInX , dl , VT ) ) ; } for ( unsigned BitInY = <NUM_LIT> , NumActiveBits = OrCI . getActiveBits ( ) ; BitInY < NumActiveBits ; ++ BitInY ) { if ( OrCI [ BitInY ] == <NUM_LIT> ) continue ; APInt Mask ( VT . getSizeInBits ( ) , <NUM_LIT> ) ; Mask . setBit ( BitInY ) ; V = DAG . getNode ( <STR_LIT> , dl , VT , V , X , DAG . getConstant ( ~ Mask , dl , VT ) ) ;


<s> case <STR_LIT> : return PerformVDIVCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformLOADCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformVLDCombine ( N , DCI ) ; case <STR_LIT> : return Perform<ISA_LIT>BUILD_VECTORCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformVLDCombine ( N , DCI ) ; default : break ; } break ; } return SDValue ( ) ;


<s> switch ( IntNo ) { case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; } SDLoc dl ( N ) ; return DAG . getNode ( VShiftOpc , dl , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , dl , <STR_LIT> ) ) ; } case <STR_LIT> : { EVT VT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; int64_t Cnt ; unsigned VShiftOpc = <NUM_LIT> ; if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , Cnt ) ) VShiftOpc = <STR_LIT> ; else if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , true , Cnt ) ) VShiftOpc = <STR_LIT> ; else { llvm_unreachable ( <STR_LIT> ) ; } SDLoc dl ( N ) ; return DAG . getNode ( VShiftOpc , dl , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , dl , <STR_LIT> ) ) ; }


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( <STR_LIT> ( N ) && VT . isVector ( ) && DCI . DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return CombineBaseUpdate ( N , DCI ) ;


<s> SDValue V = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue Res ; MulAmt >>= ShiftAmt ; if ( MulAmt >= <NUM_LIT> ) { if ( isPowerOf2_32 ( MulAmt - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt - <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmt + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt + <NUM_LIT> ) , DL , <STR_LIT> ) ) , V ) ; } else return SDValue ( ) ; } else { uint64_t MulAmtAbs = - MulAmt ; if ( isPowerOf2_32 ( MulAmtAbs + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs + <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ;

} else if ( isPowerOf2_32 ( MulAmtAbs - <NUM_LIT> ) ) {


<s> bool HasAnyUndefs ; APInt SplatBits0 , SplatBits1 ; BuildVectorSDNode * BVN0 = dyn_cast < BuildVectorSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; BuildVectorSDNode * BVN1 = dyn_cast < BuildVectorSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ; if ( BVN0 && BVN0 -> isConstantSplat ( SplatBits0 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { if ( BVN1 && BVN1 -> isConstantSplat ( SplatBits1 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { if ( SplatBits0 . getBitWidth ( ) == SplatBits1 . getBitWidth ( ) && SplatBits0 == ~ SplatBits1 ) { EVT CanonicalVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , CanonicalVT , N0 -> getOperand ( <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> ) , N1 -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Result ) ; } } } } if ( Subtarget -> isThumb1Only ( ) || ! Subtarget -> hasV6T2Ops ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue MaskOp = N0 . getOperand ( <NUM_LIT> ) ; ConstantSDNode * MaskC = dyn_cast < ConstantSDNode > ( MaskOp ) ; if ( ! MaskC ) return SDValue ( ) ; unsigned Mask = MaskC -> getZExtValue ( ) ; if ( Mask == <NUM_LIT> ) return SDValue ( ) ; SDValue Res ; ConstantSDNode * N1C = dyn_cast < ConstantSDNode > ( N1 ) ; if ( N1C ) { unsigned Val = N1C -> getZExtValue ( ) ; if ( ( Val & ~ Mask ) != Val ) return SDValue ( ) ; if ( <STR_LIT> ( Mask ) ) { Val >>= countTrailingZeros ( ~ Mask ) ;

Res = DAG . getNode ( <STR_LIT> , DL , VT , N00 , DAG . getConstant ( Val , DL , <STR_LIT> ) , DAG . getConstant ( Mask , DL , <STR_LIT> ) ) ;


<s> SDLoc dl ( N ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> ; unsigned IntrinsicOpcode = isSigned ? <STR_LIT> : <STR_LIT> ; SDValue FixConv = DAG . getNode ( <STR_LIT> , dl , NumLanes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> , DAG . getConstant ( IntrinsicOpcode , dl , <STR_LIT> ) , Op -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( C , dl , <STR_LIT> ) ) ; if ( IntBits < FloatBits ) FixConv = DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , FixConv ) ;