<s> SDValue WriteValue [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; Ops . insert ( Ops . begin ( ) + <NUM_LIT> , WriteValue , WriteValue + <NUM_LIT> ) ; } Ops . push_back ( getAL ( CurDAG , DL ) ) ; Ops . push_back ( CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; ReplaceNode ( N , CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , Ops ) ) ; return true ; } std :: string SpecialReg = RegString -> getString ( ) . lower ( ) ; int BankedReg = getBankedRegisterMask ( SpecialReg ) ; if ( BankedReg != - <NUM_LIT> ) { Ops = { CurDAG -> getTargetConstant ( BankedReg , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( IsThumb2 ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , Ops ) ) ; return true ; } unsigned Opcode = StringSwitch < unsigned > ( SpecialReg ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Opcode ) { if ( ! Subtarget -> hasVFP2 ( ) ) return false ; Ops = { N -> getOperand ( <NUM_LIT> ) , getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , Ops ) ) ; return true ; } std :: pair < StringRef , StringRef > Fields ; Fields = StringRef ( SpecialReg ) . rsplit ( '_' ) ; std :: string Reg = Fields . first . str ( ) ; StringRef Flags = Fields . second ; if ( Subtarget -> isMClass ( ) ) { if ( SpecialReg == <STR_LIT> ) { Reg = SpecialReg ; Flags = <STR_LIT> ; } int SYSmValue = getMClassRegisterMask ( Reg , Flags , false , Subtarget ) ; if ( SYSmValue == - <NUM_LIT> ) return false ; SDValue Ops [ ] = { CurDAG -> getTargetConstant ( SYSmValue , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops ) ) ; return true ; } int Mask = getARClassRegisterMask ( Reg , Flags ) ; if ( Mask != - <NUM_LIT> ) {

Ops = { CurDAG -> getTargetConstant ( Mask , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ;


<s> if ( Subtarget -> hasV6T2Ops ( ) && Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( ~ Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return <NUM_LIT> ; } else { if ( <STR_LIT> ( Val ) != - <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( ~ Val ) != - <NUM_LIT> ) return <NUM_LIT> ; if ( Subtarget -> hasV6T2Ops ( ) && Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return <NUM_LIT> ; }

if ( Subtarget -> useMovt ( * MF ) ) return <NUM_LIT> ;


<s> unsigned <ISA_LIT>DAGToDAGISel :: ConstantMaterializationCost ( unsigned Val ) const { if ( Subtarget -> isThumb ( ) ) { if ( Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( Subtarget -> hasV6T2Ops ( ) && Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( ~ Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return <NUM_LIT> ;


<s> int Mask = getMClassFlagsMask ( Flags , Subtarget -> hasDSP ( ) ) ; if ( ( SYSmvalue < <NUM_LIT> && Mask == - <NUM_LIT> ) || ( SYSmvalue > <NUM_LIT> && ! Flags . empty ( ) ) ) return - <NUM_LIT> ; if ( ! Subtarget -> hasDSP ( ) && ( Mask & <NUM_LIT> ) ) return - <NUM_LIT> ;

if ( SYSmvalue < <NUM_LIT> ) return SYSmvalue | Mask << <NUM_LIT> ;


<s> if ( ! Subtarget -> has8MSecExt ( ) && ( SYSmvalue == <NUM_LIT> || SYSmvalue == <NUM_LIT> || SYSmvalue > <NUM_LIT> ) ) return - <NUM_LIT> ; if ( ! Subtarget -> hasV8MMainlineOps ( ) && ( SYSmvalue == <NUM_LIT> || SYSmvalue == <NUM_LIT> || SYSmvalue == <NUM_LIT> || SYSmvalue == <NUM_LIT> ) ) return - <NUM_LIT> ; if ( IsRead ) { if ( Flags . empty ( ) ) return SYSmvalue ; else return - <NUM_LIT> ; }

int Mask = getMClassFlagsMask ( Flags , Subtarget -> hasDSP ( ) ) ;


<s> } ConstantSDNode * SRLSrc1 = dyn_cast < ConstantSDNode > ( SRL . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * SHLSrc1 = dyn_cast < ConstantSDNode > ( SHL . getOperand ( <NUM_LIT> ) ) ; if ( ! SRLSrc1 || ! SHLSrc1 || SRLSrc1 -> getZExtValue ( ) != <NUM_LIT> || SHLSrc1 -> getZExtValue ( ) != <NUM_LIT> ) return false ; if ( ( SRL . getOperand ( <NUM_LIT> ) . getNode ( ) != SHL . getOperand ( <NUM_LIT> ) . getNode ( ) ) || SRL . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return false ; SDNode * SMULLOHI = SRL . getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( SRL . getOperand ( <NUM_LIT> ) != SDValue ( SMULLOHI , <NUM_LIT> ) || SHL . getOperand ( <NUM_LIT> ) != SDValue ( SMULLOHI , <NUM_LIT> ) ) return false ; if ( SearchSignedMulShort ( SMULLOHI -> getOperand ( <NUM_LIT> ) , Opc , Src1 , Accumulate ) ) { Src0 = SMULLOHI -> getOperand ( <NUM_LIT> ) ;

} else if ( SearchSignedMulShort ( SMULLOHI -> getOperand ( <NUM_LIT> ) , Opc , Src1 , Accumulate ) ) {


<s> SDValue SRL = OR . getOperand ( <NUM_LIT> ) ; SDValue SHL = OR . getOperand ( <NUM_LIT> ) ; if ( SRL . getOpcode ( ) != <STR_LIT> || SHL . getOpcode ( ) != <STR_LIT> ) { SRL = OR . getOperand ( <NUM_LIT> ) ; SHL = OR . getOperand ( <NUM_LIT> ) ; if ( SRL . getOpcode ( ) != <STR_LIT> || SHL . getOpcode ( ) != <STR_LIT> ) return false ; } ConstantSDNode * SRLSrc1 = dyn_cast < ConstantSDNode > ( SRL . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * SHLSrc1 = dyn_cast < ConstantSDNode > ( SHL . getOperand ( <NUM_LIT> ) ) ; if ( ! SRLSrc1 || ! SHLSrc1 || SRLSrc1 -> getZExtValue ( ) != <NUM_LIT> || SHLSrc1 -> getZExtValue ( ) != <NUM_LIT> ) return false ; if ( ( SRL . getOperand ( <NUM_LIT> ) . getNode ( ) != SHL . getOperand ( <NUM_LIT> ) . getNode ( ) ) || SRL . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return false ; SDNode * SMULLOHI = SRL . getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( SRL . getOperand ( <NUM_LIT> ) != SDValue ( SMULLOHI , <NUM_LIT> ) || SHL . getOperand ( <NUM_LIT> ) != SDValue ( SMULLOHI , <NUM_LIT> ) ) return false ; if ( SearchSignedMulShort ( SMULLOHI -> getOperand ( <NUM_LIT> ) , Opc , Src1 , Accumulate ) ) { Src0 = SMULLOHI -> getOperand ( <NUM_LIT> ) ; } else if ( SearchSignedMulShort ( SMULLOHI -> getOperand ( <NUM_LIT> ) , Opc , Src1 , Accumulate ) ) {


<s> if ( ! SRASrc1 || SRASrc1 -> getZExtValue ( ) != <NUM_LIT> ) return false ; SDValue Op0 = SignExt . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { SDValue SHL = Op0 ; ConstantSDNode * SHLSrc1 = dyn_cast < ConstantSDNode > ( SHL . getOperand ( <NUM_LIT> ) ) ; if ( ! SHLSrc1 || SHLSrc1 -> getZExtValue ( ) != <NUM_LIT> ) return false ;

* Opc = Accumulate ? <STR_LIT> : <STR_LIT> ;


<s> if ( ! VT . is128BitVector ( ) || N -> getNumOperands ( ) != <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ;

ReplaceNode ( N , createDRegPairNode ( VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ) ;


<s> } else if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; } else { Base = N ; } OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; }


<s> if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } SDValue SuperReg ; SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) { if ( is64BitVector ) SuperReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; } else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( is64BitVector ) SuperReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQuadQRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } Ops . push_back ( SuperReg ) ; Ops . push_back ( getI32Imm ( Lane , dl ) ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes [ OpcodeIndex ] ) ; SDNode * VLdLn = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; cast < MachineSDNode > ( VLdLn ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; if ( ! IsLoad ) { ReplaceNode ( N , VLdLn ) ; return ; } SuperReg = SDValue ( VLdLn , <NUM_LIT> ) ; static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> && <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ; unsigned Sub0 = is64BitVector ? <STR_LIT> : <STR_LIT> ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) ReplaceUses ( SDValue ( N , Vec ) , CurDAG -> getTargetExtractSubreg ( Sub0 + Vec , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( VLdLn , <NUM_LIT> ) ) ; if ( isUpdating ) ReplaceUses ( SDValue ( N , NumVecs + <NUM_LIT> ) , SDValue ( VLdLn , <NUM_LIT> ) ) ; CurDAG -> RemoveDeadNode ( N ) ;


<s> } else if ( SearchSignedMulLong ( Src1 , & Opc , A , B , true ) ) { Acc = Src0 ; } else { return false ; } if ( Opc == <NUM_LIT> ) return false ; SDValue Ops [ ] = { A , B , Acc , getAL ( CurDAG , dl ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) } ; CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , <STR_LIT> , Ops ) ; return true ; } else if ( N -> getOpcode ( ) == <STR_LIT> && SearchSignedMulLong ( SDValue ( N , <NUM_LIT> ) , & Opc , A , B , false ) ) { if ( Opc == <NUM_LIT> ) return false ; SDValue Ops [ ] = { A , B , getAL ( CurDAG , dl ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) } ;

CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , Ops ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: tryT2IndexedLoad ( SDNode * N ) { LoadSDNode * LD = cast < LoadSDNode > ( N ) ; <STR_LIT> AM = LD -> getAddressingMode ( ) ; if ( AM == <STR_LIT> ) return false ; EVT LoadedVT = LD -> getMemoryVT ( ) ; bool isSExtLd = LD -> getExtensionType ( ) == <STR_LIT> ; SDValue Offset ; bool isPre = ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ; unsigned Opcode = <NUM_LIT> ; bool Match = false ; if ( SelectT2AddrModeImm8Offset ( N , LD -> getOffset ( ) , Offset ) ) { switch ( LoadedVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> :


<s> if ( OptLevel == CodeGenOpt :: None ) return true ; if ( ! CheckVMLxHazard ) return true ; if ( ! Subtarget -> isCortexA7 ( ) && ! Subtarget -> isCortexA8 ( ) && ! Subtarget -> isCortexA9 ( ) && ! Subtarget -> isSwift ( ) ) return true ; if ( ! N -> hasOneUse ( ) ) return false ; SDNode * Use = * N -> use_begin ( ) ; if ( Use -> getOpcode ( ) == <STR_LIT> ) return true ; if ( Use -> isMachineOpcode ( ) ) { const <ISA_LIT>BaseInstrInfo * TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( CurDAG -> getTarget ( ) . getInstrInfo ( ) ) ;

const MCInstrDesc & MCID = TII -> get ( Use -> getMachineOpcode ( ) ) ;


<s> if ( ! N -> hasOneUse ( ) ) return false ; SDNode * Use = * N -> use_begin ( ) ; if ( Use -> getOpcode ( ) == <STR_LIT> ) return true ; if ( Use -> isMachineOpcode ( ) ) { const <ISA_LIT>BaseInstrInfo * TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( CurDAG -> getTarget ( ) . getInstrInfo ( ) ) ; const MCInstrDesc & MCID = TII -> get ( Use -> getMachineOpcode ( ) ) ; if ( MCID . mayStore ( ) ) return true ; unsigned Opcode = MCID . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; return TII -> isFpMLxInstruction ( Opcode ) ; } return false ;


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> bool SelectAddrMode2 ( SDNode * Op , SDValue N , SDValue & Base , SDValue & Offset , SDValue & Opc ) { SelectAddrMode2Worker ( Op , N , Base , Offset , Opc ) ; return true ;


<s> bool SelectAddrMode2Base ( SDNode * Op , SDValue N , SDValue & Base , SDValue & Offset , SDValue & Opc ) {

return SelectAddrMode2Worker ( Op , N , Base , Offset , Opc ) == AM2_BASE ;


<s> return SelectAddrMode2Worker ( Op , N , Base , Offset , Opc ) == AM2_BASE ;


<s> return SelectAddrMode2Worker ( Op , N , Base , Offset , Opc ) == AM2_SHOP ;


<STR_LIT> ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ;


<s> } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { Base = N ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; }

Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC ) , <STR_LIT> ) ;


<s> if ( ! restrict_addressing_modes_for_nacl ) { if ( N . getOpcode ( ) == <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { Base = N ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC ) , <STR_LIT> ) ; return true ; }

if ( restrict_addressing_modes_for_nacl ) {


<s> } else if ( LoadedVT == <STR_LIT> && SelectAddrMode2OffsetReg ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Opcode = isPre ? <STR_LIT> : <STR_LIT> ; Match = true ; } else if ( LoadedVT == <STR_LIT> && SelectAddrMode3Offset ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = ( LD -> getExtensionType ( ) == <STR_LIT> ) ? ( isPre ? <STR_LIT> : <STR_LIT> ) : ( isPre ? <STR_LIT> : <STR_LIT> ) ; } else if ( LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) { if ( LD -> getExtensionType ( ) == <STR_LIT> ) { if ( SelectAddrMode3Offset ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } } else { if ( isPre && SelectAddrMode2OffsetImmPre ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = <STR_LIT> ; } else if ( ! isPre && SelectAddrMode2OffsetImm ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = <STR_LIT> ; } else if ( SelectAddrMode2OffsetReg ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = isPre ? <STR_LIT> : <STR_LIT> ;


<s> Match = true ; } else if ( LoadedVT == <STR_LIT> && ! isPre && SelectAddrMode2OffsetImm ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Opcode = <STR_LIT> ; Match = true ; } else if ( LoadedVT == <STR_LIT> && SelectAddrMode2OffsetReg ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Opcode = isPre ? <STR_LIT> : <STR_LIT> ; Match = true ; } else if ( LoadedVT == <STR_LIT> && SelectAddrMode3Offset ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = ( LD -> getExtensionType ( ) == <STR_LIT> ) ? ( isPre ? <STR_LIT> : <STR_LIT> ) : ( isPre ? <STR_LIT> : <STR_LIT> ) ; } else if ( LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) { if ( LD -> getExtensionType ( ) == <STR_LIT> ) { if ( SelectAddrMode3Offset ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } } else { if ( isPre && SelectAddrMode2OffsetImmPre ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = <STR_LIT> ; } else if ( ! isPre && SelectAddrMode2OffsetImm ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = <STR_LIT> ; } else if ( SelectAddrMode2OffsetReg ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } } } if ( Match ) { if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ; SDValue Ops [ ] = { Base , AMOpc , getAL ( CurDAG ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , Chain } ; return CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , <STR_LIT> , <STR_LIT> , <STR_LIT> , Ops ) ; } else { SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ;

SDValue Ops [ ] = { Base , Offset , AMOpc , getAL ( CurDAG ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , Chain } ;


<s> bool Changed = false ; unsigned NumOps = N -> getNumOperands ( ) ; SDLoc dl ( N ) ; SDValue Glue = N -> getGluedNode ( ) ? N -> getOperand ( NumOps - <NUM_LIT> ) : SDValue ( nullptr , <NUM_LIT> ) ; SmallVector < bool , <NUM_LIT> > OpChanged ; for ( unsigned i = <NUM_LIT> , e = N -> getGluedNode ( ) ? NumOps - <NUM_LIT> : NumOps ; i < e ; ++ i ) { SDValue op = N -> getOperand ( i ) ; AsmNodeOperands . push_back ( op ) ; if ( i < InlineAsm :: Op_FirstOperand ) continue ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( i ) ) ) { Flag = C -> getZExtValue ( ) ; Kind = InlineAsm :: getKind ( Flag ) ; } else continue ; if ( Kind == InlineAsm :: Kind_Imm ) { SDValue op = N -> getOperand ( ++ i ) ; AsmNodeOperands . push_back ( op ) ; continue ; } unsigned NumRegs = InlineAsm :: getNumOperandRegisters ( Flag ) ; if ( NumRegs ) OpChanged . push_back ( false ) ; unsigned DefIdx = <NUM_LIT> ; bool IsTiedToChangedOp = false ; if ( Changed && InlineAsm :: isUseOperandTiedToDef ( Flag , DefIdx ) ) IsTiedToChangedOp = OpChanged [ DefIdx ] ; if ( Kind != InlineAsm :: Kind_RegUse && Kind != InlineAsm :: Kind_RegDef && Kind != InlineAsm :: Kind_RegDefEarlyClobber ) continue ; unsigned RC ; bool HasRC = InlineAsm :: hasRegClassConstraint ( Flag , RC ) ; if ( ( ! IsTiedToChangedOp && ( ! HasRC || RC != <STR_LIT> ) ) || NumRegs != <NUM_LIT> ) continue ; assert ( ( i + <NUM_LIT> < NumOps ) && <STR_LIT> ) ;

SDValue V0 = N -> getOperand ( i + <NUM_LIT> ) ;


<s> return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { if ( SelectT2AddrModeImm8 ( N , Base , OffImm ) ) return false ; int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ;

Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeImm5S ( SDValue N , unsigned Scale , SDValue & Base , SDValue & OffImm ) { if ( Scale == <NUM_LIT> ) { SDValue TmpBase , TmpOffImm ; if ( SelectThumbAddrModeSP ( N , TmpBase , TmpOffImm ) ) return false ; if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) {


<s> case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDValue SuperReg ; unsigned Opc = Opcodes [ OpcodeIndex ] ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( Inc ) ; else if ( NumVecs > <NUM_LIT> ) Ops . push_back ( Reg0 ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; std :: vector < EVT > ResTys ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ;

if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ;


<s> EVT VT = N -> getOperand ( Vec0Idx ) . getValueType ( ) ; bool is64BitVector = VT . is64BitVector ( ) ; unsigned Alignment = <NUM_LIT> ; if ( NumVecs != <NUM_LIT> ) { Alignment = cast < ConstantSDNode > ( Align ) -> getZExtValue ( ) ; unsigned NumBytes = NumVecs * VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( Alignment > NumBytes ) Alignment = NumBytes ; if ( Alignment < <NUM_LIT> && Alignment < NumBytes ) Alignment = <NUM_LIT> ; Alignment = ( Alignment & - Alignment ) ; if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; } Align = CurDAG -> getTargetConstant ( Alignment , <STR_LIT> ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } std :: vector < EVT > ResTys ; if ( IsLoad ) { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ;

SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ;


<s> if ( IsLoad ) { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } SDValue SuperReg ; SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) { if ( is64BitVector ) SuperReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; } else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( is64BitVector ) SuperReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQuadQRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } Ops . push_back ( SuperReg ) ; Ops . push_back ( getI32Imm ( Lane ) ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes [ OpcodeIndex ] ) ; SDNode * VLdLn = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; cast < MachineSDNode > ( VLdLn ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; if ( ! IsLoad ) return VLdLn ;

SuperReg = SDValue ( VLdLn , <NUM_LIT> ) ;


<s> SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { SDValue SrcReg ; if ( NumVecs == <NUM_LIT> ) { SrcReg = N -> getOperand ( Vec0Idx ) ; } else if ( is64BitVector ) { SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) SrcReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } } else { SDValue Q0 = N -> getOperand ( Vec0Idx ) ; SDValue Q1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQRegPairNode ( <STR_LIT> , Q0 , Q1 ) , <NUM_LIT> ) ; } unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( NumVecs <= <NUM_LIT> && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( Inc ) ;

else if ( NumVecs > <NUM_LIT> && ! isVSTfixed ( Opc ) ) Ops . push_back ( Reg0 ) ;


if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return true ;


<s> unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT , NumVecs ) ; if ( ! IsImmUpdate ) { if ( isVLDfixed ( Opc ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; Ops . push_back ( Inc ) ; } else if ( ! isVLDfixed ( Opc ) ) Ops . push_back ( Reg0 ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLd = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; } else { EVT AddrTy = MemAddr . getValueType ( ) ; SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , ResTy ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , Reg0 , ImplDef , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTy , AddrTy , <STR_LIT> , OpsA ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; Ops . push_back ( SDValue ( VLdA , <NUM_LIT> ) ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; assert ( isa < ConstantSDNode > ( Inc . getNode ( ) ) && <STR_LIT> ) ; ( void ) Inc ; Ops . push_back ( Reg0 ) ;


<s> switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; EVT ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ; std :: vector < EVT > ResTys ; ResTys . push_back ( ResTy ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDNode * VLdDup ; if ( is64BitVector || NumVecs == <NUM_LIT> ) { SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; unsigned Opc = is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT . getVectorElementType ( ) , NumVecs ) ; if ( NumVecs <= <NUM_LIT> && ! IsImmUpdate ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ! IsImmUpdate ) Ops . push_back ( Inc ) ; else if ( NumVecs > <NUM_LIT> ) Ops . push_back ( Reg0 ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLdDup = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; } else if ( NumVecs == <NUM_LIT> ) { const SDValue OpsA [ ] = { MemAddr , Align , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTys , OpsA ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ;

const SDValue OpsB [ ] = { MemAddr , Align , Pred , Reg0 , Chain } ;


<s> unsigned Opc = is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT . getVectorElementType ( ) , NumVecs ) ; if ( NumVecs <= <NUM_LIT> && ! IsImmUpdate ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ! IsImmUpdate ) Ops . push_back ( Inc ) ; else if ( NumVecs > <NUM_LIT> ) Ops . push_back ( Reg0 ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLdDup = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; } else if ( NumVecs == <NUM_LIT> ) { const SDValue OpsA [ ] = { MemAddr , Align , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTys , OpsA ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; const SDValue OpsB [ ] = { MemAddr , Align , Pred , Reg0 , Chain } ; VLdDup = CurDAG -> getMachineNode ( QOpcodes1 [ OpcodeIndex ] , dl , ResTys , OpsB ) ; } else { SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , ResTy ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , ImplDef , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTys , OpsA ) ; SDValue SuperReg = SDValue ( VLdA , <NUM_LIT> ) ;


<s> SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT . getVectorElementType ( ) , NumVecs ) ; Ops . push_back ( IsImmUpdate ? Reg0 : Inc ) ; } SDValue SuperReg ; SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) { if ( is64BitVector ) SuperReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; } else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( is64BitVector ) SuperReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQuadQRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } Ops . push_back ( SuperReg ) ; Ops . push_back ( getI32Imm ( Lane , dl ) ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes [ OpcodeIndex ] ) ; SDNode * VLdLn = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( VLdLn ) , { MemOp } ) ; if ( ! IsLoad ) { ReplaceNode ( N , VLdLn ) ; return ; } SuperReg = SDValue ( VLdLn , <NUM_LIT> ) ; static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> && <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ; unsigned Sub0 = is64BitVector ? <STR_LIT> : <STR_LIT> ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) ReplaceUses ( SDValue ( N , Vec ) , CurDAG -> getTargetExtractSubreg ( Sub0 + Vec , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( VLdLn , <NUM_LIT> ) ) ; if ( isUpdating ) ReplaceUses ( SDValue ( N , NumVecs + <NUM_LIT> ) , SDValue ( VLdLn , <NUM_LIT> ) ) ;


<s> <STR_LIT> Pred ; SDValue PredReg ; SDValue Chain , Base , Offset ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { <STR_LIT> AM = LD -> getAddressingMode ( ) ; if ( AM == <STR_LIT> ) return false ; LoadedVT = LD -> getMemoryVT ( ) ; if ( ! LoadedVT . isVector ( ) ) return false ; Chain = LD -> getChain ( ) ; Base = LD -> getBasePtr ( ) ; Offset = LD -> getOffset ( ) ; Align = LD -> getAlignment ( ) ; isSExtLd = LD -> getExtensionType ( ) == <STR_LIT> ; isPre = ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ; Pred = <STR_LIT> ; PredReg = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; } else if ( MaskedLoadSDNode * LD = dyn_cast < MaskedLoadSDNode > ( N ) ) { <STR_LIT> AM = LD -> getAddressingMode ( ) ; if ( AM == <STR_LIT> ) return false ; LoadedVT = LD -> getMemoryVT ( ) ; if ( ! LoadedVT . isVector ( ) ) return false ; Chain = LD -> getChain ( ) ; Base = LD -> getBasePtr ( ) ; Offset = LD -> getOffset ( ) ; Align = LD -> getAlignment ( ) ; isSExtLd = LD -> getExtensionType ( ) == <STR_LIT> ; isPre = ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ; Pred = <STR_LIT> ; PredReg = LD -> getMask ( ) ; } else llvm_unreachable ( <STR_LIT> ) ; bool CanChangeType = Subtarget -> isLittle ( ) && ! isa < MaskedLoadSDNode > ( N ) ; SDValue NewOffset ; if ( Align >= <NUM_LIT> && LoadedVT == <STR_LIT> && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) { if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } else if ( LoadedVT == <STR_LIT> && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) { if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } else if ( LoadedVT == <STR_LIT> && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) {


<s> if ( AM == <STR_LIT> ) return false ; LoadedVT = LD -> getMemoryVT ( ) ; if ( ! LoadedVT . isVector ( ) ) return false ; Chain = LD -> getChain ( ) ; Base = LD -> getBasePtr ( ) ; Offset = LD -> getOffset ( ) ; Align = LD -> getAlignment ( ) ; isSExtLd = LD -> getExtensionType ( ) == <STR_LIT> ; isPre = ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ; Pred = <STR_LIT> ; PredReg = LD -> getMask ( ) ; } else llvm_unreachable ( <STR_LIT> ) ; bool CanChangeType = Subtarget -> isLittle ( ) && ! isa < MaskedLoadSDNode > ( N ) ; SDValue NewOffset ; if ( Align >= <NUM_LIT> && LoadedVT == <STR_LIT> && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) { if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } else if ( LoadedVT == <STR_LIT> && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) { if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } else if ( LoadedVT == <STR_LIT> && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) { if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } else if ( Align >= <NUM_LIT> && ( CanChangeType || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else if ( Align >= <NUM_LIT> && ( CanChangeType || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else if ( ( CanChangeType || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else return false ; SDValue Ops [ ] = { Base , NewOffset , CurDAG -> getTargetConstant ( Pred , SDLoc ( N ) , <STR_LIT> ) , PredReg , Chain } ; SDNode * New = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , <STR_LIT> , N -> getValueType ( <NUM_LIT> ) , <STR_LIT> , Ops ) ;


<s> Ops . push_back ( CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ) ;

Ops . push_back ( SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , Loc , InactiveTy ) , <NUM_LIT> ) ) ;


<s> Ops . push_back ( SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , Loc , InactiveTy ) , <NUM_LIT> ) ) ;


<s> void <ISA_LIT>DAGToDAGISel :: AddMVEPredicateToOps ( SDValueVector & Ops , SDLoc Loc , SDValue PredicateMask , SDValue Inactive ) { Ops . push_back ( CurDAG -> getTargetConstant ( <STR_LIT> , Loc , <STR_LIT> ) ) ; Ops . push_back ( PredicateMask ) ; Ops . push_back ( Inactive ) ;


<s> void <ISA_LIT>DAGToDAGISel :: AddMVEPredicateToOps ( SDValueVector & Ops , SDLoc Loc , SDValue PredicateMask , SDValue Inactive ) {

Ops . push_back ( CurDAG -> getTargetConstant ( <STR_LIT> , Loc , <STR_LIT> ) ) ;


<s> if ( ! N . hasOneUse ( ) ) return false ; ConstantSDNode * MulConst = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! MulConst ) return false ; if ( ! MulConst -> hasOneUse ( ) ) return false ; unsigned MulConstVal = MulConst -> getZExtValue ( ) ; if ( MulConstVal == <NUM_LIT> ) return false ; PowerOfTwo = MaxShift ; while ( ( MulConstVal % ( <NUM_LIT> << PowerOfTwo ) ) != <NUM_LIT> ) { -- PowerOfTwo ; if ( PowerOfTwo == <NUM_LIT> ) return false ; } unsigned NewMulConstVal = MulConstVal / ( <NUM_LIT> << PowerOfTwo ) ; NewMulConst = CurDAG -> getConstant ( NewMulConstVal , SDLoc ( N ) , <STR_LIT> ) ; unsigned OldCost = ConstantMaterializationCost ( MulConstVal , Subtarget ) ; unsigned NewCost = ConstantMaterializationCost ( NewMulConstVal , Subtarget ) ;


<s> bool ComplexPatternFuncMutatesDAG ( ) const override {


<s> static void getIntOperandsFromRegisterString ( StringRef RegString , SelectionDAG * CurDAG , const SDLoc & DL , std :: vector < SDValue > & Ops ) { SmallVector < StringRef , <NUM_LIT> > Fields ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; } <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } if ( FP16 ) Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC ) , SDLoc ( N ) , <STR_LIT> ) ; else Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC ) , SDLoc ( N ) , <STR_LIT> ) ; return true ; } Base = N ; if ( FP16 ) Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ; else Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ;


<s> case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ;


<s> static bool isVSTfixed ( unsigned Opc ) { switch ( Opc ) { default : return false ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ;


<s> assert ( isa < ConstantSDNode > ( SDVal ) && <STR_LIT> ) ; ConstantSDNode * SDValConstant = dyn_cast < ConstantSDNode > ( SDVal ) ;

uint64_t Value = SDValConstant -> getZExtValue ( ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrMode5 ( SDValue N , SDValue & Base , SDValue & Offset ) {

return IsAddressingMode5 ( N , Base , Offset , false ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrMode5 ( SDValue N , SDValue & Base , SDValue & Offset ) { return IsAddressingMode5 ( N , Base , Offset , false ) ;


<s> return IsAddressingMode5 ( N , Base , Offset , true ) ;


<s> } auto OpIsZero = [ N ] ( size_t OpNo ) { if ( ConstantSDNode * OpConst = dyn_cast < ConstantSDNode > ( N -> getOperand ( OpNo ) ) ) if ( OpConst -> getZExtValue ( ) == <NUM_LIT> ) return true ; return false ; } ; bool IsAccum = ! ( OpIsZero ( <NUM_LIT> ) && OpIsZero ( <NUM_LIT> ) ) ; const uint16_t * Opcodes = IsUnsigned ? OpcodesU : OpcodesS ; if ( IsSub ) Opcodes += <NUM_LIT> * Stride ; if ( IsExchange ) Opcodes += <NUM_LIT> * Stride ; if ( IsAccum ) Opcodes += Stride ; uint16_t Opcode = Opcodes [ TySize ] ; SDLoc Loc ( N ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( IsAccum ) { Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; } Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ;


<s> if ( HasAccum ) { SDValue AccLo = N -> getOperand ( OpIdx ++ ) ; SDValue AccHi = N -> getOperand ( OpIdx ++ ) ; if ( IsBigEndian ) std :: swap ( AccLo , AccHi ) ; Ops . push_back ( SDValue ( createGPRPairNode ( <STR_LIT> , AccLo , AccHi ) , <NUM_LIT> ) ) ; } for ( size_t I = <NUM_LIT> ; I < NumExtraOps ; I ++ ) Ops . push_back ( N -> getOperand ( OpIdx ++ ) ) ; SDValue Imm = N -> getOperand ( OpIdx ) ; uint32_t ImmVal = cast < ConstantSDNode > ( Imm ) -> getZExtValue ( ) ; Ops . push_back ( getI32Imm ( ImmVal , Loc ) ) ; if ( HasAccum ) { SDValue Pred = getAL ( CurDAG , Loc ) ; SDValue PredReg = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Ops . push_back ( Pred ) ; Ops . push_back ( PredReg ) ; } SDNode * InstrNode = CurDAG -> getMachineNode ( Opcode , Loc , <STR_LIT> , Ops ) ; SDValue ResultPair = SDValue ( InstrNode , <NUM_LIT> ) ; uint16_t SubRegs [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> } ; if ( IsBigEndian ) std :: swap ( SubRegs [ <NUM_LIT> ] , SubRegs [ <NUM_LIT> ] ) ; for ( size_t ResIdx = <NUM_LIT> ; ResIdx < <NUM_LIT> ; ResIdx ++ ) { if ( SDValue ( N , ResIdx ) . use_empty ( ) ) continue ; SDValue SubReg = CurDAG -> getTargetExtractSubreg ( SubRegs [ ResIdx ] , Loc , <STR_LIT> , ResultPair ) ;

ReplaceUses ( SDValue ( N , ResIdx ) , SubReg ) ;


<s> SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * CmpSwap = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) , Ops ) ; MachineMemOperand * MemOp = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( CmpSwap ) , { MemOp } ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( CmpSwap , <NUM_LIT> ) ) ;


<s> if ( isScaledConstantInRange ( N , <NUM_LIT> , Min , Max , Val ) ) {

OffImm = CurDAG -> getTargetConstant ( Val , SDLoc ( N ) , <STR_LIT> ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Constraint_m : case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_Q : case InlineAsm :: Constraint_Um : case InlineAsm :: Constraint_Un : case InlineAsm :: Constraint_Uq : case InlineAsm :: Constraint_Us : case InlineAsm :: Constraint_Ut :


<s> case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_Q : case InlineAsm :: Constraint_Um : case InlineAsm :: Constraint_Un : case InlineAsm :: Constraint_Uq : case InlineAsm :: Constraint_Us : case InlineAsm :: Constraint_Ut : case InlineAsm :: Constraint_Uv : case InlineAsm :: Constraint_Uy : OutOps . push_back ( Op ) ;


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; if ( Immediate ) { int32_t ImmValue = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Ops . push_back ( getI32Imm ( ImmValue , Loc ) ) ; } else { Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; } if ( HasSaturationOperand ) { int32_t SatOp = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; int SatBit = ( SatOp == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; Ops . push_back ( getI32Imm ( SatBit , Loc ) ) ;


<s> uint16_t Opcode ; unsigned FirstInputOp = Predicated ? <NUM_LIT> : <NUM_LIT> ; Ops . push_back ( N -> getOperand ( FirstInputOp ) ) ; Ops . push_back ( N -> getOperand ( FirstInputOp + <NUM_LIT> ) ) ; SDValue CarryIn = N -> getOperand ( FirstInputOp + <NUM_LIT> ) ; ConstantSDNode * CarryInConstant = dyn_cast < ConstantSDNode > ( CarryIn ) ; uint32_t CarryMask = <NUM_LIT> << <NUM_LIT> ; uint32_t CarryExpected = Add ? <NUM_LIT> : CarryMask ; if ( CarryInConstant && ( CarryInConstant -> getZExtValue ( ) & CarryMask ) == CarryExpected ) { Opcode = OpcodeWithNoCarry ; } else { Ops . push_back ( CarryIn ) ;


<s> transferMemOperands ( N , LoadInst ) ; } if ( HasWriteback ) ResultTys = { DataTy , <STR_LIT> , <STR_LIT> } ; SDValue Ops [ ] = { Data , N -> getOperand ( PtrOperand ) , Chain } ; auto LoadInst = CurDAG -> getMachineNode ( OurOpcodes [ NumVecs - <NUM_LIT> ] , Loc , ResultTys , Ops ) ; transferMemOperands ( N , LoadInst ) ; unsigned i ; for ( i = <NUM_LIT> ; i < NumVecs ; i ++ ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( <STR_LIT> + i , Loc , VT , SDValue ( LoadInst , <NUM_LIT> ) ) ) ; if ( HasWriteback ) ReplaceUses ( SDValue ( N , i ++ ) , SDValue ( LoadInst , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N , i ) , SDValue ( LoadInst , HasWriteback ? <NUM_LIT> : <NUM_LIT> ) ) ;


<s> EVT VecTy = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; size_t SizeIndex ;

switch ( VecTy . getVectorElementType ( ) . getSizeInBits ( ) ) {


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; int32_t ImmValue = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Ops . push_back ( getI32Imm ( ImmValue , Loc ) ) ;

if ( Predicated ) AddMVEPredicateToOps ( Ops , Loc , N -> getOperand ( <NUM_LIT> ) ) ;


<s> SDLoc Loc ( N ) ; uint16_t Opcode ; switch ( VT . getScalarSizeInBits ( ) ) { case <NUM_LIT> : Opcode = Opcodes [ <NUM_LIT> ] ; break ; case <NUM_LIT> : Opcode = Opcodes [ <NUM_LIT> ] ; break ; case <NUM_LIT> : Opcode = Opcodes [ <NUM_LIT> ] ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned OpIdx = <NUM_LIT> ; SDValue Inactive ; if ( Predicated ) Inactive = N -> getOperand ( OpIdx ++ ) ; Ops . push_back ( N -> getOperand ( OpIdx ++ ) ) ; if ( Wrapping ) Ops . push_back ( N -> getOperand ( OpIdx ++ ) ) ; SDValue ImmOp = N -> getOperand ( OpIdx ++ ) ; int ImmValue = cast < ConstantSDNode > ( ImmOp ) -> getZExtValue ( ) ; Ops . push_back ( getI32Imm ( ImmValue , Loc ) ) ; if ( Predicated ) AddMVEPredicateToOps ( Ops , Loc , N -> getOperand ( OpIdx ) , Inactive ) ; else AddEmptyMVEPredicateToOps ( Ops , Loc , N -> getValueType ( <NUM_LIT> ) ) ;

CurDAG -> SelectNodeTo ( N , Opcode , N -> getVTList ( ) , makeArrayRef ( Ops ) ) ;


<s> int32_t ImmValue = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Ops . push_back ( getI32Imm ( ImmValue , Loc ) ) ; if ( Predicated ) AddMVEPredicateToOps ( Ops , Loc , N -> getOperand ( <NUM_LIT> ) ) ; else AddEmptyMVEPredicateToOps ( Ops , Loc ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; SmallVector < EVT , <NUM_LIT> > VTs ; VTs . push_back ( N -> getValueType ( <NUM_LIT> ) ) ; VTs . push_back ( N -> getValueType ( <NUM_LIT> ) ) ; VTs . push_back ( N -> getValueType ( <NUM_LIT> ) ) ; SDNode * New = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , VTs , Ops ) ;

ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( New , <NUM_LIT> ) ) ;


<s> if ( ! N . hasOneUse ( ) ) return false ;

return SelectImmShifterOperand ( N , A , B , false ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectT2AddrModeImm7 ( SDValue N , SDValue & Base , SDValue & OffImm ) { if ( N . getOpcode ( ) == <STR_LIT> || CurDAG -> isBaseWithConstantOffset ( N ) ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> << Shift , - <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; } if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ;

OffImm = CurDAG -> getTargetConstant ( RHSC * ( <NUM_LIT> << Shift ) , SDLoc ( N ) , <STR_LIT> ) ;


<s> } int RHSC ; if ( isScaledConstantInRange ( N , <NUM_LIT> << Shift , <NUM_LIT> , <NUM_LIT> , RHSC ) ) {

OffImm = ( ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ) ? CurDAG -> getTargetConstant ( RHSC * ( <NUM_LIT> << Shift ) , SDLoc ( N ) , <STR_LIT> ) : CurDAG -> getTargetConstant ( - RHSC * ( <NUM_LIT> << Shift ) , SDLoc ( N ) , <STR_LIT> ) ;


<s> if ( N . getOpcode ( ) == <STR_LIT> || CurDAG -> isBaseWithConstantOffset ( N ) ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> << Shift , - <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; } if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; OffImm = CurDAG -> getTargetConstant ( RHSC * ( <NUM_LIT> << Shift ) , SDLoc ( N ) , <STR_LIT> ) ; return true ;


<s> Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; } if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; OffImm = CurDAG -> getTargetConstant ( RHSC * ( <NUM_LIT> << Shift ) , SDLoc ( N ) , <STR_LIT> ) ;


<s> if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; OffImm = CurDAG -> getTargetConstant ( RHSC * ( <NUM_LIT> << Shift ) , SDLoc ( N ) , <STR_LIT> ) ; return true ; } }


<s> if ( N . getOpcode ( ) == <STR_LIT> || CurDAG -> isBaseWithConstantOffset ( N ) ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> << Shift , - <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; OffImm = CurDAG -> getTargetConstant ( RHSC * ( <NUM_LIT> << Shift ) , SDLoc ( N ) , <STR_LIT> ) ; return true ; }


<s> return true ; } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { if ( N . getOpcode ( ) == <STR_LIT> ) { return false ; } else if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; } else { Base = N ; } OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeRR ( SDValue N , SDValue & Base , SDValue & Offset ) {

if ( shouldUseZeroOffsetLdSt ( N ) ) return false ;


<s> if ( ! NC || ! NC -> isNullValue ( ) ) return false ; Base = Offset = N ; return true ; } Base = N . getOperand ( <NUM_LIT> ) ;


<s> if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; if ( RHSC * <NUM_LIT> < MFI . getObjectSize ( FI ) ) {

if ( ! MFI . isFixedObjectIndex ( FI ) && MFI . getObjectAlign ( FI ) < Align ( <NUM_LIT> ) ) MFI . setObjectAlignment ( FI , Align ( <NUM_LIT> ) ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; EVT ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ; std :: vector < EVT > ResTys ; ResTys . push_back ( ResTy ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; unsigned Opc = is64BitVector ? DOpcodes [ OpcodeIndex ] : ( NumVecs == <NUM_LIT> ) ? QOpcodes0 [ OpcodeIndex ] : QOpcodes1 [ OpcodeIndex ] ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT . getVectorElementType ( ) , NumVecs ) ; if ( IsImmUpdate ) { if ( ! isVLDfixed ( Opc ) ) Ops . push_back ( Reg0 ) ; } else { if ( isVLDfixed ( Opc ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; Ops . push_back ( Inc ) ; } } if ( is64BitVector || NumVecs == <NUM_LIT> ) { } else if ( NumVecs == <NUM_LIT> ) { const SDValue OpsA [ ] = { MemAddr , Align , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTy , <STR_LIT> , OpsA ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; } else { SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , ResTy ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , ImplDef , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTy , <STR_LIT> , OpsA ) ; Ops . push_back ( SDValue ( VLdA , <NUM_LIT> ) ) ;


<s> if ( IsLoad ) { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT . getVectorElementType ( ) , NumVecs ) ; Ops . push_back ( IsImmUpdate ? Reg0 : Inc ) ; } SDValue SuperReg ; SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) { if ( is64BitVector ) SuperReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; } else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( is64BitVector ) SuperReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ;

else SuperReg = SDValue ( createQuadQRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ;


<s> void <ISA_LIT>DAGToDAGISel :: transferMemOperands ( SDNode * N , SDNode * Result ) { MachineMemOperand * MemOp = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( Result ) , { MemOp } ) ;


<s> CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( Result ) , { MemOp } ) ;


<s> if ( ! Subtarget -> hasMVEFloatOps ( ) ) return false ; auto Type = N -> getValueType ( <NUM_LIT> ) ;

if ( ! Type . isVector ( ) ) return false ;


<s> if ( Node -> getOpcode ( ) == <STR_LIT> ) { if ( Node -> getOperand ( <NUM_LIT> ) != Node -> getOperand ( <NUM_LIT> ) ) return false ; SDNodeFlags Flags = Node -> getFlags ( ) ; if ( ScalarBits == <NUM_LIT> && ! Flags . hasNoInfs ( ) && IsUnsigned ) return false ; unsigned Opcode ; switch ( ScalarBits ) { case <NUM_LIT> : Opcode = IsUnsigned ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : Opcode = IsUnsigned ? <STR_LIT> : <STR_LIT> ; break ; }

SmallVector < SDValue , <NUM_LIT> > Ops { Node -> getOperand ( <NUM_LIT> ) , CurDAG -> getConstant ( <NUM_LIT> , dl , <STR_LIT> ) } ;


<s> bool <ISA_LIT>DAGToDAGISel :: tryFP_TO_INT ( SDNode * N , SDLoc dl ) { if ( ! Subtarget -> hasMVEFloatOps ( ) ) return false ; EVT Type = N -> getValueType ( <NUM_LIT> ) ; if ( ! Type . isVector ( ) ) return false ; unsigned int ScalarBits = Type . getScalarSizeInBits ( ) ; bool IsUnsigned = N -> getOpcode ( ) == <STR_LIT> ; SDNode * Node = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( Node -> getOpcode ( ) == <STR_LIT> ) { if ( Node -> getOperand ( <NUM_LIT> ) != Node -> getOperand ( <NUM_LIT> ) ) return false ; SDNodeFlags Flags = Node -> getFlags ( ) ; if ( ScalarBits == <NUM_LIT> && ! Flags . hasNoInfs ( ) && IsUnsigned ) return false ; unsigned Opcode ; switch ( ScalarBits ) { case <NUM_LIT> :

Opcode = IsUnsigned ? <STR_LIT> : <STR_LIT> ;


<s> unsigned Lane1 = Ins1 . getConstantOperandVal ( <NUM_LIT> ) ; unsigned Lane2 = Ins2 . getConstantOperandVal ( <NUM_LIT> ) ; if ( Lane2 % <NUM_LIT> != <NUM_LIT> || Lane1 != Lane2 + <NUM_LIT> ) return false ; SDValue Val1 = Ins1 . getOperand ( <NUM_LIT> ) ; SDValue Val2 = Ins2 . getOperand ( <NUM_LIT> ) ; if ( Val1 . getOpcode ( ) == <STR_LIT> || Val2 . getOpcode ( ) == <STR_LIT> ) return false ; if ( ( Val1 . getOpcode ( ) == <STR_LIT> || Val1 . getOpcode ( ) == <STR_LIT> ) && ( Val2 . getOpcode ( ) == <STR_LIT> || Val2 . getOpcode ( ) == <STR_LIT> ) && isa < ConstantSDNode > ( Val1 . getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( Val2 . getOperand ( <NUM_LIT> ) ) && ( Val1 . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> || Val1 . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) && ( Val2 . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> || Val2 . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ) { unsigned ExtractLane1 = Val1 . getConstantOperandVal ( <NUM_LIT> ) ; unsigned ExtractLane2 = Val2 . getConstantOperandVal ( <NUM_LIT> ) ; if ( Val1 . getOperand ( <NUM_LIT> ) == Val2 . getOperand ( <NUM_LIT> ) && ExtractLane2 % <NUM_LIT> == <NUM_LIT> && ExtractLane1 == ExtractLane2 + <NUM_LIT> ) { SDValue NewExt = CurDAG -> getTargetExtractSubreg ( <STR_LIT> + ExtractLane2 / <NUM_LIT> , dl , <STR_LIT> , Val1 . getOperand ( <NUM_LIT> ) ) ; SDValue NewIns = CurDAG -> getTargetInsertSubreg ( <STR_LIT> + Lane2 / <NUM_LIT> , dl , VT , Ins2 . getOperand ( <NUM_LIT> ) , NewExt ) ; ReplaceUses ( Ins1 , NewIns ) ; return true ; } if ( VT == <STR_LIT> ) { SDValue Inp1 = CurDAG -> getTargetExtractSubreg ( <STR_LIT> + ExtractLane1 / <NUM_LIT> , dl , <STR_LIT> , Val1 . getOperand ( <NUM_LIT> ) ) ; SDValue Inp2 = CurDAG -> getTargetExtractSubreg ( <STR_LIT> + ExtractLane2 / <NUM_LIT> , dl , <STR_LIT> , Val2 . getOperand ( <NUM_LIT> ) ) ; if ( ExtractLane1 % <NUM_LIT> != <NUM_LIT> ) Inp1 = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Inp1 ) , <NUM_LIT> ) ; if ( ExtractLane2 % <NUM_LIT> != <NUM_LIT> ) Inp2 = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Inp2 ) , <NUM_LIT> ) ; SDNode * VINS = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Inp2 , Inp1 ) ; SDValue NewIns = CurDAG -> getTargetInsertSubreg ( <STR_LIT> + Lane2 / <NUM_LIT> , dl , <STR_LIT> , Ins2 . getOperand ( <NUM_LIT> ) , SDValue ( VINS , <NUM_LIT> ) ) ;


<s> Chain = LD -> getChain ( ) ; Base = LD -> getBasePtr ( ) ; Offset = LD -> getOffset ( ) ; Alignment = LD -> getAlign ( ) ; isSExtLd = LD -> getExtensionType ( ) == <STR_LIT> ; isPre = ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ; Pred = <STR_LIT> ; PredReg = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; } else if ( MaskedLoadSDNode * LD = dyn_cast < MaskedLoadSDNode > ( N ) ) { <STR_LIT> AM = LD -> getAddressingMode ( ) ; if ( AM == <STR_LIT> ) return false ; LoadedVT = LD -> getMemoryVT ( ) ; if ( ! LoadedVT . isVector ( ) ) return false ; Chain = LD -> getChain ( ) ; Base = LD -> getBasePtr ( ) ; Offset = LD -> getOffset ( ) ; Alignment = LD -> getAlign ( ) ; isSExtLd = LD -> getExtensionType ( ) == <STR_LIT> ; isPre = ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ; Pred = <STR_LIT> ; PredReg = LD -> getMask ( ) ; } else llvm_unreachable ( <STR_LIT> ) ; bool CanChangeType = Subtarget -> isLittle ( ) && ! isa < MaskedLoadSDNode > ( N ) ; SDValue NewOffset ; if ( Alignment >= Align ( <NUM_LIT> ) && LoadedVT == <STR_LIT> && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) { if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } else if ( LoadedVT == <STR_LIT> && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) { if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } else if ( LoadedVT == <STR_LIT> && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) { if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } else if ( Alignment >= Align ( <NUM_LIT> ) && ( CanChangeType || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else if ( Alignment >= Align ( <NUM_LIT> ) && ( CanChangeType || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ;

else if ( ( CanChangeType || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ;


<s> unsigned Opcode = StringSwitch < unsigned > ( SpecialReg ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Opcode ) { if ( ! Subtarget -> hasVFP2Base ( ) ) return false ; if ( Opcode == <STR_LIT> && ! Subtarget -> hasFP<ISA_LIT>v8Base ( ) ) return false ; Ops = { getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , <STR_LIT> , Ops ) ) ; return true ; } if ( Subtarget -> isMClass ( ) ) { int SYSmValue = getMClassRegisterMask ( SpecialReg , Subtarget ) ; if ( SYSmValue == - <NUM_LIT> ) return false ; SDValue Ops [ ] = { CurDAG -> getTargetConstant ( SYSmValue , DL , <STR_LIT> ) , getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , Ops ) ) ; return true ; } if ( SpecialReg == <STR_LIT> || SpecialReg == <STR_LIT> ) { Ops = { getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( IsThumb2 ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , Ops ) ) ; return true ; } if ( SpecialReg == <STR_LIT> ) { Ops = { getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( IsThumb2 ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , Ops ) ) ; return true ;


<s> if ( isInt32Immediate ( N -> getOperand ( <NUM_LIT> ) , Srl_imm ) ) { assert ( Srl_imm > <NUM_LIT> && Srl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Width = <NUM_LIT> - Srl_imm - <NUM_LIT> ; int LSB = Srl_imm - Shl_imm ; if ( LSB < <NUM_LIT> ) return false ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; assert ( LSB + Width + <NUM_LIT> <= <NUM_LIT> && <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( LSB , dl , <STR_LIT> ) , CurDAG -> getTargetConstant ( Width , dl , <STR_LIT> ) , getAL ( CurDAG , dl ) , Reg0 } ; CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , Ops ) ; return true ; } } if ( isOpcWithIntImmediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , And_imm ) && isShiftedMask_32 ( And_imm ) ) { unsigned Srl_imm = <NUM_LIT> ; unsigned LSB = countTrailingZeros ( And_imm ) ; if ( isInt32Immediate ( N -> getOperand ( <NUM_LIT> ) , Srl_imm ) && Srl_imm == LSB ) { assert ( Srl_imm > <NUM_LIT> && Srl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned MSB = <NUM_LIT> - countLeadingZeros ( And_imm ) ; unsigned Width = MSB - LSB ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; assert ( Srl_imm + Width + <NUM_LIT> <= <NUM_LIT> && <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( Srl_imm , dl , <STR_LIT> ) , CurDAG -> getTargetConstant ( Width , dl , <STR_LIT> ) , getAL ( CurDAG , dl ) , Reg0 } ; CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , Ops ) ; return true ; } } if ( N -> getOpcode ( ) == <STR_LIT> ) { unsigned Width = cast < VTSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) . getSizeInBits ( ) ;


<s> const MDNodeSDNode * MD = dyn_cast < MDNodeSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; const MDString * RegString = dyn_cast < MDString > ( MD -> getMD ( ) -> getOperand ( <NUM_LIT> ) ) ; bool IsThumb2 = Subtarget -> isThumb2 ( ) ; SDLoc DL ( N ) ; std :: vector < SDValue > Ops ; getIntOperandsFromRegisterString ( RegString -> getString ( ) , CurDAG , DL , Ops ) ; if ( ! Ops . empty ( ) ) { unsigned Opcode ; if ( Ops . size ( ) == <NUM_LIT> ) { Opcode = IsThumb2 ? <STR_LIT> : <STR_LIT> ; Ops . insert ( Ops . begin ( ) + <NUM_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; } else { assert ( Ops . size ( ) == <NUM_LIT> && <STR_LIT> ) ; Opcode = IsThumb2 ? <STR_LIT> : <STR_LIT> ; SDValue WriteValue [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; Ops . insert ( Ops . begin ( ) + <NUM_LIT> , WriteValue , WriteValue + <NUM_LIT> ) ; } Ops . push_back ( getAL ( CurDAG , DL ) ) ; Ops . push_back ( CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ;

ReplaceNode ( N , CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , Ops ) ) ;


<s> Opcode = IsThumb2 ? <STR_LIT> : <STR_LIT> ; SDValue WriteValue [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; Ops . insert ( Ops . begin ( ) + <NUM_LIT> , WriteValue , WriteValue + <NUM_LIT> ) ; } Ops . push_back ( getAL ( CurDAG , DL ) ) ; Ops . push_back ( CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; ReplaceNode ( N , CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , Ops ) ) ; return true ; } std :: string SpecialReg = RegString -> getString ( ) . lower ( ) ; int BankedReg = getBankedRegisterMask ( SpecialReg ) ; if ( BankedReg != - <NUM_LIT> ) { Ops = { CurDAG -> getTargetConstant ( BankedReg , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( IsThumb2 ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , Ops ) ) ; return true ; } unsigned Opcode = StringSwitch < unsigned > ( SpecialReg ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrMode6 ( SDNode * Parent , SDValue N , SDValue & Addr , SDValue & Align ) { Addr = N ; unsigned Alignment = <NUM_LIT> ; if ( LSBaseSDNode * LSN = dyn_cast < LSBaseSDNode > ( Parent ) ) {

unsigned LSNAlign = LSN -> getAlignment ( ) ;


<s> if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; assert ( isa < ConstantSDNode > ( Inc . getNode ( ) ) && <STR_LIT> ) ; ( void ) Inc ; Ops . push_back ( Reg0 ) ; } Ops . push_back ( SDValue ( VLdA , <NUM_LIT> ) ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLd = CurDAG -> getMachineNode ( QOpcodes1 [ OpcodeIndex ] , dl , ResTys , Ops . data ( ) , Ops . size ( ) ) ; } MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( VLd ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) return VLd ; SDValue SuperReg = SDValue ( VLd , <NUM_LIT> ) ; assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> && <STR_LIT> == <STR_LIT> + <NUM_LIT> && <STR_LIT> ) ; unsigned Sub0 = ( is64BitVector ? <STR_LIT> : <STR_LIT> ) ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) ReplaceUses ( SDValue ( N , Vec ) , CurDAG -> getTargetExtractSubreg ( Sub0 + Vec , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( VLd , <NUM_LIT> ) ) ; if ( isUpdating ) ReplaceUses ( SDValue ( N , NumVecs + <NUM_LIT> ) , SDValue ( VLd , <NUM_LIT> ) ) ;


<s> SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( QuadDRegs ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } } else { SDValue Q0 = N -> getOperand ( Vec0Idx ) ; SDValue Q1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( PairQRegs ( <STR_LIT> , Q0 , Q1 ) , <NUM_LIT> ) ; } unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( SrcReg ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; SDNode * VSt = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops . data ( ) , Ops . size ( ) ) ; cast < MachineSDNode > ( VSt ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; return VSt ; } SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue RegSeq = SDValue ( QuadQRegs ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ;

const SDValue OpsA [ ] = { MemAddr , Align , Reg0 , RegSeq , Pred , Reg0 , Chain } ;


<s> int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( isShiftedInt < <NUM_LIT> , Shift > ( RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ;

Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ;


<s> if ( isScaledConstantInRange ( N , <NUM_LIT> << Shift , <NUM_LIT> , <NUM_LIT> , RHSC ) ) {


<s> else if ( Align >= <NUM_LIT> && ( IsLE || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , LD -> getOffset ( ) , Offset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else if ( ( IsLE || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , LD -> getOffset ( ) , Offset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else return false ; SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ; SDValue Ops [ ] = { Base , Offset , CurDAG -> getTargetConstant ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , Chain } ; SDNode * New = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , LD -> getValueType ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , Ops ) ; transferMemOperands ( N , New ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( New , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( New , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( New , <NUM_LIT> ) ) ; CurDAG -> RemoveDeadNode ( N ) ;


<s> AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC , <STR_LIT> ) , <STR_LIT> ) ; return AM2_BASE ; } } if ( ( Subtarget -> isLikeA9 ( ) || Subtarget -> isSwift ( ) ) && ! N . hasOneUse ( ) ) { Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ; return AM2_BASE ; } <STR_LIT> AddSub = N . getOpcode ( ) != <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( Offset , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } if ( N . getOpcode ( ) != <STR_LIT> && ShOpcVal == <STR_LIT> && ! ( Subtarget -> isLikeA9 ( ) || Subtarget -> isSwift ( ) || N . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) { ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( N . getOperand ( <NUM_LIT> ) , ShOpcVal , ShAmt ) ) { Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Base = N . getOperand ( <NUM_LIT> ) ; } else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } }

Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , ShAmt , ShOpcVal ) , <STR_LIT> ) ;


<s> int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } else if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC ) , <STR_LIT> ) ; return true ; } Base = N ; Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ;


<s> if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: createDRegPairNode ( EVT VT , SDValue V0 , SDValue V1 ) { DebugLoc dl = V0 . getNode ( ) -> getDebugLoc ( ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 } ;

return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT , Ops , <NUM_LIT> ) ;


<s> DebugLoc dl = V0 . getNode ( ) -> getDebugLoc ( ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ;

SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ;


<s> SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT , Ops , <NUM_LIT> ) ;


<s> DebugLoc dl = V0 . getNode ( ) -> getDebugLoc ( ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ;

const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 } ;


<s> SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ;


<s> SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ;


<s> SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 , V2 , SubReg2 , V3 , SubReg3 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT , Ops , <NUM_LIT> ) ;


<s> SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 , V2 , SubReg2 , V3 , SubReg3 } ;


<s> SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ;

const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 , V2 , SubReg2 , V3 , SubReg3 } ;


<s> DebugLoc dl = V0 . getNode ( ) -> getDebugLoc ( ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 , V2 , SubReg2 , V3 , SubReg3 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT , Ops , <NUM_LIT> ) ;


<s> if ( OptLevel == CodeGenOpt :: None ) return true ; if ( ! CheckVMLxHazard ) return true ; if ( ! Subtarget -> isCortexA8 ( ) && ! Subtarget -> isLikeA9 ( ) && ! Subtarget -> isSwift ( ) ) return true ; if ( ! N -> hasOneUse ( ) ) return false ; SDNode * Use = * N -> use_begin ( ) ; if ( Use -> getOpcode ( ) == <STR_LIT> ) return true ; if ( Use -> isMachineOpcode ( ) ) { const MCInstrDesc & MCID = TII -> get ( Use -> getMachineOpcode ( ) ) ; if ( MCID . mayStore ( ) ) return true ;

unsigned Opcode = MCID . getOpcode ( ) ;


<s> unsigned And_imm = <NUM_LIT> ; if ( ! isOpcWithIntImmediate ( N1 . getNode ( ) , <STR_LIT> , And_imm ) ) { if ( isOpcWithIntImmediate ( N0 . getNode ( ) , <STR_LIT> , And_imm ) ) std :: swap ( N0 , N1 ) ; } if ( ! And_imm ) continue ; unsigned TZ = CountTrailingZeros_32 ( And_imm ) ; if ( TZ != <NUM_LIT> && TZ != <NUM_LIT> ) continue ; And_imm >>= TZ ; if ( And_imm & ( And_imm + <NUM_LIT> ) ) continue ; SDValue Srl = N1 . getOperand ( <NUM_LIT> ) ; unsigned Srl_imm = <NUM_LIT> ; if ( ! isOpcWithIntImmediate ( Srl . getNode ( ) , <STR_LIT> , Srl_imm ) || ( Srl_imm <= <NUM_LIT> ) ) continue ; SDValue CPTmp0 ; SDValue CPTmp1 ; SDValue CPTmp2 ; if ( isThumb2 ) { if ( SelectT2ShifterOperandReg ( N0 , CPTmp0 , CPTmp1 ) ) continue ; } else { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) || SelectRegShifterOperand ( N0 , CPTmp0 , CPTmp1 , CPTmp2 ) ) continue ; } Srl = CurDAG -> getNode ( <STR_LIT> , Srl . getDebugLoc ( ) , <STR_LIT> , Srl . getOperand ( <NUM_LIT> ) , CurDAG -> getConstant ( Srl_imm + TZ , <STR_LIT> ) ) ; N1 = CurDAG -> getNode ( <STR_LIT> , N1 . getDebugLoc ( ) , <STR_LIT> , Srl , CurDAG -> getConstant ( And_imm , <STR_LIT> ) ) ; N1 = CurDAG -> getNode ( <STR_LIT> , N1 . getDebugLoc ( ) , <STR_LIT> , N1 , CurDAG -> getConstant ( TZ , <STR_LIT> ) ) ; CurDAG -> UpdateNodeOperands ( N , N0 , N1 ) ; }


<s> } <STR_LIT> AddSub = N . getOpcode ( ) != <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( Offset , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } if ( N . getOpcode ( ) != <STR_LIT> && ShOpcVal == <STR_LIT> && ! ( Subtarget -> isLikeA9 ( ) || Subtarget -> isSwift ( ) || N . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) { ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( N . getOperand ( <NUM_LIT> ) , ShOpcVal , ShAmt ) ) { Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Base = N . getOperand ( <NUM_LIT> ) ; } else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } }


<s> Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( Inc ) ; else if ( NumVecs > <NUM_LIT> ) Ops . push_back ( Reg0 ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; std :: vector < EVT > ResTys ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDNode * VLdDup = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops . data ( ) , Ops . size ( ) ) ; cast < MachineSDNode > ( VLdDup ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; SuperReg = SDValue ( VLdDup , <NUM_LIT> ) ; assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> && <STR_LIT> ) ; unsigned SubIdx = <STR_LIT> ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) ReplaceUses ( SDValue ( N , Vec ) , CurDAG -> getTargetExtractSubreg ( SubIdx + Vec , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( VLdDup , <NUM_LIT> ) ) ;

if ( isUpdating ) ReplaceUses ( SDValue ( N , NumVecs + <NUM_LIT> ) , SDValue ( VLdDup , <NUM_LIT> ) ) ;


<s> std :: vector < EVT > ResTys ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { SDValue SrcReg ; if ( NumVecs == <NUM_LIT> ) { SrcReg = N -> getOperand ( Vec0Idx ) ; } else if ( is64BitVector ) { SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) SrcReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } } else { SDValue Q0 = N -> getOperand ( Vec0Idx ) ; SDValue Q1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQRegPairNode ( <STR_LIT> , Q0 , Q1 ) , <NUM_LIT> ) ; } unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( NumVecs <= <NUM_LIT> && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs > <NUM_LIT> && Opc != <STR_LIT> ) || ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( SrcReg ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ;


<s> SDValue V2 = N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; RegSeq = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } SmallVector < SDValue , <NUM_LIT> > Ops ; if ( IsExt ) Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( RegSeq ) ; Ops . push_back ( N -> getOperand ( FirstTblReg + NumVecs ) ) ; Ops . push_back ( getAL ( CurDAG ) ) ; Ops . push_back ( CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ) ; return CurDAG -> getMachineNode ( Opc , dl , VT , Ops . data ( ) , Ops . size ( ) ) ;


<s> Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC , <STR_LIT> ) , <STR_LIT> ) ; return AM2_BASE ; } } if ( ( Subtarget -> isLikeA9 ( ) || Subtarget -> isSwift ( ) ) && ! N . hasOneUse ( ) ) { Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ; return AM2_BASE ; } <STR_LIT> AddSub = N . getOpcode ( ) != <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( Offset , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } if ( N . getOpcode ( ) != <STR_LIT> && ShOpcVal == <STR_LIT> && ! ( Subtarget -> isLikeA9 ( ) || Subtarget -> isSwift ( ) || N . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) { ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ;

if ( isShifterOpProfitable ( N . getOperand ( <NUM_LIT> ) , ShOpcVal , ShAmt ) ) {


<s> Base = N ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ;


<s> int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } else if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC ) , <STR_LIT> ) ; return true ; }


<s> } if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getSExtValue ( ) ;

if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ;


<s> if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { if ( SelectT2AddrModeImm8 ( N , Base , OffImm ) ) return false ; int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; }

OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ;


<s> int RHSC = ( int ) RHS -> getSExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( ( RHSC >= - <NUM_LIT> ) && ( RHSC < <NUM_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ;

if ( Base . getOpcode ( ) == <STR_LIT> ) {


<s> return true ; } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; RegisterSDNode * LHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || ( LHSR && LHSR -> getReg ( ) == <STR_LIT> ) ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ; return true ; } } return false ;


<s> Ops . push_back ( CurDAG -> getTargetConstant ( <STR_LIT> , Loc , <STR_LIT> ) ) ;

Ops . push_back ( CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> Ops . push_back ( CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> Ops . push_back ( PredicateMask ) ; Ops . push_back ( CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> if ( isOpcWithIntImmediate ( N0 . getNode ( ) , <STR_LIT> , And_imm ) ) std :: swap ( N0 , N1 ) ; } if ( ! And_imm ) continue ; unsigned TZ = countTrailingZeros ( And_imm ) ; if ( TZ != <NUM_LIT> && TZ != <NUM_LIT> ) continue ; And_imm >>= TZ ; if ( And_imm & ( And_imm + <NUM_LIT> ) ) continue ; SDValue Srl = N1 . getOperand ( <NUM_LIT> ) ; unsigned Srl_imm = <NUM_LIT> ; if ( ! isOpcWithIntImmediate ( Srl . getNode ( ) , <STR_LIT> , Srl_imm ) || ( Srl_imm <= <NUM_LIT> ) ) continue ; SDValue CPTmp0 ; SDValue CPTmp1 ; SDValue CPTmp2 ; if ( isThumb2 ) { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) ) continue ; } else { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) || SelectRegShifterOperand ( N0 , CPTmp0 , CPTmp1 , CPTmp2 ) ) continue ; } Srl = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Srl ) , <STR_LIT> , Srl . getOperand ( <NUM_LIT> ) , CurDAG -> getConstant ( Srl_imm + TZ , SDLoc ( Srl ) , <STR_LIT> ) ) ; N1 = CurDAG -> getNode ( <STR_LIT> , SDLoc ( N1 ) , <STR_LIT> , Srl , CurDAG -> getConstant ( And_imm , SDLoc ( Srl ) , <STR_LIT> ) ) ; N1 = CurDAG -> getNode ( <STR_LIT> , SDLoc ( N1 ) , <STR_LIT> , N1 , CurDAG -> getConstant ( TZ , SDLoc ( Srl ) , <STR_LIT> ) ) ;

CurDAG -> UpdateNodeOperands ( & N , N0 , N1 ) ;


<s> SDValue CPTmp0 ; SDValue CPTmp1 ; SDValue CPTmp2 ; if ( isThumb2 ) { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) ) continue ; } else { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) || SelectRegShifterOperand ( N0 , CPTmp0 , CPTmp1 , CPTmp2 ) ) continue ; } Srl = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Srl ) , <STR_LIT> , Srl . getOperand ( <NUM_LIT> ) , CurDAG -> getConstant ( Srl_imm + TZ , SDLoc ( Srl ) , <STR_LIT> ) ) ;

N1 = CurDAG -> getNode ( <STR_LIT> , SDLoc ( N1 ) , <STR_LIT> , Srl , CurDAG -> getConstant ( And_imm , SDLoc ( Srl ) , <STR_LIT> ) ) ;


<s> assert ( N -> getOpcode ( ) == <STR_LIT> ) ; SwitchEQNEToPLMI = false ; if ( ! Subtarget -> isThumb ( ) ) return ; SDValue And = N -> getOperand ( <NUM_LIT> ) ; if ( ! And -> hasOneUse ( ) ) return ; SDValue Zero = N -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Zero ) || ! cast < ConstantSDNode > ( Zero ) -> isZero ( ) || And -> getOpcode ( ) != <STR_LIT> ) return ; SDValue X = And . getOperand ( <NUM_LIT> ) ; auto C = dyn_cast < ConstantSDNode > ( And . getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return ; auto Range = getContiguousRangeOfSetBits ( C -> getAPIntValue ( ) ) ; if ( ! Range ) return ; SDNode * NewN ; SDLoc dl ( N ) ; auto EmitShift = [ & ] ( unsigned Opc , SDValue Src , unsigned Imm ) -> SDNode * { if ( Subtarget -> isThumb2 ( ) ) { Opc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { Src , CurDAG -> getTargetConstant ( Imm , dl , <STR_LIT> ) , getAL ( CurDAG , dl ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) } ; return CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops ) ; } else { SDValue Ops [ ] = { CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) , Src , CurDAG -> getTargetConstant ( Imm , dl , <STR_LIT> ) , getAL ( CurDAG , dl ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) } ; return CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops ) ; } } ; if ( Range -> second == <NUM_LIT> ) { NewN = EmitShift ( <STR_LIT> , X , <NUM_LIT> - Range -> first ) ;

ReplaceNode ( And . getNode ( ) , NewN ) ;