<s> SDValue Op = N -> getOperand ( <NUM_LIT> ) ; unsigned OpOpcode = Op . getNode ( ) -> getOpcode ( ) ; if ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) || ( OpOpcode != <STR_LIT> && OpOpcode != <STR_LIT> ) ) return SDValue ( ) ; SDValue ConstVec = N -> getOperand ( <NUM_LIT> ) ; if ( ! isa < BuildVectorSDNode > ( ConstVec ) ) return SDValue ( ) ; MVT FloatTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; uint32_t FloatBits = FloatTy . getSizeInBits ( ) ; MVT IntTy = Op . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getVectorElementType ( ) ;

uint32_t IntBits = IntTy . getSizeInBits ( ) ;


<s> if ( ! Subtarget -> hasNEON ( ) ) return SDValue ( ) ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; unsigned OpOpcode = Op . getNode ( ) -> getOpcode ( ) ; if ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) || ( OpOpcode != <STR_LIT> && OpOpcode != <STR_LIT> ) ) return SDValue ( ) ; SDValue ConstVec = N -> getOperand ( <NUM_LIT> ) ; if ( ! isa < BuildVectorSDNode > ( ConstVec ) ) return SDValue ( ) ; MVT FloatTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; uint32_t FloatBits = FloatTy . getSizeInBits ( ) ; MVT IntTy = Op . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getVectorElementType ( ) ; uint32_t IntBits = IntTy . getSizeInBits ( ) ; unsigned NumLanes = Op . getValueType ( ) . getVectorNumElements ( ) ; if ( FloatBits != <NUM_LIT> || IntBits > <NUM_LIT> || NumLanes > <NUM_LIT> ) { return SDValue ( ) ; } BitVector UndefElements ; BuildVectorSDNode * BV = cast < BuildVectorSDNode > ( ConstVec ) ; int32_t C = BV -> getConstantFPSplatPow2ToLog2Int ( & UndefElements , <NUM_LIT> ) ; if ( C == - <NUM_LIT> || C == <NUM_LIT> || C > <NUM_LIT> ) return SDValue ( ) ; SDLoc dl ( N ) ; bool isSigned = OpOpcode == <STR_LIT> ; SDValue ConvInput = Op . getOperand ( <NUM_LIT> ) ; if ( IntBits < FloatBits ) ConvInput = DAG . getNode ( isSigned ? <STR_LIT> : <STR_LIT> , dl , NumLanes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> , ConvInput ) ; unsigned IntrinsicOpcode = isSigned ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getConstant ( IntrinsicOpcode , dl , <STR_LIT> ) , ConvInput , DAG . getConstant ( C , dl , <STR_LIT> ) ) ;


<s> static SDValue PerformVLDCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI ) { if ( DCI . isBeforeLegalize ( ) || DCI . isCalledByLegalizer ( ) ) return SDValue ( ) ;


<s> static SDValue PerformVLDCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI ) { if ( DCI . isBeforeLegalize ( ) || DCI . isCalledByLegalizer ( ) ) return SDValue ( ) ; return CombineBaseUpdate ( N , DCI ) ;


<s> SDValue NewLD2 = DAG . getLoad ( <STR_LIT> , DL , NewLD1 . getValue ( <NUM_LIT> ) , OffsetPtr , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , std :: min ( <NUM_LIT> , LD -> getAlignment ( ) / <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , NewLD2 . getValue ( <NUM_LIT> ) ) ; if ( DCI . DAG . getDataLayout ( ) . isBigEndian ( ) ) std :: swap ( NewLD1 , NewLD2 ) ; SDValue Result = DCI . CombineTo ( N , NewLD1 , NewLD2 ) ; return Result ;


<s> SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue NewLD2 = DAG . getLoad ( <STR_LIT> , DL , NewLD1 . getValue ( <NUM_LIT> ) , OffsetPtr , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , std :: min ( <NUM_LIT> , LD -> getAlignment ( ) / <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , NewLD2 . getValue ( <NUM_LIT> ) ) ; if ( DCI . DAG . getDataLayout ( ) . isBigEndian ( ) ) std :: swap ( NewLD1 , NewLD2 ) ; SDValue Result = DCI . CombineTo ( N , NewLD1 , NewLD2 ) ; return Result ; } return SDValue ( ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : ExpandREAD_REGISTER ( N , Results , DAG ) ; break ; case <STR_LIT> : Res = ExpandBITCAST ( N , DAG ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = Expand64BitShift ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerREM ( N , DAG ) ; break ; case <STR_LIT> : ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ;


<s> case <STR_LIT> : ExpandREAD_REGISTER ( N , Results , DAG ) ; break ; case <STR_LIT> : Res = ExpandBITCAST ( N , DAG ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = Expand64BitShift ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> :


<s> SDLoc DL ( N ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) } ; SDValue Cycles32 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cycles32 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ;

Results . push_back ( Cycles32 . getValue ( <NUM_LIT> ) ) ;


<s> SDValue Cycles32 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cycles32 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ;


<s> AddDefaultCC ( AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( <NUM_LIT> ) ) ) ; unsigned NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( NewVReg2 , RegState :: Kill ) . addImm ( PCLabelId ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( NewVReg3 , RegState :: Kill ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( FIMMOSt ) ) ; } else if ( isThumb ) { unsigned NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addMemOperand ( CPMMO ) ) ; unsigned NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( PCLabelId ) ; unsigned NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( <STR_LIT> , RegState :: Define ) . addImm ( <NUM_LIT> ) ) ; unsigned NewVReg4 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg4 ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( NewVReg2 , RegState :: Kill ) . addReg ( NewVReg3 , RegState :: Kill ) ) ; unsigned NewVReg5 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg5 ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( NewVReg4 , RegState :: Kill ) . addReg ( NewVReg5 , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addMemOperand ( FIMMOSt ) ) ; } else { unsigned NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addImm ( <NUM_LIT> ) . addMemOperand ( CPMMO ) ) ; unsigned NewVReg2 = MRI -> createVirtualRegister ( TRC ) ;

AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( PCLabelId ) ) ;


<s> bool <ISA_LIT>TargetLowering :: shouldAlignPointerArgs ( CallInst * CI , unsigned & MinSize , unsigned & PrefAlign ) const { if ( ! isa < MemIntrinsic > ( CI ) ) return false ; MinSize = <NUM_LIT> ; PrefAlign = ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isMClass ( ) ? <NUM_LIT> : <NUM_LIT> ) ;


PrefAlign = ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isMClass ( ) ? <NUM_LIT> : <NUM_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const {


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { return true ;


<s> unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return ( ( Size == <NUM_LIT> ) && ! Subtarget -> isMClass ( ) ) ? AtomicExpansionKind :: LLOnly : AtomicExpansionKind :: None ;


<s> return ( Size <= ( Subtarget -> isMClass ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ? AtomicExpansionKind :: LLSC : AtomicExpansionKind :: None ;


<s> return ( Size == <NUM_LIT> ) && ! Subtarget -> isMClass ( ) ;


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const {

unsigned Size = SI -> getValueOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ;


<s> ShuffleSourceInfo ( SDValue Vec ) : Vec ( Vec ) , MinElt ( UINT_MAX ) , MaxElt ( <NUM_LIT> ) , ShuffleVec ( Vec ) , WindowBase ( <NUM_LIT> ) , WindowScale ( <NUM_LIT> ) {


<s> SDNode * BVN = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; assert ( BVN -> getOpcode ( ) == <STR_LIT> && BVN -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; unsigned LowElt = DAG . getDataLayout ( ) . isBigEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , BVN -> getOperand ( LowElt ) , BVN -> getOperand ( LowElt + <NUM_LIT> ) ) ; } assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ;

unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ;


<s> SDValue FIN = DAG . getFrameIndex ( FrameIndex , PtrVT ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; const TargetRegisterClass * RC = AFI -> isThumb1OnlyFunction ( ) ? & <STR_LIT> : & <STR_LIT> ; for ( unsigned Reg = RBegin , i = <NUM_LIT> ; Reg < REnd ; ++ Reg , ++ i ) { unsigned VReg = MF . addLiveIn ( Reg , RC ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( OrigArg , <NUM_LIT> * i ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , dl , PtrVT , FIN , DAG . getConstant ( <NUM_LIT> , dl , PtrVT ) ) ; }

if ( ! MemOps . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOps ) ;


<s> return Subtarget -> isTargetMachO ( ) ;


<s> return Subtarget -> useSoftFloat ( ) ;


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ;

int FrameIndex = StoreByValRegs ( CCInfo , DAG , dl , Chain , nullptr , CCInfo . getInRegsParamsCount ( ) , CCInfo . getNextStackOffset ( ) , <NUM_LIT> ) ;


<s> if ( ! MI -> hasOptionalDef ( ) || ! MCID -> OpInfo [ ccOutIdx ] . isOptionalDef ( ) ) { assert ( ! NewOpc && <STR_LIT> ) ; return ; } bool definesCPSR = false ; bool deadCPSR = false ; for ( unsigned i = MCID -> getNumOperands ( ) , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ;

if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == <STR_LIT> ) {


<s> const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == <STR_LIT> ) { definesCPSR = true ; if ( MO . isDead ( ) ) deadCPSR = true ; MI -> RemoveOperand ( i ) ; break ; } } if ( ! definesCPSR ) { assert ( ! NewOpc && <STR_LIT> ) ; return ; } assert ( deadCPSR == ! Node -> hasAnyUseOfValue ( <NUM_LIT> ) && <STR_LIT> ) ; if ( deadCPSR ) {

assert ( ! MI -> getOperand ( ccOutIdx ) . getReg ( ) && <STR_LIT> ) ;


<s> case <STR_LIT> : { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } return false ; } case <STR_LIT> : case <STR_LIT> : { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || isLittleEndian ( ) ) ) { if ( Fast ) * Fast = true ; return true ; } return false ;


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , bool * Fast ) const { bool AllowsUnaligned = Subtarget -> allowsUnalignedMem ( ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ;


<s> } } EVT VecTy ; if ( isLoad ) VecTy = N -> getValueType ( <NUM_LIT> ) ; else if ( isIntrinsic ) VecTy = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) . getValueType ( ) ; else VecTy = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned NumBytes = NumVecs * VecTy . getSizeInBits ( ) / <NUM_LIT> ; if ( isLaneOp ) NumBytes /= VecTy . getVectorNumElements ( ) ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; if ( ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ) { uint64_t IncVal = CInc -> getZExtValue ( ) ; if ( IncVal != NumBytes ) continue ; } else if ( NumBytes >= <NUM_LIT> * <NUM_LIT> ) { continue ; } EVT AlignedVecTy = VecTy ; if ( LSBaseSDNode * LSN = dyn_cast < LSBaseSDNode > ( N ) ) { unsigned Alignment = LSN -> getAlignment ( ) ; if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; if ( Alignment < VecTy . getScalarSizeInBits ( ) / <NUM_LIT> ) { MVT EltTy = <STR_LIT> ( Alignment * <NUM_LIT> ) ; assert ( NumVecs == <NUM_LIT> && <STR_LIT> ) ; assert ( ! isLaneOp && <STR_LIT> ) ; unsigned NumElts = NumBytes / ( EltTy . getSizeInBits ( ) / <NUM_LIT> ) ; AlignedVecTy = <STR_LIT> ( EltTy , NumElts ) ; } } EVT Tys [ <NUM_LIT> ] ; unsigned NumResultVecs = ( isLoad ? NumVecs : <NUM_LIT> ) ; unsigned n ; for ( n = <NUM_LIT> ; n < NumResultVecs ; ++ n ) Tys [ n ] = AlignedVecTy ; Tys [ n ++ ] = <STR_LIT> ; Tys [ n ] = <STR_LIT> ; SDVTList SDTys = DAG . getVTList ( makeArrayRef ( Tys , NumResultVecs + <NUM_LIT> ) ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand ( AddrOpIdx ) ) ; Ops . push_back ( Inc ) ; if ( StoreSDNode * StN = dyn_cast < StoreSDNode > ( N ) ) { Ops . push_back ( StN -> getValue ( ) ) ; Ops . push_back ( DAG . getConstant ( StN -> getAlignment ( ) , <STR_LIT> ) ) ; } else { for ( unsigned i = AddrOpIdx + <NUM_LIT> ; i < N -> getNumOperands ( ) ; ++ i ) Ops . push_back ( N -> getOperand ( i ) ) ; } if ( AlignedVecTy != VecTy && N -> getOpcode ( ) == <STR_LIT> ) { SDValue & StVal = Ops [ Ops . size ( ) - <NUM_LIT> ] ; StVal = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , AlignedVecTy , StVal ) ; } MemSDNode * MemInt = cast < MemSDNode > ( N ) ;

SDValue UpdN = DAG . getMemIntrinsicNode ( NewOpc , SDLoc ( N ) , SDTys , Ops , AlignedVecTy , MemInt -> getMemOperand ( ) ) ;


<s> unsigned RBegin , REnd ; CCInfo . getInRegsParamInfo ( InRegsParamRecordIdx , RBegin , REnd ) ; NumGPRs = REnd - RBegin ; } else { unsigned int firstUnalloced ; firstUnalloced = CCInfo . getFirstUnallocated ( GPRArgRegs , sizeof ( GPRArgRegs ) / sizeof ( GPRArgRegs [ <NUM_LIT> ] ) ) ; NumGPRs = ( firstUnalloced <= <NUM_LIT> ) ? ( <NUM_LIT> - firstUnalloced ) : <NUM_LIT> ; } unsigned Align = Subtarget -> getFrameLowering ( ) -> getStackAlignment ( ) ; ArgRegsSize = NumGPRs * <NUM_LIT> ; if ( NumGPRs && Align > <NUM_LIT> && ( ArgRegsSize < ArgSize || InRegsParamRecordIdx >= CCInfo . getInRegsParamsCount ( ) ) ) { <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Padding = OffsetToAlignment ( ArgRegsSize + AFI -> getArgRegsSaveSize ( ) , Align ) ;

ArgRegsSaveSize = ArgRegsSize + Padding ;


<s> Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = isAtLeastRelease ( Ord ) ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Function * Strex = <STR_LIT> ( M , Int ) ; Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , <STR_LIT> ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , <NUM_LIT> ) , Int32Ty , <STR_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall3 ( Strex , Lo , Hi , Addr ) ; } <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Strex = <STR_LIT> ( M , Int , Tys ) ; return Builder . CreateCall2 ( Strex , Builder . CreateZExtOrBitCast ( Val , Strex -> getFunctionType ( ) -> getParamType ( <NUM_LIT> ) ) , Addr ) ;


bool result = isHomogeneousAggregate ( Ty , Base , Members ) ;


<s> bool result = isHomogeneousAggregate ( Ty , Base , Members ) ; DEBUG ( dbgs ( ) << <STR_LIT> << result << <STR_LIT> ; Ty -> dump ( ) ) ;


<s> if ( ( ! IsMemset || ZeroMemset ) && Subtarget -> hasNEON ( ) && ! F -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Size >= <NUM_LIT> && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , & Fast ) && Fast ) ) ) { return <STR_LIT> ;

} else if ( Size >= <NUM_LIT> && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , & Fast ) && Fast ) ) ) {


<s> RCPair <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; case 'h' : if ( Subtarget -> isThumb ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'r' : if ( Subtarget -> isThumb1Only ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; case 'w' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'x' :


<s> RCPair <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; case 'h' : if ( Subtarget -> isThumb ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'r' : if ( Subtarget -> isThumb1Only ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; case 'w' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'x' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 't' : if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; } } if ( StringRef ( <STR_LIT> ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ;

return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ;


<s> else if ( <STR_LIT> ( Op . getNode ( ) ) || <STR_LIT> ( Op . getNode ( ) ) ) { if ( Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue WrapperOp = Op . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ;

if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( WrapperOp ) ) if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( CP -> getConstVal ( ) ) ) return CFP -> getValueAPF ( ) . isPosZero ( ) ;


<s> static bool isFloatingPointZero ( SDValue Op ) { if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Op ) ) return CFP -> getValueAPF ( ) . isPosZero ( ) ; else if ( <STR_LIT> ( Op . getNode ( ) ) || <STR_LIT> ( Op . getNode ( ) ) ) { if ( Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue WrapperOp = Op . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( WrapperOp ) ) if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( CP -> getConstVal ( ) ) ) return CFP -> getValueAPF ( ) . isPosZero ( ) ; } } else if ( Op -> getOpcode ( ) == <STR_LIT> && Op -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDValue BitcastOp = Op -> getOperand ( <NUM_LIT> ) ; if ( BitcastOp -> getOpcode ( ) == <STR_LIT> ) { SDValue MoveOp = BitcastOp -> getOperand ( <NUM_LIT> ) ; if ( MoveOp -> getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( MoveOp ) -> getZExtValue ( ) == <NUM_LIT> ) {


<s> SDLoc dl ( Op ) ; if ( ! Subtarget -> hasDataBarrier ( ) ) { assert ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isThumb ( ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } ConstantSDNode * OrdN = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; AtomicOrdering Ord = static_cast < AtomicOrdering > ( OrdN -> getZExtValue ( ) ) ; <STR_LIT> Domain = <STR_LIT> ; if ( Subtarget -> isMClass ( ) ) { Domain = <STR_LIT> ; } else if ( Subtarget -> isSwift ( ) && Ord == Release ) {


<s> } if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; if ( getTargetMachine ( ) . Options . UnsafeFPMath && ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ) { SDValue Result = OptimizeVFPBrcond ( Op , DAG ) ; if ( Result . getNode ( ) ) return Result ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , <STR_LIT> ) ;

SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ;


<s> if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; if ( getTargetMachine ( ) . Options . UnsafeFPMath && ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ) { SDValue Result = OptimizeVFPBrcond ( Op , DAG ) ; if ( Result . getNode ( ) ) return Result ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , <STR_LIT> ) ;


<s> int ImmVal = IsDouble ? <STR_LIT> ( FPVal ) : <STR_LIT> ( FPVal ) ; if ( ImmVal != - <NUM_LIT> ) { if ( IsDouble || ! ST -> useNEONForSinglePrecisionFP ( ) ) { return Op ; } SDLoc DL ( Op ) ; SDValue NewVal = DAG . getTargetConstant ( ImmVal , <STR_LIT> ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewVal ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } if ( ! ST -> hasNEON ( ) || ( ! IsDouble && ! ST -> useNEONForSinglePrecisionFP ( ) ) ) return SDValue ( ) ; EVT VMovVT ; uint64_t iVal = FPVal . bitcastToAPInt ( ) . getZExtValue ( ) ; if ( IsDouble && ( iVal & <NUM_LIT> ) != ( iVal >> <NUM_LIT> ) ) return SDValue ( ) ; SDValue NewVal = isNEONModifiedImm ( iVal & <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , DAG , VMovVT , false , VMOVModImm ) ; if ( NewVal != SDValue ( ) ) { SDLoc DL ( Op ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , VMovVT , NewVal ) ;

if ( IsDouble ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant ) ;


<s> SDLoc DL ( Op ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; SDValue Words = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Size , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Flag ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , Words , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Chain , Flag ) ; SDValue NewSP = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> ) ; Chain = NewSP . getValue ( <NUM_LIT> ) ; SDValue Ops [ <NUM_LIT> ] = { NewSP , Chain } ; return DAG . getMergeValues ( Ops , DL ) ;


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; SDValue Words = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Size , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Flag ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , Words , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ;

SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ;


<s> SDValue SrcVal = Op . getOperand ( <NUM_LIT> ) ;

return makeLibCall ( DAG , LC , Op . getValueType ( ) , & SrcVal , <NUM_LIT> , false , SDLoc ( Op ) ) . first ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP_ROUND ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && Subtarget -> isFPOnlySP ( ) && <STR_LIT> ) ;


<s> SDLoc dl ( Op ) ; unsigned Opc ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } Op = DAG . getNode ( Opc , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ;


<s> Args . push_back ( Entry ) ; const char * LibcallName = ( ArgVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , getPointerTy ( ) ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , Callee , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; SDValue LoadSin = DAG . getLoad ( ArgVT , dl , CallResult . second , SRet , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;

SDValue Add = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , SRet , DAG . getIntPtrConstant ( ArgVT . getStoreSize ( ) ) ) ;


<s> return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : { EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } case <STR_LIT> : { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ;

CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ;


<s> unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; if ( RelocM == Reloc :: PIC_ ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; }


<s> return getCMOV ( SDLoc ( Op ) , VT , SelectTrue , SelectFalse , <ISA_LIT>cc , CCR , OverflowCmp , DAG ) ; } if ( Cond . getOpcode ( ) == <STR_LIT> && Cond . hasOneUse ( ) ) { const ConstantSDNode * CMOVTrue = dyn_cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ; const ConstantSDNode * CMOVFalse = dyn_cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ; if ( CMOVTrue && CMOVFalse ) { unsigned CMOVTrueVal = CMOVTrue -> getZExtValue ( ) ; unsigned CMOVFalseVal = CMOVFalse -> getZExtValue ( ) ; SDValue True ; SDValue False ; if ( CMOVTrueVal == <NUM_LIT> && CMOVFalseVal == <NUM_LIT> ) { True = SelectTrue ; False = SelectFalse ; } else if ( CMOVTrueVal == <NUM_LIT> && CMOVFalseVal == <NUM_LIT> ) { True = SelectFalse ; False = SelectTrue ; } if ( True . getNode ( ) && False . getNode ( ) ) { EVT VT = Op . getValueType ( ) ;

SDValue <ISA_LIT>cc = Cond . getOperand ( <NUM_LIT> ) ;


<s> RHS = DAG . getConstant ( <NUM_LIT> , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) == <STR_LIT> ) { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { CC = getInverseCCForVSEL ( CC ) ; std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { if ( getTargetMachine ( ) . Options . UnsafeFPMath ) { if ( LHS == TrueVal && RHS == FalseVal ) { if ( CC == <STR_LIT> || CC == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , TrueVal , FalseVal ) ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , TrueVal , FalseVal ) ; } else if ( LHS == FalseVal && RHS == TrueVal ) { if ( CC == <STR_LIT> || CC == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , TrueVal , FalseVal ) ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , TrueVal , FalseVal ) ; } } bool swpCmpOps = false ; bool swpVselOps = false ; checkVSELConstraints ( CC , CondCode , swpCmpOps , swpVselOps ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { if ( swpCmpOps ) std :: swap ( LHS , RHS ) ; if ( swpVselOps ) std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ;

SDValue Result = getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ;


<s> unsigned Mask2 = N11C -> getZExtValue ( ) ; if ( ( Mask & ( ~ Mask2 ) ) == <NUM_LIT> ) return DCI . DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N1 . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; } return SDValue ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformSELECT_CCCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformLOADCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformVLDCombine ( N , DCI ) ; case <STR_LIT> : return Perform<ISA_LIT>BUILD_VECTORCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformVLDCombine ( N , DCI ) ; default : break ; } break ;


<s> SelectionDAG & DAG = DCI . DAG ; bool isBigEndian = DAG . getTargetLoweringInfo ( ) . isBigEndian ( ) ; SDLoc DL ( St ) ; SDValue BasePtr = St -> getBasePtr ( ) ; SDValue NewST1 = DAG . getStore ( St -> getChain ( ) , DL , StVal . getNode ( ) -> getOperand ( isBigEndian ? <NUM_LIT> : <NUM_LIT> ) , BasePtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , St -> getAlignment ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getStore ( NewST1 . getValue ( <NUM_LIT> ) , DL , StVal . getNode ( ) -> getOperand ( isBigEndian ? <NUM_LIT> : <NUM_LIT> ) , OffsetPtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , std :: min ( <NUM_LIT> , St -> getAlignment ( ) / <NUM_LIT> ) ) ; } if ( StVal . getValueType ( ) == <STR_LIT> && StVal . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { SelectionDAG & DAG = DCI . DAG ; SDLoc dl ( StVal ) ; SDValue IntVec = StVal . getOperand ( <NUM_LIT> ) ; EVT FloatVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , IntVec . getValueType ( ) . getVectorNumElements ( ) ) ; SDValue Vec = DAG . getNode ( <STR_LIT> , dl , FloatVT , IntVec ) ; SDValue ExtElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , StVal . getOperand ( <NUM_LIT> ) ) ; dl = SDLoc ( N ) ; SDValue V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ExtElt ) ; DCI . AddToWorklist ( Vec . getNode ( ) ) ; DCI . AddToWorklist ( ExtElt . getNode ( ) ) ; DCI . AddToWorklist ( V . getNode ( ) ) ; return DAG . getStore ( St -> getChain ( ) , dl , V , St -> getBasePtr ( ) , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , St -> getAlignment ( ) , St -> getAAInfo ( ) ) ; }

if ( <STR_LIT> ( N ) && VT . isVector ( ) && DCI . DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return CombineBaseUpdate ( N , DCI ) ;


<s> EVT StoreVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StoreType , VT . getSizeInBits ( ) / EVT ( StoreType ) . getSizeInBits ( ) ) ; assert ( StoreVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue ShuffWide = DAG . getNode ( <STR_LIT> , DL , StoreVecVT , Shuff ) ; SmallVector < SDValue , <NUM_LIT> > Chains ; SDValue Increment = DAG . getConstant ( StoreType . getSizeInBits ( ) / <NUM_LIT> , TLI . getPointerTy ( ) ) ; SDValue BasePtr = St -> getBasePtr ( ) ; unsigned E = ( ToEltSz * NumElems ) / StoreType . getSizeInBits ( ) ; for ( unsigned I = <NUM_LIT> ; I < E ; I ++ ) { SDValue SubVec = DAG . getNode ( <STR_LIT> , DL , StoreType , ShuffWide , DAG . getIntPtrConstant ( I ) ) ; SDValue Ch = DAG . getStore ( St -> getChain ( ) , DL , SubVec , BasePtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , St -> getAlignment ( ) ) ; BasePtr = DAG . getNode ( <STR_LIT> , DL , BasePtr . getValueType ( ) , BasePtr , Increment ) ; Chains . push_back ( Ch ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chains ) ; } if ( ! <STR_LIT> ( St ) ) return SDValue ( ) ; if ( StVal . getNode ( ) -> getOpcode ( ) == <STR_LIT> && StVal . getNode ( ) -> hasOneUse ( ) ) { SelectionDAG & DAG = DCI . DAG ; bool isBigEndian = DAG . getTargetLoweringInfo ( ) . isBigEndian ( ) ; SDLoc DL ( St ) ; SDValue BasePtr = St -> getBasePtr ( ) ; SDValue NewST1 = DAG . getStore ( St -> getChain ( ) , DL , StVal . getNode ( ) -> getOperand ( isBigEndian ? <NUM_LIT> : <NUM_LIT> ) , BasePtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , St -> getAlignment ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getStore ( NewST1 . getValue ( <NUM_LIT> ) , DL , StVal . getNode ( ) -> getOperand ( isBigEndian ? <NUM_LIT> : <NUM_LIT> ) , OffsetPtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , std :: min ( <NUM_LIT> , St -> getAlignment ( ) / <NUM_LIT> ) ) ;


<s> if ( ConstVec . getOpcode ( ) != <STR_LIT> || ! isConstVecPow2 ( ConstVec , isSigned , C ) ) return SDValue ( ) ; MVT FloatTy = Op . getSimpleValueType ( ) . getVectorElementType ( ) ; MVT IntTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; unsigned NumLanes = Op . getValueType ( ) . getVectorNumElements ( ) ; if ( FloatTy . getSizeInBits ( ) != <NUM_LIT> || IntTy . getSizeInBits ( ) > <NUM_LIT> || NumLanes > <NUM_LIT> ) { return SDValue ( ) ; } unsigned IntrinsicOpcode = isSigned ? <STR_LIT> : <STR_LIT> ;

SDValue FixConv = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , NumLanes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> , DAG . getConstant ( IntrinsicOpcode , <STR_LIT> ) , N0 , DAG . getConstant ( Log2_64 ( C ) , <STR_LIT> ) ) ;


<s> SDValue Op = N -> getOperand ( <NUM_LIT> ) ; if ( ! Subtarget -> hasNEON ( ) || ! Op . getValueType ( ) . isVector ( ) || Op . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; uint64_t C ; SDValue N0 = Op -> getOperand ( <NUM_LIT> ) ; SDValue ConstVec = Op -> getOperand ( <NUM_LIT> ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> ; if ( ConstVec . getOpcode ( ) != <STR_LIT> || ! isConstVecPow2 ( ConstVec , isSigned , C ) ) return SDValue ( ) ; MVT FloatTy = Op . getSimpleValueType ( ) . getVectorElementType ( ) ; MVT IntTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; unsigned NumLanes = Op . getValueType ( ) . getVectorNumElements ( ) ; if ( FloatTy . getSizeInBits ( ) != <NUM_LIT> || IntTy . getSizeInBits ( ) > <NUM_LIT> || NumLanes > <NUM_LIT> ) { return SDValue ( ) ; } unsigned IntrinsicOpcode = isSigned ? <STR_LIT> : <STR_LIT> ;


<s> SDValue NewLD1 = DAG . getLoad ( <STR_LIT> , DL , LD -> getChain ( ) , BasePtr , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue NewLD2 = DAG . getLoad ( <STR_LIT> , DL , NewLD1 . getValue ( <NUM_LIT> ) , OffsetPtr , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , std :: min ( <NUM_LIT> , LD -> getAlignment ( ) / <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , NewLD2 . getValue ( <NUM_LIT> ) ) ; if ( DCI . DAG . getTargetLoweringInfo ( ) . isBigEndian ( ) ) std :: swap ( NewLD1 , NewLD2 ) ;

SDValue Result = DCI . CombineTo ( N , NewLD1 , NewLD2 ) ;


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ;

return ( Size == <NUM_LIT> ) && ! Subtarget -> isMClass ( ) ;


<s> unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ;


<s> unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return Size <= ( Subtarget -> isMClass ( ) ? <NUM_LIT> : <NUM_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ;

return Size <= ( Subtarget -> isMClass ( ) ? <NUM_LIT> : <NUM_LIT> ) ;


<s> switch ( TM . getCodeModel ( ) ) { case CodeModel :: Small : case CodeModel :: Medium : case CodeModel :: Default : case CodeModel :: Kernel : BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addExternalSymbol ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; case CodeModel :: Large : case CodeModel :: JITDefault : { MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) . addExternalSymbol ( <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; } } AddDefaultCC ( AddDefaultPred ( BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ) ; MI -> eraseFromParent ( ) ;


<s> MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) . addExternalSymbol ( <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; } }

AddDefaultCC ( AddDefaultPred ( BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ) ;


<s> ( const TargetRegisterClass * ) & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: SExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: ZExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; assert ( VA . getValVT ( ) != <STR_LIT> && <STR_LIT> ) ; int index = ArgLocs [ i ] . getValNo ( ) ; if ( index != lastInsIndex ) { <STR_LIT> Flags = Ins [ index ] . Flags ; if ( Flags . isByVal ( ) ) { unsigned CurByValIndex = CCInfo . getInRegsParamsProcessed ( ) ; ByValStoreOffset = RoundUpToAlignment ( ByValStoreOffset , Flags . getByValAlign ( ) ) ; int FrameIndex = StoreByValRegs ( CCInfo , DAG , dl , Chain , CurOrigArg , CurByValIndex , Ins [ VA . getValNo ( ) ] . PartOffset , VA . getLocMemOffset ( ) , Flags . getByValSize ( ) , true , ByValStoreOffset , TotalArgRegsSaveSize ) ; ByValStoreOffset += Flags . getByValSize ( ) ; ByValStoreOffset = std :: min ( ByValStoreOffset , <NUM_LIT> ) ; InVals . push_back ( DAG . getFrameIndex ( FrameIndex , getPointerTy ( ) ) ) ; CCInfo . nextInRegsParam ( ) ; } else { unsigned FIOffset = VA . getLocMemOffset ( ) ; int FI = MFI -> CreateFixedObject ( VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> , FIOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ) ; } lastInsIndex = index ; } } } if ( isVarArg ) VarArgStyleRegisters ( CCInfo , DAG , dl , Chain , CCInfo . getNextStackOffset ( ) , TotalArgRegsSaveSize ) ;

AFI -> setArgumentStackSize ( CCInfo . getNextStackOffset ( ) ) ;


<s> void <ISA_LIT>TargetLowering :: addAllExtLoads ( const MVT From , const MVT To , LegalizeAction Action ) { setLoadExtAction ( <STR_LIT> , From , To , Action ) ; setLoadExtAction ( <STR_LIT> , From , To , Action ) ; setLoadExtAction ( <STR_LIT> , From , To , Action ) ;


<s> setLoadExtAction ( <STR_LIT> , From , To , Action ) ; setLoadExtAction ( <STR_LIT> , From , To , Action ) ;


<s> } else return SDValue ( ) ; } if ( nextIndex != Vec . getValueType ( ) . getVectorNumElements ( ) || Vec . getValueType ( ) . getVectorElementType ( ) == VT . getVectorElementType ( ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDLoc dl ( N ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( DAG . getConstant ( <STR_LIT> , dl , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ) ; Ops . push_back ( Vec ) ; MVT widenType ; unsigned numElem = VT . getVectorNumElements ( ) ; EVT inputLaneType = Vec . getValueType ( ) . getVectorElementType ( ) ; switch ( inputLaneType . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : widenType = <STR_LIT> ( <STR_LIT> , numElem ) ; break ; case <STR_LIT> : widenType = <STR_LIT> ( <STR_LIT> , numElem ) ; break ; case <STR_LIT> : widenType = <STR_LIT> ( <STR_LIT> , numElem ) ; break ; default :


<s> static SDValue AddCombineBUILD_VECTORToVPADDL ( SDNode * N , SDValue N0 , SDValue N1 , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( DCI . isBeforeLegalize ( ) || ! Subtarget -> hasNEON ( ) || N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isInteger ( ) || VT . getVectorElementType ( ) == <STR_LIT> ) return SDValue ( ) ; if ( N0 -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Vec = N0 -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ; SDNode * V = Vec . getNode ( ) ; unsigned nextIndex = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = N0 -> getNumOperands ( ) ; i != e ; ++ i ) { if ( N0 -> getOperand ( i ) -> getOpcode ( ) == <STR_LIT> && N1 -> getOperand ( i ) -> getOpcode ( ) == <STR_LIT> ) { SDValue ExtVec0 = N0 -> getOperand ( i ) ; SDValue ExtVec1 = N1 -> getOperand ( i ) ; if ( V != ExtVec0 -> getOperand ( <NUM_LIT> ) . getNode ( ) || V != ExtVec1 -> getOperand ( <NUM_LIT> ) . getNode ( ) ) return SDValue ( ) ; ConstantSDNode * C0 = dyn_cast < ConstantSDNode > ( ExtVec0 -> getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * C1 = dyn_cast < ConstantSDNode > ( ExtVec1 -> getOperand ( <NUM_LIT> ) ) ; if ( ! C0 || ! C1 || C0 -> getZExtValue ( ) != nextIndex || C1 -> getZExtValue ( ) != nextIndex + <NUM_LIT> ) return SDValue ( ) ; nextIndex += <NUM_LIT> ; } else return SDValue ( ) ;


<s> if ( MULOp == SDValue ( ) ) MULOp = findMUL_LOHI ( AddeSubeOp1 ) ; else IsLeftOperandMUL = true ; if ( MULOp == SDValue ( ) ) return SDValue ( ) ; unsigned Opc = MULOp -> getOpcode ( ) ; unsigned FinalOpc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue * HiAddSub = nullptr ; SDValue * LoMul = nullptr ; SDValue * LowAddSub = nullptr ; if ( ( AddeSubeOp0 != MULOp . getValue ( <NUM_LIT> ) ) && ( AddeSubeOp1 != MULOp . getValue ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( IsLeftOperandMUL ) HiAddSub = & AddeSubeOp1 ; else HiAddSub = & AddeSubeOp0 ; if ( AddcSubcOp0 == MULOp . getValue ( <NUM_LIT> ) ) { LoMul = & AddcSubcOp0 ; LowAddSub = & AddcSubcOp1 ; } if ( AddcSubcOp1 == MULOp . getValue ( <NUM_LIT> ) ) { LoMul = & AddcSubcOp1 ; LowAddSub = & AddcSubcOp0 ; } if ( ! LoMul ) return SDValue ( ) ; if ( AddcSubcNode == HiAddSub -> getNode ( ) || AddcSubcNode -> isPredecessorOf ( HiAddSub -> getNode ( ) ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; if ( Subtarget -> hasV6Ops ( ) && Subtarget -> hasDSP ( ) && Subtarget -> useMulOps ( ) && FinalOpc == <STR_LIT> && ! AddeSubeNode -> hasAnyUseOfValue ( <NUM_LIT> ) && LowAddSub -> getNode ( ) -> getOpcode ( ) == <STR_LIT> && static_cast < ConstantSDNode * > ( LowAddSub -> getNode ( ) ) -> getZExtValue ( ) == <NUM_LIT> ) { Ops . push_back ( * HiAddSub ) ; if ( AddcSubcNode -> getOpcode ( ) == <STR_LIT> ) { FinalOpc = <STR_LIT> ; } else { FinalOpc = <STR_LIT> ; } SDValue NewNode = DAG . getNode ( FinalOpc , SDLoc ( AddcSubcNode ) , <STR_LIT> , Ops ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( AddeSubeNode , <NUM_LIT> ) , NewNode ) ; return SDValue ( AddeSubeNode , <NUM_LIT> ) ; } else if ( AddcSubcNode -> getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; Ops . push_back ( * LowAddSub ) ; Ops . push_back ( * HiAddSub ) ; SDValue MLALNode = DAG . getNode ( FinalOpc , SDLoc ( AddcSubcNode ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; SDValue HiMLALResult ( MLALNode . getNode ( ) , <NUM_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( AddeSubeNode , <NUM_LIT> ) , HiMLALResult ) ; SDValue LoMLALResult ( MLALNode . getNode ( ) , <NUM_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( AddcSubcNode , <NUM_LIT> ) , LoMLALResult ) ;


<s> SDValue Mul = AddcNode -> getOperand ( <NUM_LIT> ) ; SDValue Lo = AddcNode -> getOperand ( <NUM_LIT> ) ; if ( Mul . getOpcode ( ) != <STR_LIT> ) { Lo = AddcNode -> getOperand ( <NUM_LIT> ) ; Mul = AddcNode -> getOperand ( <NUM_LIT> ) ; if ( Mul . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; } SDValue SRA = AddeNode -> getOperand ( <NUM_LIT> ) ; SDValue Hi = AddeNode -> getOperand ( <NUM_LIT> ) ; if ( SRA . getOpcode ( ) != <STR_LIT> ) { SRA = AddeNode -> getOperand ( <NUM_LIT> ) ; Hi = AddeNode -> getOperand ( <NUM_LIT> ) ; if ( SRA . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; } if ( auto Const = dyn_cast < ConstantSDNode > ( SRA . getOperand ( <NUM_LIT> ) ) ) { if ( Const -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; } else return SDValue ( ) ; if ( SRA . getOperand ( <NUM_LIT> ) != Mul ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc dl ( AddcNode ) ; unsigned Opcode = <NUM_LIT> ; SDValue Op0 ; SDValue Op1 ; if ( isS16 ( Mul . getOperand ( <NUM_LIT> ) , DAG ) && isS16 ( Mul . getOperand ( <NUM_LIT> ) , DAG ) ) { Opcode = <STR_LIT> ; Op0 = Mul . getOperand ( <NUM_LIT> ) ; Op1 = Mul . getOperand ( <NUM_LIT> ) ; } else if ( isS16 ( Mul . getOperand ( <NUM_LIT> ) , DAG ) && isSRA16 ( Mul . getOperand ( <NUM_LIT> ) ) ) { Opcode = <STR_LIT> ; Op0 = Mul . getOperand ( <NUM_LIT> ) ; Op1 = Mul . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; } else if ( isSRA16 ( Mul . getOperand ( <NUM_LIT> ) ) && isS16 ( Mul . getOperand ( <NUM_LIT> ) , DAG ) ) { Opcode = <STR_LIT> ; Op0 = Mul . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Op1 = Mul . getOperand ( <NUM_LIT> ) ; } else if ( isSRA16 ( Mul . getOperand ( <NUM_LIT> ) ) && isSRA16 ( Mul . getOperand ( <NUM_LIT> ) ) ) { Opcode = <STR_LIT> ; Op0 = Mul -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Op1 = Mul -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; } if ( ! Op0 || ! Op1 ) return SDValue ( ) ; SDValue SMLAL = DAG . getNode ( Opcode , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Op0 , Op1 , Lo , Hi ) ; SDValue HiMLALResult ( SMLAL . getNode ( ) , <NUM_LIT> ) ; SDValue LoMLALResult ( SMLAL . getNode ( ) , <NUM_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( AddcNode , <NUM_LIT> ) , LoMLALResult ) ;

DAG . ReplaceAllUsesOfValueWith ( SDValue ( AddeNode , <NUM_LIT> ) , HiMLALResult ) ;


<s> } else { return AddCombineTo64bitMLAL ( AddeNode , DCI , Subtarget ) ; } if ( ! isNullConstant ( UmlalNode -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( ( isNullConstant ( AddeNode -> getOperand ( <NUM_LIT> ) ) && AddeNode -> getOperand ( <NUM_LIT> ) . getNode ( ) == UmlalNode ) || ( AddeNode -> getOperand ( <NUM_LIT> ) . getNode ( ) == UmlalNode && isNullConstant ( AddeNode -> getOperand ( <NUM_LIT> ) ) ) ) { SelectionDAG & DAG = DCI . DAG ; SDValue Ops [ ] = { UmlalNode -> getOperand ( <NUM_LIT> ) , UmlalNode -> getOperand ( <NUM_LIT> ) , UmlalNode -> getOperand ( <NUM_LIT> ) , AddHi } ; SDValue UMAAL = DAG . getNode ( <STR_LIT> , SDLoc ( AddcNode ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( AddeNode , <NUM_LIT> ) , SDValue ( UMAAL . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( AddcNode , <NUM_LIT> ) , SDValue ( UMAAL . getNode ( ) , <NUM_LIT> ) ) ; return SDValue ( AddeNode , <NUM_LIT> ) ;


<s> AddHi = AddcNode -> getOperand ( <NUM_LIT> ) ; } else if ( AddcNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { UmlalNode = AddcNode -> getOperand ( <NUM_LIT> ) . getNode ( ) ; AddHi = AddcNode -> getOperand ( <NUM_LIT> ) ; } else { return AddCombineTo64bitMLAL ( AddeNode , DCI , Subtarget ) ; } if ( ! isNullConstant ( UmlalNode -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( ( isNullConstant ( AddeNode -> getOperand ( <NUM_LIT> ) ) && AddeNode -> getOperand ( <NUM_LIT> ) . getNode ( ) == UmlalNode ) || ( AddeNode -> getOperand ( <NUM_LIT> ) . getNode ( ) == UmlalNode && isNullConstant ( AddeNode -> getOperand ( <NUM_LIT> ) ) ) ) { SelectionDAG & DAG = DCI . DAG ;

SDValue Ops [ ] = { UmlalNode -> getOperand ( <NUM_LIT> ) , UmlalNode -> getOperand ( <NUM_LIT> ) , UmlalNode -> getOperand ( <NUM_LIT> ) , AddHi } ;


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDLoc dl ( N ) ; SDNode * Unzip = N0 . getNode ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( DAG . getConstant ( <STR_LIT> , dl , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ) ;

Ops . push_back ( Unzip -> getOperand ( <NUM_LIT> ) ) ;


<s> SelectionDAG & DAG = DCI . DAG ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned Opcode ; if ( N0 . getOpcode ( ) == <STR_LIT> ) Opcode = <STR_LIT> ; else Opcode = <STR_LIT> ; Ops . push_back ( DAG . getConstant ( Opcode , dl , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ) ; EVT ElemTy = N00 . getValueType ( ) . getVectorElementType ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; EVT ConcatVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ElemTy , NumElts * <NUM_LIT> ) ;

SDValue Concat = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , ConcatVT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) ;


<s> void <ISA_LIT>TargetLowering :: addDRTypeForNEON ( MVT VT ) { addRegisterClass ( VT , & <STR_LIT> ) ;


<s> attachMEMCPYScratchRegs ( Subtarget , MI , Node ) ; return ; } const MCInstrDesc * MCID = & MI . getDesc ( ) ; unsigned NewOpc = convertAddSubFlagsOpcode ( MI . getOpcode ( ) ) ; unsigned ccOutIdx ; if ( NewOpc ) { const <ISA_LIT>BaseInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; MCID = & TII -> get ( NewOpc ) ; assert ( MCID -> getNumOperands ( ) == MI . getDesc ( ) . getNumOperands ( ) + <NUM_LIT> - MI . getDesc ( ) . getSize ( ) && <STR_LIT> <STR_LIT> ) ; MI . setDesc ( * MCID ) ; MI . addOperand ( MachineOperand :: CreateReg ( <NUM_LIT> , true ) ) ; if ( Subtarget -> isThumb1Only ( ) ) { for ( unsigned c = MCID -> getNumOperands ( ) - <NUM_LIT> ; c -- ; ) { MI . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; MI . RemoveOperand ( <NUM_LIT> ) ; } for ( unsigned i = MI . getNumOperands ( ) ; i -- ; ) { const MachineOperand & op = MI . getOperand ( i ) ; if ( op . isReg ( ) && op . isUse ( ) ) { int DefIdx = MCID -> getOperandConstraint ( i , MCOI :: TIED_TO ) ; if ( DefIdx != - <NUM_LIT> ) MI . tieOperands ( DefIdx , i ) ; } } MI . addOperand ( MachineOperand :: CreateImm ( <STR_LIT> ) ) ; MI . addOperand ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; ccOutIdx = <NUM_LIT> ; } else ccOutIdx = MCID -> getNumOperands ( ) - <NUM_LIT> ; } else ccOutIdx = MCID -> getNumOperands ( ) - <NUM_LIT> ; if ( ! MI . hasOptionalDef ( ) || ! MCID -> OpInfo [ ccOutIdx ] . isOptionalDef ( ) ) { assert ( ! NewOpc && <STR_LIT> ) ; return ; } bool definesCPSR = false ; bool deadCPSR = false ; for ( unsigned i = MCID -> getNumOperands ( ) , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == <STR_LIT> ) { definesCPSR = true ; if ( MO . isDead ( ) ) deadCPSR = true ; MI . RemoveOperand ( i ) ; break ; } } if ( ! definesCPSR ) { assert ( ! NewOpc && <STR_LIT> ) ; return ; } assert ( deadCPSR == ! Node -> hasAnyUseOfValue ( <NUM_LIT> ) && <STR_LIT> ) ; if ( deadCPSR ) {

assert ( ! MI . getOperand ( ccOutIdx ) . getReg ( ) && <STR_LIT> ) ;


<s> if ( Ty == <STR_LIT> || Ty == <STR_LIT> || Ty == <STR_LIT> ) { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } } if ( Ty == <STR_LIT> || Ty == <STR_LIT> ) { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || Subtarget -> isLittle ( ) ) ) { if ( Fast ) * Fast = true ; return true ; } } if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; if ( ( Ty == <STR_LIT> || Ty == <STR_LIT> || Ty == <STR_LIT> ) ) { if ( Fast ) * Fast = true ; return true ; } if ( ( Ty == <STR_LIT> || Ty == <STR_LIT> || Ty == <STR_LIT> ) && Alignment >= VT . getScalarSizeInBits ( ) / <NUM_LIT> ) { if ( Fast ) * Fast = true ;


<s> return Ext -> getType ( ) -> getScalarSizeInBits ( ) == <NUM_LIT> * Ext -> getOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarSizeInBits ( ) ; } ;

if ( ! match ( Ext1 , m_ZExtOrSExt ( m_Value ( ) ) ) || ! match ( Ext2 , m_ZExtOrSExt ( m_Value ( ) ) ) || ! areExtDoubled ( cast < Instruction > ( Ext1 ) ) || ! areExtDoubled ( cast < Instruction > ( Ext2 ) ) ) return false ;


<s> if ( isFloatingPointZero ( Op ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( Op ) , <STR_LIT> ) ; if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Op ) ) return DAG . getLoad ( <STR_LIT> , SDLoc ( Op ) , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , Ld -> getAlignment ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Op ) ) return DAG . getLoad ( <STR_LIT> , SDLoc ( Op ) , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , Ld -> getAlignment ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) ) ; llvm_unreachable ( <STR_LIT> ) ;


<s> const bool MinSize = ST . hasMinSize ( ) ; const bool HasDivide = ST . isThumb ( ) ? ST . hasDivideInThumbMode ( ) : ST . hasDivideIn<ISA_LIT>Mode ( ) ;

if ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . isVector ( ) ) return SDValue ( ) ;


<s> unsigned BitWidth = VectorTy -> getPrimitiveSizeInBits ( ) . getFixedSize ( ) ; if ( BitWidth == <NUM_LIT> || BitWidth == <NUM_LIT> ) { Cost = <NUM_LIT> ; return true ; } return false ;


<s> static bool canGuaranteeTCO ( CallingConv :: ID CC , bool GuaranteeTailCalls ) { return ( CC == CallingConv :: Fast && GuaranteeTailCalls ) || CC == CallingConv :: Tail || CC == CallingConv :: SwiftTail ;


<s> return isValidMVECond ( CC , N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . isFloatingPoint ( ) ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ;

return CCInfo . CheckReturn ( Outs , CCAssignFnForReturn ( CallConv , isVarArg ) ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ;

CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ;


<s> CCAssignFn * <ISA_LIT>TargetLowering :: CCAssignFnForCall ( CallingConv :: ID CC , bool isVarArg ) const { return CCAssignFnForNode ( CC , false , isVarArg ) ;


<s> default : report_fatal_error ( <STR_LIT> ) ; case CallingConv :: <ISA_LIT>_APCS : return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS ) ; case CallingConv :: <ISA_LIT>_AAPCS : return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; case CallingConv :: <ISA_LIT>_AAPCS_VFP : return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; case CallingConv :: Fast : return ( Return ? RetFastCC_<ISA_LIT>_APCS : FastCC_<ISA_LIT>_APCS ) ; case CallingConv :: GHC : return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS_GHC ) ; case CallingConv :: PreserveMost : return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ;


<s> return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS ) ; case CallingConv :: <ISA_LIT>_AAPCS : return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; case CallingConv :: <ISA_LIT>_AAPCS_VFP : return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ;


<s> CCAssignFn * <ISA_LIT>TargetLowering :: CCAssignFnForReturn ( CallingConv :: ID CC , bool isVarArg ) const { return CCAssignFnForNode ( CC , true , isVarArg ) ;


<s> if ( miI == BB -> end ( ) ) { for ( MachineBasicBlock :: succ_iterator sItr = BB -> succ_begin ( ) , sEnd = BB -> succ_end ( ) ; sItr != sEnd ; ++ sItr ) { MachineBasicBlock * succ = * sItr ; if ( succ -> isLiveIn ( <STR_LIT> ) ) return false ; }


<s> if ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) swpCmpOps = true ; if ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) { swpCmpOps = ! swpCmpOps ; swpVselOps = ! swpVselOps ; CondCode = CondCode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } if ( CC == <STR_LIT> ) { CondCode = <STR_LIT> ; swpVselOps = true ;


<s> if ( C2 < C3 ) { SDValue SHL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( C3 - C2 , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SHL , DAG . getConstant ( C3 , DL , <STR_LIT> ) ) ; } } if ( LeftShift && isMask_32 ( ~ C1 ) ) { uint32_t C3 = countTrailingZeros ( C1 ) ; if ( C2 < C3 ) { SDValue SHL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( C3 - C2 , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SHL , DAG . getConstant ( C3 , DL , <STR_LIT> ) ) ; } } if ( LeftShift && isShiftedMask_32 ( C1 ) ) { uint32_t Trailing = countTrailingZeros ( C1 ) ; uint32_t C3 = countLeadingZeros ( C1 ) ; if ( Trailing == C2 && C2 + C3 < <NUM_LIT> ) { SDValue SHL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( C2 + C3 , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SHL , DAG . getConstant ( C3 , DL , <STR_LIT> ) ) ; } } if ( ! LeftShift && isShiftedMask_32 ( C1 ) ) { uint32_t Leading = countLeadingZeros ( C1 ) ; uint32_t C3 = countTrailingZeros ( C1 ) ; if ( Leading == C2 && C2 + C3 < <NUM_LIT> ) { SDValue SHL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( C2 + C3 , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SHL , DAG . getConstant ( C3 , DL , <STR_LIT> ) ) ;


<s> if ( ! N1C ) return SDValue ( ) ; uint32_t C1 = ( uint32_t ) N1C -> getZExtValue ( ) ; if ( C1 == <NUM_LIT> || C1 == <NUM_LIT> ) return SDValue ( ) ; SDNode * N0 = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( ! N0 -> hasOneUse ( ) ) return SDValue ( ) ; if ( N0 -> getOpcode ( ) != <STR_LIT> && N0 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; bool LeftShift = N0 -> getOpcode ( ) == <STR_LIT> ; ConstantSDNode * N01C = dyn_cast < ConstantSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; if ( ! N01C ) return SDValue ( ) ; uint32_t C2 = ( uint32_t ) N01C -> getZExtValue ( ) ; if ( ! C2 || C2 >= <NUM_LIT> ) return SDValue ( ) ; if ( LeftShift ) C1 &= ( - <NUM_LIT> << C2 ) ; else C1 &= ( - <NUM_LIT> >> C2 ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; if ( ! LeftShift && isMask_32 ( C1 ) ) { uint32_t C3 = countLeadingZeros ( C1 ) ; if ( C2 < C3 ) { SDValue SHL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( C3 - C2 , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SHL , DAG . getConstant ( C3 , DL , <STR_LIT> ) ) ; } } if ( LeftShift && isMask_32 ( ~ C1 ) ) { uint32_t C3 = countTrailingZeros ( C1 ) ; if ( C2 < C3 ) { SDValue SHL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( C3 - C2 , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SHL , DAG . getConstant ( C3 , DL , <STR_LIT> ) ) ; } } if ( LeftShift && isShiftedMask_32 ( C1 ) ) { uint32_t Trailing = countTrailingZeros ( C1 ) ; uint32_t C3 = countLeadingZeros ( C1 ) ; if ( Trailing == C2 && C2 + C3 < <NUM_LIT> ) { SDValue SHL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( C2 + C3 , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SHL , DAG . getConstant ( C3 , DL , <STR_LIT> ) ) ; } } if ( ! LeftShift && isShiftedMask_32 ( C1 ) ) { uint32_t Leading = countLeadingZeros ( C1 ) ; uint32_t C3 = countTrailingZeros ( C1 ) ; if ( Leading == C2 && C2 + C3 < <NUM_LIT> ) {


<s> SDValue Addr = N -> getOperand ( AddrOpIdx ) ; SmallVector < BaseUpdateUser , <NUM_LIT> > BaseUpdates ; for ( SDNode :: use_iterator UI = Addr . getNode ( ) -> use_begin ( ) , UE = Addr . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; if ( UI . getUse ( ) . getResNo ( ) != Addr . getResNo ( ) || User -> getNumOperands ( ) != <NUM_LIT> ) continue ; SDValue Inc = User -> getOperand ( UI . getOperandNo ( ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; unsigned ConstInc = getPointerConstIncrement ( User -> getOpcode ( ) , Addr , Inc , DCI . DAG ) ; if ( ConstInc || User -> getOpcode ( ) == <STR_LIT> ) BaseUpdates . push_back ( { User , Inc , ConstInc } ) ; } SDValue Base ; SDValue CInc ; if ( findPointerConstIncrement ( Addr . getNode ( ) , & Base , & CInc ) ) { unsigned Offset = getPointerConstIncrement ( Addr -> getOpcode ( ) , Base , CInc , DCI . DAG ) ;

for ( SDNode :: use_iterator UI = Base -> use_begin ( ) , UE = Base -> use_end ( ) ;


<s> if ( N0 . getNode ( ) -> hasOneUse ( ) ) if ( SDValue Result = combineSelectAndUse ( N , N0 , N1 , DCI , AllOnes ) ) return Result ;

if ( N1 . getNode ( ) -> hasOneUse ( ) ) if ( SDValue Result = combineSelectAndUse ( N , N1 , N0 , DCI , AllOnes ) ) return Result ;


<s> auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; int Size = VA . getLocVT ( ) . getFixedSizeInBits ( ) / <NUM_LIT> ; int FI = MF . getFrameInfo ( ) . CreateFixedObject ( Size , Offset , true ) ; DstAddr = DAG . getFrameIndex ( FI , PtrVT ) ; DstInfo = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ; } else { SDValue PtrOff = DAG . getIntPtrConstant ( Offset , dl ) ; DstAddr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , PtrOff ) ; DstInfo = MachinePointerInfo :: getStack ( DAG . getMachineFunction ( ) , Offset ) ;


<s> if ( Known . isUnknown ( ) ) return ; KnownBits KnownRHS = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; Known = KnownBits :: commonBits ( Known , KnownRHS ) ; return ; } case <STR_LIT> : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : case <STR_LIT> : { EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } } case <STR_LIT> : { Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; ConstantSDNode * CI = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; const APInt & Mask = CI -> getAPIntValue ( ) ; Known . Zero &= Mask ; Known . One &= Mask ; return ; } case <STR_LIT> : case <STR_LIT> : { const SDValue & SrcSV = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = SrcSV . getValueType ( ) ; assert ( VecVT . isVector ( ) && <STR_LIT> ) ; const unsigned NumSrcElts = VecVT . getVectorNumElements ( ) ;

ConstantSDNode * Pos = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ;


<s> static SDValue ConvertCarryFlagToBooleanCarry ( SDValue Flags , EVT VT , SelectionDAG & DAG ) { SDLoc DL ( Flags ) ; return DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Flags ) ;


<s> SDValue RegClass = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg0 = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg1 = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , VLo , SubReg0 , VHi , SubReg1 } ; return SDValue ( DAG . getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ;


<s> SDLoc dl ( V . getNode ( ) ) ; SDValue VLo = DAG . getAnyExtOrTrunc ( V , dl , <STR_LIT> ) ; SDValue VHi = DAG . getAnyExtOrTrunc ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) , dl , <STR_LIT> ) ; bool isBigEndian = DAG . getDataLayout ( ) . isBigEndian ( ) ; if ( isBigEndian ) std :: swap ( VLo , VHi ) ; SDValue RegClass = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ;

SDValue SubReg0 = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ;


<s> void <ISA_LIT>TargetLowering :: emitAtomicCmpXchgNoStoreLLBalance ( IRBuilderBase & Builder ) const { if ( ! Subtarget -> hasV7Ops ( ) ) return ;

Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ;


<s> Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ;

Builder . CreateCall ( <STR_LIT> ( M , <STR_LIT> ) ) ;


<s> case AtomicOrdering :: AcquireRelease : if ( Subtarget -> preferISHSTBarriers ( ) ) return makeDMB ( Builder , <STR_LIT> ) ; else return makeDMB ( Builder , <STR_LIT> ) ; }


<s> if ( ! Inst -> hasAtomicStore ( ) ) return nullptr ; LLVM_FALLTHROUGH ; case AtomicOrdering :: Release : case AtomicOrdering :: AcquireRelease :

if ( Subtarget -> preferISHSTBarriers ( ) ) return makeDMB ( Builder , <STR_LIT> ) ;


<s> Function * Ldrex = <STR_LIT> ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldrex , Addr , <STR_LIT> ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Lo = Builder . CreateZExt ( Lo , ValueTy , <STR_LIT> ) ; Hi = Builder . CreateZExt ( Hi , ValueTy , <STR_LIT> ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValueTy , <NUM_LIT> ) ) , <STR_LIT> ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ;


<s> BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; case CodeModel :: Large : { MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; Register Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) . addExternalSymbol ( <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( gettBLXrOpcode ( * MBB -> getParent ( ) ) ) ) . add ( predOps ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ;


<s> case CodeModel :: Tiny : llvm_unreachable ( <STR_LIT> ) ; case CodeModel :: Small : case CodeModel :: Medium : case CodeModel :: Kernel : BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; case CodeModel :: Large : { MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; Register Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) . addExternalSymbol ( <STR_LIT> ) ;

BuildMI ( * MBB , MI , DL , TII . get ( gettBLXrOpcode ( * MBB -> getParent ( ) ) ) ) . add ( predOps ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ;


<s> const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; MachineBasicBlock * ContBB = MF -> CreateMachineBasicBlock ( ) ; MF -> insert ( ++ MBB -> getIterator ( ) , ContBB ) ; ContBB -> splice ( ContBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; ContBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MBB -> addSuccessor ( ContBB ) ; MachineBasicBlock * TrapBB = MF -> CreateMachineBasicBlock ( ) ; BuildMI ( TrapBB , DL , TII -> get ( <STR_LIT> ) ) ; MF -> push_back ( TrapBB ) ; MBB -> addSuccessor ( TrapBB ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( TrapBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> MF -> push_back ( TrapBB ) ; MBB -> addSuccessor ( TrapBB ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( TrapBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; MI . eraseFromParent ( ) ; return ContBB ;


<s> BuildMI ( * BB , Pos , dl , TII -> get ( LdOpc ) , Data ) . addReg ( AddrOut , RegState :: Define ) . addReg ( AddrIn ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( IsThumb1 ) { BuildMI ( * BB , Pos , dl , TII -> get ( LdOpc ) , Data ) . addReg ( AddrIn ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( * BB , Pos , dl , TII -> get ( <STR_LIT> ) , AddrOut ) . add ( t1CondCodeOp ( ) ) . addReg ( AddrIn ) . addImm ( LdSize ) . add ( predOps ( <STR_LIT> ) ) ;


<s> assert ( LdOpc != <NUM_LIT> && <STR_LIT> ) ; if ( LdSize >= <NUM_LIT> ) { BuildMI ( * BB , Pos , dl , TII -> get ( LdOpc ) , Data ) . addReg ( AddrOut , RegState :: Define ) . addReg ( AddrIn ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( IsThumb1 ) { BuildMI ( * BB , Pos , dl , TII -> get ( LdOpc ) , Data ) . addReg ( AddrIn ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( * BB , Pos , dl , TII -> get ( <STR_LIT> ) , AddrOut ) . add ( t1CondCodeOp ( ) ) . addReg ( AddrIn ) . addImm ( LdSize ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( IsThumb2 ) { BuildMI ( * BB , Pos , dl , TII -> get ( LdOpc ) , Data ) . addReg ( AddrOut , RegState :: Define ) . addReg ( AddrIn ) . addImm ( LdSize ) . add ( predOps ( <STR_LIT> ) ) ; } else {

BuildMI ( * BB , Pos , dl , TII -> get ( LdOpc ) , Data ) . addReg ( AddrOut , RegState :: Define ) . addReg ( AddrIn ) . addReg ( <NUM_LIT> ) . addImm ( LdSize ) . add ( predOps ( <STR_LIT> ) ) ;


<s> BuildMI ( * BB , Pos , dl , TII -> get ( <STR_LIT> ) , AddrOut ) . add ( t1CondCodeOp ( ) ) . addReg ( AddrIn ) . addImm ( StSize ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( IsThumb2 ) { BuildMI ( * BB , Pos , dl , TII -> get ( StOpc ) , AddrOut ) . addReg ( Data ) . addReg ( AddrIn ) . addImm ( StSize ) . add ( predOps ( <STR_LIT> ) ) ; } else {

BuildMI ( * BB , Pos , dl , TII -> get ( StOpc ) , AddrOut ) . addReg ( Data ) . addReg ( AddrIn ) . addReg ( <NUM_LIT> ) . addImm ( StSize ) . add ( predOps ( <STR_LIT> ) ) ;


<s> bool IsRelease = isReleaseOrStronger ( Ord ) ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Function * Strex = <STR_LIT> ( M , Int ) ; Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , <STR_LIT> ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , <NUM_LIT> ) , Int32Ty , <STR_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ;

Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ;


<s> emitPostLd ( BB , MI , TII , dl , <NUM_LIT> , scratch , srcIn , srcOut , IsThumb1 , IsThumb2 ) ; emitPostSt ( BB , MI , TII , dl , <NUM_LIT> , scratch , destIn , destOut , IsThumb1 , IsThumb2 ) ; srcIn = srcOut ; destIn = destOut ; } MI . eraseFromParent ( ) ; return BB ; } MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; Register varEnd = MRI . createVirtualRegister ( TRC ) ; if ( Subtarget -> useMovt ( ) ) { unsigned Vtmp = varEnd ; if ( ( LoopSize & <NUM_LIT> ) != <NUM_LIT> ) Vtmp = MRI . createVirtualRegister ( TRC ) ; BuildMI ( BB , dl , TII -> get ( IsThumb ? <STR_LIT> : <STR_LIT> ) , Vtmp ) . addImm ( LoopSize & <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; if ( ( LoopSize & <NUM_LIT> ) != <NUM_LIT> ) BuildMI ( BB , dl , TII -> get ( IsThumb ? <STR_LIT> : <STR_LIT> ) , varEnd ) . addReg ( Vtmp ) . addImm ( LoopSize >> <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else { MachineConstantPool * ConstantPool = MF -> getConstantPool ( ) ; Type * Int32Ty = Type :: getInt32Ty ( MF -> getFunction ( ) . getContext ( ) ) ; const Constant * C = ConstantInt :: get ( Int32Ty , LoopSize ) ; Align Alignment = MF -> getDataLayout ( ) . getPrefTypeAlign ( Int32Ty ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , Alignment ) ; MachineMemOperand * CPMMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( * MF ) , MachineMemOperand :: MOLoad , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; if ( IsThumb ) BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( varEnd , RegState :: Define ) . addConstantPoolIndex ( Idx ) . add ( predOps ( <STR_LIT> ) ) . addMemOperand ( CPMMO ) ; else BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( varEnd , RegState :: Define ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . addMemOperand ( CPMMO ) ; } BB -> addSuccessor ( loopMBB ) ; MachineBasicBlock * entryBB = BB ; BB = loopMBB ; Register varLoop = MRI . createVirtualRegister ( TRC ) ; Register varPhi = MRI . createVirtualRegister ( TRC ) ;

Register srcLoop = MRI . createVirtualRegister ( TRC ) ;


<s> switch ( Ord ) { case AtomicOrdering :: NotAtomic : case AtomicOrdering :: Unordered : llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : case AtomicOrdering :: Release : return nullptr ;


<s> SDValue <ISA_LIT>TargetLowering :: ExpandBITCAST ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) const { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDLoc dl ( N ) ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = Op . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; if ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && ( DstVT == <STR_LIT> || DstVT == <STR_LIT> ) ) return MoveToHPR ( SDLoc ( N ) , DAG , <STR_LIT> , DstVT . getSimpleVT ( ) , DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Op ) ) ; if ( ( DstVT == <STR_LIT> || DstVT == <STR_LIT> ) && ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , DstVT , MoveFromHPR ( SDLoc ( N ) , DAG , <STR_LIT> , SrcVT . getSimpleVT ( ) , Op ) ) ; if ( ! ( SrcVT == <STR_LIT> || DstVT == <STR_LIT> ) ) return SDValue ( ) ; if ( SrcVT == <STR_LIT> && TLI . isTypeLegal ( DstVT ) ) { if ( SDValue Val = CombineVMOVDRRCandidateWithVecOp ( N , DAG ) ) return Val ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;

return DAG . getNode ( <STR_LIT> , dl , DstVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ) ;


<s> SDLoc dl ( Op ) ; SDValue DBZCHK = WinDBZCheckDenominator ( DAG , Op . getNode ( ) , DAG . getEntryNode ( ) ) ; SDValue Result = LowerWindowsDIVLibCall ( Op , DAG , Signed , DBZCHK ) ; SDValue Lower = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result ) ; SDValue Upper = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , dl , TLI . getPointerTy ( DL ) ) ) ;

Upper = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Upper ) ;


<s> EVT PtrType = Ptr . getValueType ( ) ; unsigned NewAlign = MinAlign ( Ld -> getAlignment ( ) , <NUM_LIT> ) ; SDValue NewPtr = DAG . getNode ( <STR_LIT> , dl , PtrType , Ptr , DAG . getConstant ( <NUM_LIT> , dl , PtrType ) ) ; RetVal2 = DAG . getLoad ( <STR_LIT> , dl , Ld -> getChain ( ) , NewPtr , Ld -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , NewAlign , Ld -> getMemOperand ( ) -> getFlags ( ) ) ; return ; }


<s> } if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Op ) ) { SDValue Ptr = Ld -> getBasePtr ( ) ; RetVal1 = DAG . getLoad ( <STR_LIT> , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> getAlignment ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) ) ; EVT PtrType = Ptr . getValueType ( ) ; unsigned NewAlign = MinAlign ( Ld -> getAlignment ( ) , <NUM_LIT> ) ; SDValue NewPtr = DAG . getNode ( <STR_LIT> , dl , PtrType , Ptr , DAG . getConstant ( <NUM_LIT> , dl , PtrType ) ) ;

RetVal2 = DAG . getLoad ( <STR_LIT> , dl , Ld -> getChain ( ) , NewPtr , Ld -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , NewAlign , Ld -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> AsmStr = std :: string ( AsmPieces [ <NUM_LIT> ] ) ; AsmPieces . clear ( ) ; SplitString ( AsmStr , AsmPieces , <STR_LIT> ) ; if ( AsmPieces . size ( ) == <NUM_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && IA -> getConstraintString ( ) . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) { IntegerType * Ty = dyn_cast < IntegerType > ( CI -> getType ( ) ) ; if ( Ty && Ty -> getBitWidth ( ) == <NUM_LIT> ) return IntrinsicLowering :: LowerToByteSwap ( CI ) ; } break ; }


<s> AsmStr = std :: string ( AsmPieces [ <NUM_LIT> ] ) ; AsmPieces . clear ( ) ; SplitString ( AsmStr , AsmPieces , <STR_LIT> ) ; if ( AsmPieces . size ( ) == <NUM_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && IA -> getConstraintString ( ) . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) { IntegerType * Ty = dyn_cast < IntegerType > ( CI -> getType ( ) ) ;

if ( Ty && Ty -> getBitWidth ( ) == <NUM_LIT> ) return IntrinsicLowering :: LowerToByteSwap ( CI ) ;


<s> MF . getFrameInfo ( ) . computeMaxCallFrameSize ( MF ) ;

TargetLoweringBase :: finalizeLowering ( MF ) ;


<s> void <ISA_LIT>TargetLowering :: finalizeLowering ( MachineFunction & MF ) const {

MF . getFrameInfo ( ) . computeMaxCallFrameSize ( MF ) ;


<s> APInt ToMask , FromMask ; SDValue From = ParseBFI ( N , ToMask , FromMask ) ; SDValue To = N -> getOperand ( <NUM_LIT> ) ; SDValue V = To ; if ( V . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; APInt NewToMask , NewFromMask ;

SDValue NewFrom = ParseBFI ( V . getNode ( ) , NewToMask , NewFromMask ) ;


<s> case <STR_LIT> : { if ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) { * Ptr = N -> getOperand ( <NUM_LIT> ) ; * CInc = N -> getOperand ( <NUM_LIT> ) ; return true ; } return false ;


<s> ArrayRef < int > OpMask = Op0 -> getMask ( ) ; for ( int i = <NUM_LIT> , e = NMask . size ( ) ; i != e ; i ++ ) { if ( NMask [ i ] > <NUM_LIT> && OpMask [ NMask [ i ] ] > <NUM_LIT> && OpMask [ NMask [ i ] ] != i ) return SDValue ( ) ; }

return DAG . getNode ( Op . getOpcode ( ) , SDLoc ( Op ) , Op . getValueType ( ) , Op0 -> getOperand ( <NUM_LIT> ) , Op1 -> getOperand ( <NUM_LIT> ) ) ;


<s> break ; default : return SDValue ( ) ; } ShuffleVectorSDNode * Op0 = dyn_cast < ShuffleVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; ShuffleVectorSDNode * Op1 = dyn_cast < ShuffleVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! Op0 || ! Op1 || ! Op0 -> getOperand ( <NUM_LIT> ) . isUndef ( ) || ! Op1 -> getOperand ( <NUM_LIT> ) . isUndef ( ) || Op0 -> getMask ( ) != Op1 -> getMask ( ) || Op0 -> getOperand ( <NUM_LIT> ) . getValueType ( ) != VT ) return SDValue ( ) ; ArrayRef < int > NMask = N -> getMask ( ) ; ArrayRef < int > OpMask = Op0 -> getMask ( ) ; for ( int i = <NUM_LIT> , e = NMask . size ( ) ; i != e ; i ++ ) { if ( NMask [ i ] > <NUM_LIT> && OpMask [ NMask [ i ] ] > <NUM_LIT> && OpMask [ NMask [ i ] ] != i ) return SDValue ( ) ; } return DAG . getNode ( Op . getOpcode ( ) , SDLoc ( Op ) , Op . getValueType ( ) , Op0 -> getOperand ( <NUM_LIT> ) , Op1 -> getOperand ( <NUM_LIT> ) ) ;


if ( getEffectiveCallingConv ( CallConv , isVarArg ) != CallingConv :: <ISA_LIT>_AAPCS_VFP ) return false ;


<s> BuildMI ( TpEntry , Dl , TII -> get ( <STR_LIT> ) , LsrDestReg ) . addUse ( AddDestReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . addReg ( <NUM_LIT> ) ; Register TotalIterationsReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpEntry , Dl , TII -> get ( <STR_LIT> ) , TotalIterationsReg ) . addUse ( LsrDestReg , RegState :: Kill ) ; BuildMI ( TpEntry , Dl , TII -> get ( <STR_LIT> ) ) . addUse ( TotalIterationsReg ) . addMBB ( TpExit ) ; BuildMI ( TpEntry , Dl , TII -> get ( <STR_LIT> ) ) . addMBB ( TpLoopBody ) . add ( predOps ( <STR_LIT> ) ) ; return TotalIterationsReg ;


<s> if ( ! ArgTy -> isVectorTy ( ) ) return ABITypeAlign ; return std :: min ( ABITypeAlign , DL . getStackAlignment ( ) ) ;


<s> unsigned ShiftBits = countLeadingZeros ( Mask ) ; if ( RHSV && ( RHSV > <NUM_LIT> || ( RHSV << ShiftBits ) <= <NUM_LIT> ) ) { SDValue ShiftAmt = DAG . getConstant ( ShiftBits , dl , <STR_LIT> ) ; LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS . getOperand ( <NUM_LIT> ) , ShiftAmt ) ; RHS = DAG . getConstant ( RHSV << ShiftBits , dl , <STR_LIT> ) ; } } } if ( Subtarget -> isThumb1Only ( ) && LHS -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( RHS ) && cast < ConstantSDNode > ( RHS ) -> getZExtValue ( ) == <NUM_LIT> && CC == <STR_LIT> && isa < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) < <NUM_LIT> ) { unsigned ShiftAmt = cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) + <NUM_LIT> ; SDValue Shift = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , LHS . getOperand ( <NUM_LIT> ) , DAG . getConstant ( ShiftAmt , dl , <STR_LIT> ) ) ; SDValue Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , Shift . getValue ( <NUM_LIT> ) , SDValue ( ) ) ; <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; return Chain . getValue ( <NUM_LIT> ) ; } <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; if ( isNullConstant ( RHS ) ) { switch ( CondCode ) {


<s> case <STR_LIT> : <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS ) ; OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; break ; case <STR_LIT> : <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS ) ; OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; break ; case <STR_LIT> : <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( Op . getValueType ( ) , Op . getValueType ( ) ) , LHS , RHS ) ; OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value . getValue ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Value = Value . getValue ( <NUM_LIT> ) ; break ; case <STR_LIT> : <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ;


<s> Value = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS ) ; OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; break ; case <STR_LIT> : <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS ) ; OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; break ; case <STR_LIT> : <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( Op . getValueType ( ) , Op . getValueType ( ) ) , LHS , RHS ) ; OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value . getValue ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Value = Value . getValue ( <NUM_LIT> ) ; break ; case <STR_LIT> : <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( Op . getValueType ( ) , Op . getValueType ( ) ) , LHS , RHS ) ;

OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value . getValue ( <NUM_LIT> ) , DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Value . getValue ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ) ;


<s> SDValue TrueLow = TrueVal . getValue ( <NUM_LIT> ) ; SDValue TrueHigh = TrueVal . getValue ( <NUM_LIT> ) ; SDValue FalseLow = FalseVal . getValue ( <NUM_LIT> ) ; SDValue FalseHigh = FalseVal . getValue ( <NUM_LIT> ) ; SDValue Low = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FalseLow , TrueLow , <ISA_LIT>cc , CCR , Cmp ) ; SDValue High = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FalseHigh , TrueHigh , <ISA_LIT>cc , CCR , duplicateCmp ( Cmp , DAG ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Low , High ) ; } else {

return DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp ) ;


<s> unsigned S = Constraint . size ( ) ; if ( S == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'l' : return C_RegisterClass ; case 'w' : return C_RegisterClass ; case 'h' : return C_RegisterClass ; case 'x' : return C_RegisterClass ; case 't' : return C_RegisterClass ; case 'j' : return C_Immediate ; case 'Q' : return C_Memory ; }


<s> case CallingConv :: Swift : case CallingConv :: SwiftTail : return isVarArg ? CallingConv :: <ISA_LIT>_AAPCS : CallingConv :: <ISA_LIT>_AAPCS_VFP ; case CallingConv :: C : case CallingConv :: Tail : if ( ! Subtarget -> isAAPCS_ABI ( ) ) return CallingConv :: <ISA_LIT>_APCS ; else if ( Subtarget -> hasVFP2Base ( ) && ! Subtarget -> isThumb1Only ( ) && getTargetMachine ( ) . Options . FloatABIType == FloatABI :: Hard && ! isVarArg ) return CallingConv :: <ISA_LIT>_AAPCS_VFP ; else return CallingConv :: <ISA_LIT>_AAPCS ;


<s> return Subtarget -> useSjLjEH ( ) ? Register ( ) : <STR_LIT> ;


<s> Register <ISA_LIT>TargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { return Subtarget -> useSjLjEH ( ) ? Register ( ) : <STR_LIT> ;


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( <NUM_LIT> , NextVA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Root , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ; } else { Reg = MF . addLiveIn ( NextVA . getLocReg ( ) , RC ) ; ArgValue2 = DAG . getCopyFromReg ( Root , dl , Reg , <STR_LIT> ) ; }

if ( ! Subtarget -> isLittle ( ) ) std :: swap ( ArgValue , ArgValue2 ) ;


<s> if ( Subtarget -> hasNEON ( ) ) return <NUM_LIT> ;

if ( Subtarget -> hasMVEIntegerOps ( ) ) return MVEMaxSupportedInterleaveFactor ;


<s> unsigned <ISA_LIT>TargetLowering :: getMaxSupportedInterleaveFactor ( ) const { if ( Subtarget -> hasNEON ( ) ) return <NUM_LIT> ;


<s> isInc = false ; Offset = DAG . getConstant ( - RHSC , SDLoc ( Ptr ) , RHS -> getValueType ( <NUM_LIT> ) ) ; return true ; } else if ( RHSC > <NUM_LIT> && RHSC < Limit * Scale && RHSC % Scale == <NUM_LIT> ) { isInc = Ptr -> getOpcode ( ) == <STR_LIT> ; Offset = DAG . getConstant ( RHSC , SDLoc ( Ptr ) , RHS -> getValueType ( <NUM_LIT> ) ) ; return true ; } return false ; } ; Base = Ptr -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { if ( Alignment >= <NUM_LIT> && IsInRange ( RHSC , <NUM_LIT> , <NUM_LIT> ) ) return true ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { if ( IsInRange ( RHSC , <NUM_LIT> , <NUM_LIT> ) ) return true ; } else if ( Alignment >= <NUM_LIT> && ( CanChangeType || VT == <STR_LIT> || VT == <STR_LIT> ) && IsInRange ( RHSC , <NUM_LIT> , <NUM_LIT> ) ) return true ; else if ( Alignment >= <NUM_LIT> && ( CanChangeType || VT == <STR_LIT> || VT == <STR_LIT> ) && IsInRange ( RHSC , <NUM_LIT> , <NUM_LIT> ) ) return true ; else if ( ( CanChangeType || VT == <STR_LIT> ) && IsInRange ( RHSC , <NUM_LIT> , <NUM_LIT> ) ) return true ; return false ;


<s> return ( DL . getTypeSizeInBits ( VecTy ) + <NUM_LIT> ) / <NUM_LIT> ;


<s> unsigned <ISA_LIT>TargetLowering :: getNumInterleavedAccesses ( VectorType * VecTy , const DataLayout & DL ) const {

return ( DL . getTypeSizeInBits ( VecTy ) + <NUM_LIT> ) / <NUM_LIT> ;


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { if ( ( Op . isMemcpy ( ) || Op . isZeroMemset ( ) ) && Subtarget -> hasNEON ( ) && ! FuncAttributes . hasFnAttr ( Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Op . size ( ) >= <NUM_LIT> && ( Op . isAligned ( Align ( <NUM_LIT> ) ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , Align ( <NUM_LIT> ) , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) {


<s> bool Fast ; if ( Op . size ( ) >= <NUM_LIT> && ( Op . isAligned ( Align ( <NUM_LIT> ) ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , Align ( <NUM_LIT> ) , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return <STR_LIT> ; } else if ( Op . size ( ) >= <NUM_LIT> && ( Op . isAligned ( Align ( <NUM_LIT> ) ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , Align ( <NUM_LIT> ) , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) {


<s> switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return CInc -> getZExtValue ( ) ; case <STR_LIT> : { if ( DAG . haveNoCommonBitsSet ( Ptr , Inc ) ) { return CInc -> getZExtValue ( ) ; } return <NUM_LIT> ; } default :


<s> if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; Alignment = LD -> getAlign ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; isNonExt = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; Alignment = ST -> getAlign ( ) ; isNonExt = ! ST -> isTruncatingStore ( ) ; } else if ( MaskedLoadSDNode * LD = dyn_cast < MaskedLoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; Alignment = LD -> getAlign ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; isNonExt = LD -> getExtensionType ( ) == <STR_LIT> ; IsMasked = true ; } else if ( MaskedStoreSDNode * ST = dyn_cast < MaskedStoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; Alignment = ST -> getAlign ( ) ; isNonExt = ! ST -> isTruncatingStore ( ) ; IsMasked = true ; } else return false ; if ( Subtarget -> isThumb1Only ( ) ) { assert ( Op -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; if ( Op -> getOpcode ( ) != <STR_LIT> || ! isNonExt ) return false ; auto * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHS || RHS -> getZExtValue ( ) != <NUM_LIT> ) return false ; if ( Alignment < Align ( <NUM_LIT> ) ) return false ; Offset = Op -> getOperand ( <NUM_LIT> ) ; Base = Op -> getOperand ( <NUM_LIT> ) ; AM = <STR_LIT> ; return true ; } bool isInc ; bool isLegal = false ; if ( VT . isVector ( ) ) isLegal = Subtarget -> hasMVEIntegerOps ( ) && getMVEIndexedAddressParts ( Op , VT , Alignment , isSEXTLoad , IsMasked , Subtarget -> isLittle ( ) , Base , Offset , isInc , DAG ) ; else { if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ;

else isLegal = get<ISA_LIT>IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ;