<s> Res = LowerADDSUBSAT ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ; break ; case <STR_LIT> : ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ; return ; case <STR_LIT> : case <STR_LIT> : assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; return ExpandDIV_Windows ( SDValue ( N , <NUM_LIT> ) , DAG , N -> getOpcode ( ) == <STR_LIT> , Results ) ; case <STR_LIT> : ReplaceCMP_SWAP_64Results ( N , Results , DAG ) ; return ; case <STR_LIT> : return ReplaceLongIntrinsic ( N , Results , DAG ) ; case <STR_LIT> : lowerABS ( N , Results , DAG ) ; return ; case <STR_LIT> : LowerLOAD ( N , Results , DAG ) ; break ; case <STR_LIT> : Res = LowerTruncate ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerVectorExtend ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> :

Res = LowerFP_TO_INT_SAT ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ;


<s> SDValue Cycles32 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cycles32 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ;

Results . push_back ( Cycles32 . getValue ( <NUM_LIT> ) ) ;


<s> if ( ! Const ) return SDValue ( ) ; if ( Const -> isZero ( ) ) Imm = <NUM_LIT> ; else if ( Const -> isOne ( ) ) Imm = <NUM_LIT> ; else return SDValue ( ) ; CC = cast < CondCodeSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> get ( ) ; return SearchLoopIntrinsic ( N -> getOperand ( <NUM_LIT> ) , CC , Imm , Negate ) ; } case <STR_LIT> : { unsigned IntOp = cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( IntOp != <STR_LIT> && IntOp != <STR_LIT> ) return SDValue ( ) ; return N ; }


<s> if ( Mask . size ( ) == Elements * <NUM_LIT> ) return Index / Elements ; return Mask [ Index ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ;


<s> setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ;


<s> Register NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addMemOperand ( CPMMO ) . add ( predOps ( <STR_LIT> ) ) ; Register NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; Register NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( NewVReg2 , RegState :: Kill ) . addImm ( PCLabelId ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( NewVReg3 , RegState :: Kill ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( FIMMOSt ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( isThumb ) { Register NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addMemOperand ( CPMMO ) . add ( predOps ( <STR_LIT> ) ) ; Register NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( PCLabelId ) ; Register NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( <STR_LIT> , RegState :: Define ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; Register NewVReg4 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg4 ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( NewVReg2 , RegState :: Kill ) . addReg ( NewVReg3 , RegState :: Kill ) . add ( predOps ( <STR_LIT> ) ) ;

Register NewVReg5 = MRI -> createVirtualRegister ( TRC ) ;


<s> Type * <ISA_LIT>TargetLowering :: shouldConvertSplatType ( ShuffleVectorInst * SVI ) const { if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return nullptr ; Type * SVIType = SVI -> getType ( ) ; Type * ScalarType = SVIType -> getScalarType ( ) ;

if ( ScalarType -> isFloatTy ( ) ) return Type :: getInt32Ty ( SVIType -> getContext ( ) ) ;


<s> bool HasAtomicCmpXchg = ! Subtarget -> isThumb ( ) || Subtarget -> hasV8MBaselineOps ( ) ; if ( getTargetMachine ( ) . getOptLevel ( ) != <NUM_LIT> && HasAtomicCmpXchg && Size <= ( Subtarget -> isMClass ( ) ? <NUM_LIT> : <NUM_LIT> ) ) return AtomicExpansionKind :: LLSC ; return AtomicExpansionKind :: None ;


<s> if ( getTargetMachine ( ) . getOptLevel ( ) == CodeGenOpt :: None ) return AtomicExpansionKind :: CmpXChg ; unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ;

bool hasAtomicRMW = ! Subtarget -> isThumb ( ) || Subtarget -> hasV8MBaselineOps ( ) ;


<s> bool <ISA_LIT>TargetLowering :: shouldExpandShift ( SelectionDAG & DAG , SDNode * N ) const {

return ! Subtarget -> hasMinSize ( ) || Subtarget -> isTargetWindows ( ) ;


<s> bool <ISA_LIT>TargetLowering :: shouldExpandShift ( SelectionDAG & DAG , SDNode * N ) const { return ! Subtarget -> hasMinSize ( ) || Subtarget -> isTargetWindows ( ) ;


<s> if ( ! Subtarget -> isThumb1Only ( ) ) return true ;

if ( Level == BeforeLegalizeTypes ) return true ;


<s> bool <ISA_LIT>TargetLowering :: shouldFoldConstantShiftPairToMask ( const SDNode * N , CombineLevel Level ) const {

if ( ! Subtarget -> isThumb1Only ( ) ) return true ;


<s> bool <ISA_LIT>TargetLowering :: shouldInsertFencesForAtomic ( const Instruction * I ) const {


<s> } } if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; auto IsFMSMul = [ & ] ( Instruction * I ) { if ( ! I -> hasOneUse ( ) ) return false ; auto * Sub = cast < Instruction > ( * I -> users ( ) . begin ( ) ) ; return Sub -> getOpcode ( ) == Instruction :: FSub && Sub -> getOperand ( <NUM_LIT> ) == I ; } ; auto IsFMS = [ & ] ( Instruction * I ) { if ( match ( I -> getOperand ( <NUM_LIT> ) , m_FNeg ( m_Value ( ) ) ) || match ( I -> getOperand ( <NUM_LIT> ) , m_FNeg ( m_Value ( ) ) ) ) return true ; return false ; } ; auto IsSinker = [ & ] ( Instruction * I , int Operand ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Add : case Instruction :: Mul : case Instruction :: FAdd : case Instruction :: ICmp : case Instruction :: FCmp : return true ; case Instruction :: FMul : return ! IsFMSMul ( I ) ; case Instruction :: Sub : case Instruction :: FSub : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return Operand == <NUM_LIT> ; case Instruction :: Call : if ( auto * II = dyn_cast < IntrinsicInst > ( I ) ) { switch ( II -> getIntrinsicID ( ) ) { case <STR_LIT> :


<s> ShuffleSourceInfo ( SDValue Vec ) : Vec ( Vec ) , ShuffleVec ( Vec ) {


<s> if ( Op . getResNo ( ) == <NUM_LIT> && ! Op -> hasAnyUseOfValue ( <NUM_LIT> ) && isa < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ) { unsigned ShAmt = Op -> getConstantOperandVal ( <NUM_LIT> ) ;

if ( ShAmt < <NUM_LIT> && OriginalDemandedBits . isSubsetOf ( APInt :: getAllOnes ( <NUM_LIT> ) << ( <NUM_LIT> - ShAmt ) ) ) return TLO . CombineTo ( Op , TLO . DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , TLO . DAG . getConstant ( <NUM_LIT> - ShAmt , SDLoc ( Op ) , <STR_LIT> ) ) ) ;


<s> unsigned ShAmt = Op -> getConstantOperandVal ( <NUM_LIT> ) ; if ( ShAmt < <NUM_LIT> && OriginalDemandedBits . isSubsetOf ( APInt :: getAllOnes ( <NUM_LIT> ) << ( <NUM_LIT> - ShAmt ) ) ) return TLO . CombineTo ( Op , TLO . DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , TLO . DAG . getConstant ( <NUM_LIT> - ShAmt , SDLoc ( Op ) , <STR_LIT> ) ) ) ; } break ; } }

return TargetLowering :: SimplifyDemandedBitsForTargetNode ( Op , OriginalDemandedBits , OriginalDemandedElts , Known , TLO , Depth ) ;


<s> SDValue extLoad = DAG . getNode ( Opcode , SDLoc ( newLoad ) , LD -> getValueType ( <NUM_LIT> ) , newLoad ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , extLoad ) ; return newLoad ; } if ( N -> getOpcode ( ) == <STR_LIT> ) { SDNode * BVN = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; assert ( BVN -> getOpcode ( ) == <STR_LIT> && BVN -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; unsigned LowElt = DAG . getDataLayout ( ) . isBigEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; return DAG . getBuildVector ( <STR_LIT> , SDLoc ( N ) , { BVN -> getOperand ( LowElt ) , BVN -> getOperand ( LowElt + <NUM_LIT> ) } ) ; } assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned EltSize = VT . getScalarSizeInBits ( ) / <NUM_LIT> ;

unsigned NumElts = VT . getVectorNumElements ( ) ;


<s> static SDValue SkipLoadExtensionForVMULL ( LoadSDNode * LD , SelectionDAG & DAG ) { EVT ExtendedTy = getExtensionTo64Bits ( LD -> getMemoryVT ( ) ) ; if ( ExtendedTy == LD -> getMemoryVT ( ) ) return DAG . getLoad ( LD -> getMemoryVT ( ) , SDLoc ( LD ) , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getPointerInfo ( ) , LD -> getAlignment ( ) , LD -> getMemOperand ( ) -> getFlags ( ) ) ; return DAG . getExtLoad ( LD -> getExtensionType ( ) , SDLoc ( LD ) , ExtendedTy , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getPointerInfo ( ) , LD -> getMemoryVT ( ) , LD -> getAlignment ( ) , LD -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> EVT ExtendedTy = getExtensionTo64Bits ( LD -> getMemoryVT ( ) ) ;

if ( ExtendedTy == LD -> getMemoryVT ( ) ) return DAG . getLoad ( LD -> getMemoryVT ( ) , SDLoc ( LD ) , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getPointerInfo ( ) , LD -> getAlignment ( ) , LD -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> EVT ValueVT = Val . getValueType ( ) ; if ( IsABIRegCopy && ( ValueVT == <STR_LIT> || ValueVT == <STR_LIT> ) && PartVT == <STR_LIT> ) { unsigned ValueBits = ValueVT . getSizeInBits ( ) ; unsigned PartBits = PartVT . getSizeInBits ( ) ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ( ValueBits ) , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ( PartBits ) , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL , PartVT , Val ) ; Parts [ <NUM_LIT> ] = Val ; return true ; } return false ;


<s> if ( InRegsParamRecordIdx < CCInfo . getInRegsParamsCount ( ) ) { CCInfo . getInRegsParamInfo ( InRegsParamRecordIdx , RBegin , REnd ) ; } else { unsigned RBeginIdx = CCInfo . getFirstUnallocated ( GPRArgRegs ) ; RBegin = RBeginIdx == <NUM_LIT> ? ( unsigned ) <STR_LIT> : GPRArgRegs [ RBeginIdx ] ; REnd = <STR_LIT> ; } if ( REnd != RBegin ) ArgOffset = - <NUM_LIT> * ( <STR_LIT> - RBegin ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; int FrameIndex = MFI . CreateFixedObject ( ArgSize , ArgOffset , false ) ; SDValue FIN = DAG . getFrameIndex ( FrameIndex , PtrVT ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ;

const TargetRegisterClass * RC = AFI -> isThumb1OnlyFunction ( ) ? & <STR_LIT> : & <STR_LIT> ;


<s> isLoadOp = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; hasAlignment = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; hasAlignment = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; hasAlignment = false ; break ; } } else { isLaneOp = true ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = false ; isLoadOp = false ; break ; } } EVT VecTy ; if ( isLoadOp ) { VecTy = N -> getValueType ( <NUM_LIT> ) ; } else if ( Target . isIntrinsic ) { VecTy = N -> getOperand ( Target . AddrOpIdx + <NUM_LIT> ) . getValueType ( ) ; } else { assert ( Target . isStore && <STR_LIT> ) ; VecTy = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; } bool isVLDDUPOp = NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ; unsigned NumBytes = NumVecs * VecTy . getSizeInBits ( ) / <NUM_LIT> ; if ( isLaneOp || isVLDDUPOp ) NumBytes /= VecTy . getVectorNumElements ( ) ; if ( NumBytes >= <NUM_LIT> * <NUM_LIT> && User . ConstInc != NumBytes ) { return false ; } if ( SimpleConstIncOnly && User . ConstInc != NumBytes ) return false ; EVT AlignedVecTy = VecTy ; unsigned Alignment = MemN -> getAlignment ( ) ; if ( isa < LSBaseSDNode > ( N ) ) { if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; if ( Alignment < VecTy . getScalarSizeInBits ( ) / <NUM_LIT> ) { MVT EltTy = <STR_LIT> ( Alignment * <NUM_LIT> ) ; assert ( NumVecs == <NUM_LIT> && <STR_LIT> ) ; assert ( ! isLaneOp && <STR_LIT> ) ; unsigned NumElts = NumBytes / ( EltTy . getSizeInBits ( ) / <NUM_LIT> ) ; AlignedVecTy = <STR_LIT> ( EltTy , NumElts ) ; } Alignment = <NUM_LIT> ; } EVT Tys [ <NUM_LIT> ] ;

unsigned NumResultVecs = ( isLoadOp ? NumVecs : <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return false ; } ; auto DistrubuteAddAddVecReduce = [ & ] ( SDValue N0 , SDValue N1 ) { if ( VT == <STR_LIT> && N1 . getOpcode ( ) == <STR_LIT> && ! IsVecReduce ( N0 ) && IsVecReduce ( N1 . getOperand ( <NUM_LIT> ) ) && IsVecReduce ( N1 . getOperand ( <NUM_LIT> ) ) && ! isa < ConstantSDNode > ( N0 ) ) { SDValue Add0 = DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Add0 , N1 . getOperand ( <NUM_LIT> ) ) ; } if ( VT == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> && N1 . getOpcode ( ) == <STR_LIT> ) { unsigned N0RedOp = <NUM_LIT> ; if ( ! IsVecReduce ( N0 . getOperand ( N0RedOp ) ) ) { N0RedOp = <NUM_LIT> ; if ( ! IsVecReduce ( N0 . getOperand ( N0RedOp ) ) ) return SDValue ( ) ; } unsigned N1RedOp = <NUM_LIT> ; if ( ! IsVecReduce ( N1 . getOperand ( N1RedOp ) ) ) N1RedOp = <NUM_LIT> ; if ( ! IsVecReduce ( N1 . getOperand ( N1RedOp ) ) ) return SDValue ( ) ; SDValue Add0 = DAG . getNode ( <STR_LIT> , dl , VT , N0 . getOperand ( <NUM_LIT> - N0RedOp ) , N1 . getOperand ( <NUM_LIT> - N1RedOp ) ) ; SDValue Add1 = DAG . getNode ( <STR_LIT> , dl , VT , Add0 , N0 . getOperand ( N0RedOp ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Add1 , N1 . getOperand ( N1RedOp ) ) ; } return SDValue ( ) ; } ; if ( SDValue R = DistrubuteAddAddVecReduce ( N0 , N1 ) ) return R ; if ( SDValue R = DistrubuteAddAddVecReduce ( N1 , N0 ) ) return R ; auto DistrubuteVecReduceLoad = [ & ] ( SDValue N0 , SDValue N1 , bool IsForward ) { auto IsKnownOrderedLoad = [ & ] ( SDValue N0 , SDValue N1 ) { if ( N0 . getOpcode ( ) == <STR_LIT> ) N0 = N0 . getOperand ( <NUM_LIT> ) ; if ( N1 . getOpcode ( ) == <STR_LIT> ) N1 = N1 . getOperand ( <NUM_LIT> ) ; LoadSDNode * Load0 = dyn_cast < LoadSDNode > ( N0 ) ; LoadSDNode * Load1 = dyn_cast < LoadSDNode > ( N1 ) ; if ( ! Load0 || ! Load1 || Load0 -> getChain ( ) != Load1 -> getChain ( ) || ! Load0 -> isSimple ( ) || ! Load1 -> isSimple ( ) || Load0 -> isIndexed ( ) || Load1 -> isIndexed ( ) ) return <NUM_LIT> ; auto BaseLocDecomp0 = BaseIndexOffset :: match ( Load0 , DAG ) ;

auto BaseLocDecomp1 = BaseIndexOffset :: match ( Load1 , DAG ) ;


<s> int FrameIndex = StoreByValRegs ( CCInfo , DAG , dl , Chain , nullptr , CCInfo . getInRegsParamsCount ( ) , CCInfo . getNextStackOffset ( ) , std :: max ( <NUM_LIT> , TotalArgRegsSaveSize ) ) ;

AFI -> setVarArgsFrameIndex ( FrameIndex ) ;


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , InChain , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ) ;


<s> if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , InChain , Op ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , InChain , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ) ;


<s> void <ISA_LIT>TargetLowering :: addTypeForNEON ( MVT VT , MVT PromotedLdStVT , MVT PromotedBitwiseVT ) { if ( VT != PromotedLdStVT ) { setOperationAction ( <STR_LIT> , VT , Promote ) ; AddPromotedToType ( <STR_LIT> , VT , PromotedLdStVT ) ; setOperationAction ( <STR_LIT> , VT , Promote ) ; AddPromotedToType ( <STR_LIT> , VT , PromotedLdStVT ) ; } MVT ElemTy = VT . getVectorElementType ( ) ; if ( ElemTy != <STR_LIT> ) setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; if ( ElemTy == <STR_LIT> ) { setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } else { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; } setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ;


<s> if ( ! VT . isSimple ( ) ) return false ; bool AllowsUnaligned = Subtarget -> allowsUnalignedMem ( ) ; auto Ty = VT . getSimpleVT ( ) . SimpleTy ; if ( Ty == <STR_LIT> || Ty == <STR_LIT> || Ty == <STR_LIT> ) { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } } if ( Ty == <STR_LIT> || Ty == <STR_LIT> ) { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || Subtarget -> isLittle ( ) ) ) { if ( Fast ) * Fast = true ; return true ; } } if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; if ( ( Ty == <STR_LIT> || Ty == <STR_LIT> || Ty == <STR_LIT> ) ) {


<s> for ( auto * U : V -> users ( ) ) Worklist . push_back ( U ) ; while ( ! Worklist . empty ( ) ) { auto * U = Worklist . pop_back_val ( ) ; if ( isa < ConstantExpr > ( U ) ) { for ( auto * UU : U -> users ( ) ) Worklist . push_back ( UU ) ; continue ; } auto * I = dyn_cast < Instruction > ( U ) ;

if ( ! I || I -> getParent ( ) -> getParent ( ) != F ) return false ;


<s> switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = false ; isLoadOp = false ; break ; } } EVT VecTy ; if ( isLoadOp ) { VecTy = N -> getValueType ( <NUM_LIT> ) ; } else if ( isIntrinsic ) { VecTy = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) . getValueType ( ) ; } else { assert ( isStore && <STR_LIT> ) ; VecTy = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; } unsigned NumBytes = NumVecs * VecTy . getSizeInBits ( ) / <NUM_LIT> ; if ( isLaneOp ) NumBytes /= VecTy . getVectorNumElements ( ) ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ; if ( NumBytes >= <NUM_LIT> * <NUM_LIT> && ( ! CInc || CInc -> getZExtValue ( ) != NumBytes ) ) { continue ; } EVT AlignedVecTy = VecTy ; unsigned Alignment = MemN -> getAlignment ( ) ; if ( isa < LSBaseSDNode > ( N ) ) { if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; if ( Alignment < VecTy . getScalarSizeInBits ( ) / <NUM_LIT> ) { MVT EltTy = <STR_LIT> ( Alignment * <NUM_LIT> ) ; assert ( NumVecs == <NUM_LIT> && <STR_LIT> ) ; assert ( ! isLaneOp && <STR_LIT> ) ; unsigned NumElts = NumBytes / ( EltTy . getSizeInBits ( ) / <NUM_LIT> ) ; AlignedVecTy = <STR_LIT> ( EltTy , NumElts ) ; } Alignment = <NUM_LIT> ; } EVT Tys [ <NUM_LIT> ] ; unsigned NumResultVecs = ( isLoadOp ? NumVecs : <NUM_LIT> ) ; unsigned n ; for ( n = <NUM_LIT> ; n < NumResultVecs ; ++ n ) Tys [ n ] = AlignedVecTy ; Tys [ n ++ ] = <STR_LIT> ; Tys [ n ] = <STR_LIT> ; SDVTList SDTys = DAG . getVTList ( makeArrayRef ( Tys , NumResultVecs + <NUM_LIT> ) ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand ( AddrOpIdx ) ) ; Ops . push_back ( Inc ) ; if ( StoreSDNode * StN = dyn_cast < StoreSDNode > ( N ) ) { Ops . push_back ( StN -> getValue ( ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : { EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } } case <STR_LIT> : { Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; ConstantSDNode * CI = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; const APInt & Mask = CI -> getAPIntValue ( ) ; Known . Zero &= Mask ; Known . One &= Mask ; return ; } case <STR_LIT> : case <STR_LIT> : { const SDValue & SrcSV = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = SrcSV . getValueType ( ) ; assert ( VecVT . isVector ( ) && <STR_LIT> ) ; const unsigned NumSrcElts = VecVT . getVectorNumElements ( ) ; ConstantSDNode * Pos = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; assert ( Pos -> getAPIntValue ( ) . ult ( NumSrcElts ) && <STR_LIT> ) ; unsigned Idx = Pos -> getZExtValue ( ) ; APInt DemandedElt = APInt :: getOneBitSet ( NumSrcElts , Idx ) ; Known = DAG . computeKnownBits ( SrcSV , DemandedElt , Depth + <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; const unsigned DstSz = VT . getScalarSizeInBits ( ) ; const unsigned SrcSz = VecVT . getVectorElementType ( ) . getSizeInBits ( ) ; ( void ) SrcSz ; assert ( SrcSz == Known . getBitWidth ( ) ) ; assert ( DstSz > SrcSz ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) Known = Known . sext ( DstSz ) ; else { Known = Known . zext ( DstSz , true ) ; }

assert ( DstSz == Known . getBitWidth ( ) ) ;


<s> Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } } case <STR_LIT> : { Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; ConstantSDNode * CI = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; const APInt & Mask = CI -> getAPIntValue ( ) ; Known . Zero &= Mask ; Known . One &= Mask ; return ; } case <STR_LIT> : case <STR_LIT> : { const SDValue & SrcSV = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = SrcSV . getValueType ( ) ; assert ( VecVT . isVector ( ) && <STR_LIT> ) ; const unsigned NumSrcElts = VecVT . getVectorNumElements ( ) ; ConstantSDNode * Pos = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; assert ( Pos -> getAPIntValue ( ) . ult ( NumSrcElts ) && <STR_LIT> ) ; unsigned Idx = Pos -> getZExtValue ( ) ; APInt DemandedElt = APInt :: getOneBitSet ( NumSrcElts , Idx ) ; Known = DAG . computeKnownBits ( SrcSV , DemandedElt , Depth + <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ;

const unsigned DstSz = VT . getScalarSizeInBits ( ) ;


<s> Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Builder . CreateCall ( <STR_LIT> ( M , <STR_LIT> ) ) ;


<s> void <ISA_LIT>TargetLowering :: emitAtomicCmpXchgNoStoreLLBalance ( IRBuilder < > & Builder ) const { if ( ! Subtarget -> hasV7Ops ( ) ) return ;

Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ;


<s> return nullptr ; case AtomicOrdering :: SequentiallyConsistent : if ( ! Inst -> hasAtomicStore ( ) ) return nullptr ; LLVM_FALLTHROUGH ; case AtomicOrdering :: Release : case AtomicOrdering :: AcquireRelease : if ( Subtarget -> preferISHSTBarriers ( ) ) return makeDMB ( Builder , <STR_LIT> ) ; else return makeDMB ( Builder , <STR_LIT> ) ; } llvm_unreachable ( <STR_LIT> ) ;


<s> bool IsAcquire = isAcquireOrStronger ( Ord ) ; if ( ValTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { <STR_LIT> Int = IsAcquire ? <STR_LIT> : <STR_LIT> ; Function * Ldrex = <STR_LIT> ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldrex , Addr , <STR_LIT> ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Lo = Builder . CreateZExt ( Lo , ValTy , <STR_LIT> ) ; Hi = Builder . CreateZExt ( Hi , ValTy , <STR_LIT> ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , <NUM_LIT> ) ) , <STR_LIT> ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; <STR_LIT> Int = IsAcquire ? <STR_LIT> : <STR_LIT> ; Function * Ldrex = <STR_LIT> ( M , Int , Tys ) ;

return Builder . CreateTruncOrBitCast ( Builder . CreateCall ( Ldrex , Addr ) , cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ) ;


<s> Value * Lo = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Lo = Builder . CreateZExt ( Lo , ValTy , <STR_LIT> ) ; Hi = Builder . CreateZExt ( Hi , ValTy , <STR_LIT> ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , <NUM_LIT> ) ) , <STR_LIT> ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; <STR_LIT> Int = IsAcquire ? <STR_LIT> : <STR_LIT> ;

Function * Ldrex = <STR_LIT> ( M , Int , Tys ) ;


<s> assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; assert ( Subtarget -> isThumb2 ( ) && <STR_LIT> ) ; switch ( TM . getCodeModel ( ) ) { case CodeModel :: Tiny : llvm_unreachable ( <STR_LIT> ) ; case CodeModel :: Small : case CodeModel :: Medium : case CodeModel :: Kernel : BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; case CodeModel :: Large : { MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; Register Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) . addExternalSymbol ( <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; }


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitLowered__chkstk ( MachineInstr & MI , MachineBasicBlock * MBB ) const { const TargetMachine & TM = getTargetMachine ( ) ; const TargetInstrInfo & TII = * Subtarget -> getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; assert ( Subtarget -> isThumb2 ( ) && <STR_LIT> ) ; switch ( TM . getCodeModel ( ) ) { case CodeModel :: Tiny : llvm_unreachable ( <STR_LIT> ) ; case CodeModel :: Small : case CodeModel :: Medium : case CodeModel :: Kernel : BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; case CodeModel :: Large : { MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; Register Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) . addExternalSymbol ( <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; } } BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlags ( MachineInstr :: FrameSetup ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; MI . eraseFromParent ( ) ; return MBB ;


<s> Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , <NUM_LIT> ) , Int32Ty , <STR_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Strex , { Lo , Hi , Addr } ) ; } <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Type * Tys [ ] = { Addr -> getType ( ) } ;

Function * Strex = <STR_LIT> ( M , Int , Tys ) ;


<s> <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Function * Strex = <STR_LIT> ( M , Int ) ; Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , <STR_LIT> ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , <NUM_LIT> ) , Int32Ty , <STR_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Strex , { Lo , Hi , Addr } ) ; } <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ;

Type * Tys [ ] = { Addr -> getType ( ) } ;


<s> Register srcLoop = MRI . createVirtualRegister ( TRC ) ; Register srcPhi = MRI . createVirtualRegister ( TRC ) ; Register destLoop = MRI . createVirtualRegister ( TRC ) ; Register destPhi = MRI . createVirtualRegister ( TRC ) ; BuildMI ( * BB , BB -> begin ( ) , dl , TII -> get ( <STR_LIT> ) , varPhi ) . addReg ( varLoop ) . addMBB ( loopMBB ) . addReg ( varEnd ) . addMBB ( entryBB ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , srcPhi ) . addReg ( srcLoop ) . addMBB ( loopMBB ) . addReg ( src ) . addMBB ( entryBB ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , destPhi ) . addReg ( destLoop ) . addMBB ( loopMBB ) . addReg ( dest ) . addMBB ( entryBB ) ; Register scratch = MRI . createVirtualRegister ( IsNeon ? VecTRC : TRC ) ; emitPostLd ( BB , BB -> end ( ) , TII , dl , UnitSize , scratch , srcPhi , srcLoop , IsThumb1 , IsThumb2 ) ; emitPostSt ( BB , BB -> end ( ) , TII , dl , UnitSize , scratch , destPhi , destLoop , IsThumb1 , IsThumb2 ) ; if ( IsThumb1 ) { BuildMI ( * BB , BB -> end ( ) , dl , TII -> get ( <STR_LIT> ) , varLoop ) . add ( t1CondCodeOp ( ) ) . addReg ( varPhi ) . addImm ( UnitSize ) . add ( predOps ( <STR_LIT> ) ) ; } else { MachineInstrBuilder MIB = BuildMI ( * BB , BB -> end ( ) , dl , TII -> get ( IsThumb2 ? <STR_LIT> : <STR_LIT> ) , varLoop ) ; MIB . addReg ( varPhi ) . addImm ( UnitSize ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; MIB -> getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MIB -> getOperand ( <NUM_LIT> ) . setIsDef ( true ) ; } BuildMI ( * BB , BB -> end ( ) , dl , TII -> get ( IsThumb1 ? <STR_LIT> : IsThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( loopMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor ( loopMBB ) ; BB -> addSuccessor ( exitMBB ) ; BB = exitMBB ; auto StartOfExit = exitMBB -> begin ( ) ; unsigned srcIn = srcLoop ; unsigned destIn = destLoop ; for ( unsigned i = <NUM_LIT> ; i < BytesLeft ; i ++ ) { Register srcOut = MRI . createVirtualRegister ( TRC ) ; Register destOut = MRI . createVirtualRegister ( TRC ) ; Register scratch = MRI . createVirtualRegister ( TRC ) ;

emitPostLd ( BB , StartOfExit , TII , dl , <NUM_LIT> , scratch , srcIn , srcOut , IsThumb1 , IsThumb2 ) ;


<s> case AtomicOrdering :: Release : return nullptr ; case AtomicOrdering :: Acquire : case AtomicOrdering :: AcquireRelease : case AtomicOrdering :: SequentiallyConsistent : return makeDMB ( Builder , <STR_LIT> ) ; } llvm_unreachable ( <STR_LIT> ) ;


<s> switch ( Ord ) { case AtomicOrdering :: NotAtomic : case AtomicOrdering :: Unordered : llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : case AtomicOrdering :: Release :


<s> if ( Op . getOpcode ( ) != <STR_LIT> || Op . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; auto Move = N -> use_begin ( ) ; if ( Move -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ; SDValue Copy = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , Ops ) ; DAG . ReplaceAllUsesWith ( * Move , & Copy ) ; return Copy ; } if ( SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) { if ( ! HasFullFP16 ) return SDValue ( ) ; if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return SDValue ( ) ; } if ( SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) { if ( ! HasFullFP16 ) return SDValue ( ) ; auto ZeroExtend = N -> use_begin ( ) ; if ( N -> use_size ( ) != <NUM_LIT> || ZeroExtend -> getOpcode ( ) != <STR_LIT> || ZeroExtend -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; auto Copy = ZeroExtend -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == <STR_LIT> && Copy -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> ) {

SDValue Cvt = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , Op ) ;


<s> SDValue Result = LowerWindowsDIVLibCall ( Op , DAG , Signed , DBZCHK ) ; SDValue Lower = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result ) ; SDValue Upper = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , dl , TLI . getPointerTy ( DL ) ) ) ; Upper = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Upper ) ;


<s> switch ( OpNum ) { default : llvm_unreachable ( <STR_LIT> ) ; case OP_VREV : if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; case OP_VDUP0 : case OP_VDUP1 : case OP_VDUP2 : case OP_VDUP3 : return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS , DAG . getConstant ( OpNum - OP_VDUP0 , dl , <STR_LIT> ) ) ; case OP_VEXT1 : case OP_VEXT2 : case OP_VEXT3 : return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS , OpRHS , DAG . getConstant ( OpNum - OP_VEXT1 + <NUM_LIT> , dl , <STR_LIT> ) ) ;


<s> const Align ABITypeAlign ( DL . getABITypeAlignment ( ArgTy ) ) ; if ( ! ArgTy -> isVectorTy ( ) ) return ABITypeAlign ; return std :: min ( ABITypeAlign , DL . getStackAlignment ( ) ) ;


<s> case CallingConv :: C : if ( ! Subtarget -> isAAPCS_ABI ( ) ) return CallingConv :: <ISA_LIT>_APCS ; else if ( Subtarget -> hasVFP2Base ( ) && ! Subtarget -> isThumb1Only ( ) && getTargetMachine ( ) . Options . FloatABIType == FloatABI :: Hard && ! isVarArg ) return CallingConv :: <ISA_LIT>_AAPCS_VFP ; else return CallingConv :: <ISA_LIT>_AAPCS ; case CallingConv :: Fast : case CallingConv :: CXX_FAST_TLS : if ( ! Subtarget -> isAAPCS_ABI ( ) ) { if ( Subtarget -> hasVFP2Base ( ) && ! Subtarget -> isThumb1Only ( ) && ! isVarArg ) return CallingConv :: Fast ; return CallingConv :: <ISA_LIT>_APCS ; } else if ( Subtarget -> hasVFP2Base ( ) && ! Subtarget -> isThumb1Only ( ) && ! isVarArg ) return CallingConv :: <ISA_LIT>_AAPCS_VFP ; else return CallingConv :: <ISA_LIT>_AAPCS ;


<s> Offset = DAG . getConstant ( RHSC , SDLoc ( Ptr ) , RHS -> getValueType ( <NUM_LIT> ) ) ; return true ; } return false ; } ; Base = Ptr -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { if ( Align >= <NUM_LIT> && IsInRange ( RHSC , <NUM_LIT> , <NUM_LIT> ) ) return true ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { if ( IsInRange ( RHSC , <NUM_LIT> , <NUM_LIT> ) ) return true ; } else if ( Align >= <NUM_LIT> && ( CanChangeType || VT == <STR_LIT> || VT == <STR_LIT> ) && IsInRange ( RHSC , <NUM_LIT> , <NUM_LIT> ) ) return true ; else if ( Align >= <NUM_LIT> && ( CanChangeType || VT == <STR_LIT> || VT == <STR_LIT> ) && IsInRange ( RHSC , <NUM_LIT> , <NUM_LIT> ) ) return true ; else if ( ( CanChangeType || VT == <STR_LIT> ) && IsInRange ( RHSC , <NUM_LIT> , <NUM_LIT> ) ) return true ; return false ;


<s> if ( Ptr -> getOpcode ( ) != <STR_LIT> && Ptr -> getOpcode ( ) != <STR_LIT> ) return false ; if ( ! isa < ConstantSDNode > ( Ptr -> getOperand ( <NUM_LIT> ) ) ) return false ; bool CanChangeType = isLE && ! IsMasked ; ConstantSDNode * RHS = cast < ConstantSDNode > ( Ptr -> getOperand ( <NUM_LIT> ) ) ; int RHSC = ( int ) RHS -> getZExtValue ( ) ; auto IsInRange = [ & ] ( int RHSC , int Limit , int Scale ) { if ( RHSC < <NUM_LIT> && RHSC > - Limit * Scale && RHSC % Scale == <NUM_LIT> ) { assert ( Ptr -> getOpcode ( ) == <STR_LIT> ) ; isInc = false ; Offset = DAG . getConstant ( - RHSC , SDLoc ( Ptr ) , RHS -> getValueType ( <NUM_LIT> ) ) ; return true ; } else if ( RHSC > <NUM_LIT> && RHSC < Limit * Scale && RHSC % Scale == <NUM_LIT> ) {

isInc = Ptr -> getOpcode ( ) == <STR_LIT> ;


<s> bool Fast ; if ( Size >= <NUM_LIT> && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return <STR_LIT> ; } else if ( Size >= <NUM_LIT> && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return <STR_LIT> ; }


<s> VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; Align = ST -> getAlignment ( ) ; isNonExt = ! ST -> isTruncatingStore ( ) ; } else if ( MaskedLoadSDNode * LD = dyn_cast < MaskedLoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; Align = LD -> getAlignment ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; isNonExt = LD -> getExtensionType ( ) == <STR_LIT> ; IsMasked = true ; } else if ( MaskedStoreSDNode * ST = dyn_cast < MaskedStoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; Align = ST -> getAlignment ( ) ; isNonExt = ! ST -> isTruncatingStore ( ) ; IsMasked = true ; } else return false ; if ( Subtarget -> isThumb1Only ( ) ) { assert ( Op -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; if ( Op -> getOpcode ( ) != <STR_LIT> || ! isNonExt ) return false ; auto * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHS || RHS -> getZExtValue ( ) != <NUM_LIT> ) return false ; Offset = Op -> getOperand ( <NUM_LIT> ) ; Base = Op -> getOperand ( <NUM_LIT> ) ; AM = <STR_LIT> ; return true ; } bool isInc ; bool isLegal = false ; if ( VT . isVector ( ) ) isLegal = Subtarget -> hasMVEIntegerOps ( ) && getMVEIndexedAddressParts ( Op , VT , Align , isSEXTLoad , IsMasked , Subtarget -> isLittle ( ) , Base , Offset , isInc , DAG ) ; else { if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = get<ISA_LIT>IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; } if ( ! isLegal ) return false ; if ( Ptr != Base ) { if ( Ptr == Offset && Op -> getOpcode ( ) == <STR_LIT> && ! Subtarget -> isThumb2 ( ) ) std :: swap ( Base , Offset ) ; if ( Ptr != Base ) return false ;


<s> if ( VT == <STR_LIT> ) return & <STR_LIT> ; if ( VT == <STR_LIT> ) return & <STR_LIT> ; } return TargetLowering :: getRegClassFor ( VT ) ;


<s> break ; case 'r' : if ( Subtarget -> isThumb1Only ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; case 'w' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'x' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 't' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; } break ; case <NUM_LIT> : if ( Constraint [ <NUM_LIT> ] == 'T' ) {


<s> Register Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> Register <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , EVT VT , const MachineFunction & MF ) const { Register Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> if ( Subtarget -> hasFPAO ( ) ) return AM . Scale < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT> ; } return - <NUM_LIT> ;


<s> if ( Subtarget -> hasMVEIntegerOps ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) return <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) ) ; return VT . changeVectorElementTypeToInteger ( ) ;


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( DL ) ;

if ( Subtarget -> hasMVEIntegerOps ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) return <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : { auto & DL = I . getCalledFunction ( ) -> getParent ( ) -> getDataLayout ( ) ; PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = MaybeAlign ( DL . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : case <STR_LIT> : { auto & DL = I . getCalledFunction ( ) -> getParent ( ) -> getDataLayout ( ) ; PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = MaybeAlign ( DL . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ) ; Info . flags = MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ;


<s> assert ( Subtarget -> hasFP64 ( ) || RHS . getValueType ( ) != <STR_LIT> ) ; SDValue Cmp ;

if ( ! isFloatingPointZero ( RHS ) ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ;


<s> if ( ! isFloatingPointZero ( RHS ) ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ;

else Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ;


<s> if ( ! Reg ) return ; unsigned Excess = <NUM_LIT> * ( <STR_LIT> - Reg ) ; const unsigned NSAAOffset = State -> getNextStackOffset ( ) ; if ( NSAAOffset != <NUM_LIT> && Size > Excess ) { while ( State -> AllocateReg ( GPRArgRegs ) ) ; return ; } unsigned ByValRegBegin = Reg ; unsigned ByValRegEnd = std :: min < unsigned > ( Reg + Size / <NUM_LIT> , <STR_LIT> ) ; State -> addInRegsParamInfo ( ByValRegBegin , ByValRegEnd ) ;

for ( unsigned i = Reg + <NUM_LIT> ; i != ByValRegEnd ; ++ i ) State -> AllocateReg ( GPRArgRegs ) ;


<s> for ( unsigned i = <NUM_LIT> ; i < Waste ; ++ i ) Reg = State -> AllocateReg ( GPRArgRegs ) ; if ( ! Reg ) return ; unsigned Excess = <NUM_LIT> * ( <STR_LIT> - Reg ) ; const unsigned NSAAOffset = State -> getNextStackOffset ( ) ; if ( NSAAOffset != <NUM_LIT> && Size > Excess ) { while ( State -> AllocateReg ( GPRArgRegs ) ) ; return ; } unsigned ByValRegBegin = Reg ; unsigned ByValRegEnd = std :: min < unsigned > ( Reg + Size / <NUM_LIT> , <STR_LIT> ) ; State -> addInRegsParamInfo ( ByValRegBegin , ByValRegEnd ) ; for ( unsigned i = Reg + <NUM_LIT> ; i != ByValRegEnd ; ++ i ) State -> AllocateReg ( GPRArgRegs ) ; Size = std :: max < int > ( Size - Excess , <NUM_LIT> ) ;


<s> void <ISA_LIT>TargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( ! Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) ) return TargetLowering :: insertSSPDeclarations ( M ) ;

M . getOrInsertGlobal ( <STR_LIT> , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ;


<s> void <ISA_LIT>TargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( ! Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) ) return TargetLowering :: insertSSPDeclarations ( M ) ; M . getOrInsertGlobal ( <STR_LIT> , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; FunctionCallee SecurityCheckCookie = M . getOrInsertFunction ( <STR_LIT> , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; if ( Function * F = dyn_cast < Function > ( SecurityCheckCookie . getCallee ( ) ) ) F -> addAttribute ( <NUM_LIT> , Attribute :: AttrKind :: InReg ) ;


<s> OtherOp = N1 ; return true ; } return false ; } case <STR_LIT> : if ( AllOnes ) return false ; LLVM_FALLTHROUGH ; case <STR_LIT> : { SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; CC = N -> getOperand ( <NUM_LIT> ) ; if ( CC . getValueType ( ) != <STR_LIT> || CC . getOpcode ( ) != <STR_LIT> ) return false ; Invert = ! AllOnes ; if ( AllOnes ) OtherOp = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; else if ( N -> getOpcode ( ) == <STR_LIT> ) OtherOp = DAG . getConstant ( <NUM_LIT> , dl , VT ) ;

else OtherOp = DAG . getConstant ( APInt :: getAllOnesValue ( VT . getSizeInBits ( ) ) , dl , VT ) ;


<s> const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , realArgIdx = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i , ++ realArgIdx ) { CCValAssign & VA = ArgLocs [ i ] ; EVT RegVT = VA . getLocVT ( ) ; SDValue Arg = OutVals [ realArgIdx ] ; <STR_LIT> Flags = Outs [ realArgIdx ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( VA . needsCustom ( ) ) { if ( ! VA . isRegLoc ( ) ) return false ; if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; if ( RegVT == <STR_LIT> ) { if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; } } else if ( ! VA . isRegLoc ( ) ) { if ( ! MatchingStackOffset ( Arg , VA . getLocMemOffset ( ) , Flags , MFI , MRI , TII ) ) return false ; } } }

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , realArgIdx = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i , ++ realArgIdx ) { CCValAssign & VA = ArgLocs [ i ] ; EVT RegVT = VA . getLocVT ( ) ; SDValue Arg = OutVals [ realArgIdx ] ; <STR_LIT> Flags = Outs [ realArgIdx ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( VA . needsCustom ( ) ) { if ( ! VA . isRegLoc ( ) ) return false ; if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; if ( RegVT == <STR_LIT> ) { if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; } } else if ( ! VA . isRegLoc ( ) ) { if ( ! MatchingStackOffset ( Arg , VA . getLocMemOffset ( ) , Flags , MFI , MRI , TII ) ) return false ; } } } const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( ! parametersInCSRMatch ( MRI , CallerPreserved , ArgLocs , OutVals ) ) return false ; }


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && N -> getOpcode ( ) == <STR_LIT> ) { SDNode * BVN = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( BVN -> getValueType ( <NUM_LIT> ) != <STR_LIT> || BVN -> getOpcode ( ) != <STR_LIT> ) return false ; unsigned LoElt = DAG . getDataLayout ( ) . isBigEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; unsigned HiElt = <NUM_LIT> - LoElt ; ConstantSDNode * Lo0 = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( LoElt ) ) ; ConstantSDNode * Hi0 = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( HiElt ) ) ;

ConstantSDNode * Lo1 = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( LoElt + <NUM_LIT> ) ) ;


<s> bool <ISA_LIT>TargetLowering :: isFMAFasterThanFMulAndFAdd ( const MachineFunction & MF , EVT VT ) const { if ( ! Subtarget -> hasMVEFloatOps ( ) ) return false ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : return true ; default :


<s> if ( ! Subtarget -> hasMVEFloatOps ( ) ) return false ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : return true ; default : break ; }


<s> if ( VT == <STR_LIT> && Subtarget -> hasFullFP16 ( ) ) return <STR_LIT> ( Imm ) != - <NUM_LIT> ; if ( VT == <STR_LIT> ) return <STR_LIT> ( Imm ) != - <NUM_LIT> ; if ( VT == <STR_LIT> && Subtarget -> hasFP64 ( ) ) return <STR_LIT> ( Imm ) != - <NUM_LIT> ;


<s> unsigned VecSize = DL . getTypeSizeInBits ( VecTy ) ; unsigned ElSize = DL . getTypeSizeInBits ( VecTy -> getElementType ( ) ) ; if ( ! Subtarget -> hasNEON ( ) && ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; if ( Subtarget -> hasNEON ( ) && VecTy -> getElementType ( ) -> isHalfTy ( ) ) return false ; if ( Subtarget -> hasMVEIntegerOps ( ) && Factor == <NUM_LIT> ) return false ;

if ( VecTy -> getNumElements ( ) < <NUM_LIT> ) return false ;


<s> if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) if ( ! ( GV = GA -> getBaseObject ( ) ) ) return false ;

if ( const auto * V = dyn_cast < GlobalVariable > ( GV ) ) return V -> isConstant ( ) ;


<s> if ( const auto * V = dyn_cast < GlobalVariable > ( GV ) ) return V -> isConstant ( ) ;


<s> if ( V2Tmp -> getOpcode ( ) == <STR_LIT> ) V2TmpReg = V2Tmp -> getOperand ( <NUM_LIT> ) ; if ( ! K1 || ! K2 || * K1 == Op2 || * K2 != K2Tmp || V1Tmp != V2Tmp || V2TmpReg != V2 ) return false ; const SDValue * LowerCheckOp = isLowerSaturate ( LHS1 , RHS1 , TrueVal1 , FalseVal1 , CC1 , * K1 ) ? & Op : isLowerSaturate ( LHS2 , RHS2 , TrueVal2 , FalseVal2 , CC2 , * K2 ) ? & Op2 : nullptr ; const SDValue * UpperCheckOp = isUpperSaturate ( LHS1 , RHS1 , TrueVal1 , FalseVal1 , CC1 , * K1 ) ? & Op : isUpperSaturate ( LHS2 , RHS2 , TrueVal2 , FalseVal2 , CC2 , * K2 ) ? & Op2 : nullptr ; if ( ! UpperCheckOp || ! LowerCheckOp || LowerCheckOp == UpperCheckOp ) return false ; int64_t Val1 = cast < ConstantSDNode > ( * K1 ) -> getSExtValue ( ) ; int64_t Val2 = cast < ConstantSDNode > ( * K2 ) -> getSExtValue ( ) ; int64_t PosVal = std :: max ( Val1 , Val2 ) ;

int64_t NegVal = std :: min ( Val1 , Val2 ) ;


<s> if ( VT . getVectorNumElements ( ) == <NUM_LIT> && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( M [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> && ( Subtarget -> hasNEON ( ) || isLegalMVEShuffleOp ( PFEntry ) ) ) return true ; } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; if ( EltSize >= <NUM_LIT> || ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || ShuffleVectorInst :: isIdentityMask ( M ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF ) ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) && isReverseMask ( M , VT ) ) return true ; else if ( Subtarget -> hasMVEIntegerOps ( ) && ( isVMOVNMask ( M , VT , <NUM_LIT> ) || isVMOVNMask ( M , VT , <NUM_LIT> ) ) ) return true ; else return false ;


<s> } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; if ( EltSize >= <NUM_LIT> || ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || ShuffleVectorInst :: isIdentityMask ( M ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) ) return true ;

else if ( Subtarget -> hasNEON ( ) && ( isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF ) ) ) return true ;


<s> EVT VT = ExtVal . getValueType ( ) ; if ( ! isTypeLegal ( VT ) ) return false ; if ( auto * Ld = dyn_cast < MaskedLoadSDNode > ( ExtVal . getOperand ( <NUM_LIT> ) ) ) { if ( Ld -> isExpandingLoad ( ) ) return false ;


<s> break ; } return SDValue ( ) ; case <NUM_LIT> : VT = is128Bits ? <STR_LIT> : <STR_LIT> ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( type == OtherModImm ) return SDValue ( ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( type == MVEVMVNModImm ) return SDValue ( ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } return SDValue ( ) ; case <NUM_LIT> : { if ( type != VMOVModImm ) return SDValue ( ) ; uint64_t BitMask = <NUM_LIT> ; uint64_t Val = <NUM_LIT> ; unsigned ImmMask = <NUM_LIT> ;


<s> for ( unsigned i = <NUM_LIT> ; i < NumElts ; i += <NUM_LIT> ) { if ( M [ i ] >= <NUM_LIT> && M [ i ] != ( int ) i ) return false ; if ( M [ i + <NUM_LIT> ] >= <NUM_LIT> && M [ i + <NUM_LIT> ] != ( int ) ( NumElts + i + Offset ) ) return false ; }


<s> if ( M [ i ] >= <NUM_LIT> && M [ i ] != ( int ) i ) return false ; if ( M [ i + <NUM_LIT> ] >= <NUM_LIT> && M [ i + <NUM_LIT> ] != ( int ) ( NumElts + i + Offset ) ) return false ;


<s> static bool isVREVMask ( ArrayRef < int > M , EVT VT , unsigned BlockSize ) { assert ( ( BlockSize == <NUM_LIT> || BlockSize == <NUM_LIT> || BlockSize == <NUM_LIT> ) && <STR_LIT> ) ; unsigned EltSz = VT . getScalarSizeInBits ( ) ; if ( EltSz == <NUM_LIT> ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned BlockElts = M [ <NUM_LIT> ] + <NUM_LIT> ;

if ( M [ <NUM_LIT> ] < <NUM_LIT> ) BlockElts = BlockSize / EltSz ;


<s> if ( M [ <NUM_LIT> ] < <NUM_LIT> ) BlockElts = BlockSize / EltSz ; if ( BlockSize <= EltSz || BlockSize != BlockElts * EltSz ) return false ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( M [ i ] < <NUM_LIT> ) continue ;

if ( ( unsigned ) M [ i ] != ( i - i % BlockElts ) + ( BlockElts - <NUM_LIT> - i % BlockElts ) ) return false ;


<s> static SDValue LowerAtomicLoadStore ( SDValue Op , SelectionDAG & DAG ) { if ( isStrongerThanMonotonic ( cast < AtomicSDNode > ( Op ) -> getOrdering ( ) ) ) return SDValue ( ) ;


<s> <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( BA , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; if ( ! IsPositionIndependent ) return Result ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , DL , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , PtrVT , Result , PICLabel ) ;


<s> bool hasDominantValue = false ; bool isConstant = true ; DenseMap < SDValue , unsigned > ValueCounts ; SDValue Value ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = Op . getOperand ( i ) ; if ( V . isUndef ( ) ) continue ; if ( i > <NUM_LIT> ) isOnlyLowElement = false ; if ( ! isa < ConstantFPSDNode > ( V ) && ! isa < ConstantSDNode > ( V ) ) isConstant = false ; ValueCounts . insert ( std :: make_pair ( V , <NUM_LIT> ) ) ; unsigned & Count = ValueCounts [ V ] ; if ( ++ Count > ( NumElts / <NUM_LIT> ) ) { hasDominantValue = true ; Value = V ; } } if ( ValueCounts . size ( ) != <NUM_LIT> ) usesOnlyOneValue = false ; if ( ! Value . getNode ( ) && ! ValueCounts . empty ( ) ) Value = ValueCounts . begin ( ) -> first ; if ( ValueCounts . empty ( ) ) return DAG . getUNDEF ( VT ) ; if ( isOnlyLowElement && ! <STR_LIT> ( Value . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Value ) ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; if ( hasDominantValue && EltSize <= <NUM_LIT> ) { if ( ! isConstant ) { SDValue N ; ConstantSDNode * constIndex ; if ( Value -> getOpcode ( ) == <STR_LIT> && ( constIndex = dyn_cast < ConstantSDNode > ( Value -> getOperand ( <NUM_LIT> ) ) ) ) { if ( VT != Value -> getOperand ( <NUM_LIT> ) . getValueType ( ) ) { unsigned index = constIndex -> getAPIntValue ( ) . getLimitedValue ( ) % VT . getVectorNumElements ( ) ; N = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , DAG . getUNDEF ( VT ) , Value , DAG . getConstant ( index , dl , <STR_LIT> ) ) , DAG . getConstant ( index , dl , <STR_LIT> ) ) ; } else N = DAG . getNode ( <STR_LIT> , dl , VT , Value -> getOperand ( <NUM_LIT> ) , Value -> getOperand ( <NUM_LIT> ) ) ; } else N = DAG . getNode ( <STR_LIT> , dl , VT , Value ) ; if ( ! usesOnlyOneValue ) { for ( unsigned I = <NUM_LIT> ; I < NumElts ; ++ I ) { if ( Op . getOperand ( I ) == Value ) continue ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N ) ; Ops . push_back ( Op . getOperand ( I ) ) ; Ops . push_back ( DAG . getConstant ( I , dl , <STR_LIT> ) ) ; N = DAG . getNode ( <STR_LIT> , dl , VT , Ops ) ;


<s> VA = RVLocs [ ++ i ] ; SDValue Hi = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Hi . getValue ( <NUM_LIT> ) ; InFlag = Hi . getValue ( <NUM_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; VA = RVLocs [ ++ i ] ; Lo = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Lo . getValue ( <NUM_LIT> ) ; InFlag = Lo . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Hi = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Hi . getValue ( <NUM_LIT> ) ; InFlag = Hi . getValue ( <NUM_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } } else { Val = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val ) ;


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( Op1VT == Op2VT && <STR_LIT> ) ; assert ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( ST -> hasMVEIntegerOps ( ) && <STR_LIT> ) ; SDValue NewV1 = PromoteMVEPredVector ( dl , V1 , Op1VT , DAG ) ; SDValue NewV2 = PromoteMVEPredVector ( dl , V2 , Op2VT , DAG ) ; MVT ElType = getVectorTyFromPredicateVector ( VT ) . getScalarType ( ) . getSimpleVT ( ) ; EVT ConcatVT = <STR_LIT> ( ElType , NumElts ) ; SDValue ConVec = DAG . getNode ( <STR_LIT> , dl , ConcatVT ) ; auto ExractInto = [ & DAG , & dl ] ( SDValue NewV , SDValue ConVec , unsigned & j ) { EVT NewVT = NewV . getValueType ( ) ; EVT ConcatVT = ConVec . getValueType ( ) ; for ( unsigned i = <NUM_LIT> , e = NewVT . getVectorNumElements ( ) ; i < e ; i ++ , j ++ ) { SDValue Elt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewV , DAG . getIntPtrConstant ( i , dl ) ) ; ConVec = DAG . getNode ( <STR_LIT> , dl , ConcatVT , ConVec , Elt , DAG . getConstant ( j , dl , <STR_LIT> ) ) ;


<s> SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; EVT Op1VT = V1 . getValueType ( ) ; EVT Op2VT = V2 . getValueType ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( Op1VT == Op2VT && <STR_LIT> ) ; assert ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( ST -> hasMVEIntegerOps ( ) && <STR_LIT> ) ; SDValue NewV1 = PromoteMVEPredVector ( dl , V1 , Op1VT , DAG ) ; SDValue NewV2 = PromoteMVEPredVector ( dl , V2 , Op2VT , DAG ) ; MVT ElType = getVectorTyFromPredicateVector ( VT ) . getScalarType ( ) . getSimpleVT ( ) ; EVT ConcatVT = <STR_LIT> ( ElType , NumElts ) ; SDValue ConVec = DAG . getNode ( <STR_LIT> , dl , ConcatVT ) ; auto ExractInto = [ & DAG , & dl ] ( SDValue NewV , SDValue ConVec , unsigned & j ) { EVT NewVT = NewV . getValueType ( ) ; EVT ConcatVT = ConVec . getValueType ( ) ; for ( unsigned i = <NUM_LIT> , e = NewVT . getVectorNumElements ( ) ; i < e ; i ++ , j ++ ) {

SDValue Elt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewV , DAG . getIntPtrConstant ( i , dl ) ) ;


<s> if ( IsDouble || ! ST -> useNEONForSinglePrecisionFP ( ) ) { return Op ; } SDLoc DL ( Op ) ; SDValue NewVal = DAG . getTargetConstant ( ImmVal , DL , <STR_LIT> ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewVal ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } if ( ! ST -> hasNEON ( ) || ( ! IsDouble && ! ST -> useNEONForSinglePrecisionFP ( ) ) ) return SDValue ( ) ; EVT VMovVT ; uint64_t iVal = FPVal . bitcastToAPInt ( ) . getZExtValue ( ) ; if ( IsDouble && ( iVal & <NUM_LIT> ) != ( iVal >> <NUM_LIT> ) ) return SDValue ( ) ; SDValue NewVal = isVMOVModifiedImm ( iVal & <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , DAG , SDLoc ( Op ) , VMovVT , false , VMOVModImm ) ; if ( NewVal != SDValue ( ) ) { SDLoc DL ( Op ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , VMovVT , NewVal ) ; if ( IsDouble ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant ) ; SDValue VecFConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecFConstant , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } NewVal = isVMOVModifiedImm ( ~ iVal & <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , DAG , SDLoc ( Op ) , VMovVT , false , VMVNModImm ) ; if ( NewVal != SDValue ( ) ) { SDLoc DL ( Op ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , VMovVT , NewVal ) ; if ( IsDouble ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant ) ; SDValue VecFConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecFConstant , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } return SDValue ( ) ;


<s> SDLoc dl ( Op ) ; ConstantPoolSDNode * CP = cast < ConstantPoolSDNode > ( Op ) ; SDValue Res ; if ( Subtarget -> genExecuteOnly ( ) ) { auto AFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; auto T = const_cast < Type * > ( CP -> getType ( ) ) ; auto C = const_cast < Constant * > ( CP -> getConstVal ( ) ) ; auto M = const_cast < Module * > ( DAG . getMachineFunction ( ) . getFunction ( ) . getParent ( ) ) ; auto GV = new GlobalVariable ( * M , T , true , GlobalVariable :: InternalLinkage , C , Twine ( DAG . getDataLayout ( ) . getPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine ( DAG . getMachineFunction ( ) . getFunctionNumber ( ) ) + <STR_LIT> + Twine ( AFI -> createPICLabelUId ( ) ) ) ;

SDValue GA = DAG . getTargetGlobalAddress ( dyn_cast < GlobalValue > ( GV ) , dl , PtrVT ) ;


<s> SDValue FltRounds = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FPSCR , DAG . getConstant ( <NUM_LIT> << <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue RMODE = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FltRounds , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RMODE , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;


<s> SDValue FPSCR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; SDValue FltRounds = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FPSCR , DAG . getConstant ( <NUM_LIT> << <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue RMODE = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FltRounds , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RMODE , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;


<s> const unsigned DstSz = Op . getValueType ( ) . getSizeInBits ( ) ; const unsigned SrcSz = SrcVal . getValueType ( ) . getSizeInBits ( ) ; assert ( DstSz > SrcSz && DstSz <= <NUM_LIT> && SrcSz >= <NUM_LIT> && <STR_LIT> ) ; assert ( ( ! Subtarget -> hasFP64 ( ) || ! Subtarget -> hasFP<ISA_LIT>v8Base ( ) ) && <STR_LIT> ) ; assert ( ! ( DstSz == <NUM_LIT> && Subtarget -> hasFP16 ( ) ) && <STR_LIT> ) ; SDLoc Loc ( Op ) ; RTLIB :: Libcall LC ; MakeLibCallOptions CallOptions ; if ( SrcSz == <NUM_LIT> ) { if ( Subtarget -> hasFP16 ( ) ) SrcVal = DAG . getNode ( <STR_LIT> , Loc , <STR_LIT> , SrcVal ) ; else { LC = RTLIB :: getFPEXT ( <STR_LIT> , <STR_LIT> ) ; assert ( LC != RTLIB :: UNKNOWN_LIBCALL && <STR_LIT> ) ; SrcVal = makeLibCall ( DAG , LC , <STR_LIT> , SrcVal , CallOptions , Loc ) . first ; } } if ( DstSz != <NUM_LIT> ) return SrcVal ; if ( Subtarget -> hasFP64 ( ) ) return DAG . getNode ( <STR_LIT> , Loc , <STR_LIT> , SrcVal ) ;


<s> EVT SrcVT = SrcVal . getValueType ( ) ; EVT DstVT = Op . getValueType ( ) ; const unsigned DstSz = Op . getValueType ( ) . getSizeInBits ( ) ; const unsigned SrcSz = SrcVT . getSizeInBits ( ) ; ( void ) DstSz ; assert ( DstSz < SrcSz && SrcSz <= <NUM_LIT> && DstSz >= <NUM_LIT> && <STR_LIT> ) ;

assert ( ( ! Subtarget -> hasFP64 ( ) || ! Subtarget -> hasFP<ISA_LIT>v8Base ( ) ) && <STR_LIT> ) ;


<s> if ( VT . isVector ( ) ) return LowerVectorFP_TO_INT ( Op , DAG ) ; if ( isUnsupportedFloatingType ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { RTLIB :: Libcall LC ; if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; else LC = RTLIB :: getFPTOUINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; MakeLibCallOptions CallOptions ;

return makeLibCall ( DAG , LC , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , CallOptions , SDLoc ( Op ) ) . first ;


<s> if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; else LC = RTLIB :: getFPTOUINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; MakeLibCallOptions CallOptions ; return makeLibCall ( DAG , LC , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , CallOptions , SDLoc ( Op ) ) . first ; }


<s> EVT ArgVT = Arg . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; Type * RetTy = StructType :: get ( ArgTy , ArgTy ) ; auto & DL = DAG . getDataLayout ( ) ; ArgListTy Args ; bool ShouldUseSRet = Subtarget -> isAPCS_ABI ( ) ; SDValue SRet ; if ( ShouldUseSRet ) { const uint64_t ByteSize = DL . getTypeAllocSize ( RetTy ) ; const unsigned StackAlign = DL . getPrefTypeAlignment ( RetTy ) ; int FrameIdx = MFI . CreateStackObject ( ByteSize , StackAlign , false ) ; SRet = DAG . getFrameIndex ( FrameIdx , TLI . getPointerTy ( DL ) ) ; ArgListEntry Entry ; Entry . Node = SRet ; Entry . Ty = RetTy -> getPointerTo ( ) ; Entry . IsSExt = false ; Entry . IsZExt = false ; Entry . IsSRet = true ; Args . push_back ( Entry ) ; RetTy = Type :: getVoidTy ( * DAG . getContext ( ) ) ; } ArgListEntry Entry ;


<s> ++ NumMovwMovt ; SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; RelAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , G ) ; } else { <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; RelAddr = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; } SDValue SB = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , PtrVT ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , SB , RelAddr ) ; return Result ; } if ( Subtarget -> useMovt ( ) ) { ++ NumMovwMovt ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; } else { SDValue CPAddr = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ;


<s> Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , DescAddr , SDValue ( ) ) ; Chain = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , FuncTLVGet , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getRegisterMask ( Mask ) , Chain . getValue ( <NUM_LIT> ) ) ;

return DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ;


<s> MachineFrameInfo & MFI = F . getFrameInfo ( ) ; MFI . setAdjustsStack ( true ) ; auto TRI = getTargetMachine ( ) . getSubtargetImpl ( F . getFunction ( ) ) -> getRegisterInfo ( ) ; auto ARI = static_cast < const <ISA_LIT>RegisterInfo * > ( TRI ) ; const uint32_t * Mask = ARI -> getTLSCallPreservedMask ( DAG . getMachineFunction ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , DescAddr , SDValue ( ) ) ;

Chain = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , FuncTLVGet , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getRegisterMask ( Mask ) , Chain . getValue ( <NUM_LIT> ) ) ;


<s> SDValue TEB = CurrentTEB . getValue ( <NUM_LIT> ) ; Chain = CurrentTEB . getValue ( <NUM_LIT> ) ; SDValue TLSArray = DAG . getNode ( <STR_LIT> , DL , PtrVT , TEB , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; TLSArray = DAG . getLoad ( PtrVT , DL , Chain , TLSArray , MachinePointerInfo ( ) ) ; SDValue TLSIndex = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; TLSIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex ) ; TLSIndex = DAG . getLoad ( PtrVT , DL , Chain , TLSIndex , MachinePointerInfo ( ) ) ; SDValue Slot = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue TLS = DAG . getLoad ( PtrVT , DL , Chain , DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSArray , Slot ) , MachinePointerInfo ( ) ) ; const auto * GA = cast < GlobalAddressSDNode > ( Op ) ; auto * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <STR_LIT> ) ;

SDValue Offset = DAG . getLoad ( PtrVT , DL , Chain , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ) , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ;


<s> SDLoc DL ( Op ) ; SDValue Ops [ ] = { Chain , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) } ; SDValue CurrentTEB = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; SDValue TEB = CurrentTEB . getValue ( <NUM_LIT> ) ; Chain = CurrentTEB . getValue ( <NUM_LIT> ) ; SDValue TLSArray = DAG . getNode ( <STR_LIT> , DL , PtrVT , TEB , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; TLSArray = DAG . getLoad ( PtrVT , DL , Chain , TLSArray , MachinePointerInfo ( ) ) ; SDValue TLSIndex = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; TLSIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex ) ; TLSIndex = DAG . getLoad ( PtrVT , DL , Chain , TLSIndex , MachinePointerInfo ( ) ) ; SDValue Slot = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue TLS = DAG . getLoad ( PtrVT , DL , Chain , DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSArray , Slot ) , MachinePointerInfo ( ) ) ;

const auto * GA = cast < GlobalAddressSDNode > ( Op ) ;


<s> Type * EltPtrTy = SubVecTy -> getVectorElementType ( ) -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ; Type * Tys [ ] = { EltPtrTy , SubVecTy } ; Function * VstNFunc = <STR_LIT> ( SI -> getModule ( ) , StoreInts , Tys ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , EltPtrTy ) ) ; for ( auto S : Shuffles ) Ops . push_back ( S ) ; for ( unsigned F = <NUM_LIT> ; F < Factor ; F ++ ) { Ops . push_back ( Builder . getInt32 ( F ) ) ; Builder . CreateCall ( VstNFunc , Ops ) ; Ops . pop_back ( ) ; } } } ; for ( unsigned StoreCount = <NUM_LIT> ; StoreCount < NumStores ; ++ StoreCount ) { if ( StoreCount > <NUM_LIT> ) BaseAddr = Builder . CreateConstGEP1_32 ( SubVecTy -> getVectorElementType ( ) , BaseAddr , LaneLen * Factor ) ; SmallVector < Value * , <NUM_LIT> > Shuffles ; for ( unsigned i = <NUM_LIT> ; i < Factor ; i ++ ) { unsigned IdxI = StoreCount * LaneLen * Factor + i ; if ( Mask [ IdxI ] >= <NUM_LIT> ) { Shuffles . push_back ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Builder , Mask [ IdxI ] , LaneLen , <NUM_LIT> ) ) ) ; } else { unsigned StartMask = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < LaneLen ; j ++ ) { unsigned IdxJ = StoreCount * LaneLen * Factor + j ; if ( Mask [ IdxJ * Factor + IdxI ] >= <NUM_LIT> ) { StartMask = Mask [ IdxJ * Factor + IdxI ] - IdxJ ; break ; } } Shuffles . push_back ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Builder , StartMask , LaneLen , <NUM_LIT> ) ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerINTRINSIC_VOID ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) const { unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { default : return SDValue ( ) ; case <STR_LIT> : { MachineFunction & MF = DAG . getMachineFunction ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc dl ( Op ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; const <ISA_LIT>BaseRegisterInfo * ARI = Subtarget -> getRegisterInfo ( ) ;

const uint32_t * Mask = ARI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallingConv :: C ) ;


<s> PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , PtrOff ) ; return DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo :: getStack ( DAG . getMachineFunction ( ) , LocMemOffset ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerMemOpCallTo ( SDValue Chain , SDValue StackPtr , SDValue Arg , const SDLoc & dl , SelectionDAG & DAG , const CCValAssign & VA , <STR_LIT> Flags ) const { unsigned LocMemOffset = VA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset , dl ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , PtrOff ) ; return DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo :: getStack ( DAG . getMachineFunction ( ) , LocMemOffset ) ) ;


<s> SDValue Combo = NewLoad ; if ( ! PassThru . isUndef ( ) && ( PassThru . getOpcode ( ) != <STR_LIT> || ! isZeroVector ( PassThru -> getOperand ( <NUM_LIT> ) ) ) ) Combo = DAG . getNode ( <STR_LIT> , dl , VT , Mask , NewLoad , PassThru ) ; return DAG . getMergeValues ( { Combo , NewLoad . getValue ( <NUM_LIT> ) } , dl ) ;


<s> case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG , Subtarget ) ;

case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ;


<s> SDLoc dl ( Op ) ; SDValue Load = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , LD -> getChain ( ) , LD -> getBasePtr ( ) , EVT :: getIntegerVT ( * DAG . getContext ( ) , MemVT . getSizeInBits ( ) ) , LD -> getMemOperand ( ) ) ; SDValue Pred = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) ; if ( MemVT != <STR_LIT> ) Pred = DAG . getNode ( <STR_LIT> , dl , MemVT , Pred , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;

return DAG . getMergeValues ( { Pred , Load . getValue ( <NUM_LIT> ) } , dl ) ;


<s> static SDValue LowerPredicateLoad ( SDValue Op , SelectionDAG & DAG ) { LoadSDNode * LD = cast < LoadSDNode > ( Op . getNode ( ) ) ; EVT MemVT = LD -> getMemoryVT ( ) ; assert ( ( MemVT == <STR_LIT> || MemVT == <STR_LIT> || MemVT == <STR_LIT> ) && <STR_LIT> ) ; assert ( MemVT == Op . getValueType ( ) ) ; assert ( LD -> getExtensionType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( LD -> isUnindexed ( ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue Load = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , LD -> getChain ( ) , LD -> getBasePtr ( ) , EVT :: getIntegerVT ( * DAG . getContext ( ) , MemVT . getSizeInBits ( ) ) , LD -> getMemOperand ( ) ) ; SDValue Pred = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) ; if ( MemVT != <STR_LIT> ) Pred = DAG . getNode ( <STR_LIT> , dl , MemVT , Pred , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;


<s> StoreSDNode * ST = cast < StoreSDNode > ( Op . getNode ( ) ) ; EVT MemVT = ST -> getMemoryVT ( ) ; assert ( ( MemVT == <STR_LIT> || MemVT == <STR_LIT> || MemVT == <STR_LIT> ) && <STR_LIT> ) ; assert ( MemVT == ST -> getValue ( ) . getValueType ( ) ) ; assert ( ! ST -> isTruncatingStore ( ) && <STR_LIT> ) ; assert ( ST -> isUnindexed ( ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue Build = ST -> getValue ( ) ; if ( MemVT != <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned I = <NUM_LIT> ; I < MemVT . getVectorNumElements ( ) ; I ++ ) Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Build , DAG . getConstant ( I , dl , <STR_LIT> ) ) ) ; for ( unsigned I = MemVT . getVectorNumElements ( ) ; I < <NUM_LIT> ; I ++ ) Ops . push_back ( DAG . getUNDEF ( <STR_LIT> ) ) ; Build = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } SDValue GRP = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Build ) ; return DAG . getTruncStore ( ST -> getChain ( ) , dl , GRP , ST -> getBasePtr ( ) , EVT :: getIntegerVT ( * DAG . getContext ( ) , MemVT . getSizeInBits ( ) ) , ST -> getMemOperand ( ) ) ;


<s> NewOpcode = IsAdd ? <STR_LIT> : <STR_LIT> ; break ; } SDLoc dl ( Op ) ; SDValue Add = DAG . getNode ( NewOpcode , dl , <STR_LIT> , DAG . getSExtOrTrunc ( Op -> getOperand ( <NUM_LIT> ) , dl , <STR_LIT> ) , DAG . getSExtOrTrunc ( Op -> getOperand ( <NUM_LIT> ) , dl , <STR_LIT> ) ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , Add ) ;


<s> Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; Chain = Offset . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT , Offset , PICLabel ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; } else { assert ( model == TLSModel :: LocalExec ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <STR_LIT> ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; }

return DAG . getNode ( <STR_LIT> , dl , PtrVT , ThreadPointer , Offset ) ;


<s> SDLoc dl ( GA ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; SDValue Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Argument ; Entry . Ty = ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getInt32Ty ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ;


<s> unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> ) { if ( ST -> hasNEON ( ) ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; else if ( isLegalMVEShuffleOp ( PFEntry ) ) { unsigned LHSID = ( PFEntry >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned RHSID = ( PFEntry >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned PFEntryLHS = PerfectShuffleTable [ LHSID ] ; unsigned PFEntryRHS = PerfectShuffleTable [ RHSID ] ; if ( isLegalMVEShuffleOp ( PFEntryLHS ) && isLegalMVEShuffleOp ( PFEntryRHS ) ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; } } } if ( EltSize >= <NUM_LIT> ) { EVT EltVT = EVT :: getFloatingPointVT ( EltSize ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumElts ) ; V1 = DAG . getNode ( <STR_LIT> , dl , VecVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , VecVT , V2 ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) Ops . push_back ( DAG . getUNDEF ( EltVT ) ) ; else Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , ShuffleMask [ i ] < ( int ) NumElts ? V1 : V2 , DAG . getConstant ( ShuffleMask [ i ] & ( NumElts - <NUM_LIT> ) , dl , <STR_LIT> ) ) ) ; } SDValue Val = DAG . getNode ( <STR_LIT> , dl , VecVT , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Val ) ; } if ( ST -> hasNEON ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) && isReverseMask ( ShuffleMask , VT ) ) return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16 ( Op , DAG ) ; if ( ST -> hasNEON ( ) && VT == <STR_LIT> ) if ( SDValue NewOp = LowerVECTOR_SHUFFLEv8i8 ( Op , ShuffleMask , DAG ) ) return NewOp ;

if ( ST -> hasMVEIntegerOps ( ) ) if ( SDValue NewOp = LowerVECTOR_SHUFFLEUsingMovs ( Op , ShuffleMask , DAG ) ) return NewOp ;


<s> SDValue Parts [ <NUM_LIT> ] ; auto getMovIdx = [ ] ( ArrayRef < int > ShuffleMask , int Start , int Length ) { int MovIdx = - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < Length ; i ++ ) { if ( ShuffleMask [ Start + i ] >= <NUM_LIT> ) { if ( ShuffleMask [ Start + i ] % Length != i ) return - <NUM_LIT> ; MovIdx = ShuffleMask [ Start + i ] / Length ; break ; } } if ( MovIdx == - <NUM_LIT> ) return - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < Length ; i ++ ) { if ( ShuffleMask [ Start + i ] >= <NUM_LIT> && ( ShuffleMask [ Start + i ] / Length != MovIdx || ShuffleMask [ Start + i ] % Length != i ) ) return - <NUM_LIT> ; } return MovIdx ; } ; for ( int Part = <NUM_LIT> ; Part < <NUM_LIT> ; ++ Part ) { int Elt = getMovIdx ( ShuffleMask , Part * QuarterSize , QuarterSize ) ; if ( Elt != - <NUM_LIT> ) {

SDValue Input = Op -> getOperand ( <NUM_LIT> ) ;


<s> Instruction * <ISA_LIT>TargetLowering :: makeDMB ( IRBuilder < > & Builder , <STR_LIT> Domain ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; if ( ! Subtarget -> hasDataBarrier ( ) ) { if ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isThumb ( ) ) {

Function * MCR = <STR_LIT> ( M , <STR_LIT> ) ;


<s> Function * MCR = <STR_LIT> ( M , <STR_LIT> ) ; Value * args [ <NUM_LIT> ] = { Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) } ; return Builder . CreateCall ( MCR , args ) ;


<s> if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == <STR_LIT> ) return false ; return true ;


<s> if ( ! Subtarget -> supportsTailCall ( ) ) return false ; auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( <STR_LIT> ) ; if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == <STR_LIT> ) return false ;


<s> else { assert ( NextVA . isMemLoc ( ) ) ; if ( ! StackPtr . getNode ( ) ) StackPtr = DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , getPointerTy ( DAG . getDataLayout ( ) ) ) ; MemOpChains . push_back ( LowerMemOpCallTo ( Chain , StackPtr , fmrrd . getValue ( <NUM_LIT> - id ) , dl , DAG , NextVA , Flags ) ) ;


<s> if ( SDValue Result = PerformSHLSimplify ( N , DCI , Subtarget ) ) return Result ;

if ( SDValue Result = PerformADDCombineWithOperands ( N , N0 , N1 , DCI , Subtarget ) ) return Result ;


<s> if ( SDValue Result = PerformADDCombineWithOperands ( N , N0 , N1 , DCI , Subtarget ) ) return Result ; return PerformADDCombineWithOperands ( N , N1 , N0 , DCI , Subtarget ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SelectionDAG & DAG = DCI . DAG ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN && Subtarget -> hasNEON ( ) && BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize <= <NUM_LIT> ) { EVT VbicVT ; SDValue Val = isVMOVModifiedImm ( ( ~ SplatBits ) . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , dl , VbicVT , VT . is128BitVector ( ) , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VbicVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Vbic = DAG . getNode ( <STR_LIT> , dl , VbicVT , Input , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vbic ) ; } } } if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , true , DCI ) ) return Result ; if ( SDValue Result = PerformSHLSimplify ( N , DCI , Subtarget ) ) return Result ; } if ( Subtarget -> isThumb1Only ( ) ) if ( SDValue Result = CombineANDShift ( N , DCI , Subtarget ) ) return Result ; return SDValue ( ) ;


<s> auto IsFalseIfZero = [ ] ( <STR_LIT> CC , int Imm ) { return ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) ; } ; assert ( ( IsTrueIfZero ( CC , Imm ) || IsFalseIfZero ( CC , Imm ) ) && <STR_LIT> ) ; SDLoc dl ( Int ) ; SelectionDAG & DAG = DCI . DAG ; SDValue Elements = Int . getOperand ( <NUM_LIT> ) ; unsigned IntOp = cast < ConstantSDNode > ( Int -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; assert ( ( N -> hasOneUse ( ) && N -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; SDNode * Br = * N -> use_begin ( ) ; SDValue OtherTarget = Br -> getOperand ( <NUM_LIT> ) ; auto UpdateUncondBr = [ ] ( SDNode * Br , SDValue Dest , SelectionDAG & DAG ) { SDValue NewBrOps [ ] = { Br -> getOperand ( <NUM_LIT> ) , Dest } ; SDValue NewBr = DAG . getNode ( <STR_LIT> , SDLoc ( Br ) , <STR_LIT> , NewBrOps ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Br , <NUM_LIT> ) , NewBr ) ; } ; if ( IntOp == <STR_LIT> ) { SDValue Res ; if ( IsTrueIfZero ( CC , Imm ) ) { SDValue Ops [ ] = { Chain , Elements , Dest } ; Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } else { UpdateUncondBr ( Br , Dest , DAG ) ;

SDValue Ops [ ] = { Chain , Elements , OtherTarget } ;


<s> case <STR_LIT> : case <STR_LIT> : if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , Cnt ) ) { VShiftOpc = <STR_LIT> ; break ; } if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , true , Cnt ) ) { VShiftOpc = ( IntNo == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; break ; } return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , true , Cnt ) ) break ; return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , Cnt ) ) break ; return SDValue ( ) ; case <STR_LIT> : if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , Cnt ) ) break ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , true , true , Cnt ) ) break ; llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; } switch ( IntNo ) { case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> :


<s> return DAG . getNode ( <STR_LIT> , dl , VT , Vorr ) ; } } } if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , false , DCI ) ) return Result ; if ( SDValue Result = PerformORCombineToSMULWBT ( N , DCI , Subtarget ) ) return Result ; } SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget -> hasNEON ( ) && N1 . getOpcode ( ) == <STR_LIT> && VT . isVector ( ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) { if ( N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) ) return SDValue ( ) ; APInt SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; APInt SplatBits0 , SplatBits1 ; BuildVectorSDNode * BVN0 = dyn_cast < BuildVectorSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; BuildVectorSDNode * BVN1 = dyn_cast < BuildVectorSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ;

if ( BVN0 && BVN0 -> isConstantSplat ( SplatBits0 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) {