<s> if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) return false ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { if ( SelectT2AddrModeImm8 ( N , Base , OffImm ) ) return false ;

int RHSC = ( int ) RHS -> getZExtValue ( ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeImm5S ( SDValue N , unsigned Scale , SDValue & Base , SDValue & OffImm ) { if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { if ( N . getOpcode ( ) == <STR_LIT> ) { return false ; } else if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; } else { Base = N ; } OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , Scale , <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; OffImm = CurDAG -> getTargetConstant ( RHSC , SDLoc ( N ) , <STR_LIT> ) ; return true ; }


<s> if ( Use -> getOpcode ( ) == <STR_LIT> ) return true ; if ( Use -> isMachineOpcode ( ) ) { const TargetInstrDesc & TID = TII -> get ( Use -> getMachineOpcode ( ) ) ;


<s> if ( Use -> isMachineOpcode ( ) ) { const TargetInstrDesc & TID = TII -> get ( Use -> getMachineOpcode ( ) ) ; if ( TID . mayStore ( ) ) return true ; unsigned Opcode = TID . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; return TII -> isFpMLxInstruction ( Opcode ) ; }


<s> inline bool Pred_so_imm ( SDNode * inN ) const { ConstantSDNode * N = cast < ConstantSDNode > ( inN ) ;

return is_so_imm ( N -> getZExtValue ( ) ) ;


<s> ConstantSDNode * N = cast < ConstantSDNode > ( inN ) ;


<s> inline bool Pred_t2_so_imm ( SDNode * inN ) const {

ConstantSDNode * N = cast < ConstantSDNode > ( inN ) ;


<s> unsigned ShAmt = <NUM_LIT> ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( N , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } }

Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , ShAmt , ShOpcVal ) , <STR_LIT> ) ;


<s> int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( RHSC & <NUM_LIT> ) { RHSC = RHSC & ~ <NUM_LIT> ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } if ( isPowerOf2_32 ( RHSC ) ) { unsigned ShAmt = Log2_32 ( RHSC ) ; Base = Offset = N . getOperand ( <NUM_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , ShAmt , <STR_LIT> ) , <STR_LIT> ) ; return AM2_SHOP ; } } } } if ( N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> ) { Base = N ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } else if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ; return AM2_BASE ; } if ( N . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) || ( RHSC < <NUM_LIT> && RHSC > - <NUM_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC , <STR_LIT> ) , <STR_LIT> ) ; return AM2_BASE ; } } } if ( Subtarget -> isCortexA9 ( ) && ! N . hasOneUse ( ) ) { Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ; return AM2_BASE ; } <STR_LIT> AddSub = N . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) ) ; unsigned ShAmt = <NUM_LIT> ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrMode5 ( SDValue N , SDValue & Base , SDValue & Offset ) { if ( N . getOpcode ( ) != <STR_LIT> ) { Base = N ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } else if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( ( RHSC & <NUM_LIT> ) == <NUM_LIT> ) { RHSC >>= <NUM_LIT> ; if ( ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) || ( RHSC < <NUM_LIT> && RHSC > - <NUM_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC ) , <STR_LIT> ) ; return true ; }


<s> if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } else if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ; return true ; } }


<s> SDValue N1 = N . getOperand ( <NUM_LIT> ) ; Label = CurDAG -> getTargetConstant ( cast < ConstantSDNode > ( N1 ) -> getZExtValue ( ) , <STR_LIT> ) ; return true ; } return false ;


<s> SDValue Ops [ ] = { FalseVal , CPTmp0 , CPTmp1 , CPTmp2 , CC , CCR , InFlag } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) ; }


<s> if ( SelectShifterOperandReg ( TrueVal , CPTmp0 , CPTmp1 , CPTmp2 ) ) { SDValue CC = CurDAG -> getTargetConstant ( CCVal , <STR_LIT> ) ;

SDValue Ops [ ] = { FalseVal , CPTmp0 , CPTmp1 , CPTmp2 , CC , CCR , InFlag } ;


<s> <STR_LIT> ShOpcVal = <STR_LIT> ( N ) ; if ( ShOpcVal == <STR_LIT> ) return false ; BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { ShReg = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; ShImmVal = RHS -> getZExtValue ( ) & <NUM_LIT> ; } else { ShReg = N . getOperand ( <NUM_LIT> ) ; if ( ! isShifterOpProfitable ( N , ShOpcVal , ShImmVal ) ) return false ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( ShOpcVal , ShImmVal ) , <STR_LIT> ) ; return true ;


<s> <STR_LIT> ShOpcVal = <STR_LIT> ( N ) ; if ( ShOpcVal == <STR_LIT> ) return false ; BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { ShReg = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; ShImmVal = RHS -> getZExtValue ( ) & <NUM_LIT> ; } else { ShReg = N . getOperand ( <NUM_LIT> ) ;

if ( ! isShifterOpProfitable ( N , ShOpcVal , ShImmVal ) ) return false ;


<s> if ( ShOpcVal == <STR_LIT> ) return false ; BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ;

if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) {


<s> return true ; } else if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) return false ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { if ( SelectT2AddrModeImm8 ( N , Base , OffImm ) ) return false ; int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; }

OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ;


<s> if ( N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> ) { if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } else if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) return false ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { if ( SelectT2AddrModeImm8 ( N , Base , OffImm ) ) return false ; int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ; return true ; }


<s> Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ; return true ; }


<s> if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( ( RHSC >= - <NUM_LIT> ) && ( RHSC < <NUM_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ; return true ;


<s> <STR_LIT> ShOpcVal = <STR_LIT> ( N ) ; if ( ShOpcVal == <STR_LIT> ) return false ; BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { ShImmVal = RHS -> getZExtValue ( ) & <NUM_LIT> ; Opc = getI32Imm ( <STR_LIT> ( ShOpcVal , ShImmVal ) ) ; return true ; } return false ;


<s> if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { ShImmVal = RHS -> getZExtValue ( ) & <NUM_LIT> ; Opc = getI32Imm ( <STR_LIT> ( ShOpcVal , ShImmVal ) ) ;


<s> Base = N . getOperand ( <NUM_LIT> ) ; } else Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } RegisterSDNode * LHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; RegisterSDNode * RHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ( LHSR && LHSR -> getReg ( ) == <STR_LIT> ) || ( RHSR && RHSR -> getReg ( ) == <STR_LIT> ) ) { Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( ( RHSC & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> ) { RHSC /= Scale ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ;


<s> if ( N . getOpcode ( ) != <STR_LIT> ) { ConstantSDNode * NC = dyn_cast < ConstantSDNode > ( N ) ; if ( ! NC || ! NC -> isNullValue ( ) ) return false ; Base = Offset = N ; return true ;


<s> ConstantSDNode * NC = dyn_cast < ConstantSDNode > ( N ) ; if ( ! NC || ! NC -> isNullValue ( ) ) return false ; Base = Offset = N ; return true ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeS1 ( SDValue N , SDValue & Base , SDValue & OffImm , SDValue & Offset ) { return SelectThumbAddrModeRI5 ( N , <NUM_LIT> , Base , OffImm , Offset ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeS2 ( SDValue N , SDValue & Base , SDValue & OffImm , SDValue & Offset ) { return SelectThumbAddrModeRI5 ( N , <NUM_LIT> , Base , OffImm , Offset ) ;


<s> return SelectThumbAddrModeRI5 ( N , <NUM_LIT> , Base , OffImm , Offset ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeS4 ( SDValue N , SDValue & Base , SDValue & OffImm , SDValue & Offset ) { return SelectThumbAddrModeRI5 ( N , <NUM_LIT> , Base , OffImm , Offset ) ;


<s> if ( N . getOpcode ( ) != <STR_LIT> ) return false ; RegisterSDNode * LHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || ( LHSR && LHSR -> getReg ( ) == <STR_LIT> ) ) { if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( ( RHSC & <NUM_LIT> ) == <NUM_LIT> ) { RHSC >>= <NUM_LIT> ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ;


<s> SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDValue SuperReg ; if ( is64BitVector ) { unsigned Opc = DOpcodes [ OpcodeIndex ] ; const SDValue Ops [ ] = { MemAddr , Align , Pred , Reg0 , Chain } ; SDNode * VLd = CurDAG -> getMachineNode ( Opc , dl , ResTy , <STR_LIT> , Ops , <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) return VLd ; SuperReg = SDValue ( VLd , <NUM_LIT> ) ; assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> && <STR_LIT> ) ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) { SDValue D = CurDAG -> getTargetExtractSubreg ( <STR_LIT> + Vec , dl , VT , SuperReg ) ; ReplaceUses ( SDValue ( N , Vec ) , D ) ; } ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( VLd , <NUM_LIT> ) ) ; return NULL ; } if ( NumVecs <= <NUM_LIT> ) { unsigned Opc = QOpcodes0 [ OpcodeIndex ] ; const SDValue Ops [ ] = { MemAddr , Align , Pred , Reg0 , Chain } ; SDNode * VLd = CurDAG -> getMachineNode ( Opc , dl , ResTy , <STR_LIT> , Ops , <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) return VLd ; SuperReg = SDValue ( VLd , <NUM_LIT> ) ; Chain = SDValue ( VLd , <NUM_LIT> ) ; } else { EVT AddrTy = MemAddr . getValueType ( ) ; unsigned Opc = QOpcodes0 [ OpcodeIndex ] ;

SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , ResTy ) , <NUM_LIT> ) ;


<s> } Align = CurDAG -> getTargetConstant ( Alignment , <STR_LIT> ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDValue SuperReg ; unsigned Opc = Opcodes [ OpcodeIndex ] ; const SDValue Ops [ ] = { MemAddr , Align , Pred , Reg0 , Chain } ; unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; EVT ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ; SDNode * VLdDup = CurDAG -> getMachineNode ( Opc , dl , ResTy , <STR_LIT> , Ops , <NUM_LIT> ) ; SuperReg = SDValue ( VLdDup , <NUM_LIT> ) ; Chain = SDValue ( VLdDup , <NUM_LIT> ) ; assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> && <STR_LIT> ) ; unsigned SubIdx = <STR_LIT> ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) ReplaceUses ( SDValue ( N , Vec ) , CurDAG -> getTargetExtractSubreg ( SubIdx + Vec , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs ) , Chain ) ;


<s> case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDValue SuperReg ; unsigned Opc = Opcodes [ OpcodeIndex ] ; const SDValue Ops [ ] = { MemAddr , Align , Pred , Reg0 , Chain } ; unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; EVT ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ; SDNode * VLdDup = CurDAG -> getMachineNode ( Opc , dl , ResTy , <STR_LIT> , Ops , <NUM_LIT> ) ; SuperReg = SDValue ( VLdDup , <NUM_LIT> ) ; Chain = SDValue ( VLdDup , <NUM_LIT> ) ;


<s> case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes [ OpcodeIndex ] ) ; SDValue SuperReg ; SDValue V0 = N -> getOperand ( <NUM_LIT> + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( <NUM_LIT> + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) { if ( is64BitVector ) SuperReg = SDValue ( PairDRegs ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( PairQRegs ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; } else { SDValue V2 = N -> getOperand ( <NUM_LIT> + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( <NUM_LIT> + <NUM_LIT> ) ; if ( is64BitVector ) SuperReg = SDValue ( QuadDRegs ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( QuadQRegs ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ;


<s> Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; return CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops . data ( ) , <NUM_LIT> ) ; } SDValue V0 = N -> getOperand ( <NUM_LIT> + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( <NUM_LIT> + <NUM_LIT> ) ; SDValue V2 = N -> getOperand ( <NUM_LIT> + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( <NUM_LIT> + <NUM_LIT> ) ; SDValue RegSeq = SDValue ( QuadQRegs ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( RegSeq ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned Opc = QOpcodes0 [ OpcodeIndex ] ; SDNode * VStA = CurDAG -> getMachineNode ( Opc , dl , MemAddr . getValueType ( ) , <STR_LIT> , Ops . data ( ) , <NUM_LIT> ) ; Chain = SDValue ( VStA , <NUM_LIT> ) ; Ops [ <NUM_LIT> ] = SDValue ( VStA , <NUM_LIT> ) ; Ops [ <NUM_LIT> ] = Chain ; Opc = QOpcodes1 [ OpcodeIndex ] ; SDNode * VStB = CurDAG -> getMachineNode ( Opc , dl , MemAddr . getValueType ( ) , <STR_LIT> , Ops . data ( ) , <NUM_LIT> ) ;


<s> Ops . push_back ( Chain ) ; return CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops . data ( ) , <NUM_LIT> ) ; } SDValue V0 = N -> getOperand ( <NUM_LIT> + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( <NUM_LIT> + <NUM_LIT> ) ; SDValue V2 = N -> getOperand ( <NUM_LIT> + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( <NUM_LIT> + <NUM_LIT> ) ; SDValue RegSeq = SDValue ( QuadQRegs ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( RegSeq ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned Opc = QOpcodes0 [ OpcodeIndex ] ; SDNode * VStA = CurDAG -> getMachineNode ( Opc , dl , MemAddr . getValueType ( ) , <STR_LIT> , Ops . data ( ) , <NUM_LIT> ) ; Chain = SDValue ( VStA , <NUM_LIT> ) ; Ops [ <NUM_LIT> ] = SDValue ( VStA , <NUM_LIT> ) ; Ops [ <NUM_LIT> ] = Chain ; Opc = QOpcodes1 [ OpcodeIndex ] ; SDNode * VStB = CurDAG -> getMachineNode ( Opc , dl , MemAddr . getValueType ( ) , <STR_LIT> , Ops . data ( ) , <NUM_LIT> ) ; Chain = SDValue ( VStB , <NUM_LIT> ) ;

ReplaceUses ( SDValue ( N , <NUM_LIT> ) , Chain ) ;


<s> if ( ImmNode . getOpcode ( ) == <STR_LIT> ) { if ( ImmNode . getValueType ( ) . getScalarSizeInBits ( ) != ScalarBits ) return false ; ImmNode = ImmNode . getOperand ( <NUM_LIT> ) ; } if ( ImmNode . getValueType ( ) . getScalarSizeInBits ( ) != ScalarBits ) return false ; APFloat ImmAPF ( <NUM_LIT> ) ; switch ( ImmNode . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : { if ( ! isa < ConstantSDNode > ( ImmNode . getOperand ( <NUM_LIT> ) ) ) return false ; unsigned Imm = ImmNode . getConstantOperandVal ( <NUM_LIT> ) ; if ( ImmNode . getOpcode ( ) == <STR_LIT> ) Imm = <STR_LIT> ( Imm , ScalarBits ) ; ImmAPF = APFloat ( ScalarBits == <NUM_LIT> ? APFloat :: IEEEsingle ( ) : APFloat :: IEEEhalf ( ) , APInt ( ScalarBits , Imm ) ) ; break ; } case <STR_LIT> : { ImmAPF = APFloat ( <STR_LIT> ( ImmNode . getConstantOperandVal ( <NUM_LIT> ) ) ) ; break ; } default : return false ; } APFloat ToConvert = ImmAPF ; if ( FixedToFloat ) { if ( ! ImmAPF . getExactInverse ( & ToConvert ) ) return false ; } APSInt Converted ( <NUM_LIT> , false ) ; bool IsExact ; ToConvert . convertToInteger ( Converted , llvm :: RoundingMode :: NearestTiesToEven , & IsExact ) ; if ( ! IsExact || ! Converted . isPowerOf2 ( ) ) return false ; unsigned FracBits = Converted . logBase2 ( ) ; if ( FracBits > ScalarBits ) return false ; SmallVector < SDValue , <NUM_LIT> > Ops { VecVal , CurDAG -> getConstant ( FracBits , SDLoc ( N ) , <STR_LIT> ) } ; AddEmptyMVEPredicateToOps ( Ops , SDLoc ( N ) , Type ) ; unsigned int Opcode ;


<s> if ( SUBSrc0 . getOpcode ( ) != <STR_LIT> || SUBSrc1 . getOpcode ( ) != <STR_LIT> ) return false ; SDValue XORSrc0 = SUBSrc0 . getOperand ( <NUM_LIT> ) ; SDValue XORSrc1 = SUBSrc0 . getOperand ( <NUM_LIT> ) ; SDValue SRASrc0 = SUBSrc1 . getOperand ( <NUM_LIT> ) ; SDValue SRASrc1 = SUBSrc1 . getOperand ( <NUM_LIT> ) ; ConstantSDNode * SRAConstant = dyn_cast < ConstantSDNode > ( SRASrc1 ) ; EVT XType = SRASrc0 . getValueType ( ) ; unsigned Size = XType . getSizeInBits ( ) - <NUM_LIT> ; if ( XORSrc1 == SUBSrc1 && XORSrc0 == SRASrc0 && XType . isInteger ( ) && SRAConstant != nullptr && Size == SRAConstant -> getZExtValue ( ) ) { unsigned Opcode = Subtarget -> isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; CurDAG -> SelectNodeTo ( N , Opcode , VT , XORSrc0 ) ; return true ; } return false ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> default : return false ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ;


<s> assert ( VecTy . getVectorElementType ( ) . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SelectBaseMVE_VMLLDAV ( N , Predicated , OpcodesS , OpcodesU , <NUM_LIT> , <NUM_LIT> ) ;


<s> EVT VecTy = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; assert ( VecTy . getVectorElementType ( ) . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ;

SelectBaseMVE_VMLLDAV ( N , Predicated , OpcodesS , OpcodesU , <NUM_LIT> , <NUM_LIT> ) ;


<s> const MCInstrDesc & MCID = TII -> get ( Use -> getMachineOpcode ( ) ) ; if ( MCID . mayStore ( ) ) return true ; unsigned Opcode = MCID . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; return TII -> isFpMLxInstruction ( Opcode ) ; }


<s> Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrMode2OffsetReg ( SDNode * Op , SDValue N , SDValue & Offset , SDValue & Opc ) { unsigned Opcode = Op -> getOpcode ( ) ; <STR_LIT> AM = ( Opcode == <STR_LIT> ) ? cast < LoadSDNode > ( Op ) -> getAddressingMode ( ) : cast < StoreSDNode > ( Op ) -> getAddressingMode ( ) ; <STR_LIT> AddSub = ( AM == <STR_LIT> || AM == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; int Val ; if ( isScaledConstantInRange ( N , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Val ) ) return false ; const bool restrict_addressing_modes_for_nacl = ( FlagSfiLoad && ( Op -> getOpcode ( ) == <STR_LIT> ) ) || ( FlagSfiStore && ( Op -> getOpcode ( ) == <STR_LIT> ) ) ; Offset = N ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOpcode ( ) ) ; unsigned ShAmt = <NUM_LIT> ; if ( ShOpcVal != <STR_LIT> ) { ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! restrict_addressing_modes_for_nacl && Sh ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( N , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; }


<s> int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC ) , <STR_LIT> ) ; return true ; } if ( restrict_addressing_modes_for_nacl ) { Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ;


<s> Offset = N . getOperand ( <NUM_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { Base = N ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC ) , <STR_LIT> ) ; return true ; } if ( restrict_addressing_modes_for_nacl ) { Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ;


<s> if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; }


assert ( N . getOpcode ( ) == <STR_LIT> ) ;


<s> unsigned Srl_imm = <NUM_LIT> ; if ( isOpcWithIntImmediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , Srl_imm ) ) { assert ( Srl_imm > <NUM_LIT> && Srl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Width = CountTrailingOnes_32 ( And_imm ) - <NUM_LIT> ; unsigned LSB = Srl_imm ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( ( LSB + Width + <NUM_LIT> ) == N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ) { if ( Subtarget -> isThumb ( ) ) { Opc = isSigned ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( LSB , <STR_LIT> ) , getAL ( CurDAG ) , Reg0 , Reg0 } ; return CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , Ops , <NUM_LIT> ) ; } <STR_LIT> ShOpcVal = <STR_LIT> ( <STR_LIT> ) ; SDValue ShOpc = CurDAG -> getTargetConstant ( <STR_LIT> ( ShOpcVal , LSB ) , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , ShOpc , getAL ( CurDAG ) , Reg0 , Reg0 } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) ; } SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( LSB , <STR_LIT> ) , CurDAG -> getTargetConstant ( Width , <STR_LIT> ) , getAL ( CurDAG ) , Reg0 } ; return CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , Ops , <NUM_LIT> ) ; } } return nullptr ; } unsigned Shl_imm = <NUM_LIT> ; if ( isOpcWithIntImmediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , Shl_imm ) ) { assert ( Shl_imm > <NUM_LIT> && Shl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Srl_imm = <NUM_LIT> ; if ( isInt32Immediate ( N -> getOperand ( <NUM_LIT> ) , Srl_imm ) ) { assert ( Srl_imm > <NUM_LIT> && Srl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Width = <NUM_LIT> - Srl_imm - <NUM_LIT> ; int LSB = Srl_imm - Shl_imm ;


<s> if ( Fields . size ( ) > <NUM_LIT> ) { bool AllIntFields = true ; for ( StringRef Field : Fields ) { unsigned IntField ; AllIntFields &= ! Field . trim ( <STR_LIT> ) . getAsInteger ( <NUM_LIT> , IntField ) ; Ops . push_back ( CurDAG -> getTargetConstant ( IntField , DL , <STR_LIT> ) ) ; }


<s> if ( Flags . empty ( ) ) return <NUM_LIT> ;

return StringSwitch < int > ( Flags ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ;


<s> static inline int getMClassFlagsMask ( StringRef Flags ) {

if ( Flags . empty ( ) ) return <NUM_LIT> ;


<s> } int Mask = getMClassFlagsMask ( Flags ) ; if ( ( SYSmvalue < <NUM_LIT> && Mask == - <NUM_LIT> ) || ( SYSmvalue > <NUM_LIT> && ! Flags . empty ( ) ) ) return - <NUM_LIT> ;

if ( ! Subtarget -> hasThumb2DSP ( ) && ( Mask & <NUM_LIT> ) ) return - <NUM_LIT> ;


<s> SDValue CPTmp2 ; if ( isThumb2 ) { if ( SelectT2ShifterOperandReg ( N0 , CPTmp0 , CPTmp1 ) ) continue ; } else { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) || SelectRegShifterOperand ( N0 , CPTmp0 , CPTmp1 , CPTmp2 ) ) continue ; } Srl = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Srl ) , <STR_LIT> , Srl . getOperand ( <NUM_LIT> ) , CurDAG -> getConstant ( Srl_imm + TZ , SDLoc ( Srl ) , <STR_LIT> ) ) ; N1 = CurDAG -> getNode ( <STR_LIT> , SDLoc ( N1 ) , <STR_LIT> , Srl , CurDAG -> getConstant ( And_imm , SDLoc ( Srl ) , <STR_LIT> ) ) ;

N1 = CurDAG -> getNode ( <STR_LIT> , SDLoc ( N1 ) , <STR_LIT> , N1 , CurDAG -> getConstant ( TZ , SDLoc ( Srl ) , <STR_LIT> ) ) ;


<s> BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ; ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! RHS ) return false ; ShImmVal = RHS -> getZExtValue ( ) & <NUM_LIT> ;

Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( ShOpcVal , ShImmVal ) , SDLoc ( N ) , <STR_LIT> ) ;


<s> if ( ! RHS ) return false ; ShImmVal = RHS -> getZExtValue ( ) & <NUM_LIT> ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( ShOpcVal , ShImmVal ) , SDLoc ( N ) , <STR_LIT> ) ;


<s> return true ; } } } } if ( N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> && ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; if ( N . getOpcode ( ) == <STR_LIT> || N . getOpcode ( ) == <STR_LIT> ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) return false ; } <STR_LIT> AddSub = N . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( Offset , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } if ( N . getOpcode ( ) != <STR_LIT> && ShOpcVal == <STR_LIT> && ! ( Subtarget -> isLikeA9 ( ) || Subtarget -> isSwift ( ) || N . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) { ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( N . getOperand ( <NUM_LIT> ) , ShOpcVal , ShAmt ) ) { Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Base = N . getOperand ( <NUM_LIT> ) ; } else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectT2AddrModeSoReg ( SDValue N , SDValue & Base , SDValue & OffReg , SDValue & ShImm ) { if ( N . getOpcode ( ) != <STR_LIT> && ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) return false ; else if ( RHSC < <NUM_LIT> && RHSC >= - <NUM_LIT> ) return false ; } unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; OffReg = N . getOperand ( <NUM_LIT> ) ; <STR_LIT> ShOpcVal = <STR_LIT> ( OffReg . getOpcode ( ) ) ; if ( ShOpcVal != <STR_LIT> ) { ShOpcVal = <STR_LIT> ( Base . getOpcode ( ) ) ; if ( ShOpcVal == <STR_LIT> ) std :: swap ( Base , OffReg ) ; } if ( ShOpcVal == <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( OffReg . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( ShAmt < <NUM_LIT> && isShifterOpProfitable ( OffReg , ShOpcVal , ShAmt ) ) OffReg = OffReg . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; }


<s> if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) return false ; else if ( RHSC < <NUM_LIT> && RHSC >= - <NUM_LIT> ) return false ; } unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; OffReg = N . getOperand ( <NUM_LIT> ) ; <STR_LIT> ShOpcVal = <STR_LIT> ( OffReg . getOpcode ( ) ) ; if ( ShOpcVal != <STR_LIT> ) { ShOpcVal = <STR_LIT> ( Base . getOpcode ( ) ) ; if ( ShOpcVal == <STR_LIT> ) std :: swap ( Base , OffReg ) ; } if ( ShOpcVal == <STR_LIT> ) {

if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( OffReg . getOperand ( <NUM_LIT> ) ) ) {


<s> bool <ISA_LIT>DAGToDAGISel :: SelectT2ShifterOperandReg ( SDValue N , SDValue & BaseReg , SDValue & Opc ) { if ( DisableShifterOp ) return false ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOpcode ( ) ) ; if ( ShOpcVal == <STR_LIT> ) return false ; BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { ShImmVal = RHS -> getZExtValue ( ) & <NUM_LIT> ; Opc = getI32Imm ( <STR_LIT> ( ShOpcVal , ShImmVal ) , SDLoc ( N ) ) ;


<s> Addr = N ; Update = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ;

Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( false ) , <STR_LIT> ) ;


<s> uint32_t C = isC ? cast < ConstantSDNode > ( Size ) -> getZExtValue ( ) : ~ <NUM_LIT> ; if ( C <= <NUM_LIT> && ( ( C & <NUM_LIT> ) == <NUM_LIT> ) ) return CurDAG -> SelectNodeTo ( N , <STR_LIT> , VT , <STR_LIT> , SP , CurDAG -> getTargetConstant ( C / <NUM_LIT> , <STR_LIT> ) , Chain ) ; if ( Subtarget -> isThumb1Only ( ) ) { return CurDAG -> SelectNodeTo ( N , <STR_LIT> , VT , <STR_LIT> , SP , Size , Chain ) ; } else if ( Subtarget -> isThumb2 ( ) ) { if ( isC && Predicate_t2_so_imm ( Size . getNode ( ) ) ) { SDValue Ops [ ] = { SP , CurDAG -> getTargetConstant ( C , <STR_LIT> ) , Chain } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , VT , <STR_LIT> , Ops , <NUM_LIT> ) ; } else if ( isC && Predicate_imm0_4095 ( Size . getNode ( ) ) ) { SDValue Ops [ ] = { SP , CurDAG -> getTargetConstant ( C , <STR_LIT> ) , Chain } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , VT , <STR_LIT> , Ops , <NUM_LIT> ) ; } else {

SDValue Ops [ ] = { SP , Size , getI32Imm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) , Chain } ;


<s> ResTys . push_back ( <STR_LIT> ) ; return CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops , <NUM_LIT> ) ; } EVT RegVT = GetNEONSubregVT ( VT ) ; if ( NumVecs == <NUM_LIT> ) { unsigned Opc = QOpcodes0 [ OpcodeIndex ] ; const SDValue Ops [ ] = { MemAddr , MemUpdate , MemOpc , Align , Pred , PredReg , Chain } ; std :: vector < EVT > ResTys ( <NUM_LIT> , VT ) ; ResTys . push_back ( <STR_LIT> ) ; SDNode * VLd = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops , <NUM_LIT> ) ; Chain = SDValue ( VLd , <NUM_LIT> ) ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) { SDNode * Q = PairDRegs ( VT , SDValue ( VLd , <NUM_LIT> * Vec ) , SDValue ( VLd , <NUM_LIT> * Vec + <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N , Vec ) , SDValue ( Q , <NUM_LIT> ) ) ; } } else { MemOpc = CurDAG -> getTargetConstant ( <STR_LIT> ( true ) , <STR_LIT> ) ; std :: vector < EVT > ResTys ( NumVecs , RegVT ) ; ResTys . push_back ( MemAddr . getValueType ( ) ) ;


<s> NumElts = RegVT . getVectorNumElements ( ) ; SubregIdx = ( Lane < NumElts ) ? <STR_LIT> : <STR_LIT> ; } unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } SDValue Pred = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue PredReg = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( MemUpdate ) ; Ops . push_back ( MemOpc ) ; Ops . push_back ( Align ) ; unsigned Opc = <NUM_LIT> ; if ( is64BitVector ) { Opc = DOpcodes [ OpcodeIndex ] ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) Ops . push_back ( N -> getOperand ( Vec + <NUM_LIT> ) ) ; } else { if ( Lane < NumElts ) { Opc = QOpcodes0 [ OpcodeIndex ] ; } else { Lane -= NumElts ; Opc = QOpcodes1 [ OpcodeIndex ] ; } for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) Ops . push_back ( CurDAG -> getTargetExtractSubreg ( SubregIdx , dl , RegVT , N -> getOperand ( Vec + <NUM_LIT> ) ) ) ; } Ops . push_back ( getI32Imm ( Lane ) ) ; Ops . push_back ( Pred ) ; Ops . push_back ( PredReg ) ; Ops . push_back ( Chain ) ; if ( ! IsLoad ) return CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops . data ( ) , NumVecs + <NUM_LIT> ) ; std :: vector < EVT > ResTys ( NumVecs , RegVT ) ; ResTys . push_back ( <STR_LIT> ) ; SDNode * VLdLn = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops . data ( ) , NumVecs + <NUM_LIT> ) ; if ( is64BitVector ) return VLdLn ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) {

SDValue QuadVec = CurDAG -> getTargetInsertSubreg ( SubregIdx , dl , VT , N -> getOperand ( Vec + <NUM_LIT> ) , SDValue ( VLdLn , Vec ) ) ;


<s> DebugLoc dl = N -> getDebugLoc ( ) ; SDValue MemAddr , Align ; unsigned AddrOpIdx = isUpdating ? <NUM_LIT> : <NUM_LIT> ; if ( ! SelectAddrMode6 ( N , N -> getOperand ( AddrOpIdx ) , MemAddr , Align ) ) return NULL ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; bool is64BitVector = VT . is64BitVector ( ) ; Align = GetVLDSTAlign ( Align , NumVecs , is64BitVector ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; assert ( NumVecs == <NUM_LIT> && <STR_LIT> ) ; break ; } EVT ResTy ; if ( NumVecs == <NUM_LIT> ) ResTy = VT ; else { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ; } std :: vector < EVT > ResTys ; ResTys . push_back ( ResTy ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDNode * VLd ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( ( NumVecs == <NUM_LIT> || NumVecs == <NUM_LIT> ) && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs != <NUM_LIT> && NumVecs != <NUM_LIT> && Opc != <STR_LIT> ) || ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ;


<s> Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( NumVecs <= <NUM_LIT> && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs > <NUM_LIT> && Opc != <STR_LIT> ) || ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( SrcReg ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; SDNode * VSt = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops . data ( ) , Ops . size ( ) ) ; cast < MachineSDNode > ( VSt ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; return VSt ; } SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue RegSeq = SDValue ( QuadQRegs ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , Reg0 , RegSeq , Pred , Reg0 , Chain } ; SDNode * VStA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , MemAddr . getValueType ( ) , <STR_LIT> , OpsA , <NUM_LIT> ) ; cast < MachineSDNode > ( VStA ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; Chain = SDValue ( VStA , <NUM_LIT> ) ; Ops . push_back ( SDValue ( VStA , <NUM_LIT> ) ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; assert ( isa < ConstantSDNode > ( Inc . getNode ( ) ) && <STR_LIT> ) ;


<s> } } if ( N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> && ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; if ( N . getOpcode ( ) == <STR_LIT> || N . getOpcode ( ) == <STR_LIT> ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) return false ; } if ( Subtarget -> isCortexA9 ( ) && ! N . hasOneUse ( ) ) return false ; <STR_LIT> AddSub = N . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) ) ; unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( Offset , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } if ( N . getOpcode ( ) != <STR_LIT> && ShOpcVal == <STR_LIT> && ! ( Subtarget -> isCortexA9 ( ) || N . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) { ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) ) ;


<s> return false ; } unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; OffReg = N . getOperand ( <NUM_LIT> ) ; <STR_LIT> ShOpcVal = <STR_LIT> ( OffReg ) ; if ( ShOpcVal != <STR_LIT> ) { ShOpcVal = <STR_LIT> ( Base ) ; if ( ShOpcVal == <STR_LIT> ) std :: swap ( Base , OffReg ) ; } if ( ShOpcVal == <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( OffReg . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( ShAmt < <NUM_LIT> && isShifterOpProfitable ( OffReg , ShOpcVal , ShAmt ) ) OffReg = OffReg . getOperand ( <NUM_LIT> ) ; else {


<s> if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDNode * VLd ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLd = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops . data ( ) , Ops . size ( ) ) ; } else { EVT AddrTy = MemAddr . getValueType ( ) ; SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , ResTy ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , Reg0 , ImplDef , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTy , AddrTy , <STR_LIT> , OpsA , <NUM_LIT> ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; Ops . push_back ( SDValue ( VLdA , <NUM_LIT> ) ) ; Ops . push_back ( Align ) ;


<s> unsigned Lane = cast < ConstantSDNode > ( N -> getOperand ( Vec0Idx + NumVecs ) ) -> getZExtValue ( ) ; EVT VT = N -> getOperand ( Vec0Idx ) . getValueType ( ) ; bool is64BitVector = VT . is64BitVector ( ) ; unsigned Alignment = <NUM_LIT> ; if ( NumVecs != <NUM_LIT> ) { Alignment = cast < ConstantSDNode > ( Align ) -> getZExtValue ( ) ; unsigned NumBytes = NumVecs * VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( Alignment > NumBytes ) Alignment = NumBytes ; if ( Alignment < <NUM_LIT> && Alignment < NumBytes ) Alignment = <NUM_LIT> ; Alignment = ( Alignment & - Alignment ) ; if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; } Align = CurDAG -> getTargetConstant ( Alignment , <STR_LIT> ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } std :: vector < EVT > ResTys ; if ( IsLoad ) { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ;


<s> DebugLoc dl = N -> getDebugLoc ( ) ; SDValue MemAddr , Align ; unsigned AddrOpIdx = isUpdating ? <NUM_LIT> : <NUM_LIT> ; unsigned Vec0Idx = <NUM_LIT> ; if ( ! SelectAddrMode6 ( N , N -> getOperand ( AddrOpIdx ) , MemAddr , Align ) ) return NULL ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getOperand ( Vec0Idx ) . getValueType ( ) ; bool is64BitVector = VT . is64BitVector ( ) ; Align = GetVLDSTAlign ( Align , NumVecs , is64BitVector ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; assert ( NumVecs == <NUM_LIT> && <STR_LIT> ) ; break ; } std :: vector < EVT > ResTys ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { SDValue SrcReg ; if ( NumVecs == <NUM_LIT> ) { SrcReg = N -> getOperand ( Vec0Idx ) ; } else if ( is64BitVector ) { SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) SrcReg = SDValue ( PairDRegs ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( QuadDRegs ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } } else { SDValue Q0 = N -> getOperand ( Vec0Idx ) ; SDValue Q1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( PairQRegs ( <STR_LIT> , Q0 , Q1 ) , <NUM_LIT> ) ; } unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ;

Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ;


<s> unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( SrcReg ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; return CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops . data ( ) , Ops . size ( ) ) ; } SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue RegSeq = SDValue ( QuadQRegs ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , Reg0 , RegSeq , Pred , Reg0 , Chain } ; SDNode * VStA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , MemAddr . getValueType ( ) , <STR_LIT> , OpsA , <NUM_LIT> ) ; Chain = SDValue ( VStA , <NUM_LIT> ) ; Ops . push_back ( SDValue ( VStA , <NUM_LIT> ) ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; assert ( isa < ConstantSDNode > ( Inc . getNode ( ) ) && <STR_LIT> ) ; ( void ) Inc ; Ops . push_back ( Reg0 ) ; } Ops . push_back ( RegSeq ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; return CurDAG -> getMachineNode ( QOpcodes1 [ OpcodeIndex ] , dl , ResTys , Ops . data ( ) , Ops . size ( ) ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; }


<s> } else { if ( <STR_LIT> ( Val ) != - <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( ~ Val ) != - <NUM_LIT> ) return <NUM_LIT> ; if ( Subtarget -> hasV6T2Ops ( ) && Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return <NUM_LIT> ; }

if ( Subtarget -> useMovt ( * MF ) ) return <NUM_LIT> ;


<s> } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ; return AM2_BASE ; } if ( N . getOpcode ( ) != <STR_LIT> ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC , <STR_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ; return AM2_BASE ; } } if ( ( Subtarget -> isLikeA9 ( ) || Subtarget -> isSwift ( ) ) && ! N . hasOneUse ( ) ) { Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ; return AM2_BASE ; } <STR_LIT> AddSub = N . getOpcode ( ) != <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( Offset , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ;


<s> Base = N ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC ) , SDLoc ( N ) , <STR_LIT> ) ;


<s> Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ;


<s> } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getSExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC > - <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , SDLoc ( N ) , <STR_LIT> ) ; return true ; } } Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ;


<s> if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getSExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC > - <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ;

if ( Base . getOpcode ( ) == <STR_LIT> ) {


<s> if ( RHSC > <NUM_LIT> || RHSC % <NUM_LIT> != <NUM_LIT> ) return true ; Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC / <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ;


<s> if ( N . getOpcode ( ) != <STR_LIT> || ! CurDAG -> isBaseWithConstantOffset ( N ) ) return true ; ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! RHS ) return true ; uint32_t RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( RHSC > <NUM_LIT> || RHSC % <NUM_LIT> != <NUM_LIT> ) return true ; Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC / <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ;


<s> OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) return false ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) {

if ( SelectT2AddrModeImm8 ( N , Base , OffImm ) ) return false ;


<s> if ( ( RHSC >= - <NUM_LIT> ) && ( RHSC < <NUM_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ;


<s> Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; RegisterSDNode * LHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || ( LHSR && LHSR -> getReg ( ) == <STR_LIT> ) ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; MachineFrameInfo * MFI = MF -> getFrameInfo ( ) ; if ( MFI -> getObjectAlignment ( FI ) < <NUM_LIT> ) MFI -> setObjectAlignment ( FI , <NUM_LIT> ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , SDLoc ( N ) , <STR_LIT> ) ; return true ; } }


<s> static inline int getMClassFlagsMask ( StringRef Flags , bool hasThumb2DSP ) { if ( Flags . empty ( ) ) return <NUM_LIT> | ( int ) hasThumb2DSP ;


<s> int SYSmvalue = getMClassRegisterSYSmValueMask ( Reg ) ; if ( SYSmvalue == - <NUM_LIT> ) return - <NUM_LIT> ; if ( ! Subtarget -> hasV7Ops ( ) && SYSmvalue >= <NUM_LIT> && SYSmvalue <= <NUM_LIT> ) return - <NUM_LIT> ; if ( IsRead ) { assert ( Flags . empty ( ) && <STR_LIT> ) ; return SYSmvalue ; } int Mask = getMClassFlagsMask ( Flags , Subtarget -> hasThumb2DSP ( ) ) ; if ( ( SYSmvalue < <NUM_LIT> && Mask == - <NUM_LIT> ) || ( SYSmvalue > <NUM_LIT> && ! Flags . empty ( ) ) ) return - <NUM_LIT> ; if ( ! Subtarget -> hasThumb2DSP ( ) && ( Mask & <NUM_LIT> ) ) return - <NUM_LIT> ; if ( SYSmvalue < <NUM_LIT> ) return SYSmvalue | Mask << <NUM_LIT> ; return SYSmvalue ;


<s> return SYSmvalue ; } int Mask = getMClassFlagsMask ( Flags , Subtarget -> hasThumb2DSP ( ) ) ; if ( ( SYSmvalue < <NUM_LIT> && Mask == - <NUM_LIT> ) || ( SYSmvalue > <NUM_LIT> && ! Flags . empty ( ) ) ) return - <NUM_LIT> ;


<s> SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 } ;

return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT , Ops ) ;


<s> DebugLoc dl = V0 . getNode ( ) -> getDebugLoc ( ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ;

const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 } ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: createGPRPairNode ( EVT VT , SDValue V0 , SDValue V1 ) { DebugLoc dl = V0 . getNode ( ) -> getDebugLoc ( ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ;


<s> const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 } ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: createQRegPairNode ( EVT VT , SDValue V0 , SDValue V1 ) { DebugLoc dl = V0 . getNode ( ) -> getDebugLoc ( ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT , Ops ) ;


<s> const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT , Ops ) ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: createQuadDRegsNode ( EVT VT , SDValue V0 , SDValue V1 , SDValue V2 , SDValue V3 ) { DebugLoc dl = V0 . getNode ( ) -> getDebugLoc ( ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ;

SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ;


<s> SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 , V2 , SubReg2 , V3 , SubReg3 } ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: createQuadQRegsNode ( EVT VT , SDValue V0 , SDValue V1 , SDValue V2 , SDValue V3 ) { DebugLoc dl = V0 . getNode ( ) -> getDebugLoc ( ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ;

SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ;


<s> unsigned Opcode = <NUM_LIT> ; bool Match = false ; if ( LoadedVT == <STR_LIT> && isPre && SelectAddrMode2OffsetImmPre ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Opcode = <STR_LIT> ; Match = true ; } else if ( LoadedVT == <STR_LIT> && ! isPre && SelectAddrMode2OffsetImm ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Opcode = <STR_LIT> ; Match = true ; } else if ( LoadedVT == <STR_LIT> && SelectAddrMode2OffsetReg ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Opcode = isPre ? <STR_LIT> : <STR_LIT> ; Match = true ; } else if ( LoadedVT == <STR_LIT> && SelectAddrMode3Offset ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = ( LD -> getExtensionType ( ) == <STR_LIT> ) ? ( isPre ? <STR_LIT> : <STR_LIT> ) : ( isPre ? <STR_LIT> : <STR_LIT> ) ; } else if ( LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) { if ( LD -> getExtensionType ( ) == <STR_LIT> ) { if ( SelectAddrMode3Offset ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } } else { if ( isPre && SelectAddrMode2OffsetImmPre ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = <STR_LIT> ; } else if ( ! isPre && SelectAddrMode2OffsetImm ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = <STR_LIT> ; } else if ( SelectAddrMode2OffsetReg ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = isPre ? <STR_LIT> : <STR_LIT> ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectAtomic64 ( SDNode * Node , unsigned Opc ) { SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; if ( Opc == <STR_LIT> ) { Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; }


<s> MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( Node ) -> getMemOperand ( ) ; SDNode * ResNode = CurDAG -> getMachineNode ( Opc , Node -> getDebugLoc ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> , Ops ) ; cast < MachineSDNode > ( ResNode ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; return ResNode ;


<s> SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; bool is64BitVector = VT . is64BitVector ( ) ; Align = GetVLDSTAlign ( Align , NumVecs , is64BitVector ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; assert ( NumVecs == <NUM_LIT> && <STR_LIT> ) ; break ; } EVT ResTy ; if ( NumVecs == <NUM_LIT> ) ResTy = VT ; else { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ; } std :: vector < EVT > ResTys ; ResTys . push_back ( ResTy ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDNode * VLd ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( ( NumVecs == <NUM_LIT> || NumVecs == <NUM_LIT> ) && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs != <NUM_LIT> && NumVecs != <NUM_LIT> && Opc != <STR_LIT> ) || ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ;


<s> MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned Alignment = <NUM_LIT> ; if ( NumVecs != <NUM_LIT> ) { Alignment = cast < ConstantSDNode > ( Align ) -> getZExtValue ( ) ; unsigned NumBytes = NumVecs * VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( Alignment > NumBytes ) Alignment = NumBytes ; if ( Alignment < <NUM_LIT> && Alignment < NumBytes ) Alignment = <NUM_LIT> ; Alignment = ( Alignment & - Alignment ) ; if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; } Align = CurDAG -> getTargetConstant ( Alignment , <STR_LIT> ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDValue SuperReg ; unsigned Opc = Opcodes [ OpcodeIndex ] ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) {

SDValue Inc = N -> getOperand ( <NUM_LIT> ) ;


<s> SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) { if ( is64BitVector ) SuperReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; } else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( is64BitVector ) SuperReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQuadQRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } Ops . push_back ( SuperReg ) ; Ops . push_back ( getI32Imm ( Lane ) ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes [ OpcodeIndex ] ) ; SDNode * VLdLn = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; cast < MachineSDNode > ( VLdLn ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; if ( ! IsLoad ) return VLdLn ; SuperReg = SDValue ( VLdLn , <NUM_LIT> ) ; assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> && <STR_LIT> == <STR_LIT> + <NUM_LIT> && <STR_LIT> ) ; unsigned Sub0 = is64BitVector ? <STR_LIT> : <STR_LIT> ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) ReplaceUses ( SDValue ( N , Vec ) , CurDAG -> getTargetExtractSubreg ( Sub0 + Vec , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( VLdLn , <NUM_LIT> ) ) ; if ( isUpdating ) ReplaceUses ( SDValue ( N , NumVecs + <NUM_LIT> ) , SDValue ( VLdLn , <NUM_LIT> ) ) ; return NULL ;


<s> unsigned NumBytes = NumVecs * VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( Alignment > NumBytes ) Alignment = NumBytes ; if ( Alignment < <NUM_LIT> && Alignment < NumBytes ) Alignment = <NUM_LIT> ; Alignment = ( Alignment & - Alignment ) ; if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; } Align = CurDAG -> getTargetConstant ( Alignment , <STR_LIT> ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } std :: vector < EVT > ResTys ; if ( IsLoad ) { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } SDValue SuperReg ; SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ;


<s> std :: vector < EVT > ResTys ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { SDValue SrcReg ; if ( NumVecs == <NUM_LIT> ) { SrcReg = N -> getOperand ( Vec0Idx ) ; } else if ( is64BitVector ) { SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) SrcReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } } else { SDValue Q0 = N -> getOperand ( Vec0Idx ) ; SDValue Q1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQRegPairNode ( <STR_LIT> , Q0 , Q1 ) , <NUM_LIT> ) ; } unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( NumVecs <= <NUM_LIT> && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs > <NUM_LIT> && Opc != <STR_LIT> ) || ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( SrcReg ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; SDNode * VSt = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; cast < MachineSDNode > ( VSt ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; return VSt ; } SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ;


<s> if ( NumVecs == <NUM_LIT> ) RegSeq = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else { SDValue V2 = N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; RegSeq = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; }

SmallVector < SDValue , <NUM_LIT> > Ops ;


<s> if ( Use -> isMachineOpcode ( ) ) { const MCInstrDesc & MCID = TII -> get ( Use -> getMachineOpcode ( ) ) ; if ( MCID . mayStore ( ) ) return true ; unsigned Opcode = MCID . getOpcode ( ) ;

if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ;


<s> if ( ! N -> hasOneUse ( ) ) return false ; SDNode * Use = * N -> use_begin ( ) ; if ( Use -> getOpcode ( ) == <STR_LIT> ) return true ; if ( Use -> isMachineOpcode ( ) ) { const MCInstrDesc & MCID = TII -> get ( Use -> getMachineOpcode ( ) ) ; if ( MCID . mayStore ( ) ) return true ; unsigned Opcode = MCID . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ;

return TII -> isFpMLxInstruction ( Opcode ) ;


<s> Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getSExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC > - <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ; return true ;


<s> if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; } else Base = N ;


<s> if ( Subtarget -> isThumb1Only ( ) ) return NULL ; if ( XORSrc0 . getOpcode ( ) != <STR_LIT> || XORSrc1 . getOpcode ( ) != <STR_LIT> ) return NULL ; SDValue ADDSrc0 = XORSrc0 . getOperand ( <NUM_LIT> ) ; SDValue ADDSrc1 = XORSrc0 . getOperand ( <NUM_LIT> ) ; SDValue SRASrc0 = XORSrc1 . getOperand ( <NUM_LIT> ) ; SDValue SRASrc1 = XORSrc1 . getOperand ( <NUM_LIT> ) ; ConstantSDNode * SRAConstant = dyn_cast < ConstantSDNode > ( SRASrc1 ) ; EVT XType = SRASrc0 . getValueType ( ) ; unsigned Size = XType . getSizeInBits ( ) - <NUM_LIT> ; if ( ADDSrc1 == XORSrc1 && ADDSrc0 == SRASrc0 && XType . isInteger ( ) && SRAConstant != NULL && Size == SRAConstant -> getZExtValue ( ) ) { unsigned Opcode = <STR_LIT> ; if ( Subtarget -> isThumb2 ( ) ) Opcode = <STR_LIT> ; return CurDAG -> SelectNodeTo ( N , Opcode , VT , ADDSrc0 ) ; }


<s> if ( Subtarget -> isThumb ( ) ) { if ( Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( Subtarget -> hasV6T2Ops ( ) && ( Val <= <NUM_LIT> || <STR_LIT> ( Val ) != - <NUM_LIT> ) ) return <NUM_LIT> ; if ( Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( ~ Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return <NUM_LIT> ; } else {

if ( <STR_LIT> ( Val ) != - <NUM_LIT> ) return <NUM_LIT> ;


<s> switch ( Flag ) { case 'c' : FlagVal = <NUM_LIT> ; break ; case 'x' : FlagVal = <NUM_LIT> ; break ; case 's' : FlagVal = <NUM_LIT> ; break ; case 'f' : FlagVal = <NUM_LIT> ; break ; default : FlagVal = <NUM_LIT> ; } if ( ! FlagVal || ( Mask & FlagVal ) ) return - <NUM_LIT> ;


<s> if ( ! TheReg ) return - <NUM_LIT> ; return TheReg -> Encoding ;


<s> unsigned FirstOne = A . getBitWidth ( ) - A . countLeadingZeros ( ) - <NUM_LIT> ;

unsigned LastOne = A . countTrailingZeros ( ) ;


<s> unsigned LastOne = A . countTrailingZeros ( ) ; if ( A . countPopulation ( ) != ( FirstOne - LastOne + <NUM_LIT> ) ) return Optional < std :: pair < unsigned , unsigned >> ( ) ;

return std :: make_pair ( FirstOne , LastOne ) ;


<s> inline SDValue getI32Imm ( unsigned Imm , const SDLoc & dl ) { return CurDAG -> getTargetConstant ( Imm , dl , <STR_LIT> ) ;


<s> for ( StringRef Field : Fields ) { unsigned IntField ; AllIntFields &= ! Field . trim ( <STR_LIT> ) . getAsInteger ( <NUM_LIT> , IntField ) ; Ops . push_back ( CurDAG -> getTargetConstant ( IntField , DL , <STR_LIT> ) ) ; } assert ( AllIntFields && <STR_LIT> ) ;


<s> SmallVector < StringRef , <NUM_LIT> > Fields ; RegString . split ( Fields , ':' ) ; if ( Fields . size ( ) > <NUM_LIT> ) { bool AllIntFields = true ; for ( StringRef Field : Fields ) { unsigned IntField ; AllIntFields &= ! Field . trim ( <STR_LIT> ) . getAsInteger ( <NUM_LIT> , IntField ) ; Ops . push_back ( CurDAG -> getTargetConstant ( IntField , DL , <STR_LIT> ) ) ; } assert ( AllIntFields && <STR_LIT> ) ; }


<s> if ( ! TheReg || ! TheReg -> hasRequiredFeatures ( FeatureBits ) ) return - <NUM_LIT> ;

return ( int ) ( TheReg -> Encoding & <NUM_LIT> ) ;


<s> static int getMClassRegisterMask ( StringRef Reg , const <ISA_LIT>Subtarget * Subtarget ) { auto TheReg = <STR_LIT> ( Reg ) ; const FeatureBitset & FeatureBits = Subtarget -> getFeatureBits ( ) ; if ( ! TheReg || ! TheReg -> hasRequiredFeatures ( FeatureBits ) ) return - <NUM_LIT> ; return ( int ) ( TheReg -> Encoding & <NUM_LIT> ) ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> SDValue <ISA_LIT>DAGToDAGISel :: GetVLDSTAlign ( SDValue Align , const SDLoc & dl , unsigned NumVecs , bool is64BitVector ) { unsigned NumRegs = NumVecs ; if ( ! is64BitVector && NumVecs < <NUM_LIT> ) NumRegs *= <NUM_LIT> ; unsigned Alignment = cast < ConstantSDNode > ( Align ) -> getZExtValue ( ) ; if ( Alignment >= <NUM_LIT> && NumRegs == <NUM_LIT> ) Alignment = <NUM_LIT> ; else if ( Alignment >= <NUM_LIT> && ( NumRegs == <NUM_LIT> || NumRegs == <NUM_LIT> ) ) Alignment = <NUM_LIT> ; else if ( Alignment >= <NUM_LIT> ) Alignment = <NUM_LIT> ; else Alignment = <NUM_LIT> ;

return CurDAG -> getTargetConstant ( Alignment , dl , <STR_LIT> ) ;


<s> else if ( Alignment >= <NUM_LIT> && ( NumRegs == <NUM_LIT> || NumRegs == <NUM_LIT> ) ) Alignment = <NUM_LIT> ; else if ( Alignment >= <NUM_LIT> ) Alignment = <NUM_LIT> ; else Alignment = <NUM_LIT> ; return CurDAG -> getTargetConstant ( Alignment , dl , <STR_LIT> ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> const <ISA_LIT>BaseInstrInfo * TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( CurDAG -> getSubtarget ( ) . getInstrInfo ( ) ) ; const MCInstrDesc & MCID = TII -> get ( Use -> getMachineOpcode ( ) ) ; if ( MCID . mayStore ( ) ) return true ; unsigned Opcode = MCID . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; return TII -> isFpMLxInstruction ( Opcode ) ; }


<s> const <ISA_LIT>BaseInstrInfo * TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( CurDAG -> getSubtarget ( ) . getInstrInfo ( ) ) ; const MCInstrDesc & MCID = TII -> get ( Use -> getMachineOpcode ( ) ) ; if ( MCID . mayStore ( ) ) return true ; unsigned Opcode = MCID . getOpcode ( ) ;


<s> static bool isPerfectIncrement ( SDValue Inc , EVT VecTy , unsigned NumVecs ) { auto C = dyn_cast < ConstantSDNode > ( Inc ) ; return C && C -> getZExtValue ( ) == VecTy . getSizeInBits ( ) / <NUM_LIT> * NumVecs ;


<s> static bool isPerfectIncrement ( SDValue Inc , EVT VecTy , unsigned NumVecs ) { auto C = dyn_cast < ConstantSDNode > ( Inc ) ;

return C && C -> getZExtValue ( ) == VecTy . getSizeInBits ( ) / <NUM_LIT> * NumVecs ;


<s> case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ;


<s> case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ;


<s> CurDAG -> RepositionNode ( N . getNode ( ) -> getIterator ( ) , M . getNode ( ) ) ;


<s> void <ISA_LIT>DAGToDAGISel :: replaceDAGValue ( const SDValue & N , SDValue M ) { CurDAG -> RepositionNode ( N . getNode ( ) -> getIterator ( ) , M . getNode ( ) ) ;


<s> assert ( Parent -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; Out = N ; return CurDAG -> haveNoCommonBitsSet ( N , Parent -> getOperand ( <NUM_LIT> ) ) ;


<s> int Lwb = - <NUM_LIT> + <NUM_LIT> ; int Upb = <NUM_LIT> ; return IsAddressingMode5 ( N , Base , Offset , Lwb , Upb , false ) ;


<s> int Lwb = - <NUM_LIT> + <NUM_LIT> ; int Upb = <NUM_LIT> ;

return IsAddressingMode5 ( N , Base , Offset , Lwb , Upb , true ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrMode5FP16 ( SDValue N , SDValue & Base , SDValue & Offset ) { int Lwb = - <NUM_LIT> + <NUM_LIT> ; int Upb = <NUM_LIT> ;


<s> } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getSExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC > - <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ;


<s> if ( ! And -> hasOneUse ( ) ) return ; SDValue Zero = N -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Zero ) || ! cast < ConstantSDNode > ( Zero ) -> isNullValue ( ) || And -> getOpcode ( ) != <STR_LIT> ) return ; SDValue X = And . getOperand ( <NUM_LIT> ) ; auto C = dyn_cast < ConstantSDNode > ( And . getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return ; auto Range = getContiguousRangeOfSetBits ( C -> getAPIntValue ( ) ) ; if ( ! Range ) return ; SDNode * NewN ; SDLoc dl ( N ) ; auto EmitShift = [ & ] ( unsigned Opc , SDValue Src , unsigned Imm ) -> SDNode * { if ( Subtarget -> isThumb2 ( ) ) { Opc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { Src , CurDAG -> getTargetConstant ( Imm , dl , <STR_LIT> ) , getAL ( CurDAG , dl ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) } ; return CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops ) ;


<s> else if ( MemTy == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( MemTy == <STR_LIT> ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * CmpSwap = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) , Ops ) ;

MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectImmShifterOperand ( SDValue N , SDValue & BaseReg , SDValue & Opc , bool CheckProfitability ) { if ( DisableShifterOp ) return false ; if ( N . getOpcode ( ) == <STR_LIT> ) { unsigned PowerOfTwo = <NUM_LIT> ; SDValue NewMulConst ; if ( canExtractShiftFromMul ( N , <NUM_LIT> , PowerOfTwo , NewMulConst ) ) { HandleSDNode Handle ( N ) ; SDLoc Loc ( N ) ; replaceDAGValue ( N . getOperand ( <NUM_LIT> ) , NewMulConst ) ; BaseReg = Handle . getValue ( ) ;

Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , PowerOfTwo ) , Loc , <STR_LIT> ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Constraint_i : LLVM_FALLTHROUGH ; case InlineAsm :: Constraint_m : case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_Q : case InlineAsm :: Constraint_Um : case InlineAsm :: Constraint_Un : case InlineAsm :: Constraint_Uq : case InlineAsm :: Constraint_Us : case InlineAsm :: Constraint_Ut : case InlineAsm :: Constraint_Uv : case InlineAsm :: Constraint_Uy : OutOps . push_back ( Op ) ;


<s> } if ( isPowerOf2_32 ( RHSC ) ) { unsigned ShAmt = Log2_32 ( RHSC ) ; Base = Offset = N . getOperand ( <NUM_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , ShAmt , <STR_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ; return true ; } } } } if ( N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> && ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; if ( N . getOpcode ( ) == <STR_LIT> || N . getOpcode ( ) == <STR_LIT> ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) return false ; } <STR_LIT> AddSub = N . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( Offset , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } if ( N . getOpcode ( ) != <STR_LIT> && ShOpcVal == <STR_LIT> && ! ( Subtarget -> isLikeA9 ( ) || Subtarget -> isSwift ( ) || N . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) { ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( N . getOperand ( <NUM_LIT> ) , ShOpcVal , ShAmt ) ) { Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Base = N . getOperand ( <NUM_LIT> ) ; } else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } } if ( Offset . getOpcode ( ) == <STR_LIT> && N . hasOneUse ( ) ) { unsigned PowerOfTwo = <NUM_LIT> ; SDValue NewMulConst ; if ( canExtractShiftFromMul ( Offset , <NUM_LIT> , PowerOfTwo , NewMulConst ) ) { HandleSDNode Handle ( Offset ) ; replaceDAGValue ( Offset . getOperand ( <NUM_LIT> ) , NewMulConst ) ; Offset = Handle . getValue ( ) ; ShAmt = PowerOfTwo ;


<s> if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) return false ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { if ( SelectT2AddrModeImm8 ( N , Base , OffImm ) ) return false ; int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) {

int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ;


<s> unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; OffReg = N . getOperand ( <NUM_LIT> ) ; <STR_LIT> ShOpcVal = <STR_LIT> ( OffReg . getOpcode ( ) ) ; if ( ShOpcVal != <STR_LIT> ) { ShOpcVal = <STR_LIT> ( Base . getOpcode ( ) ) ; if ( ShOpcVal == <STR_LIT> ) std :: swap ( Base , OffReg ) ; } if ( ShOpcVal == <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( OffReg . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( ShAmt < <NUM_LIT> && isShifterOpProfitable ( OffReg , ShOpcVal , ShAmt ) ) OffReg = OffReg . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; } } } if ( OffReg . getOpcode ( ) == <STR_LIT> && N . hasOneUse ( ) ) { unsigned PowerOfTwo = <NUM_LIT> ; SDValue NewMulConst ; if ( canExtractShiftFromMul ( OffReg , <NUM_LIT> , PowerOfTwo , NewMulConst ) ) { HandleSDNode Handle ( OffReg ) ; replaceDAGValue ( OffReg . getOperand ( <NUM_LIT> ) , NewMulConst ) ; OffReg = Handle . getValue ( ) ; ShAmt = PowerOfTwo ; }


<s> } OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , Scale , <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; OffImm = CurDAG -> getTargetConstant ( RHSC , SDLoc ( N ) , <STR_LIT> ) ;


<s> } else if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; } else { Base = N ; } OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; }