<s> SDLoc dl ( Op ) ; if ( ( ! Subtarget -> isThumb ( ) && Subtarget -> hasV6Ops ( ) ) || Subtarget -> isThumb2 ( ) ) if ( SDValue SatValue = LowerSaturatingConditional ( Op , DAG ) ) return SatValue ; SDValue LowerSatConstant ; SDValue SatValue ; if ( VT == <STR_LIT> && isLowerSaturatingConditional ( Op , SatValue , LowerSatConstant ) ) { SDValue ShiftV = DAG . getNode ( <STR_LIT> , dl , VT , SatValue , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; if ( isNullConstant ( LowerSatConstant ) ) { SDValue NotShiftV = DAG . getNode ( <STR_LIT> , dl , VT , ShiftV , DAG . getAllOnesConstant ( dl , VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , SatValue , NotShiftV ) ; } else if ( isAllOnesConstant ( LowerSatConstant ) ) return DAG . getNode ( <STR_LIT> , dl , VT , SatValue , ShiftV ) ; } SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; ConstantSDNode * CFVal = dyn_cast < ConstantSDNode > ( FalseVal ) ; ConstantSDNode * CTVal = dyn_cast < ConstantSDNode > ( TrueVal ) ; if ( Subtarget -> hasV8_1MMainlineOps ( ) && CFVal && CTVal && LHS . getValueType ( ) == <STR_LIT> && RHS . getValueType ( ) == <STR_LIT> ) { unsigned TVal = CTVal -> getZExtValue ( ) ; unsigned FVal = CFVal -> getZExtValue ( ) ; unsigned Opcode = <NUM_LIT> ; if ( TVal == ~ FVal ) { Opcode = <STR_LIT> ; } else if ( TVal == ~ FVal + <NUM_LIT> ) { Opcode = <STR_LIT> ; } else if ( TVal + <NUM_LIT> == FVal ) { Opcode = <STR_LIT> ; } else if ( TVal == FVal + <NUM_LIT> ) { Opcode = <STR_LIT> ; std :: swap ( TrueVal , FalseVal ) ; std :: swap ( TVal , FVal ) ; CC = <STR_LIT> ( CC , LHS . getValueType ( ) ) ; }


<s> assert ( LHS . getSimpleValueType ( ) . isInteger ( ) && <STR_LIT> ) ; Carry = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Carry ) ; Carry = ConvertBooleanCarryToCarryFlag ( Carry , DAG ) ; SDVTList VTs = DAG . getVTList ( LHS . getValueType ( ) , <STR_LIT> ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , DL , VTs , LHS , RHS , Carry ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue TVal = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( IntCCTo<ISA_LIT>CC ( cast < CondCodeSDNode > ( Cond ) -> get ( ) ) , DL , <STR_LIT> ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , Cmp . getValue ( <NUM_LIT> ) , SDValue ( ) ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , FVal , TVal , <ISA_LIT>cc , CCR , Chain . getValue ( <NUM_LIT> ) ) ;


<s> SDValue Carry = Op . getOperand ( <NUM_LIT> ) ; SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; assert ( LHS . getSimpleValueType ( ) . isInteger ( ) && <STR_LIT> ) ; Carry = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Carry ) ; Carry = ConvertBooleanCarryToCarryFlag ( Carry , DAG ) ;

SDVTList VTs = DAG . getVTList ( LHS . getValueType ( ) , <STR_LIT> ) ;


<s> SDValue FPSCR = DAG . getNode ( <STR_LIT> , DL , { <STR_LIT> , <STR_LIT> } , Ops ) ; Chain = FPSCR . getValue ( <NUM_LIT> ) ; FPSCR = FPSCR . getValue ( <NUM_LIT> ) ; const unsigned RMMask = ~ ( <STR_LIT> :: rmMask << <STR_LIT> ) ; FPSCR = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FPSCR , DAG . getConstant ( RMMask , DL , <STR_LIT> ) ) ; FPSCR = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FPSCR , RMValue ) ; SDValue Ops2 [ ] = { Chain , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , FPSCR } ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ops2 ) ;


<s> RMValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RMValue , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) ) ; SDValue Ops [ ] = { Chain , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) } ; SDValue FPSCR = DAG . getNode ( <STR_LIT> , DL , { <STR_LIT> , <STR_LIT> } , Ops ) ; Chain = FPSCR . getValue ( <NUM_LIT> ) ; FPSCR = FPSCR . getValue ( <NUM_LIT> ) ; const unsigned RMMask = ~ ( <STR_LIT> :: rmMask << <STR_LIT> ) ; FPSCR = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FPSCR , DAG . getConstant ( RMMask , DL , <STR_LIT> ) ) ; FPSCR = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FPSCR , RMValue ) ; SDValue Ops2 [ ] = { Chain , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , FPSCR } ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ops2 ) ;


<s> assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , false , Cnt ) ) { unsigned VShiftOpc = ( N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; return DAG . getNode ( VShiftOpc , dl , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , dl , <STR_LIT> ) ) ; } EVT ShiftVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue NegatedCount = DAG . getNode ( <STR_LIT> , dl , ShiftVT , getZeroVector ( ShiftVT , DAG , dl ) , N -> getOperand ( <NUM_LIT> ) ) ; unsigned VShiftOpc = ( N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ;

return DAG . getNode ( VShiftOpc , dl , VT , N -> getOperand ( <NUM_LIT> ) , NegatedCount ) ;


<s> SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; assert ( Op . getOpcode ( ) == <STR_LIT> ) ; SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , dl , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , RevShAmt ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; SDValue HiSmallShift = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ;

SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , dl , <STR_LIT> ) ) ;


<s> SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , RevShAmt ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; SDValue HiSmallShift = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , dl , <STR_LIT> ) ) ; SDValue HiBigShift = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ExtraShAmt ) ; SDValue CmpHi = get<ISA_LIT>Cmp ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> , <ISA_LIT>cc , DAG , dl ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , VT , HiSmallShift , HiBigShift , <ISA_LIT>cc , CCR , CmpHi ) ; SDValue CmpLo = get<ISA_LIT>Cmp ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> , <ISA_LIT>cc , DAG , dl ) ; SDValue LoSmallShift = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , LoSmallShift , DAG . getConstant ( <NUM_LIT> , dl , VT ) , <ISA_LIT>cc , CCR , CmpLo ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops , dl ) ;


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , LoSmallShift , LoBigShift , <ISA_LIT>cc , CCR , CmpLo ) ; SDValue HiSmallShift = DAG . getNode ( Opc , dl , VT , ShOpHi , ShAmt ) ; SDValue HiBigShift = Opc == <STR_LIT> ? DAG . getNode ( Opc , dl , VT , ShOpHi , DAG . getConstant ( VTBits - <NUM_LIT> , dl , VT ) ) : DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue CmpHi = get<ISA_LIT>Cmp ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> , <ISA_LIT>cc , DAG , dl ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , VT , HiSmallShift , HiBigShift , <ISA_LIT>cc , CCR , CmpHi ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ;

return DAG . getMergeValues ( Ops , dl ) ;


<s> if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( Op . getValueType ( ) ) ) return SDValue ( ) ; SDValue Value , OverflowCmp ; SDValue <ISA_LIT>cc ; std :: tie ( Value , OverflowCmp ) = get<ISA_LIT>XALUOOp ( Op , DAG , <ISA_LIT>cc ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue TVal = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; EVT VT = Op . getValueType ( ) ; SDValue Overflow = DAG . getNode ( <STR_LIT> , dl , VT , TVal , FVal , <ISA_LIT>cc , CCR , OverflowCmp ) ;

SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ;


<s> SDValue FVal = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; EVT VT = Op . getValueType ( ) ; SDValue Overflow = DAG . getNode ( <STR_LIT> , dl , VT , TVal , FVal , <ISA_LIT>cc , CCR , OverflowCmp ) ;


<s> SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ST -> getValue ( ) , DAG . getTargetConstant ( DAG . getDataLayout ( ) . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , { ST -> getChain ( ) , Lo , Hi , ST -> getBasePtr ( ) } , MemVT , ST -> getMemOperand ( ) ) ;

} else if ( Subtarget -> hasMVEIntegerOps ( ) && ( ( MemVT == <STR_LIT> || MemVT == <STR_LIT> || MemVT == <STR_LIT> ) ) ) {


<s> SDNode * N = Op . getNode ( ) ; SDLoc dl ( N ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ST -> getValue ( ) , DAG . getTargetConstant ( DAG . getDataLayout ( ) . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ST -> getValue ( ) , DAG . getTargetConstant ( DAG . getDataLayout ( ) . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , { ST -> getChain ( ) , Lo , Hi , ST -> getBasePtr ( ) } , MemVT , ST -> getMemOperand ( ) ) ; } else if ( Subtarget -> hasMVEIntegerOps ( ) && ( ( MemVT == <STR_LIT> || MemVT == <STR_LIT> || MemVT == <STR_LIT> ) ) ) { return LowerPredicateStore ( Op , DAG ) ;


<s> SDLoc dl ( GA ) ; SDValue Offset ; SDValue Chain = DAG . getEntryNode ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue ThreadPointer = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; if ( model == TLSModel :: InitialExec ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , Align ( <NUM_LIT> ) ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; Chain = Offset . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ;

Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT , Offset , PICLabel ) ;


<s> EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , Align ( <NUM_LIT> ) ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; SDValue Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Argument ; Entry . Ty = ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ;

CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getInt32Ty ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , std :: move ( Args ) ) ;


<s> if ( ToVT . getScalarType ( ) == <STR_LIT> ) return LowerTruncatei1 ( N , DAG , Subtarget ) ; if ( ToVT != <STR_LIT> && ToVT != <STR_LIT> ) return SDValue ( ) ; EVT FromVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ;

if ( FromVT != <STR_LIT> && FromVT != <STR_LIT> ) return SDValue ( ) ;


<s> if ( ToVT != <STR_LIT> && ToVT != <STR_LIT> ) return SDValue ( ) ; EVT FromVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( FromVT != <STR_LIT> && FromVT != <STR_LIT> ) return SDValue ( ) ; SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = DAG . SplitVectorOperand ( N , <NUM_LIT> ) ;


<s> assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; EVT FromVT = Op . getValueType ( ) ; SDLoc DL ( N ) ; SDValue And = DAG . getNode ( <STR_LIT> , DL , FromVT , Op , DAG . getConstant ( <NUM_LIT> , DL , FromVT ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , And , DAG . getConstant ( <NUM_LIT> , DL , FromVT ) , DAG . getCondCode ( <STR_LIT> ) ) ;


<s> N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = LowerCONCAT_VECTORS ( N0 , DAG , ST ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , N0 ) ; return N0 ; } N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; SDValue BN1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , BN1 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , BN1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ;


<s> N2 = LowerSDIV_v4i16 ( N2 , N3 , dl , DAG ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = LowerCONCAT_VECTORS ( N0 , DAG , ST ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , N0 ) ; return N0 ; } N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; SDValue BN1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , BN1 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , BN1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , BN1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ;


<s> case <STR_LIT> : { Value = DAG . getNode ( <STR_LIT> , dl , VTs , LHS , RHS ) ; Overflow = ConvertCarryFlagToBooleanCarry ( Value . getValue ( <NUM_LIT> ) , VT , DAG ) ; Overflow = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , Overflow ) ; break ; } } return DAG . getNode ( <STR_LIT> , dl , VTs , Value , Overflow ) ;


<s> const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) ) ;


<s> static SDValue LowerVASTART ( SDValue Op , SelectionDAG & DAG ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; SDLoc dl ( Op ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ;

const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;


<s> EVT VT = Op0 . getValueType ( ) ; EVT EltVT = VT . getVectorElementType ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned NumActiveLanes = NumElts ; assert ( ( NumActiveLanes == <NUM_LIT> || NumActiveLanes == <NUM_LIT> || NumActiveLanes == <NUM_LIT> || NumActiveLanes == <NUM_LIT> ) && <STR_LIT> ) ; while ( NumActiveLanes > <NUM_LIT> ) { unsigned RevOpcode = NumActiveLanes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Rev = DAG . getNode ( RevOpcode , dl , VT , Op0 ) ; Op0 = DAG . getNode ( BaseOpcode , dl , VT , Op0 , Rev ) ; NumActiveLanes /= <NUM_LIT> ; } SDValue Res ; if ( NumActiveLanes == <NUM_LIT> ) { SDValue Ext0 = DAG . getNode ( <STR_LIT> , dl , EltVT , Op0 , DAG . getConstant ( <NUM_LIT> * NumElts / <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Ext1 = DAG . getNode ( <STR_LIT> , dl , EltVT , Op0 , DAG . getConstant ( <NUM_LIT> * NumElts / <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Ext2 = DAG . getNode ( <STR_LIT> , dl , EltVT , Op0 , DAG . getConstant ( <NUM_LIT> * NumElts / <NUM_LIT> , dl , <STR_LIT> ) ) ;

SDValue Ext3 = DAG . getNode ( <STR_LIT> , dl , EltVT , Op0 , DAG . getConstant ( <NUM_LIT> * NumElts / <NUM_LIT> , dl , <STR_LIT> ) ) ;


<s> static SDValue LowerVecReduceF ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget * ST ) {

if ( ! ST -> hasMVEFloatOps ( ) ) return SDValue ( ) ;


<s> if ( ! ST -> hasMVEFloatOps ( ) ) return SDValue ( ) ;

return LowerVecReduce ( Op , DAG , ST ) ;


<s> static SDValue LowerVectorExtend ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return SDValue ( ) ; EVT ToVT = N -> getValueType ( <NUM_LIT> ) ; if ( ToVT != <STR_LIT> && ToVT != <STR_LIT> && ToVT != <STR_LIT> ) return SDValue ( ) ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; EVT FromVT = Op . getValueType ( ) ; if ( FromVT != <STR_LIT> && FromVT != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT ExtVT = ToVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) ;

if ( ToVT . getScalarType ( ) == <STR_LIT> && FromVT . getScalarType ( ) == <STR_LIT> ) ExtVT = <STR_LIT> ;


<s> static SDValue LowerVectorFP_TO_INT ( SDValue Op , SelectionDAG & DAG ) { EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; if ( Op . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) { if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) return Op ; return DAG . UnrollVectorOp ( Op . getNode ( ) ) ; } const bool HasFullFP16 = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasFullFP16 ( ) ; EVT NewTy ; const EVT OpTy = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( OpTy == <STR_LIT> ) NewTy = <STR_LIT> ; else if ( OpTy == <STR_LIT> && HasFullFP16 ) NewTy = <STR_LIT> ; else if ( OpTy == <STR_LIT> && HasFullFP16 ) NewTy = <STR_LIT> ;


<s> if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) return Op ; return DAG . UnrollVectorOp ( Op . getNode ( ) ) ; } const bool HasFullFP16 = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasFullFP16 ( ) ; EVT NewTy ; const EVT OpTy = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ;

if ( OpTy == <STR_LIT> ) NewTy = <STR_LIT> ;


<s> if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) { if ( VT . getVectorElementType ( ) == <STR_LIT> ) return Op ; return DAG . UnrollVectorOp ( Op . getNode ( ) ) ; } assert ( ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> || Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) && <STR_LIT> ) ; const bool HasFullFP16 = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasFullFP16 ( ) ; EVT DestVecType ; if ( VT == <STR_LIT> ) DestVecType = <STR_LIT> ; else if ( VT == <STR_LIT> && HasFullFP16 ) DestVecType = <STR_LIT> ; else if ( VT == <STR_LIT> && HasFullFP16 ) DestVecType = <STR_LIT> ; else return DAG . UnrollVectorOp ( Op . getNode ( ) ) ; unsigned CastOpc ; unsigned Opc ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : CastOpc = <STR_LIT> ; Opc = <STR_LIT> ; break ;


<s> if ( IsScalarToVector ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 . getOperand ( <NUM_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , dl , VT , V1 , DAG . getConstant ( Lane , dl , <STR_LIT> ) ) ; } bool ReverseVEXT = false ; unsigned Imm = <NUM_LIT> ; if ( ST -> hasNEON ( ) && isVEXTMask ( ShuffleMask , VT , ReverseVEXT , Imm ) ) { if ( ReverseVEXT ) std :: swap ( V1 , V2 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG . getConstant ( Imm , dl , <STR_LIT> ) ) ; } if ( isVREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 ) ; if ( isVREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 ) ; if ( isVREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 ) ; if ( ST -> hasNEON ( ) && V2 -> isUndef ( ) && isSingletonVEXTMask ( ShuffleMask , VT , Imm ) ) { return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V1 , DAG . getConstant ( Imm , dl , <STR_LIT> ) ) ; } unsigned WhichResult = <NUM_LIT> ; bool isV_UNDEF = false ; if ( ST -> hasNEON ( ) ) { if ( unsigned ShuffleOpc = isNEONTwoResultShuffleMask ( ShuffleMask , VT , WhichResult , isV_UNDEF ) ) { if ( isV_UNDEF ) V2 = V1 ; return DAG . getNode ( ShuffleOpc , dl , DAG . getVTList ( VT , VT ) , V1 , V2 ) . getValue ( WhichResult ) ; } } if ( ST -> hasMVEIntegerOps ( ) ) { if ( isVMOVNMask ( ShuffleMask , VT , false , false ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V2 , V1 , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; if ( isVMOVNMask ( ShuffleMask , VT , true , false ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; if ( isVMOVNMask ( ShuffleMask , VT , true , true ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V1 , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;


<s> if ( ShuffleMask [ Start + i ] >= <NUM_LIT> ) { if ( ShuffleMask [ Start + i ] % Length != i ) return - <NUM_LIT> ; MovIdx = ShuffleMask [ Start + i ] / Length ; break ; } } if ( MovIdx == - <NUM_LIT> ) return - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < Length ; i ++ ) { if ( ShuffleMask [ Start + i ] >= <NUM_LIT> && ( ShuffleMask [ Start + i ] / Length != MovIdx || ShuffleMask [ Start + i ] % Length != i ) ) return - <NUM_LIT> ; } return MovIdx ; } ; for ( int Part = <NUM_LIT> ; Part < <NUM_LIT> ; ++ Part ) { int Elt = getMovIdx ( ShuffleMask , Part * QuarterSize , QuarterSize ) ; if ( Elt != - <NUM_LIT> ) { SDValue Input = Op -> getOperand ( <NUM_LIT> ) ; if ( Elt >= <NUM_LIT> ) { Input = Op -> getOperand ( <NUM_LIT> ) ; Elt -= <NUM_LIT> ; } SDValue BitCast = DAG . getBitcast ( <STR_LIT> , Input ) ; Parts [ Part ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BitCast , DAG . getConstant ( Elt , dl , <STR_LIT> ) ) ; } } if ( ! Parts [ <NUM_LIT> ] && ! Parts [ <NUM_LIT> ] && ! Parts [ <NUM_LIT> ] && ! Parts [ <NUM_LIT> ] ) return SDValue ( ) ; if ( ! Parts [ <NUM_LIT> ] || ! Parts [ <NUM_LIT> ] || ! Parts [ <NUM_LIT> ] || ! Parts [ <NUM_LIT> ] ) { SmallVector < int , <NUM_LIT> > NewShuffleMask ; for ( int Part = <NUM_LIT> ; Part < <NUM_LIT> ; ++ Part ) for ( int i = <NUM_LIT> ; i < QuarterSize ; i ++ ) NewShuffleMask . push_back ( Parts [ Part ] ? - <NUM_LIT> : ShuffleMask [ Part * QuarterSize + i ] ) ; SDValue NewShuffle = DAG . getVectorShuffle ( VT , dl , Op -> getOperand ( <NUM_LIT> ) , Op -> getOperand ( <NUM_LIT> ) , NewShuffleMask ) ; SDValue BitCast = DAG . getBitcast ( <STR_LIT> , NewShuffle ) ; for ( int Part = <NUM_LIT> ; Part < <NUM_LIT> ; ++ Part ) if ( ! Parts [ Part ] ) Parts [ Part ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BitCast , DAG . getConstant ( Part , dl , <STR_LIT> ) ) ; }

SDValue NewVec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Parts ) ;


<s> SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; SmallVector < SDValue , <NUM_LIT> > VTBLMask ; for ( ArrayRef < int > :: iterator I = ShuffleMask . begin ( ) , E = ShuffleMask . end ( ) ; I != E ; ++ I ) VTBLMask . push_back ( DAG . getConstant ( * I , DL , <STR_LIT> ) ) ; if ( V2 . getNode ( ) -> isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getBuildVector ( <STR_LIT> , DL , VTBLMask ) ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getBuildVector ( <STR_LIT> , DL , VTBLMask ) ) ;


<s> for ( ArrayRef < int > :: iterator I = ShuffleMask . begin ( ) , E = ShuffleMask . end ( ) ; I != E ; ++ I ) VTBLMask . push_back ( DAG . getConstant ( * I , DL , <STR_LIT> ) ) ; if ( V2 . getNode ( ) -> isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getBuildVector ( <STR_LIT> , DL , VTBLMask ) ) ;


<s> ShuffleVectorSDNode * SVN = cast < ShuffleVectorSDNode > ( Op . getNode ( ) ) ; ArrayRef < int > ShuffleMask = SVN -> getMask ( ) ; assert ( ST -> hasMVEIntegerOps ( ) && <STR_LIT> ) ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; if ( isReverseMask ( ShuffleMask , VT ) ) { SDValue cast = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V1 ) ; SDValue rbit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , cast ) ; SDValue srl = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , rbit , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , srl ) ;


<s> EVT VT = Op . getValueType ( ) ; ShuffleVectorSDNode * SVN = cast < ShuffleVectorSDNode > ( Op . getNode ( ) ) ; ArrayRef < int > ShuffleMask = SVN -> getMask ( ) ; assert ( ST -> hasMVEIntegerOps ( ) && <STR_LIT> ) ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; if ( isReverseMask ( ShuffleMask , VT ) ) { SDValue cast = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V1 ) ;

SDValue rbit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , cast ) ;


<s> if ( ST -> hasMVEFloatOps ( ) ) { Opc = <STR_LIT> ; break ; } else { Invert = true ; LLVM_FALLTHROUGH ; } case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Swap = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Swap = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Invert = true ; Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Invert = true ; Opc = <STR_LIT> ; break ; case <STR_LIT> : Invert = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : { SDValue TmpOp0 = DAG . getNode ( <STR_LIT> , dl , CmpVT , Op1 , Op0 , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ) ; SDValue TmpOp1 = DAG . getNode ( <STR_LIT> , dl , CmpVT , Op0 , Op1 , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , CmpVT , TmpOp0 , TmpOp1 ) ; if ( Invert ) Result = DAG . getNOT ( dl , Result , VT ) ; return Result ; } case <STR_LIT> : Invert = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : { SDValue TmpOp0 = DAG . getNode ( <STR_LIT> , dl , CmpVT , Op1 , Op0 , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ) ; SDValue TmpOp1 = DAG . getNode ( <STR_LIT> , dl , CmpVT , Op0 , Op1 , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , CmpVT , TmpOp0 , TmpOp1 ) ; if ( Invert ) Result = DAG . getNOT ( dl , Result , VT ) ; return Result ; } } } else { switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( ST -> hasMVEIntegerOps ( ) ) { Opc = <STR_LIT> ; break ; } else { Invert = true ; LLVM_FALLTHROUGH ; } case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = <STR_LIT> ; break ;


<s> EVT VT = Op . getValueType ( ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; const auto & DL = DAG . getDataLayout ( ) ; const auto & TLI = DAG . getTargetLoweringInfo ( ) ; const char * Name = nullptr ; if ( Signed ) Name = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Name = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue ES = DAG . getExternalSymbol ( Name , TLI . getPointerTy ( DL ) ) ; <ISA_LIT>TargetLowering :: ArgListTy Args ; for ( auto AI : { <NUM_LIT> , <NUM_LIT> } ) { ArgListEntry Arg ; Arg . Node = Op . getOperand ( AI ) ; Arg . Ty = Arg . Node . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; Args . push_back ( Arg ) ; } CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: <ISA_LIT>_AAPCS_VFP , VT . getTypeForEVT ( * DAG . getContext ( ) ) , ES , std :: move ( Args ) ) ;


<s> const auto & DL = DAG . getDataLayout ( ) ; const auto & TLI = DAG . getTargetLoweringInfo ( ) ; const char * Name = nullptr ; if ( Signed ) Name = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Name = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue ES = DAG . getExternalSymbol ( Name , TLI . getPointerTy ( DL ) ) ; <ISA_LIT>TargetLowering :: ArgListTy Args ; for ( auto AI : { <NUM_LIT> , <NUM_LIT> } ) { ArgListEntry Arg ; Arg . Node = Op . getOperand ( AI ) ; Arg . Ty = Arg . Node . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; Args . push_back ( Arg ) ;


<s> if ( ConstraintVT . isVector ( ) && Subtarget -> hasNEON ( ) && ( ConstraintVT . getSizeInBits ( ) == <NUM_LIT> || ConstraintVT . getSizeInBits ( ) == <NUM_LIT> ) ) return <STR_LIT> ;


<s> int FI = std :: numeric_limits < int > :: max ( ) ; if ( Arg . getOpcode ( ) == <STR_LIT> ) { unsigned VR = cast < RegisterSDNode > ( Arg . getOperand ( <NUM_LIT> ) ) -> getReg ( ) ; if ( ! Register :: isVirtualRegister ( VR ) ) return false ; MachineInstr * Def = MRI -> getVRegDef ( VR ) ; if ( ! Def ) return false ; if ( ! Flags . isByVal ( ) ) { if ( ! TII -> isLoadFromStackSlot ( * Def , FI ) ) return false ; } else { return false ; }

} else if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Arg ) ) {


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { if ( ! Subtarget -> supportsTailCall ( ) ) return false ;

if ( ! CI -> isTailCall ( ) ) return false ;


<s> Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ( LocVT . getSizeInBits ( ) ) , Val ) ; } else { Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ( ValVT . getSizeInBits ( ) ) , Val ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ( LocVT . getSizeInBits ( ) ) , Val ) ; }

return DAG . getNode ( <STR_LIT> , dl , LocVT , Val ) ;


<s> Val = DAG . getNode ( <STR_LIT> , dl , ValVT , Val ) ; } else { Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ( ValVT . getSizeInBits ( ) ) , Val ) ; Val = DAG . getNode ( <STR_LIT> , dl , ValVT , Val ) ;


<s> if ( NextVA . isRegLoc ( ) ) RegsToPass . push_back ( std :: make_pair ( NextVA . getLocReg ( ) , fmrrd . getValue ( <NUM_LIT> - id ) ) ) ; else { assert ( NextVA . isMemLoc ( ) ) ; if ( ! StackPtr . getNode ( ) ) StackPtr = DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


<s> static SDValue PerformABSCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { SDValue res ; SelectionDAG & DAG = DCI . DAG ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . isOperationLegal ( N -> getOpcode ( ) , N -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( ! TLI . expandABS ( N , res , DAG ) ) return SDValue ( ) ; return res ;


<s> if ( TLI . isOperationLegal ( N -> getOpcode ( ) , N -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ;

if ( ! TLI . expandABS ( N , res , DAG ) ) return SDValue ( ) ;


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ;

if ( SDValue Result = PerformSHLSimplify ( N , DCI , Subtarget ) ) return Result ;


<s> if ( SDValue Result = PerformADDVecReduce ( N , DCI . DAG , Subtarget ) ) return Result ; if ( SDValue Result = PerformADDCombineWithOperands ( N , N0 , N1 , DCI , Subtarget ) ) return Result ; return PerformADDCombineWithOperands ( N , N1 , N0 , DCI , Subtarget ) ;


<s> if ( SDValue Result = AddCombineToVPADD ( N , N0 , N1 , DCI , Subtarget ) ) return Result ;

if ( SDValue Result = AddCombineVUZPToVPADDL ( N , N0 , N1 , DCI , Subtarget ) ) return Result ;


<s> if ( imm < <NUM_LIT> && imm > std :: numeric_limits < int > :: min ( ) ) { SDLoc DL ( N ) ; RHS = DAG . getConstant ( - imm , DL , <STR_LIT> ) ; unsigned Opcode = ( N -> getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ;

return DAG . getNode ( Opcode , DL , N -> getVTList ( ) , N -> getOperand ( <NUM_LIT> ) , RHS ) ;


<s> SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( RHS ) ) { int32_t imm = C -> getSExtValue ( ) ; if ( imm < <NUM_LIT> && imm > std :: numeric_limits < int > :: min ( ) ) { SDLoc DL ( N ) ; RHS = DAG . getConstant ( - imm , DL , <STR_LIT> ) ; unsigned Opcode = ( N -> getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opcode , DL , N -> getVTList ( ) , N -> getOperand ( <NUM_LIT> ) , RHS ) ; } }


<s> if ( DCI . isBeforeLegalize ( ) ) return SDValue ( ) ;

return AddCombineTo64bitUMAAL ( N , DCI , Subtarget ) ;


<s> if ( Subtarget -> isThumb1Only ( ) ) return PerformAddeSubeCombine ( N , DCI , Subtarget ) ;

if ( DCI . isBeforeLegalize ( ) ) return SDValue ( ) ;


<s> if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( RHS ) ) { int64_t imm = C -> getSExtValue ( ) ; if ( imm < <NUM_LIT> ) { SDLoc DL ( N ) ; RHS = DAG . getConstant ( ~ imm , DL , <STR_LIT> ) ; unsigned Opcode = ( N -> getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opcode , DL , N -> getVTList ( ) , N -> getOperand ( <NUM_LIT> ) , RHS , N -> getOperand ( <NUM_LIT> ) ) ; } } } else if ( N -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) == <STR_LIT> ) {

return AddCombineTo64bitMLAL ( N , DCI , Subtarget ) ;


<s> for ( unsigned I = S , E = VecRed . getNumOperands ( ) ; I < E ; I ++ ) Ops . push_back ( VecRed -> getOperand ( I ) ) ; SDValue Red = DAG . getNode ( OpcodeA , dl , DAG . getVTList ( { <STR_LIT> , <STR_LIT> } ) , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Red , SDValue ( Red . getNode ( ) , <NUM_LIT> ) ) ; } ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ;


<s> EVT VbicVT ; SDValue Val = isVMOVModifiedImm ( ( ~ SplatBits ) . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , dl , VbicVT , VT , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VbicVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Vbic = DAG . getNode ( <STR_LIT> , dl , VbicVT , Input , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vbic ) ; } } } if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , true , DCI ) ) return Result ; if ( SDValue Result = PerformSHLSimplify ( N , DCI , Subtarget ) ) return Result ; }

if ( Subtarget -> isThumb1Only ( ) ) if ( SDValue Result = CombineANDShift ( N , DCI , Subtarget ) ) return Result ;


<s> static SDValue PerformANDCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { BuildVectorSDNode * BVN = dyn_cast < BuildVectorSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SelectionDAG & DAG = DCI . DAG ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return SDValue ( ) ; APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN && ( Subtarget -> hasNEON ( ) || Subtarget -> hasMVEIntegerOps ( ) ) && BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize == <NUM_LIT> || SplatBitSize == <NUM_LIT> || SplatBitSize == <NUM_LIT> || SplatBitSize == <NUM_LIT> ) { EVT VbicVT ; SDValue Val = isVMOVModifiedImm ( ( ~ SplatBits ) . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , dl , VbicVT , VT , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VbicVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Vbic = DAG . getNode ( <STR_LIT> , dl , VbicVT , Input , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vbic ) ; } } } if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , true , DCI ) ) return Result ; if ( SDValue Result = PerformSHLSimplify ( N , DCI , Subtarget ) ) return Result ; }


<s> for ( unsigned Idx = <NUM_LIT> ; Idx < NumElts ; ++ Idx ) { SDValue V = N -> getOperand ( Idx ) ; if ( V . isUndef ( ) ) continue ; if ( V . getOpcode ( ) == <STR_LIT> && V -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ; else { V = DAG . getNode ( <STR_LIT> , SDLoc ( V ) , <STR_LIT> , V ) ; DCI . AddToWorklist ( V . getNode ( ) ) ; } SDValue LaneIdx = DAG . getConstant ( Idx , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , VecVT , Vec , V , LaneIdx ) ; } Vec = DAG . getNode ( <STR_LIT> , dl , VT , Vec ) ;

DCI . AddToWorklist ( Vec . getNode ( ) ) ;


<s> SelectionDAG & DAG = DCI . DAG ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; if ( ST -> hasMVEIntegerOps ( ) && Src . getOpcode ( ) == <STR_LIT> ) { EVT SrcVT = Src . getValueType ( ) ; if ( SrcVT . getScalarSizeInBits ( ) == DstVT . getScalarSizeInBits ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , DstVT , Src . getOperand ( <NUM_LIT> ) ) ; } while ( Src . getOpcode ( ) == <STR_LIT> ) Src = Src . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; if ( ( Src . getOpcode ( ) == <STR_LIT> || Src . getOpcode ( ) == <STR_LIT> || Src . getOpcode ( ) == <STR_LIT> ) && SrcVT . getScalarSizeInBits ( ) <= DstVT . getScalarSizeInBits ( ) && DAG . getDataLayout ( ) . isBigEndian ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , DstVT , Src ) ; if ( SDValue R = PerformExtractEltToVMOVRRD ( N , DCI ) ) return R ; return SDValue ( ) ;


<s> auto * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ; if ( ( LHS00C && LHS00C -> getZExtValue ( ) == <NUM_LIT> ) && ( LHS01C && LHS01C -> getZExtValue ( ) == <NUM_LIT> ) && ( LHS1C && LHS1C -> getZExtValue ( ) == <NUM_LIT> ) && ( RHSC && RHSC -> getZExtValue ( ) == <NUM_LIT> ) ) { return DAG . getNode ( <STR_LIT> , dl , VT , Chain , BB , LHS -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) , LHS -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) , LHS -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ) ; } } return SDValue ( ) ;


<s> static SDValue PerformBUILD_VECTORCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { SelectionDAG & DAG = DCI . DAG ; if ( N -> getNumOperands ( ) == <NUM_LIT> ) if ( SDValue RV = PerformVMOVDRRCombine ( N , DAG ) ) return RV ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . getVectorElementType ( ) != <STR_LIT> || ! hasNormalLoadOperand ( N ) ) return SDValue ( ) ; SDLoc dl ( N ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned NumElts = VT . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( i ) ) ; Ops . push_back ( V ) ; DCI . AddToWorklist ( V . getNode ( ) ) ; } EVT FloatVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; SDValue BV = DAG . getBuildVector ( FloatVT , dl , Ops ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , BV ) ;


<s> assert ( CmpZ -> getOpcode ( ) == <STR_LIT> ) ; SDValue And = CmpZ -> getOperand ( <NUM_LIT> ) ; if ( And -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; const APInt * AndC = isPowerOf2Constant ( And -> getOperand ( <NUM_LIT> ) ) ; if ( ! AndC ) return SDValue ( ) ; SDValue X = And -> getOperand ( <NUM_LIT> ) ; if ( CC == <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; } else { assert ( CC == <STR_LIT> && <STR_LIT> ) ; } if ( Op1 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * OrC = dyn_cast < ConstantSDNode > ( Op1 -> getOperand ( <NUM_LIT> ) ) ; if ( ! OrC ) return SDValue ( ) ; SDValue Y = Op1 -> getOperand ( <NUM_LIT> ) ; if ( Op0 != Y ) return SDValue ( ) ; APInt OrCI = OrC -> getAPIntValue ( ) ; unsigned Heuristic = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( OrCI . countPopulation ( ) > Heuristic ) return SDValue ( ) ; KnownBits Known = DAG . computeKnownBits ( Y ) ; if ( ( OrCI & Known . Zero ) != OrCI ) return SDValue ( ) ; SDValue V = Y ; SDLoc dl ( X ) ; EVT VT = X . getValueType ( ) ; unsigned BitInX = AndC -> logBase2 ( ) ; if ( BitInX != <NUM_LIT> ) {

X = DAG . getNode ( <STR_LIT> , dl , VT , X , DAG . getConstant ( BitInX , dl , VT ) ) ;


<s> static SDValue PerformExtendCombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * ST ) { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; if ( ( ST -> hasNEON ( ) || ST -> hasMVEIntegerOps ( ) ) && N0 . getOpcode ( ) == <STR_LIT> ) { SDValue Vec = N0 . getOperand ( <NUM_LIT> ) ; SDValue Lane = N0 . getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT EltVT = N0 . getValueType ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( VT == <STR_LIT> && ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && TLI . isTypeLegal ( Vec . getValueType ( ) ) && isa < ConstantSDNode > ( Lane ) ) { unsigned Opc = <NUM_LIT> ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ;


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; if ( ( ST -> hasNEON ( ) || ST -> hasMVEIntegerOps ( ) ) && N0 . getOpcode ( ) == <STR_LIT> ) { SDValue Vec = N0 . getOperand ( <NUM_LIT> ) ; SDValue Lane = N0 . getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT EltVT = N0 . getValueType ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( VT == <STR_LIT> && ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && TLI . isTypeLegal ( Vec . getValueType ( ) ) && isa < ConstantSDNode > ( Lane ) ) { unsigned Opc = <NUM_LIT> ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; break ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( N ) ; if ( Op0 -> getOpcode ( ) == <STR_LIT> ) { SDValue X = Op0 -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && X . getValueType ( ) == <STR_LIT> ) return DCI . DAG . getNode ( <STR_LIT> , dl , VT , X ) ; if ( VT == <STR_LIT> && X . getValueType ( ) == <STR_LIT> ) return DCI . DAG . getNode ( <STR_LIT> , dl , VT , X ) ; if ( VT == <STR_LIT> && X . getValueType ( ) == <STR_LIT> ) return DCI . DAG . getNode ( <STR_LIT> , dl , VT , X ) ; while ( X . getValueType ( ) != VT && X -> getOpcode ( ) == <STR_LIT> ) X = X -> getOperand ( <NUM_LIT> ) ; if ( X . getValueType ( ) == VT ) return X ; }

if ( Op0 -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) && N -> getConstantOperandVal ( <NUM_LIT> ) < Op0 . getNumOperands ( ) ) {


<s> while ( X . getValueType ( ) != VT && X -> getOpcode ( ) == <STR_LIT> ) X = X -> getOperand ( <NUM_LIT> ) ; if ( X . getValueType ( ) == VT ) return X ; } if ( Op0 -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) && N -> getConstantOperandVal ( <NUM_LIT> ) < Op0 . getNumOperands ( ) ) { return Op0 . getOperand ( N -> getConstantOperandVal ( <NUM_LIT> ) ) ; } if ( Op0 . getValueType ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { SDValue BV = Op0 . getOperand ( <NUM_LIT> ) ; unsigned Offset = N -> getConstantOperandVal ( <NUM_LIT> ) ; SDValue MOV = BV . getOperand ( Offset < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( MOV . getOpcode ( ) == <STR_LIT> ) return MOV . getOperand ( ST -> isLittle ( ) ? Offset % <NUM_LIT> : <NUM_LIT> - Offset % <NUM_LIT> ) ; } if ( SDValue R = PerformExtractEltToVMOVRRD ( N , DCI ) ) return R ; if ( Op0 -> getOpcode ( ) == <STR_LIT> ) { unsigned Idx = N -> getConstantOperandVal ( <NUM_LIT> ) ; unsigned Vec = Idx / Op0 -> getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorNumElements ( ) ; unsigned SubIdx = Idx % Op0 -> getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorNumElements ( ) ; return DCI . DAG . getNode ( <STR_LIT> , dl , VT , Op0 . getOperand ( Vec ) , DCI . DAG . getConstant ( SubIdx , dl , <STR_LIT> ) ) ; }


<s> SDLoc dl ( N ) ; if ( ! DCI . isAfterLegalizeDAG ( ) || VT != <STR_LIT> || ! DCI . DAG . getTargetLoweringInfo ( ) . isTypeLegal ( <STR_LIT> ) ) return SDValue ( ) ; SDValue Ext = SDValue ( N , <NUM_LIT> ) ; if ( Ext . getOpcode ( ) == <STR_LIT> && Ext . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) Ext = Ext . getOperand ( <NUM_LIT> ) ; if ( Ext . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Ext . getOperand ( <NUM_LIT> ) ) || Ext . getConstantOperandVal ( <NUM_LIT> ) % <NUM_LIT> != <NUM_LIT> ) return SDValue ( ) ; if ( Ext -> use_size ( ) == <NUM_LIT> && ( Ext -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> || Ext -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> ) ) return SDValue ( ) ; SDValue Op0 = Ext . getOperand ( <NUM_LIT> ) ; EVT VecVT = Op0 . getValueType ( ) ; unsigned ResNo = Op0 . getResNo ( ) ; unsigned Lane = Ext . getConstantOperandVal ( <NUM_LIT> ) ; if ( VecVT . getVectorNumElements ( ) != <NUM_LIT> ) return SDValue ( ) ; auto OtherIt = find_if ( Op0 -> uses ( ) , [ & ] ( SDNode * V ) {

return V -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( V -> getOperand ( <NUM_LIT> ) ) && V -> getConstantOperandVal ( <NUM_LIT> ) == Lane + <NUM_LIT> && V -> getOperand ( <NUM_LIT> ) . getResNo ( ) == ResNo ;


<s> if ( ! GetLane ) return SDValue ( ) ; LLVMContext & C = * DAG . getContext ( ) ; SDLoc DL ( St ) ; SDValue Ch = St -> getChain ( ) ; SDValue BasePtr = St -> getBasePtr ( ) ; Align Alignment = St -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = St -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = St -> getAAInfo ( ) ;

EVT NewToVT = EVT :: getIntegerVT ( C , VT . getSizeInBits ( ) ) ;


<s> EVT SubVT = SubVec . getValueType ( ) ; if ( ! VecVT . isFixedLengthVector ( ) || ! DCI . DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VecVT ) || ! DCI . DAG . getTargetLoweringInfo ( ) . isTypeLegal ( SubVT ) ) return SDValue ( ) ; if ( IdxVal == <NUM_LIT> && Vec . isUndef ( ) ) return SDValue ( ) ; unsigned NumSubElts = SubVT . getVectorNumElements ( ) ; if ( ( SubVT . getSizeInBits ( ) * <NUM_LIT> ) != VecVT . getSizeInBits ( ) || ( IdxVal != <NUM_LIT> && IdxVal != NumSubElts ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue Lo , Hi ;


<s> static SDValue PerformLOADCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( Subtarget -> hasNEON ( ) && <STR_LIT> ( N ) && VT . isVector ( ) && DCI . DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return CombineBaseUpdate ( N , DCI ) ; return SDValue ( ) ;


<s> return SDValue ( ) ; } if ( ShiftAmt >= - <NUM_LIT> && ShiftAmt < <NUM_LIT> ) { unsigned NewOpcode = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue NewShift = DAG . getNode ( NewOpcode , DL , N -> getVTList ( ) , Op0 , Op1 , DAG . getConstant ( - ShiftAmt , DL , <STR_LIT> ) ) ;

DAG . ReplaceAllUsesWith ( N , NewShift . getNode ( ) ) ;


<s> if ( Min -> getOpcode ( ) != <STR_LIT> ) std :: swap ( Min , Max ) ; if ( Min -> getOpcode ( ) != <STR_LIT> || Max -> getOpcode ( ) != <STR_LIT> ) return false ; APInt SaturateC ; if ( VT == <STR_LIT> ) SaturateC = APInt ( <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , true ) ; else SaturateC = APInt ( <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , true ) ; APInt MinC , MaxC ; if ( ! <STR_LIT> ( Min -> getOperand ( <NUM_LIT> ) . getNode ( ) , MinC ) || MinC != SaturateC ) return false ; if ( ! <STR_LIT> ( Max -> getOperand ( <NUM_LIT> ) . getNode ( ) , MaxC ) || MaxC != ~ SaturateC ) return false ; return true ; } ; if ( IsSignedSaturate ( N , N0 . getNode ( ) ) ) { SDLoc DL ( N ) ; MVT ExtVT , HalfVT ; if ( VT == <STR_LIT> ) { HalfVT = <STR_LIT> ; ExtVT = <STR_LIT> ; } else { HalfVT = <STR_LIT> ; ExtVT = <STR_LIT> ; } SDValue VQMOVN = DAG . getNode ( <STR_LIT> , DL , HalfVT , DAG . getUNDEF ( HalfVT ) , N0 -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Bitcast = DAG . getNode ( <STR_LIT> , DL , VT , VQMOVN ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Bitcast , DAG . getValueType ( ExtVT ) ) ; } auto IsUnsignedSaturate = [ & ] ( SDNode * Min ) {

if ( Min -> getOpcode ( ) != <STR_LIT> ) return false ;


<s> } else if ( isPowerOf2_32 ( MulAmt + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt + <NUM_LIT> ) , DL , <STR_LIT> ) ) , V ) ; } else return SDValue ( ) ; } else { uint64_t MulAmtAbs = - MulAmt ; if ( isPowerOf2_32 ( MulAmtAbs + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs + <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmtAbs - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs - <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Res ) ; } else return SDValue ( ) ; } if ( ShiftAmt != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getConstant ( ShiftAmt , DL , <STR_LIT> ) ) ; DCI . CombineTo ( N , Res , false ) ;


<s> if ( VT . is64BitVector ( ) || VT . is128BitVector ( ) ) return PerformVMULCombine ( N , DCI , Subtarget ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return SDValue ( ) ; int64_t MulAmt = C -> getSExtValue ( ) ; unsigned ShiftAmt = countTrailingZeros < uint64_t > ( MulAmt ) ; ShiftAmt = ShiftAmt & ( <NUM_LIT> - <NUM_LIT> ) ; SDValue V = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue Res ; MulAmt >>= ShiftAmt ; if ( MulAmt >= <NUM_LIT> ) { if ( isPowerOf2_32 ( MulAmt - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt - <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmt + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt + <NUM_LIT> ) , DL , <STR_LIT> ) ) , V ) ; } else return SDValue ( ) ; } else { uint64_t MulAmtAbs = - MulAmt ; if ( isPowerOf2_32 ( MulAmtAbs + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs + <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmtAbs - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs - <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Res ) ;


<s> SmallVector < int , <NUM_LIT> > Mask ( S0 -> getMask ( ) . begin ( ) , S0 -> getMask ( ) . end ( ) ) ; Mask . append ( S1 -> getMask ( ) . begin ( ) , S1 -> getMask ( ) . end ( ) ) ; if ( isVMOVNTruncMask ( Mask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , S0 -> getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , VT , S0 -> getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; if ( isVMOVNTruncMask ( Mask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , S0 -> getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , VT , S0 -> getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } } if ( all_of ( N -> ops ( ) , [ ] ( SDValue Op ) { return Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> || ( Op . getOpcode ( ) == <STR_LIT> && Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ; } ) ) { SmallVector < SDValue , <NUM_LIT> > Extracts ; for ( unsigned Op = <NUM_LIT> ; Op < N -> getNumOperands ( ) ; Op ++ ) { SDValue O = N -> getOperand ( Op ) ; for ( unsigned i = <NUM_LIT> ; i < O . getValueType ( ) . getVectorNumElements ( ) ; i ++ ) { SDValue Ext = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , O , DAG . getConstant ( i , DL , <STR_LIT> ) ) ; Extracts . push_back ( Ext ) ; } } return DAG . getBuildVector ( VT , DL , Extracts ) ; } if ( ! DCI . isAfterLegalizeDAG ( ) ) return SDValue ( ) ; SDValue StackPtr = DAG . CreateStackTemporary ( TypeSize :: Fixed ( <NUM_LIT> ) , Align ( <NUM_LIT> ) ) ; int SPFI = cast < FrameIndexSDNode > ( StackPtr . getNode ( ) ) -> getIndex ( ) ;


<s> unsigned NumBytes = NumVecs * VecTy . getSizeInBits ( ) / <NUM_LIT> ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ; if ( ! CInc || CInc -> getZExtValue ( ) != NumBytes ) continue ; EVT Tys [ <NUM_LIT> ] ; unsigned NumResultVecs = ( isLoadOp ? NumVecs : <NUM_LIT> ) ; unsigned n ; for ( n = <NUM_LIT> ; n < NumResultVecs ; ++ n ) Tys [ n ] = VecTy ; Tys [ n ++ ] = <STR_LIT> ; Tys [ n ] = <STR_LIT> ; SDVTList SDTys = DAG . getVTList ( makeArrayRef ( Tys , NumResultVecs + <NUM_LIT> ) ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Inc ) ; for ( unsigned i = <NUM_LIT> ; i < N -> getNumOperands ( ) ; ++ i ) Ops . push_back ( N -> getOperand ( i ) ) ; SDValue UpdN = DAG . getMemIntrinsicNode ( NewOpc , dl , SDTys , Ops , VecTy , MemN -> getMemOperand ( ) ) ; SmallVector < SDValue , <NUM_LIT> > NewResults ; for ( unsigned i = <NUM_LIT> ; i < NumResultVecs ; ++ i ) NewResults . push_back ( SDValue ( UpdN . getNode ( ) , i ) ) ; NewResults . push_back ( SDValue ( UpdN . getNode ( ) , NumResultVecs + <NUM_LIT> ) ) ; DCI . CombineTo ( N , NewResults ) ; DCI . CombineTo ( User , SDValue ( UpdN . getNode ( ) , NumResultVecs ) ) ; break ;


<s> SDValue Mask = And -> getOperand ( <NUM_LIT> ) ; if ( Mask -> getOpcode ( ) == <STR_LIT> ) Mask = Mask -> getOperand ( <NUM_LIT> ) ; if ( Mask -> getOpcode ( ) != <STR_LIT> || Mask . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( isAllOnesConstant ( Mask -> getOperand ( <NUM_LIT> ) ) && isNullConstant ( Mask -> getOperand ( <NUM_LIT> ) ) && isAllOnesConstant ( Mask -> getOperand ( <NUM_LIT> ) ) && isNullConstant ( Mask -> getOperand ( <NUM_LIT> ) ) ) return And -> getOperand ( <NUM_LIT> ) ; return SDValue ( ) ; } ; SDLoc dl ( N ) ; if ( SDValue Op0 = IsSignExt ( N0 ) ) { if ( SDValue Op1 = IsSignExt ( N1 ) ) { SDValue New0a = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 ) ; SDValue New1a = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op1 ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , New0a , New1a ) ;


<s> if ( Subtarget -> hasDSP ( ) && ( Mask2 == <NUM_LIT> || Mask2 == <NUM_LIT> ) ) return SDValue ( ) ; unsigned lsb = countTrailingZeros ( Mask ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N00 , DAG . getConstant ( lsb , DL , <STR_LIT> ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N1 . getOperand ( <NUM_LIT> ) , Res , DAG . getConstant ( Mask2 , DL , <STR_LIT> ) ) ; DCI . CombineTo ( N , Res , false ) ; return SDValue ( N , <NUM_LIT> ) ; } } if ( DAG . MaskedValueIsZero ( N1 , MaskC -> getAPIntValue ( ) ) && N00 . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N00 . getOperand ( <NUM_LIT> ) ) && <STR_LIT> ( ~ Mask ) ) { SDValue ShAmt = N00 . getOperand ( <NUM_LIT> ) ; unsigned ShAmtC = cast < ConstantSDNode > ( ShAmt ) -> getZExtValue ( ) ; unsigned LSB = countTrailingZeros ( Mask ) ; if ( ShAmtC != LSB ) return SDValue ( ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N1 , N00 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( ~ Mask , DL , <STR_LIT> ) ) ; DCI . CombineTo ( N , Res , false ) ; return SDValue ( N , <NUM_LIT> ) ; } return SDValue ( ) ;


<s> DCI . CombineTo ( N , Res , false ) ; return SDValue ( N , <NUM_LIT> ) ; } } else if ( N1 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * N11C = dyn_cast < ConstantSDNode > ( N1 . getOperand ( <NUM_LIT> ) ) ; if ( ! N11C ) return SDValue ( ) ; unsigned Mask2 = N11C -> getZExtValue ( ) ; if ( <STR_LIT> ( Mask ) && ( Mask == ~ Mask2 ) ) { if ( Subtarget -> hasDSP ( ) && ( Mask == <NUM_LIT> || Mask == <NUM_LIT> ) ) return SDValue ( ) ; unsigned amt = countTrailingZeros ( Mask2 ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N1 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( amt , DL , <STR_LIT> ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N00 , Res , DAG . getConstant ( Mask , DL , <STR_LIT> ) ) ; DCI . CombineTo ( N , Res , false ) ; return SDValue ( N , <NUM_LIT> ) ; } else if ( <STR_LIT> ( ~ Mask ) && ( ~ Mask == Mask2 ) ) { if ( Subtarget -> hasDSP ( ) && ( Mask2 == <NUM_LIT> || Mask2 == <NUM_LIT> ) ) return SDValue ( ) ;

unsigned lsb = countTrailingZeros ( Mask ) ;


<s> SelectionDAG & DAG = DCI . DAG ; if ( ! isS16 ( OpS16 , DAG ) && ! isSRA16 ( OpS16 ) ) { OpS16 = OpS32 ; OpS32 = SMULLOHI -> getOperand ( <NUM_LIT> ) ; } SDLoc dl ( OR ) ; unsigned Opcode = <NUM_LIT> ; if ( isS16 ( OpS16 , DAG ) ) Opcode = <STR_LIT> ; else if ( isSRA16 ( OpS16 ) ) { Opcode = <STR_LIT> ; OpS16 = OpS16 -> getOperand ( <NUM_LIT> ) ; } else return SDValue ( ) ; SDValue Res = DAG . getNode ( Opcode , dl , <STR_LIT> , OpS32 , OpS16 ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( OR , <NUM_LIT> ) , Res ) ;


<s> } ; if ( ! ( IsFreelyInvertable ( N0 ) || IsFreelyInvertable ( N1 ) ) ) return SDValue ( ) ; SDValue NewN0 = DAG . getLogicalNOT ( DL , N0 , VT ) ; SDValue NewN1 = DAG . getLogicalNOT ( DL , N1 , VT ) ; SDValue And = DAG . getNode ( <STR_LIT> , DL , VT , NewN0 , NewN1 ) ; return DAG . getLogicalNOT ( DL , And , VT ) ;


<s> auto IsFreelyInvertable = [ & ] ( SDValue V ) { if ( V -> getOpcode ( ) == <STR_LIT> || V -> getOpcode ( ) == <STR_LIT> ) return CanInvertMVEVCMP ( V ) ; return false ; } ; if ( ! ( IsFreelyInvertable ( N0 ) || IsFreelyInvertable ( N1 ) ) ) return SDValue ( ) ; SDValue NewN0 = DAG . getLogicalNOT ( DL , N0 , VT ) ; SDValue NewN1 = DAG . getLogicalNOT ( DL , N1 , VT ) ;

SDValue And = DAG . getNode ( <STR_LIT> , DL , VT , NewN0 , NewN1 ) ;


<s> CC = cast < CondCodeSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> get ( ) ; TrueVal = N -> getOperand ( <NUM_LIT> ) ; FalseVal = N -> getOperand ( <NUM_LIT> ) ; } else { return SDValue ( ) ; } unsigned int Opcode = <NUM_LIT> ; if ( ( TrueVal -> getOpcode ( ) == <STR_LIT> || FalseVal -> getOpcode ( ) == <STR_LIT> ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { Opcode = <STR_LIT> ; if ( CC == <STR_LIT> ) std :: swap ( TrueVal , FalseVal ) ; } else if ( ( TrueVal -> getOpcode ( ) == <STR_LIT> || FalseVal -> getOpcode ( ) == <STR_LIT> ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { Opcode = <STR_LIT> ; if ( CC == <STR_LIT> ) std :: swap ( TrueVal , FalseVal ) ; } else if ( ( TrueVal -> getOpcode ( ) == <STR_LIT> || FalseVal -> getOpcode ( ) == <STR_LIT> ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { Opcode = <STR_LIT> ; if ( CC == <STR_LIT> ) std :: swap ( TrueVal , FalseVal ) ; } else if ( ( TrueVal -> getOpcode ( ) == <STR_LIT> || FalseVal -> getOpcode ( ) == <STR_LIT> ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { Opcode = <STR_LIT> ; if ( CC == <STR_LIT> ) std :: swap ( TrueVal , FalseVal ) ; } else return SDValue ( ) ; switch ( TrueVal -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : std :: swap ( LHS , RHS ) ; std :: swap ( TrueVal , FalseVal ) ; break ; } EVT VectorType = FalseVal -> getOperand ( <NUM_LIT> ) . getValueType ( ) ;

if ( VectorType != <STR_LIT> && VectorType != <STR_LIT> && VectorType != <STR_LIT> ) return SDValue ( ) ;


<s> } } if ( ST -> isThumb1Only ( ) && N -> getOpcode ( ) == <STR_LIT> && VT == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) -> hasOneUse ( ) ) { if ( DCI . isBeforeLegalize ( ) || DCI . isCalledByLegalizer ( ) ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * ShiftAmtNode = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! ShiftAmtNode ) return SDValue ( ) ; uint32_t ShiftAmt = static_cast < uint32_t > ( ShiftAmtNode -> getZExtValue ( ) ) ; ConstantSDNode * AndMaskNode = dyn_cast < ConstantSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; if ( ! AndMaskNode ) return SDValue ( ) ; uint32_t AndMask = static_cast < uint32_t > ( AndMaskNode -> getZExtValue ( ) ) ; if ( AndMask == <NUM_LIT> || AndMask == <NUM_LIT> ) return SDValue ( ) ; if ( isMask_32 ( AndMask ) ) { uint32_t MaskedBits = countLeadingZeros ( AndMask ) ; if ( MaskedBits > ShiftAmt ) { SDLoc DL ( N ) ; SDValue SHL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( MaskedBits , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SHL , DAG . getConstant ( MaskedBits - ShiftAmt , DL , <STR_LIT> ) ) ; } } } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! VT . isVector ( ) || ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( ST -> hasMVEIntegerOps ( ) && VT == <STR_LIT> ) return SDValue ( ) ; int64_t Cnt ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ;


<s> } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! VT . isVector ( ) || ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( ST -> hasMVEIntegerOps ( ) && VT == <STR_LIT> ) return SDValue ( ) ; int64_t Cnt ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , Cnt ) ) { SDLoc dl ( N ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , dl , <STR_LIT> ) ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , false , Cnt ) ) { unsigned VShiftOpc = ( N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SDLoc dl ( N ) ; return DAG . getNode ( VShiftOpc , dl , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , dl , <STR_LIT> ) ) ;


<s> if ( DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; if ( ST -> isThumb ( ) && ST -> isThumb1Only ( ) ) return SDValue ( ) ; for ( auto U : N -> uses ( ) ) { switch ( U -> getOpcode ( ) ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isa < ConstantSDNode > ( U -> getOperand ( <NUM_LIT> ) ) || isa < ConstantSDNode > ( U -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; break ; } } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue SHL = N -> getOperand ( <NUM_LIT> ) ; auto * C1ShlC2 = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; auto * C2 = dyn_cast < ConstantSDNode > ( SHL . getOperand ( <NUM_LIT> ) ) ; if ( ! C1ShlC2 || ! C2 ) return SDValue ( ) ;


<s> if ( isVMOVNTruncMask ( N -> getMask ( ) , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; else if ( isVMOVNTruncMask ( N -> getMask ( ) , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return SDValue ( ) ;


<s> if ( Trunc . getOpcode ( ) != <STR_LIT> || ! N -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) return SDValue ( ) ; SDLoc DL ( Trunc ) ; if ( isVMOVNTruncMask ( N -> getMask ( ) , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; else if ( isVMOVNTruncMask ( N -> getMask ( ) , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> static SDValue PerformSignExtendInregCombine ( SDNode * N , SelectionDAG & DAG ) { SDValue Op = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( Op . getOpcode ( ) == <STR_LIT> && cast < VTSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) == Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; return SDValue ( ) ;


<s> <STR_LIT> NewExtType = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( LD -> getExtensionType ( ) != <STR_LIT> && LD -> getExtensionType ( ) != <STR_LIT> && LD -> getExtensionType ( ) != NewExtType ) return SDValue ( ) ; LLVMContext & C = * DAG . getContext ( ) ; SDLoc DL ( LD ) ; SDValue Ch = LD -> getChain ( ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; Align Alignment = LD -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = LD -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = LD -> getAAInfo ( ) ; SDValue Offset = DAG . getUNDEF ( BasePtr . getValueType ( ) ) ; EVT NewFromVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , FromEltVT . getScalarSizeInBits ( ) ) , NumElements ) ; EVT NewToVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , ToEltVT . getScalarSizeInBits ( ) ) , NumElements ) ; SmallVector < SDValue , <NUM_LIT> > Loads ; SmallVector < SDValue , <NUM_LIT> > Chains ; for ( unsigned i = <NUM_LIT> ; i < FromVT . getVectorNumElements ( ) / NumElements ; i ++ ) { unsigned NewOffset = ( i * NewFromVT . getSizeInBits ( ) ) / <NUM_LIT> ; SDValue NewPtr = DAG . getObjectPtrOffset ( DL , BasePtr , TypeSize :: Fixed ( NewOffset ) ) ; SDValue NewLoad = DAG . getLoad ( <STR_LIT> , NewExtType , NewToVT , DL , Ch , NewPtr , Offset , LD -> getPointerInfo ( ) . getWithOffset ( NewOffset ) , NewFromVT , Alignment , MMOFlags , AAInfo ) ; Loads . push_back ( NewLoad ) ; Chains . push_back ( SDValue ( NewLoad . getNode ( ) , <NUM_LIT> ) ) ; }

SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chains ) ;


<s> SDValue BasePtr = LD -> getBasePtr ( ) ; Align Alignment = LD -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = LD -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = LD -> getAAInfo ( ) ; SDValue Offset = DAG . getUNDEF ( BasePtr . getValueType ( ) ) ; EVT NewFromVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , FromEltVT . getScalarSizeInBits ( ) ) , NumElements ) ; EVT NewToVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , ToEltVT . getScalarSizeInBits ( ) ) , NumElements ) ; SmallVector < SDValue , <NUM_LIT> > Loads ; SmallVector < SDValue , <NUM_LIT> > Chains ; for ( unsigned i = <NUM_LIT> ; i < FromVT . getVectorNumElements ( ) / NumElements ; i ++ ) { unsigned NewOffset = ( i * NewFromVT . getSizeInBits ( ) ) / <NUM_LIT> ; SDValue NewPtr = DAG . getObjectPtrOffset ( DL , BasePtr , TypeSize :: Fixed ( NewOffset ) ) ; SDValue NewLoad = DAG . getLoad ( <STR_LIT> , NewExtType , NewToVT , DL , Ch , NewPtr , Offset , LD -> getPointerInfo ( ) . getWithOffset ( NewOffset ) , NewFromVT , Alignment , MMOFlags , AAInfo ) ; Loads . push_back ( NewLoad ) ; Chains . push_back ( SDValue ( NewLoad . getNode ( ) , <NUM_LIT> ) ) ; }


<s> Align Alignment = St -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = St -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = St -> getAAInfo ( ) ; EVT NewToVT = EVT :: getVectorVT ( C , ToVT . getVectorElementType ( ) , FromVT . getVectorNumElements ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Stores ; for ( unsigned i = <NUM_LIT> ; i < Trunc . getNumOperands ( ) ; i ++ ) { unsigned NewOffset = i * FromVT . getVectorNumElements ( ) * ToVT . getScalarSizeInBits ( ) / <NUM_LIT> ; SDValue NewPtr = DAG . getObjectPtrOffset ( DL , BasePtr , TypeSize :: Fixed ( NewOffset ) ) ; SDValue Extract = Trunc . getOperand ( i ) ; SDValue Store = DAG . getTruncStore ( Ch , DL , Extract , NewPtr , St -> getPointerInfo ( ) . getWithOffset ( NewOffset ) , NewToVT , Alignment . value ( ) , MMOFlags , AAInfo ) ;


SmallVector < SDValue , <NUM_LIT> > Stores ;


<s> EVT NewFromVT = EVT :: getVectorVT ( C , FromEltVT , NumElements ) ; EVT NewToVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , ToEltVT . getSizeInBits ( ) ) , NumElements ) ; SmallVector < SDValue , <NUM_LIT> > Stores ; for ( unsigned i = <NUM_LIT> ; i < FromVT . getVectorNumElements ( ) / NumElements ; i ++ ) { unsigned NewOffset = i * NumElements * ToEltVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue NewPtr = DAG . getObjectPtrOffset ( DL , BasePtr , TypeSize :: Fixed ( NewOffset ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , DL , NewFromVT , Trunc . getOperand ( <NUM_LIT> ) , DAG . getConstant ( i * NumElements , DL , <STR_LIT> ) ) ; SDValue FPTrunc = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , Extract , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Extract = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FPTrunc ) ; SDValue Store = DAG . getTruncStore ( Ch , DL , Extract , NewPtr , St -> getPointerInfo ( ) . getWithOffset ( NewOffset ) , NewToVT , Alignment . value ( ) , MMOFlags , AAInfo ) ; Stores . push_back ( Store ) ;


<s> if ( ToEltVT == <STR_LIT> && FromEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( ToEltVT == <STR_LIT> && FromEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( NumElements == <NUM_LIT> || ( FromEltVT != <STR_LIT> && FromVT . getVectorNumElements ( ) == NumElements ) || FromVT . getVectorNumElements ( ) % NumElements != <NUM_LIT> || ! isPowerOf2_32 ( NumElements ) ) return SDValue ( ) ; LLVMContext & C = * DAG . getContext ( ) ; SDLoc DL ( LD ) ; SDValue Ch = LD -> getChain ( ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; Align Alignment = LD -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = LD -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = LD -> getAAInfo ( ) ; <STR_LIT> NewExtType = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Offset = DAG . getUNDEF ( BasePtr . getValueType ( ) ) ; EVT NewFromVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , FromEltVT . getScalarSizeInBits ( ) ) , NumElements ) ;

EVT NewToVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , ToEltVT . getScalarSizeInBits ( ) ) , NumElements ) ;


<s> if ( N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; LoadSDNode * LD = cast < LoadSDNode > ( N0 . getNode ( ) ) ; if ( ! LD -> isSimple ( ) || ! N0 . hasOneUse ( ) || LD -> isIndexed ( ) || LD -> getExtensionType ( ) != <STR_LIT> ) return SDValue ( ) ; EVT FromVT = LD -> getValueType ( <NUM_LIT> ) ; EVT ToVT = N -> getValueType ( <NUM_LIT> ) ; if ( ! ToVT . isVector ( ) ) return SDValue ( ) ; assert ( FromVT . getVectorNumElements ( ) == ToVT . getVectorNumElements ( ) ) ; EVT ToEltVT = ToVT . getVectorElementType ( ) ; EVT FromEltVT = FromVT . getVectorElementType ( ) ; unsigned NumElements = <NUM_LIT> ; if ( ToEltVT == <STR_LIT> && FromEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( ToEltVT == <STR_LIT> && FromEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( NumElements == <NUM_LIT> || ( FromEltVT != <STR_LIT> && FromVT . getVectorNumElements ( ) == NumElements ) || FromVT . getVectorNumElements ( ) % NumElements != <NUM_LIT> || ! isPowerOf2_32 ( NumElements ) ) return SDValue ( ) ; LLVMContext & C = * DAG . getContext ( ) ; SDLoc DL ( LD ) ;


SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> if ( VMov -> getOpcode ( ) != <STR_LIT> || ! isZeroVector ( VMov ) ) return SDValue ( ) ; SDLoc dl ( N ) ; SDValue Negate = DCI . DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DCI . DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , VDup -> getOperand ( <NUM_LIT> ) ) ; return DCI . DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , Negate ) ;


<s> SDValue VDup = N -> getOperand ( <NUM_LIT> ) ; if ( VDup -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue VMov = N -> getOperand ( <NUM_LIT> ) ; if ( VMov -> getOpcode ( ) == <STR_LIT> ) VMov = VMov -> getOperand ( <NUM_LIT> ) ; if ( VMov -> getOpcode ( ) != <STR_LIT> || ! isZeroVector ( VMov ) ) return SDValue ( ) ; SDLoc dl ( N ) ; SDValue Negate = DCI . DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DCI . DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , VDup -> getOperand ( <NUM_LIT> ) ) ; return DCI . DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , Negate ) ;


<s> if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> || ! isNullConstant ( N -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue CSINC = N -> getOperand ( <NUM_LIT> ) ; if ( CSINC . getOpcode ( ) != <STR_LIT> || ! CSINC . hasOneUse ( ) ) return SDValue ( ) ;

ConstantSDNode * X = dyn_cast < ConstantSDNode > ( CSINC . getOperand ( <NUM_LIT> ) ) ;


<s> ConstantSDNode * X = dyn_cast < ConstantSDNode > ( CSINC . getOperand ( <NUM_LIT> ) ) ; if ( ! X ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , CSINC . getOperand ( <NUM_LIT> ) ) , CSINC . getOperand ( <NUM_LIT> ) , CSINC . getOperand ( <NUM_LIT> ) , CSINC . getOperand ( <NUM_LIT> ) ) ;


<s> static SDValue PerformUMLALCombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { if ( ! Subtarget -> hasV6Ops ( ) || ! Subtarget -> hasDSP ( ) ) return SDValue ( ) ; SDNode * AddcNode = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; SDNode * AddeNode = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( ( AddcNode -> getOpcode ( ) == <STR_LIT> ) && ( AddeNode -> getOpcode ( ) == <STR_LIT> ) && isNullConstant ( AddeNode -> getOperand ( <NUM_LIT> ) ) && isNullConstant ( AddeNode -> getOperand ( <NUM_LIT> ) ) && ( AddeNode -> getOperand ( <NUM_LIT> ) . getNode ( ) == AddcNode ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , AddcNode -> getOperand ( <NUM_LIT> ) , AddcNode -> getOperand ( <NUM_LIT> ) } ) ;


<s> if ( isZeroVector ( Op0 ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Op1 , DAG . getConstant ( SwappedCond , dl , <STR_LIT> ) ) ; if ( Op0 -> getOpcode ( ) == <STR_LIT> && Op1 -> getOpcode ( ) != <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Op1 , Op0 , DAG . getConstant ( SwappedCond , dl , <STR_LIT> ) ) ;


<s> uint32_t FloatBits = FloatTy . getSizeInBits ( ) ; MVT IntTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; uint32_t IntBits = IntTy . getSizeInBits ( ) ; unsigned NumLanes = Op . getValueType ( ) . getVectorNumElements ( ) ; if ( FloatBits != <NUM_LIT> || IntBits > <NUM_LIT> || ( NumLanes != <NUM_LIT> && NumLanes != <NUM_LIT> ) ) { return SDValue ( ) ; } BitVector UndefElements ; BuildVectorSDNode * BV = cast < BuildVectorSDNode > ( ConstVec ) ; int32_t C = BV -> getConstantFPSplatPow2ToLog2Int ( & UndefElements , <NUM_LIT> ) ; if ( C == - <NUM_LIT> || C == <NUM_LIT> || C > <NUM_LIT> ) return SDValue ( ) ; SDLoc dl ( N ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> ; unsigned IntrinsicOpcode = isSigned ? <STR_LIT> : <STR_LIT> ; SDValue FixConv = DAG . getNode ( <STR_LIT> , dl , NumLanes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> , DAG . getConstant ( IntrinsicOpcode , dl , <STR_LIT> ) , Op -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( C , dl , <STR_LIT> ) ) ; if ( IntBits < FloatBits ) FixConv = DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , FixConv ) ;


<s> unsigned NumLanes = Op . getValueType ( ) . getVectorNumElements ( ) ; if ( FloatBits != <NUM_LIT> || IntBits > <NUM_LIT> || ( NumLanes != <NUM_LIT> && NumLanes != <NUM_LIT> ) ) { return SDValue ( ) ; } BitVector UndefElements ; BuildVectorSDNode * BV = cast < BuildVectorSDNode > ( ConstVec ) ; int32_t C = BV -> getConstantFPSplatPow2ToLog2Int ( & UndefElements , <NUM_LIT> ) ; if ( C == - <NUM_LIT> || C == <NUM_LIT> || C > <NUM_LIT> ) return SDValue ( ) ; SDLoc dl ( N ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> ; unsigned IntrinsicOpcode = isSigned ? <STR_LIT> : <STR_LIT> ;

SDValue FixConv = DAG . getNode ( <STR_LIT> , dl , NumLanes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> , DAG . getConstant ( IntrinsicOpcode , dl , <STR_LIT> ) , Op -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( C , dl , <STR_LIT> ) ) ;


<s> MVT FloatTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; uint32_t FloatBits = FloatTy . getSizeInBits ( ) ; MVT IntTy = Op . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getVectorElementType ( ) ; uint32_t IntBits = IntTy . getSizeInBits ( ) ; unsigned NumLanes = Op . getValueType ( ) . getVectorNumElements ( ) ; if ( FloatBits != <NUM_LIT> || IntBits > <NUM_LIT> || ( NumLanes != <NUM_LIT> && NumLanes != <NUM_LIT> ) ) { return SDValue ( ) ; } BitVector UndefElements ; BuildVectorSDNode * BV = cast < BuildVectorSDNode > ( ConstVec ) ; int32_t C = BV -> getConstantFPSplatPow2ToLog2Int ( & UndefElements , <NUM_LIT> ) ; if ( C == - <NUM_LIT> || C == <NUM_LIT> || C > <NUM_LIT> ) return SDValue ( ) ; SDLoc dl ( N ) ; bool isSigned = OpOpcode == <STR_LIT> ; SDValue ConvInput = Op . getOperand ( <NUM_LIT> ) ; if ( IntBits < FloatBits ) ConvInput = DAG . getNode ( isSigned ? <STR_LIT> : <STR_LIT> , dl , NumLanes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> , ConvInput ) ; unsigned IntrinsicOpcode = isSigned ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getConstant ( IntrinsicOpcode , dl , <STR_LIT> ) , ConvInput , DAG . getConstant ( C , dl , <STR_LIT> ) ) ;


<s> SDLoc dl ( N ) ; if ( Subtarget -> hasMVEIntegerOps ( ) ) { if ( Op . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ) ; else if ( Op . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ) ; } if ( ! Subtarget -> hasNEON ( ) ) return SDValue ( ) ; LoadSDNode * LD = dyn_cast < LoadSDNode > ( Op . getNode ( ) ) ; if ( LD && Op . hasOneUse ( ) && LD -> isUnindexed ( ) && LD -> getMemoryVT ( ) == N -> getValueType ( <NUM_LIT> ) . getVectorElementType ( ) ) { SDValue Ops [ ] = { LD -> getOperand ( <NUM_LIT> ) , LD -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( LD -> getAlignment ( ) , SDLoc ( N ) , <STR_LIT> ) } ;

SDVTList SDTys = DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ;


<s> SDLoc dl ( N ) ; if ( ST -> isLittle ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Op ) ; if ( Op . isUndef ( ) ) return DAG . getUNDEF ( VT ) ; if ( Op -> getOpcode ( ) == <STR_LIT> ) {

if ( Op -> getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) return Op -> getOperand ( <NUM_LIT> ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; SDLoc dl ( N ) ; if ( ST -> isLittle ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Op ) ; if ( Op . isUndef ( ) ) return DAG . getUNDEF ( VT ) ; if ( Op -> getOpcode ( ) == <STR_LIT> ) { if ( Op -> getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) return Op -> getOperand ( <NUM_LIT> ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , Op -> getOperand ( <NUM_LIT> ) ) ;


<s> if ( ! TLI . isTypeLegal ( VT ) || ! TLI . isTypeLegal ( Concat0Op1 . getValueType ( ) ) || ! TLI . isTypeLegal ( Concat1Op1 . getValueType ( ) ) ) return SDValue ( ) ; SDValue NewConcat = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 . getOperand ( <NUM_LIT> ) , Op1 . getOperand ( <NUM_LIT> ) ) ; SmallVector < int , <NUM_LIT> > NewMask ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned HalfElts = NumElts / <NUM_LIT> ; ShuffleVectorSDNode * SVN = cast < ShuffleVectorSDNode > ( N ) ; for ( unsigned n = <NUM_LIT> ; n < NumElts ; ++ n ) { int MaskElt = SVN -> getMaskElt ( n ) ;


<s> SDValue Load = DCI . DAG . getLoad ( N -> getValueType ( <NUM_LIT> ) , SDLoc ( N ) , LN0 -> getChain ( ) , LN0 -> getBasePtr ( ) , LN0 -> getMemOperand ( ) ) ; DCI . DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; DCI . DAG . ReplaceAllUsesOfValueWith ( Op0 . getValue ( <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; return Load ; } } APInt DemandedMask = APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; const TargetLowering & TLI = DCI . DAG . getTargetLoweringInfo ( ) ; if ( TLI . SimplifyDemandedBits ( Op0 , DemandedMask , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; return SDValue ( ) ;


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; unsigned IsTop = N -> getConstantOperandVal ( <NUM_LIT> ) ; if ( Op1 -> isUndef ( ) ) return Op0 ; if ( Op0 -> isUndef ( ) && ! IsTop ) return Op1 ; if ( ( Op1 -> getOpcode ( ) == <STR_LIT> || Op1 -> getOpcode ( ) == <STR_LIT> ) && Op1 -> getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> ) return DCI . DAG . getNode ( Op1 -> getOpcode ( ) , SDLoc ( Op1 ) , N -> getValueType ( <NUM_LIT> ) , Op0 , Op1 -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; unsigned NumElts = N -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) ; APInt Op1DemandedElts = APInt :: getSplat ( NumElts , APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ;

APInt Op0DemandedElts = IsTop ? Op1DemandedElts : APInt :: getSplat ( NumElts , APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ;


<s> if ( Op1 -> isUndef ( ) ) return Op0 ; if ( Op0 -> isUndef ( ) && ! IsTop ) return Op1 ; if ( ( Op1 -> getOpcode ( ) == <STR_LIT> || Op1 -> getOpcode ( ) == <STR_LIT> ) && Op1 -> getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> ) return DCI . DAG . getNode ( Op1 -> getOpcode ( ) , SDLoc ( Op1 ) , N -> getValueType ( <NUM_LIT> ) , Op0 , Op1 -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; unsigned NumElts = N -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) ; APInt Op1DemandedElts = APInt :: getSplat ( NumElts , APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ; APInt Op0DemandedElts = IsTop ? Op1DemandedElts : APInt :: getSplat ( NumElts , APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ; APInt KnownUndef , KnownZero ; const TargetLowering & TLI = DCI . DAG . getTargetLoweringInfo ( ) ; if ( TLI . SimplifyDemandedVectorElts ( Op0 , Op0DemandedElts , KnownUndef , KnownZero , DCI ) ) return SDValue ( N , <NUM_LIT> ) ;

if ( TLI . SimplifyDemandedVectorElts ( Op1 , Op1DemandedElts , KnownUndef , KnownZero , DCI ) ) return SDValue ( N , <NUM_LIT> ) ;


<s> return DAG . getConstant ( V . bitcastToAPInt ( ) . getZExtValue ( ) , SDLoc ( N ) , VT ) ; } if ( <STR_LIT> ( N0 . getNode ( ) ) && N0 . hasOneUse ( ) ) { LoadSDNode * LN0 = cast < LoadSDNode > ( N0 ) ; SDValue Load = DAG . getExtLoad ( <STR_LIT> , SDLoc ( N ) , VT , LN0 -> getChain ( ) , LN0 -> getBasePtr ( ) , <STR_LIT> , LN0 -> getMemOperand ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( N0 . getValue ( <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; return Load ; } if ( N0 -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N0 -> getOperand ( <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> ) ) ; return SDValue ( ) ;


<s> LoadSDNode * LN0 = cast < LoadSDNode > ( N0 ) ; SDValue Load = DAG . getExtLoad ( <STR_LIT> , SDLoc ( N ) , VT , LN0 -> getChain ( ) , LN0 -> getBasePtr ( ) , <STR_LIT> , LN0 -> getMemOperand ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( N0 . getValue ( <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ;


<s> SDValue NewLD1 = DAG . getLoad ( <STR_LIT> , DL , LD -> getChain ( ) , BasePtr , LD -> getPointerInfo ( ) , LD -> getAlignment ( ) , LD -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue NewLD2 = DAG . getLoad ( <STR_LIT> , DL , LD -> getChain ( ) , OffsetPtr , LD -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , std :: min ( <NUM_LIT> , LD -> getAlignment ( ) ) , LD -> getMemOperand ( ) -> getFlags ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , NewLD2 . getValue ( <NUM_LIT> ) ) ; if ( DCI . DAG . getDataLayout ( ) . isBigEndian ( ) ) std :: swap ( NewLD1 , NewLD2 ) ; SDValue Result = DCI . CombineTo ( N , NewLD1 , NewLD2 ) ; return Result ; } if ( InDouble . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( InDouble . getOperand ( <NUM_LIT> ) ) ) { SDValue BV = InDouble . getOperand ( <NUM_LIT> ) ; bool BVSwap = BV . getOpcode ( ) == <STR_LIT> ; while ( ( BV . getOpcode ( ) == <STR_LIT> || BV . getOpcode ( ) == <STR_LIT> ) && ( BV . getValueType ( ) == <STR_LIT> || BV . getValueType ( ) == <STR_LIT> ) ) { BVSwap = BV . getOpcode ( ) == <STR_LIT> ; BV = BV . getOperand ( <NUM_LIT> ) ; } if ( BV . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned Offset = InDouble . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( BV . getOpcode ( ) == <STR_LIT> ) { SDValue Op0 = BV . getOperand ( Offset ) ; SDValue Op1 = BV . getOperand ( Offset + <NUM_LIT> ) ; if ( ! Subtarget -> isLittle ( ) && BVSwap ) std :: swap ( Op0 , Op1 ) ; return DCI . DAG . getMergeValues ( { Op0 , Op1 } , SDLoc ( N ) ) ; } SDValue Op0 , Op1 ; while ( BV . getOpcode ( ) == <STR_LIT> ) {

if ( isa < ConstantSDNode > ( BV . getOperand ( <NUM_LIT> ) ) ) {


<s> MVT ScalarType ; int ShftAmt = <NUM_LIT> ; switch ( Clamp -> getSExtValue ( ) ) { case ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> : ScalarType = <STR_LIT> ; ShftAmt = <NUM_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> : ScalarType = <STR_LIT> ; ShftAmt = <NUM_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> : ScalarType = <STR_LIT> ; ShftAmt = <NUM_LIT> ; break ; default : return SDValue ( ) ; } if ( Shft . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * N1 = isConstOrConstSplat ( Shft . getOperand ( <NUM_LIT> ) ) ; if ( ! N1 || N1 -> getSExtValue ( ) != ShftAmt ) return SDValue ( ) ; SDValue Mul = Shft . getOperand ( <NUM_LIT> ) ; if ( Mul . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Ext0 = Mul . getOperand ( <NUM_LIT> ) ; SDValue Ext1 = Mul . getOperand ( <NUM_LIT> ) ; if ( Ext0 . getOpcode ( ) != <STR_LIT> || Ext1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT VecVT = Ext0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ! VecVT . isPow2VectorType ( ) || VecVT . getVectorNumElements ( ) == <NUM_LIT> ) return SDValue ( ) ; if ( Ext1 . getOperand ( <NUM_LIT> ) . getValueType ( ) != VecVT || VecVT . getScalarType ( ) != ScalarType || VT . getScalarSizeInBits ( ) < ScalarType . getScalarSizeInBits ( ) * <NUM_LIT> ) return SDValue ( ) ;


<s> case ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> : ScalarType = <STR_LIT> ; ShftAmt = <NUM_LIT> ; break ; default : return SDValue ( ) ; } if ( Shft . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * N1 = isConstOrConstSplat ( Shft . getOperand ( <NUM_LIT> ) ) ; if ( ! N1 || N1 -> getSExtValue ( ) != ShftAmt ) return SDValue ( ) ; SDValue Mul = Shft . getOperand ( <NUM_LIT> ) ; if ( Mul . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Ext0 = Mul . getOperand ( <NUM_LIT> ) ; SDValue Ext1 = Mul . getOperand ( <NUM_LIT> ) ; if ( Ext0 . getOpcode ( ) != <STR_LIT> || Ext1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT VecVT = Ext0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ! VecVT . isPow2VectorType ( ) || VecVT . getVectorNumElements ( ) == <NUM_LIT> ) return SDValue ( ) ; if ( Ext1 . getOperand ( <NUM_LIT> ) . getValueType ( ) != VecVT || VecVT . getScalarType ( ) != ScalarType || VT . getScalarSizeInBits ( ) < ScalarType . getScalarSizeInBits ( ) * <NUM_LIT> ) return SDValue ( ) ; SDLoc DL ( Mul ) ; unsigned LegalLanes = <NUM_LIT> / ( ShftAmt + <NUM_LIT> ) ; EVT LegalVecVT = <STR_LIT> ( ScalarType , LegalLanes ) ; if ( VecVT . getSizeInBits ( ) < <NUM_LIT> ) { EVT ExtVecVT = <STR_LIT> ( <STR_LIT> ( <NUM_LIT> / VecVT . getVectorNumElements ( ) ) , VecVT . getVectorNumElements ( ) ) ; SDValue Inp0 = DAG . getNode ( <STR_LIT> , DL , ExtVecVT , Ext0 . getOperand ( <NUM_LIT> ) ) ; SDValue Inp1 = DAG . getNode ( <STR_LIT> , DL , ExtVecVT , Ext1 . getOperand ( <NUM_LIT> ) ) ; Inp0 = DAG . getNode ( <STR_LIT> , DL , LegalVecVT , Inp0 ) ; Inp1 = DAG . getNode ( <STR_LIT> , DL , LegalVecVT , Inp1 ) ; SDValue VQDMULH = DAG . getNode ( <STR_LIT> , DL , LegalVecVT , Inp0 , Inp1 ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , DL , ExtVecVT , VQDMULH ) ; Trunc = DAG . getNode ( <STR_LIT> , DL , VecVT , Trunc ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Trunc ) ; }

assert ( VecVT . getSizeInBits ( ) % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ;


<s> static SDValue PerformVQMOVNCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI ) { SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; unsigned IsTop = N -> getConstantOperandVal ( <NUM_LIT> ) ;

unsigned NumElts = N -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) ;


<s> SDValue XOR = N -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * Const = isConstOrConstSplat ( XOR -> getOperand ( <NUM_LIT> ) , false , true ) ; if ( ! Const || ! Const -> isOne ( ) ) return SDValue ( ) ; SDValue Cond = XOR -> getOperand ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; EVT Type = N -> getValueType ( <NUM_LIT> ) ; return DCI . DAG . getNode ( <STR_LIT> , SDLoc ( N ) , Type , Cond , RHS , LHS ) ;


<s> if ( SDValue V = PerformVQDMULHCombine ( N , DCI . DAG ) ) return V ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue XOR = N -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * Const = isConstOrConstSplat ( XOR -> getOperand ( <NUM_LIT> ) , false , true ) ; if ( ! Const || ! Const -> isOne ( ) ) return SDValue ( ) ; SDValue Cond = XOR -> getOperand ( <NUM_LIT> ) ;

SDValue LHS = N -> getOperand ( <NUM_LIT> ) ;


<s> if ( Subtarget -> hasMVEIntegerOps ( ) ) { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; const TargetLowering * TLI = Subtarget -> getTargetLowering ( ) ; if ( TLI -> isConstTrueVal ( N1 . getNode ( ) ) && ( N0 -> getOpcode ( ) == <STR_LIT> || N0 -> getOpcode ( ) == <STR_LIT> ) ) { if ( CanInvertMVEVCMP ( N0 ) ) { SDLoc DL ( N0 ) ; <STR_LIT> CC = <STR_LIT> ( getVCMPCondCode ( N0 ) ) ;

SmallVector < SDValue , <NUM_LIT> > Ops ;


<s> if ( ! Subtarget -> hasNEON ( ) ) { if ( Subtarget -> isThumb1Only ( ) ) return VT . getScalarSizeInBits ( ) <= <NUM_LIT> ;


<s> bool <ISA_LIT>TargetLowering :: preferIncOfAddToSubOfNot ( EVT VT ) const {


<s> static SDValue PromoteMVEPredVector ( SDLoc dl , SDValue Pred , EVT VT , SelectionDAG & DAG ) { SDValue AllOnes = DAG . getTargetConstant ( <STR_LIT> ( <NUM_LIT> , <NUM_LIT> ) , dl , <STR_LIT> ) ; AllOnes = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AllOnes ) ; SDValue AllZeroes = DAG . getTargetConstant ( <STR_LIT> ( <NUM_LIT> , <NUM_LIT> ) , dl , <STR_LIT> ) ;

AllZeroes = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AllZeroes ) ;


<s> static SDValue PromoteMVEPredVector ( SDLoc dl , SDValue Pred , EVT VT , SelectionDAG & DAG ) { SDValue AllOnes = DAG . getTargetConstant ( <STR_LIT> ( <NUM_LIT> , <NUM_LIT> ) , dl , <STR_LIT> ) ; AllOnes = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AllOnes ) ; SDValue AllZeroes = DAG . getTargetConstant ( <STR_LIT> ( <NUM_LIT> , <NUM_LIT> ) , dl , <STR_LIT> ) ; AllZeroes = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AllZeroes ) ; EVT NewVT = getVectorTyFromPredicateVector ( VT ) ; SDValue RecastV1 ; if ( VT != <STR_LIT> ) RecastV1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Pred ) ; else RecastV1 = Pred ; SDValue PredAsVector = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RecastV1 , AllOnes , AllZeroes ) ;

return DAG . getNode ( <STR_LIT> , dl , NewVT , PredAsVector ) ;


<s> if ( ! AFI -> getGlobalsPromotedToConstantPool ( ) . count ( GVar ) && Size > <NUM_LIT> ) if ( AFI -> getPromotedConstpoolIncrease ( ) + PaddedSize - <NUM_LIT> >= ConstpoolPromotionMaxTotal ) return SDValue ( ) ; if ( ! allUsersAreInFunction ( GVar , & F ) ) return SDValue ( ) ; if ( RequiredPadding != <NUM_LIT> ) { StringRef S = CDAInit -> getAsString ( ) ; SmallVector < uint8_t , <NUM_LIT> > V ( S . size ( ) ) ; std :: copy ( S . bytes_begin ( ) , S . bytes_end ( ) , V . begin ( ) ) ; while ( RequiredPadding -- ) V . push_back ( <NUM_LIT> ) ; Init = ConstantDataArray :: get ( * DAG . getContext ( ) , V ) ; } auto CPVal = <ISA_LIT>ConstantPoolConstant :: Create ( GVar , Init ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPVal , PtrVT , Align ( <NUM_LIT> ) ) ; if ( ! AFI -> getGlobalsPromotedToConstantPool ( ) . count ( GVar ) ) { AFI -> markGlobalAsPromotedToConstantPool ( GVar ) ; AFI -> setPromotedConstpoolIncrease ( AFI -> getPromotedConstpoolIncrease ( ) + PaddedSize - <NUM_LIT> ) ;


<s> SDNode * CmpSwap = DAG . getMachineNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) , Ops ) ; MachineMemOperand * MemOp = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; DAG . setNodeMemRefs ( cast < MachineSDNode > ( CmpSwap ) , { MemOp } ) ; bool isBigEndian = DAG . getDataLayout ( ) . isBigEndian ( ) ; SDValue Lo = DAG . getTargetExtractSubreg ( isBigEndian ? <STR_LIT> : <STR_LIT> , SDLoc ( N ) , <STR_LIT> , SDValue ( CmpSwap , <NUM_LIT> ) ) ;

SDValue Hi = DAG . getTargetExtractSubreg ( isBigEndian ? <STR_LIT> : <STR_LIT> , SDLoc ( N ) , <STR_LIT> , SDValue ( CmpSwap , <NUM_LIT> ) ) ;


<s> static void ReplaceCMP_SWAP_64Results ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , createGPRPairNode ( DAG , N -> getOperand ( <NUM_LIT> ) ) , createGPRPairNode ( DAG , N -> getOperand ( <NUM_LIT> ) ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * CmpSwap = DAG . getMachineNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) , Ops ) ; MachineMemOperand * MemOp = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; DAG . setNodeMemRefs ( cast < MachineSDNode > ( CmpSwap ) , { MemOp } ) ; bool isBigEndian = DAG . getDataLayout ( ) . isBigEndian ( ) ; SDValue Lo = DAG . getTargetExtractSubreg ( isBigEndian ? <STR_LIT> : <STR_LIT> , SDLoc ( N ) , <STR_LIT> , SDValue ( CmpSwap , <NUM_LIT> ) ) ; SDValue Hi = DAG . getTargetExtractSubreg ( isBigEndian ? <STR_LIT> : <STR_LIT> , SDLoc ( N ) , <STR_LIT> , SDValue ( CmpSwap , <NUM_LIT> ) ) ;

Results . push_back ( DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Lo , Hi ) ) ;


<s> static void ReplaceLongIntrinsic ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) { unsigned IntNo = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned Opc = <NUM_LIT> ; if ( IntNo == <STR_LIT> ) Opc = <STR_LIT> ; else if ( IntNo == <STR_LIT> ) Opc = <STR_LIT> ; else if ( IntNo == <STR_LIT> ) Opc = <STR_LIT> ; else if ( IntNo == <STR_LIT> ) Opc = <STR_LIT> ; else return ; SDLoc dl ( N ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;

SDValue LongMul = DAG . getNode ( Opc , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Lo , Hi ) ;


<s> else return ; SDLoc dl ( N ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue LongMul = DAG . getNode ( Opc , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Lo , Hi ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LongMul . getValue ( <NUM_LIT> ) , LongMul . getValue ( <NUM_LIT> ) ) ) ;