<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> if ( ! Subtarget -> useConstIslands ( ) ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; } unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * DAG . getContext ( ) , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ;

SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( ) ; SDLoc dl ( Op ) ; if ( ! Subtarget -> useConstIslands ( ) ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; } unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * DAG . getContext ( ) , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ;

CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ;


<s> default : return SDValue ( ) ; case <STR_LIT> : { assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } case <STR_LIT> : { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; if ( RelocM == Reloc :: PIC_ ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; } return Result ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } }


<s> case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return DAG . getIntPtrConstant ( <NUM_LIT> * <NUM_LIT> ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , false ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; Chain = Argument . getValue ( <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , CPAddr ) ; } else { unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ; } ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Argument ;

Entry . Ty = ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , isVarArg ) ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , realArgIdx = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i , ++ realArgIdx ) { CCValAssign & VA = ArgLocs [ i ] ; EVT RegVT = VA . getLocVT ( ) ; SDValue Arg = OutVals [ realArgIdx ] ; <STR_LIT> Flags = Outs [ realArgIdx ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( VA . needsCustom ( ) ) { if ( ! VA . isRegLoc ( ) ) return false ; if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; if ( RegVT == <STR_LIT> ) { if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; } } else if ( ! VA . isRegLoc ( ) ) { if ( ! MatchingStackOffset ( Arg , VA . getLocMemOffset ( ) , Flags , MFI , MRI , TII ) ) return false ; } } } const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( ! parametersInCSRMatch ( MRI , CallerPreserved , ArgLocs , OutVals ) ) return false ; }


<s> const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } LLVMContext & C = * DAG . getContext ( ) ; if ( ! CCState :: resultsCompatible ( getEffectiveCallingConv ( CalleeCC , isVarArg ) , getEffectiveCallingConv ( CallerCC , CallerF . isVarArg ( ) ) , MF , C , Ins , CCAssignFnForReturn ( CalleeCC , isVarArg ) , CCAssignFnForReturn ( CallerCC , CallerF . isVarArg ( ) ) ) ) return false ; const <ISA_LIT>BaseRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( CalleeCC != CallerCC ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } const <ISA_LIT>FunctionInfo * AFI_Caller = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI_Caller -> getArgRegsSaveSize ( ) ) return false ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , isVarArg ) ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , realArgIdx = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i , ++ realArgIdx ) { CCValAssign & VA = ArgLocs [ i ] ; EVT RegVT = VA . getLocVT ( ) ; SDValue Arg = OutVals [ realArgIdx ] ; <STR_LIT> Flags = Outs [ realArgIdx ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( VA . needsCustom ( ) ) { if ( ! VA . isRegLoc ( ) ) return false ; if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; if ( RegVT == <STR_LIT> ) { if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; } } else if ( ! VA . isRegLoc ( ) ) { if ( ! MatchingStackOffset ( Arg , VA . getLocMemOffset ( ) , Flags , MFI , MRI , TII ) ) return false ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & dl , SelectionDAG & DAG ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , CCAssignFnForReturn ( CallConv , isVarArg ) ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ; bool isLittleEndian = Subtarget -> isLittle ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; AFI -> setReturnRegsCount ( RVLocs . size ( ) ) ; if ( AFI -> isCmseNSEntryFunction ( ) && MF . getFunction ( ) . hasStructRetAttr ( ) ) { DiagnosticInfoUnsupported Diag ( DAG . getMachineFunction ( ) . getFunction ( ) , <STR_LIT> , SDLoc ( ) . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( Diag ) ; } for ( unsigned i = <NUM_LIT> , realRVLocIdx = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i , ++ realRVLocIdx ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = OutVals [ realRVLocIdx ] ; bool ReturnF16 = false ; if ( Subtarget -> hasFullFP16 ( ) && Subtarget -> isTargetHardFloat ( ) ) { if ( Arg . getValueType ( ) == <STR_LIT> && Arg . getOpcode ( ) == <STR_LIT> ) { SDValue ZE = Arg . getOperand ( <NUM_LIT> ) ; if ( ZE . getOpcode ( ) == <STR_LIT> && ZE . getValueType ( ) == <STR_LIT> ) { SDValue BC = ZE . getOperand ( <NUM_LIT> ) ; if ( BC . getOpcode ( ) == <STR_LIT> && BC . getValueType ( ) == <STR_LIT> ) { Arg = BC . getOperand ( <NUM_LIT> ) ; ReturnF16 = true ; } } } } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : if ( ! ReturnF16 ) Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) {

SDValue Half = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;


<s> if ( LN0 -> hasOneUse ( ) && LN0 -> isUnindexed ( ) && LN0 -> getMemoryVT ( ) == <STR_LIT> ) { SDValue Load = DCI . DAG . getLoad ( <STR_LIT> , SDLoc ( N ) , LN0 -> getChain ( ) , LN0 -> getBasePtr ( ) , LN0 -> getMemOperand ( ) ) ; DCI . DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; DCI . DAG . ReplaceAllUsesOfValueWith ( Op0 . getValue ( <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; return Load ; } } APInt DemandedMask = APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; const TargetLowering & TLI = DCI . DAG . getTargetLoweringInfo ( ) ;

if ( TLI . SimplifyDemandedBits ( Op0 , DemandedMask , DCI ) ) return SDValue ( N , <NUM_LIT> ) ;


<s> if ( ! AFI -> getGlobalsPromotedToConstantPool ( ) . count ( GVar ) && Size > <NUM_LIT> ) if ( AFI -> getPromotedConstpoolIncrease ( ) + PaddedSize - <NUM_LIT> >= ConstpoolPromotionMaxTotal ) return SDValue ( ) ; if ( ! allUsersAreInFunction ( GVar , & F ) ) return SDValue ( ) ; if ( RequiredPadding != <NUM_LIT> ) { StringRef S = CDAInit -> getAsString ( ) ; SmallVector < uint8_t , <NUM_LIT> > V ( S . size ( ) ) ; std :: copy ( S . bytes_begin ( ) , S . bytes_end ( ) , V . begin ( ) ) ; while ( RequiredPadding -- ) V . push_back ( <NUM_LIT> ) ; Init = ConstantDataArray :: get ( * DAG . getContext ( ) , V ) ; } auto CPVal = <ISA_LIT>ConstantPoolConstant :: Create ( GVar , Init ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPVal , PtrVT , Align ( <NUM_LIT> ) ) ; if ( ! AFI -> getGlobalsPromotedToConstantPool ( ) . count ( GVar ) ) { AFI -> markGlobalAsPromotedToConstantPool ( GVar ) ; AFI -> setPromotedConstpoolIncrease ( AFI -> getPromotedConstpoolIncrease ( ) + PaddedSize - <NUM_LIT> ) ; } ++ NumConstpoolPromoted ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ;


<s> setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; for ( unsigned im = ( unsigned ) <STR_LIT> ; im != ( unsigned ) <STR_LIT> ; ++ im ) { setIndexedLoadAction ( im , VT , Legal ) ; setIndexedStoreAction ( im , VT , Legal ) ; } if ( HasMVEFP ) { setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; } } const MVT LongTypes [ ] = { <STR_LIT> , <STR_LIT> } ; for ( auto VT : LongTypes ) { addRegisterClass ( VT , & <STR_LIT> ) ; setAllExpand ( VT ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; addAllExtLoads ( <STR_LIT> , <STR_LIT> , Legal ) ; addAllExtLoads ( <STR_LIT> , <STR_LIT> , Legal ) ; addAllExtLoads ( <STR_LIT> , <STR_LIT> , Legal ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( unsigned im = ( unsigned ) <STR_LIT> ; im != ( unsigned ) <STR_LIT> ; ++ im ) { setIndexedLoadAction ( im , <STR_LIT> , Legal ) ; setIndexedStoreAction ( im , <STR_LIT> , Legal ) ;


<s> DAG . getTargetLoweringInfo ( ) . softenSetCCOperands ( DAG , LHS . getValueType ( ) , LHS , RHS , CC , dl , LHS , RHS ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) == <STR_LIT> ) { if ( Subtarget -> hasFP<ISA_LIT>v8Base ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { CC = <STR_LIT> ( CC , true ) ; std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; if ( cast < ConstantSDNode > ( <ISA_LIT>cc ) -> getZExtValue ( ) == <STR_LIT> ) <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; bool InvalidOnQNaN ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 , InvalidOnQNaN ) ; if ( Subtarget -> hasFP<ISA_LIT>v8Base ( ) && ! ( isFloatingPointZero ( RHS ) && TrueVal . getValueType ( ) != <STR_LIT> ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { bool swpCmpOps = false ; bool swpVselOps = false ; checkVSELConstraints ( CC , CondCode , swpCmpOps , swpVselOps ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { if ( swpCmpOps ) std :: swap ( LHS , RHS ) ; if ( swpVselOps ) std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl , InvalidOnQNaN ) ;


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; if ( isUnsupportedFloatingType ( LHS . getValueType ( ) ) ) { DAG . getTargetLoweringInfo ( ) . softenSetCCOperands ( DAG , LHS . getValueType ( ) , LHS , RHS , CC , dl , LHS , RHS ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) == <STR_LIT> ) { if ( Subtarget -> hasFP<ISA_LIT>v8Base ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { CC = <STR_LIT> ( CC , true ) ; std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; if ( cast < ConstantSDNode > ( <ISA_LIT>cc ) -> getZExtValue ( ) == <STR_LIT> ) <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; bool InvalidOnQNaN ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 , InvalidOnQNaN ) ; if ( Subtarget -> hasFP<ISA_LIT>v8Base ( ) && ! ( isFloatingPointZero ( RHS ) && TrueVal . getValueType ( ) != <STR_LIT> ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) {


<s> return CC == <STR_LIT> || CC == <STR_LIT> ;


<s> SDValue * K1 = isa < ConstantSDNode > ( LHS1 ) ? & LHS1 : isa < ConstantSDNode > ( RHS1 ) ? & RHS1 : NULL ; SDValue * K2 = isa < ConstantSDNode > ( LHS2 ) ? & LHS2 : isa < ConstantSDNode > ( RHS2 ) ? & RHS2 : NULL ; SDValue K2Tmp = isa < ConstantSDNode > ( TrueVal2 ) ? TrueVal2 : FalseVal2 ; SDValue V1Tmp = ( K1 && * K1 == LHS1 ) ? RHS1 : LHS1 ; SDValue V2Tmp = ( K2 && * K2 == LHS2 ) ? RHS2 : LHS2 ; SDValue V2 = ( K2Tmp == TrueVal2 ) ? FalseVal2 : TrueVal2 ; SDValue V2TmpReg = V2Tmp ; if ( V2Tmp -> getOpcode ( ) == <STR_LIT> ) V2TmpReg = V2Tmp -> getOperand ( <NUM_LIT> ) ; if ( ! K1 || ! K2 || * K1 == Op2 || * K2 != K2Tmp || V1Tmp != V2Tmp || V2TmpReg != V2 ) return false ; const SDValue * LowerCheckOp = isLowerSaturate ( LHS1 , RHS1 , TrueVal1 , FalseVal1 , CC1 , * K1 ) ? & Op : isLowerSaturate ( LHS2 , RHS2 , TrueVal2 , FalseVal2 , CC2 , * K2 ) ? & Op2 : NULL ; const SDValue * UpperCheckOp = isUpperSaturate ( LHS1 , RHS1 , TrueVal1 , FalseVal1 , CC1 , * K1 ) ? & Op : isUpperSaturate ( LHS2 , RHS2 , TrueVal2 , FalseVal2 , CC2 , * K2 ) ? & Op2 : NULL ;

if ( ! UpperCheckOp || ! LowerCheckOp || LowerCheckOp == UpperCheckOp ) return false ;


<s> <STR_LIT> CC2 = cast < CondCodeSDNode > ( Op2 . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue * K1 = isa < ConstantSDNode > ( LHS1 ) ? & LHS1 : isa < ConstantSDNode > ( RHS1 ) ? & RHS1 : NULL ; SDValue * K2 = isa < ConstantSDNode > ( LHS2 ) ? & LHS2 : isa < ConstantSDNode > ( RHS2 ) ? & RHS2 : NULL ; SDValue K2Tmp = isa < ConstantSDNode > ( TrueVal2 ) ? TrueVal2 : FalseVal2 ; SDValue V1Tmp = ( K1 && * K1 == LHS1 ) ? RHS1 : LHS1 ; SDValue V2Tmp = ( K2 && * K2 == LHS2 ) ? RHS2 : LHS2 ; SDValue V2 = ( K2Tmp == TrueVal2 ) ? FalseVal2 : TrueVal2 ; SDValue V2TmpReg = V2Tmp ; if ( V2Tmp -> getOpcode ( ) == <STR_LIT> ) V2TmpReg = V2Tmp -> getOperand ( <NUM_LIT> ) ; if ( ! K1 || ! K2 || * K1 == Op2 || * K2 != K2Tmp || V1Tmp != V2Tmp || V2TmpReg != V2 ) return false ; const SDValue * LowerCheckOp = isLowerSaturate ( LHS1 , RHS1 , TrueVal1 , FalseVal1 , CC1 , * K1 ) ? & Op : isLowerSaturate ( LHS2 , RHS2 , TrueVal2 , FalseVal2 , CC2 , * K2 ) ? & Op2 : NULL ; const SDValue * UpperCheckOp = isUpperSaturate ( LHS1 , RHS1 , TrueVal1 , FalseVal1 , CC1 , * K1 ) ? & Op : isUpperSaturate ( LHS2 , RHS2 , TrueVal2 , FalseVal2 , CC2 , * K2 ) ? & Op2 : NULL ; if ( ! UpperCheckOp || ! LowerCheckOp || LowerCheckOp == UpperCheckOp ) return false ; int64_t Val1 = cast < ConstantSDNode > ( * K1 ) -> getSExtValue ( ) ; int64_t Val2 = cast < ConstantSDNode > ( * K2 ) -> getSExtValue ( ) ; int64_t PosVal = std :: max ( Val1 , Val2 ) ; if ( ( ( Val1 > Val2 && UpperCheckOp == & Op ) || ( Val1 < Val2 && UpperCheckOp == & Op2 ) ) && Val1 == ~ Val2 && isPowerOf2_64 ( PosVal + <NUM_LIT> ) ) { V = V2 ; K = ( uint64_t ) PosVal ; return true ; } return false ;


<s> bool isUpperSaturate ( const SDValue LHS , const SDValue RHS , const SDValue TrueVal , const SDValue FalseVal , const <STR_LIT> CC , const SDValue K ) {

return ( isGTorGE ( CC ) && ( ( K == RHS && K == TrueVal ) || ( K == LHS && K == FalseVal ) ) ) || ( isLTorLE ( CC ) && ( ( K == LHS && K == TrueVal ) || ( K == RHS && K == FalseVal ) ) ) ;


<s> } if ( NumCopies != <NUM_LIT> && NumCopies != <NUM_LIT> ) return false ; bool HasRet = false ; for ( unsigned i = <NUM_LIT> ; i < NumCopies ; ++ i ) { SDNode * Copy = Copies [ i ] ; for ( SDNode :: use_iterator UI = Copy -> use_begin ( ) , UE = Copy -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) == <STR_LIT> ) { SDNode * Use = * UI ; if ( Use == Copies [ <NUM_LIT> ] || ( ( NumCopies == <NUM_LIT> ) && ( Use == Copies [ <NUM_LIT> ] ) ) ) continue ; return false ; }

if ( UI -> getOpcode ( ) != <STR_LIT> ) return false ;


<s> } else if ( Use -> getOpcode ( ) == <STR_LIT> ) { for ( SDNode :: use_iterator UI = Use -> use_begin ( ) , UE = Use -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != <STR_LIT> ) return false ; Copies [ UI . getUse ( ) . getResNo ( ) ] = * UI ; ++ NumCopies ; } } else if ( Use -> getOpcode ( ) == <STR_LIT> ) { if ( ! Use -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) return false ; Use = * Use -> use_begin ( ) ; if ( Use -> getOpcode ( ) != <STR_LIT> || ! Use -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) return false ; Copies [ NumCopies ++ ] = Use ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ;

case <STR_LIT> : return LowerMUL ( Op , DAG ) ;


<s> unsigned CPI = MCP -> getConstantPoolIndex ( CPV , <NUM_LIT> ) ; const TargetRegisterClass * TRC = isThumb ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; MachineMemOperand * CPMMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; MachineMemOperand * FIMMOSt = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; if ( isThumb2 ) { unsigned NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addMemOperand ( CPMMO ) ) ; unsigned NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultCC ( AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( <NUM_LIT> ) ) ) ; unsigned NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( NewVReg2 , RegState :: Kill ) . addImm ( PCLabelId ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( NewVReg3 , RegState :: Kill ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( FIMMOSt ) ) ;


<s> bool <ISA_LIT>TargetLowering :: shouldExpandShift ( SelectionDAG & DAG , SDNode * N ) const {


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> assert ( LD -> isUnindexed ( ) && <STR_LIT> ) ; if ( MemVT == <STR_LIT> && Subtarget -> hasV5TEOps ( ) && ! Subtarget -> isThumb1Only ( ) && LD -> isVolatile ( ) ) { SDLoc dl ( N ) ;

SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) , { LD -> getChain ( ) , LD -> getBasePtr ( ) } , MemVT , LD -> getMemOperand ( ) ) ;


<s> SDLoc dl ( N ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) , { LD -> getChain ( ) , LD -> getBasePtr ( ) } , MemVT , LD -> getMemOperand ( ) ) ;

SDValue Pair = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result . getValue ( <NUM_LIT> ) , Result . getValue ( <NUM_LIT> ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , true ) ; return LowerSDIV ( Op , DAG , Subtarget ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , false ) ; return LowerUDIV ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerADDSUBCARRY ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerSignedALUO ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerUnsignedALUO ( Op , DAG ) ; case <STR_LIT> :


<s> case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , true ) ; return LowerSDIV ( Op , DAG , Subtarget ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , false ) ; return LowerUDIV ( Op , DAG , Subtarget ) ; case <STR_LIT> :

case <STR_LIT> : return LowerADDSUBCARRY ( Op , DAG ) ;


<s> if ( MemVT == <STR_LIT> && Subtarget -> hasV5TEOps ( ) && ! Subtarget -> isThumb1Only ( ) && ST -> isVolatile ( ) ) { SDNode * N = Op . getNode ( ) ; SDLoc dl ( N ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ST -> getValue ( ) , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ST -> getValue ( ) , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;

return DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , { ST -> getChain ( ) , Lo , Hi , ST -> getBasePtr ( ) } , MemVT , ST -> getMemOperand ( ) ) ;


<s> void <ISA_LIT>TargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { unsigned BitWidth = Known . getBitWidth ( ) ; Known . resetAll ( ) ; switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Op . getResNo ( ) == <NUM_LIT> ) { SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; if ( Op -> getOpcode ( ) == <STR_LIT> && isNullConstant ( LHS ) && isNullConstant ( RHS ) ) { Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - <NUM_LIT> ) ; return ; } } break ; case <STR_LIT> : { Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; if ( Known . isUnknown ( ) ) return ; KnownBits KnownRHS = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; Known = KnownBits :: commonBits ( Known , KnownRHS ) ; return ; } case <STR_LIT> : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : case <STR_LIT> : { EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ;


<s> if ( Cmp -> getOpcode ( ) != <STR_LIT> || ! isNullConstant ( Cmp -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue CSInc = Cmp -> getOperand ( <NUM_LIT> ) ; while ( CSInc . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( CSInc . getOperand ( <NUM_LIT> ) ) && CSInc . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> && CSInc -> hasOneUse ( ) ) CSInc = CSInc . getOperand ( <NUM_LIT> ) ; if ( CSInc . getOpcode ( ) != <STR_LIT> || ! isNullConstant ( CSInc . getOperand ( <NUM_LIT> ) ) || ! isNullConstant ( CSInc . getOperand ( <NUM_LIT> ) ) || ! CSInc -> hasOneUse ( ) ) return SDValue ( ) ; CC = ( <STR_LIT> ) CSInc . getConstantOperandVal ( <NUM_LIT> ) ; return CSInc . getOperand ( <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : { const SDValue & SrcSV = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = SrcSV . getValueType ( ) ; assert ( VecVT . isVector ( ) && <STR_LIT> ) ; const unsigned NumSrcElts = VecVT . getVectorNumElements ( ) ; ConstantSDNode * Pos = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; assert ( Pos -> getAPIntValue ( ) . ult ( NumSrcElts ) && <STR_LIT> ) ; unsigned Idx = Pos -> getZExtValue ( ) ; APInt DemandedElt = APInt :: getOneBitSet ( NumSrcElts , Idx ) ; Known = DAG . computeKnownBits ( SrcSV , DemandedElt , Depth + <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; const unsigned DstSz = VT . getScalarSizeInBits ( ) ; const unsigned SrcSz = VecVT . getVectorElementType ( ) . getSizeInBits ( ) ; ( void ) SrcSz ; assert ( SrcSz == Known . getBitWidth ( ) ) ; assert ( DstSz > SrcSz ) ;

if ( Op . getOpcode ( ) == <STR_LIT> ) Known = Known . sext ( DstSz ) ;


<s> SmallVector < StringRef , <NUM_LIT> > AsmPieces ; SplitString ( AsmStr , AsmPieces , <STR_LIT> ) ; switch ( AsmPieces . size ( ) ) { default : return false ; case <NUM_LIT> : AsmStr = std :: string ( AsmPieces [ <NUM_LIT> ] ) ; AsmPieces . clear ( ) ; SplitString ( AsmStr , AsmPieces , <STR_LIT> ) ; if ( AsmPieces . size ( ) == <NUM_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && IA -> getConstraintString ( ) . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) { IntegerType * Ty = dyn_cast < IntegerType > ( CI -> getType ( ) ) ; if ( Ty && Ty -> getBitWidth ( ) == <NUM_LIT> ) return IntrinsicLowering :: LowerToByteSwap ( CI ) ;


<s> SplitString ( AsmStr , AsmPieces , <STR_LIT> ) ; switch ( AsmPieces . size ( ) ) { default : return false ; case <NUM_LIT> : AsmStr = std :: string ( AsmPieces [ <NUM_LIT> ] ) ; AsmPieces . clear ( ) ; SplitString ( AsmStr , AsmPieces , <STR_LIT> ) ;

if ( AsmPieces . size ( ) == <NUM_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && IA -> getConstraintString ( ) . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) {


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN && ( Subtarget -> hasNEON ( ) || Subtarget -> hasMVEIntegerOps ( ) ) && BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize <= <NUM_LIT> ) { EVT VbicVT ; SDValue Val = isVMOVModifiedImm ( ( ~ SplatBits ) . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , dl , VbicVT , VT . is128BitVector ( ) , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VbicVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Vbic = DAG . getNode ( <STR_LIT> , dl , VbicVT , Input , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vbic ) ; }


<s> } } if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , false , DCI ) ) return Result ; if ( SDValue Result = PerformORCombineToSMULWBT ( N , DCI , Subtarget ) ) return Result ; } SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget -> hasNEON ( ) && N1 . getOpcode ( ) == <STR_LIT> && VT . isVector ( ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) { if ( N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) ) return SDValue ( ) ; APInt SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; APInt SplatBits0 , SplatBits1 ; BuildVectorSDNode * BVN0 = dyn_cast < BuildVectorSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; BuildVectorSDNode * BVN1 = dyn_cast < BuildVectorSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ; if ( BVN0 && BVN0 -> isConstantSplat ( SplatBits0 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { if ( BVN1 && BVN1 -> isConstantSplat ( SplatBits1 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) {

if ( SplatBits0 . getBitWidth ( ) == SplatBits1 . getBitWidth ( ) && SplatBits0 == ~ SplatBits1 ) {


<s> EVT ElemTy = VT . getVectorElementType ( ) ; if ( ElemTy != <STR_LIT> && ElemTy != <STR_LIT> ) setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; if ( ElemTy == <STR_LIT> || ElemTy == <STR_LIT> ) setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; if ( ElemTy != <STR_LIT> ) { setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; } setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ;


<s> AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedLdStVT . getSimpleVT ( ) ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Promote ) ; AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedLdStVT . getSimpleVT ( ) ) ; } EVT ElemTy = VT . getVectorElementType ( ) ; if ( ElemTy != <STR_LIT> && ElemTy != <STR_LIT> ) setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; if ( ElemTy == <STR_LIT> || ElemTy == <STR_LIT> ) setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; if ( ElemTy != <STR_LIT> ) { setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; } setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ;


<s> SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , <STR_LIT> ) ;

return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getByValAlign ( ) , false , false , NULL , <NUM_LIT> , NULL , <NUM_LIT> ) ;


<s> DstOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & TFOps [ <NUM_LIT> ] , i ) ; EmittedNumMemOps += i ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; unsigned BytesLeftSave = BytesLeft ; i = <NUM_LIT> ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , <STR_LIT> ) ) , SrcSV , SrcSVOff + SrcOff , false , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; ++ i ; SrcOff += VTSize ; BytesLeft -= VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & TFOps [ <NUM_LIT> ] , i ) ; i = <NUM_LIT> ; BytesLeft = BytesLeftSave ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ;


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isTypeLegal ( Op . getValueType ( ) ) ) return SDValue ( ) ; DebugLoc dl = N -> getDebugLoc ( ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; } SDValue Cvt = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Op , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cvt , Cvt . getValue ( <NUM_LIT> ) ) ;


<s> ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Root , FIN , PseudoSourceValue :: getFixedStack ( FI ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; } else { Reg = MF . addLiveIn ( NextVA . getLocReg ( ) , RC ) ; ArgValue2 = DAG . getCopyFromReg ( Root , dl , Reg , <STR_LIT> ) ; }

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue2 ) ;


<s> case 'w' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; break ;


<s> if ( Subtarget -> isThumb ( ) ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; else return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; case 'r' : return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; case 'w' :

if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ;


<s> unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>PCLabelIndex = AFI -> createConstPoolEntryUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( BA , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , CPAddr ) ;

SDValue Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , CPAddr , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ;


<s> CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForNode ( CallConv , false , isVarArg ) ) ; SmallVector < SDValue , <NUM_LIT> > ArgValues ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; SDValue ArgValue ; if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue ArgValue1 = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; VA = ArgLocs [ ++ i ] ; SDValue ArgValue2 ; if ( VA . isMemLoc ( ) ) { int FI = MFI -> CreateFixedObject ( <NUM_LIT> , VA . getLocMemOffset ( ) , true , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Chain , FIN , PseudoSourceValue :: getFixedStack ( FI ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; } else { ArgValue2 = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; } ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue2 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else ArgValue = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; } else { TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) RC = <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = ( AFI -> isThumb1OnlyFunction ( ) ? <STR_LIT> : <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ;


<s> switch ( Op . getOpcode ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; }

Op = DAG . getNode ( Opc , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ;


<s> unsigned Opc ; switch ( Op . getOpcode ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; }


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = <NUM_LIT> ; EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; if ( RelocM == Reloc :: Static ) CPAddr = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> ) ; else { <ISA_LIT>PCLabelIndex = AFI -> createConstPoolEntryUId ( ) ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ;

SDValue Chain = Result . getValue ( <NUM_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddressELF ( SDValue Op , SelectionDAG & DAG ) { EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; if ( RelocM == Reloc :: PIC_ ) { bool UseGOTOFF = GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , UseGOTOFF ? <STR_LIT> : <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , GOT ) ; if ( ! UseGOTOFF ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , PseudoSourceValue :: getGOT ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; return Result ;


<s> unsigned Opc ; switch ( Op . getOpcode ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> :


<s> Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; Chain = Offset . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT , Offset , PICLabel ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; } else { <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , <STR_LIT> ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : Res = ExpandBIT_CONVERT ( N , DAG ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerShift ( N , DAG , Subtarget ) ; break ; }

if ( Res . getNode ( ) ) Results . push_back ( Res ) ;


<s> if ( Subtarget -> hasNEON ( ) ) return <NUM_LIT> ; if ( Subtarget -> hasMVEIntegerOps ( ) ) return <NUM_LIT> ; return TargetLoweringBase :: getMaxSupportedInterleaveFactor ( ) ;


<s> if ( Subtarget -> hasMVEIntegerOps ( ) ) return <NUM_LIT> ;

return TargetLoweringBase :: getMaxSupportedInterleaveFactor ( ) ;


<s> Register Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( Reg != <STR_LIT> ) return Reg ;

report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ) ;


<s> MVT VT = Op . getSimpleValueType ( ) ; SDValue Mask = N -> getMask ( ) ; SDValue PassThru = N -> getPassThru ( ) ; SDLoc dl ( Op ) ; auto IsZero = [ ] ( SDValue PassThru ) { return ( <STR_LIT> ( PassThru . getNode ( ) ) || ( PassThru -> getOpcode ( ) == <STR_LIT> && isNullConstant ( PassThru -> getOperand ( <NUM_LIT> ) ) ) ) ; } ; if ( IsZero ( PassThru ) ) return Op ;

SDValue ZeroVec = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;


<s> static SDValue LowerATOMIC_FENCE ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { SDLoc dl ( Op ) ; if ( ! Subtarget -> hasDataBarrier ( ) ) { assert ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isThumb ( ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ) ;


<s> static SDValue LowerATOMIC_FENCE ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { SDLoc dl ( Op ) ; if ( ! Subtarget -> hasDataBarrier ( ) ) { assert ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isThumb ( ) && <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> bool isSigned = OpOpcode == <STR_LIT> ; if ( ConstVec . getOpcode ( ) != <STR_LIT> || ! isConstVecPow2 ( ConstVec , isSigned , C ) ) return SDValue ( ) ; unsigned IntrinsicOpcode = isSigned ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , Op . getValueType ( ) , DAG . getConstant ( IntrinsicOpcode , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( C ) , <STR_LIT> ) ) ;


<s> firstRegToSaveIndex = CCInfo . getFirstUnallocated ( GPRArgRegs , sizeof ( GPRArgRegs ) / sizeof ( GPRArgRegs [ <NUM_LIT> ] ) ) ; lastRegToSaveIndex = <NUM_LIT> ; } unsigned ArgRegsSize , ArgRegsSaveSize ; computeRegArea ( CCInfo , MF , InRegsParamRecordIdx , ArgSize , ArgRegsSize , ArgRegsSaveSize ) ; if ( ArgRegsSaveSize ) { unsigned Padding = ArgRegsSaveSize - ArgRegsSize ; if ( Padding ) { assert ( AFI -> getStoredByValParamsPadding ( ) == <NUM_LIT> && <STR_LIT> ) ; AFI -> setStoredByValParamsPadding ( Padding ) ; } int FrameIndex = MFI -> CreateFixedObject ( ArgRegsSaveSize , Padding + ArgOffset , false ) ; SDValue FIN = DAG . getFrameIndex ( FrameIndex , getPointerTy ( ) ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; for ( unsigned i = <NUM_LIT> ; firstRegToSaveIndex < lastRegToSaveIndex ; ++ firstRegToSaveIndex , ++ i ) {


<s> Ops . push_back ( Builder . getInt32 ( LI -> getAlignment ( ) ) ) ; assert ( isTypeLegal ( EVT :: getEVT ( VecTy ) ) && <STR_LIT> ) ; Type * Tys [ ] = { VecTy , Int8Ptr } ; Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; CallInst * VldN = Builder . CreateCall ( VldnFunc , Ops , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < Shuffles . size ( ) ; i ++ ) { ShuffleVectorInst * SV = Shuffles [ i ] ; unsigned Index = Indices [ i ] ; Value * SubVec = Builder . CreateExtractValue ( VldN , Index ) ; if ( EltTy -> isPointerTy ( ) ) SubVec = Builder . CreateIntToPtr ( SubVec , SV -> getType ( ) ) ; SV -> replaceAllUsesWith ( SubVec ) ;


<s> const DataLayout & DL = SI -> getModule ( ) -> getDataLayout ( ) ; unsigned SubVecSize = DL . getTypeSizeInBits ( SubVecTy ) ; bool EltIs64Bits = DL . getTypeSizeInBits ( EltTy ) == <NUM_LIT> ; if ( ! Subtarget -> hasNEON ( ) || ( SubVecSize != <NUM_LIT> && SubVecSize != <NUM_LIT> ) || EltIs64Bits ) return false ; if ( EltTy -> isHalfTy ( ) ) return false ; Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( SI ) ; if ( EltTy -> isPointerTy ( ) ) { Type * IntTy = DL . getIntPtrType ( EltTy ) ; Type * IntVecTy = VectorType :: get ( IntTy , Op0 -> getType ( ) -> getVectorNumElements ( ) ) ; Op0 = Builder . CreatePtrToInt ( Op0 , IntVecTy ) ; Op1 = Builder . CreatePtrToInt ( Op1 , IntVecTy ) ; SubVecTy = VectorType :: get ( IntTy , LaneLen ) ; } static const <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; SmallVector < Value * , <NUM_LIT> > Ops ;

Type * Int8Ptr = Builder . getInt8PtrTy ( SI -> getPointerAddressSpace ( ) ) ;


<s> Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( SI ) ; if ( EltTy -> isPointerTy ( ) ) { Type * IntTy = DL . getIntPtrType ( EltTy ) ; Type * IntVecTy = VectorType :: get ( IntTy , Op0 -> getType ( ) -> getVectorNumElements ( ) ) ; Op0 = Builder . CreatePtrToInt ( Op0 , IntVecTy ) ; Op1 = Builder . CreatePtrToInt ( Op1 , IntVecTy ) ; SubVecTy = VectorType :: get ( IntTy , LaneLen ) ; } static const <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; SmallVector < Value * , <NUM_LIT> > Ops ; Type * Int8Ptr = Builder . getInt8PtrTy ( SI -> getPointerAddressSpace ( ) ) ; Ops . push_back ( Builder . CreateBitCast ( SI -> getPointerOperand ( ) , Int8Ptr ) ) ; assert ( isTypeLegal ( EVT :: getEVT ( SubVecTy ) ) && <STR_LIT> ) ; Type * Tys [ ] = { Int8Ptr , SubVecTy } ; Function * VstNFunc = <STR_LIT> ( SI -> getModule ( ) , StoreInts [ Factor - <NUM_LIT> ] , Tys ) ; auto Mask = SVI -> getShuffleMask ( ) ; for ( unsigned i = <NUM_LIT> ; i < Factor ; i ++ ) { if ( Mask [ i ] >= <NUM_LIT> ) { Ops . push_back ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Builder , Mask [ i ] , LaneLen , <NUM_LIT> ) ) ) ; } else { unsigned StartMask = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < LaneLen ; j ++ ) { if ( Mask [ j * Factor + i ] >= <NUM_LIT> ) { StartMask = Mask [ j * Factor + i ] - j ; break ;


<s> unsigned Align = GVar -> getAlignment ( ) ; unsigned RequiredPadding = <NUM_LIT> - ( Size % <NUM_LIT> ) ; bool PaddingPossible = RequiredPadding == <NUM_LIT> || ( CDAInit && CDAInit -> isString ( ) ) ; if ( ! PaddingPossible || Align > <NUM_LIT> || Size > ConstpoolPromotionMaxSize ) return SDValue ( ) ; unsigned PaddedSize = Size + ( ( RequiredPadding == <NUM_LIT> ) ? <NUM_LIT> : RequiredPadding ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! AFI -> getGlobalsPromotedToConstantPool ( ) . count ( GVar ) && Size > <NUM_LIT> ) if ( AFI -> getPromotedConstpoolIncrease ( ) + PaddedSize - <NUM_LIT> >= ConstpoolPromotionMaxTotal ) return SDValue ( ) ; if ( ! allUsersAreInFunction ( GVar , F ) && ! ( Size <= <NUM_LIT> && allUsersAreInFunctions ( GVar ) ) ) return SDValue ( ) ; if ( RequiredPadding != <NUM_LIT> ) { StringRef S = CDAInit -> getAsString ( ) ; SmallVector < uint8_t , <NUM_LIT> > V ( S . size ( ) ) ; std :: copy ( S . bytes_begin ( ) , S . bytes_end ( ) , V . begin ( ) ) ; while ( RequiredPadding -- ) V . push_back ( <NUM_LIT> ) ; Init = ConstantDataArray :: get ( * DAG . getContext ( ) , V ) ; }

auto CPVal = <ISA_LIT>ConstantPoolConstant :: Create ( GVar , Init ) ;


<s> APInt NegOne = APInt :: getAllOnesValue ( CarryVT . getScalarSizeInBits ( ) ) ;

return DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( CarryVT , <STR_LIT> ) , BoolCarry , DAG . getConstant ( NegOne , DL , CarryVT ) ) ;


<s> static SDValue ConvertBooleanCarryToCarryFlag ( SDValue BoolCarry , SelectionDAG & DAG ) { SDLoc DL ( BoolCarry ) ;

EVT CarryVT = BoolCarry . getValueType ( ) ;


<s> EVT CarryVT = Carry . getValueType ( ) ; SDLoc DL ( Op ) ; APInt NegOne = APInt :: getAllOnesValue ( CarryVT . getScalarSizeInBits ( ) ) ; SDValue Result ; if ( Op . getOpcode ( ) == <STR_LIT> ) { Carry = ConvertBooleanCarryToCarryFlag ( Carry , DAG ) ; Result = DAG . getNode ( <STR_LIT> , DL , VTs , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Carry . getValue ( <NUM_LIT> ) ) ; Carry = ConvertCarryFlagToBooleanCarry ( Result . getValue ( <NUM_LIT> ) , VT , DAG ) ; } else { Carry = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Carry ) ; Carry = ConvertBooleanCarryToCarryFlag ( Carry , DAG ) ; Result = DAG . getNode ( <STR_LIT> , DL , VTs , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Carry . getValue ( <NUM_LIT> ) ) ;


<s> } } unsigned Opc = LHS . getOpcode ( ) ; if ( LHS . getResNo ( ) == <NUM_LIT> && ( isOneConstant ( RHS ) || isNullConstant ( RHS ) ) && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( LHS -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue Value , OverflowCmp ; SDValue <ISA_LIT>cc ; std :: tie ( Value , OverflowCmp ) = get<ISA_LIT>XALUOOp ( LHS . getValue ( <NUM_LIT> ) , DAG , <ISA_LIT>cc ) ; if ( ( CC == <STR_LIT> ) != isOneConstant ( RHS ) ) { <STR_LIT> CondCode = ( <STR_LIT> ) cast < const ConstantSDNode > ( <ISA_LIT>cc ) -> getZExtValue ( ) ; CondCode = <STR_LIT> ( CondCode ) ; <ISA_LIT>cc = DAG . getConstant ( CondCode , SDLoc ( <ISA_LIT>cc ) , <STR_LIT> ) ; } SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , OverflowCmp ) ; } if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ;


<s> GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( Op ) ; if ( DAG . getTarget ( ) . Options . EmulatedTLS ) return LowerToTLSEmulatedModel ( GA , DAG ) ; if ( Subtarget -> isTargetDarwin ( ) ) return LowerGlobalTLSAddressDarwin ( Op , DAG ) ; if ( Subtarget -> isTargetWindows ( ) ) return LowerGlobalTLSAddressWindows ( Op , DAG ) ; assert ( Subtarget -> isTargetELF ( ) && <STR_LIT> ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GA -> getGlobal ( ) ) ; switch ( model ) { case TLSModel :: GeneralDynamic : case TLSModel :: LocalDynamic : return LowerToTLSGeneralDynamicModel ( GA , DAG ) ; case TLSModel :: InitialExec : case TLSModel :: LocalExec :

return LowerToTLSExecModels ( GA , DAG , model ) ;


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; if ( Subtarget -> isFPOnlySP ( ) && LHS . getValueType ( ) == <STR_LIT> ) { DAG . getTargetLoweringInfo ( ) . softenSetCCOperands ( DAG , <STR_LIT> , LHS , RHS , CC , dl ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) == <STR_LIT> ) { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { CC = <STR_LIT> ( CC , true ) ; std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ;

SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ;


<s> } } if ( Subtarget -> isThumb1Only ( ) ) { SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( RHS ) ) { int32_t imm = C -> getSExtValue ( ) ; if ( imm < <NUM_LIT> && imm > std :: numeric_limits < int > :: min ( ) ) { SDLoc DL ( N ) ; RHS = DAG . getConstant ( - imm , DL , <STR_LIT> ) ;

unsigned Opcode = ( N -> getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ;


<s> if ( ( AddeOp0 != MULOp . getValue ( <NUM_LIT> ) ) && ( AddeOp1 != MULOp . getValue ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( IsLeftOperandMUL ) HiAdd = & AddeOp1 ; else HiAdd = & AddeOp0 ; if ( AddcOp0 == MULOp . getValue ( <NUM_LIT> ) ) { LoMul = & AddcOp0 ; LowAdd = & AddcOp1 ; } if ( AddcOp1 == MULOp . getValue ( <NUM_LIT> ) ) { LoMul = & AddcOp1 ; LowAdd = & AddcOp0 ; } if ( ! LoMul ) return SDValue ( ) ; if ( AddcNode == HiAdd -> getNode ( ) || AddcNode -> isPredecessorOf ( HiAdd -> getNode ( ) ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( * LowAdd ) ; Ops . push_back ( * HiAdd ) ; SDValue MLALNode = DAG . getNode ( FinalOpc , SDLoc ( AddcNode ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; SDValue HiMLALResult ( MLALNode . getNode ( ) , <NUM_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( AddeNode , <NUM_LIT> ) , HiMLALResult ) ;

SDValue LoMLALResult ( MLALNode . getNode ( ) , <NUM_LIT> ) ;


<s> bool canMergeStoresTo ( unsigned AddressSpace , EVT MemVT ) const override { return ( MemVT . getSizeInBits ( ) <= <NUM_LIT> ) ;


<s> <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS ) ; OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; break ; case <STR_LIT> : <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS ) ; OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; break ; } return std :: make_pair ( Value , OverflowCmp ) ;


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS ) ; OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , LHS ) ; break ; case <STR_LIT> : <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) , LHS , RHS ) . getValue ( <NUM_LIT> ) ; OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , LHS ) ; break ; case <STR_LIT> : <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS ) ; OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; break ; case <STR_LIT> : <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS ) ; OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; break ; }

return std :: make_pair ( Value , OverflowCmp ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerBRCOND ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; unsigned Opc = Cond . getOpcode ( ) ; if ( Cond . getResNo ( ) == <NUM_LIT> && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( Cond -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue Value , OverflowCmp ; SDValue <ISA_LIT>cc ; std :: tie ( Value , OverflowCmp ) = get<ISA_LIT>XALUOOp ( Cond , DAG , <ISA_LIT>cc ) ;

<STR_LIT> CondCode = ( <STR_LIT> ) cast < const ConstantSDNode > ( <ISA_LIT>cc ) -> getZExtValue ( ) ;


<s> SDValue <ISA_LIT>cc ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; if ( getTargetMachine ( ) . Options . UnsafeFPMath && ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue Result = OptimizeVFPBrcond ( Op , DAG ) ) return Result ; } <STR_LIT> CondCode , CondCode2 ; bool InvalidOnQNaN ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 , InvalidOnQNaN ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl , InvalidOnQNaN ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Dest , <ISA_LIT>cc , CCR , Cmp } ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , VTList , Ops ) ; if ( CondCode2 != <STR_LIT> ) { <ISA_LIT>cc = DAG . getConstant ( CondCode2 , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Res , Dest , <ISA_LIT>cc , CCR , Res . getValue ( <NUM_LIT> ) } ;


<s> if ( RegIdx != array_lengthof ( GPRArgRegs ) ) ArgRegBegin = std :: min ( ArgRegBegin , ( unsigned ) GPRArgRegs [ RegIdx ] ) ; } unsigned TotalArgRegsSaveSize = <NUM_LIT> * ( <STR_LIT> - ArgRegBegin ) ; AFI -> setArgRegsSaveSize ( TotalArgRegsSaveSize ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( Ins [ VA . getValNo ( ) ] . isOrigArg ( ) ) { std :: advance ( CurOrigArg , Ins [ VA . getValNo ( ) ] . getOrigArgIndex ( ) - CurArgIdx ) ; CurArgIdx = Ins [ VA . getValNo ( ) ] . getOrigArgIndex ( ) ; } if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue ArgValue1 = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; VA = ArgLocs [ ++ i ] ; SDValue ArgValue2 ; if ( VA . isMemLoc ( ) ) { int FI = MFI . CreateFixedObject ( <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ; } else { ArgValue2 = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; } ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue1 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue2 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } else ArgValue = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; } else { const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = AFI -> isThumb1OnlyFunction ( ) ? & <STR_LIT> : & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; }


<s> case <STR_LIT> : return PerformVCVTCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformVDIVCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformBRCONDCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformLOADCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformVLDCombine ( N , DCI ) ; case <STR_LIT> : return Perform<ISA_LIT>BUILD_VECTORCombine ( N , DCI ) ; case <STR_LIT> : { unsigned BitWidth = N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ; APInt DemandedMask = APInt :: getLowBitsSet ( BitWidth , <NUM_LIT> ) ; if ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , DemandedMask , DCI ) ) return SDValue ( ) ; break ; } case <STR_LIT> : { unsigned BitWidth = N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ; APInt DemandedMask = APInt :: getHighBitsSet ( BitWidth , <NUM_LIT> ) ; if ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , DemandedMask , DCI ) ) return SDValue ( ) ; break ; } case <STR_LIT> : { unsigned BitWidth = N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ; APInt DemandedMask = APInt :: getLowBitsSet ( BitWidth , <NUM_LIT> ) ; if ( ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , DemandedMask , DCI ) ) || ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , DemandedMask , DCI ) ) ) return SDValue ( ) ; break ; } case <STR_LIT> : {

unsigned LowWidth = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits ( ) ;


<s> default : break ; case <STR_LIT> : return PerformADDECombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformUMLALCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformADDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformSUBCombine ( N , DCI ) ; case <STR_LIT> : return PerformMULCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformXORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformANDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformAddcSubcCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformAddeSubeCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformBFICombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVRRDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformVMOVDRRCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformSTORECombine ( N , DCI ) ; case <STR_LIT> : return PerformBUILD_VECTORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformInsertEltCombine ( N , DCI ) ; case <STR_LIT> : return PerformVECTOR_SHUFFLECombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformVDUPLANECombine ( N , DCI ) ; case <STR_LIT> : return PerformVDUPCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return PerformVCVTCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformVDIVCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformBRCONDCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformLOADCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> static SDValue PerformABSCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { SelectionDAG & DAG = DCI . DAG ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . isOperationLegal ( N -> getOpcode ( ) , N -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ;


<s> SelectionDAG & DAG = DCI . DAG ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . isOperationLegal ( N -> getOpcode ( ) , N -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ;


<s> case CallingConv :: GHC : return CC ; case CallingConv :: PreserveMost : return CallingConv :: PreserveMost ; case CallingConv :: <ISA_LIT>_AAPCS_VFP : return isVarArg ? CallingConv :: <ISA_LIT>_AAPCS : CallingConv :: <ISA_LIT>_AAPCS_VFP ; case CallingConv :: C : if ( ! Subtarget -> isAAPCS_ABI ( ) ) return CallingConv :: <ISA_LIT>_APCS ; else if ( Subtarget -> hasVFP2 ( ) && ! Subtarget -> isThumb1Only ( ) && getTargetMachine ( ) . Options . FloatABIType == FloatABI :: Hard && ! isVarArg ) return CallingConv :: <ISA_LIT>_AAPCS_VFP ; else return CallingConv :: <ISA_LIT>_AAPCS ; case CallingConv :: Fast : case CallingConv :: CXX_FAST_TLS : if ( ! Subtarget -> isAAPCS_ABI ( ) ) { if ( Subtarget -> hasVFP2 ( ) && ! Subtarget -> isThumb1Only ( ) && ! isVarArg ) return CallingConv :: Fast ; return CallingConv :: <ISA_LIT>_APCS ; } else if ( Subtarget -> hasVFP2 ( ) && ! Subtarget -> isThumb1Only ( ) && ! isVarArg ) return CallingConv :: <ISA_LIT>_AAPCS_VFP ; else return CallingConv :: <ISA_LIT>_AAPCS ;


<s> for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ; else PFIndexes [ i ] = ShuffleMask [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; } if ( EltSize >= <NUM_LIT> ) { EVT EltVT = EVT :: getFloatingPointVT ( EltSize ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumElts ) ; V1 = DAG . getNode ( <STR_LIT> , dl , VecVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , VecVT , V2 ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) Ops . push_back ( DAG . getUNDEF ( EltVT ) ) ; else Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , ShuffleMask [ i ] < ( int ) NumElts ? V1 : V2 , DAG . getConstant ( ShuffleMask [ i ] & ( NumElts - <NUM_LIT> ) , dl , <STR_LIT> ) ) ) ; } SDValue Val = DAG . getNode ( <STR_LIT> , dl , VecVT , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Val ) ; } if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && isReverseMask ( ShuffleMask , VT ) ) return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16 ( Op , DAG ) ; if ( VT == <STR_LIT> ) if ( SDValue NewOp = LowerVECTOR_SHUFFLEv8i8 ( Op , ShuffleMask , DAG ) ) return NewOp ;


<s> return i < ( int ) VT . getVectorNumElements ( ) ; } ) && <STR_LIT> ) ; if ( unsigned ShuffleOpc = isNEONTwoResultShuffleMask ( ShuffleMask , SubVT , WhichResult , isV_UNDEF ) ) { if ( isV_UNDEF ) SubV2 = SubV1 ; assert ( ( WhichResult == <NUM_LIT> ) && <STR_LIT> ) ; SDValue Res = DAG . getNode ( ShuffleOpc , dl , DAG . getVTList ( SubVT , SubVT ) , SubV1 , SubV2 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res . getValue ( <NUM_LIT> ) , Res . getValue ( <NUM_LIT> ) ) ; } } } unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == <NUM_LIT> ) { unsigned PFIndexes [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ; else PFIndexes [ i ] = ShuffleMask [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; } if ( EltSize >= <NUM_LIT> ) { EVT EltVT = EVT :: getFloatingPointVT ( EltSize ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumElts ) ; V1 = DAG . getNode ( <STR_LIT> , dl , VecVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , VecVT , V2 ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) Ops . push_back ( DAG . getUNDEF ( EltVT ) ) ; else Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , ShuffleMask [ i ] < ( int ) NumElts ? V1 : V2 , DAG . getConstant ( ShuffleMask [ i ] & ( NumElts - <NUM_LIT> ) , dl , <STR_LIT> ) ) ) ; } SDValue Val = DAG . getNode ( <STR_LIT> , dl , VecVT , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Val ) ; } if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && isReverseMask ( ShuffleMask , VT ) ) return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16 ( Op , DAG ) ; if ( VT == <STR_LIT> ) if ( SDValue NewOp = LowerVECTOR_SHUFFLEv8i8 ( Op , ShuffleMask , DAG ) ) return NewOp ;


<s> if ( N -> getNumOperands ( ) == <NUM_LIT> ) if ( SDValue RV = PerformVMOVDRRCombine ( N , DAG ) ) return RV ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . getVectorElementType ( ) != <STR_LIT> || ! hasNormalLoadOperand ( N ) ) return SDValue ( ) ; SDLoc dl ( N ) ; SmallVector < SDValue , <NUM_LIT> > Ops ;

unsigned NumElts = VT . getVectorNumElements ( ) ;


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , DstVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ) ; } if ( DstVT == <STR_LIT> && TLI . isTypeLegal ( SrcVT ) ) { SDValue Cvt ; if ( DAG . getDataLayout ( ) . isBigEndian ( ) && SrcVT . isVector ( ) && SrcVT . getVectorNumElements ( ) > <NUM_LIT> ) Cvt = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , DAG . getNode ( <STR_LIT> , dl , SrcVT , Op ) ) ; else Cvt = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Op ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cvt , Cvt . getValue ( <NUM_LIT> ) ) ; } return SDValue ( ) ;


<s> SDValue Op = N -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = Op . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; const bool HasFullFP16 = Subtarget -> hasFullFP16 ( ) ; if ( SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) { if ( ! HasFullFP16 ) return SDValue ( ) ; if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return SDValue ( ) ; } if ( SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) { if ( ! HasFullFP16 ) return SDValue ( ) ; auto ZeroExtend = N -> use_begin ( ) ; if ( N -> use_size ( ) != <NUM_LIT> || ZeroExtend -> getOpcode ( ) != <STR_LIT> || ZeroExtend -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; auto Copy = ZeroExtend -> use_begin ( ) ;

if ( Copy -> getOpcode ( ) == <STR_LIT> && Copy -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> ) {


<s> SDValue Copy = BC -> getOperand ( <NUM_LIT> ) ; if ( Copy . getValueType ( ) != <STR_LIT> || Copy -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Ops [ ] = { Copy -> getOperand ( <NUM_LIT> ) , Copy -> getOperand ( <NUM_LIT> ) } ; SDValue NewCopy = DCI . DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Ops ) ; return NewCopy ;


<s> SDValue BC = N -> getOperand ( <NUM_LIT> ) ; if ( BC -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Copy = BC -> getOperand ( <NUM_LIT> ) ;

if ( Copy . getValueType ( ) != <STR_LIT> || Copy -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , true ) ; return LowerSDIV ( Op , DAG , Subtarget ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , false ) ; return LowerUDIV ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerADDSUBCARRY ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerSignedALUO ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerUnsignedALUO ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerSADDSUBSAT ( Op , DAG , Subtarget ) ; case <STR_LIT> :

return LowerPredicateLoad ( Op , DAG ) ;


<s> if ( ! HasMVEFP ) setAllExpand ( VT ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT . getVectorElementType ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT . getVectorElementType ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; if ( HasMVEFP ) { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; } } const MVT LongTypes [ ] = { <STR_LIT> , <STR_LIT> } ; for ( auto VT : LongTypes ) { addRegisterClass ( VT , & <STR_LIT> ) ; setAllExpand ( VT ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ;


<s> static SDValue PerformHWLoopCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * ST ) { SDValue CC = N -> getOperand ( <NUM_LIT> ) ; if ( CC -> getOpcode ( ) != <STR_LIT> && CC -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( CC -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Int = CC -> getOperand ( <NUM_LIT> ) ; unsigned IntOp = cast < ConstantSDNode > ( Int . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( IntOp != <STR_LIT> ) return SDValue ( ) ; assert ( ( isa < ConstantSDNode > ( CC -> getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( CC -> getOperand ( <NUM_LIT> ) ) -> isOne ( ) ) && <STR_LIT> ) ; SDLoc dl ( Int ) ;

SDValue Chain = N -> getOperand ( <NUM_LIT> ) ;


<s> if ( IntOp != <STR_LIT> ) return SDValue ( ) ; assert ( ( isa < ConstantSDNode > ( CC -> getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( CC -> getOperand ( <NUM_LIT> ) ) -> isOne ( ) ) && <STR_LIT> ) ; SDLoc dl ( Int ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Elements = Int . getOperand ( <NUM_LIT> ) ; SDValue ExitBlock = N -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { Chain , Elements , ExitBlock } ; SDValue Res = DCI . DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; DCI . DAG . ReplaceAllUsesOfValueWith ( Int . getValue ( <NUM_LIT> ) , Int . getOperand ( <NUM_LIT> ) ) ;


<s> EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( Subtarget -> useMovt ( ) && RelocM != Reloc :: Static && ! DAG . getMachineFunction ( ) . getFunction ( ) -> hasFnAttr ( Attribute :: OptimizeForSize ) ) { ++ NumMovwMovt ; if ( RelocM == Reloc :: Static ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; unsigned Wrapper = ( RelocM == Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; SDValue Result = DAG . getNode ( Wrapper , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( ) , false , false , <NUM_LIT> ) ; return Result ; } unsigned <ISA_LIT>PCLabelIndex = <NUM_LIT> ;