<s> void <ISA_LIT>InstPrinter :: printAM2PreOrOffsetIndexOp ( const MCInst * MI , unsigned Op , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( Op ) ; const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; const MCOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << <STR_LIT> ( MO3 . getImm ( ) ) ; O << <STR_LIT> ; return ; } O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << getRegisterName ( MO2 . getReg ( ) ) ; printRegImmShift ( O , <STR_LIT> ( MO3 . getImm ( ) ) , <STR_LIT> ( MO3 . getImm ( ) ) ) ; O << <STR_LIT> ;


<s> if ( ShOpc == <STR_LIT> || ( ShOpc == <STR_LIT> && ! ShImm ) ) return ; O << <STR_LIT> ;

assert ( ! ( ShOpc == <STR_LIT> && ! ShImm ) && <STR_LIT> ) ;


<s> const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ;

O << getRegisterName ( MO1 . getReg ( ) ) ;


<s> void <ISA_LIT>InstPrinter :: printT2AddrModeImm8s4OffsetOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) {

const MCOperand & MO1 = MI -> getOperand ( OpNum ) ;


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; int32_t OffImm = ( int32_t ) MO1 . getImm ( ) ; assert ( ( ( OffImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( OffImm == INT32_MIN ) O << <STR_LIT> ; else if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm ; else if ( OffImm > <NUM_LIT> ) O << <STR_LIT> << OffImm ;


<s> return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; assert ( ( ( OffImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( OffImm == INT32_MIN ) O << <STR_LIT> ;

else if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm ;


<s> void <ISA_LIT>InstPrinter :: printT2SOOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ;

const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ;


<s> void <ISA_LIT>InstPrinter :: printT2SOOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; unsigned Reg = MO1 . getReg ( ) ; O << getRegisterName ( Reg ) ;

assert ( MO2 . isImm ( ) && <STR_LIT> ) ;


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; if ( MO1 . isExpr ( ) ) O << * MO1 . getExpr ( ) ; else if ( MO1 . isImm ( ) ) { O << markup ( <STR_LIT> ) << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( MO1 . getImm ( ) ) << markup ( <STR_LIT> , <STR_LIT> ) ; } else llvm_unreachable ( <STR_LIT> ) ;


<s> int32_t OffImm = ( int32_t ) MO . getImm ( ) << scale ; O << markup ( <STR_LIT> ) ; if ( OffImm == INT32_MIN ) O << <STR_LIT> ; else if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm ; else O << <STR_LIT> << OffImm ; O << markup ( <STR_LIT> ) ;


<s> unsigned val = MI -> getOperand ( OpNum ) . getImm ( ) ;

O << <STR_LIT> ( val , ( STI . getFeatureBits ( ) & <STR_LIT> ) ) ;


<s> switch ( Expr -> getKind ( ) ) { case MCExpr :: Binary : O << '#' << * Expr ; break ; case MCExpr :: Constant : { const MCConstantExpr * Constant = cast < MCConstantExpr > ( Expr ) ; int64_t TargetAddress ; if ( ! Constant -> EvaluateAsAbsolute ( TargetAddress ) ) { O << '#' << * Expr ; } else { O << <STR_LIT> ;

O . write_hex ( static_cast < uint32_t > ( TargetAddress ) ) ;


<s> if ( Imm == <NUM_LIT> ) return ; O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> ; switch ( Imm ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; }


<s> O << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( - OffImm ) << markup ( <STR_LIT> ) ; } else { O << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( OffImm ) << markup ( <STR_LIT> ) ; }

O << <STR_LIT> << markup ( <STR_LIT> ) ;


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; if ( ! MO1 . getReg ( ) ) { unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ;


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; if ( ! MO1 . getReg ( ) ) { unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; assert ( ImmOffs && <STR_LIT> ) ; O << '#' << ( char ) <STR_LIT> ( MO2 . getImm ( ) ) << ImmOffs ;


<s> return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << <STR_LIT> ( MO3 . getImm ( ) ) ; O << <STR_LIT> ; return ; } O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << getRegisterName ( MO2 . getReg ( ) ) ; if ( unsigned ShImm = <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << <STR_LIT> << ShImm ;


<s> return ; } unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; assert ( ImmOffs && <STR_LIT> ) ;

O << <STR_LIT> << ( char ) <STR_LIT> ( MO2 . getImm ( ) ) << ImmOffs ;


<s> O << ( char ) <STR_LIT> ( MO2 . getImm ( ) ) << getRegisterName ( MO1 . getReg ( ) ) ; return ; }

unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ;


<s> O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << getRegisterName ( MO2 . getReg ( ) ) << ']' ; return ; }

if ( unsigned ImmOffs = <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << ImmOffs ;


<s> void <ISA_LIT>InstPrinter :: printAddrMode3Operand ( const MCInst * MI , unsigned OpNum ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; const MCOperand & MO3 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << '[' << getRegisterName ( MO1 . getReg ( ) ) ; if ( MO2 . getReg ( ) ) { O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << getRegisterName ( MO2 . getReg ( ) ) << ']' ;


<s> void <ISA_LIT>InstPrinter :: printAddrMode4Operand ( const MCInst * MI , unsigned OpNum , const char * Modifier ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; <STR_LIT> Mode = <STR_LIT> ( MO2 . getImm ( ) ) ; if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { if ( MO1 . getReg ( ) == <STR_LIT> ) { bool isLDM = ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ; O << <STR_LIT> ( Mode , isLDM ) ;


<s> return ; } if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { <STR_LIT> Mode = <STR_LIT> ( MO2 . getImm ( ) ) ; O << <STR_LIT> ( Mode ) ; return ; } else if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { O << getRegisterName ( MO1 . getReg ( ) ) ; if ( <STR_LIT> ( MO2 . getImm ( ) ) ) O << <STR_LIT> ; return ; }

O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ;


<s> const MCOperand & MO3 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << '[' << getRegisterName ( MO1 . getReg ( ) ) << ']' ; if ( <STR_LIT> ( MO3 . getImm ( ) ) ) { if ( MO2 . getReg ( ) == <NUM_LIT> ) O << '!' ;

else O << <STR_LIT> << getRegisterName ( MO2 . getReg ( ) ) ;


<s> void <ISA_LIT>InstPrinter :: printAddrModePCOperand ( const MCInst * MI , unsigned OpNum , const char * Modifier ) {


<s> uint32_t v = ~ MO . getImm ( ) ; int32_t lsb = CountTrailingZeros_32 ( v ) ;

int32_t width = ( <NUM_LIT> - CountLeadingZeros_32 ( v ) ) - lsb ;


<s> const MCOperand & MO = MI -> getOperand ( OpNum ) ; uint32_t v = ~ MO . getImm ( ) ;

int32_t lsb = CountTrailingZeros_32 ( v ) ;


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI ) { printInstruction ( MI ) ;


<s> <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum ) . getImm ( ) ;


<s> void <ISA_LIT>InstPrinter :: printNoHashImmediate ( const MCInst * MI , unsigned OpNum ) { O << MI -> getOperand ( OpNum ) . getImm ( ) ;


<s> assert ( <NUM_LIT> ) ; } else if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { assert ( <NUM_LIT> ) ; } else { O << getRegisterName ( Reg ) ; } } else if ( Op . isImm ( ) ) { assert ( ( Modifier == <NUM_LIT> || Modifier [ <NUM_LIT> ] == <NUM_LIT> ) && <STR_LIT> ) ; O << '#' << Op . getImm ( ) ;


<s> void <ISA_LIT>InstPrinter :: printPredicateOperand ( const MCInst * MI , unsigned OpNum ) { <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum ) . getImm ( ) ; if ( CC != <STR_LIT> ) O << <ISA_LIT>CondCodeToString ( CC ) ;


<s> void <ISA_LIT>InstPrinter :: printPredicateOperand ( const MCInst * MI , unsigned OpNum ) { <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum ) . getImm ( ) ;

if ( CC != <STR_LIT> ) O << <ISA_LIT>CondCodeToString ( CC ) ;


<s> for ( unsigned i = OpNum + <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i != OpNum + <NUM_LIT> ) O << <STR_LIT> ; O << getRegisterName ( MI -> getOperand ( i ) . getReg ( ) ) ; }


<s> if ( i != OpNum + <NUM_LIT> ) O << <STR_LIT> ; O << getRegisterName ( MI -> getOperand ( i ) . getReg ( ) ) ; } O << <STR_LIT> ;


<s> assert ( MI -> getOperand ( OpNum ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; O << 's' ;


<s> void <ISA_LIT>InstPrinter :: printSOImm2PartOperand ( const MCInst * MI , unsigned OpNum ) { abort ( ) ;


<s> const MCOperand & MO = MI -> getOperand ( OpNum ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; printSOImm ( O , MO . getImm ( ) , VerboseAsm , & MAI ) ;


<s>
O
<<
<STR_LIT>
<<
<STR_LIT>
(
<STR_LIT>
(
MO3
.
getImm
(
)
)
)
<<
' '
;
if
(
MO2
.
getReg
(
)
)
{
O
<<
getRegisterName
(
MO2
.
getReg
(
)
)
;
assert
(
<STR_LIT>
(
MO3
.
getImm
(
)
)
==
<NUM_LIT>
)
;
}
else
{
O
<<
<STR_LIT>
<<
<STR_LIT>
(
MO3
.
getImm
(
)
)
;
}


<s> O << <STR_LIT> << MI -> getOperand ( OpNum ) . getImm ( ) * <NUM_LIT> ;


<s> unsigned Mask = Op . getImm ( ) & <NUM_LIT> ; if ( getAvailableFeatures ( ) & <STR_LIT> ) { switch ( Op . getImm ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } } if ( ! SpecRegRBit && ( Mask == <NUM_LIT> || Mask == <NUM_LIT> || Mask == <NUM_LIT> ) ) { O << <STR_LIT> ; switch ( Mask ) { default : assert ( <NUM_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } llvm_unreachable ( <STR_LIT> ) ;


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } } if ( ! SpecRegRBit && ( Mask == <NUM_LIT> || Mask == <NUM_LIT> || Mask == <NUM_LIT> ) ) { O << <STR_LIT> ; switch ( Mask ) { default : assert ( <NUM_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } llvm_unreachable ( <STR_LIT> ) ; } if ( SpecRegRBit ) O << <STR_LIT> ; else O << <STR_LIT> ; if ( Mask ) { O << '_' ; if ( Mask & <NUM_LIT> ) O << 'f' ;


<s> O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> ;


<s> case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } } SYSm &= <NUM_LIT> ; if ( Opcode == <STR_LIT> && FeatureBits [ <STR_LIT> ] ) { switch ( SYSm ) { case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } } switch ( SYSm ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> :


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , bool verboseAsm ) : MCInstPrinter ( MAI ) , VerboseAsm ( verboseAsm ) {


<s> void printHex16ImmOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) {


<s> void printHex32ImmOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) {


<s> void printHex64ImmOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) {


<s> void printHex8ImmOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) {


<s> void printJT2BlockOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) {


<s> void printJTBlockOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) {


<s> void PrintSpecial ( const MCInst * MI , raw_ostream & O , const char * Kind ) {


<s> O << <STR_LIT> ; for ( unsigned i = OpNum , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i != OpNum ) O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( i ) . getReg ( ) ) ; }


<s> void printCPSOptionOperand ( const MCInst * MI , unsigned OpNum ) {


<s> void printMSRMaskOperand ( const MCInst * MI , unsigned OpNum ) {


<s> void printNegZeroOperand ( const MCInst * MI , unsigned OpNum ) {


<s> void printT2AddrModeImm8s4OffsetOperand ( const MCInst * MI , unsigned OpNum ) {


<s> O << markup ( <STR_LIT> ) << '#' << formatImm ( Op . getImm ( ) ) << markup ( <STR_LIT> ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = Op . getExpr ( ) ; switch ( Expr -> getKind ( ) ) { case MCExpr :: Binary : O << '#' << * Expr ; break ; case MCExpr :: Constant : { const MCConstantExpr * Constant = cast < MCConstantExpr > ( Expr ) ; int64_t TargetAddress ;

if ( ! Constant -> evaluateAsAbsolute ( TargetAddress ) ) {


<s> void <ISA_LIT>InstPrinter :: printOperand ( const MCInst * MI , uint64_t Address , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNum ) ; if ( ! Op . isImm ( ) || ! PrintBranchImmAsAddress || getUseMarkup ( ) ) return printOperand ( MI , OpNum , STI , O ) ; uint64_t Target = <ISA_LIT>_MC :: evaluateBranchTarget ( MII . get ( MI -> getOpcode ( ) ) , Address , Op . getImm ( ) ) ; Target &= <NUM_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printThumbLdrLabelOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; if ( MO1 . isExpr ( ) ) O << * MO1 . getExpr ( ) ; else if ( MO1 . isImm ( ) ) O << <STR_LIT> << MO1 . getImm ( ) << <STR_LIT> ;


<s> else if ( MO1 . isImm ( ) ) O << <STR_LIT> << MO1 . getImm ( ) << <STR_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printAddrMode3Operand ( const MCInst * MI , unsigned Op , raw_ostream & O ) { const MCOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; unsigned IdxMode = <STR_LIT> ( MO3 . getImm ( ) ) ; if ( IdxMode == <STR_LIT> ) { printAM3PostIndexOp ( MI , Op , O ) ;


<s> void <ISA_LIT>InstPrinter :: printAddrMode3Operand ( const MCInst * MI , unsigned Op , raw_ostream & O ) { const MCOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; unsigned IdxMode = <STR_LIT> ( MO3 . getImm ( ) ) ; if ( IdxMode == <STR_LIT> ) { printAM3PostIndexOp ( MI , Op , O ) ; return ; } printAM3PreOrOffsetIndexOp ( MI , Op , O ) ;


<s> return ; } if ( Opcode == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == - <NUM_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) << <STR_LIT> ; printAnnotation ( O , Annot ) ; return ; } if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; if ( Opcode == <STR_LIT> ) O << <STR_LIT> ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( Opcode == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) << <STR_LIT> ; printAnnotation ( O , Annot ) ; return ; } if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( Opcode == <STR_LIT> ) { bool Writeback = true ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( unsigned i = <NUM_LIT> ; i < MI -> getNumOperands ( ) ; ++ i ) { if ( MI -> getOperand ( i ) . getReg ( ) == BaseReg ) Writeback = false ; } O << <STR_LIT> ;


<s> O << markup ( <STR_LIT> ) << <STR_LIT> ; O . write_hex ( Val ) ; O << markup ( <STR_LIT> ) ;


<s> uint32_t Val = MI -> getOperand ( OpNum ) . getImm ( ) ;

O << markup ( <STR_LIT> ) << <STR_LIT> ;


<s> const MCOperand & MO1 = MI -> getOperand ( Op ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op , O ) ; return ;


<s> uint32_t R = ( Banked & <NUM_LIT> ) >> <NUM_LIT> ; uint32_t SysM = Banked & <NUM_LIT> ; if ( R ) { O << <STR_LIT> ; switch ( SysM ) { case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; default : llvm_unreachable ( <STR_LIT> ) ; } } assert ( ! R && <STR_LIT> ) ; const char * RegNames [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const char * Name = RegNames [ SysM ] ; assert ( Name [ <NUM_LIT> ] && <STR_LIT> ) ; O << Name ;


<s> const MCOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; const MCOperand & MO1 = MI -> getOperand ( <NUM_LIT> ) ; const MCOperand & MO2 = MI -> getOperand ( <NUM_LIT> ) ; const MCOperand & MO3 = MI -> getOperand ( <NUM_LIT> ) ; O << '\t' << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) ; printSBitModifierOperand ( MI , <NUM_LIT> , O ) ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegName ( O , Dst . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MO2 . getReg ( ) ) ; assert ( <STR_LIT> ( MO3 . getImm ( ) ) == <NUM_LIT> ) ; printAnnotation ( O , Annot ) ; return ; } case <STR_LIT> : { const MCOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; const MCOperand & MO1 = MI -> getOperand ( <NUM_LIT> ) ; const MCOperand & MO2 = MI -> getOperand ( <NUM_LIT> ) ; O << '\t' << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) ; printSBitModifierOperand ( MI , <NUM_LIT> , O ) ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegName ( O , Dst . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; if ( <STR_LIT> ( MO2 . getImm ( ) ) == <STR_LIT> ) { printAnnotation ( O , Annot ) ; return ; } O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << translateShiftImm ( <STR_LIT> ( MO2 . getImm ( ) ) ) << markup ( <STR_LIT> ) ; printAnnotation ( O , Annot ) ; return ; } case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getNumOperands ( ) > <NUM_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; if ( Opcode == <STR_LIT> ) O << <STR_LIT> ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } else break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == - <NUM_LIT> ) {


<s> case <STR_LIT> : PrintUnsigned = true ; break ; } int32_t Rotated = <STR_LIT> ( Bits , Rot ) ; if ( <STR_LIT> ( Rotated ) == Op . getImm ( ) ) { O << <STR_LIT> << markup ( <STR_LIT> ) ; if ( PrintUnsigned ) O << static_cast < uint32_t > ( Rotated ) ; else O << Rotated ; O << markup ( <STR_LIT> ) ; return ;


<s> return ; } O << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << getRegisterName ( MO1 . getReg ( ) ) ;

if ( unsigned ShImm = <STR_LIT> ( MO2 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << <STR_LIT> << ShImm ;


<s> O << '#' << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << ImmOffs ; return ; } O << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << getRegisterName ( MO1 . getReg ( ) ) ; if ( unsigned ShImm = <STR_LIT> ( MO2 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << <STR_LIT> << ShImm ;


<s> if ( ! MO1 . isReg ( ) ) { printOperand ( MI , OpNum , O ) ; return ; } if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { <STR_LIT> Mode = <STR_LIT> ( MO2 . getImm ( ) ) ; O << <STR_LIT> ( Mode ) ; return ; } else if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { O << getRegisterName ( MO1 . getReg ( ) ) ; return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ) {

O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << ImmOffs * <NUM_LIT> ;


<s> } if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { <STR_LIT> Mode = <STR_LIT> ( MO2 . getImm ( ) ) ; O << <STR_LIT> ( Mode ) ; return ; } else if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { O << getRegisterName ( MO1 . getReg ( ) ) ; return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ) { O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << ImmOffs * <NUM_LIT> ; } O << <STR_LIT> ;


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( MO2 . getImm ( ) ) { O << <STR_LIT> << MO2 . getImm ( ) ; }


<s> const MCOperand & MO = MI -> getOperand ( OpNum ) ; uint32_t v = ~ MO . getImm ( ) ; int32_t lsb = CountTrailingZeros_32 ( v ) ;


<s> void <ISA_LIT>InstPrinter :: printBitfieldInvMaskImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; uint32_t v = ~ MO . getImm ( ) ; int32_t lsb = CountTrailingZeros_32 ( v ) ; int32_t width = ( <NUM_LIT> - CountLeadingZeros_32 ( v ) ) - lsb ;

assert ( MO . isImm ( ) && <STR_LIT> ) ;


<s> printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' << getRegisterName ( Dst . getReg ( ) ) << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( <STR_LIT> ( MO3 . getImm ( ) ) == <STR_LIT> ) return ; O << <STR_LIT> ; if ( MO2 . getReg ( ) ) { O << getRegisterName ( MO2 . getReg ( ) ) ; assert ( <STR_LIT> ( MO3 . getImm ( ) ) == <NUM_LIT> ) ; } else { O << <STR_LIT> << <STR_LIT> ( MO3 . getImm ( ) ) ; } return ; } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { const MCOperand & MO1 = MI -> getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( MO1 . getImm ( ) ) == <STR_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; return ; } } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { const MCOperand & MO1 = MI -> getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( MO1 . getImm ( ) ) == <STR_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; return ; } } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) {


<s> assert ( ( Modifier && ! strcmp ( Modifier , <STR_LIT> ) ) || ( ( Modifier == <NUM_LIT> || Modifier [ <NUM_LIT> ] == <NUM_LIT> ) && <STR_LIT> ) ) ; O << '#' << Op . getImm ( ) ; } else { assert ( ( Modifier == <NUM_LIT> || Modifier [ <NUM_LIT> ] == <NUM_LIT> ) && <STR_LIT> ) ; assert ( Op . isExpr ( ) && <STR_LIT> ) ; O << * Op . getExpr ( ) ; }


<s> assert ( ( Modifier && ! strcmp ( Modifier , <STR_LIT> ) ) || ( ( Modifier == <NUM_LIT> || Modifier [ <NUM_LIT> ] == <NUM_LIT> ) && <STR_LIT> ) ) ; O << '#' << Op . getImm ( ) ; } else { assert ( ( Modifier == <NUM_LIT> || Modifier [ <NUM_LIT> ] == <NUM_LIT> ) && <STR_LIT> ) ; assert ( Op . isExpr ( ) && <STR_LIT> ) ; O << * Op . getExpr ( ) ;


<s> if ( MO2 . getReg ( ) ) { O << getRegisterName ( MO2 . getReg ( ) ) ; assert ( <STR_LIT> ( MO3 . getImm ( ) ) == <NUM_LIT> ) ; } else { O << <STR_LIT> << <STR_LIT> ( MO3 . getImm ( ) ) ; }


<s> MCInstPrinter ( MAI , MRI ) { setAvailableFeatures ( STI . getFeatureBits ( ) ) ;


<s> if ( isSub ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( - OffImm ) << markup ( <STR_LIT> ) ; } else if ( AlwaysPrintImm0 || OffImm > <NUM_LIT> ) {

O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( OffImm ) << markup ( <STR_LIT> ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>BaseInstrInfo ( STI ) , RI ( ) {


<s> if ( ! Subtarget . isGVIndirectSymbol ( GV ) ) { expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; Register Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( * MBB . getParent ( ) ) , Flags , <NUM_LIT> , <NUM_LIT> ) ; MIB . addMemOperand ( MMO ) ;

BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . cloneMemRefs ( * MI ) . add ( predOps ( <STR_LIT> ) ) ;


<s> NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } else { NopInst . setOpcode ( <STR_LIT> ) ;

NopInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ;


<s> if ( hasNOP ( ) ) { NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } else { NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; } return <NUM_LIT> ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>BaseInstrInfo ( STI ) , RI ( STI ) {


<s> FunctionPass * llvm :: create<ISA_LIT>GlobalBaseRegPass ( ) {


<s> AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ) ) ;

NopInst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ;


<s> virtual const char * getPassName ( ) const {


<s> MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; unsigned Opc = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetInstrInfo & TII = * TM -> getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; return true ;


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> getGlobalBaseReg ( ) == <NUM_LIT> ) return false ; const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF . getTarget ( ) ) ; if ( TM -> getRelocationModel ( ) != Reloc :: PIC_ ) return false ; LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; GlobalValue * GV = new GlobalVariable ( Type :: getInt32Ty ( * Context ) , false , GlobalValue :: ExternalLinkage , <NUM_LIT> , <STR_LIT> ) ; unsigned Id = AFI -> createPICLabelUId ( ) ;

<ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , Id ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>BaseInstrInfo ( STI ) , RI ( * this , STI ) {


<s> case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> void <ISA_LIT>InstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr * Orig , const TargetRegisterInfo & TRI ) const { DebugLoc dl = Orig -> getDebugLoc ( ) ; unsigned Opcode = Orig -> getOpcode ( ) ; switch ( Opcode ) { default : break ; case <STR_LIT> : { RI . emitLoadConstPool ( MBB , I , dl , DestReg , SubIdx , Orig -> getOperand ( <NUM_LIT> ) . getImm ( ) , ( <STR_LIT> ) Orig -> getOperand ( <NUM_LIT> ) . getImm ( ) , Orig -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineInstr * NewMI = prior ( I ) ;

NewMI -> getOperand ( <NUM_LIT> ) . setSubReg ( SubIdx ) ;


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; unsigned Flag = MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( ) , Flag , <NUM_LIT> , <NUM_LIT> ) ; MIB . addMemOperand ( MMO ) ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; MIB . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ;


<s> MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! Subtarget . useMovt ( MF ) ) { if ( RM == Reloc :: PIC_ ) expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> , RM ) ; else expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> , RM ) ; return ; } if ( RM != Reloc :: PIC_ ) { expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> , RM ) ; return ; } const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; if ( ! Subtarget . GVIsIndirectSymbol ( GV , RM ) ) { expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> , RM ) ; return ; } MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; unsigned Flag = MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( ) , Flag , <NUM_LIT> , <NUM_LIT> ) ; MIB . addMemOperand ( MMO ) ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; MIB . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; AddDefaultPred ( MIB ) ;


<s> LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = STI . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * Context , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; unsigned Align = TM . getDataLayout ( ) -> getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned TempReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ;

unsigned Opc = STI . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ;


<s> MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , TempReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; Opc = STI . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addReg ( TempReg ) . addImm ( <ISA_LIT>PCLabelIndex ) ; if ( Opc == <STR_LIT> ) AddDefaultPred ( MIB ) ; return true ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & STI ) : TargetInstrInfoImpl ( <ISA_LIT>Insts , array_lengthof ( <ISA_LIT>Insts ) ) , RI ( * this , STI ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( OpNum == <NUM_LIT> ) { unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RI . isPhysicalRegister ( SrcReg ) && ! RI . isLowRegister ( SrcReg ) ) return false ; } else { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RI . isPhysicalRegister ( DstReg ) && ! RI . isLowRegister ( DstReg ) ) return false ; } return true ; } case <STR_LIT> :


<s> AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ) ; return true ; } } else { if ( DestRC == <STR_LIT> ) { if ( SrcRC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return true ; } else if ( SrcRC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return true ; } } else if ( DestRC == <STR_LIT> ) { if ( SrcRC == <STR_LIT> ) {


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> ) { Pred . push_back ( MO ) ;


<s> if ( ! TID . getImplicitDefs ( ) && ! TID . hasOptionalDef ( ) ) return false ; bool Found = false ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> ) {


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; } return <NUM_LIT> ;


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int BOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; int BccOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) BuildMI ( & MBB , dl , get ( BOpc ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , dl , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; return <NUM_LIT> ; } BuildMI ( & MBB , dl , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ;

BuildMI ( & MBB , dl , get ( BOpc ) ) . addMBB ( FBB ) ;


<s> switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> :


<s> bool <ISA_LIT>InstrInfo :: isMoveInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SrcSubIdx , unsigned & DstSubIdx ) const { SrcSubIdx = DstSubIdx = <NUM_LIT> ; unsigned oc = MI . getOpcode ( ) ; switch ( oc ) { default : return false ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return true ;


<s> case <STR_LIT> : case <STR_LIT> : assert ( MI . getDesc ( ) . getNumOperands ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ;

SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> int PIdx = MI -> findFirstPredOperandIdx ( ) ; return PIdx != - <NUM_LIT> && MI -> getOperand ( PIdx ) . getImm ( ) != <STR_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: isPredicated ( const MachineInstr * MI ) const { int PIdx = MI -> findFirstPredOperandIdx ( ) ; return PIdx != - <NUM_LIT> && MI -> getOperand ( PIdx ) . getImm ( ) != <STR_LIT> ;


<s> switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> } Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else { assert ( RC == <STR_LIT> && <STR_LIT> ) ; Opc = <STR_LIT> ; } MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) , DestReg ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; AddDefaultPred ( MIB ) ;


<s> loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == <STR_LIT> ) { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( ! AFI -> isThumbFunction ( ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; } else if ( RC == <STR_LIT> ) { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( AFI -> isThumbFunction ( ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; } else if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ) ;


<s> unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { MI -> setDesc ( get ( Opc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; MI -> addOperand ( MachineOperand :: CreateImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) ) ; MI -> addOperand ( MachineOperand :: CreateReg ( Pred [ <NUM_LIT> ] . getReg ( ) , false ) ) ; return true ; } int PIdx = MI -> findFirstPredOperandIdx ( ) ;


<s> void <ISA_LIT>InstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , const MachineInstr * Orig ) const { DebugLoc dl = Orig -> getDebugLoc ( ) ; if ( Orig -> getOpcode ( ) == <STR_LIT> ) { RI . emitLoadConstPool ( MBB , I , DestReg , Orig -> getOperand ( <NUM_LIT> ) . getImm ( ) , Orig -> getOperand ( <NUM_LIT> ) . getImm ( ) , Orig -> getOperand ( <NUM_LIT> ) . getReg ( ) , this , false , dl ) ; return ; }

MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ;


<s> MachineBasicBlock :: iterator I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( I -> getOpcode ( ) != BOpc && I -> getOpcode ( ) != BccOpc ) return <NUM_LIT> ; I -> eraseFromParent ( ) ;


<s> restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! AFI -> isThumbFunction ( ) || CSI . empty ( ) ) return false ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > <NUM_LIT> ; MachineInstr * PopMI = MF . CreateMachineInstr ( get ( <STR_LIT> ) , MI -> getDebugLoc ( ) ) ; MBB . insert ( MI , PopMI ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( Reg == <STR_LIT> ) { if ( isVarArg ) continue ; Reg = <STR_LIT> ; PopMI -> setDesc ( get ( <STR_LIT> ) ) ; MBB . erase ( MI ) ; } PopMI -> addOperand ( MachineOperand :: CreateReg ( Reg , true ) ) ; } return true ;


<s> MachineInstr * PopMI = MF . CreateMachineInstr ( get ( <STR_LIT> ) , MI -> getDebugLoc ( ) ) ; MBB . insert ( MI , PopMI ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ;


<s> bool <ISA_LIT>InstrInfo :: ReverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { <STR_LIT> CC = ( <STR_LIT> ) ( int ) Cond [ <NUM_LIT> ] . getImm ( ) ; Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ( CC ) ) ;


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! AFI -> isThumbFunction ( ) || CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ;

for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) {


<s> MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! AFI -> isThumbFunction ( ) || CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) {

unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ;


<s> if ( RC == <STR_LIT> ) { <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> isThumbFunction ( ) ) { Opc = Addr [ <NUM_LIT> ] . isFI ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; NewMIs . push_back ( MIB ) ; return ; } Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else {

assert ( RC == <STR_LIT> && <STR_LIT> ) ;


<s> DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; unsigned Opc = <NUM_LIT> ; if ( RC == <STR_LIT> ) { <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> isThumbFunction ( ) ) { Opc = Addr [ <NUM_LIT> ] . isFI ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; NewMIs . push_back ( MIB ) ; return ; } Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else {


<s> assert ( ! AFI -> isThumbFunction ( ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; } else if ( RC == <STR_LIT> ) { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( AFI -> isThumbFunction ( ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; } else if ( RC == <STR_LIT> ) {

AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ) ;


<s> bool <ISA_LIT>InstrInfo :: SubsumesPredicate ( const SmallVectorImpl < MachineOperand > & Pred1 , const SmallVectorImpl < MachineOperand > & Pred2 ) const { if ( Pred1 . size ( ) > <NUM_LIT> || Pred2 . size ( ) > <NUM_LIT> ) return false ; <STR_LIT> CC1 = ( <STR_LIT> ) Pred1 [ <NUM_LIT> ] . getImm ( ) ; <STR_LIT> CC2 = ( <STR_LIT> ) Pred2 [ <NUM_LIT> ] . getImm ( ) ;


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return RI ;


<s> void <ISA_LIT>InstrInfo :: expandLoadStackGuard ( MachineBasicBlock :: iterator MI ) const { MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; if ( ! Subtarget . useMovt ( MF ) ) { if ( TM . isPositionIndependent ( ) ) expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; else expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } if ( ! TM . isPositionIndependent ( ) ) { expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; if ( ! Subtarget . isGVIndirectSymbol ( GV ) ) { expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ;

auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & STI ) : RI ( * this , STI ) , Subtarget ( STI ) {


<s> virtual const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const {


<s> virtual const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return RI ;


<s> expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; if ( ! Subtarget . isGVIndirectSymbol ( GV ) ) { expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( * MBB . getParent ( ) ) , Flags , <NUM_LIT> , <NUM_LIT> ) ; MIB . addMemOperand ( MMO ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>BaseInstrInfo ( STI ) {


<s> NopInst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } else { NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } return NopInst ;


<s> NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } else { NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ;


<s> return ; } const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; if ( ! Subtarget . isGVIndirectSymbol ( GV ) ) { expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ;


<s> MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( * MBB . getParent ( ) ) , Flags , <NUM_LIT> , <NUM_LIT> ) ; MIB . addMemOperand ( MMO ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) . add ( predOps ( <STR_LIT> ) ) ;


<s> reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr * Orig , const TargetRegisterInfo * TRI ) const { DebugLoc dl = Orig -> getDebugLoc ( ) ; unsigned Opcode = Orig -> getOpcode ( ) ; switch ( Opcode ) { default : break ;


<s> break ; case <STR_LIT> : { RI . emitLoadConstPool ( MBB , I , dl , DestReg , SubIdx , Orig -> getOperand ( <NUM_LIT> ) . getImm ( ) , ( <STR_LIT> ) Orig -> getOperand ( <NUM_LIT> ) . getImm ( ) , Orig -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineInstr * NewMI = prior ( I ) ; NewMI -> getOperand ( <NUM_LIT> ) . setSubReg ( SubIdx ) ; return ; } } return <ISA_LIT>BaseInstrInfo :: reMaterialize ( MBB , I , DestReg , SubIdx , Orig , TRI ) ;


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> getGlobalBaseReg ( ) == <NUM_LIT> ) return false ; const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF . getTarget ( ) ) ; if ( TM -> getRelocationModel ( ) != Reloc :: PIC_ ) return false ; LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ;

<ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * Context , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ;


<s> MachineInstrBuilder MIB ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; unsigned Flag = MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( ) , Flag , <NUM_LIT> , <NUM_LIT> ) ; MIB . addMemOperand ( MMO ) ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ;

MIB . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ;


<s> unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = STI . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * Context , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; unsigned Align = TM . getDataLayout ( ) -> getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned TempReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; unsigned Opc = STI . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ;

const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ;


<s> case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ; case <STR_LIT> : { if ( OpNum == <NUM_LIT> ) { unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RI . isPhysicalRegister ( SrcReg ) && ! RI . isLowRegister ( SrcReg ) ) return false ; } else {

unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( DestRC == <STR_LIT> ) { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ;

if ( AFI -> isThumbFunction ( ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ;


<s> else AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ) ; } else if ( DestRC == <STR_LIT> ) AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; else if ( DestRC == <STR_LIT> ) AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; else return false ;


<s> unsigned NumOps = TID . getNumOperands ( ) ; MachineOperand JTOP = MI -> getOperand ( NumOps - ( TID . isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOP . getIndex ( ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; assert ( JTI < JT . size ( ) ) ; return getNumJTEntries ( JT , JTI ) * <NUM_LIT> + ( MI -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; } default : return <NUM_LIT> ; } } }


<s> case <STR_LIT> : case <STR_LIT> : assert ( MI . getDesc ( ) . getNumOperands ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ;


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return true ; case <STR_LIT> : case <STR_LIT> : assert ( MI . getDesc ( ) . getNumOperands ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> unsigned Opc = <NUM_LIT> ; if ( RC == <STR_LIT> ) { <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> isThumbFunction ( ) ) { Opc = Addr [ <NUM_LIT> ] . isFI ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) , DestReg ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; NewMIs . push_back ( MIB ) ; return ; } Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else {


<s> loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == <STR_LIT> ) { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> isThumbFunction ( ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; } else if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ) ; } else { assert ( RC == <STR_LIT> && <STR_LIT> ) ;


<s> } else if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ) ; } else { assert ( RC == <STR_LIT> && <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ) ; }


<s> return true ; } int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) { MachineOperand & PMO = MI -> getOperand ( PIdx ) ; PMO . setImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) ; MI -> getOperand ( PIdx + <NUM_LIT> ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; return true ; }


<s> MI -> setDesc ( get ( Opc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; MI -> addOperand ( MachineOperand :: CreateImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) ) ; MI -> addOperand ( MachineOperand :: CreateReg ( Pred [ <NUM_LIT> ] . getReg ( ) , false ) ) ; return true ; } int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) {

MachineOperand & PMO = MI -> getOperand ( PIdx ) ;


<s> bool <ISA_LIT>InstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! AFI -> isThumbFunction ( ) || CSI . empty ( ) ) return false ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > <NUM_LIT> ; MachineInstr * PopMI = MF . CreateMachineInstr ( get ( <STR_LIT> ) , MI -> getDebugLoc ( ) ) ; MBB . insert ( MI , PopMI ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( Reg == <STR_LIT> ) { if ( isVarArg ) continue ; Reg = <STR_LIT> ; PopMI -> setDesc ( get ( <STR_LIT> ) ) ; MBB . erase ( MI ) ; }

PopMI -> addOperand ( MachineOperand :: CreateReg ( Reg , true ) ) ;


<s> bool <ISA_LIT>InstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! AFI -> isThumbFunction ( ) || CSI . empty ( ) ) return false ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > <NUM_LIT> ; MachineInstr * PopMI = MF . CreateMachineInstr ( get ( <STR_LIT> ) , MI -> getDebugLoc ( ) ) ; MBB . insert ( MI , PopMI ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( Reg == <STR_LIT> ) { if ( isVarArg ) continue ; Reg = <STR_LIT> ;

PopMI -> setDesc ( get ( <STR_LIT> ) ) ;


<s> for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ;

MIB . addReg ( Reg , false , false , true ) ;


<s> if ( ! AFI -> isThumbFunction ( ) || CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , false , false , true ) ; } return true ;


<s> if ( AFI -> isThumbFunction ( ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , false , false , isKill ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , false , false , isKill ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; } else if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , false , false , isKill ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ) ; } else { assert ( RC == <STR_LIT> && <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , false , false , isKill ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ) ;


<s> bool <ISA_LIT>InstrInfo :: SubsumesPredicate ( const SmallVectorImpl < MachineOperand > & Pred1 , const SmallVectorImpl < MachineOperand > & Pred2 ) const { if ( Pred1 . size ( ) > <NUM_LIT> || Pred2 . size ( ) > <NUM_LIT> ) return false ; <STR_LIT> CC1 = ( <STR_LIT> ) Pred1 [ <NUM_LIT> ] . getImm ( ) ; <STR_LIT> CC2 = ( <STR_LIT> ) Pred2 [ <NUM_LIT> ] . getImm ( ) ; if ( CC1 == CC2 ) return true ; switch ( CC1 ) { default : return false ; case <STR_LIT> : return true ; case <STR_LIT> : return CC2 == <STR_LIT> ;


<s> <STR_LIT> CC1 = ( <STR_LIT> ) Pred1 [ <NUM_LIT> ] . getImm ( ) ; <STR_LIT> CC2 = ( <STR_LIT> ) Pred2 [ <NUM_LIT> ] . getImm ( ) ; if ( CC1 == CC2 ) return true ; switch ( CC1 ) { default : return false ; case <STR_LIT> : return true ; case <STR_LIT> : return CC2 == <STR_LIT> ; case <STR_LIT> : return CC2 == <STR_LIT> || CC2 == <STR_LIT> ; case <STR_LIT> : return CC2 == <STR_LIT> ; case <STR_LIT> : return CC2 == <STR_LIT> ; }


<s> DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; unsigned Opc = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetInstrInfo & TII = * TM -> getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ;


<s> unsigned TempReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; unsigned Opc = STI . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , TempReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; Opc = STI . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addReg ( TempReg ) . addImm ( <ISA_LIT>PCLabelIndex ) ; if ( Opc == <STR_LIT> ) AddDefaultPred ( MIB ) ;


<s> unsigned PCAdj = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * Context , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; unsigned Align = TM -> getSubtargetImpl ( ) -> getDataLayout ( ) -> getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned TempReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ;

unsigned Opc = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ;


return std :: make_pair ( TF & Mask , TF & ~ Mask ) ;


<s> { MO_GOT , <STR_LIT> } , { MO_SBREL , <STR_LIT> } , { MO_DLLIMPORT , <STR_LIT> } , { MO_SECREL , <STR_LIT> } , { MO_NONLAZY , <STR_LIT> } } ; return makeArrayRef ( TargetFlags ) ;


<s> { MO_LO16 , <STR_LIT> } , { MO_HI16 , <STR_LIT> } } ; return makeArrayRef ( TargetFlags ) ;


<s> if ( RM == Reloc :: PIC_ ) expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> , RM ) ; else expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> , RM ) ;


<s> void <ISA_LIT>InstrInfo :: expandLoadStackGuard ( MachineBasicBlock :: iterator MI ) const { MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; if ( ! Subtarget . useMovt ( MF ) ) { if ( TM . isPositionIndependent ( ) ) expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; else expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } if ( ! TM . isPositionIndependent ( ) ) { expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ;

if ( ! Subtarget . isGVIndirectSymbol ( GV ) ) {


<s> const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF . getTarget ( ) ) ; if ( TM -> getRelocationModel ( ) != Reloc :: PIC_ ) return false ; LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * Context , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; unsigned Align = TM -> getDataLayout ( ) -> getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; unsigned Opc = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetInstrInfo & TII = * TM -> getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; return true ;


<s> unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; unsigned Opc = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetInstrInfo & TII = * TM -> getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addConstantPoolIndex ( Idx ) ;

if ( Opc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ;


<s> NopInst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; } else { NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ;


<s> NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ;


<s> <ISA_LIT>CGBR ( ) : MachineFunctionPass ( ID ) {


<s> AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;


MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> } else { NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ;


<s> const char * getPassName ( ) const override { return <STR_LIT> ;


<s> unsigned Opc = STI . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , TempReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; Opc = STI . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ;

MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addReg ( TempReg ) . addImm ( <ISA_LIT>PCLabelIndex ) ;


<s> <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * Context , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; unsigned Align = MF . getDataLayout ( ) . getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned TempReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; unsigned Opc = STI . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , TempReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; Opc = STI . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addReg ( TempReg ) . addImm ( <ISA_LIT>PCLabelIndex ) ;

if ( Opc == <STR_LIT> ) AddDefaultPred ( MIB ) ;


<s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const <ISA_LIT>BaseTargetMachine & TM , const <ISA_LIT>Subtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI ) : InstructionSelector ( ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , TM ( TM ) , RBI ( RBI ) , STI ( STI ) , Opcodes ( STI ) , {


<s> CmpConstants ( unsigned CmpOpcode , unsigned FlagsOpcode , unsigned OpRegBank , unsigned OpSize ) : ComparisonOpcode ( CmpOpcode ) , ReadFlagsOpcode ( FlagsOpcode ) , OperandRegBankID ( OpRegBank ) , OperandSize ( OpSize ) {


<s> InstructionSelector * create<ISA_LIT>InstructionSelector ( const <ISA_LIT>BaseTargetMachine & TM , const <ISA_LIT>Subtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI ) { return new <ISA_LIT>InstructionSelector ( TM , STI , RBI ) ;


<s> break ; case CmpInst :: ICMP_SGT : case CmpInst :: FCMP_OGT : Preds . first = <STR_LIT> ; break ; case CmpInst :: ICMP_SGE : case CmpInst :: FCMP_OGE : Preds . first = <STR_LIT> ; break ; case CmpInst :: ICMP_UGT : case CmpInst :: FCMP_UGT : Preds . first = <STR_LIT> ; break ; case CmpInst :: FCMP_OLT : Preds . first = <STR_LIT> ; break ; case CmpInst :: ICMP_ULE : case CmpInst :: FCMP_OLE : Preds . first = <STR_LIT> ; break ; case CmpInst :: FCMP_ORD : Preds . first = <STR_LIT> ; break ; case CmpInst :: FCMP_UNO : Preds . first = <STR_LIT> ; break ; case CmpInst :: FCMP_UGE : Preds . first = <STR_LIT> ; break ; case CmpInst :: ICMP_SLT : case CmpInst :: FCMP_ULT : Preds . first = <STR_LIT> ; break ; case CmpInst :: ICMP_SLE : case CmpInst :: FCMP_ULE : Preds . first = <STR_LIT> ; break ; case CmpInst :: FCMP_UNE : case CmpInst :: ICMP_NE : Preds . first = <STR_LIT> ; break ; case CmpInst :: ICMP_UGE : Preds . first = <STR_LIT> ;


<s> const RegisterBank * RegBank = RBI . getRegBank ( Reg , MRI , TRI ) ; assert ( RegBank && <STR_LIT> ) ; const unsigned Size = MRI . getType ( Reg ) . getSizeInBits ( ) ; assert ( ( RegBank -> getID ( ) == <STR_LIT> || RegBank -> getID ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( RegBank -> getID ( ) == <STR_LIT> ) { if ( Size == <NUM_LIT> ) return & <STR_LIT> ; else if ( Size == <NUM_LIT> ) return & <STR_LIT> ;


<s> static const TargetRegisterClass * guessRegClass ( unsigned Reg , MachineRegisterInfo & MRI , const TargetRegisterInfo & TRI , const RegisterBankInfo & RBI ) { const RegisterBank * RegBank = RBI . getRegBank ( Reg , MRI , TRI ) ; assert ( RegBank && <STR_LIT> ) ; const unsigned Size = MRI . getType ( Reg ) . getSizeInBits ( ) ; assert ( ( RegBank -> getID ( ) == <STR_LIT> || RegBank -> getID ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( RegBank -> getID ( ) == <STR_LIT> ) { if ( Size == <NUM_LIT> ) return & <STR_LIT> ; else if ( Size == <NUM_LIT> ) return & <STR_LIT> ; else if ( Size == <NUM_LIT> ) return & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; }


<s> if ( ! constrainSelectedInstRegOperands ( * CmpI , TII , TRI , RBI ) ) return false ; if ( Helper . ReadFlagsOpcode != <STR_LIT> ) { auto ReadI = BuildMI ( I . MBB , I . InsertBefore , I . DbgLoc , TII . get ( Helper . ReadFlagsOpcode ) ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * ReadI , TII , TRI , RBI ) ) return false ;


<s> InsertInfo ( MachineInstrBuilder & MIB ) : MBB ( * MIB -> getParent ( ) ) , InsertBefore ( std :: next ( MIB -> getIterator ( ) ) ) , DbgLoc ( MIB -> getDebugLoc ( ) ) {


<s> ( void ) BuildMI ( I . MBB , I . InsertBefore , I . DbgLoc , TII . get ( <STR_LIT> ) ) . addDef ( DestReg ) . addImm ( Constant ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ;


<s> void <ISA_LIT>InstructionSelector :: putConstant ( InsertInfo I , unsigned DestReg , unsigned Constant ) const { ( void ) BuildMI ( I . MBB , I . InsertBefore , I . DbgLoc , TII . get ( <STR_LIT> ) ) . addDef ( DestReg ) . addImm ( Constant ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ;


<s> MIB -> eraseFromParent ( ) ; return true ; } auto LHSReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto RHSReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! validOpRegPair ( MRI , LHSReg , RHSReg , Helper . OperandSize , Helper . OperandRegBankID ) ) return false ; auto <ISA_LIT>Conds = getComparePreds ( Cond ) ; auto ZeroReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; putConstant ( I , ZeroReg , <NUM_LIT> ) ; if ( <ISA_LIT>Conds . second == <STR_LIT> ) { if ( ! insertComparison ( Helper , I , ResReg , <ISA_LIT>Conds . first , LHSReg , RHSReg , ZeroReg ) ) return false ; } else { auto IntermediateRes = MRI . createVirtualRegister ( & <STR_LIT> ) ; if ( ! insertComparison ( Helper , I , IntermediateRes , <ISA_LIT>Conds . first , LHSReg , RHSReg , ZeroReg ) ) return false ; if ( ! insertComparison ( Helper , I , ResReg , <ISA_LIT>Conds . second , LHSReg , RHSReg , IntermediateRes ) ) return false ; }


<s> auto LHSReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto RHSReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! validOpRegPair ( MRI , LHSReg , RHSReg , Helper . OperandSize , Helper . OperandRegBankID ) ) return false ; auto <ISA_LIT>Conds = getComparePreds ( Cond ) ; auto ZeroReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; putConstant ( I , ZeroReg , <NUM_LIT> ) ; if ( <ISA_LIT>Conds . second == <STR_LIT> ) { if ( ! insertComparison ( Helper , I , ResReg , <ISA_LIT>Conds . first , LHSReg , RHSReg , ZeroReg ) ) return false ; } else { auto IntermediateRes = MRI . createVirtualRegister ( & <STR_LIT> ) ;

if ( ! insertComparison ( Helper , I , IntermediateRes , <ISA_LIT>Conds . first , LHSReg , RHSReg , ZeroReg ) ) return false ;


<s> if ( ! RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return false ;


<s> bool UseMovt = STI . useMovt ( MF ) ; unsigned Size = TM . getPointerSize ( <NUM_LIT> ) ; unsigned Alignment = <NUM_LIT> ; auto addOpsForConstantPoolLoad = [ & MF , Alignment , Size ] ( MachineInstrBuilder & MIB , const GlobalValue * GV , bool IsSBREL ) { assert ( MIB -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; auto ConstPool = MF . getConstantPool ( ) ; auto CPIndex = IsSBREL ? ConstPool -> getConstantPoolIndex ( <ISA_LIT>ConstantPoolConstant :: Create ( GV , <STR_LIT> ) , Alignment ) : ConstPool -> getConstantPoolIndex ( GV , Alignment ) ; MIB . addConstantPoolIndex ( CPIndex , <NUM_LIT> , <NUM_LIT> ) . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( MF ) , MachineMemOperand :: MOLoad , Size , Alignment ) ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } ; if ( TM . isPositionIndependent ( ) ) { bool Indirect = STI . isGVIndirectSymbol ( GV ) ; unsigned Opc = UseMovt && ! STI . isTargetELF ( ) ? ( Indirect ? <STR_LIT> : <STR_LIT> ) : ( Indirect ? <STR_LIT> : <STR_LIT> ) ; MIB -> setDesc ( TII . get ( Opc ) ) ; int TargetFlags = <STR_LIT> ; if ( STI . isTargetDarwin ( ) ) TargetFlags |= <STR_LIT> ; if ( STI . isGVInGOT ( GV ) ) TargetFlags |= <STR_LIT> ;

MIB -> getOperand ( <NUM_LIT> ) . setTargetFlags ( TargetFlags ) ;


<s> } if ( STI . isRWPI ( ) && ! isReadOnly ) { auto Offset = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstrBuilder OffsetMIB ; if ( UseMovt ) { OffsetMIB = BuildMI ( MBB , * MIB , MIB -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , Offset ) ; OffsetMIB . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; } else { OffsetMIB = BuildMI ( MBB , * MIB , MIB -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , Offset ) ; addOpsForConstantPoolLoad ( OffsetMIB , GV , true ) ; } if ( ! constrainSelectedInstRegOperands ( * OffsetMIB , TII , TRI , RBI ) ) return false ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; MIB -> RemoveOperand ( <NUM_LIT> ) ; MIB . addReg ( <STR_LIT> ) . addReg ( Offset ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ; } if ( STI . isTargetELF ( ) ) { if ( UseMovt ) { MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; } else { MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; MIB -> RemoveOperand ( <NUM_LIT> ) ; addOpsForConstantPoolLoad ( MIB , GV , false ) ; } } else if ( STI . isTargetMachO ( ) ) {

if ( UseMovt ) MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ;


<s> unsigned <ISA_LIT>InstructionSelector :: selectLoadStoreOpCode ( unsigned Opc , unsigned RegBank , unsigned Size ) const { bool isStore = Opc == TargetOpcode :: G_STORE ; if ( RegBank == <STR_LIT> ) { switch ( Size ) { case <NUM_LIT> : case <NUM_LIT> : return isStore ? Opcodes . STORE8 : Opcodes . LOAD8 ;


<s> assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg2 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg2 ; assert ( MRI . getType ( VReg2 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg2 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; return true ;


<s> static bool selectMergeValues ( MachineInstrBuilder & MIB , const <ISA_LIT>BaseInstrInfo & TII , MachineRegisterInfo & MRI , const TargetRegisterInfo & TRI , const RegisterBankInfo & RBI ) { assert ( TII . getSubtarget ( ) . hasVFP2 ( ) && <STR_LIT> ) ; unsigned VReg0 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg0 ; assert ( MRI . getType ( VReg0 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg0 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ;

unsigned VReg2 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> auto InsertBefore = std :: next ( MIB -> getIterator ( ) ) ; auto & DbgLoc = MIB -> getDebugLoc ( ) ; auto CondReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( validReg ( MRI , CondReg , <NUM_LIT> , <STR_LIT> ) && <STR_LIT> ) ; auto CmpI = BuildMI ( MBB , InsertBefore , DbgLoc , TII . get ( <STR_LIT> ) ) . addUse ( CondReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * CmpI , TII , TRI , RBI ) ) return false ; auto ResReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto TrueReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto FalseReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( validOpRegPair ( MRI , ResReg , TrueReg , <NUM_LIT> , <STR_LIT> ) && validOpRegPair ( MRI , TrueReg , FalseReg , <NUM_LIT> , <STR_LIT> ) && <STR_LIT> ) ; auto Mov1I = BuildMI ( MBB , InsertBefore , DbgLoc , TII . get ( <STR_LIT> ) ) . addDef ( ResReg ) . addUse ( TrueReg ) . addUse ( FalseReg ) . add ( predOps ( <STR_LIT> , <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * Mov1I , TII , TRI , RBI ) ) return false ;


<s> bool <ISA_LIT>InstructionSelector :: selectShift ( unsigned ShiftOpc , MachineInstrBuilder & MIB ) const { MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . addImm ( ShiftOpc ) ; MIB . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ;

return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ;


<s> if ( Size != <NUM_LIT> && Size != <NUM_LIT> ) return Opc ;

if ( Opc == G_SEXT ) return Size == <NUM_LIT> ? Opcodes . SEXT8 : Opcodes . SEXT16 ;


<s> assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg2 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg2 ;

assert ( MRI . getType ( VReg2 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg2 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ;


<s> unsigned VReg0 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg0 ; assert ( MRI . getType ( VReg0 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg0 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> bool <ISA_LIT>InstructionSelector :: validOpRegPair ( MachineRegisterInfo & MRI , unsigned LHSReg , unsigned RHSReg , unsigned ExpectedSize , unsigned ExpectedRegBankID ) const { return MRI . getType ( LHSReg ) == MRI . getType ( RHSReg ) && validReg ( MRI , LHSReg , ExpectedSize , ExpectedRegBankID ) && validReg ( MRI , RHSReg , ExpectedSize , ExpectedRegBankID ) ;


<s> if ( MRI . getType ( Reg ) . getSizeInBits ( ) != ExpectedSize ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( RBI . getRegBank ( Reg , MRI , TRI ) -> getID ( ) != ExpectedRegBankID ) {


<s> bool <ISA_LIT>InstructionSelector :: validReg ( MachineRegisterInfo & MRI , unsigned Reg , unsigned ExpectedSize , unsigned ExpectedRegBankID ) const { if ( MRI . getType ( Reg ) . getSizeInBits ( ) != ExpectedSize ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( RBI . getRegBank ( Reg , MRI , TRI ) -> getID ( ) != ExpectedRegBankID ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; }


<s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const <ISA_LIT>Subtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI ) : InstructionSelector ( ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , RBI ( RBI ) {


<s> auto & MRI = MF . getRegInfo ( ) ; if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { if ( I . isCopy ( ) ) return selectCopy ( I , TII , MRI , TRI , RBI ) ; return true ; } MachineInstrBuilder MIB { MF , I } ; using namespace TargetOpcode ; switch ( I . getOpcode ( ) ) { case G_ADD : I . setDesc ( TII . get ( <STR_LIT> ) ) ; AddDefaultCC ( AddDefaultPred ( MIB ) ) ; break ; case G_FRAME_INDEX : I . setDesc ( TII . get ( <STR_LIT> ) ) ; AddDefaultCC ( AddDefaultPred ( MIB . addImm ( <NUM_LIT> ) ) ) ; break ; case G_LOAD :


<s> assert ( ( DstSize == SrcSize || ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && DstSize <= SrcSize ) ) && <STR_LIT> ) ; assert ( RegBank -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( ! RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ) {

DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ;


<s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const <ISA_LIT>BaseTargetMachine & TM , const <ISA_LIT>Subtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI ) : InstructionSelector ( ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , TM ( TM ) , RBI ( RBI ) , STI ( STI ) , {


<s> const RegisterBank * RegBank = RBI . getRegBank ( Reg , MRI , TRI ) ; assert ( RegBank && <STR_LIT> ) ; const unsigned Size = MRI . getType ( Reg ) . getSizeInBits ( ) ; assert ( ( RegBank -> getID ( ) == <STR_LIT> || RegBank -> getID ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( RegBank -> getID ( ) == <STR_LIT> ) { if ( Size == <NUM_LIT> ) return & <STR_LIT> ;


<s> static bool selectCopy ( MachineInstr & I , const TargetInstrInfo & TII , MachineRegisterInfo & MRI , const TargetRegisterInfo & TRI , const RegisterBankInfo & RBI ) { unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DstReg ) ) return true ; const TargetRegisterClass * RC = guessRegClass ( DstReg , MRI , TRI , RBI ) ; if ( ! RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ;


<s> if ( STI . isTargetDarwin ( ) ) TargetFlags |= <STR_LIT> ; if ( STI . isGVInGOT ( GV ) ) TargetFlags |= <STR_LIT> ; MIB -> getOperand ( <NUM_LIT> ) . setTargetFlags ( TargetFlags ) ; if ( Indirect ) MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getGOT ( MF ) , MachineMemOperand :: MOLoad , TM . getPointerSize ( ) , Alignment ) ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ; } bool isReadOnly = STI . getTargetLowering ( ) -> isReadOnly ( GV ) ; if ( STI . isROPI ( ) && isReadOnly ) { unsigned Opc = UseMovt ? <STR_LIT> : <STR_LIT> ; MIB -> setDesc ( TII . get ( Opc ) ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ; } if ( STI . isRWPI ( ) && ! isReadOnly ) { auto Offset = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstrBuilder OffsetMIB ; if ( UseMovt ) { OffsetMIB = BuildMI ( MBB , * MIB , MIB -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , Offset ) ; OffsetMIB . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; } else { OffsetMIB = BuildMI ( MBB , * MIB , MIB -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , Offset ) ; addOpsForConstantPoolLoad ( OffsetMIB , GV , true ) ; } if ( ! constrainSelectedInstRegOperands ( * OffsetMIB , TII , TRI , RBI ) ) return false ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; MIB -> RemoveOperand ( <NUM_LIT> ) ; MIB . addReg ( <STR_LIT> ) . addReg ( Offset ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ;


<s> switch ( Size ) { case <NUM_LIT> : case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; default : return Opc ; } } if ( RegBank == <STR_LIT> ) { switch ( Size ) { case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; default : return Opc ; } }


<s> case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; default : return Opc ; } }


<s> if ( Opc == G_SEXT ) return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ;

if ( Opc == G_ZEXT ) return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ;


<s> bool <ISA_LIT>InstructionSelector :: validReg ( MachineRegisterInfo & MRI , unsigned Reg , unsigned ExpectedSize , unsigned ExpectedRegBankID ) const { if ( MRI . getType ( Reg ) . getSizeInBits ( ) != ExpectedSize ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( RBI . getRegBank ( Reg , MRI , TRI ) -> getID ( ) != ExpectedRegBankID ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; }


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } LLT SrcTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned SrcSize = SrcTy . getSizeInBits ( ) ; switch ( SrcSize ) { case <NUM_LIT> : { I . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; if ( isSExt ) { unsigned SExtResult = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AndResult = MRI . createVirtualRegister ( & <STR_LIT> ) ; I . getOperand ( <NUM_LIT> ) . setReg ( AndResult ) ; auto InsertBefore = std :: next ( I . getIterator ( ) ) ; auto SubI = BuildMI ( MBB , InsertBefore , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( SExtResult ) . addUse ( AndResult ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; if ( ! constrainSelectedInstRegOperands ( * SubI , TII , TRI , RBI ) ) return false ; } break ; } case <NUM_LIT> : case <NUM_LIT> : { unsigned NewOpc = selectSimpleExtOpc ( I . getOpcode ( ) , SrcSize ) ; I . setDesc ( TII . get ( NewOpc ) ) ; MIB . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; break ; } default : DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } break ; } case G_ADD : I . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ;


<s> if ( ! constrainSelectedInstRegOperands ( * SubI , TII , TRI , RBI ) ) return false ; } break ; } case <NUM_LIT> : case <NUM_LIT> : { unsigned NewOpc = selectSimpleExtOpc ( I . getOpcode ( ) , SrcSize ) ; I . setDesc ( TII . get ( NewOpc ) ) ; MIB . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; break ; } default : DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } break ; } case G_ADD : I . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; break ; case G_FRAME_INDEX : I . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; break ; case G_LOAD : { LLT ValTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; const auto ValSize = ValTy . getSizeInBits ( ) ; if ( ValSize != <NUM_LIT> && ValSize != <NUM_LIT> && ValSize != <NUM_LIT> && ValSize != <NUM_LIT> ) return false ; const auto NewOpc = selectLoadOpCode ( ValSize ) ; I . setDesc ( TII . get ( NewOpc ) ) ;

if ( NewOpc == <STR_LIT> ) MIB . addReg ( <NUM_LIT> ) ;


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> :


<s> ( void ) SrcSize ; assert ( ( DstSize == SrcSize || ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && DstSize <= SrcSize ) ) && <STR_LIT> ) ; assert ( ( RegBank -> getID ( ) == <STR_LIT> || RegBank -> getID ( ) == <STR_LIT> ) && <STR_LIT> ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( RegBank -> getID ( ) == <STR_LIT> ) { if ( DstSize == <NUM_LIT> ) RC = & <STR_LIT> ; else if ( DstSize == <NUM_LIT> ) RC = & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; } if ( ! RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ;


<s> static bool selectExtract ( MachineInstrBuilder & MIB , const <ISA_LIT>BaseInstrInfo & TII , MachineRegisterInfo & MRI , const TargetRegisterInfo & TRI , const RegisterBankInfo & RBI ) { assert ( TII . getSubtarget ( ) . hasVFP2 ( ) && <STR_LIT> ) ; unsigned VReg0 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg0 ; assert ( MRI . getType ( VReg0 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg0 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg2 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg2 ;


<s> LLT Ty = MRI . getType ( MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned ValSize = Ty . getSizeInBits ( ) ; if ( ValSize == <NUM_LIT> ) { if ( TII . getSubtarget ( ) . useNEONForSinglePrecisionFP ( ) ) return false ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; } else {

assert ( ValSize == <NUM_LIT> && <STR_LIT> ) ;


<s> unsigned VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg2 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg2 ; assert ( MRI . getType ( VReg2 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg2 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; MIB -> RemoveOperand ( <NUM_LIT> ) ; MIB -> RemoveOperand ( <NUM_LIT> ) ;

MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ;


<s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const <ISA_LIT>BaseTargetMachine & TM , const <ISA_LIT>Subtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI ) : TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , TM ( TM ) , RBI ( RBI ) , STI ( STI ) , Opcodes ( STI ) , {


<s> CmpConstants ( unsigned CmpOpcode , unsigned FlagsOpcode , unsigned SelectOpcode , unsigned OpRegBank , unsigned OpSize ) : ComparisonOpcode ( CmpOpcode ) , ReadFlagsOpcode ( FlagsOpcode ) , SelectResultOpcode ( SelectOpcode ) , OperandRegBankID ( OpRegBank ) , OperandSize ( OpSize ) {


<s> bool <ISA_LIT>InstructionSelector :: insertComparison ( CmpConstants Helper , InsertInfo I , unsigned ResReg , <STR_LIT> Cond , unsigned LHSReg , unsigned RHSReg , unsigned PrevRes ) const { auto CmpI = BuildMI ( I . MBB , I . InsertBefore , I . DbgLoc , TII . get ( Helper . ComparisonOpcode ) ) . addUse ( LHSReg ) . addUse ( RHSReg ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * CmpI , TII , TRI , RBI ) ) return false ; if ( Helper . ReadFlagsOpcode != <STR_LIT> ) {

auto ReadI = BuildMI ( I . MBB , I . InsertBefore , I . DbgLoc , TII . get ( Helper . ReadFlagsOpcode ) ) . add ( predOps ( <STR_LIT> ) ) ;


<s> if ( ! constrainSelectedInstRegOperands ( * ReadI , TII , TRI , RBI ) ) return false ; } auto Mov1I = BuildMI ( I . MBB , I . InsertBefore , I . DbgLoc , TII . get ( Helper . SelectResultOpcode ) ) . addDef ( ResReg ) . addUse ( PrevRes ) . addImm ( <NUM_LIT> ) . add ( predOps ( Cond , <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * Mov1I , TII , TRI , RBI ) ) return false ; return true ;


<s> void <ISA_LIT>InstructionSelector :: putConstant ( InsertInfo I , unsigned DestReg , unsigned Constant ) const { ( void ) BuildMI ( I . MBB , I . InsertBefore , I . DbgLoc , TII . get ( Opcodes . MOVi ) ) . addDef ( DestReg ) . addImm ( Constant ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ;


<s> void <ISA_LIT>InstructionSelector :: renderVFPF32Imm ( MachineInstrBuilder & NewInstBuilder , const MachineInstr & OldInst , int OpIdx ) const { assert ( OldInst . getOpcode ( ) == TargetOpcode :: G_FCONSTANT && OpIdx == - <NUM_LIT> && <STR_LIT> ) ; APFloat FPImmValue = OldInst . getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ;

int FPImmEncoding = <STR_LIT> ( FPImmValue ) ;


<s> APFloat FPImmValue = OldInst . getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; int FPImmEncoding = <STR_LIT> ( FPImmValue ) ;

assert ( FPImmEncoding != - <NUM_LIT> && <STR_LIT> ) ;


<s> APFloat FPImmValue = OldInst . getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ;


<s> void <ISA_LIT>InstructionSelector :: renderVFPF64Imm ( MachineInstrBuilder & NewInstBuilder , const MachineInstr & OldInst , int OpIdx ) const { assert ( OldInst . getOpcode ( ) == TargetOpcode :: G_FCONSTANT && OpIdx == - <NUM_LIT> && <STR_LIT> ) ;

APFloat FPImmValue = OldInst . getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ;