<s> unsigned TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> ) emitThumbRegPlusImmInReg ( MBB , II , dl , TmpReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , TmpReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else { emitThumbRegPlusImmediate ( MBB , II , dl , TmpReg , FrameReg , Offset , TII , * this ) ; } MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( i ) . ChangeToRegister ( TmpReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( i + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else if ( MI . mayStore ( ) ) { VReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> ) emitThumbRegPlusImmInReg ( MBB , II , dl , VReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , VReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else emitThumbRegPlusImmediate ( MBB , II , dl , VReg , FrameReg , Offset , TII , * this ) ; MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( i ) . ChangeToRegister ( VReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( i + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( MI . isPredicable ( ) ) AddDefaultPred ( MIB ) ;


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const TargetInstrInfo & TII , DebugLoc dl , const Thumb1RegisterInfo & MRI , int NumBytes ) { emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , <STR_LIT> , NumBytes , TII , MRI ) ;


<s> else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ; } else { if ( MBBI -> getOpcode ( ) == <STR_LIT> && & MBB . front ( ) != MBBI && prior ( MBBI ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PMBBI = prior ( MBBI ) ; emitSPUpdate ( MBB , PMBBI , TII , dl , * this , NumBytes ) ; } else emitSPUpdate ( MBB , MBBI , TII , dl , * this , NumBytes ) ; } } if ( VARegSaveSize ) { while ( MBBI != MBB . end ( ) && isCSRestore ( MBBI , CSRegs ) ) ++ MBBI ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ) . addReg ( <NUM_LIT> ) . addReg ( <STR_LIT> , RegState :: Define ) ; emitSPUpdate ( MBB , MBBI , TII , dl , * this , VARegSaveSize ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetDarwin ( ) ) { AFI -> addGPRCalleeSavedArea2Frame ( FI ) ; GPRCS2Size += <NUM_LIT> ; } else { AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; } break ; default : AFI -> addDPRCalleeSavedAreaFrame ( FI ) ; DPRCSSize += <NUM_LIT> ; } } if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { ++ MBBI ; if ( MBBI != MBB . end ( ) ) dl = MBBI -> getDebugLoc ( ) ; } if ( STI . isTargetDarwin ( ) || hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FramePtr ) . addFrameIndex ( FramePtrSpillFI ) . addImm ( <NUM_LIT> ) ; } unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI ) + NumBytes ) ; AFI -> setGPRCalleeSavedArea1Offset ( GPRCS1Offset ) ; AFI -> setGPRCalleeSavedArea2Offset ( GPRCS2Offset ) ; AFI -> setDPRCalleeSavedAreaOffset ( DPRCSOffset ) ; NumBytes = DPRCSOffset ; if ( NumBytes ) { emitSPUpdate ( MBB , MBBI , TII , dl , * this , - NumBytes ) ; } if ( STI . isTargetELF ( ) && hasFP ( MF ) ) { MFI -> setOffsetAdjustment ( MFI -> getOffsetAdjustment ( ) - AFI -> getFramePtrSpillOffset ( ) ) ; } AFI -> setGPRCalleeSavedArea1Size ( GPRCS1Size ) ; AFI -> setGPRCalleeSavedArea2Size ( GPRCS2Size ) ;

AFI -> setDPRCalleeSavedAreaSize ( DPRCSSize ) ;


<s> static void emitThumbRegPlusImmInReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned DestReg , unsigned BaseReg , int NumBytes , bool CanChangeCC , const TargetInstrInfo & TII , const Thumb1RegisterInfo & MRI , DebugLoc dl ) { MachineFunction & MF = * MBB . getParent ( ) ; bool isHigh = ! is<ISA_LIT>LowRegister ( DestReg ) || ( BaseReg != <NUM_LIT> && ! is<ISA_LIT>LowRegister ( BaseReg ) ) ; bool isSub = false ; if ( NumBytes < <NUM_LIT> && ! isHigh && CanChangeCC ) { isSub = true ; NumBytes = - NumBytes ; } unsigned LdReg = DestReg ; if ( DestReg == <STR_LIT> ) { assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; LdReg = MF . getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; } if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> ) AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) ; else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) ;

AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addReg ( LdReg , RegState :: Kill ) ;


<s> for ( int i = <NUM_LIT> , e = MI -> getNumOperands ( ) - <NUM_LIT> ; i != e ; ++ i ) if ( ! isCalleeSavedRegister ( MI -> getOperand ( i ) . getReg ( ) , CSRegs ) ) return false ; return true ;


<s> bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> ) emitThumbRegPlusImmInReg ( MBB , II , dl , TmpReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , TmpReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else { emitThumbRegPlusImmediate ( MBB , II , dl , TmpReg , FrameReg , Offset , TII , * this ) ; } MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( i ) . ChangeToRegister ( TmpReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( i + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else if ( MI . mayStore ( ) ) { VReg = MF . getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> ) emitThumbRegPlusImmInReg ( MBB , II , dl , VReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , VReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else emitThumbRegPlusImmediate ( MBB , II , dl , VReg , FrameReg , Offset , TII , * this ) ; MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( i ) . ChangeToRegister ( VReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( i + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else { assert ( false && <STR_LIT> ) ;


<s> isSub = true ; NumBytes = - NumBytes ; } unsigned LdReg = DestReg ; if ( DestReg == <STR_LIT> ) { assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; LdReg = MF . getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; } if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> ) AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addReg ( LdReg , RegState :: Kill ) . setMIFlags ( MIFlags ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , dl , LdReg , <NUM_LIT> , NumBytes , <STR_LIT> , <NUM_LIT> , MIFlags ) ; int Opc = ( isSub ) ? <STR_LIT> : ( isHigh ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ; if ( Opc != <STR_LIT> ) MIB = AddDefaultT1CC ( MIB ) ;

if ( DestReg == <STR_LIT> || isSub ) MIB . addReg ( BaseReg ) . addReg ( LdReg , RegState :: Kill ) ;


<s> } if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> ) AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addReg ( LdReg , RegState :: Kill ) . setMIFlags ( MIFlags ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , dl , LdReg , <NUM_LIT> , NumBytes , <STR_LIT> , <NUM_LIT> , MIFlags ) ; int Opc = ( isSub ) ? <STR_LIT> : ( isHigh ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ; if ( Opc != <STR_LIT> ) MIB = AddDefaultT1CC ( MIB ) ; if ( DestReg == <STR_LIT> || isSub ) MIB . addReg ( BaseReg ) . addReg ( LdReg , RegState :: Kill ) ; else MIB . addReg ( LdReg ) . addReg ( BaseReg , RegState :: Kill ) ; AddDefaultPred ( MIB ) ;


<s> const TargetRegisterClass * Thumb1RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC ) const {

if ( <STR_LIT> . hasSubClassEq ( RC ) ) return <STR_LIT> ;


<s> const TargetRegisterClass * Thumb1RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC ) const { if ( <STR_LIT> . hasSubClassEq ( RC ) ) return <STR_LIT> ; return <ISA_LIT>BaseRegisterInfo :: getLargestLegalSuperClass ( RC ) ;


<s> if ( Opcode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; if ( FrameReg != <STR_LIT> ) { Opcode = <STR_LIT> ; NumBits = <NUM_LIT> ; } else { NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; assert ( ( Offset & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; } unsigned PredReg ; if ( Offset == <NUM_LIT> && getInstrPredicate ( & MI , PredReg ) == <STR_LIT> ) { MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . RemoveOperand ( FrameRegIdx + <NUM_LIT> ) ; MachineInstrBuilder MIB ( & MI ) ; return true ; } unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( ( Offset / Scale ) & ~ Mask ) == <NUM_LIT> ) { if ( Opcode == <STR_LIT> ) { MI . setDesc ( TII . get ( Opcode ) ) ; removeOperands ( MI , FrameRegIdx ) ; MachineInstrBuilder MIB ( & MI ) ; AddDefaultPred ( AddDefaultT1CC ( MIB ) . addReg ( FrameReg ) . addImm ( Offset / Scale ) ) ; } else { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( Offset / Scale ) ; } return true ; } unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Bytes = ( Offset > <NUM_LIT> ) ? Offset : - Offset ; unsigned NumMIs = calcNumMI ( Opcode , <NUM_LIT> , Bytes , NumBits , Scale ) ; if ( NumMIs > <NUM_LIT> ) { emitThumbRegPlusImmediate ( MBB , II , dl , DestReg , FrameReg , Offset , TII , * this ) ; MBB . erase ( II ) ; return true ; } if ( Offset > <NUM_LIT> ) { if ( Opcode == <STR_LIT> ) { MI . setDesc ( TII . get ( Opcode ) ) ; removeOperands ( MI , FrameRegIdx ) ; MachineInstrBuilder MIB ( & MI ) ; AddDefaultPred ( AddDefaultT1CC ( MIB ) . addReg ( FrameReg ) . addImm ( Mask ) ) ; } else { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( Mask ) ; } Offset = ( Offset - Mask * Scale ) ; MachineBasicBlock :: iterator NII = llvm :: next ( II ) ;

emitThumbRegPlusImmediate ( MBB , NII , dl , DestReg , DestReg , Offset , TII , * this ) ;


<s> DebugLoc DL ; AddDefaultPred ( BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugValue ( ) ) continue ; for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i != e ; ++ i ) {

const MachineOperand & MO = II -> getOperand ( i ) ;


<s> DebugLoc DL ; AddDefaultPred ( BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugValue ( ) ) continue ; for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) { UseMI = II ; done = true ; break ; } }


<s> const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB ( * MBB . getParent ( ) , & MI ) ; unsigned FrameReg = <STR_LIT> ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MF . getFrameInfo ( ) -> getStackSize ( ) + SPAdj ; if ( MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ) { assert ( SPAdj == <NUM_LIT> && MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) && <STR_LIT> ) ; if ( ! hasBasePointer ( MF ) ) { FrameReg = getFrameRegister ( MF ) ; Offset -= AFI -> getFramePtrSpillOffset ( ) ; } else FrameReg = BasePtr ; } if ( RS && FrameReg == <STR_LIT> && RS -> isScavengingFrameIndex ( FrameIndex ) ) { assert ( MF . getTarget ( ) . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) && <STR_LIT> <STR_LIT> ) ; assert ( ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) && <STR_LIT> <STR_LIT> ) ; } if ( MI . isDebugValue ( ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; }

assert ( AFI -> isThumbFunction ( ) && <STR_LIT> ) ;


<s> void Thumb1RegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ;


<s> void Thumb1RegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ;

BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ;


<s> int Off = Offset ; unsigned i = <NUM_LIT> ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } bool Done = rewriteFrameIndex ( MI , i , BaseReg , Off , TII ) ; assert ( Done && <STR_LIT> ) ;


<s> ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } bool Done = rewriteFrameIndex ( MI , i , BaseReg , Off , TII ) ; assert ( Done && <STR_LIT> ) ;


<s> if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { UseMI = II ; done = true ; break ; } if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) { UseMI = II ; done = true ; break ; } } } AddDefaultPred ( BuildMI ( MBB , UseMI , DL , TII . get ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) ) ; return true ;


<s> Thumb1RegisterInfo :: Thumb1RegisterInfo ( const <ISA_LIT>Subtarget & sti ) : <ISA_LIT>BaseRegisterInfo ( sti ) {


<s> MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } assert ( AFI -> isThumbFunction ( ) && <STR_LIT> ) ; if ( rewriteFrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( Offset && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands ( MI , PIdx ) ; if ( MI . mayLoad ( ) ) { unsigned TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> ) emitThumbRegPlusImmInReg ( MBB , II , dl , TmpReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , TmpReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else { emitThumbRegPlusImmediate ( MBB , II , dl , TmpReg , FrameReg , Offset , TII , * this ) ; } MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( TmpReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else if ( MI . mayStore ( ) ) { VReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> ) emitThumbRegPlusImmInReg ( MBB , II , dl , VReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , VReg , <NUM_LIT> , Offset ) ;


<s> while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } bool Done = rewriteFrameIndex ( MI , i , BaseReg , Off , TII ) ;


<s> const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ;


<s> ExtraNeedsCC = true ; } else { if ( DestReg == BaseReg ) { } else { CopyOpc = <STR_LIT> ; CopyBits = <NUM_LIT> ; } ExtraOpc = <NUM_LIT> ; } assert ( ( ( Bytes & <NUM_LIT> ) == <NUM_LIT> || ExtraScale == <NUM_LIT> ) && <STR_LIT> ) ; unsigned CopyRange = ( ( <NUM_LIT> << CopyBits ) - <NUM_LIT> ) * CopyScale ; if ( CopyOpc && Bytes < CopyScale ) { CopyOpc = <STR_LIT> ; CopyScale = <NUM_LIT> ; CopyNeedsCC = false ; CopyRange = <NUM_LIT> ; } unsigned ExtraRange = ( ( <NUM_LIT> << ExtraBits ) - <NUM_LIT> ) * ExtraScale ; unsigned RequiredCopyInstrs = CopyOpc ? <NUM_LIT> : <NUM_LIT> ; unsigned RangeAfterCopy = ( CopyRange > Bytes ) ? <NUM_LIT> : ( Bytes - CopyRange ) ; assert ( RangeAfterCopy % ExtraScale == <NUM_LIT> && <STR_LIT> ) ; unsigned RequiredExtraInstrs ; if ( ExtraRange ) RequiredExtraInstrs = RoundUpToAlignment ( RangeAfterCopy , ExtraRange ) / ExtraRange ; else if ( RangeAfterCopy > <NUM_LIT> ) RequiredExtraInstrs = <NUM_LIT> ; else RequiredExtraInstrs = <NUM_LIT> ; unsigned RequiredInstrs = RequiredCopyInstrs + RequiredExtraInstrs ; unsigned Threshold = ( DestReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( RequiredInstrs > Threshold ) { emitThumbRegPlusImmInReg ( MBB , MBBI , dl , DestReg , BaseReg , NumBytes , true , TII , MRI , MIFlags ) ; return ; }


<s> } else { CopyOpc = <STR_LIT> ; CopyBits = <NUM_LIT> ; } ExtraOpc = isSub ? <STR_LIT> : <STR_LIT> ; ExtraBits = <NUM_LIT> ; ExtraNeedsCC = true ; } else { if ( DestReg == BaseReg ) { } else { CopyOpc = <STR_LIT> ; CopyBits = <NUM_LIT> ; } ExtraOpc = <NUM_LIT> ; } assert ( ( ( Bytes & <NUM_LIT> ) == <NUM_LIT> || ExtraScale == <NUM_LIT> ) && <STR_LIT> ) ; unsigned CopyRange = ( ( <NUM_LIT> << CopyBits ) - <NUM_LIT> ) * CopyScale ; if ( CopyOpc && Bytes < CopyScale ) { CopyOpc = <STR_LIT> ; CopyScale = <NUM_LIT> ; CopyNeedsCC = false ; CopyRange = <NUM_LIT> ; } unsigned ExtraRange = ( ( <NUM_LIT> << ExtraBits ) - <NUM_LIT> ) * ExtraScale ; unsigned RequiredCopyInstrs = CopyOpc ? <NUM_LIT> : <NUM_LIT> ; unsigned RangeAfterCopy = ( CopyRange > Bytes ) ? <NUM_LIT> : ( Bytes - CopyRange ) ; assert ( RangeAfterCopy % ExtraScale == <NUM_LIT> && <STR_LIT> ) ; unsigned RequiredExtraInstrs ; if ( ExtraRange ) RequiredExtraInstrs = RoundUpToAlignment ( RangeAfterCopy , ExtraRange ) / ExtraRange ; else if ( RangeAfterCopy > <NUM_LIT> ) RequiredExtraInstrs = <NUM_LIT> ; else RequiredExtraInstrs = <NUM_LIT> ;

unsigned RequiredInstrs = RequiredCopyInstrs + RequiredExtraInstrs ;


<s> if ( DestReg == <STR_LIT> ) assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; if ( ! is<ISA_LIT>LowRegister ( DestReg ) && ! MRI . isVirtualRegister ( DestReg ) ) LdReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> && CanChangeCC ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> && CanChangeCC ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addReg ( LdReg , RegState :: Kill ) . setMIFlags ( MIFlags ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , dl , LdReg , <NUM_LIT> , NumBytes , <STR_LIT> , <NUM_LIT> , MIFlags ) ; int Opc = ( isSub ) ? <STR_LIT> : ( ( isHigh || ! CanChangeCC ) ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ; if ( Opc != <STR_LIT> ) MIB = AddDefaultT1CC ( MIB ) ; if ( DestReg == <STR_LIT> || isSub ) MIB . addReg ( BaseReg ) . addReg ( LdReg , RegState :: Kill ) ; else MIB . addReg ( LdReg ) . addReg ( BaseReg , RegState :: Kill ) ;


<s> if ( DestReg == <STR_LIT> ) assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; if ( ! is<ISA_LIT>LowRegister ( DestReg ) && ! MRI . isVirtualRegister ( DestReg ) ) LdReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> && CanChangeCC ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> && CanChangeCC ) {


<s> int InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; unsigned NumBits = ( FrameReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; Offset += InstrOffs * Scale ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand & ImmOp = MI . getOperand ( ImmIdx ) ; int ImmedOffset = Offset / Scale ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( unsigned ) Offset <= Mask * Scale ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; ImmOp . ChangeToImmediate ( ImmedOffset ) ; unsigned NewOpc = convertToNonSPOpcode ( Opcode ) ; if ( NewOpc != Opcode && FrameReg != <STR_LIT> ) MI . setDesc ( TII . get ( NewOpc ) ) ; return true ; } NumBits = <NUM_LIT> ; Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { ImmOp . ChangeToImmediate ( <NUM_LIT> ) ; } else { ImmedOffset = ImmedOffset & Mask ; ImmOp . ChangeToImmediate ( ImmedOffset ) ; Offset &= ~ ( Mask * Scale ) ;


<s> MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB ( * MBB . getParent ( ) , & MI ) ; unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MI . getDesc ( ) ; unsigned AddrMode = ( Desc . TSFlags & <STR_LIT> ) ; if ( Opcode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; emitThumbRegPlusImmediate ( MBB , II , dl , DestReg , FrameReg , Offset , TII , * this ) ; MBB . erase ( II ) ; return true ; } else { if ( AddrMode != <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; unsigned ImmIdx = FrameRegIdx + <NUM_LIT> ; int InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; unsigned NumBits = ( FrameReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ;


<s> if ( ! hasBasePointer ( MF ) ) { FrameReg = getFrameRegister ( MF ) ; Offset -= AFI -> getFramePtrSpillOffset ( ) ; } else FrameReg = BasePtr ; } if ( MI . isDebugValue ( ) ) { MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } assert ( AFI -> isThumbFunction ( ) && <STR_LIT> ) ; if ( rewriteFrameIndex ( MI , i , FrameReg , Offset , TII ) ) return ; assert ( Offset && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MI . getDesc ( ) ; int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands ( MI , PIdx ) ; if ( Desc . mayLoad ( ) ) { unsigned TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> ) emitThumbRegPlusImmInReg ( MBB , II , dl , TmpReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , TmpReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else { emitThumbRegPlusImmediate ( MBB , II , dl , TmpReg , FrameReg , Offset , TII , * this ) ; }

MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ;


<s> } else { emitThumbRegPlusImmediate ( MBB , II , dl , TmpReg , FrameReg , Offset , TII , * this ) ; } MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( i ) . ChangeToRegister ( TmpReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( i + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else if ( Desc . mayStore ( ) ) { VReg = MF . getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> ) emitThumbRegPlusImmInReg ( MBB , II , dl , VReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , VReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else emitThumbRegPlusImmediate ( MBB , II , dl , VReg , FrameReg , Offset , TII , * this ) ; MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( i ) . ChangeToRegister ( VReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( i + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else {


<s> unsigned Bytes = ( unsigned ) NumBytes ; if ( isSub ) Bytes = - NumBytes ; bool isMul4 = ( Bytes & <NUM_LIT> ) == <NUM_LIT> ; bool isTwoAddr = false ; bool DstNotEqBase = false ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; int Opc = <NUM_LIT> ; int ExtraOpc = <NUM_LIT> ; bool NeedCC = false ; if ( DestReg == BaseReg && BaseReg == <STR_LIT> ) { assert ( isMul4 && <STR_LIT> ) ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; isTwoAddr = true ; } else if ( ! isSub && BaseReg == <STR_LIT> ) { if ( ! isMul4 ) { Bytes &= ~ <NUM_LIT> ; ExtraOpc = <STR_LIT> ; } DstNotEqBase = true ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; Opc = <STR_LIT> ; } else { if ( DestReg != BaseReg ) DstNotEqBase = true ; NumBits = <NUM_LIT> ; if ( DestReg == <STR_LIT> ) { Opc = isSub ? <STR_LIT> : <STR_LIT> ; assert ( isMul4 && <STR_LIT> ) ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; } else { Opc = isSub ? <STR_LIT> : <STR_LIT> ; NumBits = <NUM_LIT> ; NeedCC = true ; } isTwoAddr = true ; } unsigned NumMIs = calcNumMI ( Opc , ExtraOpc , Bytes , NumBits , Scale ) ; unsigned Threshold = ( DestReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( NumMIs > Threshold ) { emitThumbRegPlusImmInReg ( MBB , MBBI , dl , DestReg , BaseReg , NumBytes , true , TII , MRI , MIFlags ) ; return ; }


<s> for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) { UseMI = II ; done = true ; break ; } } }

BuildMI ( MBB , UseMI , DL , TII . get ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) ;


<s> for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) { UseMI = II ;


<s> unsigned VReg = <NUM_LIT> ; unsigned i = <NUM_LIT> ; MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } unsigned FrameReg = <STR_LIT> ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MF . getFrameInfo ( ) -> getStackSize ( ) + SPAdj ; if ( AFI -> isGPRCalleeSavedArea1Frame ( FrameIndex ) ) Offset -= AFI -> getGPRCalleeSavedArea1Offset ( ) ; else if ( AFI -> isGPRCalleeSavedArea2Frame ( FrameIndex ) ) Offset -= AFI -> getGPRCalleeSavedArea2Offset ( ) ; else if ( MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ) { assert ( SPAdj == <NUM_LIT> && hasFP ( MF ) && <STR_LIT> ) ; if ( ! hasBasePointer ( MF ) ) { FrameReg = getFrameRegister ( MF ) ; Offset -= AFI -> getFramePtrSpillOffset ( ) ; } else FrameReg = BasePtr ; } if ( MI . isDebugValue ( ) ) { MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } assert ( AFI -> isThumbFunction ( ) && <STR_LIT> ) ; if ( rewriteFrameIndex ( MI , i , FrameReg , Offset , TII ) ) return ; assert ( Offset && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; const TargetInstrDesc & Desc = MI . getDesc ( ) ; int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands ( MI , PIdx ) ; if ( Desc . mayLoad ( ) ) { unsigned TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> ) emitThumbRegPlusImmInReg ( MBB , II , TmpReg , FrameReg , Offset , false , TII , * this , dl ) ; else { emitLoadConstPool ( MBB , II , dl , TmpReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else { emitThumbRegPlusImmediate ( MBB , II , TmpReg , FrameReg , Offset , TII , * this , dl ) ; } MI . setDesc ( TII . get ( <STR_LIT> ) ) ;

MI . getOperand ( i ) . ChangeToRegister ( TmpReg , false , false , true ) ;


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned VARegSaveSize = AFI -> getVarArgsRegSaveSize ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; const unsigned * CSRegs = getCalleeSavedRegs ( ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( MBB , MBBI , TII , dl , * this , NumBytes ) ; } else { if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) emitThumbRegPlusImmediate ( MBB , MBBI , <STR_LIT> , FramePtr , - NumBytes , TII , * this , dl ) ; else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ; } else { if ( MBBI -> getOpcode ( ) == <STR_LIT> && & MBB . front ( ) != MBBI && prior ( MBBI ) -> getOpcode ( ) == <STR_LIT> ) {

MachineBasicBlock :: iterator PMBBI = prior ( MBBI ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetDarwin ( ) ) { AFI -> addGPRCalleeSavedArea2Frame ( FI ) ; GPRCS2Size += <NUM_LIT> ; } else { AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; } break ; default : AFI -> addDPRCalleeSavedAreaFrame ( FI ) ; DPRCSSize += <NUM_LIT> ; } } if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { ++ MBBI ; if ( MBBI != MBB . end ( ) ) dl = MBBI -> getDebugLoc ( ) ; } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FramePtr ) . addFrameIndex ( FramePtrSpillFI ) . addImm ( <NUM_LIT> ) ; AFI -> setShouldRestoreSPFromFP ( true ) ; } unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI ) + NumBytes ) ; AFI -> setGPRCalleeSavedArea1Offset ( GPRCS1Offset ) ; AFI -> setGPRCalleeSavedArea2Offset ( GPRCS2Offset ) ; AFI -> setDPRCalleeSavedAreaOffset ( DPRCSOffset ) ; NumBytes = DPRCSOffset ; if ( NumBytes ) { emitSPUpdate ( MBB , MBBI , TII , dl , * this , - NumBytes ) ; } if ( STI . isTargetELF ( ) && hasFP ( MF ) ) MFI -> setOffsetAdjustment ( MFI -> getOffsetAdjustment ( ) - AFI -> getFramePtrSpillOffset ( ) ) ; AFI -> setGPRCalleeSavedArea1Size ( GPRCS1Size ) ; AFI -> setGPRCalleeSavedArea2Size ( GPRCS2Size ) ; AFI -> setDPRCalleeSavedAreaSize ( DPRCSSize ) ;

if ( hasBasePointer ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , BasePtr ) . addReg ( <STR_LIT> ) ;


<s> DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; NumBytes = ( NumBytes + <NUM_LIT> ) & ~ <NUM_LIT> ; MFI -> setStackSize ( NumBytes ) ; unsigned GPRCS1Size = <NUM_LIT> , GPRCS2Size = <NUM_LIT> , DPRCSSize = <NUM_LIT> ; int FramePtrSpillFI = <NUM_LIT> ; if ( VARegSaveSize ) emitSPUpdate ( MBB , MBBI , TII , dl , * this , - VARegSaveSize ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( MBB , MBBI , TII , dl , * this , - NumBytes ) ; return ; } for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; int FI = CSI [ i ] . getFrameIdx ( ) ; switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetDarwin ( ) ) { AFI -> addGPRCalleeSavedArea2Frame ( FI ) ; GPRCS2Size += <NUM_LIT> ; } else { AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; } break ; default : AFI -> addDPRCalleeSavedAreaFrame ( FI ) ; DPRCSSize += <NUM_LIT> ; } } if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { ++ MBBI ; if ( MBBI != MBB . end ( ) ) dl = MBBI -> getDebugLoc ( ) ; } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FramePtr ) . addFrameIndex ( FramePtrSpillFI ) . addImm ( <NUM_LIT> ) ; AFI -> setShouldRestoreSPFromFP ( true ) ; } unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ;

AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI ) + NumBytes ) ;


<s> if ( CFSize >= ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> / <NUM_LIT> ) return false ; return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ;


<s> unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> / <NUM_LIT> ) return false ;

return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ;


<s> DebugLoc dl = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB ( * MBB . getParent ( ) , & MI ) ; unsigned FrameReg = <STR_LIT> ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MF . getFrameInfo ( ) -> getStackSize ( ) + SPAdj ; if ( MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ) { assert ( SPAdj == <NUM_LIT> && STI . getFrameLowering ( ) -> hasFP ( MF ) && <STR_LIT> ) ; if ( ! hasBasePointer ( MF ) ) { FrameReg = getFrameRegister ( MF ) ; Offset -= AFI -> getFramePtrSpillOffset ( ) ; } else FrameReg = BasePtr ; } if ( RS && FrameReg == <STR_LIT> && RS -> isScavengingFrameIndex ( FrameIndex ) ) { assert ( STI . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) && <STR_LIT> <STR_LIT> ) ; assert ( ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) && <STR_LIT> <STR_LIT> ) ; } if ( MI . isDebugValue ( ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } assert ( AFI -> isThumbFunction ( ) && <STR_LIT> ) ; if ( rewriteFrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( Offset && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands ( MI , PIdx ) ; if ( MI . mayLoad ( ) ) {

unsigned TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> void Thumb1RegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg , unsigned MIFlags ) const { assert ( ( is<ISA_LIT>LowRegister ( DestReg ) || isVirtualRegister ( DestReg ) ) && <STR_LIT> ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ;

unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ;


<s> ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } bool Done = rewriteFrameIndex ( MI , i , BaseReg , Off , TII ) ; assert ( Done && <STR_LIT> ) ;


<s> const <ISA_LIT>BaseInstrInfo & TII = * STI . getInstrInfo ( ) ; int Off = Offset ; unsigned i = <NUM_LIT> ;

while ( ! MI . getOperand ( i ) . isFI ( ) ) {


<s> switch ( Opcode ) { case <STR_LIT> : return <STR_LIT> ;


<s> MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ;


<s> unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ;


<s> int Chunk = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; int ThisVal = ( Imm > Chunk ) ? Chunk : Imm ; Imm -= ThisVal ; AddDefaultPred ( AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) ) . addImm ( ThisVal ) ) ;

if ( Imm > <NUM_LIT> ) emitThumbRegPlusImmediate ( MBB , MBBI , dl , DestReg , DestReg , Imm , TII , MRI ) ;


<s> Opc = isSub ? <STR_LIT> : <STR_LIT> ; assert ( isMul4 && <STR_LIT> ) ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; } else { Opc = isSub ? <STR_LIT> : <STR_LIT> ; NumBits = <NUM_LIT> ; NeedCC = true ; } isTwoAddr = true ; } unsigned NumMIs = calcNumMI ( Opc , ExtraOpc , Bytes , NumBits , Scale ) ; unsigned Threshold = ( DestReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( NumMIs > Threshold ) { emitThumbRegPlusImmInReg ( MBB , MBBI , dl , DestReg , BaseReg , NumBytes , true , TII , MRI , MIFlags ) ; return ; } if ( DstNotEqBase ) { if ( is<ISA_LIT>LowRegister ( DestReg ) && is<ISA_LIT>LowRegister ( BaseReg ) ) { unsigned Chunk = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; unsigned ThisVal = ( Bytes > Chunk ) ? Chunk : Bytes ; Bytes -= ThisVal ; const MCInstrDesc & MCID = TII . get ( isSub ? <STR_LIT> : <STR_LIT> ) ; const MachineInstrBuilder MIB = AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , MCID , DestReg ) . setMIFlags ( MIFlags ) ) ; AddDefaultPred ( MIB . addReg ( BaseReg , RegState :: Kill ) . addImm ( ThisVal ) ) ; } else { AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) ) . setMIFlags ( MIFlags ) ; } BaseReg = DestReg ; } unsigned Chunk = ( ( <NUM_LIT> << NumBits ) - <NUM_LIT> ) * Scale ; while ( Bytes ) { unsigned ThisVal = ( Bytes > Chunk ) ? Chunk : Bytes ; Bytes -= ThisVal ; ThisVal /= Scale ; if ( isTwoAddr ) { MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ; if ( NeedCC ) MIB = AddDefaultT1CC ( MIB ) ; MIB . addReg ( DestReg ) . addImm ( ThisVal ) ; MIB = AddDefaultPred ( MIB ) ; MIB . setMIFlags ( MIFlags ) ; } else { bool isKill = BaseReg != <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ; if ( NeedCC ) MIB = AddDefaultT1CC ( MIB ) ;

MIB . addReg ( BaseReg , getKillRegState ( isKill ) ) . addImm ( ThisVal ) ;


<s> if ( DestReg == <STR_LIT> ) { assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; LdReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; } if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> ) AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addReg ( LdReg , RegState :: Kill ) . setMIFlags ( MIFlags ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , dl , LdReg , <NUM_LIT> , NumBytes , <STR_LIT> , <NUM_LIT> , MIFlags ) ; int Opc = ( isSub ) ? <STR_LIT> : ( isHigh ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ;

if ( Opc != <STR_LIT> ) MIB = AddDefaultT1CC ( MIB ) ;


<s> static void removeOperands ( MachineInstr & MI , unsigned i ) { unsigned Op = i ; for ( unsigned e = MI . getNumOperands ( ) ; i != e ; ++ i ) MI . RemoveOperand ( Op ) ;


for ( unsigned e = MI . getNumOperands ( ) ; i != e ; ++ i ) MI . RemoveOperand ( Op ) ;


<s> MachineInstr & MI = * I ; int Off = Offset ; unsigned i = <NUM_LIT> ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } bool Done = rewriteFrameIndex ( MI , i , BaseReg , Off , TII ) ;


<s> NumBits = <NUM_LIT> ; } else { NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; assert ( ( Offset & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; } unsigned PredReg ; if ( Offset == <NUM_LIT> && getInstrPredicate ( & MI , PredReg ) == <STR_LIT> ) { MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . RemoveOperand ( FrameRegIdx + <NUM_LIT> ) ; return true ; } unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( ( Offset / Scale ) & ~ Mask ) == <NUM_LIT> ) { if ( Opcode == <STR_LIT> ) { MI . setDesc ( TII . get ( Opcode ) ) ; removeOperands ( MI , FrameRegIdx ) ; AddDefaultPred ( AddDefaultT1CC ( MIB ) . addReg ( FrameReg ) . addImm ( Offset / Scale ) ) ; } else { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( Offset / Scale ) ; } return true ; } unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Bytes = ( Offset > <NUM_LIT> ) ? Offset : - Offset ; unsigned NumMIs = calcNumMI ( Opcode , <NUM_LIT> , Bytes , NumBits , Scale ) ; if ( NumMIs > <NUM_LIT> ) { emitThumbRegPlusImmediate ( MBB , II , dl , DestReg , FrameReg , Offset , TII , * this ) ; MBB . erase ( II ) ; return true ; } if ( Offset > <NUM_LIT> ) { if ( Opcode == <STR_LIT> ) { MI . setDesc ( TII . get ( Opcode ) ) ; removeOperands ( MI , FrameRegIdx ) ; AddDefaultPred ( AddDefaultT1CC ( MIB ) . addReg ( FrameReg ) . addImm ( Mask ) ) ; } else { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( Mask ) ; } Offset = ( Offset - Mask * Scale ) ; MachineBasicBlock :: iterator NII = llvm :: next ( II ) ;

emitThumbRegPlusImmediate ( MBB , NII , dl , DestReg , DestReg , Offset , TII , * this ) ;


<s> unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MI . getDesc ( ) ; unsigned AddrMode = ( Desc . TSFlags & <STR_LIT> ) ; if ( Opcode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; if ( FrameReg != <STR_LIT> ) { Opcode = <STR_LIT> ; NumBits = <NUM_LIT> ; } else { NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; assert ( ( Offset & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; } unsigned PredReg ; if ( Offset == <NUM_LIT> && getInstrPredicate ( & MI , PredReg ) == <STR_LIT> ) { MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . RemoveOperand ( FrameRegIdx + <NUM_LIT> ) ; return true ; } unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( ( Offset / Scale ) & ~ Mask ) == <NUM_LIT> ) { if ( Opcode == <STR_LIT> ) { MI . setDesc ( TII . get ( Opcode ) ) ; removeOperands ( MI , FrameRegIdx ) ; AddDefaultPred ( AddDefaultT1CC ( MIB ) . addReg ( FrameReg ) . addImm ( Offset / Scale ) ) ; } else { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( Offset / Scale ) ; } return true ; } unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Bytes = ( Offset > <NUM_LIT> ) ? Offset : - Offset ; unsigned NumMIs = calcNumMI ( Opcode , <NUM_LIT> , Bytes , NumBits , Scale ) ; if ( NumMIs > <NUM_LIT> ) { emitThumbRegPlusImmediate ( MBB , II , dl , DestReg , FrameReg , Offset , TII , * this ) ; MBB . erase ( II ) ; return true ; } if ( Offset > <NUM_LIT> ) {


<s> const MachineOperand & MO = II -> getOperand ( i ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { UseMI = II ; done = true ; break ; } if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) { UseMI = II ; done = true ; break ; } } }

AddDefaultPred ( BuildMI ( MBB , UseMI , DL , TII . get ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) ) ;


<s> for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { UseMI = II ; done = true ; break ; } if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) { UseMI = II ; done = true ; break ; } } } AddDefaultPred ( BuildMI ( MBB , UseMI , DL , TII . get ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) ) ;


<s> Thumb1RegisterInfo :: Thumb1RegisterInfo ( const <ISA_LIT>BaseInstrInfo & tii , const <ISA_LIT>Subtarget & sti ) : <ISA_LIT>BaseRegisterInfo ( tii , sti ) {


<s> unsigned Opcode = MI -> getOpcode ( ) ; if ( ITBlockSize ) { -- ITBlockSize ; } else if ( Opcode == <STR_LIT> ) { unsigned Mask = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned NumTZ = CountTrailingZeros_32 ( Mask ) ; assert ( NumTZ <= <NUM_LIT> && <STR_LIT> ) ; ITBlockSize = <NUM_LIT> - NumTZ ; MachineBasicBlock :: iterator I = MI ; for ( unsigned i = <NUM_LIT> ; i < ITBlockSize ; ++ i ) {


<s> unsigned Mask = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned NumTZ = CountTrailingZeros_32 ( Mask ) ; assert ( NumTZ <= <NUM_LIT> && <STR_LIT> ) ; ITBlockSize = <NUM_LIT> - NumTZ ; MachineBasicBlock :: iterator I = MI ; for ( unsigned i = <NUM_LIT> ; i < ITBlockSize ; ++ i ) { do { ++ I ; } while ( I -> isDebugValue ( ) ) ; ITBlockMIs [ ITBlockSize - <NUM_LIT> - i ] = & * I ; } }

PostRAHazardRecognizer :: EmitInstruction ( SU ) ;


<s> PostRAHazardRecognizer ( ItinData ) {


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps ( <STR_LIT> ) ) ;


<s> void Thumb2InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { if ( ! <STR_LIT> . contains ( DestReg , SrcReg ) ) return <ISA_LIT>BaseInstrInfo :: copyPhysReg ( MBB , I , DL , DestReg , SrcReg , KillSrc ) ;

BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps ( <STR_LIT> ) ) ;


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addImm ( NumBytes ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ; Fits = true ; } else if ( ( NumBytes & <NUM_LIT> ) == <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg ) . addImm ( NumBytes >> <NUM_LIT> ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ; Fits = true ; } if ( Fits ) { if ( isSub ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . addReg ( DestReg , RegState :: Kill ) . add ( predOps ( Pred , PredReg ) ) . add ( condCodeOp ( ) ) . setMIFlags ( MIFlags ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . addReg ( DestReg , RegState :: Kill ) . add ( predOps ( Pred , PredReg ) ) . add ( condCodeOp ( ) ) . setMIFlags ( MIFlags ) ; } return ; } } while ( NumBytes ) { unsigned ThisVal = NumBytes ; unsigned Opc = <NUM_LIT> ; if ( DestReg == <STR_LIT> && BaseReg != <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . setMIFlags ( MIFlags ) . add ( predOps ( <STR_LIT> ) ) ; BaseReg = <STR_LIT> ; continue ; } bool HasCCOut = true ; if ( BaseReg == <STR_LIT> ) { if ( DestReg == <STR_LIT> && ( ThisVal < ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ) { assert ( ( ThisVal & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg ) . addImm ( ThisVal / <NUM_LIT> ) . setMIFlags ( MIFlags ) . add ( predOps ( <STR_LIT> ) ) ; NumBytes = <NUM_LIT> ; continue ; } Opc = isSub ? <STR_LIT> : <STR_LIT> ;

if ( <STR_LIT> ( NumBytes ) != - <NUM_LIT> ) {


<s> MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; if ( MF . getTarget ( ) . isPositionIndependent ( ) ) expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ;

else expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ;


<s> MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ;

if ( MF . getTarget ( ) . isPositionIndependent ( ) ) expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ;


<s> if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) return <STR_LIT> ; return getInstrPredicate ( MI , PredReg ) ;


<s> NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ;

NopInst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ;


<s> NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ;


<s> if ( MBBI == MBB . end ( ) ) return false ; }


<s> while ( MBBI -> isDebugInstr ( ) ) { ++ MBBI ; if ( MBBI == MBB . end ( ) ) return false ; }


<s> MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; }

<ISA_LIT>BaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ;


<s> void Thumb2InstrInfo :: ReplaceTailWithBranchTo ( MachineBasicBlock :: iterator Tail , MachineBasicBlock * NewDest ) const { MachineBasicBlock * MBB = Tail -> getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! AFI -> hasITBlocks ( ) || Tail -> isBranch ( ) ) { TargetInstrInfo :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; return ; } unsigned PredReg = <NUM_LIT> ; <STR_LIT> CC = getInstrPredicate ( * Tail , PredReg ) ; MachineBasicBlock :: iterator MBBI = Tail ; if ( CC != <STR_LIT> ) -- MBBI ; TargetInstrInfo :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; if ( CC != <STR_LIT> ) { MachineBasicBlock :: iterator E = MBB -> begin ( ) ; unsigned Count = <NUM_LIT> ; while ( Count && MBBI != E ) { if ( MBBI -> isDebugInstr ( ) ) { -- MBBI ; continue ; } if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { unsigned Mask = MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Count == <NUM_LIT> ) MBBI -> eraseFromParent ( ) ; else {


<s> } unsigned PredReg = <NUM_LIT> ; <STR_LIT> CC = getInstrPredicate ( * Tail , PredReg ) ; MachineBasicBlock :: iterator MBBI = Tail ; if ( CC != <STR_LIT> ) -- MBBI ; TargetInstrInfo :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; if ( CC != <STR_LIT> ) { MachineBasicBlock :: iterator E = MBB -> begin ( ) ; unsigned Count = <NUM_LIT> ; while ( Count && MBBI != E ) { if ( MBBI -> isDebugInstr ( ) ) {


<s> unsigned Scale = <NUM_LIT> ; if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) ; if ( Offset < <NUM_LIT> ) { NewOpc = negativeOffsetOpcode ( Opcode ) ; NumBits = <NUM_LIT> ; isSub = true ; Offset = - Offset ; } else { NewOpc = positiveOffsetOpcode ( Opcode ) ; NumBits = <NUM_LIT> ; } } else if ( AddrMode == <STR_LIT> ) { const MachineOperand & OffOp = MI . getOperand ( FrameRegIdx + <NUM_LIT> ) ; int InstrOffs = <STR_LIT> ( OffOp . getImm ( ) ) ; if ( <STR_LIT> ( OffOp . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; Offset += InstrOffs * <NUM_LIT> ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( Offset < <NUM_LIT> ) { Offset = - Offset ; isSub = true ; } } else if ( AddrMode == <STR_LIT> ) { const MachineOperand & OffOp = MI . getOperand ( FrameRegIdx + <NUM_LIT> ) ; int InstrOffs = <STR_LIT> ( OffOp . getImm ( ) ) ; if ( <STR_LIT> ( OffOp . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; Offset += InstrOffs * <NUM_LIT> ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( Offset < <NUM_LIT> ) { Offset = - Offset ; isSub = true ; } } else if ( AddrMode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; assert ( ( Offset & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; } else if ( AddrMode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; assert ( ( Offset & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( NewOpc != Opcode ) MI . setDesc ( TII . get ( NewOpc ) ) ; MachineOperand & ImmOp = MI . getOperand ( FrameRegIdx + <NUM_LIT> ) ; int ImmedOffset = Offset / Scale ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( unsigned ) Offset <= Mask * Scale ) {

MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ;


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( SrcReg , & <STR_LIT> ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; return ; }

<ISA_LIT>BaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC , TRI ) ;


<s> Thumb2InstrInfo :: Thumb2InstrInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>BaseInstrInfo ( STI ) {


<s> if ( ! <STR_LIT> . contains ( DestReg , SrcReg ) ) return <ISA_LIT>BaseInstrInfo :: copyPhysReg ( MBB , I , DL , DestReg , SrcReg , KillSrc ) ;

AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ) ;


<s> Opc = isSub ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg ) . addImm ( ThisVal / <NUM_LIT> ) . setMIFlags ( MIFlags ) ) ; NumBytes = <NUM_LIT> ; continue ; } Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( NumBytes ) != - <NUM_LIT> ) { NumBytes = <NUM_LIT> ; } else { unsigned RotAmt = countLeadingZeros ( ThisVal ) ; ThisVal = ThisVal & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; NumBytes &= ~ ThisVal ; assert ( <STR_LIT> ( ThisVal ) != - <NUM_LIT> && <STR_LIT> ) ; } } else { assert ( DestReg != <STR_LIT> && BaseReg != <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( NumBytes ) != - <NUM_LIT> ) { NumBytes = <NUM_LIT> ; } else if ( ThisVal < <NUM_LIT> ) { Opc = isSub ? <STR_LIT> : <STR_LIT> ; HasCCOut = false ; NumBytes = <NUM_LIT> ; } else { unsigned RotAmt = countLeadingZeros ( ThisVal ) ; ThisVal = ThisVal & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; NumBytes &= ~ ThisVal ; assert ( <STR_LIT> ( ThisVal ) != - <NUM_LIT> && <STR_LIT> ) ; } }

MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ThisVal ) ) . setMIFlags ( MIFlags ) ;


<s> void Thumb2InstrInfo :: expandLoadStackGuard ( MachineBasicBlock :: iterator MI , Reloc :: Model RM ) const { if ( RM == Reloc :: PIC_ ) expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> , RM ) ;

else expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> , RM ) ;


<s> if ( RM == Reloc :: PIC_ ) expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> , RM ) ; else expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> , RM ) ;


<s> <STR_LIT> llvm :: getITInstrPredicate ( const MachineInstr * MI , unsigned & PredReg ) { unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) return <STR_LIT> ;

return getInstrPredicate ( MI , PredReg ) ;


<s> if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) return <STR_LIT> ;


NopInst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ;


<s> unsigned Thumb2InstrInfo :: getUnindexedOpcode ( unsigned Opc ) const {


<s> if ( MBBI == MBB . end ( ) ) return false ; } unsigned PredReg = <NUM_LIT> ; return getITInstrPredicate ( MBBI , PredReg ) == <STR_LIT> ;


<s> AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; AddDefaultPred ( MIB ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; }


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & <STR_LIT> ) ;

MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ;


<s> switch ( opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> return ; } unsigned PredReg = <NUM_LIT> ; <STR_LIT> CC = getInstrPredicate ( Tail , PredReg ) ; MachineBasicBlock :: iterator MBBI = Tail ; if ( CC != <STR_LIT> ) -- MBBI ; TargetInstrInfo :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; if ( CC != <STR_LIT> ) { MachineBasicBlock :: iterator E = MBB -> begin ( ) ; unsigned Count = <NUM_LIT> ; while ( Count && MBBI != E ) {


<s> unsigned NewOpc = Opcode ; if ( AddrMode == <STR_LIT> ) { unsigned OffsetReg = MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getReg ( ) ; if ( OffsetReg != <NUM_LIT> ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; return Offset == <NUM_LIT> ; } MI . RemoveOperand ( FrameRegIdx + <NUM_LIT> ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; NewOpc = immediateOffsetOpcode ( Opcode ) ; AddrMode = <STR_LIT> ; } unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) ; if ( Offset < <NUM_LIT> ) { NewOpc = negativeOffsetOpcode ( Opcode ) ; NumBits = <NUM_LIT> ; isSub = true ; Offset = - Offset ; } else { NewOpc = positiveOffsetOpcode ( Opcode ) ; NumBits = <NUM_LIT> ; } } else if ( AddrMode == <STR_LIT> ) { const MachineOperand & OffOp = MI . getOperand ( FrameRegIdx + <NUM_LIT> ) ; int InstrOffs = <STR_LIT> ( OffOp . getImm ( ) ) ; if ( <STR_LIT> ( OffOp . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; Offset += InstrOffs * <NUM_LIT> ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( Offset < <NUM_LIT> ) { Offset = - Offset ; isSub = true ; } } else if ( AddrMode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; assert ( ( Offset & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( NewOpc != Opcode ) MI . setDesc ( TII . get ( NewOpc ) ) ; MachineOperand & ImmOp = MI . getOperand ( FrameRegIdx + <NUM_LIT> ) ; int ImmedOffset = Offset / Scale ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( unsigned ) Offset <= Mask * Scale ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; if ( isSub ) { if ( AddrMode == <STR_LIT> ) ImmedOffset |= <NUM_LIT> << NumBits ; else ImmedOffset = - ImmedOffset ; } ImmOp . ChangeToImmediate ( ImmedOffset ) ; Offset = <NUM_LIT> ; return true ; } ImmedOffset = ImmedOffset & Mask ; if ( isSub ) { if ( AddrMode == <STR_LIT> ) ImmedOffset |= <NUM_LIT> << NumBits ; else { ImmedOffset = - ImmedOffset ; if ( ImmedOffset == <NUM_LIT> ) MI . setDesc ( TII . get ( positiveOffsetOpcode ( NewOpc ) ) ) ; } } ImmOp . ChangeToImmediate ( ImmedOffset ) ; Offset &= ~ ( Mask * Scale ) ; }

Offset = ( isSub ) ? - Offset : Offset ;


<s> if ( Opcode == <STR_LIT> ) AddrMode = <STR_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) ; unsigned PredReg ; if ( Offset == <NUM_LIT> && getInstrPredicate ( & MI , PredReg ) == <STR_LIT> ) { MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; do MI . RemoveOperand ( FrameRegIdx + <NUM_LIT> ) ; while ( MI . getNumOperands ( ) > FrameRegIdx + <NUM_LIT> ) ; MachineInstrBuilder MIB ( * MI . getParent ( ) -> getParent ( ) , & MI ) ; AddDefaultPred ( MIB ) ; return true ; } bool HasCCOut = Opcode != <STR_LIT> ; if ( Offset < <NUM_LIT> ) { Offset = - Offset ; isSub = true ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; } else { MI . setDesc ( TII . get ( <STR_LIT> ) ) ; } if ( <STR_LIT> ( Offset ) != - <NUM_LIT> ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; if ( ! HasCCOut ) MI . addOperand ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; Offset = <NUM_LIT> ; return true ; } if ( Offset < <NUM_LIT> && ( ! HasCCOut || MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <NUM_LIT> ) ) { unsigned NewOpc = isSub ? <STR_LIT> : <STR_LIT> ; MI . setDesc ( TII . get ( NewOpc ) ) ; MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; if ( HasCCOut ) MI . RemoveOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) ; Offset = <NUM_LIT> ; return true ; } unsigned RotAmt = countLeadingZeros < unsigned > ( Offset ) ; unsigned ThisImmVal = Offset & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; Offset &= ~ ThisImmVal ; assert ( <STR_LIT> ( ThisImmVal ) != - <NUM_LIT> && <STR_LIT> ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( ThisImmVal ) ;


<s> } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( SrcReg , & <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; AddDefaultPred ( MIB ) ; return ; } <ISA_LIT>BaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC , TRI ) ;


<s> Thumb2InstrInfo :: Thumb2InstrInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>BaseInstrInfo ( STI ) , RI ( ) {


<s> int PIdx = findFirstVPTPredOperandIdx ( MI ) ; if ( PIdx == - <NUM_LIT> ) { PredReg = <NUM_LIT> ; return <STR_LIT> ;


<s> PredReg = MI . getOperand ( PIdx + <NUM_LIT> ) . getReg ( ) ;

return ( <STR_LIT> ) MI . getOperand ( PIdx ) . getImm ( ) ;


<s> switch ( opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Register :: isVirtualRegister ( DestReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & <STR_LIT> ) ;


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Register :: isVirtualRegister ( DestReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & <STR_LIT> ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ;

MIB . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ;


<s> static unsigned negativeOffsetOpcode ( unsigned opcode ) { switch ( opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Register :: isVirtualRegister ( SrcReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( SrcReg , & <STR_LIT> ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ;

AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ;


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } return ; } } while ( NumBytes ) { unsigned ThisVal = NumBytes ; unsigned Opc = <NUM_LIT> ; if ( DestReg == <STR_LIT> && BaseReg != <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . setMIFlags ( MIFlags ) ) ; BaseReg = <STR_LIT> ; continue ; } bool HasCCOut = true ; if ( BaseReg == <STR_LIT> ) { if ( DestReg == <STR_LIT> && ( ThisVal < ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ) { assert ( ( ThisVal & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg ) . addImm ( ThisVal / <NUM_LIT> ) . setMIFlags ( MIFlags ) ) ; NumBytes = <NUM_LIT> ; continue ; } Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( NumBytes ) != - <NUM_LIT> ) { NumBytes = <NUM_LIT> ; } else { unsigned RotAmt = countLeadingZeros ( ThisVal ) ; ThisVal = ThisVal & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; NumBytes &= ~ ThisVal ; assert ( <STR_LIT> ( ThisVal ) != - <NUM_LIT> && <STR_LIT> ) ; } } else { assert ( DestReg != <STR_LIT> && BaseReg != <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( NumBytes ) != - <NUM_LIT> ) { NumBytes = <NUM_LIT> ; } else if ( ThisVal < <NUM_LIT> ) { Opc = isSub ? <STR_LIT> : <STR_LIT> ; HasCCOut = false ;


<s> void Thumb2InstrInfo :: getNoopForMachoTarget ( MCInst & NopInst ) const {


<s> NopInst . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ;


<s> inline <STR_LIT> getVPTInstrPredicate ( const MachineInstr & MI ) {


<s> inline <STR_LIT> getVPTInstrPredicate ( const MachineInstr & MI ) { Register PredReg ; return getVPTInstrPredicate ( MI , PredReg ) ;


<s> MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; AddDefaultPred ( MIB ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ;


<s> switch ( opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( SrcReg , & <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ;

AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ;


<s> Thumb2InstrInfo :: Thumb2InstrInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>BaseInstrInfo ( STI ) , RI ( STI ) {


<s> } const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isGVInGOT ( GV ) ) expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ;

else if ( MF . getTarget ( ) . isPositionIndependent ( ) ) expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ;


<s> const Thumb2RegisterInfo & getRegisterInfo ( ) const {


<s> while ( MBBI -> isDebugValue ( ) ) { ++ MBBI ; if ( MBBI == MBB . end ( ) ) return false ; } unsigned PredReg = <NUM_LIT> ;

return getITInstrPredicate ( * MBBI , PredReg ) == <STR_LIT> ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & <STR_LIT> ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ;


<s> if ( CC != <STR_LIT> ) { MachineBasicBlock :: iterator E = MBB -> begin ( ) ; unsigned Count = <NUM_LIT> ; while ( Count && MBBI != E ) { if ( MBBI -> isDebugValue ( ) ) { -- MBBI ; continue ; } if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { unsigned Mask = MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Count == <NUM_LIT> ) MBBI -> eraseFromParent ( ) ; else { unsigned MaskOn = <NUM_LIT> << Count ; unsigned MaskOff = ~ ( MaskOn - <NUM_LIT> ) ; MBBI -> getOperand ( <NUM_LIT> ) . setImm ( ( Mask & MaskOff ) | MaskOn ) ; } return ; } -- MBBI ; -- Count ;


<s> while ( Count && MBBI != E ) { if ( MBBI -> isDebugValue ( ) ) { -- MBBI ; continue ; } if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { unsigned Mask = MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Count == <NUM_LIT> ) MBBI -> eraseFromParent ( ) ; else { unsigned MaskOn = <NUM_LIT> << Count ; unsigned MaskOff = ~ ( MaskOn - <NUM_LIT> ) ; MBBI -> getOperand ( <NUM_LIT> ) . setImm ( ( Mask & MaskOff ) | MaskOn ) ; } return ;


<s> } MI . RemoveOperand ( FrameRegIdx + <NUM_LIT> ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; NewOpc = immediateOffsetOpcode ( Opcode ) ; AddrMode = <STR_LIT> ; } unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) ; if ( Offset < <NUM_LIT> ) { NewOpc = negativeOffsetOpcode ( Opcode ) ; NumBits = <NUM_LIT> ; isSub = true ; Offset = - Offset ; } else { NewOpc = positiveOffsetOpcode ( Opcode ) ; NumBits = <NUM_LIT> ; } } else if ( AddrMode == <STR_LIT> ) { const MachineOperand & OffOp = MI . getOperand ( FrameRegIdx + <NUM_LIT> ) ; int InstrOffs = <STR_LIT> ( OffOp . getImm ( ) ) ; if ( <STR_LIT> ( OffOp . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; Offset += InstrOffs * <NUM_LIT> ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( Offset < <NUM_LIT> ) { Offset = - Offset ; isSub = true ; } } else if ( AddrMode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; assert ( ( Offset & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( NewOpc != Opcode ) MI . setDesc ( TII . get ( NewOpc ) ) ; MachineOperand & ImmOp = MI . getOperand ( FrameRegIdx + <NUM_LIT> ) ; int ImmedOffset = Offset / Scale ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( unsigned ) Offset <= Mask * Scale ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; if ( isSub ) {

if ( AddrMode == <STR_LIT> ) ImmedOffset |= <NUM_LIT> << NumBits ;


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( SrcReg , & <STR_LIT> ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; return ; }


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( SrcReg , & <STR_LIT> ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; return ;


<s> bool tDest = <STR_LIT> . contains ( DestReg ) ; bool tSrc = <STR_LIT> . contains ( SrcReg ) ; unsigned Opc = <STR_LIT> ; if ( tDest && tSrc ) Opc = <STR_LIT> ; else if ( tSrc ) Opc = <STR_LIT> ; else if ( tDest ) Opc = <STR_LIT> ;

BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> ScheduleHazardRecognizer * Thumb2InstrInfo :: CreateTargetPostRAHazardRecognizer ( const InstrItineraryData & II ) const { return ( ScheduleHazardRecognizer * ) new Thumb2HazardRecognizer ( II ) ;


<s> CreateTargetPostRAHazardRecognizer ( const InstrItineraryData & II ) const { return ( ScheduleHazardRecognizer * ) new Thumb2HazardRecognizer ( II ) ;


<s> <STR_LIT> llvm :: getITInstrPredicate ( const MachineInstr * MI , unsigned & PredReg ) { unsigned Opc = MI -> getOpcode ( ) ;

if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) return <STR_LIT> ;


<s> if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) return <STR_LIT> ;

return llvm :: getInstrPredicate ( MI , PredReg ) ;


<s> return llvm :: getITInstrPredicate ( MBBI , PredReg ) == <STR_LIT> ;


<s> return NumT && NumF && NumT <= ( IfCvtDiamondLimit ) && NumF <= ( IfCvtDiamondLimit ) ;


<s> loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { if ( RC == <STR_LIT> || RC == <STR_LIT> || RC == <STR_LIT> || RC == <STR_LIT> ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ;

MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ;


<s> return ; } unsigned PredReg = <NUM_LIT> ; <STR_LIT> CC = llvm :: getInstrPredicate ( Tail , PredReg ) ; MachineBasicBlock :: iterator MBBI = Tail ; if ( CC != <STR_LIT> ) -- MBBI ; TargetInstrInfoImpl :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; if ( CC != <STR_LIT> ) { MachineBasicBlock :: iterator E = MBB -> begin ( ) ; unsigned Count = <NUM_LIT> ; while ( Count && MBBI != E ) { if ( MBBI -> isDebugValue ( ) ) { -- MBBI ; continue ; } if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { unsigned Mask = MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Count == <NUM_LIT> ) MBBI -> eraseFromParent ( ) ;


<s> MachineBasicBlock * MBB = Tail -> getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! AFI -> hasITBlocks ( ) ) { TargetInstrInfoImpl :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; return ; } unsigned PredReg = <NUM_LIT> ; <STR_LIT> CC = llvm :: getInstrPredicate ( Tail , PredReg ) ; MachineBasicBlock :: iterator MBBI = Tail ; if ( CC != <STR_LIT> ) -- MBBI ; TargetInstrInfoImpl :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; if ( CC != <STR_LIT> ) { MachineBasicBlock :: iterator E = MBB -> begin ( ) ; unsigned Count = <NUM_LIT> ; while ( Count && MBBI != E ) { if ( MBBI -> isDebugValue ( ) ) { -- MBBI ; continue ; } if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { unsigned Mask = MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Count == <NUM_LIT> ) MBBI -> eraseFromParent ( ) ; else { unsigned MaskOn = <NUM_LIT> << Count ; unsigned MaskOff = ~ ( MaskOn - <NUM_LIT> ) ; MBBI -> getOperand ( <NUM_LIT> ) . setImm ( ( Mask & MaskOff ) | MaskOn ) ; } return ; } -- MBBI ; -- Count ;


<s> bool isSP = FrameReg == <STR_LIT> ; bool HasCCOut = Opcode != <STR_LIT> ; if ( Offset < <NUM_LIT> ) { Offset = - Offset ; isSub = true ; MI . setDesc ( TII . get ( isSP ? <STR_LIT> : <STR_LIT> ) ) ; } else { MI . setDesc ( TII . get ( isSP ? <STR_LIT> : <STR_LIT> ) ) ; } if ( <STR_LIT> ( Offset ) != - <NUM_LIT> ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; if ( ! HasCCOut ) MI . addOperand ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; Offset = <NUM_LIT> ; return true ; } if ( Offset < <NUM_LIT> && ( ! HasCCOut || MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <NUM_LIT> ) ) { unsigned NewOpc = isSP ? ( isSub ? <STR_LIT> : <STR_LIT> ) : ( isSub ? <STR_LIT> : <STR_LIT> ) ; MI . setDesc ( TII . get ( NewOpc ) ) ; MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; if ( HasCCOut ) MI . RemoveOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) ; Offset = <NUM_LIT> ; return true ; } unsigned RotAmt = CountLeadingZeros_32 ( Offset ) ; unsigned ThisImmVal = Offset & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; Offset &= ~ ThisImmVal ; assert ( <STR_LIT> ( ThisImmVal ) != - <NUM_LIT> && <STR_LIT> ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( ThisImmVal ) ; if ( ! HasCCOut ) MI . addOperand ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; } else { if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) return false ; unsigned NewOpc = Opcode ; if ( AddrMode == <STR_LIT> ) { unsigned OffsetReg = MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getReg ( ) ; if ( OffsetReg != <NUM_LIT> ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; return Offset == <NUM_LIT> ; } MI . RemoveOperand ( FrameRegIdx + <NUM_LIT> ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; NewOpc = immediateOffsetOpcode ( Opcode ) ; AddrMode = <STR_LIT> ; } unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) ; if ( Offset < <NUM_LIT> ) { NewOpc = negativeOffsetOpcode ( Opcode ) ; NumBits = <NUM_LIT> ; isSub = true ; Offset = - Offset ; } else { NewOpc = positiveOffsetOpcode ( Opcode ) ; NumBits = <NUM_LIT> ; }


<s> if ( OffsetReg != <NUM_LIT> ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; return Offset == <NUM_LIT> ; } MI . RemoveOperand ( FrameRegIdx + <NUM_LIT> ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; NewOpc = immediateOffsetOpcode ( Opcode ) ; AddrMode = <STR_LIT> ; } unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) ; if ( Offset < <NUM_LIT> ) { NewOpc = negativeOffsetOpcode ( Opcode ) ; NumBits = <NUM_LIT> ; isSub = true ; Offset = - Offset ; } else { NewOpc = positiveOffsetOpcode ( Opcode ) ; NumBits = <NUM_LIT> ; } } else if ( AddrMode == <STR_LIT> ) { const MachineOperand & OffOp = MI . getOperand ( FrameRegIdx + <NUM_LIT> ) ; int InstrOffs = <STR_LIT> ( OffOp . getImm ( ) ) ; if ( <STR_LIT> ( OffOp . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; Offset += InstrOffs * <NUM_LIT> ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( Offset < <NUM_LIT> ) { Offset = - Offset ; isSub = true ; } } else { llvm_unreachable ( <STR_LIT> ) ; } if ( NewOpc != Opcode ) MI . setDesc ( TII . get ( NewOpc ) ) ; MachineOperand & ImmOp = MI . getOperand ( FrameRegIdx + <NUM_LIT> ) ; int ImmedOffset = Offset / Scale ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( unsigned ) Offset <= Mask * Scale ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; if ( isSub ) { if ( AddrMode == <STR_LIT> ) ImmedOffset |= <NUM_LIT> << NumBits ; else ImmedOffset = - ImmedOffset ; } ImmOp . ChangeToImmediate ( ImmedOffset ) ; Offset = <NUM_LIT> ; return true ; } ImmedOffset = ImmedOffset & Mask ; if ( isSub ) { if ( AddrMode == <STR_LIT> ) ImmedOffset |= <NUM_LIT> << NumBits ; else { ImmedOffset = - ImmedOffset ; if ( ImmedOffset == <NUM_LIT> ) MI . setDesc ( TII . get ( positiveOffsetOpcode ( NewOpc ) ) ) ;


<s> MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ;

AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ;


<s> Thumb2InstrInfo :: Thumb2InstrInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>BaseInstrInfo ( STI ) , RI ( * this , STI ) {


<s> if ( isSub ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addReg ( DestReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } return ; } } while ( NumBytes ) { unsigned ThisVal = NumBytes ; unsigned Opc = <NUM_LIT> ; if ( DestReg == <STR_LIT> && BaseReg != <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . setMIFlags ( MIFlags ) ) ; BaseReg = <STR_LIT> ; continue ; } bool HasCCOut = true ; if ( BaseReg == <STR_LIT> ) { if ( DestReg == <STR_LIT> && ( ThisVal < ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ) { assert ( ( ThisVal & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg ) . addImm ( ThisVal / <NUM_LIT> ) . setMIFlags ( MIFlags ) ) ; NumBytes = <NUM_LIT> ; continue ; } Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( NumBytes ) != - <NUM_LIT> ) { NumBytes = <NUM_LIT> ; } else { unsigned RotAmt = countLeadingZeros ( ThisVal ) ; ThisVal = ThisVal & <STR_LIT> ( <NUM_LIT> , RotAmt ) ;


<s> NopInst . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ;


<s> void Thumb2InstrInfo :: getNoopForMachoTarget ( MCInst & NopInst ) const {


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg ) . addImm ( NumBytes >> <NUM_LIT> ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ; Fits = true ; } if ( Fits ) { if ( isSub ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addReg ( DestReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } return ; } } while ( NumBytes ) { unsigned ThisVal = NumBytes ; unsigned Opc = <NUM_LIT> ; if ( DestReg == <STR_LIT> && BaseReg != <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . setMIFlags ( MIFlags ) ) ; BaseReg = <STR_LIT> ; continue ; } bool HasCCOut = true ; if ( BaseReg == <STR_LIT> ) { if ( DestReg == <STR_LIT> && ( ThisVal < ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ) { assert ( ( ThisVal & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg ) . addImm ( ThisVal / <NUM_LIT> ) . setMIFlags ( MIFlags ) ) ; NumBytes = <NUM_LIT> ; continue ; } Opc = isSub ? <STR_LIT> : <STR_LIT> ;

if ( <STR_LIT> ( NumBytes ) != - <NUM_LIT> ) {


<s> if ( RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; return ; }

<ISA_LIT>BaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ;


<s> if ( RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; return ; } <ISA_LIT>BaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ;


<s> while ( Count && MBBI != E ) { if ( MBBI -> isDebugValue ( ) ) { -- MBBI ; continue ; } if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { unsigned Mask = MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Count == <NUM_LIT> ) MBBI -> eraseFromParent ( ) ; else { unsigned MaskOn = <NUM_LIT> << Count ;

unsigned MaskOff = ~ ( MaskOn - <NUM_LIT> ) ;


<s> unsigned Count = <NUM_LIT> ; while ( Count && MBBI != E ) { if ( MBBI -> isDebugValue ( ) ) { -- MBBI ; continue ; } if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { unsigned Mask = MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Count == <NUM_LIT> ) MBBI -> eraseFromParent ( ) ; else { unsigned MaskOn = <NUM_LIT> << Count ; unsigned MaskOff = ~ ( MaskOn - <NUM_LIT> ) ;

MBBI -> getOperand ( <NUM_LIT> ) . setImm ( ( Mask & MaskOff ) | MaskOn ) ;


<s> if ( MBBI -> isDebugValue ( ) ) continue ; MachineInstr * NMI = & * MBBI ; <STR_LIT> NCC = getInstrPredicate ( NMI , PredReg ) ; if ( ! ( NCC == CC || NCC == OCC ) || NMI -> modifiesRegister ( SrcReg , & TRI ) || NMI -> modifiesRegister ( <STR_LIT> , & TRI ) ) break ; if ( ++ NumInsts == <NUM_LIT> ) return ; }


<s> if ( RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ;


<s> storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { if ( RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> ) { DebugLoc DL ;

if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ;


<s> if ( ! <STR_LIT> . contains ( DestReg , SrcReg ) ) return <ISA_LIT>BaseInstrInfo :: copyPhysReg ( MBB , I , DL , DestReg , SrcReg , KillSrc ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ) ;


<s> if ( ! <STR_LIT> . contains ( DestReg , SrcReg ) ) return <ISA_LIT>BaseInstrInfo :: copyPhysReg ( MBB , I , DL , DestReg , SrcReg , KillSrc ) ;

AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ) ;