<s> DebugLoc dl = MI -> getDebugLoc ( ) ; MachineBasicBlock * BB = MI -> getParent ( ) ; MachineInstrBuilder LDM , STM ; if ( isThumb1 || ! MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) { MachineOperand LDWb ( MI -> getOperand ( <NUM_LIT> ) ) ; LDM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ) ) . add ( LDWb ) ; } else { LDM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) ; } if ( isThumb1 || ! MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) { MachineOperand STWb ( MI -> getOperand ( <NUM_LIT> ) ) ; STM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ) ) . add ( STWb ) ; } else { STM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) ; } MachineOperand LDBase ( MI -> getOperand ( <NUM_LIT> ) ) ; LDM . add ( LDBase ) . add ( predOps ( <STR_LIT> ) ) ;

MachineOperand STBase ( MI -> getOperand ( <NUM_LIT> ) ) ;


<s> } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Subtarget . hasV5TEOps ( ) ) { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } } else llvm_unreachable ( <STR_LIT> ) ;


<s> { MO_GOT , <STR_LIT> } , { MO_SBREL , <STR_LIT> } , { MO_DLLIMPORT , <STR_LIT> } , { MO_SECREL , <STR_LIT> } , { MO_NONLAZY , <STR_LIT> } } ;


<s> bool <ISA_LIT>BaseInstrInfo :: isCopyInstr ( const MachineInstr & MI , const MachineOperand * & Src , const MachineOperand * & Dest ) const { if ( ! MI . isMoveReg ( ) || ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) != MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; Dest = & MI . getOperand ( <NUM_LIT> ) ;


<s> bool <ISA_LIT>BaseInstrInfo :: isCopyInstr ( const MachineInstr & MI , const MachineOperand * & Src , const MachineOperand * & Dest ) const { if ( ! MI . isMoveReg ( ) || ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) != MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; Dest = & MI . getOperand ( <NUM_LIT> ) ; Src = & MI . getOperand ( <NUM_LIT> ) ;


<s> switch ( AddrMode ) { case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) ; case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) && Imm % <NUM_LIT> == <NUM_LIT> ; case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) && Imm % <NUM_LIT> == <NUM_LIT> ; case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) ; case <STR_LIT> :


<s> } else { return true ; } if ( ! isPredicated ( * I ) && ( isUncondBranchOpcode ( I -> getOpcode ( ) ) || isIndirectBranchOpcode ( I -> getOpcode ( ) ) || isJumpTableBranchOpcode ( I -> getOpcode ( ) ) || I -> isReturn ( ) ) ) { Cond . clear ( ) ; FBB = nullptr ; if ( AllowModify ) { MachineBasicBlock :: iterator DI = std :: next ( I ) ; while ( DI != MBB . end ( ) ) { MachineInstr & InstToDelete = * DI ; ++ DI ; InstToDelete . eraseFromParent ( ) ; } } } if ( CantAnalyze ) return true ; if ( I == MBB . begin ( ) ) return false ; -- I ; } return false ;


<s> bool <ISA_LIT>BaseInstrInfo :: analyzeCompare ( const MachineInstr & MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = ~ <NUM_LIT> ; CmpValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = ~ <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; CmpValue = <NUM_LIT> ; return true ; } return false ;


<s> unsigned Reg = MO . getReg ( ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) && <STR_LIT> ) ; unsigned DReg = Reg ; if ( <STR_LIT> . contains ( Reg ) ) { DReg = <STR_LIT> + ( Reg - <STR_LIT> ) / <NUM_LIT> ; assert ( TRI -> isSuperRegister ( Reg , DReg ) && <STR_LIT> ) ; } assert ( <STR_LIT> . contains ( DReg ) && <STR_LIT> ) ; assert ( MI . definesRegister ( DReg , TRI ) && <STR_LIT> ) ;

BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) , DReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ;


<s> std :: vector < MachineInstr * > NewMIs ; if ( isPre ) { if ( isLoad ) MemMI = BuildMI ( MF , MI . getDebugLoc ( ) , get ( MemOpc ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( WBReg ) . addImm ( <NUM_LIT> ) . addImm ( Pred ) ; else MemMI = BuildMI ( MF , MI . getDebugLoc ( ) , get ( MemOpc ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( WBReg ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( Pred ) ; NewMIs . push_back ( MemMI ) ; NewMIs . push_back ( UpdateMI ) ; } else { if ( isLoad ) MemMI = BuildMI ( MF , MI . getDebugLoc ( ) , get ( MemOpc ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( BaseReg ) . addImm ( <NUM_LIT> ) . addImm ( Pred ) ; else MemMI = BuildMI ( MF , MI . getDebugLoc ( ) , get ( MemOpc ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( BaseReg ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( Pred ) ; if ( WB . isDead ( ) ) UpdateMI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; NewMIs . push_back ( UpdateMI ) ; NewMIs . push_back ( MemMI ) ; } if ( LV ) { for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) && TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) { unsigned Reg = MO . getReg ( ) ; LiveVariables :: VarInfo & VI = LV -> getVarInfo ( Reg ) ; if ( MO . isDef ( ) ) { MachineInstr * NewMI = ( Reg == WBReg ) ? UpdateMI : MemMI ; if ( MO . isDead ( ) ) LV -> addVirtualRegisterDead ( Reg , * NewMI ) ; } if ( MO . isUse ( ) && MO . isKill ( ) ) { for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) { MachineInstr * NewMI = NewMIs [ j ] ; if ( ! NewMI -> readsRegister ( Reg ) ) continue ; LV -> addVirtualRegisterKilled ( Reg , * NewMI ) ; if ( VI . removeKill ( MI ) ) VI . Kills . push_back ( NewMI ) ; break ; }


<s> if ( Subtarget . isMClass ( ) ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Implicit | getKillRegState ( KillSrc ) ) ;


<s> MachineInstrBuilder MIB = BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( Opc ) , DestReg ) ; if ( Subtarget . isMClass ( ) ) MIB . addImm ( <NUM_LIT> ) ;

MIB . add ( predOps ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Implicit | getKillRegState ( KillSrc ) ) ;


<s> MachineInstrBuilder MIB = BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( Opc ) ) ; if ( Subtarget . isMClass ( ) ) MIB . addImm ( <NUM_LIT> ) ; else MIB . addImm ( <NUM_LIT> ) ; MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) ;


<s> if ( Subtarget . isMClass ( ) ) MIB . addImm ( <NUM_LIT> ) ; else MIB . addImm ( <NUM_LIT> ) ;

MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) ;


return std :: make_pair ( TF & Mask , TF & ~ Mask ) ;


<s> return std :: make_pair ( TF & Mask , TF & ~ Mask ) ;


<s> switch ( I -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CPI = I -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; I -> getOperand ( <NUM_LIT> ) . setIndex ( CPI ) ; I -> getOperand ( <NUM_LIT> ) . setImm ( PCLabelId ) ; break ; } }

if ( ! I -> isBundledWithSucc ( ) ) break ;


<s> if ( ACPV -> isGlobalValue ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getGV ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> , ACPV -> getModifier ( ) , ACPV -> mustAddCurrentAddress ( ) ) ; else if ( ACPV -> isExtSymbol ( ) ) NewCPV = <ISA_LIT>ConstantPoolSymbol :: Create ( MF . getFunction ( ) . getContext ( ) , cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) , PCLabelId , <NUM_LIT> ) ; else if ( ACPV -> isBlockAddress ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getBlockAddress ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ;

else if ( ACPV -> isLSDA ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( & MF . getFunction ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ;


<s> if ( NumBytes == <NUM_LIT> && DestReg != BaseReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . add ( predOps ( Pred , PredReg ) ) . add ( condCodeOp ( ) ) . setMIFlags ( MIFlags ) ; return ; } bool isSub = NumBytes < <NUM_LIT> ; if ( isSub ) NumBytes = - NumBytes ; while ( NumBytes ) { unsigned RotAmt = <STR_LIT> ( NumBytes ) ; unsigned ThisVal = NumBytes & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; assert ( ThisVal && <STR_LIT> ) ;


<s> void <ISA_LIT>BaseInstrInfo :: expandLoadStackGuardBase ( MachineBasicBlock :: iterator MI , unsigned LoadImmOpc , unsigned LoadOpc ) const { assert ( ! Subtarget . isROPI ( ) && ! Subtarget . isRWPI ( ) && <STR_LIT> ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; MachineInstrBuilder MIB ; BuildMI ( MBB , MI , DL , get ( LoadImmOpc ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; if ( Subtarget . isGVIndirectSymbol ( GV ) ) { MIB = BuildMI ( MBB , MI , DL , get ( LoadOpc ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( * MBB . getParent ( ) ) , Flags , <NUM_LIT> , <NUM_LIT> ) ; MIB . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; }


<s> } else { STM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) ; } MachineOperand LDBase ( MI -> getOperand ( <NUM_LIT> ) ) ; LDM . add ( LDBase ) . add ( predOps ( <STR_LIT> ) ) ; MachineOperand STBase ( MI -> getOperand ( <NUM_LIT> ) ) ; STM . add ( STBase ) . add ( predOps ( <STR_LIT> ) ) ; const TargetRegisterInfo & TRI = getRegisterInfo ( ) ; SmallVector < unsigned , <NUM_LIT> > ScratchRegs ; for ( unsigned I = <NUM_LIT> ; I < MI -> getNumOperands ( ) ; ++ I ) ScratchRegs . push_back ( MI -> getOperand ( I ) . getReg ( ) ) ; llvm :: sort ( ScratchRegs , [ & TRI ] ( const unsigned & Reg1 , const unsigned & Reg2 ) -> bool { return TRI . getEncodingValue ( Reg1 ) < TRI . getEncodingValue ( Reg2 ) ; } ) ;

for ( const auto & Reg : ScratchRegs ) {


<s> expandLoadStackGuard ( MI ) ; MI . getParent ( ) -> erase ( MI ) ; return true ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { expandMEMCPY ( MI ) ; return true ; } if ( ! MI . isCopy ( ) || Subtarget . dontWidenVMOVS ( ) || Subtarget . isFPOnlySP ( ) ) return false ; unsigned DstRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || ! SrcRegD ) return false ; if ( ! MI . definesRegister ( DstRegD , TRI ) || MI . readsRegister ( DstRegD , TRI ) ) return false ; if ( MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; MachineInstrBuilder MIB ( * MI . getParent ( ) -> getParent ( ) , MI ) ;

int ImpDefIdx = MI . findRegisterDefOperandIdx ( DstRegD ) ;


<s> case <STR_LIT> : { Commute = UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) != Reg ; switch ( UseOpc ) { default : break ; case <STR_LIT> : case <STR_LIT> : if ( UseOpc == <STR_LIT> && Commute ) return false ; if ( <STR_LIT> ( ImmVal ) ) NewUseOpc = UseOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> ( - ImmVal ) ) { ImmVal = - ImmVal ; NewUseOpc = UseOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! <STR_LIT> ( ImmVal ) ) return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; switch ( UseOpc ) { default : break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; } break ; case <STR_LIT> : case <STR_LIT> : if ( UseOpc == <STR_LIT> && Commute ) return false ; if ( <STR_LIT> ( ImmVal ) ) NewUseOpc = UseOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> ( - ImmVal ) ) { ImmVal = - ImmVal ; NewUseOpc = UseOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! <STR_LIT> ( ImmVal ) ) return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; switch ( UseOpc ) { default : break ;


<s> default : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; }


<s> bool <ISA_LIT>BaseInstrInfo :: getExtractSubregLikeInputs ( const MachineInstr & MI , unsigned DefIdx , RegSubRegPairAndIdx & InputReg ) const { assert ( DefIdx < MI . getDesc ( ) . getNumDefs ( ) && <STR_LIT> ) ; assert ( MI . isExtractSubregLike ( ) && <STR_LIT> ) ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : const MachineOperand & MOReg = MI . getOperand ( <NUM_LIT> ) ; if ( MOReg . isUndef ( ) ) return false ; InputReg . Reg = MOReg . getReg ( ) ; InputReg . SubReg = MOReg . getSubReg ( ) ; InputReg . SubIdx = DefIdx == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ;


<s> const MachineOperand & MOInsertedReg = MI . getOperand ( <NUM_LIT> ) ; if ( MOInsertedReg . isUndef ( ) ) return false ; const MachineOperand & MOIndex = MI . getOperand ( <NUM_LIT> ) ; BaseReg . Reg = MOBaseReg . getReg ( ) ; BaseReg . SubReg = MOBaseReg . getSubReg ( ) ; InsertedReg . Reg = MOInsertedReg . getReg ( ) ; InsertedReg . SubReg = MOInsertedReg . getSubReg ( ) ;

InsertedReg . SubIdx = MOIndex . getImm ( ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ;


<s> unsigned Size = <NUM_LIT> ; MachineBasicBlock :: const_instr_iterator I = MI . getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI . getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) {

assert ( ! I -> isBundle ( ) && <STR_LIT> ) ;


<s> while ( ++ I != E && I -> isInsideBundle ( ) ) { if ( I -> getOpcode ( ) != <STR_LIT> ) Latency += getInstrLatency ( ItinData , * I , PredCost ) ; } return Latency ; } const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( PredCost && ( MCID . isCall ( ) || ( MCID . hasImplicitDefOfPhysReg ( <STR_LIT> ) && ! Subtarget . cheapPredicableCPSRDef ( ) ) ) ) { * PredCost = <NUM_LIT> ; } if ( ! ItinData ) return MI . mayLoad ( ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Class = MCID . getSchedClass ( ) ; if ( ! ItinData -> isEmpty ( ) && ItinData -> getNumMicroOps ( Class ) < <NUM_LIT> ) return getNumMicroOps ( ItinData , MI ) ; unsigned Latency = ItinData -> getStageLatency ( Class ) ; unsigned DefAlign = MI . hasOneMemOperand ( ) ? ( * MI . memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; int Adj = adjustDefLatency ( Subtarget , MI , MCID , DefAlign ) ; if ( Adj >= <NUM_LIT> || ( int ) Latency > - Adj ) { return Latency + Adj ; } return Latency ;


<s> unsigned <ISA_LIT>BaseInstrInfo :: getLDMVariableDefsSize ( const MachineInstr & MI ) const { return MI . getNumOperands ( ) + <NUM_LIT> - MI . getDesc ( ) . getNumOperands ( ) ;


<s> unsigned <ISA_LIT>BaseInstrInfo :: getLDMVariableDefsSize ( const MachineInstr & MI ) const {

return MI . getNumOperands ( ) + <NUM_LIT> - MI . getDesc ( ) . getNumOperands ( ) ;


<s> if ( MF -> getFunction ( ) . hasFnAttribute ( Attribute :: OptimizeForSize ) ) -- Latency ; } return Latency ; } if ( DefMO . isImplicit ( ) || UseMI . getOperand ( UseIdx ) . isImplicit ( ) ) return - <NUM_LIT> ; unsigned DefAlign = DefMI . hasOneMemOperand ( ) ? ( * DefMI . memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; unsigned UseAlign = UseMI . hasOneMemOperand ( ) ? ( * UseMI . memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; int Latency = getOperandLatency ( ItinData , DefMCID , DefIdx , DefAlign , UseMCID , UseIdx , UseAlign ) ; if ( Latency < <NUM_LIT> ) return Latency ;


<s> unsigned <ISA_LIT>BaseInstrInfo :: getPredicationCost ( const MachineInstr & MI ) const {

if ( MI . isCopyLike ( ) || MI . isInsertSubreg ( ) || MI . isRegSequence ( ) || MI . isImplicitDef ( ) ) return <NUM_LIT> ;


<s> if ( MI . isBundle ( ) ) return <NUM_LIT> ; const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( MCID . isCall ( ) || ( MCID . hasImplicitDefOfPhysReg ( <STR_LIT> ) && ! Subtarget . cheapPredicableCPSRDef ( ) ) ) {


<s> assert ( DefIdx < MI . getDesc ( ) . getNumDefs ( ) && <STR_LIT> ) ; assert ( MI . isRegSequenceLike ( ) && <STR_LIT> ) ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : const MachineOperand * MOReg = & MI . getOperand ( <NUM_LIT> ) ; if ( ! MOReg -> isUndef ( ) ) InputRegs . push_back ( RegSubRegPairAndIdx ( MOReg -> getReg ( ) , MOReg -> getSubReg ( ) , <STR_LIT> ) ) ; MOReg = & MI . getOperand ( <NUM_LIT> ) ; if ( ! MOReg -> isUndef ( ) ) InputRegs . push_back ( RegSubRegPairAndIdx ( MOReg -> getReg ( ) , MOReg -> getSubReg ( ) , <STR_LIT> ) ) ;


<s> bool <ISA_LIT>BaseInstrInfo :: getRegSequenceLikeInputs ( const MachineInstr & MI , unsigned DefIdx , SmallVectorImpl < RegSubRegPairAndIdx > & InputRegs ) const { assert ( DefIdx < MI . getDesc ( ) . getNumDefs ( ) && <STR_LIT> ) ; assert ( MI . isRegSequenceLike ( ) && <STR_LIT> ) ;


<s> { MO_COFFSTUB , <STR_LIT> } , { MO_GOT , <STR_LIT> } , { MO_SBREL , <STR_LIT> } , { MO_DLLIMPORT , <STR_LIT> } , { MO_SECREL , <STR_LIT> } , { MO_NONLAZY , <STR_LIT> } } ; return makeArrayRef ( TargetFlags ) ;


<s> using namespace <ISA_LIT>II ; static const std :: pair < unsigned , const char * > TargetFlags [ ] = {

{ MO_COFFSTUB , <STR_LIT> } , { MO_GOT , <STR_LIT> } , { MO_SBREL , <STR_LIT> } , { MO_DLLIMPORT , <STR_LIT> } , { MO_SECREL , <STR_LIT> } , { MO_NONLAZY , <STR_LIT> } } ;


<s> static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_LO16 , <STR_LIT> } , { MO_HI16 , <STR_LIT> } } ; return makeArrayRef ( TargetFlags ) ;


<s> if ( isThumb ) BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) . add ( predOps ( <STR_LIT> ) ) ; else BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else BuildMI ( & MBB , DL , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . add ( Cond [ <NUM_LIT> ] ) ; return <NUM_LIT> ; } BuildMI ( & MBB , DL , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . add ( Cond [ <NUM_LIT> ] ) ; if ( isThumb ) BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( FBB ) . add ( predOps ( <STR_LIT> ) ) ; else BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( FBB ) ; return <NUM_LIT> ;


<s> bool <ISA_LIT>BaseInstrInfo :: isAddrMode3OpImm ( const MachineInstr & MI , unsigned Op ) const {

const MachineOperand & Offset = MI . getOperand ( Op + <NUM_LIT> ) ;


<s> bool <ISA_LIT>BaseInstrInfo :: isAddrMode3OpMinusReg ( const MachineInstr & MI , unsigned Op ) const { const MachineOperand & Offset = MI . getOperand ( Op + <NUM_LIT> ) ; const MachineOperand & Opc = MI . getOperand ( Op + <NUM_LIT> ) ; assert ( Opc . isImm ( ) ) ; assert ( Offset . isReg ( ) ) ; int64_t OpcImm = Opc . getImm ( ) ; bool isSub = <STR_LIT> ( OpcImm ) == <STR_LIT> ;

return ( isSub && Offset . getReg ( ) != <NUM_LIT> ) ;


<s> bool <ISA_LIT>BaseInstrInfo :: isAm2ScaledReg ( const MachineInstr & MI , unsigned Op ) const {

unsigned OffImm = MI . getOperand ( Op + <NUM_LIT> ) . getImm ( ) ;


<s> bool <ISA_LIT>BaseInstrInfo :: isCopyInstrImpl ( const MachineInstr & MI , const MachineOperand * & Src , const MachineOperand * & Dest ) const { if ( ! MI . isMoveReg ( ) || ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) != MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; Dest = & MI . getOperand ( <NUM_LIT> ) ;


<s> bool <ISA_LIT>BaseInstrInfo :: isCPSRDefined ( const MachineInstr & MI ) {

for ( const auto & MO : MI . operands ( ) ) if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> && MO . isDef ( ) && ! MO . isDead ( ) ) return true ;


<s> for ( const auto & MO : MI . operands ( ) ) if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> && MO . isDef ( ) && ! MO . isDead ( ) ) return true ;


<s> default : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>BaseInstrInfo :: isLDMBaseRegInList ( const MachineInstr & MI ) const { unsigned BaseReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( unsigned i = <NUM_LIT> , sz = MI . getNumOperands ( ) ; i < sz ; ++ i ) { const auto & Op = MI . getOperand ( i ) ; if ( Op . isReg ( ) && Op . getReg ( ) == BaseReg ) return true ;


<s> unsigned OffImm = Opc . getImm ( ) ;

return <STR_LIT> ( OffImm ) != <STR_LIT> ;


<s> unsigned OffImm = Opc . getImm ( ) ; return <STR_LIT> ( OffImm ) != <STR_LIT> ;


<s> const MachineOperand & Opc = MI . getOperand ( Op + <NUM_LIT> ) ; unsigned OffImm = Opc . getImm ( ) ; bool isAdd = <STR_LIT> ( OffImm ) == <STR_LIT> ; unsigned Amt = <STR_LIT> ( OffImm ) ; <STR_LIT> ShiftOpc = <STR_LIT> ( OffImm ) ;

if ( ShiftOpc == <STR_LIT> ) return false ;


<s> const MachineOperand & Opc = MI . getOperand ( Op + <NUM_LIT> ) ; unsigned OffImm = Opc . getImm ( ) ;

bool isAdd = <STR_LIT> ( OffImm ) == <STR_LIT> ;


<s> bool <ISA_LIT>BaseInstrInfo :: isLdstSoMinusReg ( const MachineInstr & MI , unsigned Op ) const { unsigned OffImm = MI . getOperand ( Op + <NUM_LIT> ) . getImm ( ) ;

return <STR_LIT> ( OffImm ) == <STR_LIT> ;


<s> bool <ISA_LIT>BaseInstrInfo :: isLdstSoMinusReg ( const MachineInstr & MI , unsigned Op ) const { unsigned OffImm = MI . getOperand ( Op + <NUM_LIT> ) . getImm ( ) ; return <STR_LIT> ( OffImm ) == <STR_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ;


<s> unsigned <ISA_LIT>BaseInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { SmallVector < const MachineMemOperand * , <NUM_LIT> > Accesses ; if ( MI . mayLoad ( ) && hasLoadFromStackSlot ( MI , Accesses ) ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ; return true ; }


<s> SmallVector < const MachineMemOperand * , <NUM_LIT> > Accesses ; if ( MI . mayLoad ( ) && hasLoadFromStackSlot ( MI , Accesses ) ) {

FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; }


<s> bool <ISA_LIT>BaseInstrInfo :: isPredicable ( const MachineInstr & MI ) const { if ( ! MI . isPredicable ( ) ) return false ; if ( MI . isBundle ( ) ) return false ; if ( ! isEligibleForITBlock ( & MI ) ) return false ; const <ISA_LIT>FunctionInfo * AFI = MI . getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) return false ; if ( AFI -> isThumb2Function ( ) ) {

if ( getSubtarget ( ) . restrictIT ( ) ) return isV8EligibleForIT ( & MI ) ;


<s> TUnpredCycles = TCycles + NotTakenBranchCost ; FUnpredCycles = TakenBranchCost ; } else { TUnpredCycles = TCycles + TakenBranchCost ; FUnpredCycles = FCycles + NotTakenBranchCost ; PredCost -= <NUM_LIT> * ScalingUpFactor ; } unsigned TUnpredCost = Probability . scale ( TUnpredCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FUnpredCycles * ScalingUpFactor ) ; UnpredCost = TUnpredCost + FUnpredCost ; if ( Subtarget . isThumb2 ( ) && TCycles + FCycles > <NUM_LIT> ) { PredCost += ( ( TCycles + FCycles - <NUM_LIT> ) / <NUM_LIT> ) * ScalingUpFactor ; } } else {

unsigned TUnpredCost = Probability . scale ( TCycles * ScalingUpFactor ) ;


<s> if ( ( CmpI -> getOpcode ( ) == <STR_LIT> || CmpI -> getOpcode ( ) == <STR_LIT> ) && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && ( ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) || ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ) ) return true ;

if ( ( CmpI -> getOpcode ( ) == <STR_LIT> || CmpI -> getOpcode ( ) == <STR_LIT> ) && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getImm ( ) == ImmValue ) return true ;


<s> MachineBasicBlock :: const_iterator I = MI ; while ( ++ I != MBB -> end ( ) && I -> isDebugInstr ( ) ) ; if ( I != MBB -> end ( ) && I -> getOpcode ( ) == <STR_LIT> ) return true ; if ( ! MI . isCall ( ) && MI . definesRegister ( <STR_LIT> ) ) return true ;


<s> if ( MI . isDebugInstr ( ) ) return false ; if ( MI . isTerminator ( ) || MI . isPosition ( ) ) return true ; MachineBasicBlock :: const_iterator I = MI ;

while ( ++ I != MBB -> end ( ) && I -> isDebugInstr ( ) ) ;


<s> if ( MI . mayStore ( ) && hasStoreToStackSlot ( MI , Accesses ) ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ;


<s> SmallVector < const MachineMemOperand * , <NUM_LIT> > Accesses ; if ( MI . mayStore ( ) && hasStoreToStackSlot ( MI , Accesses ) ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ; return true ;


<s> break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . add ( predOps ( <STR_LIT> ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . add ( predOps ( <STR_LIT> ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ;


<s> case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; } if ( SubAdd ) { unsigned Opc = SubAdd -> getOpcode ( ) ; bool IsSub = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( ! IsSub || ( SrcReg2 != <NUM_LIT> && SubAdd -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && SubAdd -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ) { if ( IsInstrVSel ) return false ; <STR_LIT> NewCC = ( IsSub ? getSwappedCondition ( CC ) : getCmpToAddCondition ( CC ) ) ; if ( NewCC == <STR_LIT> ) return false ; OperandsToUpdate . push_back ( std :: make_pair ( & ( ( * I ) . getOperand ( IO - <NUM_LIT> ) ) , NewCC ) ) ; } } else { switch ( CC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } } } } if ( ! isSafe ) { MachineBasicBlock * MBB = CmpInstr . getParent ( ) ; for ( MachineBasicBlock :: succ_iterator SI = MBB -> succ_begin ( ) , SE = MBB -> succ_end ( ) ; SI != SE ; ++ SI ) if ( ( * SI ) -> isLiveIn ( <STR_LIT> ) ) return false ; } if ( ! IsThumb1 ) { MI -> getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDef ( true ) ; } assert ( ! isPredicated ( * MI ) && <STR_LIT> ) ; CmpInstr . eraseFromParent ( ) ; for ( unsigned i = <NUM_LIT> , e = OperandsToUpdate . size ( ) ; i < e ; i ++ ) OperandsToUpdate [ i ] . first -> setImm ( OperandsToUpdate [ i ] . second ) ; MI -> clearRegisterDeads ( <STR_LIT> ) ; return true ;


<s> assert ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MachineInstr * DefMI = canFoldIntoMOVCC ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; bool Invert = ! DefMI ; if ( ! DefMI ) DefMI = canFoldIntoMOVCC ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; if ( ! DefMI ) return nullptr ; MachineOperand FalseReg = MI . getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * PreviousClass = MRI . getRegClass ( FalseReg . getReg ( ) ) ; if ( ! MRI . constrainRegClass ( DestReg , PreviousClass ) ) return nullptr ; MachineInstrBuilder NewMI = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . add ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( <STR_LIT> ( <STR_LIT> ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . add ( MI . getOperand ( <NUM_LIT> ) ) ; if ( NewMI -> hasOptionalDef ( ) ) NewMI . add ( condCodeOp ( ) ) ; FalseReg . setImplicit ( ) ; NewMI . add ( FalseReg ) ; NewMI -> tieOperands ( <NUM_LIT> , NewMI -> getNumOperands ( ) - <NUM_LIT> ) ;


<s> MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( & Orig ) ; MI -> substituteRegister ( Orig . getOperand ( <NUM_LIT> ) . getReg ( ) , DestReg , SubIdx , TRI ) ; MBB . insert ( I , MI ) ; break ; } case <STR_LIT> : case <STR_LIT> : { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CPI = Orig . getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; BuildMI ( MBB , I , Orig . getDebugLoc ( ) , get ( Opcode ) , DestReg ) . addConstantPoolIndex ( CPI ) . addImm ( PCLabelId ) . cloneMemRefs ( Orig ) ;


<s> if ( I == MBB . end ( ) ) return <NUM_LIT> ; if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ;


<s> if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ;


<s> Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ( CC ) ) ; return false ;


<s> MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . RemoveOperand ( FrameRegIdx + <NUM_LIT> ) ; Offset = <NUM_LIT> ; return true ; } else if ( Offset < <NUM_LIT> ) { Offset = - Offset ; isSub = true ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; } if ( <STR_LIT> ( Offset ) != - <NUM_LIT> ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; Offset = <NUM_LIT> ; return true ; } unsigned RotAmt = <STR_LIT> ( Offset ) ; unsigned ThisImmVal = Offset & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; Offset &= ~ ThisImmVal ; assert ( <STR_LIT> ( ThisImmVal ) != - <NUM_LIT> && <STR_LIT> ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( ThisImmVal ) ; } else { unsigned ImmIdx = <NUM_LIT> ; int InstrOffs = <NUM_LIT> ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; switch ( AddrMode ) { case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : return false ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ;


<s> ++ Next ; unsigned SrcReg , SrcReg2 ; int CmpMask , CmpValue ;

if ( Next != MI . getParent ( ) -> end ( ) && analyzeCompare ( * Next , SrcReg , SrcReg2 , CmpMask , CmpValue ) && isRedundantFlagInstr ( & * Next , SrcReg , SrcReg2 , CmpValue , & MI ) ) return false ;


<s> AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { BuildMI ( MBB , I , DebugLoc ( ) , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else { BuildMI ( MBB , I , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { BuildMI ( MBB , I , DebugLoc ( ) , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else { MachineInstrBuilder MIB = BuildMI ( MBB , I , DebugLoc ( ) , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . add ( predOps ( <STR_LIT> ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { BuildMI ( MBB , I , DebugLoc ( ) , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else { MachineInstrBuilder MIB = BuildMI ( MBB , I , DebugLoc ( ) , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . add ( predOps ( <STR_LIT> ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ;


<s> assert ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> const MachineSDNode * DefMN = dyn_cast < MachineSDNode > ( DefNode ) ; unsigned DefAlign = ! DefMN -> memoperands_empty ( ) ? ( * DefMN -> memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; const MachineSDNode * UseMN = dyn_cast < MachineSDNode > ( UseNode ) ; unsigned UseAlign = ! UseMN -> memoperands_empty ( ) ? ( * UseMN -> memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; int Latency = getOperandLatency ( ItinData , DefMCID , DefIdx , DefAlign , UseMCID , UseIdx , UseAlign ) ; if ( Latency > <NUM_LIT> && ( Subtarget . isCortexA8 ( ) || Subtarget . isCortexA9 ( ) ) ) { switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned ShOpVal = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned ShImm = <STR_LIT> ( ShOpVal ) ; if ( ShImm == <NUM_LIT> || ( ShImm == <NUM_LIT> && <STR_LIT> ( ShOpVal ) == <STR_LIT> ) ) -- Latency ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned ShAmt = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( ShAmt == <NUM_LIT> || ShAmt == <NUM_LIT> ) -- Latency ; break ; } } } if ( DefAlign < <NUM_LIT> && Subtarget . isCortexA9 ( ) ) switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> static inline bool isIndirectBranchOpcode ( int Opc ) { return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> bool isPredicated ( const MachineInstr * MI ) const {

int PIdx = MI -> findFirstPredOperandIdx ( ) ;


<s> int PIdx = MI -> findFirstPredOperandIdx ( ) ;

return PIdx != - <NUM_LIT> && MI -> getOperand ( PIdx ) . getImm ( ) != <STR_LIT> ;


<s> virtual bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumInstrs ) const { return NumInstrs && NumInstrs == <NUM_LIT> ;


<s> std :: string <ISA_LIT>BaseInstrInfo :: createMIROperandComment ( const MachineInstr & MI , const MachineOperand & Op , unsigned OpIdx ) const { if ( Op . getType ( ) != MachineOperand :: MO_Immediate ) return std :: string ( ) ; int FirstPredOp = MI . findFirstPredOperandIdx ( ) ; if ( FirstPredOp != ( int ) OpIdx ) return std :: string ( ) ; std :: string CC = <STR_LIT> ; CC += <ISA_LIT>CondCodeToString ( ( <STR_LIT> ) Op . getImm ( ) ) ; return CC ;


<s> bool <ISA_LIT>BaseInstrInfo :: isAddImmediate ( const MachineInstr & MI , const MachineOperand * & Destination , const MachineOperand * & Source , int64_t & Offset ) const { int Sign = <NUM_LIT> ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> ) Sign = - <NUM_LIT> ; else if ( Opcode != <STR_LIT> ) return false ;

if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ;


<s> if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; Destination = & MI . getOperand ( <NUM_LIT> ) ; Source = & MI . getOperand ( <NUM_LIT> ) ; Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) * Sign ;


<s> virtual void getNoopForElfTarget ( MCInst & NopInst ) const { getNoopForMachoTarget ( NopInst ) ;


<s> static inline MachineOperand condCodeOp ( unsigned CCReg = <NUM_LIT> ) { return MachineOperand :: CreateReg ( CCReg , <NUM_LIT> ) ;


<s> return MachineOperand :: CreateReg ( CCReg , <NUM_LIT> ) ;


<s> if ( IntInst == nullptr ) return false ; unsigned IntrinsicID = IntInst -> getIntrinsicID ( ) ; return ( IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> ) ;


<s> inline bool isLegalAddressImm ( unsigned Opcode , int Imm , const TargetInstrInfo * TII ) { const MCInstrDesc & Desc = TII -> get ( Opcode ) ; unsigned AddrMode = ( Desc . TSFlags & <STR_LIT> ) ; switch ( AddrMode ) { case <STR_LIT> :

return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) ;


<s> case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) ; case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) && Imm % <NUM_LIT> == <NUM_LIT> ; case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) && Imm % <NUM_LIT> == <NUM_LIT> ;


<s> default : break ; case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ;


<s> default : break ; case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; } return <NUM_LIT> ;


<s> FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; }


<s> TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isUncondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } if ( isJumpTableBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return true ; }


<s> <ISA_LIT>BaseInstrInfo :: <ISA_LIT>BaseInstrInfo ( ) : TargetInstrInfoImpl ( <ISA_LIT>Insts , array_lengthof ( <ISA_LIT>Insts ) ) {


<s> } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) { return true ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { return true ;


<s> if ( DestRC != SrcRC ) { if ( ( ( DestRC == <STR_LIT> ) && ( SrcRC == <STR_LIT> ) ) || ( ( SrcRC == <STR_LIT> ) && ( DestRC == <STR_LIT> ) ) ) { } else { return false ; } } if ( DestRC == <STR_LIT> ) { AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ) ; } else if ( DestRC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; } else if ( ( DestRC == <STR_LIT> ) || ( DestRC == <STR_LIT> ) ) {


<s> return false ; } } if ( DestRC == <STR_LIT> ) { AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ) ; } else if ( DestRC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; } else if ( ( DestRC == <STR_LIT> ) || ( DestRC == <STR_LIT> ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ;


<s> int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( PIdx == - <NUM_LIT> ) { PredReg = <NUM_LIT> ; return <STR_LIT> ; }

PredReg = MI -> getOperand ( PIdx + <NUM_LIT> ) . getReg ( ) ;


<s> return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned EntrySize = ( Opc == <STR_LIT> ) ? <NUM_LIT> : ( ( Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned NumOps = TID . getNumOperands ( ) ; MachineOperand JTOP = MI -> getOperand ( NumOps - ( TID . isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOP . getIndex ( ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; assert ( JTI < JT . size ( ) ) ; unsigned InstSize = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned NumEntries = getNumJTEntries ( JT , JTI ) ; if ( Opc == <STR_LIT> && ( NumEntries & <NUM_LIT> ) ) ++ NumEntries ; return NumEntries * EntrySize + InstSize ; } default : return <NUM_LIT> ; } } } return <NUM_LIT> ;


<s> static unsigned getNumJTEntries ( const std :: vector < MachineJumpTableEntry > & JT , unsigned JTI ) { return JT [ JTI ] . MBBs . size ( ) ;


<s> return JT [ JTI ] . MBBs . size ( ) ;


<s> case <STR_LIT> : { assert ( MI . getDesc ( ) . getNumOperands ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return true ; } } return false ;


<s> unsigned <ISA_LIT>BaseInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> :


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; } else if ( RC == <STR_LIT> || RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ) ; } else if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ) ;


<s> bool isSub = false ; if ( Opcode == <STR_LIT> ) AddrMode = <STR_LIT> ; if ( Opcode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) ; if ( Offset == <NUM_LIT> ) { MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . RemoveOperand ( FrameRegIdx + <NUM_LIT> ) ; return <NUM_LIT> ; } else if ( Offset < <NUM_LIT> ) { Offset = - Offset ; isSub = true ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; } if ( <STR_LIT> ( Offset ) != - <NUM_LIT> ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return <NUM_LIT> ; } unsigned RotAmt = <STR_LIT> ( Offset ) ; unsigned ThisImmVal = Offset & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; Offset &= ~ ThisImmVal ; assert ( <STR_LIT> ( ThisImmVal ) != - <NUM_LIT> && <STR_LIT> ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( ThisImmVal ) ; } else { unsigned ImmIdx = <NUM_LIT> ; int InstrOffs = <NUM_LIT> ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; switch ( AddrMode ) { case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; } case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; } case <STR_LIT> : break ; case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ;


<s> void <ISA_LIT>BaseInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ;

} else if ( RC == <STR_LIT> || RC == <STR_LIT> ) {


<s> virtual bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCyles , float Probability , float Confidence ) const { return NumCyles == <NUM_LIT> ;


<s> unsigned SrcRegS = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || ! SrcRegD ) return false ; if ( ! MI -> definesRegister ( DstRegD , TRI ) || MI -> readsRegister ( DstRegD , TRI ) ) return false ; if ( MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MachineInstrBuilder MIB ( * MI -> getParent ( ) -> getParent ( ) , MI ) ; int ImpDefIdx = MI -> findRegisterDefOperandIdx ( DstRegD ) ;

if ( ImpDefIdx != - <NUM_LIT> ) MI -> RemoveOperand ( ImpDefIdx ) ;


<s> MI -> setDesc ( get ( <STR_LIT> ) ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( DstRegD ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( SrcRegD ) ; AddDefaultPred ( MIB ) ; MI -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; MIB . addReg ( SrcRegS , RegState :: Implicit ) ; if ( MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) { MI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; MI -> addRegisterKilled ( SrcRegS , TRI , true ) ; }

DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ;


<s> const MachineOperand & Base = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & Offset = MI . getOperand ( NumOps - <NUM_LIT> ) ; Register WBReg = WB . getReg ( ) ; Register BaseReg = Base . getReg ( ) ; Register OffReg = Offset . getReg ( ) ; unsigned OffImm = MI . getOperand ( NumOps - <NUM_LIT> ) . getImm ( ) ; <STR_LIT> Pred = ( <STR_LIT> ) MI . getOperand ( NumOps - <NUM_LIT> ) . getImm ( ) ; switch ( AddrMode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : { bool isSub = <STR_LIT> ( OffImm ) == <STR_LIT> ; unsigned Amt = <STR_LIT> ( OffImm ) ; if ( OffReg == <NUM_LIT> ) { if ( <STR_LIT> ( Amt ) == - <NUM_LIT> ) return nullptr ; UpdateMI = BuildMI ( MF , MI . getDebugLoc ( ) , get ( isSub ? <STR_LIT> : <STR_LIT> ) , WBReg ) . addReg ( BaseReg ) . addImm ( Amt ) . add ( predOps ( Pred ) ) . add ( condCodeOp ( ) ) ; } else if ( Amt != <NUM_LIT> ) { <STR_LIT> ShOpc = <STR_LIT> ( OffImm ) ; unsigned SOOpc = <STR_LIT> ( ShOpc , Amt ) ; UpdateMI = BuildMI ( MF , MI . getDebugLoc ( ) , get ( isSub ? <STR_LIT> : <STR_LIT> ) , WBReg ) . addReg ( BaseReg ) . addReg ( OffReg ) . addReg ( <NUM_LIT> ) . addImm ( SOOpc ) . add ( predOps ( Pred ) ) . add ( condCodeOp ( ) ) ; } else UpdateMI = BuildMI ( MF , MI . getDebugLoc ( ) , get ( isSub ? <STR_LIT> : <STR_LIT> ) , WBReg ) . addReg ( BaseReg ) . addReg ( OffReg ) . add ( predOps ( Pred ) ) . add ( condCodeOp ( ) ) ; break ; } case <STR_LIT> : { bool isSub = <STR_LIT> ( OffImm ) == <STR_LIT> ; unsigned Amt = <STR_LIT> ( OffImm ) ; if ( OffReg == <NUM_LIT> ) UpdateMI = BuildMI ( MF , MI . getDebugLoc ( ) , get ( isSub ? <STR_LIT> : <STR_LIT> ) , WBReg ) . addReg ( BaseReg ) . addImm ( Amt ) . add ( predOps ( Pred ) ) . add ( condCodeOp ( ) ) ; else UpdateMI = BuildMI ( MF , MI . getDebugLoc ( ) , get ( isSub ? <STR_LIT> : <STR_LIT> ) , WBReg ) . addReg ( BaseReg ) . addReg ( OffReg ) . add ( predOps ( Pred ) ) . add ( condCodeOp ( ) ) ; break ;


<s> FUnpredCycles = FCycles + NotTakenBranchCost ; } unsigned TUnpredCost = Probability . scale ( TUnpredCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FUnpredCycles * ScalingUpFactor ) ; UnpredCost = TUnpredCost + FUnpredCost ; if ( Subtarget . isThumb2 ( ) && TCycles + FCycles > <NUM_LIT> ) { PredCost += ( ( TCycles + FCycles - <NUM_LIT> ) / <NUM_LIT> ) * ScalingUpFactor ; } } else { unsigned TUnpredCost = Probability . scale ( TCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FCycles * ScalingUpFactor ) ;


<s> bool <ISA_LIT>BaseInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TBB , unsigned TCycles , unsigned TExtra , MachineBasicBlock & FBB , unsigned FCycles , unsigned FExtra , BranchProbability Probability ) const { if ( ! TCycles ) return false ; const unsigned ScalingUpFactor = <NUM_LIT> ; unsigned PredCost = ( TCycles + FCycles + TExtra + FExtra ) * ScalingUpFactor ; unsigned UnpredCost ; if ( ! Subtarget . hasBranchPredictor ( ) ) {

unsigned NotTakenBranchCost = <NUM_LIT> ;


<s> case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) && Imm % <NUM_LIT> == <NUM_LIT> ; case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) && Imm % <NUM_LIT> == <NUM_LIT> ;


<s> return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ;


<s> return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> static inline bool isLowOverheadTerminatorOpcode ( int Opc ) {

return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ;


<s> bool isUnspillableTerminatorImpl ( const MachineInstr * MI ) const override {

return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ;


<s> switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;

CmpValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; }


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( Load1 -> getOperand ( <NUM_LIT> ) != Load2 -> getOperand ( <NUM_LIT> ) || Load1 -> getOperand ( <NUM_LIT> ) != Load2 -> getOperand ( <NUM_LIT> ) ) return false ; if ( Load1 -> getOperand ( <NUM_LIT> ) != Load2 -> getOperand ( <NUM_LIT> ) ) return false ; if ( isa < ConstantSDNode > ( Load1 -> getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( Load2 -> getOperand ( <NUM_LIT> ) ) ) { Offset1 = cast < ConstantSDNode > ( Load1 -> getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; Offset2 = cast < ConstantSDNode > ( Load2 -> getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; return true ; } return false ;


<s> } if ( Load1 -> getOperand ( <NUM_LIT> ) != Load2 -> getOperand ( <NUM_LIT> ) || Load1 -> getOperand ( <NUM_LIT> ) != Load2 -> getOperand ( <NUM_LIT> ) ) return false ; if ( Load1 -> getOperand ( <NUM_LIT> ) != Load2 -> getOperand ( <NUM_LIT> ) ) return false ; if ( isa < ConstantSDNode > ( Load1 -> getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( Load2 -> getOperand ( <NUM_LIT> ) ) ) { Offset1 = cast < ConstantSDNode > ( Load1 -> getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ;

Offset2 = cast < ConstantSDNode > ( Load2 -> getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ;


<s> bool <ISA_LIT>BaseInstrInfo :: ConvertToSetZeroFlag ( MachineInstr * MI , MachineInstr * CmpInstr ) const { if ( MI -> getParent ( ) != CmpInstr -> getParent ( ) ) return false ; MachineBasicBlock :: const_iterator I = CmpInstr , E = MI , B = MI -> getParent ( ) -> begin ( ) ; -- I ; for ( ; I != E ; -- I ) {


<s> MachineInstr * MemMI = NULL ; unsigned AddrMode = ( TSFlags & <STR_LIT> ) ; const TargetInstrDesc & TID = MI -> getDesc ( ) ; unsigned NumOps = TID . getNumOperands ( ) ; bool isLoad = ! TID . mayStore ( ) ; const MachineOperand & WB = isLoad ? MI -> getOperand ( <NUM_LIT> ) : MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & Base = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & Offset = MI -> getOperand ( NumOps - <NUM_LIT> ) ; unsigned WBReg = WB . getReg ( ) ; unsigned BaseReg = Base . getReg ( ) ; unsigned OffReg = Offset . getReg ( ) ; unsigned OffImm = MI -> getOperand ( NumOps - <NUM_LIT> ) . getImm ( ) ; <STR_LIT> Pred = ( <STR_LIT> ) MI -> getOperand ( NumOps - <NUM_LIT> ) . getImm ( ) ; switch ( AddrMode ) { default : assert ( false && <STR_LIT> ) ; return NULL ; case <STR_LIT> : { bool isSub = <STR_LIT> ( OffImm ) == <STR_LIT> ; unsigned Amt = <STR_LIT> ( OffImm ) ; if ( OffReg == <NUM_LIT> ) { if ( <STR_LIT> ( Amt ) == - <NUM_LIT> ) return NULL ; UpdateMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isSub ? <STR_LIT> : <STR_LIT> ) , WBReg ) . addReg ( BaseReg ) . addImm ( Amt ) . addImm ( Pred ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } else if ( Amt != <NUM_LIT> ) { <STR_LIT> ShOpc = <STR_LIT> ( OffImm ) ; unsigned SOOpc = <STR_LIT> ( ShOpc , Amt ) ; UpdateMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isSub ? <STR_LIT> : <STR_LIT> ) , WBReg ) . addReg ( BaseReg ) . addReg ( OffReg ) . addReg ( <NUM_LIT> ) . addImm ( SOOpc ) . addImm ( Pred ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } else UpdateMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isSub ? <STR_LIT> : <STR_LIT> ) , WBReg ) . addReg ( BaseReg ) . addReg ( OffReg ) . addImm ( Pred ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; break ; } case <STR_LIT> : { bool isSub = <STR_LIT> ( OffImm ) == <STR_LIT> ; unsigned Amt = <STR_LIT> ( OffImm ) ;

if ( OffReg == <NUM_LIT> ) UpdateMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isSub ? <STR_LIT> : <STR_LIT> ) , WBReg ) . addReg ( BaseReg ) . addImm ( Amt ) . addImm ( Pred ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ;


<s> unsigned PCLabelId = AFI -> createConstPoolEntryUId ( ) ; <ISA_LIT>ConstantPoolValue * NewCPV = <NUM_LIT> ; if ( ACPV -> isGlobalValue ( ) ) NewCPV = new <ISA_LIT>ConstantPoolValue ( ACPV -> getGV ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isExtSymbol ( ) ) NewCPV = new <ISA_LIT>ConstantPoolValue ( MF . getFunction ( ) -> getContext ( ) , ACPV -> getSymbol ( ) , PCLabelId , <NUM_LIT> ) ; else if ( ACPV -> isBlockAddress ( ) ) NewCPV = new <ISA_LIT>ConstantPoolValue ( ACPV -> getBlockAddress ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isLSDA ( ) ) NewCPV = new <ISA_LIT>ConstantPoolValue ( MF . getFunction ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ;

CPI = MCP -> getConstantPoolIndex ( NewCPV , MCPE . getAlignment ( ) ) ;


<s> break ; } case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : { switch ( Opc ) { case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned EntrySize = ( Opc == <STR_LIT> ) ? <NUM_LIT> : ( ( Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned NumOps = TID . getNumOperands ( ) ; MachineOperand JTOP = MI -> getOperand ( NumOps - ( TID . isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOP . getIndex ( ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; assert ( MJTI != <NUM_LIT> ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; assert ( JTI < JT . size ( ) ) ; unsigned InstSize = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned NumEntries = getNumJTEntries ( JT , JTI ) ; if ( Opc == <STR_LIT> && ( NumEntries & <NUM_LIT> ) ) ++ NumEntries ; return NumEntries * EntrySize + InstSize ; } default : return <NUM_LIT> ;


isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumT , MachineBasicBlock & FMBB , unsigned NumF ) const {


<s> MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; AddDefaultPred ( MIB . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <STR_LIT> ( <STR_LIT> ) ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; } break ; case <STR_LIT> : { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <STR_LIT> ( <STR_LIT> ) ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; break ; } default :


<s> if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) {


<s> case <STR_LIT> : AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <STR_LIT> ( <STR_LIT> ) ) . addMemOperand ( MMO ) ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; AddDefaultPred ( MIB . addMemOperand ( MMO ) ) ; } else { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <STR_LIT> ( <STR_LIT> ) ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ;


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , MFI . getObjectSize ( FI ) , Align ) ; if ( RC == <STR_LIT> || RC == <STR_LIT> || RC == <STR_LIT> ) RC = <STR_LIT> ; switch ( RC -> getID ( ) ) { case <STR_LIT> : AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; break ; case <STR_LIT> : AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <STR_LIT> ( <STR_LIT> ) ) . addMemOperand ( MMO ) ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ;

MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ;


<s> if ( ! MI . isMoveReg ( ) || ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) != MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; Dest = MI . getOperand ( <NUM_LIT> ) ;


<s> bool <ISA_LIT>BaseInstrInfo :: isCopyInstr ( const MachineInstr & MI , MachineOperand & Src , MachineOperand & Dest ) const {

if ( ! MI . isMoveReg ( ) || ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) != MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ;


<s> for ( MachineRegisterInfo :: use_iterator UI = MRI -> use_begin ( SrcReg ) , UE = MRI -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getParent ( ) != CmpInstr -> getParent ( ) ) continue ; MachineInstr * PotentialAND = & * UI ; if ( ! isSuitableForMask ( PotentialAND , SrcReg , CmpMask , true ) ) continue ; MI = PotentialAND ; break ; } if ( ! MI ) return false ; } } if ( MI -> getParent ( ) != CmpInstr -> getParent ( ) ) return false ; MachineBasicBlock :: const_iterator I = CmpInstr , E = MI , B = MI -> getParent ( ) -> begin ( ) ; if ( I == B ) return false ; -- I ; for ( ; I != E ; -- I ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( ! MO . isReg ( ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) return false ; } if ( I == B ) return false ; } switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool isSafe = false ; I = CmpInstr ; E = MI -> getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } <STR_LIT> CC = ( <STR_LIT> ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; switch ( CC ) { default : isSafe = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } }


<s> case <STR_LIT> : { unsigned NumRegs = MI -> getNumOperands ( ) - Desc . getNumOperands ( ) ; return ( NumRegs / <NUM_LIT> ) + ( NumRegs % <NUM_LIT> ) + <NUM_LIT> ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumRegs = MI -> getNumOperands ( ) - Desc . getNumOperands ( ) + <NUM_LIT> ; if ( Subtarget . isCortexA8 ( ) ) { if ( NumRegs < <NUM_LIT> ) return <NUM_LIT> ; int A8UOps = ( NumRegs / <NUM_LIT> ) ; if ( NumRegs % <NUM_LIT> ) ++ A8UOps ; return A8UOps ; } else if ( Subtarget . isCortexA9 ( ) ) { int A9UOps = ( NumRegs / <NUM_LIT> ) ; if ( ( NumRegs % <NUM_LIT> ) || ! MI -> hasOneMemOperand ( ) || ( * MI -> memoperands_begin ( ) ) -> getAlignment ( ) < <NUM_LIT> ) ++ A9UOps ; return A9UOps ; } else { return NumRegs ; } } }


<s> unsigned Reg = DefMO . getReg ( ) ; const MCInstrDesc * DefMCID = & DefMI -> getDesc ( ) ; const MCInstrDesc * UseMCID = & UseMI -> getDesc ( ) ; unsigned DefAdj = <NUM_LIT> ; if ( DefMI -> isBundle ( ) ) { DefMI = getBundledDefMI ( & getRegisterInfo ( ) , DefMI , Reg , DefIdx , DefAdj ) ; DefMCID = & DefMI -> getDesc ( ) ; } if ( DefMI -> isCopyLike ( ) || DefMI -> isInsertSubreg ( ) || DefMI -> isRegSequence ( ) || DefMI -> isImplicitDef ( ) ) { return <NUM_LIT> ; } unsigned UseAdj = <NUM_LIT> ; if ( UseMI -> isBundle ( ) ) { unsigned NewUseIdx ; const MachineInstr * NewUseMI = getBundledUseMI ( & getRegisterInfo ( ) , UseMI , Reg , NewUseIdx , UseAdj ) ; if ( ! NewUseMI ) return - <NUM_LIT> ; UseMI = NewUseMI ; UseIdx = NewUseIdx ; UseMCID = & UseMI -> getDesc ( ) ; } if ( Reg == <STR_LIT> ) { if ( DefMI -> getOpcode ( ) == <STR_LIT> ) { return Subtarget . isCortexA9 ( ) ? <NUM_LIT> : <NUM_LIT> ; } if ( UseMI -> isBranch ( ) ) return <NUM_LIT> ; unsigned Latency = getInstrLatency ( ItinData , DefMI ) ; if ( Latency > <NUM_LIT> && Subtarget . isThumb2 ( ) ) { const MachineFunction * MF = DefMI -> getParent ( ) -> getParent ( ) ;

if ( MF -> getFunction ( ) -> hasFnAttr ( Attribute :: OptimizeForSize ) ) -- Latency ;


<s> } if ( DefMI -> isCopyLike ( ) || DefMI -> isInsertSubreg ( ) || DefMI -> isRegSequence ( ) || DefMI -> isImplicitDef ( ) ) { return <NUM_LIT> ; } unsigned UseAdj = <NUM_LIT> ; if ( UseMI -> isBundle ( ) ) { unsigned NewUseIdx ; const MachineInstr * NewUseMI = getBundledUseMI ( & getRegisterInfo ( ) , UseMI , Reg , NewUseIdx , UseAdj ) ; if ( ! NewUseMI ) return - <NUM_LIT> ; UseMI = NewUseMI ; UseIdx = NewUseIdx ; UseMCID = & UseMI -> getDesc ( ) ; } if ( Reg == <STR_LIT> ) { if ( DefMI -> getOpcode ( ) == <STR_LIT> ) { return Subtarget . isCortexA9 ( ) ? <NUM_LIT> : <NUM_LIT> ; } if ( UseMI -> isBranch ( ) ) return <NUM_LIT> ; unsigned Latency = getInstrLatency ( ItinData , DefMI ) ; if ( Latency > <NUM_LIT> && Subtarget . isThumb2 ( ) ) { const MachineFunction * MF = DefMI -> getParent ( ) -> getParent ( ) ; if ( MF -> getFunction ( ) -> hasFnAttr ( Attribute :: OptimizeForSize ) ) -- Latency ;


<s> unsigned Reg = DefMI -> getOperand ( DefIdx ) . getReg ( ) ; if ( DepMI -> readsRegister ( Reg , & getRegisterInfo ( ) ) || ! isPredicated ( DepMI ) ) return <NUM_LIT> ;

return getInstrLatency ( ItinData , DefMI ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SmallVector < std :: pair < MachineOperand * , <STR_LIT> > , <NUM_LIT> > OperandsToUpdate ; bool isSafe = false ; I = CmpInstr ; E = CmpInstr -> getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } <STR_LIT> CC = ( <STR_LIT> ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; if ( Sub ) { <STR_LIT> NewCC = getSwappedCondition ( CC ) ; if ( NewCC == <STR_LIT> ) return false ; if ( SrcReg2 != <NUM_LIT> && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) OperandsToUpdate . push_back ( std :: make_pair ( & ( ( * I ) . getOperand ( IO - <NUM_LIT> ) ) , NewCC ) ) ; } else switch ( CC ) { default : isSafe = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } } }


<s> AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ;


<s> switch ( RC -> getSize ( ) / <NUM_LIT> ) { case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ;


<s> Create ( MF . getFunction ( ) . getContext ( ) , cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) , PCLabelId , <NUM_LIT> , ACPV -> getModifier ( ) ) ; else if ( ACPV -> isBlockAddress ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getBlockAddress ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isLSDA ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( & MF . getFunction ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isMachineBasicBlock ( ) ) NewCPV = <ISA_LIT>ConstantPoolMBB :: Create ( MF . getFunction ( ) . getContext ( ) , cast < <ISA_LIT>ConstantPoolMBB > ( ACPV ) -> getMBB ( ) , PCLabelId , <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; CPI = MCP -> getConstantPoolIndex ( NewCPV , MCPE . getAlignment ( ) ) ;


<s> else if ( ACPV -> isBlockAddress ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getBlockAddress ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isLSDA ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( & MF . getFunction ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isMachineBasicBlock ( ) ) NewCPV = <ISA_LIT>ConstantPoolMBB :: Create ( MF . getFunction ( ) . getContext ( ) , cast < <ISA_LIT>ConstantPoolMBB > ( ACPV ) -> getMBB ( ) , PCLabelId , <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; CPI = MCP -> getConstantPoolIndex ( NewCPV , MCPE . getAlignment ( ) ) ; return PCLabelId ;


<s> bool isThumb = Subtarget . isThumb ( ) ; unsigned FuncOp = isThumb ? <NUM_LIT> : <NUM_LIT> ; unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? <STR_LIT> : <STR_LIT> : isThumb ? Subtarget . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> : <STR_LIT> ;

MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ;


<s> unsigned LastInstrOpcode = RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> getOpcode ( ) ; auto SetCandidateCallInfo = [ & RepeatedSequenceLocs ] ( unsigned CallID , unsigned NumBytesForCall ) { for ( outliner :: Candidate & C : RepeatedSequenceLocs ) C . setCallInfo ( CallID , NumBytesForCall ) ; } ; auto Costs = std :: make_unique < OutlinerCosts > ( Subtarget ) ; unsigned FrameID = <NUM_LIT> ; unsigned NumBytesToCreateFrame = <NUM_LIT> ; if ( RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> isTerminator ( ) ) { FrameID = MachineOutlinerTailCall ; NumBytesToCreateFrame = Costs -> FrameTailCall ; SetCandidateCallInfo ( MachineOutlinerTailCall , Costs -> CallTailCall ) ; } else if ( LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> ) { FrameID = MachineOutlinerThunk ;

NumBytesToCreateFrame = Costs -> FrameThunk ;


<s> if ( ( MIFlags & <STR_LIT> ) == <STR_LIT> ) return outliner :: InstrType :: Illegal ; if ( MI . isTerminator ( ) ) { if ( isPredicated ( MI ) ) return outliner :: InstrType :: Illegal ; if ( MI . getParent ( ) -> succ_empty ( ) ) return outliner :: InstrType :: Legal ; return outliner :: InstrType :: Illegal ; } for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return outliner :: InstrType :: Illegal ; } if ( MI . readsRegister ( <STR_LIT> , TRI ) || MI . readsRegister ( <STR_LIT> , TRI ) ) return outliner :: InstrType :: Illegal ; if ( MI . isCall ( ) ) { auto UnknownCallOutlineType = outliner :: InstrType :: Illegal ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) UnknownCallOutlineType = outliner :: InstrType :: LegalTerminator ; return UnknownCallOutlineType ; } if ( MI . modifiesRegister ( <STR_LIT> , TRI ) || MI . modifiesRegister ( <STR_LIT> , TRI ) ) return outliner :: InstrType :: Illegal ; if ( MI . readsRegister ( <STR_LIT> , TRI ) || MI . modifiesRegister ( <STR_LIT> , TRI ) ) return outliner :: InstrType :: Illegal ; if ( MI . isPosition ( ) ) return outliner :: InstrType :: Illegal ; return outliner :: InstrType :: Legal ;


<s> Opc = isThumb ? Subtarget . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; if ( isThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; It = MBB . insert ( It , MIB ) ; return It ; } Opc = isThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder CallMIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) ; if ( isThumb ) CallMIB . add ( predOps ( <STR_LIT> ) ) ; CallMIB . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; It = MBB . insert ( It , CallMIB ) ;


<s> OutlinerCosts ( const <ISA_LIT>Subtarget & target ) : CallTailCall ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , FrameTailCall ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , CallThunk ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , FrameThunk ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SmallVector < std :: pair < MachineOperand * , <STR_LIT> > , <NUM_LIT> > OperandsToUpdate ; bool isSafe = false ; I = CmpInstr ; E = CmpInstr -> getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } <STR_LIT> CC = ( <STR_LIT> ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; if ( Sub ) { <STR_LIT> NewCC = getSwappedCondition ( CC ) ; if ( NewCC == <STR_LIT> ) return false ; if ( SrcReg2 != <NUM_LIT> && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) OperandsToUpdate . push_back ( std :: make_pair ( & ( ( * I ) . getOperand ( IO - <NUM_LIT> ) ) , NewCC ) ) ; } else switch ( CC ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } } } if ( ! isSafe ) { MachineBasicBlock * MBB = CmpInstr -> getParent ( ) ; for ( MachineBasicBlock :: succ_iterator SI = MBB -> succ_begin ( ) , SE = MBB -> succ_end ( ) ; SI != SE ; ++ SI ) if ( ( * SI ) -> isLiveIn ( <STR_LIT> ) ) return false ; } MI -> getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDef ( true ) ; CmpInstr -> eraseFromParent ( ) ; for ( unsigned i = <NUM_LIT> , e = OperandsToUpdate . size ( ) ; i < e ; i ++ ) OperandsToUpdate [ i ] . first -> setImm ( OperandsToUpdate [ i ] . second ) ;


<s> CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II ) const { if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2 ( ) ) return ( ScheduleHazardRecognizer * ) new <ISA_LIT>HazardRecognizer ( II , * this , getRegisterInfo ( ) , Subtarget ) ; return TargetInstrInfoImpl :: CreateTargetPostRAHazardRecognizer ( II ) ;


<s> CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II ) const { if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2 ( ) ) return ( ScheduleHazardRecognizer * ) new <ISA_LIT>HazardRecognizer ( II , * this , getRegisterInfo ( ) , Subtarget ) ;

return TargetInstrInfoImpl :: CreateTargetPostRAHazardRecognizer ( II ) ;


<s> if ( MI -> getOpcode ( ) == <STR_LIT> ) return getInlineAsmLength ( MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MAI ) ; if ( MI -> isLabel ( ) ) return <NUM_LIT> ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: PROLOG_LABEL : case TargetOpcode :: EH_LABEL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; } break ; } case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : { switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned EntrySize = ( Opc == <STR_LIT> ) ? <NUM_LIT> : ( ( Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned NumOps = TID . getNumOperands ( ) ; MachineOperand JTOP = MI -> getOperand ( NumOps - ( TID . isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOP . getIndex ( ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; assert ( MJTI != <NUM_LIT> ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; assert ( JTI < JT . size ( ) ) ; unsigned InstSize = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned NumEntries = getNumJTEntries ( JT , JTI ) ; if ( Opc == <STR_LIT> && ( NumEntries & <NUM_LIT> ) ) ++ NumEntries ; return NumEntries * EntrySize + InstSize ; } default : return <NUM_LIT> ; } }


<s> const TargetInstrDesc & UseTID = get ( UseNode -> getMachineOpcode ( ) ) ; const MachineSDNode * DefMN = dyn_cast < MachineSDNode > ( DefNode ) ; unsigned DefAlign = ! DefMN -> memoperands_empty ( ) ? ( * DefMN -> memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; const MachineSDNode * UseMN = dyn_cast < MachineSDNode > ( UseNode ) ; unsigned UseAlign = ! UseMN -> memoperands_empty ( ) ? ( * UseMN -> memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; int Latency = getOperandLatency ( ItinData , DefTID , DefIdx , DefAlign , UseTID , UseIdx , UseAlign ) ; if ( Latency > <NUM_LIT> && ( Subtarget . isCortexA8 ( ) || Subtarget . isCortexA9 ( ) ) ) { switch ( DefTID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned ShOpVal = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned ShImm = <STR_LIT> ( ShOpVal ) ; if ( ShImm == <NUM_LIT> || ( ShImm == <NUM_LIT> && <STR_LIT> ( ShOpVal ) == <STR_LIT> ) ) -- Latency ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned ShAmt = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( ShAmt == <NUM_LIT> || ShAmt == <NUM_LIT> ) -- Latency ; break ;


<s> const InstrItineraryData * II = & static_cast < const <ISA_LIT>Subtarget * > ( STI ) -> getInstrItineraryData ( ) ; return new ScoreboardHazardRecognizer ( II , DAG , <STR_LIT> ) ; } return TargetInstrInfo :: CreateTargetHazardRecognizer ( STI , DAG ) ;


<s> unsigned <ISA_LIT>BaseInstrInfo :: GetInstSizeInBytes ( const MachineInstr * MI ) const { const MachineBasicBlock & MBB = * MI -> getParent ( ) ; const MachineFunction * MF = MBB . getParent ( ) ; const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . getSize ( ) ) return MCID . getSize ( ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) return getInlineAsmLength ( MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MAI ) ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { default : return <NUM_LIT> ; case TargetOpcode :: BUNDLE : return getInstBundleLength ( MI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned EntrySize = ( Opc == <STR_LIT> ) ? <NUM_LIT> : ( ( Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned NumOps = MCID . getNumOperands ( ) ; MachineOperand JTOP = MI -> getOperand ( NumOps - ( MI -> isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOP . getIndex ( ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; assert ( MJTI != nullptr ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; assert ( JTI < JT . size ( ) ) ; unsigned InstSize = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned NumEntries = JT [ JTI ] . MBBs . size ( ) ; if ( Opc == <STR_LIT> && ( NumEntries & <NUM_LIT> ) ) ++ NumEntries ; return NumEntries * EntrySize + InstSize ;


<s> MachineOperand LDWb ( MI -> getOperand ( <NUM_LIT> ) ) ; LDM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ) ) . add ( LDWb ) ; } else { LDM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) ; } if ( isThumb1 || ! MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) { MachineOperand STWb ( MI -> getOperand ( <NUM_LIT> ) ) ; STM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ) ) . add ( STWb ) ; } else { STM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) ; } MachineOperand LDBase ( MI -> getOperand ( <NUM_LIT> ) ) ; LDM . add ( LDBase ) . add ( predOps ( <STR_LIT> ) ) ; MachineOperand STBase ( MI -> getOperand ( <NUM_LIT> ) ) ; STM . add ( STBase ) . add ( predOps ( <STR_LIT> ) ) ; const TargetRegisterInfo & TRI = getRegisterInfo ( ) ;

SmallVector < unsigned , <NUM_LIT> > ScratchRegs ;