<s> uint64_t SrcOff = <NUM_LIT> , DstOff = <NUM_LIT> ; while ( EmittedNumMemOps < NumMemOps ) { for ( i = <NUM_LIT> ; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps ; ++ i ) { Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , dl , <STR_LIT> ) ) , SrcPtrInfo . getWithOffset ( SrcOff ) , isVolatile , false , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; SrcOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , makeArrayRef ( TFOps , i ) ) ; for ( i = <NUM_LIT> ; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps ; ++ i ) { TFOps [ i ] = DAG . getStore ( Chain , dl , Loads [ i ] , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Dst , DAG . getConstant ( DstOff , dl , <STR_LIT> ) ) , DstPtrInfo . getWithOffset ( DstOff ) , isVolatile , false , <NUM_LIT> ) ; DstOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , makeArrayRef ( TFOps , i ) ) ; EmittedNumMemOps += i ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; unsigned BytesLeftSave = BytesLeft ; i = <NUM_LIT> ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , dl , <STR_LIT> ) ) , SrcPtrInfo . getWithOffset ( SrcOff ) , false , false , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; ++ i ; SrcOff += VTSize ;


<s> enum { ALIGN1 = <NUM_LIT> , ALIGN4 , ALIGN8 } AlignVariant ; if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN8 ; else if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN4 ; else AlignVariant = ALIGN1 ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; if ( AEABILibcall == AEABI_MEMCLR ) { Entry . Node = Size ; Args . push_back ( Entry ) ; } else if ( AEABILibcall == AEABI_MEMSET ) { Entry . Node = Size ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else if ( Src . getValueType ( ) . bitsLT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = false ; Args . push_back ( Entry ) ; } else { Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; } char const * FunctionNames [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , {


<s> if ( ConstantSDNode * ConstantSrc = dyn_cast < ConstantSDNode > ( Src ) ) if ( ConstantSrc -> getZExtValue ( ) == <NUM_LIT> ) AEABILibcall = AEABI_MEMCLR ; break ; default : return SDValue ( ) ; } enum { ALIGN1 = <NUM_LIT> , ALIGN4 , ALIGN8 } AlignVariant ; if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN8 ; else if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN4 ; else AlignVariant = ALIGN1 ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; if ( AEABILibcall == AEABI_MEMCLR ) { Entry . Node = Size ; Args . push_back ( Entry ) ; } else if ( AEABILibcall == AEABI_MEMSET ) { Entry . Node = Size ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else if ( Src . getValueType ( ) . bitsLT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = false ; Args . push_back ( Entry ) ; } else { Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; } char const * FunctionNames [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI -> getLibcallCallingConv ( LC ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( FunctionNames [ AEABILibcall ] [ AlignVariant ] , TLI -> getPointerTy ( DAG . getDataLayout ( ) ) ) , std :: move ( Args ) ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI -> LowerCallTo ( CLI ) ; return CallResult . second ;


<s> Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ;

TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ;


<s> TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getTargetData ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ;


<s> Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ;


<s> TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getTargetData ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ;


<s> Entry . isSExt = true ; Args . push_back ( Entry ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; return CallResult . second ;


<s> if ( ! ConstantSize ) return SDValue ( ) ; uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; if ( ! AlwaysInline && SizeVal > Subtarget -> getMaxInlineSizeThreshold ( ) ) return SDValue ( ) ; unsigned BytesLeft = SizeVal & <NUM_LIT> ; unsigned NumMemOps = SizeVal >> <NUM_LIT> ; unsigned EmittedNumMemOps = <NUM_LIT> ; EVT VT = <STR_LIT> ; unsigned VTSize = <NUM_LIT> ; unsigned i = <NUM_LIT> ; const unsigned MAX_LOADS_IN_LDM = <NUM_LIT> ; SDValue TFOps [ MAX_LOADS_IN_LDM ] ; SDValue Loads [ MAX_LOADS_IN_LDM ] ; uint64_t SrcOff = <NUM_LIT> , DstOff = <NUM_LIT> ; while ( EmittedNumMemOps < NumMemOps ) { for ( i = <NUM_LIT> ; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps ; ++ i ) { Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , <STR_LIT> ) ) , SrcPtrInfo . getWithOffset ( SrcOff ) , isVolatile , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; SrcOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & TFOps [ <NUM_LIT> ] , i ) ; for ( i = <NUM_LIT> ; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps ; ++ i ) { TFOps [ i ] = DAG . getStore ( Chain , dl , Loads [ i ] , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Dst , DAG . getConstant ( DstOff , <STR_LIT> ) ) , DstPtrInfo . getWithOffset ( DstOff ) , isVolatile , false , <NUM_LIT> ) ; DstOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & TFOps [ <NUM_LIT> ] , i ) ; EmittedNumMemOps += i ; }

if ( BytesLeft == <NUM_LIT> ) return Chain ;


<s> ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( ! ConstantSize ) return SDValue ( ) ; uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; if ( ! AlwaysInline && SizeVal > Subtarget -> getMaxInlineSizeThreshold ( ) ) return SDValue ( ) ; unsigned BytesLeft = SizeVal & <NUM_LIT> ; unsigned NumMemOps = SizeVal >> <NUM_LIT> ; unsigned EmittedNumMemOps = <NUM_LIT> ; EVT VT = <STR_LIT> ; unsigned VTSize = <NUM_LIT> ; unsigned i = <NUM_LIT> ; const unsigned MAX_LOADS_IN_LDM = <NUM_LIT> ; SDValue TFOps [ MAX_LOADS_IN_LDM ] ; SDValue Loads [ MAX_LOADS_IN_LDM ] ; uint64_t SrcOff = <NUM_LIT> , DstOff = <NUM_LIT> ; while ( EmittedNumMemOps < NumMemOps ) { for ( i = <NUM_LIT> ; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps ; ++ i ) { Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , <STR_LIT> ) ) , SrcPtrInfo . getWithOffset ( SrcOff ) , isVolatile , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; SrcOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & TFOps [ <NUM_LIT> ] , i ) ; for ( i = <NUM_LIT> ; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps ; ++ i ) { TFOps [ i ] = DAG . getStore ( Chain , dl , Loads [ i ] , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Dst , DAG . getConstant ( DstOff , <STR_LIT> ) ) , DstPtrInfo . getWithOffset ( DstOff ) , isVolatile , false , <NUM_LIT> ) ; DstOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & TFOps [ <NUM_LIT> ] , i ) ;


<s> ALIGN1 = <NUM_LIT> , ALIGN4 , ALIGN8 } AlignVariant ; if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN8 ; else if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN4 ; else AlignVariant = ALIGN1 ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; if ( AEABILibcall == AEABI_MEMCLR ) { Entry . Node = Size ; Args . push_back ( Entry ) ; } else if ( AEABILibcall == AEABI_MEMSET ) { Entry . Node = Size ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else if ( Src . getValueType ( ) . bitsLT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = false ; Args . push_back ( Entry ) ; } else {


<s> SDValue Loads [ <NUM_LIT> ] ; uint64_t SrcOff = <NUM_LIT> , DstOff = <NUM_LIT> ; unsigned NumMEMCPYs = ( NumMemOps + MaxLoadsInLDM - <NUM_LIT> ) / MaxLoadsInLDM ; if ( NumMEMCPYs > <NUM_LIT> && DAG . getMachineFunction ( ) . getFunction ( ) -> optForMinSize ( ) ) { return SDValue ( ) ; } SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I != NumMEMCPYs ; ++ I ) { unsigned NextEmittedNumMemOps = NumMemOps * ( I + <NUM_LIT> ) / NumMEMCPYs ; unsigned NumRegs = NextEmittedNumMemOps - EmittedNumMemOps ; Dst = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Dst , Src , DAG . getConstant ( NumRegs , dl , <STR_LIT> ) ) ; Src = Dst . getValue ( <NUM_LIT> ) ; Chain = Dst . getValue ( <NUM_LIT> ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( NumRegs * VTSize ) ; SrcPtrInfo = SrcPtrInfo . getWithOffset ( NumRegs * VTSize ) ; EmittedNumMemOps = NextEmittedNumMemOps ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; unsigned BytesLeftSave = BytesLeft ; i = <NUM_LIT> ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , dl , <STR_LIT> ) ) , SrcPtrInfo . getWithOffset ( SrcOff ) , false , false , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; ++ i ; SrcOff += VTSize ; BytesLeft -= VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , makeArrayRef ( TFOps , i ) ) ; i = <NUM_LIT> ; BytesLeft = BytesLeftSave ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; }

TFOps [ i ] = DAG . getStore ( Chain , dl , Loads [ i ] , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Dst , DAG . getConstant ( DstOff , dl , <STR_LIT> ) ) , DstPtrInfo . getWithOffset ( DstOff ) , false , false , <NUM_LIT> ) ;


<s> unsigned NumRegs = NextEmittedNumMemOps - EmittedNumMemOps ; Dst = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Dst , Src , DAG . getConstant ( NumRegs , dl , <STR_LIT> ) ) ; Src = Dst . getValue ( <NUM_LIT> ) ; Chain = Dst . getValue ( <NUM_LIT> ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( NumRegs * VTSize ) ; SrcPtrInfo = SrcPtrInfo . getWithOffset ( NumRegs * VTSize ) ; EmittedNumMemOps = NextEmittedNumMemOps ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; unsigned BytesLeftSave = BytesLeft ; i = <NUM_LIT> ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , dl , <STR_LIT> ) ) , SrcPtrInfo . getWithOffset ( SrcOff ) , false , false , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; ++ i ; SrcOff += VTSize ; BytesLeft -= VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , makeArrayRef ( TFOps , i ) ) ; i = <NUM_LIT> ; BytesLeft = BytesLeftSave ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) {


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { if ( ! Subtarget -> isAAPCS_ABI ( ) || Subtarget -> isTargetDarwin ( ) ) return SDValue ( ) ; const <ISA_LIT>TargetLowering & TLI = * static_cast < const <ISA_LIT>TargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ;

Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ;


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , DebugLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { if ( ! Subtarget -> isAAPCS_ABI ( ) || Subtarget -> isTargetDarwin ( ) ) return SDValue ( ) ; const <ISA_LIT>TargetLowering & TLI = * static_cast < const <ISA_LIT>TargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; unsigned AS = DstPtrInfo . getAddrSpace ( ) ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) , AS ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ;

else Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ;


<s> if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ;


<s> enum { AEABI_MEMCPY = <NUM_LIT> , AEABI_MEMMOVE , AEABI_MEMSET , AEABI_MEMCLR } AEABILibcall ; switch ( LC ) { case RTLIB :: MEMCPY : AEABILibcall = AEABI_MEMCPY ; break ; case RTLIB :: MEMMOVE : AEABILibcall = AEABI_MEMMOVE ; break ; case RTLIB :: MEMSET : AEABILibcall = AEABI_MEMSET ; if ( ConstantSDNode * ConstantSrc = dyn_cast < ConstantSDNode > ( Src ) ) if ( ConstantSrc -> getZExtValue ( ) == <NUM_LIT> ) AEABILibcall = AEABI_MEMCLR ; break ; default : return SDValue ( ) ; } enum { ALIGN1 = <NUM_LIT> , ALIGN4 , ALIGN8 } AlignVariant ; if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN8 ; else if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN4 ; else AlignVariant = ALIGN1 ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; if ( AEABILibcall == AEABI_MEMCLR ) { Entry . Node = Size ; Args . push_back ( Entry ) ; } else if ( AEABILibcall == AEABI_MEMSET ) { Entry . Node = Size ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else if ( Src . getValueType ( ) . bitsLT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . IsSExt = false ; Args . push_back ( Entry ) ; } else { Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; } char const * FunctionNames [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT>


<s> SDValue Loads [ <NUM_LIT> ] ; uint64_t SrcOff = <NUM_LIT> , DstOff = <NUM_LIT> ; unsigned NumMEMCPYs = ( NumMemOps + MaxLoadsInLDM - <NUM_LIT> ) / MaxLoadsInLDM ; if ( NumMEMCPYs > <NUM_LIT> && DAG . getMachineFunction ( ) . getFunction ( ) . optForMinSize ( ) ) { return SDValue ( ) ; } SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I != NumMEMCPYs ; ++ I ) { unsigned NextEmittedNumMemOps = NumMemOps * ( I + <NUM_LIT> ) / NumMEMCPYs ; unsigned NumRegs = NextEmittedNumMemOps - EmittedNumMemOps ; Dst = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Dst , Src , DAG . getConstant ( NumRegs , dl , <STR_LIT> ) ) ; Src = Dst . getValue ( <NUM_LIT> ) ; Chain = Dst . getValue ( <NUM_LIT> ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( NumRegs * VTSize ) ; SrcPtrInfo = SrcPtrInfo . getWithOffset ( NumRegs * VTSize ) ; EmittedNumMemOps = NextEmittedNumMemOps ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; auto getRemainingValueType = [ ] ( unsigned BytesLeft ) { return ( BytesLeft >= <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; } ; auto getRemainingSize = [ ] ( unsigned BytesLeft ) { return ( BytesLeft >= <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ;


<s> Dst = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Dst , Src , DAG . getConstant ( NumRegs , dl , <STR_LIT> ) ) ; Src = Dst . getValue ( <NUM_LIT> ) ; Chain = Dst . getValue ( <NUM_LIT> ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( NumRegs * VTSize ) ; SrcPtrInfo = SrcPtrInfo . getWithOffset ( NumRegs * VTSize ) ; EmittedNumMemOps = NextEmittedNumMemOps ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; auto getRemainingValueType = [ ] ( unsigned BytesLeft ) { return ( BytesLeft >= <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; } ; auto getRemainingSize = [ ] ( unsigned BytesLeft ) { return ( BytesLeft >= <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; } ; unsigned BytesLeftSave = BytesLeft ; i = <NUM_LIT> ; while ( BytesLeft ) { VT = getRemainingValueType ( BytesLeft ) ; VTSize = getRemainingSize ( BytesLeft ) ; Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , dl , <STR_LIT> ) ) , SrcPtrInfo . getWithOffset ( SrcOff ) ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; ++ i ; SrcOff += VTSize ; BytesLeft -= VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , makeArrayRef ( TFOps , i ) ) ; i = <NUM_LIT> ; BytesLeft = BytesLeftSave ; while ( BytesLeft ) { VT = getRemainingValueType ( BytesLeft ) ; VTSize = getRemainingSize ( BytesLeft ) ; TFOps [ i ] = DAG . getStore ( Chain , dl , Loads [ i ] , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Dst , DAG . getConstant ( DstOff , dl , <STR_LIT> ) ) , DstPtrInfo . getWithOffset ( DstOff ) ) ; ++ i ; DstOff += VTSize ;


<s> return EmitSpecializedLibcall ( DAG , dl , Chain , Dst , Src , Size , Align , RTLIB :: MEMMOVE ) ;


<s> const GlobalValue * GV = cast < GlobalValue > ( M -> getNamedValue ( ThunkIt -> Name ) ) ; MachineInstr * BL = isThumb ? BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( IndirectCall . getOperand ( <NUM_LIT> ) . getImm ( ) ) . addReg ( IndirectCall . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addGlobalAddress ( GV ) : BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addGlobalAddress ( GV ) ; int ImpLROpIdx = - <NUM_LIT> ; int ImpSPOpIdx = - <NUM_LIT> ; for ( unsigned OpIdx = BL -> getNumExplicitOperands ( ) ; OpIdx < BL -> getNumOperands ( ) ; OpIdx ++ ) { MachineOperand Op = BL -> getOperand ( OpIdx ) ; if ( ! Op . isReg ( ) ) continue ; if ( Op . getReg ( ) == <STR_LIT> && Op . isDef ( ) ) ImpLROpIdx = OpIdx ; if ( Op . getReg ( ) == <STR_LIT> && ! Op . isDef ( ) ) ImpSPOpIdx = OpIdx ; } assert ( ImpLROpIdx != - <NUM_LIT> ) ; assert ( ImpSPOpIdx != - <NUM_LIT> ) ; int FirstOpIdxToRemove = std :: max ( ImpLROpIdx , ImpSPOpIdx ) ; int SecondOpIdxToRemove = std :: min ( ImpLROpIdx , ImpSPOpIdx ) ; BL -> RemoveOperand ( FirstOpIdxToRemove ) ; BL -> RemoveOperand ( SecondOpIdxToRemove ) ; BL -> copyImplicitOps ( MF , IndirectCall ) ; MF . moveCallSiteInfo ( & IndirectCall , BL ) ; BL -> addOperand ( MachineOperand :: CreateReg ( Reg , false , true , RegIsKilled ) ) ; MBB . erase ( MBBI ) ;


<s> void SLSBLRThunkInserter :: insertThunks ( MachineModuleInfo & MMI ) { for ( auto T : SLSBLRThunks ) createThunkFunction ( MMI , T . Name ) ;


<s> return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hardenSlsBlr ( ) ;


<s> <ISA_LIT>IndirectThunks ( ) : MachineFunctionPass ( ID ) {


<s> <ISA_LIT>SLSHardening ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>SLSHardeningPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> } ) ; assert ( ThunkIt != std :: end ( SLSBLRThunks ) ) ; Module * M = MF . getFunction ( ) . getParent ( ) ; const GlobalValue * GV = cast < GlobalValue > ( M -> getNamedValue ( ThunkIt -> Name ) ) ; MachineInstr * BL = isThumb ? BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( IndirectCall . getOperand ( <NUM_LIT> ) . getImm ( ) ) . addReg ( IndirectCall . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addGlobalAddress ( GV ) : BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addGlobalAddress ( GV ) ; int ImpLROpIdx = - <NUM_LIT> ; int ImpSPOpIdx = - <NUM_LIT> ; for ( unsigned OpIdx = BL -> getNumExplicitOperands ( ) ; OpIdx < BL -> getNumOperands ( ) ; OpIdx ++ ) { MachineOperand Op = BL -> getOperand ( OpIdx ) ; if ( ! Op . isReg ( ) ) continue ; if ( Op . getReg ( ) == <STR_LIT> && Op . isDef ( ) ) ImpLROpIdx = OpIdx ; if ( Op . getReg ( ) == <STR_LIT> && ! Op . isDef ( ) ) ImpSPOpIdx = OpIdx ; } assert ( ImpLROpIdx != - <NUM_LIT> ) ; assert ( ImpSPOpIdx != - <NUM_LIT> ) ; int FirstOpIdxToRemove = std :: max ( ImpLROpIdx , ImpSPOpIdx ) ; int SecondOpIdxToRemove = std :: min ( ImpLROpIdx , ImpSPOpIdx ) ; BL -> removeOperand ( FirstOpIdxToRemove ) ;

BL -> removeOperand ( SecondOpIdxToRemove ) ;


<s> return new <ISA_LIT>IndirectThunks ( ) ;


<s> return new <ISA_LIT>SLSHardening ( ) ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override {

MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> const char * getThunkPrefix ( ) { return SLSBLRNamePrefix ;


<s> MachineBasicBlock :: iterator NextMBBI ; for ( ; MBBI != E ; MBBI = NextMBBI ) { MachineInstr & MI = * MBBI ; NextMBBI = std :: next ( MBBI ) ; if ( isIndirectCall ( MI ) && ! MI . isReturn ( ) ) { ConvertIndirectCallToIndirectJump ( MBB , MBBI ) ; Modified = true ; } } return Modified ;


<s> MachineBasicBlock :: iterator NextMBBI ; for ( ; MBBI != E ; MBBI = NextMBBI ) { MachineInstr & MI = * MBBI ; NextMBBI = std :: next ( MBBI ) ; if ( isIndirectControlFlowNotComingBack ( MI ) ) {


<s> ( std :: get < ThunkInserterT > ( ThunkInserters ) . init ( M ) , <NUM_LIT> ) ... } ;


<s> assert ( std :: prev ( MBBI ) -> isTerminator ( ) && <STR_LIT> ) ; const TargetInstrInfo * TII = ST -> getInstrInfo ( ) ; assert ( ST -> hasDataBarrier ( ) || ST -> hasSB ( ) ) ; bool ProduceSB = ST -> hasSB ( ) && ! AlwaysUseISBDSB ; unsigned BarrierOpc = ProduceSB ? ( ST -> isThumb ( ) ? <STR_LIT> : <STR_LIT> ) : ( ST -> isThumb ( ) ? <STR_LIT> : <STR_LIT> ) ;

if ( MBBI == MBB . end ( ) || ! isSpeculationBarrierEndBBOpcode ( MBBI -> getOpcode ( ) ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( BarrierOpc ) ) ;


<s> void SLSBLRThunkInserter :: insertThunks ( MachineModuleInfo & MMI ) { for ( auto T : SLSBLRThunks ) createThunkFunction ( MMI , T . Name , ComdatThunks ) ;


<s> bool mayUseThunk ( const MachineFunction & MF ) { ComdatThunks &= ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hardenSlsNoComdat ( ) ;

return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hardenSlsBlr ( ) ;


<s> Register ThunkReg = ThunkIt -> Reg ; bool isThumb = ThunkIt -> isThumb ; const TargetInstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; MachineBasicBlock * Entry = & MF . front ( ) ; Entry -> clear ( ) ; Entry -> addLiveIn ( ThunkReg ) ;

if ( isThumb ) BuildMI ( Entry , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( ThunkReg ) . add ( predOps ( <STR_LIT> ) ) ;


<s> assert ( MF . getName ( ) . startswith ( getThunkPrefix ( ) ) ) ; auto ThunkIt = llvm :: find_if ( SLSBLRThunks , [ & MF ] ( auto T ) { return T . Name == MF . getName ( ) ; } ) ; assert ( ThunkIt != std :: end ( SLSBLRThunks ) ) ; Register ThunkReg = ThunkIt -> Reg ; bool isThumb = ThunkIt -> isThumb ; const TargetInstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; MachineBasicBlock * Entry = & MF . front ( ) ;


<s> bool <ISA_LIT>IndirectThunks :: runOnMachineFunction ( MachineFunction & MF ) {

LLVM_DEBUG ( dbgs ( ) << getPassName ( ) << '\n' ) ;


<s> static bool runTIs ( MachineModuleInfo & MMI , MachineFunction & MF , std :: tuple < ThunkInserterT ... > & ThunkInserters ) { bool Modified = false ;

( void ) std :: initializer_list < int > {


<s> bool Modified = false ; ( void ) std :: initializer_list < int > {

Modified |= std :: get < ThunkInserterT > ( ThunkInserters ) . run ( MMI , MF ) ... } ;


<s> bool allowsUnalignedMem ( ) const { return ! StrictAlign ;


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const override { return FrameLowering . get ( ) ;


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ;


<s> const InstrItineraryData * getInstrItineraryData ( ) const override {


<s> const <ISA_LIT>BaseRegisterInfo * getRegisterInfo ( ) const override {

return & InstrInfo -> getRegisterInfo ( ) ;


<s> return & InstrInfo -> getRegisterInfo ( ) ;


<s> const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const override { return & TSInfo ;


<s> bool isR9Reserved ( ) const { return isTargetMachO ( ) ? ( ReserveR9 || ! HasV6Ops ) : ReserveR9 ;


<s> return isTargetMachO ( ) ? ( ReserveR9 || ! HasV6Ops ) : ReserveR9 ;


<s> bool isTargetAndroid ( ) const { return TargetTriple . isAndroid ( ) ;


<s> return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || isTargetAndroid ( ) ) && ! isTargetDarwin ( ) && ! isTargetWindows ( ) ;


<s> bool isTargetHardFloat ( ) const { return TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || isTargetWindows ( ) || isAAPCS16_ABI ( ) ;


<s> return TargetTriple . isOSNetBSD ( ) ;


<s> return TargetTriple . isWatchOS ( ) ;


<s> bool useNEONForSinglePrecisionFP ( ) const {

return hasNEON ( ) && UseNEONForSinglePrecisionFP ;


<s> bool useSjLjEH ( ) const { return UseSjLjEH ;


<s> bool <ISA_LIT>Subtarget :: enablePostMachineScheduler ( ) const { return ( ! isThumb ( ) || hasThumb2 ( ) ) ;


<s> HasThumb2 = false ; No<ISA_LIT> = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ;


<s> HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; HasCRC = false ; HasZeroCycleZeroing = false ; AllowsUnalignedMem = false ; Thumb2DSP = false ;


<s> case Triple :: EABI : case Triple :: EABIHF : case Triple :: GNUEABI : case Triple :: GNUEABIHF : TargetABI = <ISA_LIT>_ABI_AAPCS ; break ; default : if ( ( isTargetIOS ( ) && isMClass ( ) ) || ( TargetTriple . isOSBinFormatMachO ( ) && TargetTriple . getOS ( ) == Triple :: UnknownOS ) ) TargetABI = <ISA_LIT>_ABI_AAPCS ; else TargetABI = <ISA_LIT>_ABI_APCS ; break ; } } if ( isTargetWindows ( ) ) { TargetABI = <ISA_LIT>_ABI_AAPCS ; No<ISA_LIT> = true ; } if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) ) stackAlignment = <NUM_LIT> ; UseMovt = hasV6T2Ops ( ) && ArmUseMOVT ; if ( isTargetMachO ( ) ) { IsR9Reserved = ReserveR9 | ! HasV6Ops ; SupportsTailCall = ! isTargetIOS ( ) || ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } else { IsR9Reserved = ReserveR9 ; SupportsTailCall = ! isThumb1Only ( ) ;


<s> bool allowPositionIndependentMovt ( ) const {

return isROPI ( ) || ! isTargetELF ( ) ;


<s> return isROPI ( ) || ! isTargetELF ( ) ;


<s> bool cheapPredicableCPSRDef ( ) const {


<s> bool cheapPredicableCPSRDef ( ) const { return CheapPredicableCPSRDef ;


<s> bool checkVLDnAccessAlignment ( ) const {


<s> bool disablePostRAScheduler ( ) const {


<s> bool expandMLx ( ) const { return ExpandMLx ;


<s> bool genExecuteOnly ( ) const { return GenExecuteOnly ;


<s> unsigned getMaxInterleaveFactor ( ) const { return MaxInterleaveFactor ;


<s> unsigned getMVEVectorCostFactor ( ) const {


<s> int getPreISelOperandLatencyAdjustment ( ) const {


<s> if ( isThumb ( ) ) return <STR_LIT> ; if ( hasV4TOps ( ) ) return <STR_LIT> ;


<s> Align getStackAlignment ( ) const { return stackAlignment ;


<s> bool has8MSecExt ( ) const { return Has8MSecExt ;


<s> bool hasAES ( ) const { return HasAES ;


<s> bool hasBaseDSP ( ) const { if ( isThumb ( ) ) return hasDSP ( ) ; else return hasV5TEOps ( ) ;


<s> bool hasDivideInThumbMode ( ) const { return HasHardwareDivideInThumb ;


<s> bool hasFP<ISA_LIT>v8Base ( ) const {


<s> bool hasFusion ( ) const { return hasFuseAES ( ) || hasFuseLiterals ( ) ;


<s> bool hasMuxedUnits ( ) const { return HasMuxedUnits ;


<s> bool hasMVEIntegerOps ( ) const { return HasMVEIntegerOps ;


<s> bool hasRetAddrStack ( ) const { return HasRetAddrStack ;


<s> bool hasSB ( ) const { return HasSB ;


<s> bool hasSlowLoadDSubregister ( ) const {


<s> bool hasV7Clrex ( ) const { return HasV7Clrex ;


<s> bool hasV8_1MMainlineOps ( ) const {


<s> bool hasV8_4aOps ( ) const { return HasV8_4aOps ;


<s> bool hasV8_5aOps ( ) const { return HasV8_5aOps ;


<s> bool hasVFP2Base ( ) const { return HasVFPv2SP ;


<s> bool hasVFP3Base ( ) const { return HasVFPv3D16SP ;


<s> bool hasVFP4Base ( ) const { return HasVFPv4D16SP ;


<s> bool isCortexM3 ( ) const { return <ISA_LIT>ProcFamily == CortexM3 ;


<s> return <ISA_LIT>ProcFamily == CortexM3 ;


<s> bool isProfitableToUnpredicate ( ) const { return IsProfitableToUnpredicate ;


<s> bool isProfitableToUnpredicate ( ) const {


<s> bool isReadTPHard ( ) const { return ReadTPHard ;


<s> bool isTargetEHABICompatible ( ) const {

return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF || isTargetAndroid ( ) ) && ! isTargetDarwin ( ) && ! isTargetWindows ( ) ;


<s> return ( TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF ) && ! isTargetDarwin ( ) && ! isTargetWindows ( ) ;


<s> return TargetTriple . isWatchABI ( ) ;


<s> bool nonpipelinedVFP ( ) const { return NonpipelinedVFP ;


<s> bool preferISHSTBarriers ( ) const { return PreferISHST ;


<s> bool useAA ( ) const override { return true ;


<s> bool allowsUnalignedMem ( ) const { return AllowsUnalignedMem ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , TargetMachine & TM , bool IsLittle , const TargetOptions & Options ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , <ISA_LIT>ProcClass ( None ) , stackAlignment ( <NUM_LIT> ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( Options ) , TargetABI ( <ISA_LIT>_ABI_UNKNOWN ) , DL ( computeDataLayout ( initializeSubtargetDependencies ( CPU , FS ) ) ) , TSInfo ( DL ) , JITInfo ( ) , InstrInfo ( isThumb1Only ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new <ISA_LIT>InstrInfo ( * this ) : ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM ) , FrameLowering ( ! isThumb1Only ( ) ? new <ISA_LIT>FrameLowering ( * this ) : ( <ISA_LIT>FrameLowering * ) new Thumb1FrameLowering ( * this ) ) {


<s> bool avoidMOVsShifterOperand ( ) const { return AvoidMOVsShifterOperand ;


<s> if ( ST . isThumb ( ) ) Ret += <STR_LIT> ; if ( ! ST . isAPCS_ABI ( ) ) Ret += <STR_LIT> ; if ( ST . isAPCS_ABI ( ) ) Ret += <STR_LIT> ; if ( ST . isAPCS_ABI ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ST . isThumb ( ) || ST . isAPCS_ABI ( ) ) Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( ST . isTargetNaCl ( ) ) Ret += <STR_LIT> ; else if ( ST . isAAPCS_ABI ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ;


<s> return hasAnyDataBarrier ( ) && ! isThumb1Only ( ) ;


<s> bool <ISA_LIT>Subtarget :: enablePostMachineScheduler ( ) const {


<s> Mode = TargetSubtargetInfo :: ANTIDEP_NONE ;

return PostRAScheduler && OptLevel >= CodeGenOpt :: Default ;


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const { return FrameLowering . get ( ) ;


<s> const InstrItineraryData & getInstrItineraryData ( ) const { return InstrItins ;


<s> return SchedModel -> MispredictPenalty ;


<s> const <ISA_LIT>BaseRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo -> getRegisterInfo ( ) ;


<s> if ( GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ) return false ; return true ; } else { if ( RelocM == Reloc :: PIC_ ) { if ( ! isDecl && ! GV -> isWeakForLinker ( ) ) return false ; if ( ! GV -> hasHiddenVisibility ( ) ) return true ; if ( isDecl || GV -> hasCommonLinkage ( ) ) return true ; return false ; } else { if ( ! isDecl && ! GV -> isWeakForLinker ( ) ) return false ; if ( ! GV -> hasHiddenVisibility ( ) ) return true ; } }


<s> return HasDataBarrier || ( hasV6Ops ( ) && ! isThumb ( ) ) ;


<s> bool hasCRC ( ) const { return HasCRC ;


<s> bool hasDataBarrier ( ) const { return HasDataBarrier ;


<s> bool hasDivideIn<ISA_LIT>Mode ( ) const {


<s> bool hasPerfMon ( ) const { return HasPerfMon ;


<s> bool <ISA_LIT>Subtarget :: hasSinCos ( ) const { return getTargetTriple ( ) . getOS ( ) == Triple :: IOS && ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ;


<s> bool hasThumb2DSP ( ) const { return Thumb2DSP ;


<s> bool hasV5TEOps ( ) const { return HasV5TEOps ;


<s> bool hasV6MOps ( ) const { return HasV6MOps ;


<s> bool hasV6T2Ops ( ) const { return HasV6T2Ops ;


<s> bool hasV7Ops ( ) const { return HasV7Ops ;


<s> bool hasVFP4 ( ) const { return HasVFPv4 ;


<s> bool hasZeroCycleZeroing ( ) const {


<s> HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; HasCRC = false ; HasZeroCycleZeroing = false ;


<s> assert ( TargetABI != <ISA_LIT>_ABI_UNKNOWN ) ; return TargetABI == <ISA_LIT>_ABI_AAPCS ;


<s> return TargetABI == <ISA_LIT>_ABI_AAPCS ;


<s> return TargetABI == <ISA_LIT>_ABI_APCS ;


<s> return <ISA_LIT>ProcFamily == CortexA5 ;


<s> return <ISA_LIT>ProcFamily == CortexA7 ;


<s> return <ISA_LIT>ProcFamily == CortexA9 ;


<s> bool isCortexA9 ( ) const { return <ISA_LIT>ProcFamily == CortexA9 ;


<s> bool isKrait ( ) const { return <ISA_LIT>ProcFamily == Krait ;


return isCortexA9 ( ) || isCortexA15 ( ) || isKrait ( ) ;


<s> return isCortexA9 ( ) || isCortexA15 ( ) || isKrait ( ) ;


<s> return <ISA_LIT>ProcClass == MClass ;


<s> bool isR9Reserved ( ) const { return IsR9Reserved ;


return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF ) && ! isTargetDarwin ( ) && ! isTargetWindows ( ) ;


<s> return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF ) && ! isTargetDarwin ( ) && ! isTargetWindows ( ) ;


<s> bool isTargetCOFF ( ) const { return TargetTriple . isOSBinFormatCOFF ( ) ;


<s> bool isTargetDarwin ( ) const { return TargetTriple . isOSDarwin ( ) ;


<s> bool isTargetEHABICompatible ( ) const { return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: Android ) && ! isTargetDarwin ( ) && ! isTargetWindows ( ) ;


<s> return TargetTriple . isOSBinFormatELF ( ) ;


return TargetTriple . isOSBinFormatELF ( ) ;


<s> bool isTargetHardFloat ( ) const { return TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || isTargetWindows ( ) ;


<s> bool isTargetIOS ( ) const { return TargetTriple . isiOS ( ) ;


<s> return TargetTriple . isOSNaCl ( ) ;


return TargetTriple . getOS ( ) == Triple :: NetBSD ;


<s> return TargetTriple . getOS ( ) == Triple :: NetBSD ;


<s> bool isTargetWindows ( ) const { return TargetTriple . isOSWindows ( ) ;


<s> bool isThumb ( ) const { return InThumbMode ;


<s> bool isThumb1Only ( ) const { return InThumbMode && ! HasThumb2 ;


<s> void <ISA_LIT>Subtarget :: resetSubtargetFeatures ( StringRef CPU , StringRef FS ) { if ( CPUString . empty ( ) ) { if ( isTargetIOS ( ) && TargetTriple . getArchName ( ) . endswith ( <STR_LIT> ) ) CPUString = <STR_LIT> ; else CPUString = <STR_LIT> ; } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple . getTriple ( ) , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + <STR_LIT> + FS . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( TargetABI == <ISA_LIT>_ABI_UNKNOWN ) { switch ( TargetTriple . getEnvironment ( ) ) { case Triple :: Android : case Triple :: EABI : case Triple :: EABIHF : case Triple :: GNUEABI : case Triple :: GNUEABIHF : TargetABI = <ISA_LIT>_ABI_AAPCS ; break ; default : if ( ( isTargetIOS ( ) && isMClass ( ) ) || ( TargetTriple . isOSBinFormatMachO ( ) && TargetTriple . getOS ( ) == Triple :: UnknownOS ) ) TargetABI = <ISA_LIT>_ABI_AAPCS ; else TargetABI = <ISA_LIT>_ABI_APCS ;


<s> bool restrictIT ( ) const { return RestrictIT ;


<s> bool <ISA_LIT>Subtarget :: useMovt ( const MachineFunction & MF ) const { return UseMovt && ( isTargetWindows ( ) || ! MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ) ;


<s> bool useNEONForSinglePrecisionFP ( ) const {

return hasNEON ( ) && UseNEONForSinglePrecisionFP ; }


<s> if ( isTargetDarwin ( ) || ( ! isTargetWindows ( ) && isThumb ( ) ) ) return <STR_LIT> ; return <STR_LIT> ;


<s> unsigned getMaxMemcpyTPInlineSizeThreshold ( ) const { return <NUM_LIT> ;


<s> if ( CostKind == TargetTransformInfo :: TCK_CodeSize ) return <NUM_LIT> ;


<s> unsigned getMVEVectorCostFactor ( TargetTransformInfo :: TargetCostKind CostKind ) const { if ( CostKind == TargetTransformInfo :: TCK_CodeSize ) return <NUM_LIT> ; return MVEVectorCostFactor ;


<s> bool hardenSlsRetBr ( ) const { return HardenSlsRetBr ;


<s> bool hasBF16 ( ) const { return HasBF16 ;


<s> bool splitFramePushPop ( const MachineFunction & MF ) const {

return ( getFramePointerReg ( ) == <STR_LIT> && MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) || isThumb1Only ( ) ;


<s> bool useFPVFMx ( ) const { return ! isTargetDarwin ( ) && hasVFP4Base ( ) && ! SlowFPVFMx ;


<s> return useFPVFMx ( ) && hasFullFP16 ( ) ;


return useFPVFMx ( ) && hasFullFP16 ( ) ;


<s> bool hasV9_0aOps ( ) const { return HasV9_0aOps ;


<s> return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: Android ) && ! isTargetDarwin ( ) && ! isTargetWindows ( ) && ! isTargetNaCl ( ) && ! Enable<ISA_LIT>DwarfEH ;


<s> bool isV6M ( ) const { return isThumb1Only ( ) && isMClass ( ) ;


<s> return <ISA_LIT>ArchVersion >= V4T ;


<s> bool hasV7Ops ( ) const { return <ISA_LIT>ArchVersion >= V7A ;


<s> return <ISA_LIT>ArchVersion >= V7A ;


<s> bool hasVFP3 ( ) const { return <ISA_LIT>FPUType >= VFPv3 ;


<s> bool isTargetDarwin ( ) const { return TargetType == isDarwin ;


<s> bool isThumb1Only ( ) const { return IsThumb && ( ThumbMode == Thumb1 ) ;


<s> return IsThumb && ( ThumbMode == Thumb2 ) ;


<s> void setGISelAccessor ( GISelAccessor & GISel ) { this -> GISel . reset ( & GISel ) ;


<s> bool hasVFP2Base ( ) const { return HasVFPv2D16SP ;


<s> <ISA_LIT>ArchVersion = V7A ; } else if ( SubVer == '6' ) { <ISA_LIT>ArchVersion = V6 ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == '2' ) <ISA_LIT>ArchVersion = V6T2 ; } else if ( SubVer == '5' ) { <ISA_LIT>ArchVersion = V5T ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == 'e' ) <ISA_LIT>ArchVersion = V5TE ; } else if ( SubVer == '4' ) { if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' ) <ISA_LIT>ArchVersion = V4T ; else <ISA_LIT>ArchVersion = V4 ; } } if ( <ISA_LIT>ArchVersion >= V6T2 ) ThumbMode = Thumb2 ; else if ( ThumbMode >= Thumb2 ) <ISA_LIT>ArchVersion = V6T2 ; if ( Len >= <NUM_LIT> ) {

if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) TargetType = isDarwin ;


<s> CriticalPathRCs . push_back ( & <STR_LIT> ) ; return PostRAScheduler && OptLevel >= CodeGenOpt :: Default ;


<s> CriticalPathRCs . clear ( ) ; CriticalPathRCs . push_back ( & <STR_LIT> ) ; return PostRAScheduler && OptLevel >= CodeGenOpt :: Default ;


<s> unsigned getMaxInlineSizeThreshold ( ) const {


<s> return isThumb1Only ( ) ? <NUM_LIT> : <NUM_LIT> ;


<s> bool isDecl = GV -> isDeclaration ( ) && ! GV -> isMaterializable ( ) ; if ( ! isTargetDarwin ( ) ) { if ( GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ) return false ; return true ; } else { if ( RelocM == Reloc :: PIC_ ) { if ( ! isDecl && ! GV -> isWeakForLinker ( ) ) return false ;

if ( ! GV -> hasHiddenVisibility ( ) ) return true ;


<s> return TargetABI == <ISA_LIT>_ABI_AAPCS ;


<s> return TargetABI == <ISA_LIT>_ABI_APCS ;


<s> bool isLikeA9 ( ) const { return isCortexA9 ( ) || isCortexA15 ( ) ;


<s> return isCortexA9 ( ) || isCortexA15 ( ) ;


<s> bool isMClass ( ) const { return IsMClass ;


<s> bool isTargetELF ( ) const { return ! isTargetDarwin ( ) ;


return TargetTriple . getOS ( ) == Triple :: IOS ;


<s> const DataLayout * getDataLayout ( ) const override { return & DL ;


<s> bool isTargetNaCl ( ) const { return TargetTriple . getOS ( ) == Triple :: NaCl ;


return TargetTriple . getOS ( ) == Triple :: NaCl ;


<s> bool getNoBTIAtReturnTwice ( ) const {


<s> bool isTargetEHABICompatible ( ) const { return TargetTriple . isTargetEHABICompatible ( ) ;


<s> if ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> shouldSignReturnAddress ( ) ) return true ;


<s> bool isGPRegisterReserved ( size_t i ) const {


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetOptions & Options ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , stackAlignment ( <NUM_LIT> ) , CPUString ( CPU ) , TargetTriple ( TT ) , Options ( Options ) , TargetABI ( <ISA_LIT>_ABI_APCS ) { initializeEnvironment ( ) ;


<s> HasVFPv4 = false ; HasV8FP = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; IsMClass = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ;


<s> bool useVMLx ( ) const { return hasVFP2 ( ) && ! SlowVMLx ;


return TargetTriple . getOS ( ) == Triple :: Linux ;


<s> bool hasNEON2 ( ) const { return HasNEON2 || ( HasNEON && HasVFPv4 ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , HasV4TOps ( false ) , HasV5TOps ( false ) , HasV5TEOps ( false ) , HasV6Ops ( false ) , HasV6T2Ops ( false ) , HasV7Ops ( false ) , HasVFPv2 ( false ) , HasVFPv3 ( false ) , HasVFPv4 ( false ) , HasNEON ( false ) , UseNEONForSinglePrecisionFP ( false ) , SlowFPVMLx ( false ) , HasVMLxForwarding ( false ) , SlowFPBrcc ( false ) , InThumbMode ( false ) , HasThumb2 ( false ) , IsMClass ( false ) , No<ISA_LIT> ( false ) , PostRAScheduler ( false ) , IsR9Reserved ( ReserveR9 ) , UseMovt ( false ) , SupportsTailCall ( false ) , HasFP16 ( false ) , HasD16 ( false ) , HasHardwareDivide ( false ) , HasT2ExtractPack ( false ) , HasDataBarrier ( false ) , Pref32BitThumb ( false ) , AvoidCPSRPartialUpdate ( false ) , HasMPExtension ( false ) , FPOnlySP ( false ) , AllowsUnalignedMem ( false ) , Thumb2DSP ( false ) , stackAlignment ( <NUM_LIT> ) , CPUString ( CPU ) , TargetTriple ( TT ) , TargetABI ( <ISA_LIT>_ABI_APCS ) { if ( CPUString . empty ( ) ) CPUString = <STR_LIT> ; std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TT ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + <STR_LIT> + FS ;


<s> itin -> FirstStage != ~ <NUM_LIT> ; ++ itin ) { const InstrStage * IS = InstrItins . Stages + itin -> FirstStage ; allStage1Units |= IS -> getUnits ( ) ; } InstrItins . IssueWidth = <NUM_LIT> ;


<s> ++ InstrItins . IssueWidth ; allStage1Units ^= allStage1Units & ~ ( allStage1Units - <NUM_LIT> ) ; } assert ( InstrItins . IssueWidth <= <NUM_LIT> && <STR_LIT> ) ;


<s> if ( isCortexA8 ( ) ) return <NUM_LIT> ; else if ( isCortexA9 ( ) ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> unsigned <ISA_LIT>Subtarget :: getMispredictionPenalty ( ) const {

if ( isCortexA8 ( ) ) return <NUM_LIT> ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>BaseTargetMachine & TM , bool IsLittle ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , <ISA_LIT>ProcClass ( None ) , <ISA_LIT>Arch ( <ISA_LIT>v4t ) , stackAlignment ( <NUM_LIT> ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new <ISA_LIT>InstrInfo ( * this ) : ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) {


<s> bool <ISA_LIT>Subtarget :: enableAtomicExpand ( ) const {

return hasAnyDataBarrier ( ) && ! isThumb1Only ( ) ;


<s> bool <ISA_LIT>Subtarget :: enableAtomicExpand ( ) const { return hasAnyDataBarrier ( ) && ! isThumb1Only ( ) ;


<s> if ( getSchedModel ( ) . isOutOfOrder ( ) && isSwift ( ) ) return false ; return ( ! isThumb ( ) || hasThumb2 ( ) ) ;


<s> } else { if ( isDef ) return false ; if ( ! GV -> hasHiddenVisibility ( ) ) return true ; if ( RelocM == Reloc :: PIC_ ) { if ( GV -> isDeclarationForLinker ( ) || GV -> hasCommonLinkage ( ) ) return true ; } }


<s> } else { if ( isDef ) return false ; if ( ! GV -> hasHiddenVisibility ( ) ) return true ; if ( RelocM == Reloc :: PIC_ ) { if ( GV -> isDeclarationForLinker ( ) || GV -> hasCommonLinkage ( ) ) return true ; } } return false ;


<s> bool <ISA_LIT>Subtarget :: hasSinCos ( ) const {

return isTargetWatchOS ( ) || ( isTargetIOS ( ) && ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) ;


<s> HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; UseSoftFloat = false ; HasThumb2 = false ; No<ISA_LIT> = false ; ReserveR9 = false ; NoMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasFullFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; HasCRC = false ; HasZeroCycleZeroing = false ; StrictAlign = false ; HasDSP = false ; UseNaClTrap = false ; GenLongCalls = false ; UnsafeFPMath = false ; UseSjLjEH = isTargetDarwin ( ) && ! isTargetWatchOS ( ) ; assert ( ( ! TM . getMCAsmInfo ( ) || ( TM . getMCAsmInfo ( ) -> getExceptionHandlingType ( ) == ExceptionHandling :: SjLj ) == UseSjLjEH ) && <STR_LIT> ) ;


<s> InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = <NUM_LIT> ; SupportsTailCall = ! isThumb1Only ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ; break ; case RestrictedIT : RestrictIT = true ;


<s> StringRef ArchName = TargetTriple . getArchName ( ) ; if ( ArchName . endswith ( <STR_LIT> ) ) CPUString = <STR_LIT> ; else if ( ArchName . endswith ( <STR_LIT> ) ) CPUString = <STR_LIT> ; } } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = <NUM_LIT> ; SupportsTailCall = ! isThumb1Only ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) {


<s> return TargetTriple . getEnvironment ( ) == Triple :: EABI ;


<s> bool isTargetAEABI ( ) const { return TargetTriple . getEnvironment ( ) == Triple :: EABI ;


<s> return ! NoMovt && hasV6T2Ops ( ) && ( isTargetWindows ( ) || ! MF . getFunction ( ) -> optForMinSize ( ) ) ;


<s> bool <ISA_LIT>Subtarget :: useMovt ( const MachineFunction & MF ) const { return ! NoMovt && hasV6T2Ops ( ) && ( isTargetWindows ( ) || ! MF . getFunction ( ) -> optForMinSize ( ) ) ;


<s> return isTargetWatchOS ( ) || ( isSwift ( ) && ! MF . getFunction ( ) -> optForMinSize ( ) ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>BaseTargetMachine & TM , bool IsLittle , bool MinSize ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , UseMulOps ( UseFusedMulOps ) , CPUString ( CPU ) , OptMinSize ( MinSize ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new <ISA_LIT>InstrInfo ( * this ) : ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) { CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( create<ISA_LIT>InstructionSelector ( * static_cast < const <ISA_LIT>BaseTargetMachine * > ( & TM ) , * this , * RBI ) ) ;


<s> if ( isMClass ( ) && hasMinSize ( ) ) return false ; return useMachineScheduler ( ) ;


<s> if ( isMClass ( ) && hasMinSize ( ) ) return false ;


<s> if ( isThumb1Only ( ) ) return <NUM_LIT> ; if ( isThumb2 ( ) && MF . getFunction ( ) . hasMinSize ( ) ) return <NUM_LIT> ;


<s> return isThumb2 ( ) && MF . getFunction ( ) . hasMinSize ( ) && <STR_LIT> . contains ( PhysReg ) ;


<s> bool <ISA_LIT>Subtarget :: useMovt ( ) const {

return ! NoMovt && hasV8MBaselineOps ( ) && ( isTargetWindows ( ) || ! OptMinSize || genExecuteOnly ( ) ) ;


<s> return isTargetWatchABI ( ) || ( useWideStrideVFP ( ) && ! OptMinSize ) ;


<s> UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; IsMClass = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; AllowsUnalignedMem = false ;


<s> InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( ( TargetTriple . getTriple ( ) . find ( <STR_LIT> ) != std :: string :: npos ) || ( isTargetIOS ( ) && isMClass ( ) ) ) TargetABI = <ISA_LIT>_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; UseMovt = hasV6T2Ops ( ) && ArmUseMOVT ; if ( ! isTargetIOS ( ) ) { IsR9Reserved = ReserveR9 ; } else { IsR9Reserved = ReserveR9 | ! HasV6Ops ; SupportsTailCall = ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; switch ( Align ) { case DefaultAlign : AllowsUnalignedMem = ( ( hasV7Ops ( ) && ( isTargetLinux ( ) || isTargetNaCl ( ) ) ) || ( hasV6Ops ( ) && isTargetDarwin ( ) ) ) ; break ; case StrictAlign : AllowsUnalignedMem = false ; break ; case NoStrictAlign : AllowsUnalignedMem = true ; break ; } uint64_t Bits = getFeatureBits ( ) ; if ( ( Bits & <STR_LIT> || Bits & <STR_LIT> ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ;


<s> HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; HasCRC = false ; AllowsUnalignedMem = false ;


<s> InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( ( TargetTriple . getTriple ( ) . find ( <STR_LIT> ) != std :: string :: npos ) || ( isTargetIOS ( ) && isMClass ( ) ) ) TargetABI = <ISA_LIT>_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; UseMovt = hasV6T2Ops ( ) && ArmUseMOVT ; if ( ! isTargetIOS ( ) ) { IsR9Reserved = ReserveR9 ; } else { IsR9Reserved = ReserveR9 | ! HasV6Ops ; SupportsTailCall = ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; switch ( Align ) { case DefaultAlign : AllowsUnalignedMem = ( ( hasV7Ops ( ) && ( isTargetLinux ( ) || isTargetNaCl ( ) ) ) || ( hasV6Ops ( ) && isTargetDarwin ( ) ) ) ; break ; case StrictAlign : AllowsUnalignedMem = false ; break ; case NoStrictAlign : AllowsUnalignedMem = true ; break ; } switch ( IT ) { case DefaultIT :

RestrictIT = hasV8Ops ( ) ? true : false ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , stackAlignment ( <NUM_LIT> ) , CPUString ( CPU ) , TargetTriple ( TT ) , TargetABI ( <ISA_LIT>_ABI_APCS ) {


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , stackAlignment ( <NUM_LIT> ) , CPUString ( CPU ) , TargetTriple ( TT ) , TargetABI ( <ISA_LIT>_ABI_APCS ) { initializeEnvironment ( ) ;


<s> CriticalPathRCs . clear ( ) ; CriticalPathRCs . push_back ( & <STR_LIT> ) ;

return PostRAScheduler && OptLevel >= CodeGenOpt :: Default ;


<s> bool <ISA_LIT>Subtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo :: ANTIDEP_CRITICAL ; CriticalPathRCs . clear ( ) ; CriticalPathRCs . push_back ( & <STR_LIT> ) ;


<s> bool isDecl = GV -> hasAvailableExternallyLinkage ( ) ; if ( GV -> isDeclaration ( ) && ! GV -> isMaterializable ( ) ) isDecl = true ; if ( ! isTargetDarwin ( ) ) {

if ( GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ) return false ;


<s> if ( ( TargetTriple . getTriple ( ) . find ( <STR_LIT> ) != std :: string :: npos ) || ( isTargetIOS ( ) && isMClass ( ) ) ) TargetABI = <ISA_LIT>_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( ! isTargetIOS ( ) ) UseMovt = hasV6T2Ops ( ) ; else { IsR9Reserved = ReserveR9 | ! HasV6Ops ; UseMovt = DarwinUseMOVT && hasV6T2Ops ( ) ; SupportsTailCall = ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; if ( ! StrictAlign && hasV6Ops ( ) && isTargetDarwin ( ) ) AllowsUnalignedMem = true ;


<s> } ParseSubtargetFeatures ( CPUString , ArchFS ) ; if ( ! HasV6T2Ops && hasThumb2 ( ) ) HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( ( TargetTriple . getTriple ( ) . find ( <STR_LIT> ) != std :: string :: npos ) || ( isTargetIOS ( ) && isMClass ( ) ) ) TargetABI = <ISA_LIT>_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( ! isTargetIOS ( ) ) UseMovt = hasV6T2Ops ( ) ; else { IsR9Reserved = ReserveR9 | ! HasV6Ops ; UseMovt = DarwinUseMOVT && hasV6T2Ops ( ) ; SupportsTailCall = ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ;


<s> bool <ISA_LIT>Subtarget :: useMovt ( const MachineFunction & MF ) const { return ! NoMovt && hasV8MBaselineOps ( ) && ( isTargetWindows ( ) || ! MF . getFunction ( ) -> optForMinSize ( ) || genExecuteOnly ( ) ) ;


<s> bool <ISA_LIT>Subtarget :: useStride4VFPs ( const MachineFunction & MF ) const {

return isTargetWatchABI ( ) || ( isSwift ( ) && ! MF . getFunction ( ) -> optForMinSize ( ) ) ;


<s> CPUString = ParseSubtargetFeatures ( FS , CPUString ) ; if ( CPUString == <STR_LIT> && ( FS . empty ( ) || FS == <STR_LIT> ) ) <ISA_LIT>ArchVersion = V4T ; unsigned Len = TT . length ( ) ; unsigned Idx = <NUM_LIT> ; if ( Len >= <NUM_LIT> && TT . substr ( <NUM_LIT> , <NUM_LIT> ) == <STR_LIT> ) Idx = <NUM_LIT> ; else if ( Len >= <NUM_LIT> && TT . substr ( <NUM_LIT> , <NUM_LIT> ) == <STR_LIT> ) { IsThumb = true ; if ( Len >= <NUM_LIT> && TT [ <NUM_LIT> ] == 'v' ) Idx = <NUM_LIT> ; } if ( Idx ) { unsigned SubVer = TT [ Idx ] ; if ( SubVer >= '7' && SubVer <= '9' ) { <ISA_LIT>ArchVersion = V7A ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 'm' ) <ISA_LIT>ArchVersion = V7M ; } else if ( SubVer == '6' ) { <ISA_LIT>ArchVersion = V6 ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == '2' ) <ISA_LIT>ArchVersion = V6T2 ; } else if ( SubVer == '5' ) { <ISA_LIT>ArchVersion = V5T ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == 'e' ) <ISA_LIT>ArchVersion = V5TE ; } else if ( SubVer == '4' ) { if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' ) <ISA_LIT>ArchVersion = V4T ; else <ISA_LIT>ArchVersion = V4 ; } } if ( <ISA_LIT>ArchVersion >= V6T2 ) ThumbMode = Thumb2 ; else if ( ThumbMode >= Thumb2 ) <ISA_LIT>ArchVersion = V6T2 ; if ( Len >= <NUM_LIT> ) { if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) TargetType = isDarwin ; } if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) TargetABI = <ISA_LIT>_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetDarwin ( ) ) IsR9Reserved = ReserveR9 | ( <ISA_LIT>ArchVersion < V6 ) ;

if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>BaseTargetMachine & TM , bool IsLittle ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , <ISA_LIT>ProcClass ( None ) , stackAlignment ( <NUM_LIT> ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , TSInfo ( * TM . getDataLayout ( ) ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new <ISA_LIT>InstrInfo ( * this ) : ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) {


<s> if ( RelocM == Reloc :: Static ) return false ; bool isDecl = GV -> isDeclarationForLinker ( ) ; if ( ! isTargetMachO ( ) ) { if ( GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ) return false ; return true ; } else { if ( RelocM == Reloc :: PIC_ ) { if ( ! isDecl && ! GV -> isWeakForLinker ( ) ) return false ; if ( ! GV -> hasHiddenVisibility ( ) ) return true ; if ( isDecl || GV -> hasCommonLinkage ( ) ) return true ; return false ; } else {


<s> if ( RelocM == Reloc :: Static ) return false ; bool isDecl = GV -> isDeclarationForLinker ( ) ; if ( ! isTargetMachO ( ) ) { if ( GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ) return false ; return true ;


<s> bool <ISA_LIT>Subtarget :: hasSinCos ( ) const { return getTargetTriple ( ) . isiOS ( ) && ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ;


<s> bool <ISA_LIT>Subtarget :: hasSinCos ( ) const {

return getTargetTriple ( ) . isiOS ( ) && ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ;


<s> void <ISA_LIT>Subtarget :: initSubtargetFeatures ( StringRef CPU , StringRef FS ) { if ( CPUString . empty ( ) ) { if ( isTargetDarwin ( ) && TargetTriple . getArchName ( ) . endswith ( <STR_LIT> ) ) CPUString = <STR_LIT> ; else CPUString = <STR_LIT> ; } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple . getTriple ( ) , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + <STR_LIT> + FS . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) ) stackAlignment = <NUM_LIT> ; UseMovt = hasV6T2Ops ( ) && ArmUseMOVT ; if ( isTargetMachO ( ) ) { IsR9Reserved = ReserveR9 || ! HasV6Ops ; SupportsTailCall = ! isTargetIOS ( ) || ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } else { IsR9Reserved = ReserveR9 ; SupportsTailCall = ! isThumb1Only ( ) ; } if ( Align == DefaultAlign ) { AllowsUnalignedMem = ( hasV7Ops ( ) && ( isTargetLinux ( ) || isTargetNaCl ( ) || isTargetNetBSD ( ) ) ) || ( hasV6Ops ( ) && ( isTargetMachO ( ) || isTargetNetBSD ( ) ) ) ; } else { AllowsUnalignedMem = ! ( Align == StrictAlign ) ; } if ( isV6M ( ) ) AllowsUnalignedMem = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ? true : false ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } uint64_t Bits = getFeatureBits ( ) ; if ( ( Bits & <STR_LIT> || Bits & <STR_LIT> ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ;


<s> } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) ) stackAlignment = <NUM_LIT> ; UseMovt = hasV6T2Ops ( ) && ArmUseMOVT ; if ( isTargetMachO ( ) ) { IsR9Reserved = ReserveR9 || ! HasV6Ops ; SupportsTailCall = ! isTargetIOS ( ) || ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } else { IsR9Reserved = ReserveR9 ; SupportsTailCall = ! isThumb1Only ( ) ; } if ( Align == DefaultAlign ) { AllowsUnalignedMem = ( hasV7Ops ( ) && ( isTargetLinux ( ) || isTargetNaCl ( ) || isTargetNetBSD ( ) ) ) || ( hasV6Ops ( ) && ( isTargetMachO ( ) || isTargetNetBSD ( ) ) ) ; } else { AllowsUnalignedMem = ! ( Align == StrictAlign ) ;


<s> bool <ISA_LIT>Subtarget :: isAAPCS_ABI ( ) const { assert ( TM . TargetABI != <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_UNKNOWN ) ;

return TM . TargetABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS ;


<s> return TM . TargetABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>BaseTargetMachine & TM , bool IsLittle ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , UseMulOps ( UseFusedMulOps ) , GenExecuteOnly ( EnableExecuteOnly ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new <ISA_LIT>InstrInfo ( * this ) : ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) , GISel ( ) {


<s> const CallLowering * <ISA_LIT>Subtarget :: getCallLowering ( ) const { assert ( GISel && <STR_LIT> ) ; return GISel -> getCallLowering ( ) ;


<s> return GISel -> getInstructionSelector ( ) ;


<s> assert ( GISel && <STR_LIT> ) ; return GISel -> getLegalizerInfo ( ) ;


<s> return GISel -> getRegBankInfo ( ) ;


<s> const RegisterBankInfo * <ISA_LIT>Subtarget :: getRegBankInfo ( ) const { assert ( GISel && <STR_LIT> ) ;


<s> void <ISA_LIT>Subtarget :: initializeEnvironment ( ) {

UseSjLjEH = isTargetDarwin ( ) && ! isTargetWatchABI ( ) ;


<s> RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9 : LdStMultipleTiming = DoubleIssueCheckUnalignedAccess ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case CortexA12 : break ; case CortexA15 : MaxInterleaveFactor = <NUM_LIT> ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; PartialUpdateClearance = <NUM_LIT> ; break ; case CortexA17 : case CortexA32 : case CortexA35 : case CortexA53 : case CortexA57 : case CortexA72 : case CortexA73 : case CortexR4 : case CortexR4F : case CortexR5 : case CortexR7 : case CortexM3 : case ExynosM1 : case CortexR52 : break ; case Krait : PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case Swift : MaxInterleaveFactor = <NUM_LIT> ; LdStMultipleTiming = SingleIssuePlusExtras ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; PartialUpdateClearance = <NUM_LIT> ; break ; }


<s> if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == 'e' ) <ISA_LIT>ArchVersion = V5TE ; } } } if ( Len >= <NUM_LIT> ) { if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) TargetType = isDarwin ; } else if ( TT . empty ( ) ) { TargetType = isDarwin ; } if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) TargetABI = <ISA_LIT>_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetDarwin ( ) ) { UseThumbBacktraces = true ; IsR9Reserved = true ;


<s> assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; if ( genExecuteOnly ( ) ) assert ( hasV8MBaselineOps ( ) && ! NoMovt && <STR_LIT> ) ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = <NUM_LIT> ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 :


<s> HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; No<ISA_LIT> = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ;


<s> HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; HasCRC = false ; HasZeroCycleZeroing = false ; AllowsUnalignedMem = false ;


<s> void <ISA_LIT>Subtarget :: initSubtargetFeatures ( StringRef CPU , StringRef FS ) { if ( CPUString . empty ( ) ) { if ( isTargetDarwin ( ) && TargetTriple . getArchName ( ) . endswith ( <STR_LIT> ) ) CPUString = <STR_LIT> ; else CPUString = <STR_LIT> ; } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple . getTriple ( ) , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) ) stackAlignment = <NUM_LIT> ; UseMovt = hasV6T2Ops ( ) && ArmUseMOVT ; if ( isTargetMachO ( ) ) { IsR9Reserved = ReserveR9 || ! HasV6Ops ; SupportsTailCall = ! isTargetIOS ( ) || ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } else { IsR9Reserved = ReserveR9 ; SupportsTailCall = ! isThumb1Only ( ) ; } if ( Align == DefaultAlign ) {

AllowsUnalignedMem = ( hasV7Ops ( ) && ( isTargetLinux ( ) || isTargetNaCl ( ) || isTargetNetBSD ( ) ) ) || ( hasV6Ops ( ) && ( isTargetMachO ( ) || isTargetNetBSD ( ) ) ) ;


<s> bool <ISA_LIT>Subtarget :: useMovt ( const MachineFunction & MF ) const { return UseMovt && ( isTargetWindows ( ) || ! MF . getFunction ( ) -> hasFnAttribute ( Attribute :: MinSize ) ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetOptions & Options ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , <ISA_LIT>ProcClass ( None ) , stackAlignment ( <NUM_LIT> ) , CPUString ( CPU ) , TargetTriple ( TT ) , Options ( Options ) , TargetABI ( <ISA_LIT>_ABI_UNKNOWN ) { initializeEnvironment ( ) ;


<s> HasV5TEOps = false ; HasV6Ops = false ; HasV6MOps = false ; HasV6T2Ops = false ; HasV7Ops = false ; HasV8Ops = false ; HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; MinSize = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ;


<s> void <ISA_LIT>Subtarget :: resetSubtargetFeatures ( StringRef CPU , StringRef FS ) { if ( CPUString . empty ( ) ) { if ( isTargetIOS ( ) && TargetTriple . getArchName ( ) . endswith ( <STR_LIT> ) ) CPUString = <STR_LIT> ; else CPUString = <STR_LIT> ; } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple . getTriple ( ) , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + <STR_LIT> + FS . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( TargetABI == <ISA_LIT>_ABI_UNKNOWN ) { switch ( TargetTriple . getEnvironment ( ) ) { case Triple :: Android : case Triple :: EABI : case Triple :: EABIHF : case Triple :: GNUEABI : case Triple :: GNUEABIHF : TargetABI = <ISA_LIT>_ABI_AAPCS ; break ; default : if ( ( isTargetIOS ( ) && isMClass ( ) ) || ( TargetTriple . isOSBinFormatMachO ( ) && TargetTriple . getOS ( ) == Triple :: UnknownOS ) ) TargetABI = <ISA_LIT>_ABI_AAPCS ; else TargetABI = <ISA_LIT>_ABI_APCS ; break ; } } if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) ) stackAlignment = <NUM_LIT> ; UseMovt = hasV6T2Ops ( ) && ArmUseMOVT ; if ( isTargetMachO ( ) ) { IsR9Reserved = ReserveR9 | ! HasV6Ops ; SupportsTailCall = ! isTargetIOS ( ) || ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } else { IsR9Reserved = ReserveR9 ; SupportsTailCall = ! isThumb1Only ( ) ; } if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; switch ( Align ) { case DefaultAlign : AllowsUnalignedMem = ( hasV7Ops ( ) && ( isTargetLinux ( ) || isTargetNaCl ( ) || isTargetNetBSD ( ) ) ) || ( hasV6Ops ( ) && ( isTargetMachO ( ) || isTargetNetBSD ( ) ) ) ; break ; case StrictAlign : AllowsUnalignedMem = false ; break ; case NoStrictAlign : AllowsUnalignedMem = true ; break ; } switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ? true : false ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; }


<s> return TM . getRelocationModel ( ) == Reloc :: PIP ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>BaseTargetMachine & TM , bool IsLittle ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , UseMulOps ( UseFusedMulOps ) , GenExecuteOnly ( EnableExecuteOnly ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new <ISA_LIT>InstrInfo ( * this ) : ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) {


<s> if ( CPUString . empty ( ) ) { CPUString = <STR_LIT> ; if ( isTargetDarwin ( ) ) { StringRef ArchName = TargetTriple . getArchName ( ) ; unsigned ArchKind = <STR_LIT> ( ArchName ) ; if ( ArchKind == <STR_LIT> ) CPUString = <STR_LIT> ; else if ( ArchKind == <STR_LIT> ) CPUString = <STR_LIT> ; } } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; if ( genExecuteOnly ( ) ) assert ( hasV8MBaselineOps ( ) && ! NoMovt && <STR_LIT> ) ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = <NUM_LIT> ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) {


<s> unsigned getMaxInlineSizeThreshold ( ) const {

return isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ;


<s> return IsThumb && ( ThumbMode >= Thumb2 ) ;


<s> bool useThumbBacktraces ( ) const { return UseThumbBacktraces ;


<s> if ( Len >= <NUM_LIT> && TT . substr ( <NUM_LIT> , <NUM_LIT> ) == <STR_LIT> ) Idx = <NUM_LIT> ; else if ( Len >= <NUM_LIT> && TT . substr ( <NUM_LIT> , <NUM_LIT> ) == <STR_LIT> ) { IsThumb = true ; if ( Len >= <NUM_LIT> && TT [ <NUM_LIT> ] == 'v' ) Idx = <NUM_LIT> ; } if ( Idx ) { unsigned SubVer = TT [ Idx ] ; if ( SubVer >= '7' && SubVer <= '9' ) { <ISA_LIT>ArchVersion = V7A ; <ISA_LIT>ArchFeature = <STR_LIT> ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 'm' ) { <ISA_LIT>ArchVersion = V7M ; <ISA_LIT>ArchFeature = <STR_LIT> ; } } else if ( SubVer == '6' ) { <ISA_LIT>ArchVersion = V6 ; <ISA_LIT>ArchFeature = <STR_LIT> ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == '2' ) { <ISA_LIT>ArchVersion = V6T2 ; <ISA_LIT>ArchFeature = <STR_LIT> ; } } else if ( SubVer == '5' ) { <ISA_LIT>ArchVersion = V5T ; <ISA_LIT>ArchFeature = <STR_LIT> ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == 'e' ) { <ISA_LIT>ArchVersion = V5TE ;


<s> } else if ( SubVer == '6' ) { <ISA_LIT>ArchVersion = V6 ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == '2' ) <ISA_LIT>ArchVersion = V6T2 ; } else if ( SubVer == '5' ) { <ISA_LIT>ArchVersion = V5T ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == 'e' ) <ISA_LIT>ArchVersion = V5TE ; } if ( <ISA_LIT>ArchVersion >= V6T2 ) ThumbMode = Thumb2 ; } } if ( <ISA_LIT>ArchVersion < V6T2 && ThumbMode >= Thumb2 ) <ISA_LIT>ArchVersion = V6T2 ; if ( Len >= <NUM_LIT> ) { if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) TargetType = isDarwin ; } if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) TargetABI = <ISA_LIT>_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ;

if ( isTargetDarwin ( ) ) IsR9Reserved = ReserveR9 | ( <ISA_LIT>ArchVersion < V6 ) ;


<s> bool isDecl = GV -> isDeclaration ( ) || GV -> hasAvailableExternallyLinkage ( ) ; if ( GV -> hasHiddenVisibility ( ) && ( ! isDecl && ! GV -> hasCommonLinkage ( ) ) ) return false ;

return ! isStatic && ( isDecl || GV -> isWeakForLinker ( ) ) ;


<s> return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF ) && ! isTargetDarwin ( ) ;


<s> return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: Android ) && ! isTargetDarwin ( ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool IsLittle ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , <ISA_LIT>ProcClass ( None ) , stackAlignment ( <NUM_LIT> ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TargetABI ( <ISA_LIT>_ABI_UNKNOWN ) , DL ( computeDataLayout ( initializeSubtargetDependencies ( CPU , FS ) ) ) , TSInfo ( DL ) , InstrInfo ( isThumb1Only ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new <ISA_LIT>InstrInfo ( * this ) : ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM ) , FrameLowering ( ! isThumb1Only ( ) ? new <ISA_LIT>FrameLowering ( * this ) : ( <ISA_LIT>FrameLowering * ) new Thumb1FrameLowering ( * this ) ) {


<s> Ret += DataLayout :: getManglingComponent ( ST . getTargetTriple ( ) ) ; Ret += <STR_LIT> ; if ( ! ST . isAPCS_ABI ( ) ) Ret += <STR_LIT> ; if ( ST . isAPCS_ABI ( ) ) Ret += <STR_LIT> ; if ( ST . isAPCS_ABI ( ) ) Ret += <STR_LIT> ;


<s> } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple . getTriple ( ) , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + <STR_LIT> + FS . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( TargetABI == <ISA_LIT>_ABI_UNKNOWN ) { switch ( TargetTriple . getEnvironment ( ) ) { case Triple :: Android : case Triple :: EABI : case Triple :: EABIHF : case Triple :: GNUEABI : case Triple :: GNUEABIHF : TargetABI = <ISA_LIT>_ABI_AAPCS ; break ; default : if ( TargetTriple . isOSBinFormatMachO ( ) && TargetTriple . getOS ( ) == Triple :: UnknownOS ) TargetABI = <ISA_LIT>_ABI_AAPCS ; else TargetABI = <ISA_LIT>_ABI_APCS ; break ; } } if ( isTargetWindows ( ) ) { TargetABI = <ISA_LIT>_ABI_AAPCS ; No<ISA_LIT> = true ; } if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) ) stackAlignment = <NUM_LIT> ; UseMovt = hasV6T2Ops ( ) && ArmUseMOVT ; if ( isTargetMachO ( ) ) { IsR9Reserved = ReserveR9 || ! HasV6Ops ; SupportsTailCall = ! isTargetIOS ( ) || ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } else { IsR9Reserved = ReserveR9 ; SupportsTailCall = ! isThumb1Only ( ) ; } if ( Align == DefaultAlign ) { AllowsUnalignedMem = ( hasV7Ops ( ) && ( isTargetLinux ( ) || isTargetNaCl ( ) || isTargetNetBSD ( ) ) ) || ( hasV6Ops ( ) && ( isTargetMachO ( ) || isTargetNetBSD ( ) ) ) ; } else { AllowsUnalignedMem = ! ( Align == StrictAlign ) ;


<s> if ( CPUString . empty ( ) ) CPUString = <STR_LIT> ; std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TT , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + <STR_LIT> + FS ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; if ( ! HasV6T2Ops && hasThumb2 ( ) ) HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( ( TT . find ( <STR_LIT> ) != std :: string :: npos ) || ( isTargetIOS ( ) && isMClass ( ) ) ) TargetABI = <ISA_LIT>_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( ! isTargetIOS ( ) ) UseMovt = hasV6T2Ops ( ) ; else {


<s> if ( ! enableMachineScheduler ( ) ) return false ; if ( disablePostRAScheduler ( ) ) return false ; return ! isThumb1Only ( ) ;


<s> bool <ISA_LIT>Subtarget :: enablePostRAMachineScheduler ( ) const {

if ( ! enableMachineScheduler ( ) ) return false ;


<s> bool <ISA_LIT>Subtarget :: enablePostRAScheduler ( ) const { if ( enableMachineScheduler ( ) ) return false ; if ( disablePostRAScheduler ( ) ) return false ; return ! isThumb1Only ( ) ;


<s> bool <ISA_LIT>Subtarget :: enableSubRegLiveness ( ) const {


<s> } SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) && ! hasMinSize ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ;


<s> StringRef ArchName = TargetTriple . getArchName ( ) ; <STR_LIT> AK = <STR_LIT> ( ArchName ) ; if ( AK == <STR_LIT> :: <ISA_LIT>V7S ) CPUString = <STR_LIT> ; else if ( AK == <STR_LIT> :: <ISA_LIT>V7K ) CPUString = <STR_LIT> ; } } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; if ( genExecuteOnly ( ) ) { NoMovt = false ; assert ( hasV8MBaselineOps ( ) && <STR_LIT> ) ; } SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; if ( MVEVectorCostFactor == <NUM_LIT> ) MVEVectorCostFactor = <NUM_LIT> ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9 : LdStMultipleTiming = DoubleIssueCheckUnalignedAccess ; PreISelOperandLatencyAdjustment = <NUM_LIT> ;


<s> HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; IsMClass = false ; No<ISA_LIT> = false ; PostRAScheduler = false ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>BaseTargetMachine & TM , bool IsLittle ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , <ISA_LIT>ProcClass ( None ) , stackAlignment ( <NUM_LIT> ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , DL ( computeDataLayout ( initializeSubtargetDependencies ( CPU , FS ) ) ) , TSInfo ( DL ) , InstrInfo ( isThumb1Only ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new <ISA_LIT>InstrInfo ( * this ) : ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM ) , FrameLowering ( ! isThumb1Only ( ) ? new <ISA_LIT>FrameLowering ( * this ) : ( <ISA_LIT>FrameLowering * ) new Thumb1FrameLowering ( * this ) ) {


<s> else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; if ( ! HasV6T2Ops && hasThumb2 ( ) ) HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( ( TT . find ( <STR_LIT> ) != std :: string :: npos ) || ( isTargetIOS ( ) && isMClass ( ) ) ) TargetABI = <ISA_LIT>_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( ! isTargetIOS ( ) ) UseMovt = hasV6T2Ops ( ) ; else { IsR9Reserved = ReserveR9 | ! HasV6Ops ; UseMovt = DarwinUseMOVT && hasV6T2Ops ( ) ; SupportsTailCall = ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; if ( ! StrictAlign && hasV6Ops ( ) && isTargetDarwin ( ) ) AllowsUnalignedMem = true ;


<s> InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) && ! hasMinSize ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; if ( MVEVectorCostFactor == <NUM_LIT> ) MVEVectorCostFactor = <NUM_LIT> ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9 : LdStMultipleTiming = DoubleIssueCheckUnalignedAccess ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case CortexA12 : break ; case CortexA15 : MaxInterleaveFactor = <NUM_LIT> ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; PartialUpdateClearance = <NUM_LIT> ; break ; case CortexA17 : case CortexA32 : case CortexA35 : case CortexA53 : case CortexA55 : case CortexA57 : case CortexA72 : case CortexA73 : case CortexA75 : case CortexA76 : case CortexA77 : case CortexA78 : case CortexR4 : case CortexR4F : case CortexR5 : case CortexR7 : case CortexM3 : case CortexR52 : case CortexX1 : break ; case Exynos : LdStMultipleTiming = SingleIssuePlusExtras ; MaxInterleaveFactor = <NUM_LIT> ; if ( ! isThumb ( ) ) PrefLoopLogAlignment = <NUM_LIT> ; break ; case Kryo : break ; case Krait : PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case NeoverseN1 : case NeoverseN2 : case NeoverseV1 :


<s> HasVFPv4 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseInlineJumpTables = ! NoInlineJumpTables ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; IsMClass = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ;


<s> if ( ! HasV6T2Ops && hasThumb2 ( ) ) HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( ( TargetTriple . getTriple ( ) . find ( <STR_LIT> ) != std :: string :: npos ) || ( isTargetIOS ( ) && isMClass ( ) ) ) TargetABI = <ISA_LIT>_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( ! isTargetIOS ( ) ) UseMovt = hasV6T2Ops ( ) ; else { IsR9Reserved = ReserveR9 | ! HasV6Ops ; UseMovt = DarwinUseMOVT && hasV6T2Ops ( ) ; SupportsTailCall = ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } if ( isTargetNaCl ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) && ! useConstPool ( ) ) UseMovt = true ; if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; switch ( Align ) { case DefaultAlign :

AllowsUnalignedMem = ( ( hasV7Ops ( ) && ( isTargetLinux ( ) || isTargetNaCl ( ) ) ) || ( hasV6Ops ( ) && isTargetDarwin ( ) ) ) ;


<s> bool <ISA_LIT>Subtarget :: enableMachinePipeliner ( ) const {

return getSchedModel ( ) . hasInstrSchedModel ( ) && useMachinePipeliner ( ) ;


<s> if ( EnableSubRegLiveness . getNumOccurrences ( ) ) return EnableSubRegLiveness ;