<s> static inline bool Thumb2SRSOpcode ( unsigned Opcode ) { switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; }


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; return <NUM_LIT> ; case <NUM_LIT> : return imm8 ; case <NUM_LIT> : return imm8 << <NUM_LIT> | imm8 ; case <NUM_LIT> : return imm8 << <NUM_LIT> | imm8 << <NUM_LIT> ; case <NUM_LIT> : return imm8 << <NUM_LIT> | imm8 << <NUM_LIT> | imm8 << <NUM_LIT> | imm8 ; } } else { unsigned Val = <NUM_LIT> << <NUM_LIT> | slice ( imm12 , <NUM_LIT> , <NUM_LIT> ) ; unsigned Amt = slice ( imm12 , <NUM_LIT> , <NUM_LIT> ) ;


<s> int Offset = TFI -> ResolveFrameIndexReference ( MF , FrameIndex , FrameReg , SPAdj ) ; if ( RS && FrameReg == <STR_LIT> && RS -> isScavengingFrameIndex ( FrameIndex ) ) { assert ( STI . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) && <STR_LIT> <STR_LIT> ) ; assert ( ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) && <STR_LIT> <STR_LIT> ) ; } if ( MI . isDebugValue ( ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } assert ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) && <STR_LIT> ) ; if ( rewriteFrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( Offset && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands ( MI , PIdx ) ; if ( MI . mayLoad ( ) ) { unsigned TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , TmpReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , TmpReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else { emitThumbRegPlusImmediate ( MBB , II , dl , TmpReg , FrameReg , Offset , TII , * this ) ; } MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ;

MI . getOperand ( FIOperandNum ) . ChangeToRegister ( TmpReg , false , false , true ) ;


<s> if ( STI . isThumb1Only ( ) ) { assert ( ( is<ISA_LIT>LowRegister ( DestReg ) || isVirtualRegister ( DestReg ) ) && <STR_LIT> ) ; return emitThumb1LoadConstPool ( MBB , MBBI , dl , DestReg , SubIdx , Val , Pred , PredReg , MIFlags ) ; }

return emitThumb2LoadConstPool ( MBB , MBBI , dl , DestReg , SubIdx , Val , Pred , PredReg , MIFlags ) ;


<s> if ( STI . isThumb1Only ( ) ) { assert ( ( is<ISA_LIT>LowRegister ( DestReg ) || isVirtualRegister ( DestReg ) ) && <STR_LIT> ) ;

return emitThumb1LoadConstPool ( MBB , MBBI , dl , DestReg , SubIdx , Val , Pred , PredReg , MIFlags ) ;


<s> static void emitThumb1LoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const DebugLoc & dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg , unsigned MIFlags ) { MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ;


<s> unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ;

BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . add ( predOps ( <STR_LIT> ) ) . setMIFlags ( MIFlags ) ;


<s> static void emitThumb2LoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const DebugLoc & dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg , unsigned MIFlags ) { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) . getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . add ( predOps ( <STR_LIT> ) ) . setMIFlags ( MIFlags ) ;


<s> assert ( ( ( Bytes & <NUM_LIT> ) == <NUM_LIT> || ExtraScale == <NUM_LIT> ) && <STR_LIT> ) ; unsigned CopyRange = ( ( <NUM_LIT> << CopyBits ) - <NUM_LIT> ) * CopyScale ; if ( CopyOpc && Bytes < CopyScale ) { CopyOpc = <STR_LIT> ; CopyScale = <NUM_LIT> ; CopyNeedsCC = false ; CopyRange = <NUM_LIT> ; } unsigned ExtraRange = ( ( <NUM_LIT> << ExtraBits ) - <NUM_LIT> ) * ExtraScale ; unsigned RequiredCopyInstrs = CopyOpc ? <NUM_LIT> : <NUM_LIT> ; unsigned RangeAfterCopy = ( CopyRange > Bytes ) ? <NUM_LIT> : ( Bytes - CopyRange ) ; assert ( RangeAfterCopy % ExtraScale == <NUM_LIT> && <STR_LIT> ) ; unsigned RequiredExtraInstrs ; if ( ExtraRange ) RequiredExtraInstrs = alignTo ( RangeAfterCopy , ExtraRange ) / ExtraRange ; else if ( RangeAfterCopy > <NUM_LIT> ) RequiredExtraInstrs = <NUM_LIT> ; else RequiredExtraInstrs = <NUM_LIT> ; unsigned RequiredInstrs = RequiredCopyInstrs + RequiredExtraInstrs ; unsigned Threshold = ( DestReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( RequiredInstrs > Threshold ) { emitThumbRegPlusImmInReg ( MBB , MBBI , dl , DestReg , BaseReg , NumBytes , true , TII , MRI , MIFlags ) ; return ; } if ( CopyOpc ) { unsigned CopyImm = std :: min ( Bytes , CopyRange ) / CopyScale ; Bytes -= CopyImm * CopyScale ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( CopyOpc ) , DestReg ) ; if ( CopyNeedsCC ) MIB = MIB . add ( t1CondCodeOp ( ) ) ; MIB . addReg ( BaseReg , RegState :: Kill ) ; if ( CopyOpc != <STR_LIT> ) { MIB . addImm ( CopyImm ) ; } MIB . setMIFlags ( MIFlags ) . add ( predOps ( <STR_LIT> ) ) ; BaseReg = DestReg ; } while ( Bytes ) { unsigned ExtraImm = std :: min ( Bytes , ExtraRange ) / ExtraScale ; Bytes -= ExtraImm * ExtraScale ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( ExtraOpc ) , DestReg ) ; if ( ExtraNeedsCC ) MIB = MIB . add ( t1CondCodeOp ( ) ) ; MIB . addReg ( BaseReg ) . addImm ( ExtraImm ) . add ( predOps ( <STR_LIT> ) ) . setMIFlags ( MIFlags ) ; }


<s> static void emitThumbRegPlusImmInReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const DebugLoc & dl , unsigned DestReg , unsigned BaseReg , int NumBytes , bool CanChangeCC , const TargetInstrInfo & TII , const <ISA_LIT>BaseRegisterInfo & MRI , unsigned MIFlags = MachineInstr :: NoFlags ) { MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool isHigh = ! is<ISA_LIT>LowRegister ( DestReg ) || ( BaseReg != <NUM_LIT> && ! is<ISA_LIT>LowRegister ( BaseReg ) ) ; bool isSub = false ; if ( NumBytes < <NUM_LIT> && ! isHigh && CanChangeCC ) { isSub = true ; NumBytes = - NumBytes ; } unsigned LdReg = DestReg ; if ( DestReg == <STR_LIT> ) assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; if ( ! is<ISA_LIT>LowRegister ( DestReg ) && ! MRI . isVirtualRegister ( DestReg ) ) LdReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> && CanChangeCC ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> && CanChangeCC ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addReg ( LdReg , RegState :: Kill ) . setMIFlags ( MIFlags ) ; } else if ( ST . genExecuteOnly ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , dl , LdReg , <NUM_LIT> , NumBytes , <STR_LIT> , <NUM_LIT> , MIFlags ) ; int Opc = ( isSub ) ? <STR_LIT> : ( ( isHigh || ! CanChangeCC ) ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ; if ( Opc != <STR_LIT> ) MIB = MIB . add ( t1CondCodeOp ( ) ) ; if ( DestReg == <STR_LIT> || isSub ) MIB . addReg ( BaseReg ) . addReg ( LdReg , RegState :: Kill ) ; else MIB . addReg ( LdReg ) . addReg ( BaseReg , RegState :: Kill ) ; MIB . add ( predOps ( <STR_LIT> ) ) ;


<s> const TargetRegisterClass * ThumbRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb1Only ( ) ) return <ISA_LIT>BaseRegisterInfo :: getLargestLegalSuperClass ( RC , MF ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return & <STR_LIT> ;


<s> const TargetRegisterClass * ThumbRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const {

if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb1Only ( ) ) return <ISA_LIT>BaseRegisterInfo :: getPointerRegClass ( MF , Kind ) ;


<s> if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb1Only ( ) ) return <ISA_LIT>BaseRegisterInfo :: getPointerRegClass ( MF , Kind ) ; return & <STR_LIT> ;


<s> void ThumbRegisterInfo :: resolveFrameIndex ( MachineInstr & MI , unsigned BaseReg , int64_t Offset ) const { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! STI . isThumb1Only ( ) ) return <ISA_LIT>BaseRegisterInfo :: resolveFrameIndex ( MI , BaseReg , Offset ) ; const <ISA_LIT>BaseInstrInfo & TII = * STI . getInstrInfo ( ) ;


<s> MBB . erase ( II ) ; return true ; } else { if ( AddrMode != <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; unsigned ImmIdx = FrameRegIdx + <NUM_LIT> ; int InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; unsigned NumBits = ( FrameReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; Offset += InstrOffs * Scale ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand & ImmOp = MI . getOperand ( ImmIdx ) ; int ImmedOffset = Offset / Scale ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( unsigned ) Offset <= Mask * Scale ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; ImmOp . ChangeToImmediate ( ImmedOffset ) ; unsigned NewOpc = convertToNonSPOpcode ( Opcode ) ; if ( NewOpc != Opcode && FrameReg != <STR_LIT> ) MI . setDesc ( TII . get ( NewOpc ) ) ; return true ; } NumBits = <NUM_LIT> ; Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { ImmOp . ChangeToImmediate ( <NUM_LIT> ) ; } else { ImmedOffset = ImmedOffset & Mask ; ImmOp . ChangeToImmediate ( ImmedOffset ) ; Offset &= ~ ( Mask * Scale ) ;


<s> bool ThumbRegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! STI . isThumb1Only ( ) ) return <ISA_LIT>BaseRegisterInfo :: saveScavengerRegister ( MBB , I , UseMI , RC , Reg ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; DebugLoc DL ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) . add ( predOps ( <STR_LIT> ) ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugInstr ( ) ) continue ;

for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i != e ; ++ i ) {


<s> ThumbRegisterInfo :: ThumbRegisterInfo ( ) : <ISA_LIT>BaseRegisterInfo ( ) {


<s> Register VReg ; const <ISA_LIT>BaseInstrInfo & TII = * STI . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB ( * MBB . getParent ( ) , & MI ) ; Register FrameReg ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; int Offset = TFI -> ResolveFrameIndexReference ( MF , FrameIndex , FrameReg , SPAdj ) ; if ( RS && FrameReg == <STR_LIT> && RS -> isScavengingFrameIndex ( FrameIndex ) ) { assert ( STI . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) && <STR_LIT> <STR_LIT> ) ; assert ( ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) && <STR_LIT> <STR_LIT> ) ; } if ( MI . isDebugValue ( ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } assert ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) && <STR_LIT> ) ; if ( rewriteFrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( Offset && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands ( MI , PIdx ) ; if ( MI . mayLoad ( ) ) { Register TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , TmpReg , FrameReg , Offset , false , TII , * this ) ; else {

emitLoadConstPool ( MBB , II , dl , TmpReg , <NUM_LIT> , Offset ) ;


<s> assert ( ( is<ISA_LIT>LowRegister ( DestReg ) || DestReg . isVirtual ( ) ) && <STR_LIT> ) ; return emitThumb1LoadConstPool ( MBB , MBBI , dl , DestReg , SubIdx , Val , Pred , PredReg , MIFlags ) ; }


<s> const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) . getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , Align ( <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ;


<s> static void emitThumb2LoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const DebugLoc & dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg , unsigned MIFlags ) { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ;

MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ;


<s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) . getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , Align ( <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . add ( predOps ( <STR_LIT> ) ) . setMIFlags ( MIFlags ) ;


<s> CopyBits = <NUM_LIT> ; CopyScale = <NUM_LIT> ; } else if ( DestReg == BaseReg ) { } else if ( is<ISA_LIT>LowRegister ( BaseReg ) ) { CopyOpc = isSub ? <STR_LIT> : <STR_LIT> ; CopyBits = <NUM_LIT> ; CopyNeedsCC = true ; } else { CopyOpc = <STR_LIT> ; CopyBits = <NUM_LIT> ; } ExtraOpc = isSub ? <STR_LIT> : <STR_LIT> ; ExtraBits = <NUM_LIT> ; ExtraNeedsCC = true ; } else { if ( DestReg == BaseReg ) { } else { CopyOpc = <STR_LIT> ; CopyBits = <NUM_LIT> ; } ExtraOpc = <NUM_LIT> ; } assert ( ( ( Bytes & <NUM_LIT> ) == <NUM_LIT> || ExtraScale == <NUM_LIT> ) && <STR_LIT> ) ; unsigned CopyRange = ( ( <NUM_LIT> << CopyBits ) - <NUM_LIT> ) * CopyScale ; if ( CopyOpc && Bytes < CopyScale ) { CopyOpc = <STR_LIT> ; CopyScale = <NUM_LIT> ; CopyNeedsCC = false ; CopyRange = <NUM_LIT> ; } unsigned ExtraRange = ( ( <NUM_LIT> << ExtraBits ) - <NUM_LIT> ) * ExtraScale ; unsigned RequiredCopyInstrs = CopyOpc ? <NUM_LIT> : <NUM_LIT> ; unsigned RangeAfterCopy = ( CopyRange > Bytes ) ? <NUM_LIT> : ( Bytes - CopyRange ) ; assert ( RangeAfterCopy % ExtraScale == <NUM_LIT> && <STR_LIT> ) ; unsigned RequiredExtraInstrs ; if ( ExtraRange ) RequiredExtraInstrs = alignTo ( RangeAfterCopy , ExtraRange ) / ExtraRange ; else if ( RangeAfterCopy > <NUM_LIT> ) RequiredExtraInstrs = <NUM_LIT> ; else RequiredExtraInstrs = <NUM_LIT> ; unsigned RequiredInstrs = RequiredCopyInstrs + RequiredExtraInstrs ; unsigned Threshold = ( DestReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( RequiredInstrs > Threshold ) { emitThumbRegPlusImmInReg ( MBB , MBBI , dl , DestReg , BaseReg , NumBytes , true , TII , MRI , MIFlags ) ; return ; } if ( CopyOpc ) { unsigned CopyImm = std :: min ( Bytes , CopyRange ) / CopyScale ; Bytes -= CopyImm * CopyScale ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( CopyOpc ) , DestReg ) ; if ( CopyNeedsCC ) MIB = MIB . add ( t1CondCodeOp ( ) ) ; MIB . addReg ( BaseReg , RegState :: Kill ) ; if ( CopyOpc != <STR_LIT> ) { MIB . addImm ( CopyImm ) ; } MIB . setMIFlags ( MIFlags ) . add ( predOps ( <STR_LIT> ) ) ;


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addReg ( LdReg , RegState :: Kill ) . setMIFlags ( MIFlags ) ; } else if ( ST . genExecuteOnly ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , dl , LdReg , <NUM_LIT> , NumBytes , <STR_LIT> , <NUM_LIT> , MIFlags ) ; int Opc = ( isSub ) ? <STR_LIT> : ( ( isHigh || ! CanChangeCC ) ? <STR_LIT> : <STR_LIT> ) ;

MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ;


<s> const <ISA_LIT>BaseInstrInfo & TII = * STI . getInstrInfo ( ) ; int Off = Offset ; unsigned i = <NUM_LIT> ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } bool Done = rewriteFrameIndex ( MI , i , BaseReg , Off , TII ) ; assert ( Done && <STR_LIT> ) ; ( void ) Done ;


<s> Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; emitThumbRegPlusImmediate ( MBB , II , dl , DestReg , FrameReg , Offset , TII , * this ) ; MBB . erase ( II ) ; return true ; } else { if ( AddrMode != <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; unsigned ImmIdx = FrameRegIdx + <NUM_LIT> ; int InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; unsigned NumBits = ( FrameReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; Offset += InstrOffs * Scale ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand & ImmOp = MI . getOperand ( ImmIdx ) ; int ImmedOffset = Offset / Scale ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( unsigned ) Offset <= Mask * Scale ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; ImmOp . ChangeToImmediate ( ImmedOffset ) ;

unsigned NewOpc = convertToNonSPOpcode ( Opcode ) ;


<s> if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb1Only ( ) ) {


<s> bool ThumbRegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb1Only ( ) ) {


<s> int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands ( MI , PIdx ) ; if ( MI . mayLoad ( ) ) { unsigned TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , TmpReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , TmpReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else { emitThumbRegPlusImmediate ( MBB , II , dl , TmpReg , FrameReg , Offset , TII , * this ) ; } MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( TmpReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else if ( MI . mayStore ( ) ) { VReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , VReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , VReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else emitThumbRegPlusImmediate ( MBB , II , dl , VReg , FrameReg , Offset , TII , * this ) ; MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( VReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else { llvm_unreachable ( <STR_LIT> ) ; }

if ( MI . isPredicable ( ) ) MIB . add ( predOps ( <STR_LIT> ) ) ;


<s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ;

const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ;


<s> for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { UseMI = II ; done = true ; break ; } if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) { UseMI = II ; done = true ; break ; } }


<s> const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; DebugLoc DL ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) . add ( predOps ( <STR_LIT> ) ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugValue ( ) ) continue ; for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i != e ; ++ i ) {

const MachineOperand & MO = II -> getOperand ( i ) ;


<s> void ThumbRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ;


<s> static void emitThumb1LoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg , unsigned MIFlags ) { MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ;


<s> unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( ( int64_t ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ;


<s> MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( ( int64_t ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ;


<s> } ExtraOpc = isSub ? <STR_LIT> : <STR_LIT> ; ExtraBits = <NUM_LIT> ; ExtraScale = <NUM_LIT> ; } else if ( is<ISA_LIT>LowRegister ( DestReg ) ) { if ( BaseReg == <STR_LIT> ) { assert ( ! isSub && <STR_LIT> ) ; CopyOpc = <STR_LIT> ; CopyBits = <NUM_LIT> ; CopyScale = <NUM_LIT> ; } else if ( DestReg == BaseReg ) { } else if ( is<ISA_LIT>LowRegister ( BaseReg ) ) { CopyOpc = isSub ? <STR_LIT> : <STR_LIT> ; CopyBits = <NUM_LIT> ; CopyNeedsCC = true ; } else { CopyOpc = <STR_LIT> ; CopyBits = <NUM_LIT> ; } ExtraOpc = isSub ? <STR_LIT> : <STR_LIT> ; ExtraBits = <NUM_LIT> ; ExtraNeedsCC = true ; } else { if ( DestReg == BaseReg ) { } else { CopyOpc = <STR_LIT> ; CopyBits = <NUM_LIT> ; } ExtraOpc = <NUM_LIT> ; } assert ( ( ( Bytes & <NUM_LIT> ) == <NUM_LIT> || ExtraScale == <NUM_LIT> ) && <STR_LIT> ) ; unsigned CopyRange = ( ( <NUM_LIT> << CopyBits ) - <NUM_LIT> ) * CopyScale ; if ( CopyOpc && Bytes < CopyScale ) { CopyOpc = <STR_LIT> ; CopyScale = <NUM_LIT> ; CopyNeedsCC = false ; CopyRange = <NUM_LIT> ; } unsigned ExtraRange = ( ( <NUM_LIT> << ExtraBits ) - <NUM_LIT> ) * ExtraScale ; unsigned RequiredCopyInstrs = CopyOpc ? <NUM_LIT> : <NUM_LIT> ; unsigned RangeAfterCopy = ( CopyRange > Bytes ) ? <NUM_LIT> : ( Bytes - CopyRange ) ; assert ( RangeAfterCopy % ExtraScale == <NUM_LIT> && <STR_LIT> ) ; unsigned RequiredExtraInstrs ; if ( ExtraRange ) RequiredExtraInstrs = alignTo ( RangeAfterCopy , ExtraRange ) / ExtraRange ; else if ( RangeAfterCopy > <NUM_LIT> ) RequiredExtraInstrs = <NUM_LIT> ; else RequiredExtraInstrs = <NUM_LIT> ; unsigned RequiredInstrs = RequiredCopyInstrs + RequiredExtraInstrs ; unsigned Threshold = ( DestReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( RequiredInstrs > Threshold ) { emitThumbRegPlusImmInReg ( MBB , MBBI , dl , DestReg , BaseReg , NumBytes , true , TII , MRI , MIFlags ) ; return ; } if ( CopyOpc ) { unsigned CopyImm = std :: min ( Bytes , CopyRange ) / CopyScale ; Bytes -= CopyImm * CopyScale ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( CopyOpc ) , DestReg ) ; if ( CopyNeedsCC ) MIB = AddDefaultT1CC ( MIB ) ; MIB . addReg ( BaseReg , RegState :: Kill ) ; if ( CopyOpc != <STR_LIT> ) { MIB . addImm ( CopyImm ) ; } AddDefaultPred ( MIB . setMIFlags ( MIFlags ) ) ; BaseReg = DestReg ; } while ( Bytes ) {

unsigned ExtraImm = std :: min ( Bytes , ExtraRange ) / ExtraScale ;


<s> unsigned TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , TmpReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , TmpReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else { emitThumbRegPlusImmediate ( MBB , II , dl , TmpReg , FrameReg , Offset , TII , * this ) ; } MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( TmpReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else if ( MI . mayStore ( ) ) { VReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , VReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , VReg , <NUM_LIT> , Offset ) ; UseRR = true ; }

} else emitThumbRegPlusImmediate ( MBB , II , dl , VReg , FrameReg , Offset , TII , * this ) ;


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , dl , LdReg , <NUM_LIT> , NumBytes , <STR_LIT> , <NUM_LIT> , MIFlags ) ; int Opc = ( isSub ) ? <STR_LIT> : ( ( isHigh || ! CanChangeCC ) ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ; if ( Opc != <STR_LIT> ) MIB = AddDefaultT1CC ( MIB ) ; if ( DestReg == <STR_LIT> || isSub ) MIB . addReg ( BaseReg ) . addReg ( LdReg , RegState :: Kill ) ; else MIB . addReg ( LdReg ) . addReg ( BaseReg , RegState :: Kill ) ; AddDefaultPred ( MIB ) ;


<s> if ( DestReg == <STR_LIT> ) assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; if ( ! is<ISA_LIT>LowRegister ( DestReg ) && ! MRI . isVirtualRegister ( DestReg ) ) LdReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> && CanChangeCC ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> && CanChangeCC ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addReg ( LdReg , RegState :: Kill ) . setMIFlags ( MIFlags ) ; } else if ( ST . genExecuteOnly ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , dl , LdReg , <NUM_LIT> , NumBytes , <STR_LIT> , <NUM_LIT> , MIFlags ) ; int Opc = ( isSub ) ? <STR_LIT> : ( ( isHigh || ! CanChangeCC ) ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ;

if ( Opc != <STR_LIT> ) MIB = AddDefaultT1CC ( MIB ) ;


<s> ThumbRegisterInfo :: ThumbRegisterInfo ( ) {


<s> if ( MI . isDebugValue ( ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } assert ( AFI -> isThumbFunction ( ) && <STR_LIT> ) ; if ( rewriteFrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( Offset && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands ( MI , PIdx ) ; if ( MI . mayLoad ( ) ) { unsigned TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> ) emitThumbRegPlusImmInReg ( MBB , II , dl , TmpReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , TmpReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else { emitThumbRegPlusImmediate ( MBB , II , dl , TmpReg , FrameReg , Offset , TII , * this ) ; } MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( TmpReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else if ( MI . mayStore ( ) ) { VReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> ) emitThumbRegPlusImmInReg ( MBB , II , dl , VReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , VReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else emitThumbRegPlusImmediate ( MBB , II , dl , VReg , FrameReg , Offset , TII , * this ) ; MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( VReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else { llvm_unreachable ( <STR_LIT> ) ;


<s> unsigned FrameReg = <STR_LIT> ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MF . getFrameInfo ( ) -> getStackSize ( ) + SPAdj ; if ( MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ) { assert ( SPAdj == <NUM_LIT> && STI . getFrameLowering ( ) -> hasFP ( MF ) && <STR_LIT> ) ; if ( ! hasBasePointer ( MF ) ) { FrameReg = getFrameRegister ( MF ) ; Offset -= AFI -> getFramePtrSpillOffset ( ) ; } else FrameReg = BasePtr ; } if ( RS && FrameReg == <STR_LIT> && RS -> isScavengingFrameIndex ( FrameIndex ) ) { assert ( STI . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) && <STR_LIT> <STR_LIT> ) ; assert ( ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) && <STR_LIT> <STR_LIT> ) ; } if ( MI . isDebugValue ( ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } assert ( AFI -> isThumbFunction ( ) && <STR_LIT> ) ; if ( rewriteFrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( Offset && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands ( MI , PIdx ) ; if ( MI . mayLoad ( ) ) { unsigned TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> ) emitThumbRegPlusImmInReg ( MBB , II , dl , TmpReg , FrameReg , Offset , false , TII , * this ) ;


<s> if ( MI . isDebugValue ( ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } assert ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) && <STR_LIT> ) ; if ( rewriteFrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( Offset && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands ( MI , PIdx ) ; if ( MI . mayLoad ( ) ) { Register TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , TmpReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , TmpReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else { emitThumbRegPlusImmediate ( MBB , II , dl , TmpReg , FrameReg , Offset , TII , * this ) ; } MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( TmpReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else if ( MI . mayStore ( ) ) { VReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) {

if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , VReg , FrameReg , Offset , false , TII , * this ) ;


<s> } assert ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) && <STR_LIT> ) ; if ( rewriteFrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( Offset && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands ( MI , PIdx ) ; if ( MI . mayLoad ( ) ) { Register TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , TmpReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , TmpReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else { emitThumbRegPlusImmediate ( MBB , II , dl , TmpReg , FrameReg , Offset , TII , * this ) ; } MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( TmpReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else if ( MI . mayStore ( ) ) { VReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , VReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , VReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else emitThumbRegPlusImmediate ( MBB , II , dl , VReg , FrameReg , Offset , TII , * this ) ; MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( VReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( MI . isPredicable ( ) ) MIB . add ( predOps ( <STR_LIT> ) ) ;


<s> void ThumbRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const DebugLoc & dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ;

const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . isThumb1Only ( ) ) { assert ( ( is<ISA_LIT>LowRegister ( DestReg ) || Register :: isVirtualRegister ( DestReg ) ) && <STR_LIT> ) ; return emitThumb1LoadConstPool ( MBB , MBBI , dl , DestReg , SubIdx , Val , Pred , PredReg , MIFlags ) ; } return emitThumb2LoadConstPool ( MBB , MBBI , dl , DestReg , SubIdx , Val , Pred , PredReg , MIFlags ) ;


<s> if ( NumBytes < <NUM_LIT> && ! isHigh && CanChangeCC ) { isSub = true ; NumBytes = - NumBytes ; } unsigned LdReg = DestReg ; if ( DestReg == <STR_LIT> ) assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; if ( ! is<ISA_LIT>LowRegister ( DestReg ) && ! Register :: isVirtualRegister ( DestReg ) ) LdReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> && CanChangeCC ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> && CanChangeCC ) {


<s> } unsigned LdReg = DestReg ; if ( DestReg == <STR_LIT> ) assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; if ( ! is<ISA_LIT>LowRegister ( DestReg ) && ! Register :: isVirtualRegister ( DestReg ) ) LdReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> && CanChangeCC ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> && CanChangeCC ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addReg ( LdReg , RegState :: Kill ) . setMIFlags ( MIFlags ) ; } else if ( ST . genExecuteOnly ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , dl , LdReg , <NUM_LIT> , NumBytes , <STR_LIT> , <NUM_LIT> , MIFlags ) ; int Opc = ( isSub ) ? <STR_LIT> : ( ( isHigh || ! CanChangeCC ) ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ; if ( Opc != <STR_LIT> ) MIB = MIB . add ( t1CondCodeOp ( ) ) ;

if ( DestReg == <STR_LIT> || isSub ) MIB . addReg ( BaseReg ) . addReg ( LdReg , RegState :: Kill ) ;


<s> DebugLoc dl = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB ( * MBB . getParent ( ) , & MI ) ; unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MI . getDesc ( ) ; unsigned AddrMode = ( Desc . TSFlags & <STR_LIT> ) ; if ( Opcode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; emitThumbRegPlusImmediate ( MBB , II , dl , DestReg , FrameReg , Offset , TII , * this ) ; MBB . erase ( II ) ; return true ; } else { if ( AddrMode != <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; unsigned ImmIdx = FrameRegIdx + <NUM_LIT> ; int InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; unsigned NumBits = ( FrameReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; Offset += InstrOffs * Scale ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand & ImmOp = MI . getOperand ( ImmIdx ) ; int ImmedOffset = Offset / Scale ;

unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ;


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; assert ( MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb1Only ( ) && <STR_LIT> ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB ( * MBB . getParent ( ) , & MI ) ; unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MI . getDesc ( ) ; unsigned AddrMode = ( Desc . TSFlags & <STR_LIT> ) ; if ( Opcode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; emitThumbRegPlusImmediate ( MBB , II , dl , DestReg , FrameReg , Offset , TII , * this ) ; MBB . erase ( II ) ; return true ; } else { if ( AddrMode != <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; unsigned ImmIdx = FrameRegIdx + <NUM_LIT> ; int InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; unsigned NumBits = ( FrameReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; Offset += InstrOffs * Scale ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ;

MachineOperand & ImmOp = MI . getOperand ( ImmIdx ) ;


for ( unsigned e = MI . getNumOperands ( ) ; i != e ; ++ i ) MI . removeOperand ( Op ) ;


<s> unsigned Op = i ; for ( unsigned e = MI . getNumOperands ( ) ; i != e ; ++ i ) MI . removeOperand ( Op ) ;


<s> const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ;


<s> unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( ( int64_t ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; bool isHigh = ! is<ISA_LIT>LowRegister ( DestReg ) || ( BaseReg != <NUM_LIT> && ! is<ISA_LIT>LowRegister ( BaseReg ) ) ; bool isSub = false ; if ( NumBytes < <NUM_LIT> && ! isHigh && CanChangeCC ) { isSub = true ; NumBytes = - NumBytes ; } unsigned LdReg = DestReg ; if ( DestReg == <STR_LIT> ) assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; if ( ! is<ISA_LIT>LowRegister ( DestReg ) && ! MRI . isVirtualRegister ( DestReg ) ) LdReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> && CanChangeCC ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> && CanChangeCC ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addReg ( LdReg , RegState :: Kill ) . setMIFlags ( MIFlags ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , dl , LdReg , <NUM_LIT> , NumBytes , <STR_LIT> , <NUM_LIT> , MIFlags ) ; int Opc = ( isSub ) ? <STR_LIT> : ( ( isHigh || ! CanChangeCC ) ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ; if ( Opc != <STR_LIT> ) MIB = AddDefaultT1CC ( MIB ) ; if ( DestReg == <STR_LIT> || isSub ) MIB . addReg ( BaseReg ) . addReg ( LdReg , RegState :: Kill ) ; else MIB . addReg ( LdReg ) . addReg ( BaseReg , RegState :: Kill ) ;


<s> if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { UseMI = II ; done = true ; break ; } if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) { UseMI = II ; done = true ; break ; } } }

AddDefaultPred ( BuildMI ( MBB , UseMI , DL , TII . get ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) ) ;