<s> } if ( MI . getOpcode ( ) == <STR_LIT> ) { expandMEMCPY ( MI ) ; return true ; } if ( ! MI . isCopy ( ) || Subtarget . dontWidenVMOVS ( ) || ! Subtarget . hasFP64 ( ) ) return false ; unsigned DstRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ;

unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ;


<s> while ( CmpMI != Br -> getParent ( ) -> begin ( ) ) { -- CmpMI ; if ( CmpMI -> modifiesRegister ( <STR_LIT> , TRI ) ) break ; if ( CmpMI -> readsRegister ( <STR_LIT> , TRI ) ) break ; } if ( CmpMI -> getOpcode ( ) != <STR_LIT> && CmpMI -> getOpcode ( ) != <STR_LIT> ) return nullptr ; unsigned Reg = CmpMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * CmpMI , PredReg ) ; if ( Pred != <STR_LIT> || CmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return nullptr ;

if ( ! is<ISA_LIT>LowRegister ( Reg ) ) return nullptr ;


<s> } if ( CmpMI -> getOpcode ( ) != <STR_LIT> && CmpMI -> getOpcode ( ) != <STR_LIT> ) return nullptr ; unsigned Reg = CmpMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * CmpMI , PredReg ) ; if ( Pred != <STR_LIT> || CmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return nullptr ;


<s> case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : case <STR_LIT> : { unsigned Size = getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MAI ) ; if ( ! MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) ) Size = alignTo ( Size , <NUM_LIT> ) ; return Size ; } }


return std :: min ( Size / <NUM_LIT> , <NUM_LIT> ) ;


<s> for ( MachineInstr :: mmo_iterator I = MI . memoperands_begin ( ) , E = MI . memoperands_end ( ) ; I != E ; ++ I ) { Size += ( * I ) -> getSize ( ) ;


<s> return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return <STR_LIT> ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ;


<s> unsigned <ISA_LIT>BaseInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { SmallVector < const MachineMemOperand * , <NUM_LIT> > Accesses ; if ( MI . mayLoad ( ) && hasLoadFromStackSlot ( MI , Accesses ) && Accesses . size ( ) == <NUM_LIT> ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ; return true ; }


<s> unsigned <ISA_LIT>BaseInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { SmallVector < const MachineMemOperand * , <NUM_LIT> > Accesses ; if ( MI . mayLoad ( ) && hasLoadFromStackSlot ( MI , Accesses ) && Accesses . size ( ) == <NUM_LIT> ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ;


<s> unsigned TakenBranchCost = Subtarget . getMispredictionPenalty ( ) ; unsigned TUnpredCycles , FUnpredCycles ; if ( ! FCycles ) { TUnpredCycles = TCycles + NotTakenBranchCost ; FUnpredCycles = TakenBranchCost ; } else { TUnpredCycles = TCycles + TakenBranchCost ; FUnpredCycles = FCycles + NotTakenBranchCost ; PredCost -= <NUM_LIT> * ScalingUpFactor ; } unsigned TUnpredCost = Probability . scale ( TUnpredCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FUnpredCycles * ScalingUpFactor ) ; UnpredCost = TUnpredCost + FUnpredCost ; if ( Subtarget . isThumb2 ( ) && TCycles + FCycles > <NUM_LIT> ) { PredCost += ( ( TCycles + FCycles - <NUM_LIT> ) / <NUM_LIT> ) * ScalingUpFactor ;


<s> unsigned TakenBranchCost = Subtarget . getMispredictionPenalty ( ) ; unsigned TUnpredCycles , FUnpredCycles ; if ( ! FCycles ) { TUnpredCycles = TCycles + NotTakenBranchCost ; FUnpredCycles = TakenBranchCost ; } else { TUnpredCycles = TCycles + TakenBranchCost ; FUnpredCycles = FCycles + NotTakenBranchCost ; PredCost -= <NUM_LIT> * ScalingUpFactor ; } unsigned TUnpredCost = Probability . scale ( TUnpredCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FUnpredCycles * ScalingUpFactor ) ; UnpredCost = TUnpredCost + FUnpredCost ; if ( Subtarget . isThumb2 ( ) && TCycles + FCycles > <NUM_LIT> ) {

PredCost += ( ( TCycles + FCycles - <NUM_LIT> ) / <NUM_LIT> ) * ScalingUpFactor ;


<s> return true ; } if ( CmpI -> getOpcode ( ) == <STR_LIT> && OI -> getOpcode ( ) == <STR_LIT> && ( ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) || ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ) ) { IsThumb1 = true ; return true ; } if ( ( CmpI -> getOpcode ( ) == <STR_LIT> || CmpI -> getOpcode ( ) == <STR_LIT> ) && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getImm ( ) == ImmValue ) { IsThumb1 = false ; return true ; } if ( CmpI -> getOpcode ( ) == <STR_LIT> && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getImm ( ) == ImmValue ) { IsThumb1 = true ; return true ; } if ( ( CmpI -> getOpcode ( ) == <STR_LIT> || CmpI -> getOpcode ( ) == <STR_LIT> ) && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && OI -> getOperand ( <NUM_LIT> ) . isReg ( ) && OI -> getOperand ( <NUM_LIT> ) . isReg ( ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) {


<s> default : break ; case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return <STR_LIT> ; } break ; case <STR_LIT> : case <STR_LIT> :


<s> case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return <STR_LIT> ;


<s> unsigned <ISA_LIT>BaseInstrInfo :: isStoreToStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { SmallVector < const MachineMemOperand * , <NUM_LIT> > Accesses ;

if ( MI . mayStore ( ) && hasStoreToStackSlot ( MI , Accesses ) && Accesses . size ( ) == <NUM_LIT> ) {


<s> SmallVector < const MachineMemOperand * , <NUM_LIT> > Accesses ; if ( MI . mayStore ( ) && hasStoreToStackSlot ( MI , Accesses ) && Accesses . size ( ) == <NUM_LIT> ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ; return true ; } return false ;


<s> ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } <STR_LIT> CC ; bool IsInstrVSel = true ; switch ( Instr . getOpcode ( ) ) { default : IsInstrVSel = false ; CC = ( <STR_LIT> ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; } if ( SubAdd ) { unsigned Opc = SubAdd -> getOpcode ( ) ; bool IsSub = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; unsigned OpI = Opc != <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( ! IsSub || ( SrcReg2 != <NUM_LIT> && SubAdd -> getOperand ( OpI ) . getReg ( ) == SrcReg2 && SubAdd -> getOperand ( OpI + <NUM_LIT> ) . getReg ( ) == SrcReg ) ) { if ( IsInstrVSel ) return false ; <STR_LIT> NewCC = ( IsSub ? getSwappedCondition ( CC ) : getCmpToAddCondition ( CC ) ) ; if ( NewCC == <STR_LIT> ) return false ; OperandsToUpdate . push_back ( std :: make_pair ( & ( ( * I ) . getOperand ( IO - <NUM_LIT> ) ) , NewCC ) ) ; } } else { switch ( CC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } } } } if ( ! isSafe ) { MachineBasicBlock * MBB = CmpInstr . getParent ( ) ; for ( MachineBasicBlock :: succ_iterator SI = MBB -> succ_begin ( ) , SE = MBB -> succ_end ( ) ; SI != SE ; ++ SI ) if ( ( * SI ) -> isLiveIn ( <STR_LIT> ) ) return false ; } if ( ! IsThumb1 ) {

MI -> getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ;


<s> for ( auto I = From ; I != To ; ++ I ) if ( I -> modifiesRegister ( Reg , TRI ) ) return true ;


<s> if ( IsVFPPushPop ) { RegsNeeded = NumBytes / <NUM_LIT> ; RegClass = & <STR_LIT> ; } else { RegsNeeded = NumBytes / <NUM_LIT> ; RegClass = & <STR_LIT> ; } SmallVector < MachineOperand , <NUM_LIT> > RegList ; unsigned FirstRegEnc = - <NUM_LIT> ; const TargetRegisterInfo * TRI = MF . getRegInfo ( ) . getTargetRegisterInfo ( ) ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx ; -- i ) { MachineOperand & MO = MI -> getOperand ( i ) ; RegList . push_back ( MO ) ; if ( MO . isReg ( ) && TRI -> getEncodingValue ( MO . getReg ( ) ) < FirstRegEnc ) FirstRegEnc = TRI -> getEncodingValue ( MO . getReg ( ) ) ; } const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( int CurRegEnc = FirstRegEnc - <NUM_LIT> ; CurRegEnc >= <NUM_LIT> && RegsNeeded ; -- CurRegEnc ) { unsigned CurReg = RegClass -> getRegister ( CurRegEnc ) ; if ( IsT1PushPop && CurReg > <STR_LIT> ) continue ; if ( ! IsPop ) { RegList . push_back ( MachineOperand :: CreateReg ( CurReg , false , false , false , false , true ) ) ; -- RegsNeeded ; continue ; } if ( isCalleeSavedRegister ( CurReg , CSRegs ) || MI -> getParent ( ) -> computeRegisterLiveness ( TRI , CurReg , MI ) != MachineBasicBlock :: LQR_Dead ) { if ( IsVFPPushPop ) return false ; else continue ; } RegList . push_back ( MachineOperand :: CreateReg ( CurReg , true , false , false , true ) ) ; -- RegsNeeded ; } if ( RegsNeeded > <NUM_LIT> ) return false ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx ; -- i ) MI -> RemoveOperand ( i ) ; MachineInstrBuilder MIB ( MF , & * MI ) ; for ( int i = RegList . size ( ) - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) MIB . add ( RegList [ i ] ) ; return true ;


<s> bool IsPush = isPushOpcode ( MI -> getOpcode ( ) ) ; if ( ! IsPush && ! IsPop ) return false ; bool IsVFPPushPop = MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ; bool IsT1PushPop = MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ; assert ( ( IsT1PushPop || ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; if ( NumBytes % ( IsVFPPushPop ? <NUM_LIT> : <NUM_LIT> ) != <NUM_LIT> ) return false ; int RegListIdx = IsT1PushPop ? <NUM_LIT> : <NUM_LIT> ; unsigned RegsNeeded ; const TargetRegisterClass * RegClass ; if ( IsVFPPushPop ) { RegsNeeded = NumBytes / <NUM_LIT> ; RegClass = & <STR_LIT> ; } else { RegsNeeded = NumBytes / <NUM_LIT> ; RegClass = & <STR_LIT> ; } SmallVector < MachineOperand , <NUM_LIT> > RegList ; unsigned FirstRegEnc = - <NUM_LIT> ; const TargetRegisterInfo * TRI = MF . getRegInfo ( ) . getTargetRegisterInfo ( ) ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx ; -- i ) {

MachineOperand & MO = MI -> getOperand ( i ) ;


<s> if ( ! SubIdx ) return MIB . addReg ( Reg , State ) ; if ( Register :: isPhysicalRegister ( Reg ) ) return MIB . addReg ( TRI -> getSubReg ( Reg , SubIdx ) , State ) ;

return MIB . addReg ( Reg , State , SubIdx ) ;


<s> if ( Register :: isPhysicalRegister ( Reg ) ) return MIB . addReg ( TRI -> getSubReg ( Reg , SubIdx ) , State ) ;


<s> MIB . addReg ( <STR_LIT> , RegState :: Implicit ) ; MIB . addReg ( <NUM_LIT> ) ;


<s> void llvm :: addPredicatedMveVpredNOp ( MachineInstrBuilder & MIB , unsigned Cond ) { MIB . addImm ( Cond ) ; MIB . addReg ( <STR_LIT> , RegState :: Implicit ) ;


<s> void llvm :: addUnpredicatedMveVpredNOp ( MachineInstrBuilder & MIB ) { MIB . addImm ( <STR_LIT> ) ;


<s> MIB . addReg ( DestReg , RegState :: Undef ) ;


<s> void llvm :: addUnpredicatedMveVpredROp ( MachineInstrBuilder & MIB , Register DestReg ) {


<s> SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = ~ <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ;

CmpMask = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = ~ <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ;


<s> if ( <STR_LIT> . contains ( Reg ) ) { DReg = <STR_LIT> + ( Reg - <STR_LIT> ) / <NUM_LIT> ; assert ( TRI -> isSuperRegister ( Reg , DReg ) && <STR_LIT> ) ; } assert ( <STR_LIT> . contains ( DReg ) && <STR_LIT> ) ;

assert ( MI . definesRegister ( DReg , TRI ) && <STR_LIT> ) ;


<s> MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ; if ( isThumb && ! Call -> getOperand ( FuncOp ) . isReg ( ) ) MIB . add ( predOps ( <STR_LIT> ) ) ; Call -> eraseFromParent ( ) ; } auto IsNonTailCall = [ ] ( MachineInstr & MI ) { return MI . isCall ( ) && ! MI . isReturn ( ) ; } ; if ( llvm :: any_of ( MBB . instrs ( ) , IsNonTailCall ) ) { MachineBasicBlock :: iterator It = MBB . begin ( ) ; MachineBasicBlock :: iterator Et = MBB . end ( ) ;

if ( OF . FrameConstructionID == MachineOutlinerTailCall || OF . FrameConstructionID == MachineOutlinerThunk ) Et = std :: prev ( MBB . end ( ) ) ;


<s> void <ISA_LIT>BaseInstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: OutlinedFunction & OF ) const { if ( OF . FrameConstructionID == MachineOutlinerThunk ) { MachineInstr * Call = & * -- MBB . instr_end ( ) ; bool isThumb = Subtarget . isThumb ( ) ; unsigned FuncOp = isThumb ? <NUM_LIT> : <NUM_LIT> ; unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? <STR_LIT> : <STR_LIT> : isThumb ? Subtarget . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ; if ( isThumb && ! Call -> getOperand ( FuncOp ) . isReg ( ) ) MIB . add ( predOps ( <STR_LIT> ) ) ; Call -> eraseFromParent ( ) ; } auto IsNonTailCall = [ ] ( MachineInstr & MI ) { return MI . isCall ( ) && ! MI . isReturn ( ) ;


<s> const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isFI ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return nullptr ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isTied ( ) ) return nullptr ; if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) return nullptr ;

if ( MO . isDef ( ) && ! MO . isDead ( ) ) return nullptr ;


<s> if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> || AddrMode == <STR_LIT> || AddrMode == <STR_LIT> || AddrMode == <STR_LIT> || AddrMode == <STR_LIT> || AddrMode == <STR_LIT> || AddrMode == <STR_LIT> || AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) return false ; unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; unsigned ImmIdx = NumOps - <NUM_LIT> ; const MachineOperand & Offset = MI -> getOperand ( ImmIdx ) ; assert ( Offset . isImm ( ) && <STR_LIT> ) ; int64_t OffVal = Offset . getImm ( ) ; if ( OffVal < <NUM_LIT> ) return false ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; switch ( AddrMode ) { case <STR_LIT> : if ( <STR_LIT> ( OffVal ) == <STR_LIT> ) return false ; OffVal = <STR_LIT> ( OffVal ) ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : if ( <STR_LIT> ( OffVal ) == <STR_LIT> ) return false ; OffVal = <STR_LIT> ( OffVal ) ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : if ( <STR_LIT> ( OffVal ) == <STR_LIT> ) return false ; OffVal = <STR_LIT> ( OffVal ) ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : assert ( ( Fixup & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ;


<s> case <STR_LIT> : if ( <STR_LIT> ( OffVal ) == <STR_LIT> ) return false ; OffVal = <STR_LIT> ( OffVal ) ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : assert ( ( Fixup & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } assert ( ( ( OffVal * Scale + Fixup ) & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; OffVal += Fixup / Scale ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( OffVal <= Mask ) { if ( Updt ) MI -> getOperand ( ImmIdx ) . setImm ( OffVal ) ;


<s> bool Found = false ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ;

bool ClobbersCPSR = MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ;


<s> for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; bool ClobbersCPSR = MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ; bool IsCPSR = MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == <STR_LIT> ;


<s> MachineInstr * CommutedMI = TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ; if ( ! CommutedMI ) return nullptr ; CommutedMI -> getOperand ( CommutedMI -> findFirstPredOperandIdx ( ) ) . setImm ( <STR_LIT> ( CC ) ) ;


<s> case <STR_LIT> : { Register PredReg ; <STR_LIT> CC = getInstrPredicate ( MI , PredReg ) ; if ( CC == <STR_LIT> || PredReg != <STR_LIT> ) return nullptr ; MachineInstr * CommutedMI = TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ; if ( ! CommutedMI ) return nullptr ;

CommutedMI -> getOperand ( CommutedMI -> findFirstPredOperandIdx ( ) ) . setImm ( <STR_LIT> ( CC ) ) ;


<s> if ( Subtarget -> isThumb ( ) ) { if ( Val <= <NUM_LIT> ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( Subtarget -> hasV6T2Ops ( ) && ( Val <= <NUM_LIT> || <STR_LIT> ( Val ) != - <NUM_LIT> || <STR_LIT> ( ~ Val ) != - <NUM_LIT> ) ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( Val <= <NUM_LIT> ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( ~ Val <= <NUM_LIT> ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; } else { if ( <STR_LIT> ( Val ) != - <NUM_LIT> ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( <STR_LIT> ( ~ Val ) != - <NUM_LIT> ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( Subtarget -> hasV6T2Ops ( ) && Val <= <NUM_LIT> ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; }

if ( Subtarget -> useMovt ( ) ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ;


<s> if ( Op . getType ( ) != MachineOperand :: MO_Immediate ) return std :: string ( ) ; int FirstPredOp = MI . findFirstPredOperandIdx ( ) ; if ( FirstPredOp != ( int ) OpIdx ) return std :: string ( ) ;


<s> auto BHR = TargetInstrInfo :: CreateTargetMIHazardRecognizer ( II , DAG ) ; MHR -> AddHazardRecognizer ( std :: unique_ptr < ScheduleHazardRecognizer > ( BHR ) ) ;


<s> MultiHazardRecognizer * MHR = new MultiHazardRecognizer ( ) ; if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2Base ( ) ) MHR -> AddHazardRecognizer ( std :: make_unique < <ISA_LIT>HazardRecognizerFPMLx > ( ) ) ; auto BHR = TargetInstrInfo :: CreateTargetPostRAHazardRecognizer ( II , DAG ) ;

if ( BHR ) MHR -> AddHazardRecognizer ( std :: unique_ptr < ScheduleHazardRecognizer > ( BHR ) ) ;


<s> CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAG * DAG ) const { MultiHazardRecognizer * MHR = new MultiHazardRecognizer ( ) ; if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2Base ( ) ) MHR -> AddHazardRecognizer ( std :: make_unique < <ISA_LIT>HazardRecognizerFPMLx > ( ) ) ; auto BHR = TargetInstrInfo :: CreateTargetPostRAHazardRecognizer ( II , DAG ) ;


<s> Optional < ParamLoadedValue > <ISA_LIT>BaseInstrInfo :: describeLoadedValue ( const MachineInstr & MI , Register Reg ) const {

if ( auto DstSrcPair = isCopyInstrImpl ( MI ) ) {


<s> else if ( ACPV -> isLSDA ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( & MF . getFunction ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isMachineBasicBlock ( ) ) NewCPV = <ISA_LIT>ConstantPoolMBB :: Create ( MF . getFunction ( ) . getContext ( ) , cast < <ISA_LIT>ConstantPoolMBB > ( ACPV ) -> getMBB ( ) , PCLabelId , <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; CPI = MCP -> getConstantPoolIndex ( NewCPV , MCPE . getAlign ( ) ) ;


<s> void llvm :: emit<ISA_LIT>RegPlusImmediate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const DebugLoc & dl , Register DestReg , Register BaseReg , int NumBytes , <STR_LIT> Pred , Register PredReg , const <ISA_LIT>BaseInstrInfo & TII , unsigned MIFlags ) { if ( NumBytes == <NUM_LIT> && DestReg != BaseReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . add ( predOps ( Pred , PredReg ) ) . add ( condCodeOp ( ) ) . setMIFlags ( MIFlags ) ; return ; }


<s> void <ISA_LIT>BaseInstrInfo :: emitCFIForLRRestoreFromReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator It ) const { MachineFunction & MF = * MBB . getParent ( ) ; const MCRegisterInfo * MRI = Subtarget . getRegisterInfo ( ) ; unsigned DwarfLR = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; int64_t LRPosEntry = MF . addFrameInst ( MCCFIInstruction :: createRestore ( nullptr , DwarfLR ) ) ;

BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( LRPosEntry ) . setMIFlags ( MachineInstr :: FrameDestroy ) ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; const MCRegisterInfo * MRI = Subtarget . getRegisterInfo ( ) ; unsigned DwarfLR = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ;

int64_t StackPosEntry = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , <NUM_LIT> ) ) ;


<s> const MCRegisterInfo * MRI = Subtarget . getRegisterInfo ( ) ; unsigned DwarfLR = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; int Align = Subtarget . getStackAlignment ( ) . value ( ) ;

int64_t StackPosEntry = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , Align ) ) ;


<s> const MCRegisterInfo * MRI = Subtarget . getRegisterInfo ( ) ; unsigned DwarfLR = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; int Align = Subtarget . getStackAlignment ( ) . value ( ) ; int64_t StackPosEntry = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , Align ) ) ;

BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( StackPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ;


<s> int64_t LRPosEntry = MF . addFrameInst ( MCCFIInstruction :: createRegister ( nullptr , DwarfLR , DwarfReg ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( LRPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ;


<s> if ( Subtarget . isGVIndirectSymbol ( GV ) ) { MIB = BuildMI ( MBB , MI , DL , get ( LoadOpc ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( * MBB . getParent ( ) ) , Flags , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; MIB . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } MIB = BuildMI ( MBB , MI , DL , get ( LoadOpc ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . cloneMemRefs ( * MI ) . add ( predOps ( <STR_LIT> ) ) ;


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) { expandMEMCPY ( MI ) ; return true ; } if ( ! MI . isCopy ( ) || Subtarget . dontWidenVMOVS ( ) || ! Subtarget . hasFP64 ( ) ) return false ; Register DstRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || ! SrcRegD ) return false ; if ( ! MI . definesRegister ( DstRegD , TRI ) || MI . readsRegister ( DstRegD , TRI ) ) return false ; if ( MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; MachineInstrBuilder MIB ( * MI . getParent ( ) -> getParent ( ) , MI ) ; int ImpDefIdx = MI . findRegisterDefOperandIdx ( DstRegD ) ;

if ( ImpDefIdx != - <NUM_LIT> ) MI . RemoveOperand ( ImpDefIdx ) ;


<s> unsigned MaxInsts = Subtarget . restrictIT ( ) ? <NUM_LIT> : <NUM_LIT> ;

return divideCeil ( NumInsts , MaxInsts ) * <NUM_LIT> ;


<s> assert ( C . LRUWasSet && <STR_LIT> ) ; MachineFunction * MF = C . getMF ( ) ; const <ISA_LIT>BaseRegisterInfo * ARI = static_cast < const <ISA_LIT>BaseRegisterInfo * > ( MF -> getSubtarget ( ) . getRegisterInfo ( ) ) ; BitVector regsReserved = ARI -> getReservedRegs ( * MF ) ; for ( unsigned Reg : <STR_LIT> ) { if ( ! ( Reg < regsReserved . size ( ) && regsReserved . test ( Reg ) ) && Reg != <STR_LIT> && Reg != <STR_LIT> && C . LRU . available ( Reg ) && C . UsedInSequence . available ( Reg ) ) return Reg ;


<s> void <ISA_LIT>BaseInstrInfo :: fixupPostOutline ( MachineBasicBlock & MBB ) const { for ( MachineInstr & MI : MBB ) { checkAndUpdateStackOffset ( & MI , Subtarget . getStackAlignment ( ) . value ( ) , true ) ; }


<s> unsigned llvm :: getBLXOpcode ( const MachineFunction & MF ) { return ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hardenSlsBlr ( ) ) ? <STR_LIT> : <STR_LIT> ;


<s> return ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hardenSlsBlr ( ) ) ? <STR_LIT> : <STR_LIT> ;


<s> unsigned llvm :: getBLXpredOpcode ( const MachineFunction & MF ) {

return ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hardenSlsBlr ( ) ) ? <STR_LIT> : <STR_LIT> ;


<s> bool <ISA_LIT>BaseInstrInfo :: getInsertSubregLikeInputs ( const MachineInstr & MI , unsigned DefIdx , RegSubRegPair & BaseReg , RegSubRegPairAndIdx & InsertedReg ) const { assert ( DefIdx < MI . getDesc ( ) . getNumDefs ( ) && <STR_LIT> ) ; assert ( MI . isInsertSubregLike ( ) && <STR_LIT> ) ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : const MachineOperand & MOBaseReg = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & MOInsertedReg = MI . getOperand ( <NUM_LIT> ) ; if ( MOInsertedReg . isUndef ( ) ) return false ; const MachineOperand & MOIndex = MI . getOperand ( <NUM_LIT> ) ; BaseReg . Reg = MOBaseReg . getReg ( ) ; BaseReg . SubReg = MOBaseReg . getSubReg ( ) ; InsertedReg . Reg = MOInsertedReg . getReg ( ) ; InsertedReg . SubReg = MOInsertedReg . getSubReg ( ) ;

InsertedReg . SubIdx = <STR_LIT> + MOIndex . getImm ( ) ;


<s> } const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( PredCost && ( MCID . isCall ( ) || ( MCID . hasImplicitDefOfPhysReg ( <STR_LIT> ) && ! Subtarget . cheapPredicableCPSRDef ( ) ) ) ) { * PredCost = <NUM_LIT> ; } if ( ! ItinData ) return MI . mayLoad ( ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Class = MCID . getSchedClass ( ) ; if ( ! ItinData -> isEmpty ( ) && ItinData -> getNumMicroOps ( Class ) < <NUM_LIT> ) return getNumMicroOps ( ItinData , MI ) ; unsigned Latency = ItinData -> getStageLatency ( Class ) ;

unsigned DefAlign = MI . hasOneMemOperand ( ) ? ( * MI . memoperands_begin ( ) ) -> getAlign ( ) . value ( ) : <NUM_LIT> ;


<s> if ( PIdx == - <NUM_LIT> ) { PredReg = <NUM_LIT> ; return <STR_LIT> ; }

PredReg = MI . getOperand ( PIdx + <NUM_LIT> ) . getReg ( ) ;


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumRegs = MI . getNumOperands ( ) - Desc . getNumOperands ( ) ; return ( NumRegs / <NUM_LIT> ) + ( NumRegs % <NUM_LIT> ) + <NUM_LIT> ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : {

unsigned NumRegs = MI . getNumOperands ( ) - Desc . getNumOperands ( ) + <NUM_LIT> ;


<s> return Latency ; } if ( DefMO . isImplicit ( ) || UseMI . getOperand ( UseIdx ) . isImplicit ( ) ) return - <NUM_LIT> ; unsigned DefAlign = DefMI . hasOneMemOperand ( ) ? ( * DefMI . memoperands_begin ( ) ) -> getAlign ( ) . value ( ) : <NUM_LIT> ; unsigned UseAlign = UseMI . hasOneMemOperand ( ) ? ( * UseMI . memoperands_begin ( ) ) -> getAlign ( ) . value ( ) : <NUM_LIT> ; int Latency = getOperandLatency ( ItinData , DefMCID , DefIdx , DefAlign , UseMCID , UseIdx , UseAlign ) ; if ( Latency < <NUM_LIT> ) return Latency ; int Adj = DefAdj + UseAdj ; Adj += adjustDefLatency ( Subtarget , DefMI , DefMCID , DefAlign ) ; if ( Adj >= <NUM_LIT> || ( int ) Latency > - Adj ) {


<s> if ( C . Flags & UnsafeRegsDead ) return false ; C . initLRU ( TRI ) ; LiveRegUnits LRU = C . LRU ; return ( ! LRU . available ( <STR_LIT> ) || ! LRU . available ( <STR_LIT> ) ) ; } ; if ( ! ( FlagsSetInAll & UnsafeRegsDead ) ) { llvm :: erase_if ( RepeatedSequenceLocs , CantGuaranteeValueAcrossCall ) ; if ( RepeatedSequenceLocs . size ( ) < <NUM_LIT> ) return outliner :: OutlinedFunction ( ) ; } unsigned LastInstrOpcode = RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> getOpcode ( ) ; auto SetCandidateCallInfo = [ & RepeatedSequenceLocs ] ( unsigned CallID , unsigned NumBytesForCall ) { for ( outliner :: Candidate & C : RepeatedSequenceLocs ) C . setCallInfo ( CallID , NumBytesForCall ) ; } ; OutlinerCosts Costs ( Subtarget ) ; unsigned FrameID = MachineOutlinerDefault ; unsigned NumBytesToCreateFrame = Costs . FrameDefault ; if ( RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> isTerminator ( ) ) { FrameID = MachineOutlinerTailCall ; NumBytesToCreateFrame = Costs . FrameTailCall ; SetCandidateCallInfo ( MachineOutlinerTailCall , Costs . CallTailCall ) ; } else if ( LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> ) { FrameID = MachineOutlinerThunk ; NumBytesToCreateFrame = Costs . FrameThunk ; SetCandidateCallInfo ( MachineOutlinerThunk , Costs . CallThunk ) ; } else { unsigned NumBytesNoStackCalls = <NUM_LIT> ; std :: vector < outliner :: Candidate > CandidatesWithoutStackFixups ; for ( outliner :: Candidate & C : RepeatedSequenceLocs ) { C . initLRU ( TRI ) ; const auto Last = C . getMBB ( ) -> rbegin ( ) ; const bool LRIsAvailable = C . getMBB ( ) -> isReturnBlock ( ) && ! Last -> isCall ( ) ? isLRAvailable ( TRI , Last , ( MachineBasicBlock :: reverse_iterator ) C . front ( ) ) : C . LRU . available ( <STR_LIT> ) ; if ( LRIsAvailable ) { FrameID = MachineOutlinerNoLRSave ; NumBytesNoStackCalls += Costs . CallNoLRSave ; C . setCallInfo ( MachineOutlinerNoLRSave , Costs . CallNoLRSave ) ; CandidatesWithoutStackFixups . push_back ( C ) ; } else if ( findRegisterToSaveLRTo ( C ) ) {


<s> unsigned SequenceSize = std :: accumulate ( FirstCand . front ( ) , std :: next ( FirstCand . back ( ) ) , <NUM_LIT> , [ this ] ( unsigned Sum , const MachineInstr & MI ) { return Sum + getInstSizeInBytes ( MI ) ; } ) ; unsigned FlagsSetInAll = <NUM_LIT> ; const TargetRegisterInfo & TRI = getRegisterInfo ( ) ; std :: for_each ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , [ & FlagsSetInAll ] ( outliner :: Candidate & C ) { FlagsSetInAll &= C . Flags ; } ) ; auto CantGuaranteeValueAcrossCall = [ & TRI ] ( outliner :: Candidate & C ) { if ( C . Flags & UnsafeRegsDead ) return false ; C . initLRU ( TRI ) ; LiveRegUnits LRU = C . LRU ; return ( ! LRU . available ( <STR_LIT> ) || ! LRU . available ( <STR_LIT> ) ) ; } ; if ( ! ( FlagsSetInAll & UnsafeRegsDead ) ) { llvm :: erase_if ( RepeatedSequenceLocs , CantGuaranteeValueAcrossCall ) ; if ( RepeatedSequenceLocs . size ( ) < <NUM_LIT> ) return outliner :: OutlinedFunction ( ) ; } unsigned LastInstrOpcode = RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> getOpcode ( ) ; auto SetCandidateCallInfo = [ & RepeatedSequenceLocs ] ( unsigned CallID , unsigned NumBytesForCall ) { for ( outliner :: Candidate & C : RepeatedSequenceLocs ) C . setCallInfo ( CallID , NumBytesForCall ) ; } ; OutlinerCosts Costs ( Subtarget ) ; unsigned FrameID = MachineOutlinerDefault ; unsigned NumBytesToCreateFrame = Costs . FrameDefault ; if ( RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> isTerminator ( ) ) { FrameID = MachineOutlinerTailCall ;

NumBytesToCreateFrame = Costs . FrameTailCall ;


<s> if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) return outliner :: InstrType :: Illegal ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) return outliner :: InstrType :: Illegal ; const MCInstrDesc & MCID = MI . getDesc ( ) ; uint64_t MIFlags = MCID . TSFlags ; if ( ( MIFlags & <STR_LIT> ) == <STR_LIT> ) return outliner :: InstrType :: Illegal ; if ( MI . isTerminator ( ) ) { if ( isPredicated ( MI ) ) return outliner :: InstrType :: Illegal ; if ( MI . getParent ( ) -> succ_empty ( ) ) return outliner :: InstrType :: Legal ; return outliner :: InstrType :: Illegal ; } for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return outliner :: InstrType :: Illegal ; } if ( MI . readsRegister ( <STR_LIT> , TRI ) || MI . readsRegister ( <STR_LIT> , TRI ) ) return outliner :: InstrType :: Illegal ; if ( MI . isCall ( ) ) { const Function * Callee = nullptr ; for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isGlobal ( ) ) { Callee = dyn_cast < Function > ( MOP . getGlobal ( ) ) ; break ; } } if ( Callee && ( Callee -> getName ( ) == <STR_LIT> || Callee -> getName ( ) == <STR_LIT> || Callee -> getName ( ) == <STR_LIT> ) ) return outliner :: InstrType :: Illegal ; auto UnknownCallOutlineType = outliner :: InstrType :: Illegal ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) UnknownCallOutlineType = outliner :: InstrType :: LegalTerminator ;

if ( ! Callee ) return UnknownCallOutlineType ;


<s> for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isGlobal ( ) ) { Callee = dyn_cast < Function > ( MOP . getGlobal ( ) ) ; break ; } } if ( Callee && ( Callee -> getName ( ) == <STR_LIT> || Callee -> getName ( ) == <STR_LIT> || Callee -> getName ( ) == <STR_LIT> ) ) return outliner :: InstrType :: Illegal ; auto UnknownCallOutlineType = outliner :: InstrType :: Illegal ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) UnknownCallOutlineType = outliner :: InstrType :: LegalTerminator ; if ( ! Callee ) return UnknownCallOutlineType ; MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; MachineFunction * CalleeMF = MF -> getMMI ( ) . getMachineFunction ( * Callee ) ; if ( ! CalleeMF ) return UnknownCallOutlineType ; MachineFrameInfo & MFI = CalleeMF -> getFrameInfo ( ) ; if ( ! MFI . isCalleeSavedInfoValid ( ) || MFI . getStackSize ( ) > <NUM_LIT> || MFI . getNumObjects ( ) > <NUM_LIT> ) return UnknownCallOutlineType ; return outliner :: InstrType :: Legal ; } if ( MI . modifiesRegister ( <STR_LIT> , TRI ) || MI . modifiesRegister ( <STR_LIT> , TRI ) ) return outliner :: InstrType :: Illegal ; if ( MI . modifiesRegister ( <STR_LIT> , TRI ) || MI . readsRegister ( <STR_LIT> , TRI ) ) { bool MightNeedStackFixUp = ( Flags & ( MachineOutlinerMBBFlags :: LRUnavailableSomewhere | MachineOutlinerMBBFlags :: HasCalls ) ) ; if ( ! MightNeedStackFixUp ) return outliner :: InstrType :: Legal ; if ( MI . modifiesRegister ( <STR_LIT> , TRI ) ) return outliner :: InstrType :: Illegal ; if ( checkAndUpdateStackOffset ( & MI , Subtarget . getStackAlignment ( ) . value ( ) , false ) ) return outliner :: InstrType :: Legal ; return outliner :: InstrType :: Illegal ; }

if ( MI . readsRegister ( <STR_LIT> , TRI ) || MI . modifiesRegister ( <STR_LIT> , TRI ) ) return outliner :: InstrType :: Illegal ;


<s> unsigned <ISA_LIT>BaseInstrInfo :: getPartialRegUpdateClearance ( const MachineInstr & MI , unsigned OpNum , const TargetRegisterInfo * TRI ) const { auto PartialUpdateClearance = Subtarget . getPartialUpdateClearance ( ) ; if ( ! PartialUpdateClearance ) return <NUM_LIT> ; assert ( TRI && <STR_LIT> ) ; const MachineOperand & MO = MI . getOperand ( OpNum ) ; if ( MO . readsReg ( ) ) return <NUM_LIT> ; Register Reg = MO . getReg ( ) ; int UseOp = - <NUM_LIT> ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> :


<s> bool llvm :: HasLowerConstantMaterializationCost ( unsigned Val1 , unsigned Val2 , const <ISA_LIT>Subtarget * Subtarget , bool ForCodesize ) { unsigned Cost1 = ConstantMaterializationCost ( Val1 , Subtarget , ForCodesize ) ;

unsigned Cost2 = ConstantMaterializationCost ( Val2 , Subtarget , ForCodesize ) ;


<s> unsigned Cost2 = ConstantMaterializationCost ( Val2 , Subtarget , ForCodesize ) ; if ( Cost1 < Cost2 ) return true ;


<s> if ( C . CallConstructionID == MachineOutlinerTailCall ) { Opc = isThumb ? Subtarget . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; if ( isThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; It = MBB . insert ( It , MIB ) ; return It ; } Opc = isThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder CallMIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) ; if ( isThumb ) CallMIB . add ( predOps ( <STR_LIT> ) ) ; CallMIB . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; if ( C . CallConstructionID == MachineOutlinerNoLRSave || C . CallConstructionID == MachineOutlinerThunk ) { It = MBB . insert ( It , CallMIB ) ; return It ; }

const <ISA_LIT>FunctionInfo & AFI = * C . getMF ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ;


<s> const MachineOperand & Op0 = MI . getOperand ( <NUM_LIT> ) ; if ( ! Op0 . isReg ( ) || Reg != Op0 . getReg ( ) ) return None ; if ( Opcode == <STR_LIT> ) Sign = - <NUM_LIT> ; else if ( Opcode != <STR_LIT> ) return None ; if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return None ;

Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) * Sign ;


<s> const Function & F = MF . getFunction ( ) ; if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; if ( F . hasSection ( ) ) return false ; if ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumb1OnlyFunction ( ) ) return false ; return true ;


<s> if ( F . hasSection ( ) ) return false ; if ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumb1OnlyFunction ( ) ) return false ; return true ;


<s> } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; }


<s> bool R12AvailableInBlock = LRU . available ( <STR_LIT> ) ; bool CPSRAvailableInBlock = LRU . available ( <STR_LIT> ) ; if ( R12AvailableInBlock && CPSRAvailableInBlock ) Flags |= MachineOutlinerMBBFlags :: UnsafeRegsDead ; LRU . addLiveOuts ( MBB ) ; if ( R12AvailableInBlock && ! LRU . available ( <STR_LIT> ) ) return false ; if ( CPSRAvailableInBlock && ! LRU . available ( <STR_LIT> ) ) return false ; if ( any_of ( MBB , [ ] ( MachineInstr & MI ) { return MI . isCall ( ) ; } ) ) Flags |= MachineOutlinerMBBFlags :: HasCalls ; bool LRIsAvailable = MBB . isReturnBlock ( ) && ! MBB . back ( ) . isCall ( ) ? isLRAvailable ( getRegisterInfo ( ) , MBB . rbegin ( ) , MBB . rend ( ) ) : LRU . available ( <STR_LIT> ) ;

if ( ! LRIsAvailable ) Flags |= MachineOutlinerMBBFlags :: LRUnavailableSomewhere ;


<s> if ( MI . isBundle ( ) ) return false ; if ( ! isEligibleForITBlock ( & MI ) ) return false ; const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>FunctionInfo * AFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) return false ; const <ISA_LIT>Subtarget & ST = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ;

if ( ST . hardenSlsRetBr ( ) && isIndirectControlFlowNotComingBack ( MI ) ) return false ;


<s> const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>FunctionInfo * AFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) return false ; const <ISA_LIT>Subtarget & ST = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ST . hardenSlsRetBr ( ) && isIndirectControlFlowNotComingBack ( MI ) ) return false ; if ( ST . hardenSlsBlr ( ) && isIndirectCall ( MI ) ) return false ; if ( AFI -> isThumb2Function ( ) ) { if ( getSubtarget ( ) . restrictIT ( ) ) return isV8EligibleForIT ( & MI ) ; } return true ;


<s> return isVCTP ( & MI ) && ! isPredicated ( MI ) ;


<s> if ( CmpI -> getOpcode ( ) == <STR_LIT> && OI -> getOpcode ( ) == <STR_LIT> && ( ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) || ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ) ) { IsThumb1 = true ; return true ; } if ( ( CmpI -> getOpcode ( ) == <STR_LIT> || CmpI -> getOpcode ( ) == <STR_LIT> ) && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getImm ( ) == ImmValue ) { IsThumb1 = false ; return true ; } if ( CmpI -> getOpcode ( ) == <STR_LIT> && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getImm ( ) == ImmValue ) { IsThumb1 = true ; return true ; } if ( ( CmpI -> getOpcode ( ) == <STR_LIT> || CmpI -> getOpcode ( ) == <STR_LIT> ) && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && OI -> getOperand ( <NUM_LIT> ) . isReg ( ) && OI -> getOperand ( <NUM_LIT> ) . isReg ( ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) { IsThumb1 = false ; return true ; } if ( CmpI -> getOpcode ( ) == <STR_LIT> && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) { IsThumb1 = true ;


<s> if ( ( CmpI -> getOpcode ( ) == <STR_LIT> || CmpI -> getOpcode ( ) == <STR_LIT> ) && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && OI -> getOperand ( <NUM_LIT> ) . isReg ( ) && OI -> getOperand ( <NUM_LIT> ) . isReg ( ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) { IsThumb1 = false ; return true ; } if ( CmpI -> getOpcode ( ) == <STR_LIT> && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) { IsThumb1 = true ; return true ; } return false ;


<s> MachineBasicBlock :: const_iterator I = MI ; while ( ++ I != MBB -> end ( ) && I -> isDebugInstr ( ) ) ;

if ( I != MBB -> end ( ) && I -> getOpcode ( ) == <STR_LIT> ) return true ;


<s> return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ;


<s> case <STR_LIT> : case <STR_LIT> : if ( CmpMask != MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) return false ; if ( SrcReg == MI -> getOperand ( CommonUse ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ) return true ; break ; }


<s> if ( CmpMask != MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) return false ; if ( SrcReg == MI -> getOperand ( CommonUse ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ) return true ; break ; } return false ;


<s> bool isSafe = false ; I = CmpInstr ; E = CmpInstr . getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } <STR_LIT> CC ; bool IsInstrVSel = true ; switch ( Instr . getOpcode ( ) ) { default : IsInstrVSel = false ; CC = ( <STR_LIT> ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; } if ( SubAdd ) { unsigned Opc = SubAdd -> getOpcode ( ) ; bool IsSub = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; unsigned OpI = Opc != <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( ! IsSub || ( SrcReg2 != <NUM_LIT> && SubAdd -> getOperand ( OpI ) . getReg ( ) == SrcReg2 && SubAdd -> getOperand ( OpI + <NUM_LIT> ) . getReg ( ) == SrcReg ) ) { if ( IsInstrVSel ) return false ; <STR_LIT> NewCC = ( IsSub ? getSwappedCondition ( CC ) : getCmpToAddCondition ( CC ) ) ; if ( NewCC == <STR_LIT> ) return false ; OperandsToUpdate . push_back ( std :: make_pair ( & ( ( * I ) . getOperand ( IO - <NUM_LIT> ) ) , NewCC ) ) ; } } else { switch ( CC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } } } }


<s> for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . add ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( <STR_LIT> ( <STR_LIT> ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . add ( MI . getOperand ( <NUM_LIT> ) ) ; if ( NewMI -> hasOptionalDef ( ) ) NewMI . add ( condCodeOp ( ) ) ; FalseReg . setImplicit ( ) ; NewMI . add ( FalseReg ) ; NewMI -> tieOperands ( <NUM_LIT> , NewMI -> getNumOperands ( ) - <NUM_LIT> ) ; SeenMIs . insert ( NewMI ) ; SeenMIs . erase ( DefMI ) ; if ( DefMI -> getParent ( ) != MI . getParent ( ) ) NewMI -> clearKillInfo ( ) ; DefMI -> eraseFromParent ( ) ; return NewMI ;


<s> MachineInstr * DefMI = canFoldIntoMOVCC ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; bool Invert = ! DefMI ; if ( ! DefMI ) DefMI = canFoldIntoMOVCC ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; if ( ! DefMI ) return nullptr ; MachineOperand FalseReg = MI . getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * PreviousClass = MRI . getRegClass ( FalseReg . getReg ( ) ) ; if ( ! MRI . constrainRegClass ( DestReg , PreviousClass ) ) return nullptr ;

MachineInstrBuilder NewMI = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ;


<s> OutlinerCosts ( const <ISA_LIT>Subtarget & target ) : CallTailCall ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , FrameTailCall ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , CallThunk ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , FrameThunk ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , CallNoLRSave ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , FrameNoLRSave ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , CallRegSave ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , FrameRegSave ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , CallDefault ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , FrameDefault ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , SaveRestoreLROnStack ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) {


<s> const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( MCID . TSFlags & <STR_LIT> ) { assert ( MCID . OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) && <STR_LIT> ) ; assert ( ( MI . getOperand ( <NUM_LIT> ) . isDead ( ) || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) && <STR_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; } return true ; }


<s> unsigned Size = getInstSizeInBytes ( MI ) ;

if ( Subtarget . isThumb2 ( ) ) Size /= <NUM_LIT> ;


<s> const MachineConstantPoolEntry & MCPE0 = MCP -> getConstants ( ) [ CPI0 ] ; const MachineConstantPoolEntry & MCPE1 = MCP -> getConstants ( ) [ CPI1 ] ; bool is<ISA_LIT>CP0 = MCPE0 . isMachineConstantPoolEntry ( ) ; bool is<ISA_LIT>CP1 = MCPE1 . isMachineConstantPoolEntry ( ) ; if ( is<ISA_LIT>CP0 && is<ISA_LIT>CP1 ) { <ISA_LIT>ConstantPoolValue * ACPV0 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE0 . Val . MachineCPVal ) ; <ISA_LIT>ConstantPoolValue * ACPV1 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE1 . Val . MachineCPVal ) ; return ACPV0 -> hasSameValue ( ACPV1 ) ; } else if ( ! is<ISA_LIT>CP0 && ! is<ISA_LIT>CP1 ) { return MCPE0 . Val . ConstVal == MCPE1 . Val . ConstVal ; } return false ; } else if ( Opcode == <STR_LIT> ) { if ( MI1 . getOpcode ( ) != Opcode ) return false ; if ( MI0 . getNumOperands ( ) != MI1 . getNumOperands ( ) ) return false ; Register Addr0 = MI0 . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Addr1 = MI1 . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Addr0 != Addr1 ) { if ( ! MRI || ! Register :: isVirtualRegister ( Addr0 ) || ! Register :: isVirtualRegister ( Addr1 ) ) return false ; MachineInstr * Def0 = MRI -> getVRegDef ( Addr0 ) ; MachineInstr * Def1 = MRI -> getVRegDef ( Addr1 ) ;

if ( ! produceSameValue ( * Def0 , * Def1 , MRI ) ) return false ;


<s> case <STR_LIT> : { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CPI = Orig . getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; BuildMI ( MBB , I , Orig . getDebugLoc ( ) , get ( Opcode ) , DestReg ) . addConstantPoolIndex ( CPI ) . addImm ( PCLabelId ) . cloneMemRefs ( Orig ) ; break ; }


<s> void <ISA_LIT>BaseInstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register DestReg , unsigned SubIdx , const MachineInstr & Orig , const TargetRegisterInfo & TRI ) const { unsigned Opcode = Orig . getOpcode ( ) ; switch ( Opcode ) { default : { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( & Orig ) ; MI -> substituteRegister ( Orig . getOperand ( <NUM_LIT> ) . getReg ( ) , DestReg , SubIdx , TRI ) ; MBB . insert ( I , MI ) ; break ; } case <STR_LIT> : case <STR_LIT> : { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CPI = Orig . getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ;

BuildMI ( MBB , I , Orig . getDebugLoc ( ) , get ( Opcode ) , DestReg ) . addConstantPoolIndex ( CPI ) . addImm ( PCLabelId ) . cloneMemRefs ( Orig ) ;


<s> MachineInstrBuilder MIB = BuildMI ( MBB , It , DebugLoc ( ) , get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ;

if ( ! Subtarget . isThumb ( ) ) MIB . addReg ( <NUM_LIT> ) ;


<s> void <ISA_LIT>BaseInstrInfo :: restoreLRFromStack ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator It ) const { unsigned Opc = Subtarget . isThumb ( ) ? <STR_LIT> : <STR_LIT> ;

MachineInstrBuilder MIB = BuildMI ( MBB , It , DebugLoc ( ) , get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ;


<s> Offset = - Offset ; isSub = true ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; } if ( <STR_LIT> ( Offset ) != - <NUM_LIT> ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; Offset = <NUM_LIT> ; return true ; } unsigned RotAmt = <STR_LIT> ( Offset ) ; unsigned ThisImmVal = Offset & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; Offset &= ~ ThisImmVal ; assert ( <STR_LIT> ( ThisImmVal ) != - <NUM_LIT> && <STR_LIT> ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( ThisImmVal ) ; } else { unsigned ImmIdx = <NUM_LIT> ; int InstrOffs = <NUM_LIT> ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; switch ( AddrMode ) { case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : return false ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ;


<s> unsigned Opc = Subtarget . isThumb ( ) ? <STR_LIT> : <STR_LIT> ; int Align = - Subtarget . getStackAlignment ( ) . value ( ) ;

BuildMI ( MBB , It , DebugLoc ( ) , get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> ) . addImm ( Align ) . add ( predOps ( <STR_LIT> ) ) ;


<s> void <ISA_LIT>BaseInstrInfo :: saveLROnStack ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator It ) const { unsigned Opc = Subtarget . isThumb ( ) ? <STR_LIT> : <STR_LIT> ; int Align = - Subtarget . getStackAlignment ( ) . value ( ) ;


if ( Next != MI . getParent ( ) -> end ( ) && analyzeCompare ( * Next , SrcReg , SrcReg2 , CmpMask , CmpValue ) && isRedundantFlagInstr ( & * Next , SrcReg , SrcReg2 , CmpValue , & MI , IsThumb1 ) ) return false ;


<s> bool <ISA_LIT>BaseInstrInfo :: shouldSink ( const MachineInstr & MI ) const { if ( isPredicated ( MI ) ) return true ; MachineBasicBlock :: const_iterator Next = & MI ; ++ Next ; Register SrcReg , SrcReg2 ; int64_t CmpMask , CmpValue ; bool IsThumb1 ; if ( Next != MI . getParent ( ) -> end ( ) && analyzeCompare ( * Next , SrcReg , SrcReg2 , CmpMask , CmpValue ) && isRedundantFlagInstr ( & * Next , SrcReg , SrcReg2 , CmpValue , & MI , IsThumb1 ) ) return false ;


<s> const TargetRegisterClass * RegClass ; if ( IsVFPPushPop ) { RegsNeeded = NumBytes / <NUM_LIT> ; RegClass = & <STR_LIT> ; } else { RegsNeeded = NumBytes / <NUM_LIT> ; RegClass = & <STR_LIT> ; } SmallVector < MachineOperand , <NUM_LIT> > RegList ; unsigned FirstRegEnc = - <NUM_LIT> ; const TargetRegisterInfo * TRI = MF . getRegInfo ( ) . getTargetRegisterInfo ( ) ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx ; -- i ) { MachineOperand & MO = MI -> getOperand ( i ) ; RegList . push_back ( MO ) ; if ( MO . isReg ( ) && ! MO . isImplicit ( ) && TRI -> getEncodingValue ( MO . getReg ( ) ) < FirstRegEnc ) FirstRegEnc = TRI -> getEncodingValue ( MO . getReg ( ) ) ; } const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( int CurRegEnc = FirstRegEnc - <NUM_LIT> ; CurRegEnc >= <NUM_LIT> && RegsNeeded ; -- CurRegEnc ) { unsigned CurReg = RegClass -> getRegister ( CurRegEnc ) ; if ( IsT1PushPop && CurRegEnc > TRI -> getEncodingValue ( <STR_LIT> ) ) continue ; if ( ! IsPop ) { RegList . push_back ( MachineOperand :: CreateReg ( CurReg , false , false , false , false , true ) ) ; -- RegsNeeded ; continue ; } if ( isCalleeSavedRegister ( CurReg , CSRegs ) || MI -> getParent ( ) -> computeRegisterLiveness ( TRI , CurReg , MI ) != MachineBasicBlock :: LQR_Dead ) { if ( IsVFPPushPop ) return false ; else continue ; } RegList . push_back ( MachineOperand :: CreateReg ( CurReg , true , false , false , true ) ) ; -- RegsNeeded ; } if ( RegsNeeded > <NUM_LIT> ) return false ;

for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx ; -- i ) MI -> RemoveOperand ( i ) ;


<s> assert ( ( IsT1PushPop || ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; if ( NumBytes % ( IsVFPPushPop ? <NUM_LIT> : <NUM_LIT> ) != <NUM_LIT> ) return false ; int RegListIdx = IsT1PushPop ? <NUM_LIT> : <NUM_LIT> ; unsigned RegsNeeded ; const TargetRegisterClass * RegClass ; if ( IsVFPPushPop ) { RegsNeeded = NumBytes / <NUM_LIT> ; RegClass = & <STR_LIT> ; } else { RegsNeeded = NumBytes / <NUM_LIT> ; RegClass = & <STR_LIT> ; } SmallVector < MachineOperand , <NUM_LIT> > RegList ; unsigned FirstRegEnc = - <NUM_LIT> ; const TargetRegisterInfo * TRI = MF . getRegInfo ( ) . getTargetRegisterInfo ( ) ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx ; -- i ) { MachineOperand & MO = MI -> getOperand ( i ) ; RegList . push_back ( MO ) ; if ( MO . isReg ( ) && ! MO . isImplicit ( ) && TRI -> getEncodingValue ( MO . getReg ( ) ) < FirstRegEnc ) FirstRegEnc = TRI -> getEncodingValue ( MO . getReg ( ) ) ;


<s> assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps ( <STR_LIT> ) ) ; return ; } else if ( SrcReg == <STR_LIT> ) { assert ( <STR_LIT> . contains ( DestReg ) ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps ( <STR_LIT> ) ) ; return ; } else if ( DestReg == <STR_LIT> ) { assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps ( <STR_LIT> ) ) ; return ; } else if ( SrcReg == <STR_LIT> ) { assert ( <STR_LIT> . contains ( DestReg ) ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps ( <STR_LIT> ) ) ; return ; } assert ( Opc && <STR_LIT> ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; MachineInstrBuilder Mov ; if ( TRI -> regsOverlap ( SrcReg , TRI -> getSubReg ( DestReg , BeginIdx ) ) ) { BeginIdx = BeginIdx + ( ( SubRegs - <NUM_LIT> ) * Spacing ) ; Spacing = - Spacing ; } SmallSet < unsigned , <NUM_LIT> > DstRegs ; for ( unsigned i = <NUM_LIT> ; i != SubRegs ; ++ i ) { Register Dst = TRI -> getSubReg ( DestReg , BeginIdx + i * Spacing ) ; Register Src = TRI -> getSubReg ( SrcReg , BeginIdx + i * Spacing ) ; assert ( Dst && Src && <STR_LIT> ) ; assert ( ! DstRegs . count ( Src ) && <STR_LIT> ) ; DstRegs . insert ( Dst ) ; Mov = BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( Opc ) , Dst ) . addReg ( Src ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { Mov . addReg ( Src ) ; } if ( Opc == <STR_LIT> ) addUnpredicatedMveVpredROp ( Mov , Dst ) ; else Mov = Mov . add ( predOps ( <STR_LIT> ) ) ; if ( Opc == <STR_LIT> ) Mov = Mov . add ( condCodeOp ( ) ) ; } Mov -> addRegisterDefined ( DestReg , TRI ) ; if ( KillSrc ) Mov -> addRegisterKilled ( SrcReg , TRI ) ;


<s> } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = Subtarget . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; Spacing = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; Spacing = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; Spacing = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) && ! Subtarget . hasFP64 ( ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( SrcReg == <STR_LIT> ) { copyFromCPSR ( MBB , I , DestReg , KillSrc , Subtarget ) ; return ; } else if ( DestReg == <STR_LIT> ) { copyToCPSR ( MBB , I , SrcReg , KillSrc , Subtarget ) ; return ; } else if ( DestReg == <STR_LIT> ) { assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps ( <STR_LIT> ) ) ; return ; } else if ( SrcReg == <STR_LIT> ) { assert ( <STR_LIT> . contains ( DestReg ) ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps ( <STR_LIT> ) ) ;


<s> loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , Align ) ; switch ( RC -> getSize ( ) ) { case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . needsStackRealignment ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) {


<s> break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . needsStackRealignment ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; } } else llvm_unreachable ( <STR_LIT> ) ;


<s> case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . needsStackRealignment ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ;

MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ;


<s> const MachineFunction * MF = MBB . getParent ( ) ; const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . getSize ( ) ) return MCID . getSize ( ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) return getInlineAsmLength ( MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MAI ) ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { default : return <NUM_LIT> ; case TargetOpcode :: BUNDLE : return getInstBundleLength ( MI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> return ( Subtarget . getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ;


<s> MachineOperand FalseReg = MI -> getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * PreviousClass = MRI . getRegClass ( FalseReg . getReg ( ) ) ; if ( ! MRI . constrainRegClass ( DestReg , PreviousClass ) ) return nullptr ; MachineInstrBuilder NewMI = BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . addOperand ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( <STR_LIT> ( <STR_LIT> ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMI -> hasOptionalDef ( ) ) AddDefaultCC ( NewMI ) ; FalseReg . setImplicit ( ) ; NewMI . addOperand ( FalseReg ) ;

NewMI -> tieOperands ( <NUM_LIT> , NewMI -> getNumOperands ( ) - <NUM_LIT> ) ;


<s> bool <ISA_LIT>BaseInstrInfo :: AnalyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( -- I ) ) return false ; MachineInstr * LastInst = I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( -- I ) ) { if ( isUncondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isCondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ;

if ( isCondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) {


<s> <ISA_LIT>BaseInstrInfo :: <ISA_LIT>BaseInstrInfo ( const <ISA_LIT>Subtarget & STI ) : TargetInstrInfoImpl ( <ISA_LIT>Insts , array_lengthof ( <ISA_LIT>Insts ) ) , Subtarget ( STI ) {


<s> } std :: vector < MachineInstr * > NewMIs ; if ( isPre ) { if ( isLoad ) MemMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( MemOpc ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( WBReg ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( Pred ) ; else MemMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( MemOpc ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( WBReg ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( Pred ) ; NewMIs . push_back ( MemMI ) ; NewMIs . push_back ( UpdateMI ) ; } else { if ( isLoad ) MemMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( MemOpc ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( BaseReg ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( Pred ) ; else MemMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( MemOpc ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( BaseReg ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( Pred ) ; if ( WB . isDead ( ) ) UpdateMI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; NewMIs . push_back ( UpdateMI ) ; NewMIs . push_back ( MemMI ) ; } if ( LV ) { for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . getReg ( ) && TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) { unsigned Reg = MO . getReg ( ) ; LiveVariables :: VarInfo & VI = LV -> getVarInfo ( Reg ) ;


<s> DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( DestRC == <STR_LIT> ) DestRC = <STR_LIT> ; if ( SrcRC == <STR_LIT> ) SrcRC = <STR_LIT> ; if ( DestRC != SrcRC ) { if ( DestRC -> getSize ( ) != SrcRC -> getSize ( ) ) return false ; if ( DestRC -> getSize ( ) != <NUM_LIT> && DestRC -> getSize ( ) != <NUM_LIT> ) return false ; } if ( DestRC == <STR_LIT> ) {

AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ) ;


<s> AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; } else if ( DestRC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; } else if ( DestRC == <STR_LIT> || DestRC == <STR_LIT> || SrcRC == <STR_LIT> || SrcRC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; } else if ( DestRC == <STR_LIT> || DestRC == <STR_LIT> || DestRC == <STR_LIT> ) {


<s> <ISA_LIT>ConstantPoolValue * NewCPV = <NUM_LIT> ; if ( ACPV -> isGlobalValue ( ) ) NewCPV = new <ISA_LIT>ConstantPoolValue ( ACPV -> getGV ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isExtSymbol ( ) ) NewCPV = new <ISA_LIT>ConstantPoolValue ( MF . getFunction ( ) -> getContext ( ) , ACPV -> getSymbol ( ) , PCLabelId , <NUM_LIT> ) ;

else if ( ACPV -> isBlockAddress ( ) ) NewCPV = new <ISA_LIT>ConstantPoolValue ( ACPV -> getBlockAddress ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ;


<s> unsigned Opc = isSub ? <STR_LIT> : <STR_LIT> ;

BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ThisVal ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ;


<s> MachineInstr * <ISA_LIT>BaseInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const {


<s> case <STR_LIT> : { unsigned EntrySize = ( Opc == <STR_LIT> ) ? <NUM_LIT> : ( ( Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned NumOps = TID . getNumOperands ( ) ; MachineOperand JTOP = MI -> getOperand ( NumOps - ( TID . isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOP . getIndex ( ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; assert ( MJTI != <NUM_LIT> ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; assert ( JTI < JT . size ( ) ) ; unsigned InstSize = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned NumEntries = getNumJTEntries ( JT , JTI ) ;

if ( Opc == <STR_LIT> && ( NumEntries & <NUM_LIT> ) ) ++ NumEntries ;


<s> DebugLoc dl = DebugLoc :: getUnknownLoc ( ) ; <ISA_LIT>FunctionInfo * AFI = MBB . getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; int BOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : ( AFI -> isThumb2Function ( ) ? <STR_LIT> : <STR_LIT> ) ; int BccOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : ( AFI -> isThumb2Function ( ) ? <STR_LIT> : <STR_LIT> ) ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) BuildMI ( & MBB , dl , get ( BOpc ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , dl , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; return <NUM_LIT> ;


<s> int BccOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : ( AFI -> isThumb2Function ( ) ? <STR_LIT> : <STR_LIT> ) ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) BuildMI ( & MBB , dl , get ( BOpc ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , dl , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; return <NUM_LIT> ; } BuildMI ( & MBB , dl , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; BuildMI ( & MBB , dl , get ( BOpc ) ) . addMBB ( FBB ) ; return <NUM_LIT> ;


<s> default : break ; case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; }


<s> case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; }


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { assert ( MI . getDesc ( ) . getNumOperands ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return true ;


<s> } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { assert ( MI . getDesc ( ) . getNumOperands ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ;

SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , MFI . getObjectSize ( FI ) , Align ) ; if ( RC == <STR_LIT> ) RC = <STR_LIT> ; if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( RC == <STR_LIT> || RC == <STR_LIT> || RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else { assert ( ( RC == <STR_LIT> || RC == <STR_LIT> || RC == <STR_LIT> ) && <STR_LIT> ) ; if ( Align >= <NUM_LIT> && ( getRegisterInfo ( ) . canRealignStack ( MF ) ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ;


<s> } else if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else { assert ( ( RC == <STR_LIT> || RC == <STR_LIT> || RC == <STR_LIT> ) && <STR_LIT> ) ; if ( Align >= <NUM_LIT> && ( getRegisterInfo ( ) . canRealignStack ( MF ) ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ;


<s> int CPI1 = MO1 . getIndex ( ) ; const MachineConstantPoolEntry & MCPE0 = MCP -> getConstants ( ) [ CPI0 ] ; const MachineConstantPoolEntry & MCPE1 = MCP -> getConstants ( ) [ CPI1 ] ; <ISA_LIT>ConstantPoolValue * ACPV0 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE0 . Val . MachineCPVal ) ; <ISA_LIT>ConstantPoolValue * ACPV1 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE1 . Val . MachineCPVal ) ;

return ACPV0 -> hasSameValue ( ACPV1 ) ;


<s> if ( MI1 -> getOpcode ( ) != Opcode ) return false ; if ( MI0 -> getNumOperands ( ) != MI1 -> getNumOperands ( ) ) return false ; const MachineOperand & MO0 = MI0 -> getOperand ( <NUM_LIT> ) ; const MachineOperand & MO1 = MI1 -> getOperand ( <NUM_LIT> ) ; if ( MO0 . getOffset ( ) != MO1 . getOffset ( ) ) return false ; const MachineFunction * MF = MI0 -> getParent ( ) -> getParent ( ) ; const MachineConstantPool * MCP = MF -> getConstantPool ( ) ; int CPI0 = MO0 . getIndex ( ) ;


<s> MachineInstrBuilder MIB = BuildMI ( MBB , I , Orig -> getDebugLoc ( ) , get ( Opcode ) , DestReg ) . addConstantPoolIndex ( CPI ) . addImm ( PCLabelId ) ; ( * MIB ) . setMemRefs ( Orig -> memoperands_begin ( ) , Orig -> memoperands_end ( ) ) ; break ; } } MachineInstr * NewMI = prior ( I ) ;

NewMI -> getOperand ( <NUM_LIT> ) . setSubReg ( SubIdx ) ;


<s> MachineBasicBlock :: iterator I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; return <NUM_LIT> ;


<s> unsigned <ISA_LIT>BaseInstrInfo :: RemoveBranch ( MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ;


<s> case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; break ; } Offset += InstrOffs * Scale ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( Offset < <NUM_LIT> ) { Offset = - Offset ; isSub = true ; } if ( NumBits > <NUM_LIT> ) { MachineOperand & ImmOp = MI . getOperand ( ImmIdx ) ; int ImmedOffset = Offset / Scale ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( unsigned ) Offset <= Mask * Scale ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; if ( isSub ) ImmedOffset |= <NUM_LIT> << NumBits ; ImmOp . ChangeToImmediate ( ImmedOffset ) ; Offset = <NUM_LIT> ; return true ; } ImmedOffset = ImmedOffset & Mask ; if ( isSub ) ImmedOffset |= <NUM_LIT> << NumBits ; ImmOp . ChangeToImmediate ( ImmedOffset ) ; Offset &= ~ ( Mask * Scale ) ; } }

Offset = ( isSub ) ? - Offset : Offset ;


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , MFI . getObjectSize ( FI ) , Align ) ; if ( RC == <STR_LIT> ) RC = <STR_LIT> ; if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( RC == <STR_LIT> || RC == <STR_LIT> || RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else { assert ( ( RC == <STR_LIT> || RC == <STR_LIT> ) && <STR_LIT> ) ;

if ( Align >= <NUM_LIT> && ( getRegisterInfo ( ) . canRealignStack ( MF ) ) ) {


<s> storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , MFI . getObjectSize ( FI ) , Align ) ; if ( RC == <STR_LIT> ) RC = <STR_LIT> ; if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( RC == <STR_LIT> || RC == <STR_LIT> || RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ;


<s> SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = ~ <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = ~ <NUM_LIT> ; CmpValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = ~ <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? <STR_LIT> : <STR_LIT> : isThumb ? Subtarget . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ; if ( isThumb && ! Call -> getOperand ( FuncOp ) . isReg ( ) ) MIB . add ( predOps ( <STR_LIT> ) ) ; Call -> eraseFromParent ( ) ; } auto IsNonTailCall = [ ] ( MachineInstr & MI ) { return MI . isCall ( ) && ! MI . isReturn ( ) ; } ; if ( std :: any_of ( MBB . instr_begin ( ) , MBB . instr_end ( ) , IsNonTailCall ) ) { MachineBasicBlock :: iterator It = MBB . begin ( ) ; MachineBasicBlock :: iterator Et = MBB . end ( ) ; if ( OF . FrameConstructionID == MachineOutlinerTailCall || OF . FrameConstructionID == MachineOutlinerThunk ) Et = std :: prev ( MBB . end ( ) ) ; if ( ! MBB . isLiveIn ( <STR_LIT> ) ) MBB . addLiveIn ( <STR_LIT> ) ; saveLROnStack ( MBB , It ) ; unsigned StackAlignment = Subtarget . getStackAlignment ( ) . value ( ) ; const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ;

const MCRegisterInfo * MRI = STI . getRegisterInfo ( ) ;


<s> ScheduleHazardRecognizer * <ISA_LIT>BaseInstrInfo :: CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAG * DAG ) const {

if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2Base ( ) ) return new <ISA_LIT>HazardRecognizer ( II , DAG ) ;


<s> CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAG * DAG ) const {


<s> SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; switch ( UseOpc ) { default : break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; } break ; case <STR_LIT> : case <STR_LIT> : { if ( UseOpc == <STR_LIT> && Commute ) return false ; const bool ToSP = DefMI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ; const unsigned t2ADD = ToSP ? <STR_LIT> : <STR_LIT> ; const unsigned t2SUB = ToSP ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( ImmVal ) ) NewUseOpc = UseOpc == <STR_LIT> ? t2ADD : t2SUB ; else if ( <STR_LIT> ( - ImmVal ) ) { ImmVal = - ImmVal ; NewUseOpc = UseOpc == <STR_LIT> ? t2SUB : t2ADD ; } else return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; break ; } case <STR_LIT> : case <STR_LIT> : if ( ! <STR_LIT> ( ImmVal ) ) return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; switch ( UseOpc ) { default : break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; } break ; } } } unsigned OpIdx = Commute ? <NUM_LIT> : <NUM_LIT> ; Register Reg1 = UseMI . getOperand ( OpIdx ) . getReg ( ) ; bool isKill = UseMI . getOperand ( OpIdx ) . isKill ( ) ; const TargetRegisterClass * TRC = MRI -> getRegClass ( Reg ) ; Register NewReg = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( NewUseOpc ) , NewReg ) . addReg ( Reg1 , getKillRegState ( isKill ) ) . addImm ( SOImmValV1 ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; UseMI . setDesc ( get ( NewUseOpc ) ) ;

UseMI . getOperand ( <NUM_LIT> ) . setReg ( NewReg ) ;


<s> bool <ISA_LIT>BaseInstrInfo :: FoldImmediate ( MachineInstr & UseMI , MachineInstr & DefMI , Register Reg , MachineRegisterInfo * MRI ) const { unsigned DefOpc = DefMI . getOpcode ( ) ; if ( DefOpc != <STR_LIT> && DefOpc != <STR_LIT> ) return false ; if ( ! DefMI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; if ( ! MRI -> hasOneNonDBGUse ( Reg ) ) return false ; const MCInstrDesc & DefMCID = DefMI . getDesc ( ) ; if ( DefMCID . hasOptionalDef ( ) ) { unsigned NumOps = DefMCID . getNumOperands ( ) ; const MachineOperand & MO = DefMI . getOperand ( NumOps - <NUM_LIT> ) ; if ( MO . getReg ( ) == <STR_LIT> && ! MO . isDead ( ) ) return false ; } const MCInstrDesc & UseMCID = UseMI . getDesc ( ) ; if ( UseMCID . hasOptionalDef ( ) ) { unsigned NumOps = UseMCID . getNumOperands ( ) ; if ( UseMI . getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; } unsigned UseOpc = UseMI . getOpcode ( ) ; unsigned NewUseOpc = <NUM_LIT> ; uint32_t ImmVal = ( uint32_t ) DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; uint32_t SOImmValV1 = <NUM_LIT> , SOImmValV2 = <NUM_LIT> ; bool Commute = false ; switch ( UseOpc ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Commute = UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) != Reg ; switch ( UseOpc ) { default : break ;