<s> bool RequiresBundling = STI -> isTargetWindows ( ) && IsAnAddressOperand ( MO ) ; MachineInstrBuilder LO16 , HI16 ; if ( ! STI -> hasV6T2Ops ( ) && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) { assert ( ! STI -> isTargetWindows ( ) && <STR_LIT> ) ; LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; unsigned ImmVal = ( unsigned ) MO . getImm ( ) ; unsigned SOImmValV1 = <STR_LIT> ( ImmVal ) ; unsigned SOImmValV2 = <STR_LIT> ( ImmVal ) ; LO16 = LO16 . addImm ( SOImmValV1 ) ; HI16 = HI16 . addImm ( SOImmValV2 ) ; LO16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; HI16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; LO16 . addImm ( Pred ) . addReg ( PredReg ) . add ( condCodeOp ( ) ) ; HI16 . addImm ( Pred ) . addReg ( PredReg ) . add ( condCodeOp ( ) ) ; TransferImpOps ( MI , LO16 , HI16 ) ; MI . eraseFromParent ( ) ; return ; } unsigned LO16Opc = <NUM_LIT> ; unsigned HI16Opc = <NUM_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } else { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( LO16Opc ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( HI16Opc ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { const char * ES = MO . getSymbolName ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ;

HI16 = HI16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ;


<s> unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( TableEntry -> isUpdating ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; unsigned SrcOpIdx = <NUM_LIT> ; if ( RegSpc == EvenDblSpc || RegSpc == OddDblSpc ) SrcOpIdx = OpIdx ++ ;


<s> if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , getUndefRegState ( SrcIsUndef ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( SrcIsKill && ! SrcIsUndef ) MIB -> addRegisterKilled ( SrcReg , TRI , true ) ; else if ( ! SrcIsUndef ) MIB . addReg ( SrcReg , RegState :: Implicit ) ; TransferImpOps ( MI , MIB , MIB ) ; MIB -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; MI . eraseFromParent ( ) ;


<s> MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; bool SrcIsUndef = MI . getOperand ( OpIdx ) . isUndef ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , getUndefRegState ( SrcIsUndef ) ) ;


<s> unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , SingleSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ;

MIB . addReg ( SrcReg , RegState :: Implicit | getKillRegState ( SrcIsKill ) ) ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> unsigned RegLo = TRI -> getSubReg ( Reg . getReg ( ) , <STR_LIT> ) ; unsigned RegHi = TRI -> getSubReg ( Reg . getReg ( ) , <STR_LIT> ) ;

MIB . addReg ( RegLo , Flags | getKillRegState ( Reg . isDead ( ) ) ) ;


<s> static void addPostLoopLiveIns ( MachineBasicBlock * MBB , LivePhysRegs & LiveRegs ) { for ( auto I = LiveRegs . begin ( ) ; I != LiveRegs . end ( ) ; ++ I ) MBB -> addLiveIn ( * I ) ;


<s> MF -> insert ( ++ LoadCmpBB -> getIterator ( ) , StoreBB ) ; MF -> insert ( ++ StoreBB -> getIterator ( ) , DoneBB ) ; if ( UxtOp ) { MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( UxtOp ) , Desired . getReg ( ) ) . addReg ( Desired . getReg ( ) , RegState :: Kill ) ; if ( ! IsThumb ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; } LoadCmpBB -> addLiveIn ( Addr . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( Dest . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( Desired . getReg ( ) ) ; addPostLoopLiveIns ( LoadCmpBB , LiveRegs ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( LdrexOp ) , Dest . getReg ( ) ) ; MIB . addReg ( Addr . getReg ( ) ) ; if ( LdrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( Dest . getReg ( ) , getKillRegState ( Dest . isDead ( ) ) ) . addOperand ( Desired ) ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; StoreBB -> addLiveIn ( Addr . getReg ( ) ) ; StoreBB -> addLiveIn ( New . getReg ( ) ) ; addPostLoopLiveIns ( StoreBB , LiveRegs ) ; MIB = BuildMI ( StoreBB , DL , TII -> get ( StrexOp ) , StatusReg ) ; MIB . addOperand ( New ) ; MIB . addOperand ( Addr ) ; if ( StrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ;

unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ;


<s> LoadCmpBB -> addLiveIn ( Addr . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( Dest . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( Desired . getReg ( ) ) ; addPostLoopLiveIns ( LoadCmpBB , LiveRegs ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( LdrexOp ) , Dest . getReg ( ) ) ; MIB . addReg ( Addr . getReg ( ) ) ; if ( LdrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( Dest . getReg ( ) , getKillRegState ( Dest . isDead ( ) ) ) . addOperand ( Desired ) ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; StoreBB -> addLiveIn ( Addr . getReg ( ) ) ; StoreBB -> addLiveIn ( New . getReg ( ) ) ; addPostLoopLiveIns ( StoreBB , LiveRegs ) ; MIB = BuildMI ( StoreBB , DL , TII -> get ( StrexOp ) , StatusReg ) ; MIB . addOperand ( New ) ; MIB . addOperand ( Addr ) ; if ( StrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( StatusReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ) ;

BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ;


<s> MachineInstrBuilder MIB ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( LDREXD ) ) ; addExclusiveRegPair ( MIB , Dest , RegState :: Define , IsThumb , TRI ) ; MIB . addReg ( Addr . getReg ( ) ) ; AddDefaultPred ( MIB ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestLo , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredLo , getKillRegState ( Desired . isDead ( ) ) ) ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestHi , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredHi , getKillRegState ( Desired . isDead ( ) ) ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; StoreBB -> addLiveIn ( Addr . getReg ( ) ) ; StoreBB -> addLiveIn ( New . getReg ( ) ) ; addPostLoopLiveIns ( StoreBB , LiveRegs ) ; unsigned STREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( StoreBB , DL , TII -> get ( STREXD ) , StatusReg ) ; addExclusiveRegPair ( MIB , New , <NUM_LIT> , IsThumb , TRI ) ; MIB . addOperand ( Addr ) ; AddDefaultPred ( MIB ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( StatusReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; addPostLoopLiveIns ( DoneBB , LiveRegs ) ; MBB . addSuccessor ( LoadCmpBB ) ; NextMBBI = MBB . end ( ) ;


<s> LoadCmpBB -> addLiveIn ( Desired . getReg ( ) ) ; addPostLoopLiveIns ( LoadCmpBB , LiveRegs ) ; unsigned LDREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( LDREXD ) ) ; addExclusiveRegPair ( MIB , Dest , RegState :: Define , IsThumb , TRI ) ; MIB . addReg ( Addr . getReg ( ) ) ; AddDefaultPred ( MIB ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestLo , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredLo , getKillRegState ( Desired . isDead ( ) ) ) ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestHi , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredHi , getKillRegState ( Desired . isDead ( ) ) ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; StoreBB -> addLiveIn ( Addr . getReg ( ) ) ; StoreBB -> addLiveIn ( New . getReg ( ) ) ; addPostLoopLiveIns ( StoreBB , LiveRegs ) ; unsigned STREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( StoreBB , DL , TII -> get ( STREXD ) , StatusReg ) ; addExclusiveRegPair ( MIB , New , <NUM_LIT> , IsThumb , TRI ) ; MIB . addOperand ( Addr ) ; AddDefaultPred ( MIB ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( StatusReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; addPostLoopLiveIns ( DoneBB , LiveRegs ) ;


<s> bool <ISA_LIT>ExpandPseudo :: ExpandMBB ( MachineBasicBlock & MBB ) { bool Modified = false ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI != E ) { MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; Modified |= ExpandMI ( MBB , MBBI , NMBBI ) ; MBBI = NMBBI ;


<s> bool Modified = false ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI != E ) { MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; Modified |= ExpandMI ( MBB , MBBI , NMBBI ) ;


<s> unsigned Opcode = MI . getOpcode ( ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool isCC = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; const MachineOperand & MO = MI . getOperand ( isCC ? <NUM_LIT> : <NUM_LIT> ) ; bool RequiresBundling = STI -> isTargetWindows ( ) && IsAnAddressOperand ( MO ) ; MachineInstrBuilder LO16 , HI16 ; if ( ! STI -> hasV6T2Ops ( ) && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) { assert ( ! STI -> isTargetWindows ( ) && <STR_LIT> ) ; LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; unsigned ImmVal = ( unsigned ) MO . getImm ( ) ; unsigned SOImmValV1 = <STR_LIT> ( ImmVal ) ; unsigned SOImmValV2 = <STR_LIT> ( ImmVal ) ; LO16 = LO16 . addImm ( SOImmValV1 ) ; HI16 = HI16 . addImm ( SOImmValV2 ) ; LO16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; HI16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ;

LO16 . addImm ( Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ;


<s> if ( STI -> hasV8_1MMainlineOps ( ) ) return CMSEClearFPRegsV81 ( MBB , MBBI , ClearRegs ) ; else return CMSEClearFPRegsV8 ( MBB , MBBI , ClearRegs ) ;


<s> const DebugLoc & DL = RetI . getDebugLoc ( ) ; MachineBasicBlock * ClearBB , * DoneBB ; if ( STI -> hasMinSize ( ) ) { ClearBB = DoneBB = & MBB ; } else { MachineFunction * MF = MBB . getParent ( ) ; ClearBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; DoneBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , ClearBB ) ; MF -> insert ( ++ ClearBB -> getIterator ( ) , DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MBBI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( ClearBB ) ; MBB . addSuccessor ( DoneBB ) ; ClearBB -> addSuccessor ( DoneBB ) ; for ( const MachineOperand & Op : RetI . operands ( ) ) { if ( ! Op . isReg ( ) ) continue ; Register Reg = Op . getReg ( ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) continue ; assert ( Register :: isPhysicalRegister ( Reg ) && <STR_LIT> ) ; ClearBB -> addLiveIn ( Reg ) ; DoneBB -> addLiveIn ( Reg ) ; } ClearBB -> addLiveIn ( <STR_LIT> ) ; DoneBB -> addLiveIn ( <STR_LIT> ) ; BuildMI ( MBB , MBB . end ( ) , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( MBB , MBB . end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( MBB , MBB . end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; } for ( unsigned D = <NUM_LIT> ; D < <NUM_LIT> ; D ++ ) { if ( ClearRegs [ D * <NUM_LIT> + <NUM_LIT> ] && ClearRegs [ D * <NUM_LIT> + <NUM_LIT> ] ) { unsigned Reg = <STR_LIT> + D ; BuildMI ( ClearBB , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else { if ( ClearRegs [ D * <NUM_LIT> + <NUM_LIT> ] ) { unsigned Reg = <STR_LIT> + D * <NUM_LIT> ; BuildMI ( ClearBB , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; }


<s> void <ISA_LIT>ExpandPseudo :: CMSEClearGPRegs ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , const SmallVectorImpl < unsigned > & ClearRegs , unsigned ClobberReg ) { if ( STI -> hasV8_1MMainlineOps ( ) ) { MachineInstrBuilder CLRM = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) ; for ( unsigned R : ClearRegs ) CLRM . addReg ( R , RegState :: Define ) ; CLRM . addReg ( <STR_LIT> , RegState :: Define ) ;

CLRM . addReg ( <STR_LIT> , RegState :: Define | RegState :: Implicit ) ;


<s> BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( ClobberReg ) . add ( predOps ( <STR_LIT> ) ) ; } BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( STI -> hasDSP ( ) ? <NUM_LIT> : <NUM_LIT> ) . addReg ( ClobberReg ) . add ( predOps ( <STR_LIT> ) ) ; }


<s> MachineInstrBuilder PopMIB = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) ; for ( int R = <NUM_LIT> ; R < <NUM_LIT> ; ++ R ) { PopMIB . addReg ( <STR_LIT> + R , RegState :: Define ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> + R ) . addReg ( <STR_LIT> + R , RegState :: Kill ) . add ( predOps ( <STR_LIT> ) ) ; } MachineInstrBuilder PopMIB2 = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) ; for ( int R = <NUM_LIT> ; R < <NUM_LIT> ; ++ R ) PopMIB2 . addReg ( <STR_LIT> + R , RegState :: Define ) ; } else { MachineInstrBuilder PopMIB = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; for ( int Reg = <STR_LIT> ; Reg < <STR_LIT> ; ++ Reg ) PopMIB . addReg ( Reg , RegState :: Define ) ;


<s> for ( int R = <NUM_LIT> ; R < <NUM_LIT> ; ++ R ) PopMIB2 . addReg ( <STR_LIT> + R , RegState :: Define ) ; } else { MachineInstrBuilder PopMIB = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ;

for ( int Reg = <STR_LIT> ; Reg < <STR_LIT> ; ++ Reg ) PopMIB . addReg ( Reg , RegState :: Define ) ;


<s> BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , LoReg ) . addReg ( HiReg , LiveRegs . contains ( HiReg ) ? <NUM_LIT> : RegState :: Undef ) . add ( predOps ( <STR_LIT> ) ) ; -- HiReg ; } MachineInstrBuilder PushMIB2 = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) ; for ( int Reg = <STR_LIT> ; Reg < <STR_LIT> ; ++ Reg ) { if ( Reg == JumpReg ) continue ; PushMIB2 . addReg ( Reg , RegState :: Kill ) ; } if ( JumpReg >= <STR_LIT> && JumpReg <= <STR_LIT> ) { int LoReg = JumpReg == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , LoReg ) . addReg ( <STR_LIT> , LiveRegs . contains ( <STR_LIT> ) ? <NUM_LIT> : RegState :: Undef ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) . addReg ( LoReg , RegState :: Kill ) ; } } else { MachineInstrBuilder PushMIB = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; for ( int Reg = <STR_LIT> ; Reg < <STR_LIT> ; ++ Reg ) { PushMIB . addReg ( Reg , Reg == JumpReg || LiveRegs . contains ( Reg ) ? <NUM_LIT> : RegState :: Undef ) ; } }


<s> if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Reg ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Reg ) . addReg ( <STR_LIT> ) . addImm ( Reg - <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } MachineInstrBuilder VLLDM = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; if ( STI -> fixCMSE_CVE_2021_35465 ( ) ) { auto Bundler = MIBundleBuilder ( MBB , VLLDM ) ; Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Define ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ) ; Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ) ; Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; if ( STI -> hasFPRegs ( ) ) Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Undef ) . add ( predOps ( <STR_LIT> ) ) ) ; else Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addImm ( InlineAsm :: Extra_HasSideEffects ) ) ; finalizeBundle ( MBB , Bundler . begin ( ) , Bundler . end ( ) ) ; } for ( const auto & Regs : ClearedFPRegs ) { unsigned Reg , SaveReg1 , SaveReg2 ; std :: tie ( Reg , SaveReg1 , SaveReg2 ) = Regs ; if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( SaveReg1 ) . addReg ( SaveReg2 ) . add ( predOps ( <STR_LIT> ) ) ;

else if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( SaveReg1 ) . add ( predOps ( <STR_LIT> ) ) ;


<s> BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( CMSE_FP_SAVE_SIZE >> <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; MachineInstrBuilder VPOP = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; for ( int Reg = <STR_LIT> ; Reg <= <STR_LIT> ; ++ Reg ) VPOP . addReg ( Reg , RegState :: Define ) ; }


<s> else if ( STI -> hasV8MMainlineOps ( ) ) CMSESaveClearFPRegsV8 ( MBB , MBBI , DL , LiveRegs , ScratchRegs ) ;


<s> void <ISA_LIT>ExpandPseudo :: CMSESaveClearFPRegs ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc & DL , const LivePhysRegs & LiveRegs , SmallVectorImpl < unsigned > & ScratchRegs ) { if ( STI -> hasV8_1MMainlineOps ( ) ) CMSESaveClearFPRegsV81 ( MBB , MBBI , DL , LiveRegs ) ; else if ( STI -> hasV8MMainlineOps ( ) ) CMSESaveClearFPRegsV8 ( MBB , MBBI , DL , LiveRegs , ScratchRegs ) ;


<s> } else { NonclearedFPRegs . push_back ( Reg ) ; } } } } bool passesFPReg = ( ! NonclearedFPRegs . empty ( ) || ! ClearedFPRegs . empty ( ) ) ; if ( passesFPReg ) assert ( STI -> hasFPRegs ( ) && <STR_LIT> ) ; MachineInstrBuilder VLSTM = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; for ( auto R : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) VLSTM . addReg ( R , RegState :: Implicit | ( LiveRegs . contains ( R ) ? <NUM_LIT> : RegState :: Undef ) ) ; for ( const auto & Regs : ClearedFPRegs ) { unsigned Reg , SaveReg1 , SaveReg2 ; std :: tie ( Reg , SaveReg1 , SaveReg2 ) = Regs ; if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( SaveReg1 ) . addReg ( SaveReg2 ) . add ( predOps ( <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( SaveReg1 ) . add ( predOps ( <STR_LIT> ) ) ; } for ( unsigned Reg : NonclearedFPRegs ) { if ( <STR_LIT> . contains ( Reg ) ) { if ( STI -> isLittle ( ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else { unsigned SReg0 = TRI -> getSubReg ( Reg , <STR_LIT> ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SReg0 ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ;


<s> MachineInstrBuilder VLSTM = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; for ( auto R : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) VLSTM . addReg ( R , RegState :: Implicit | ( LiveRegs . contains ( R ) ? <NUM_LIT> : RegState :: Undef ) ) ; } else {

MachineInstrBuilder VPUSH = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ;


<s> if ( Op . isDef ( ) ) { if ( ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) ) DefFP = true ; continue ; } if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { int R = Reg - <STR_LIT> ;

ClearRegs . reset ( R * <NUM_LIT> , ( R + <NUM_LIT> ) * <NUM_LIT> ) ;


std :: set_difference ( Regs . begin ( ) , Regs . end ( ) , OpRegs . begin ( ) , OpRegs . end ( ) , std :: back_inserter ( ClearRegs ) ) ;


<s> MachineInstr & MI = * MBBI ; DebugLoc DL = MI . getDebugLoc ( ) ; const MachineOperand & Dest = MI . getOperand ( <NUM_LIT> ) ; Register TempReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( ! MI . getOperand ( <NUM_LIT> ) . isUndef ( ) && <STR_LIT> ) ; Register AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register DesiredReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register NewReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( IsThumb ) { assert ( STI -> hasV8MBaselineOps ( ) && <STR_LIT> ) ; assert ( ( UxtOp == <NUM_LIT> || UxtOp == <STR_LIT> || UxtOp == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( UxtOp == <NUM_LIT> || <STR_LIT> . contains ( DesiredReg ) ) && <STR_LIT> ) ; } MachineFunction * MF = MBB . getParent ( ) ; auto LoadCmpBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto StoreBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto DoneBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , LoadCmpBB ) ; MF -> insert ( ++ LoadCmpBB -> getIterator ( ) , StoreBB ) ; MF -> insert ( ++ StoreBB -> getIterator ( ) , DoneBB ) ;


<s> MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( NewOpc ) ) ; unsigned Flags = getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) | getDefRegState ( MI . getOperand ( <NUM_LIT> ) . isDef ( ) ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MIB . add ( MI . getOperand ( <NUM_LIT> ) ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; MIB . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , Flags ) ; MIB . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , Flags ) ; MIB . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , Flags ) ; MIB . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , Flags ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { MIB . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , Flags ) ; MIB . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , Flags ) ; MIB . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , Flags ) ; MIB . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , Flags ) ; }

if ( NewOpc == <STR_LIT> ) MIB . addReg ( SrcReg , RegState :: Implicit ) ;


<s> SubRegIndex = <STR_LIT> ; } Register SubReg = TRI -> getSubReg ( DstReg , SubRegIndex ) ; unsigned DstRegPair = TRI -> getMatchingSuperReg ( SubReg , <STR_LIT> , & <STR_LIT> ) ; MIB . addReg ( DstRegPair , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } else { unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } if ( TableEntry -> isUpdating ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) { const MachineOperand & AM6Offset = MI . getOperand ( OpIdx ++ ) ; if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { assert ( AM6Offset . getReg ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; } else { MIB . add ( AM6Offset ) ; } } unsigned SrcOpIdx = <NUM_LIT> ; if ( ! IsVLD2DUP ) { if ( RegSpc == EvenDblSpc || RegSpc == OddDblSpc || RegSpc == SingleLowSpc || RegSpc == SingleHighQSpc || RegSpc == SingleHighTSpc ) SrcOpIdx = OpIdx ++ ; } MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( SrcOpIdx != <NUM_LIT> ) { MachineOperand MO = MI . getOperand ( SrcOpIdx ) ; MO . setImplicit ( true ) ;


<s> if ( ! TableChecked . load ( std :: memory_order_relaxed ) ) { assert ( llvm :: is_sorted ( NEONLdStTable ) && <STR_LIT> ) ; TableChecked . store ( true , std :: memory_order_relaxed ) ; } auto I = llvm :: lower_bound ( NEONLdStTable , Opcode ) ; if ( I != std :: end ( NEONLdStTable ) && I -> PseudoOpc == Opcode ) return I ; return nullptr ;


<s> auto I = llvm :: lower_bound ( NEONLdStTable , Opcode ) ; if ( I != std :: end ( NEONLdStTable ) && I -> PseudoOpc == Opcode ) return I ;


<s> if ( ! STI -> hasV6T2Ops ( ) && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) { assert ( ! STI -> isTargetWindows ( ) && <STR_LIT> ) ; LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; unsigned ImmVal = ( unsigned ) MO . getImm ( ) ; unsigned SOImmValV1 = <STR_LIT> ( ImmVal ) ; unsigned SOImmValV2 = <STR_LIT> ( ImmVal ) ; LO16 = LO16 . addImm ( SOImmValV1 ) ; HI16 = HI16 . addImm ( SOImmValV2 ) ; LO16 . cloneMemRefs ( MI ) ; HI16 . cloneMemRefs ( MI ) ; LO16 . addImm ( Pred ) . addReg ( PredReg ) . add ( condCodeOp ( ) ) ; HI16 . addImm ( Pred ) . addReg ( PredReg ) . add ( condCodeOp ( ) ) ; if ( isCC ) LO16 . add ( makeImplicit ( MI . getOperand ( <NUM_LIT> ) ) ) ; TransferImpOps ( MI , LO16 , HI16 ) ; MI . eraseFromParent ( ) ; return ; } unsigned LO16Opc = <NUM_LIT> ; unsigned HI16Opc = <NUM_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } else { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( LO16Opc ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( HI16Opc ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { const char * ES = MO . getSymbolName ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ; HI16 = HI16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ; break ; } default : { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ;

LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ;


<s> if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { assert ( AM6Offset . getReg ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; } else { MIB . add ( AM6Offset ) ; } } unsigned SrcOpIdx = <NUM_LIT> ; if ( TableEntry -> RealOpc != <STR_LIT> && TableEntry -> RealOpc != <STR_LIT> && TableEntry -> RealOpc != <STR_LIT> ) { if ( RegSpc == EvenDblSpc || RegSpc == OddDblSpc || RegSpc == SingleLowSpc || RegSpc == SingleHighQSpc || RegSpc == SingleHighTSpc ) SrcOpIdx = OpIdx ++ ; } MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( SrcOpIdx != <NUM_LIT> ) { MachineOperand MO = MI . getOperand ( SrcOpIdx ) ; MO . setImplicit ( true ) ; MIB . add ( MO ) ; }

MIB . addReg ( DstReg , RegState :: ImplicitDefine | getDeadRegState ( DstIsDead ) ) ;


<s> if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } if ( TableEntry -> isUpdating ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) { const MachineOperand & AM6Offset = MI . getOperand ( OpIdx ++ ) ; if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { assert ( AM6Offset . getReg ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ;


<s> } } bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; bool SrcIsUndef = MI . getOperand ( OpIdx ) . isUndef ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , getUndefRegState ( SrcIsUndef ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( SrcIsKill && ! SrcIsUndef ) MIB -> addRegisterKilled ( SrcReg , TRI , true ) ; else if ( ! SrcIsUndef ) MIB . addReg ( SrcReg , RegState :: Implicit ) ; TransferImpOps ( MI , MIB , MIB ) ;


<s> MachineOperand VdSrc ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( VdSrc ) ; } bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , SingleSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 ) ; MachineOperand VmSrc ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( VmSrc ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addReg ( SrcReg , RegState :: Implicit | getKillRegState ( SrcIsKill ) ) ;


<s> auto I = std :: lower_bound ( std :: begin ( NEONLdStTable ) , std :: end ( NEONLdStTable ) , Opcode ) ; if ( I != std :: end ( NEONLdStTable ) && I -> PseudoOpc == Opcode ) return I ; return nullptr ;


<s> AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) Modified |= ExpandMBB ( MBB ) ; if ( Verify<ISA_LIT>Pseudo ) MF . verify ( this , <STR_LIT> ) ;


<s> void <ISA_LIT>ExpandPseudo :: TransferImpOps ( MachineInstr & OldMI , MachineInstrBuilder & UseMI , MachineInstrBuilder & DefMI ) { const MCInstrDesc & Desc = OldMI . getDesc ( ) ; for ( const MachineOperand & MO : llvm :: drop_begin ( OldMI . operands ( ) , Desc . getNumOperands ( ) ) ) {

assert ( MO . isReg ( ) && MO . getReg ( ) ) ;


<s> llvm :: drop_begin ( OldMI . operands ( ) , Desc . getNumOperands ( ) ) ) { assert ( MO . isReg ( ) && MO . getReg ( ) ) ; if ( MO . isUse ( ) ) UseMI . add ( MO ) ;


<s> DebugLoc DL = MI . getDebugLoc ( ) ; MachineOperand & Dest = MI . getOperand ( <NUM_LIT> ) ; unsigned TempReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( ! MI . getOperand ( <NUM_LIT> ) . isUndef ( ) && <STR_LIT> ) ; unsigned AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DesiredReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand New = MI . getOperand ( <NUM_LIT> ) ; New . setIsKill ( false ) ; unsigned DestLo = TRI -> getSubReg ( Dest . getReg ( ) , <STR_LIT> ) ; unsigned DestHi = TRI -> getSubReg ( Dest . getReg ( ) , <STR_LIT> ) ; unsigned DesiredLo = TRI -> getSubReg ( DesiredReg , <STR_LIT> ) ; unsigned DesiredHi = TRI -> getSubReg ( DesiredReg , <STR_LIT> ) ; MachineFunction * MF = MBB . getParent ( ) ; auto LoadCmpBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto StoreBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto DoneBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , LoadCmpBB ) ; MF -> insert ( ++ LoadCmpBB -> getIterator ( ) , StoreBB ) ; MF -> insert ( ++ StoreBB -> getIterator ( ) , DoneBB ) ; unsigned LDREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( LDREXD ) ) ; addExclusiveRegPair ( MIB , Dest , RegState :: Define , IsThumb , TRI ) ; MIB . addReg ( AddrReg ) . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestLo , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredLo ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestHi , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredHi ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ;

BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ;


<s> HI16 . addImm ( Pred ) . addReg ( PredReg ) . add ( condCodeOp ( ) ) ; if ( isCC ) LO16 . add ( makeImplicit ( MI . getOperand ( <NUM_LIT> ) ) ) ; TransferImpOps ( MI , LO16 , HI16 ) ; MI . eraseFromParent ( ) ; return ; } unsigned LO16Opc = <NUM_LIT> ; unsigned HI16Opc = <NUM_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } else { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( LO16Opc ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( HI16Opc ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { const char * ES = MO . getSymbolName ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ; HI16 = HI16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ; break ; } default : { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; break ; } } LO16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; HI16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; LO16 . addImm ( Pred ) . addReg ( PredReg ) ; HI16 . addImm ( Pred ) . addReg ( PredReg ) ; if ( RequiresBundling ) finalizeBundle ( MBB , LO16 -> getIterator ( ) , MBBI -> getIterator ( ) ) ; if ( isCC ) LO16 . add ( makeImplicit ( MI . getOperand ( <NUM_LIT> ) ) ) ;


<s> if ( RegSpc == SingleSpc ) { D0 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D2 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D3 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; } else if ( RegSpc == EvenDblSpc ) { D0 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D2 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D3 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; } else { assert ( RegSpc == OddDblSpc && <STR_LIT> ) ; D0 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D2 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D3 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; } MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( hasWriteBack ) { bool WBIsDead = MI . getOperand ( OpIdx ) . isDead ( ) ; unsigned WBReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; MIB . addReg ( WBReg , RegState :: Define | getDeadRegState ( WBIsDead ) ) ; } bool AddrIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; MIB . addReg ( MI . getOperand ( OpIdx ++ ) . getReg ( ) , getKillRegState ( AddrIsKill ) ) ; MIB . addImm ( MI . getOperand ( OpIdx ++ ) . getImm ( ) ) ; if ( hasWriteBack ) { bool OffsetIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; MIB . addReg ( MI . getOperand ( OpIdx ++ ) . getReg ( ) , getKillRegState ( OffsetIsKill ) ) ; }


<s> D3 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; } else { assert ( RegSpc == OddDblSpc && <STR_LIT> ) ; D0 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D2 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D3 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; } MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( hasWriteBack ) { bool WBIsDead = MI . getOperand ( OpIdx ) . isDead ( ) ; unsigned WBReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; MIB . addReg ( WBReg , RegState :: Define | getDeadRegState ( WBIsDead ) ) ; } bool AddrIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; MIB . addReg ( MI . getOperand ( OpIdx ++ ) . getReg ( ) , getKillRegState ( AddrIsKill ) ) ; MIB . addImm ( MI . getOperand ( OpIdx ++ ) . getImm ( ) ) ; if ( hasWriteBack ) { bool OffsetIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; MIB . addReg ( MI . getOperand ( OpIdx ++ ) . getReg ( ) , getKillRegState ( OffsetIsKill ) ) ;


<s> bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ;


<s> bool <ISA_LIT>ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getTarget ( ) . getInstrInfo ( ) ; TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; bool Modified = false ;

for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ;


<s> void <ISA_LIT>ExpandPseudo :: TransferImpOps ( MachineInstr & OldMI , MachineInstrBuilder & UseMI , MachineInstrBuilder & DefMI ) { const TargetInstrDesc & Desc = OldMI . getDesc ( ) ;

for ( unsigned i = Desc . getNumOperands ( ) , e = OldMI . getNumOperands ( ) ;


<s> unsigned RegElts = TableEntry -> RegElts ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TableEntry -> RealOpc ) ) ; unsigned OpIdx = <NUM_LIT> ; unsigned Lane = MI . getOperand ( MI . getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) . getImm ( ) ; assert ( RegSpc != OddDblSpc && <STR_LIT> ) ; if ( RegSpc == EvenDblSpc && Lane >= RegElts ) { RegSpc = OddDblSpc ; Lane -= RegElts ; } assert ( Lane < RegElts && <STR_LIT> ) ; unsigned D0 = <NUM_LIT> , D1 = <NUM_LIT> , D2 = <NUM_LIT> , D3 = <NUM_LIT> ; unsigned DstReg = <NUM_LIT> ; bool DstIsDead = false ; if ( TableEntry -> IsLoad ) { DstIsDead = MI . getOperand ( OpIdx ) . isDead ( ) ; DstReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } if ( TableEntry -> isUpdating ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MachineOperand MO = MI . getOperand ( OpIdx ++ ) ; if ( ! TableEntry -> IsLoad ) GetDSubRegs ( MO . getReg ( ) , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; unsigned SrcFlags = ( getUndefRegState ( MO . isUndef ( ) ) | getKillRegState ( MO . isKill ( ) ) ) ; MIB . addReg ( D0 , SrcFlags ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D1 , SrcFlags ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , SrcFlags ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , SrcFlags ) ; MIB . addImm ( Lane ) ;


<s> } assert ( Lane < RegElts && <STR_LIT> ) ; unsigned D0 = <NUM_LIT> , D1 = <NUM_LIT> , D2 = <NUM_LIT> , D3 = <NUM_LIT> ; unsigned DstReg = <NUM_LIT> ; bool DstIsDead = false ; if ( TableEntry -> IsLoad ) { DstIsDead = MI . getOperand ( OpIdx ) . isDead ( ) ; DstReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } if ( TableEntry -> isUpdating ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MachineOperand MO = MI . getOperand ( OpIdx ++ ) ; if ( ! TableEntry -> IsLoad ) GetDSubRegs ( MO . getReg ( ) , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; unsigned SrcFlags = ( getUndefRegState ( MO . isUndef ( ) ) | getKillRegState ( MO . isKill ( ) ) ) ; MIB . addReg ( D0 , SrcFlags ) ;

if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D1 , SrcFlags ) ;


<s> MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; bool SrcIsUndef = MI . getOperand ( OpIdx ) . isUndef ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , getUndefRegState ( SrcIsUndef ) ) ;

if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , getUndefRegState ( SrcIsUndef ) ) ;


<s> void <ISA_LIT>ExpandPseudo :: CMSESaveClearFPRegs ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc & DL , const LivePhysRegs & LiveRegs , SmallVectorImpl < unsigned > & ScratchRegs ) {

if ( STI -> hasV8_1MMainlineOps ( ) ) CMSESaveClearFPRegsV81 ( MBB , MBBI , DL , LiveRegs ) ;


<s> MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> HasWriteBack ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MachineOperand MO = MI . getOperand ( OpIdx ++ ) ; if ( ! TableEntry -> IsLoad ) GetDSubRegs ( MO . getReg ( ) , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; unsigned SrcFlags = ( getUndefRegState ( MO . isUndef ( ) ) | getKillRegState ( MO . isKill ( ) ) ) ; MIB . addReg ( D0 , SrcFlags ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D1 , SrcFlags ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , SrcFlags ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , SrcFlags ) ; MIB . addImm ( Lane ) ; OpIdx += <NUM_LIT> ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ;


<s> void <ISA_LIT>ExpandPseudo :: ExpandVLD ( MachineBasicBlock :: iterator & MBBI ) { MachineInstr & MI = * MBBI ; MachineBasicBlock & MBB = * MI . getParent ( ) ; const NEONLdStTableEntry * TableEntry = LookupNEONLdSt ( MI . getOpcode ( ) ) ; assert ( TableEntry && TableEntry -> IsLoad && <STR_LIT> ) ; NEONRegSpacing RegSpc = TableEntry -> RegSpacing ; unsigned NumRegs = TableEntry -> NumRegs ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TableEntry -> RealOpc ) ) ; unsigned OpIdx = <NUM_LIT> ; bool DstIsDead = MI . getOperand ( OpIdx ) . isDead ( ) ; unsigned DstReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( TableEntry -> HasWriteBack ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> HasWriteBack ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; unsigned SrcOpIdx = <NUM_LIT> ; if ( RegSpc == EvenDblSpc || RegSpc == OddDblSpc ) SrcOpIdx = OpIdx ++ ;


<s> const NEONLdStTableEntry * TableEntry = LookupNEONLdSt ( MI . getOpcode ( ) ) ; assert ( TableEntry && ! TableEntry -> IsLoad && <STR_LIT> ) ; NEONRegSpacing RegSpc = TableEntry -> RegSpacing ; unsigned NumRegs = TableEntry -> NumRegs ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TableEntry -> RealOpc ) ) ; unsigned OpIdx = <NUM_LIT> ; if ( TableEntry -> HasWriteBack ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> HasWriteBack ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 ) . addReg ( D1 ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 ) ;


<s> const NEONLdStTableEntry * TableEntry = LookupNEONLdSt ( MI . getOpcode ( ) ) ; assert ( TableEntry && ! TableEntry -> IsLoad && <STR_LIT> ) ; NEONRegSpacing RegSpc = TableEntry -> RegSpacing ; unsigned NumRegs = TableEntry -> NumRegs ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TableEntry -> RealOpc ) ) ; unsigned OpIdx = <NUM_LIT> ; if ( TableEntry -> HasWriteBack ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> HasWriteBack ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 ) . addReg ( D1 ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( SrcIsKill ) ( * MIB ) . addRegisterKilled ( SrcReg , TRI , true ) ; TransferImpOps ( MI , MIB , MIB ) ; MI . eraseFromParent ( ) ;


<s> unsigned OpIdx = <NUM_LIT> ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( IsExt ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , SingleSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 ) . addReg ( D1 ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 ) ;


<s> MIB . addReg ( D0 ) . addReg ( D1 ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ;

if ( SrcIsKill ) ( * MIB ) . addRegisterKilled ( SrcReg , TRI , true ) ;


<s> TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; STI = & MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ;


<s> TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; STI = & MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ;

++ MFI ) Modified |= ExpandMBB ( * MFI ) ;


<s> const MachineOperand & MO = OldMI . getOperand ( i ) ; assert ( MO . isReg ( ) && MO . getReg ( ) ) ; if ( MO . isUse ( ) ) UseMI . addOperand ( MO ) ; else DefMI . addOperand ( MO ) ;


<s> } } } bool returnsFPReg = ( ! NonclearedFPRegs . empty ( ) || ! ClearedFPRegs . empty ( ) ) ; if ( returnsFPReg ) assert ( STI -> hasFPRegs ( ) && <STR_LIT> ) ; for ( unsigned Reg : NonclearedFPRegs ) { if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Reg ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Reg ) . addReg ( <STR_LIT> ) . addImm ( Reg - <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } MachineInstrBuilder VLLDM = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; if ( STI -> fixCMSE_CVE_2021_35465 ( ) ) { auto Bundler = MIBundleBuilder ( MBB , VLLDM ) ; Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Define ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ) ; Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ) ; Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; if ( STI -> hasFPRegs ( ) ) Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Undef ) . add ( predOps ( <STR_LIT> ) ) ) ; else Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addImm ( InlineAsm :: Extra_HasSideEffects ) ) ; finalizeBundle ( MBB , Bundler . begin ( ) , Bundler . end ( ) ) ; } for ( const auto & Regs : ClearedFPRegs ) { unsigned Reg , SaveReg1 , SaveReg2 ;

std :: tie ( Reg , SaveReg1 , SaveReg2 ) = Regs ;


<s> unsigned Reg , SaveReg1 , SaveReg2 ; std :: tie ( Reg , SaveReg1 , SaveReg2 ) = Regs ; if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( SaveReg1 ) . addReg ( SaveReg2 ) . add ( predOps ( <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( SaveReg1 ) . add ( predOps ( <STR_LIT> ) ) ; } for ( unsigned Reg : NonclearedFPRegs ) { if ( <STR_LIT> . contains ( Reg ) ) { if ( STI -> isLittle ( ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else { unsigned SReg0 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SReg0 ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SReg0 + <NUM_LIT> ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> + <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } } else if ( <STR_LIT> . contains ( Reg ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( Reg - <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } } if ( passesFPReg ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SpareReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SpareReg ) . addReg ( SpareReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ;


<s> if ( ! Op . isReg ( ) ) continue ; Register Reg = Op . getReg ( ) ;

if ( ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) ) return true ;


<s> if ( ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) ) DefFP = true ; continue ; } if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { int R = Reg - <STR_LIT> ; ClearRegs . reset ( R * <NUM_LIT> , ( R + <NUM_LIT> ) * <NUM_LIT> ) ;

} else if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) {


<s> BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( Dest . getReg ( ) , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredReg ) . add ( predOps ( <STR_LIT> ) ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; MIB = BuildMI ( StoreBB , DL , TII -> get ( StrexOp ) , TempReg ) . addReg ( NewReg ) . addReg ( AddrReg ) ; if ( StrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( TempReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ;


<s> unsigned NumRegs = TableEntry -> NumRegs ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TableEntry -> RealOpc ) ) ; unsigned OpIdx = <NUM_LIT> ; bool DstIsDead = MI . getOperand ( OpIdx ) . isDead ( ) ; unsigned DstReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { unsigned SubRegIndex ; if ( RegSpc == EvenDblSpc ) { SubRegIndex = <STR_LIT> ; } else { assert ( RegSpc == OddDblSpc && <STR_LIT> ) ; SubRegIndex = <STR_LIT> ; } unsigned SubReg = TRI -> getSubReg ( DstReg , SubRegIndex ) ; unsigned DstRegPair = TRI -> getMatchingSuperReg ( SubReg , <STR_LIT> , & <STR_LIT> ) ; MIB . addReg ( DstRegPair , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } else { unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } if ( TableEntry -> isUpdating ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) { const MachineOperand & AM6Offset = MI . getOperand ( OpIdx ++ ) ; if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { assert ( AM6Offset . getReg ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; } else { MIB . add ( AM6Offset ) ; } } unsigned SrcOpIdx = <NUM_LIT> ; if ( TableEntry -> RealOpc != <STR_LIT> && TableEntry -> RealOpc != <STR_LIT> && TableEntry -> RealOpc != <STR_LIT> ) { if ( RegSpc == EvenDblSpc || RegSpc == OddDblSpc || RegSpc == SingleLowSpc || RegSpc == SingleHighQSpc || RegSpc == SingleHighTSpc ) SrcOpIdx = OpIdx ++ ; } MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ;


<s> unsigned NumRegs = TableEntry -> NumRegs ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TableEntry -> RealOpc ) ) ; unsigned OpIdx = <NUM_LIT> ; bool DstIsDead = MI . getOperand ( OpIdx ) . isDead ( ) ; unsigned DstReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { unsigned SubRegIndex ; if ( RegSpc == EvenDblSpc ) { SubRegIndex = <STR_LIT> ; } else { assert ( RegSpc == OddDblSpc && <STR_LIT> ) ; SubRegIndex = <STR_LIT> ; } unsigned SubReg = TRI -> getSubReg ( DstReg , SubRegIndex ) ; unsigned DstRegPair = TRI -> getMatchingSuperReg ( SubReg , <STR_LIT> , & <STR_LIT> ) ; MIB . addReg ( DstRegPair , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } else { unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } if ( TableEntry -> isUpdating ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) { const MachineOperand & AM6Offset = MI . getOperand ( OpIdx ++ ) ; if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { assert ( AM6Offset . getReg ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; } else { MIB . add ( AM6Offset ) ;


<s> MachineInstr & MI = * MBBI ; MachineBasicBlock & MBB = * MI . getParent ( ) ; const NEONLdStTableEntry * TableEntry = LookupNEONLdSt ( MI . getOpcode ( ) ) ; assert ( TableEntry && ! TableEntry -> IsLoad && <STR_LIT> ) ; NEONRegSpacing RegSpc = ( NEONRegSpacing ) TableEntry -> RegSpacing ; unsigned NumRegs = TableEntry -> NumRegs ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TableEntry -> RealOpc ) ) ; unsigned OpIdx = <NUM_LIT> ; if ( TableEntry -> isUpdating ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) { const MachineOperand & AM6Offset = MI . getOperand ( OpIdx ++ ) ; if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { assert ( AM6Offset . getReg ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; } else { MIB . add ( AM6Offset ) ; } } bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; bool SrcIsUndef = MI . getOperand ( OpIdx ) . isUndef ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ;

MIB . addReg ( D0 , getUndefRegState ( SrcIsUndef ) ) ;


<s> if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { assert ( AM6Offset . getReg ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; } else { MIB . add ( AM6Offset ) ; } } bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; bool SrcIsUndef = MI . getOperand ( OpIdx ) . isUndef ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , getUndefRegState ( SrcIsUndef ) ) ;

if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , getUndefRegState ( SrcIsUndef ) ) ;


<s> static void CMSEPushCalleeSaves ( const TargetInstrInfo & TII , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , int JumpReg , bool Thumb1Only ) { const DebugLoc & DL = MBBI -> getDebugLoc ( ) ; if ( Thumb1Only ) { MachineInstrBuilder PushMIB = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) ; for ( int Reg = <STR_LIT> ; Reg < <STR_LIT> ; ++ Reg ) PushMIB . addReg ( Reg , Reg != JumpReg ? RegState :: Undef : <NUM_LIT> ) ; for ( int LoReg = <STR_LIT> , HiReg = <STR_LIT> ; LoReg >= <STR_LIT> ; -- LoReg ) { if ( JumpReg == LoReg ) continue ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , LoReg ) . addReg ( HiReg , RegState :: Undef ) . add ( predOps ( <STR_LIT> ) ) ; -- HiReg ; } MachineInstrBuilder PushMIB2 = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) ; for ( int Reg = <STR_LIT> ; Reg < <STR_LIT> ; ++ Reg ) { if ( Reg == JumpReg ) continue ; PushMIB2 . addReg ( Reg , RegState :: Kill ) ; } if ( JumpReg >= <STR_LIT> && JumpReg <= <STR_LIT> ) { int LoReg = JumpReg == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , LoReg ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) . addReg ( LoReg ) ; } } else { MachineInstrBuilder PushMIB = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; for ( int Reg = <STR_LIT> ; Reg < <STR_LIT> ; ++ Reg ) PushMIB . addReg ( Reg , Reg != JumpReg ? RegState :: Undef : <NUM_LIT> ) ;


<s> if ( STI -> hasV8_1MMainlineOps ( ) ) CMSERestoreFPRegsV81 ( MBB , MBBI , DL , AvailableRegs ) ;

else CMSERestoreFPRegsV8 ( MBB , MBBI , DL , AvailableRegs ) ;


<s> void <ISA_LIT>ExpandPseudo :: CMSERestoreFPRegs ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc & DL , SmallVectorImpl < unsigned > & AvailableRegs ) {

if ( STI -> hasV8_1MMainlineOps ( ) ) CMSERestoreFPRegsV81 ( MBB , MBBI , DL , AvailableRegs ) ;


<s> if ( <STR_LIT> . contains ( Reg ) ) { if ( AvailableRegs . size ( ) >= <NUM_LIT> ) { unsigned SaveReg2 = AvailableRegs . pop_back_val ( ) ; unsigned SaveReg1 = AvailableRegs . pop_back_val ( ) ; ClearedFPRegs . emplace_back ( Reg , SaveReg1 , SaveReg2 ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( SaveReg1 , RegState :: Define ) . addReg ( SaveReg2 , RegState :: Define ) . addReg ( Reg ) . add ( predOps ( <STR_LIT> ) ) ; } else { NonclearedFPRegs . push_back ( Reg ) ; } } else if ( <STR_LIT> . contains ( Reg ) ) { if ( AvailableRegs . size ( ) >= <NUM_LIT> ) { unsigned SaveReg = AvailableRegs . pop_back_val ( ) ; ClearedFPRegs . emplace_back ( Reg , SaveReg , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SaveReg ) . addReg ( Reg ) . add ( predOps ( <STR_LIT> ) ) ; } else { NonclearedFPRegs . push_back ( Reg ) ; } } } } for ( unsigned Reg : NonclearedFPRegs ) { if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ;

else if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( Reg - <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ;


<s> BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; MachineInstrBuilder VPOP = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; for ( int Reg = <STR_LIT> ; Reg <= <STR_LIT> ; ++ Reg ) VPOP . addReg ( Reg , RegState :: Define ) ;


<s> } bool passesFPReg = ( ! NonclearedFPRegs . empty ( ) || ! ClearedFPRegs . empty ( ) ) ; MachineInstrBuilder VLSTM = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; for ( const auto & Regs : ClearedFPRegs ) { unsigned Reg , SaveReg1 , SaveReg2 ; std :: tie ( Reg , SaveReg1 , SaveReg2 ) = Regs ; if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( SaveReg1 ) . addReg ( SaveReg2 ) . add ( predOps ( <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( SaveReg1 ) . add ( predOps ( <STR_LIT> ) ) ; } for ( unsigned Reg : NonclearedFPRegs ) { if ( <STR_LIT> . contains ( Reg ) ) { if ( STI -> isLittle ( ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else { unsigned SReg0 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SReg0 ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SReg0 + <NUM_LIT> ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> + <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } } else if ( <STR_LIT> . contains ( Reg ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( Reg - <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ;


<s> MachineInstrBuilder VPUSH = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; for ( int Reg = <STR_LIT> ; Reg <= <STR_LIT> ; ++ Reg ) VPUSH . addReg ( Reg ) ; ( void ) CMSEClearFPRegsV81 ( MBB , MBBI , ClearRegs ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ;


<s> bool DefFP = determineFPRegsToClear ( * MBBI , ClearRegs ) ; if ( ! DefFP && ClearRegs . count ( ) == ClearRegs . size ( ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( CMSE_FP_SAVE_SIZE >> <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else {

MachineInstrBuilder VPUSH = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ;


<s> auto DoneBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , LoadCmpBB ) ; MF -> insert ( ++ LoadCmpBB -> getIterator ( ) , StoreBB ) ; MF -> insert ( ++ StoreBB -> getIterator ( ) , DoneBB ) ; if ( UxtOp ) { MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( UxtOp ) , Desired . getReg ( ) ) . addReg ( Desired . getReg ( ) , RegState :: Kill ) ; if ( ! IsThumb ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; } LoadCmpBB -> addLiveIn ( Addr . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( Dest . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( Desired . getReg ( ) ) ; addPostLoopLiveIns ( LoadCmpBB , LiveRegs ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( LdrexOp ) , Dest . getReg ( ) ) ; MIB . addReg ( Addr . getReg ( ) ) ; if ( LdrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( Dest . getReg ( ) , getKillRegState ( Dest . isDead ( ) ) ) . add ( Desired ) . add ( predOps ( <STR_LIT> ) ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ;

StoreBB -> addLiveIn ( Addr . getReg ( ) ) ;


<s> BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; StoreBB -> addLiveIn ( Addr . getReg ( ) ) ; StoreBB -> addLiveIn ( New . getReg ( ) ) ; addPostLoopLiveIns ( StoreBB , LiveRegs ) ; unsigned STREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( StoreBB , DL , TII -> get ( STREXD ) , StatusReg ) ; addExclusiveRegPair ( MIB , New , <NUM_LIT> , IsThumb , TRI ) ; MIB . add ( Addr ) . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( StatusReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; addPostLoopLiveIns ( DoneBB , LiveRegs ) ; MBB . addSuccessor ( LoadCmpBB ) ; NextMBBI = MBB . end ( ) ; MI . eraseFromParent ( ) ; return true ;


<s> MIB . addReg ( Addr . getReg ( ) ) . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestLo , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredLo , getKillRegState ( Desired . isDead ( ) ) ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestHi , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredHi , getKillRegState ( Desired . isDead ( ) ) ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; StoreBB -> addLiveIn ( Addr . getReg ( ) ) ; StoreBB -> addLiveIn ( New . getReg ( ) ) ; addPostLoopLiveIns ( StoreBB , LiveRegs ) ; unsigned STREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( StoreBB , DL , TII -> get ( STREXD ) , StatusReg ) ; addExclusiveRegPair ( MIB , New , <NUM_LIT> , IsThumb , TRI ) ; MIB . add ( Addr ) . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( StatusReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ;

DoneBB -> transferSuccessors ( & MBB ) ;


<s> MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned PC_ID = AFI -> createPICLabelUId ( ) ; MachineInstrBuilder PicADD = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( NotThumb ? <STR_LIT> : <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) . addImm ( PC_ID ) . addImm ( Pred ) . addReg ( PredReg ) ; ( void ) PicADD ;


<s> } const bool ShouldUseMOV16PIC = FlagSfiDisableCP && IsRelocPIC && ( MO . isCPI ( ) || MO . isJTI ( ) || MO . isGlobal ( ) ) ; if ( ShouldUseMOV16PIC ) { if ( isThumb2 ) llvm_unreachable ( <STR_LIT> ) ; LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( LO16Opc ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( HI16Opc ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , RegState :: Kill ) ; if ( MO . isImm ( ) ) { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; } else if ( MO . isGlobal ( ) ) { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; } else if ( MO . isCPI ( ) ) { int i = MO . getIndex ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addConstantPoolIndex ( i , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addConstantPoolIndex ( i , MO . getOffset ( ) , TF | <STR_LIT> ) ; } else if ( MO . isJTI ( ) ) {


<s> TRI = TM . getRegisterInfo ( ) ; STI = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; IsRelocPIC = MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ;

if ( Verify<ISA_LIT>Pseudo ) MF . verify ( this , <STR_LIT> ) ;


<s> bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ;


<s> TRI = STI -> getRegisterInfo ( ) ; AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << MF . getName ( ) << '\n' ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) Modified |= ExpandMBB ( MBB ) ; if ( Verify<ISA_LIT>Pseudo ) MF . verify ( this , <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return Modified ;


<s> AddDefaultPred ( MIB ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestLo , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredLo , getKillRegState ( Desired . isDead ( ) ) ) ) ; unsigned SBCrr = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( SBCrr ) ) . addReg ( StatusReg , RegState :: Define | RegState :: Dead ) . addReg ( DestHi , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredHi , getKillRegState ( Desired . isDead ( ) ) ) ; AddDefaultPred ( MIB ) ; MIB . addReg ( <STR_LIT> , RegState :: Kill ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; StoreBB -> addLiveIn ( Addr . getReg ( ) ) ; StoreBB -> addLiveIn ( New . getReg ( ) ) ; addPostLoopLiveIns ( StoreBB , LiveRegs ) ; unsigned STREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( StoreBB , DL , TII -> get ( STREXD ) , StatusReg ) ; addExclusiveRegPair ( MIB , New , <NUM_LIT> , IsThumb , TRI ) ; MIB . addOperand ( Addr ) ; AddDefaultPred ( MIB ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( StatusReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; addPostLoopLiveIns ( DoneBB , LiveRegs ) ; MBB . addSuccessor ( LoadCmpBB ) ; NextMBBI = MBB . end ( ) ;


<s> unsigned DesiredHi = TRI -> getSubReg ( Desired . getReg ( ) , <STR_LIT> ) ; LivePhysRegs LiveRegs ( & TII -> getRegisterInfo ( ) ) ; LiveRegs . addLiveOuts ( MBB ) ; for ( auto I = std :: prev ( MBB . end ( ) ) ; I != MBBI ; -- I ) LiveRegs . stepBackward ( * I ) ; MachineFunction * MF = MBB . getParent ( ) ; auto LoadCmpBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto StoreBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto DoneBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , LoadCmpBB ) ; MF -> insert ( ++ LoadCmpBB -> getIterator ( ) , StoreBB ) ; MF -> insert ( ++ StoreBB -> getIterator ( ) , DoneBB ) ; LoadCmpBB -> addLiveIn ( Addr . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( Dest . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( Desired . getReg ( ) ) ; addPostLoopLiveIns ( LoadCmpBB , LiveRegs ) ; unsigned LDREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( LDREXD ) ) ; addExclusiveRegPair ( MIB , Dest , RegState :: Define , IsThumb , TRI ) ; MIB . addReg ( Addr . getReg ( ) ) ; AddDefaultPred ( MIB ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestLo , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredLo , getKillRegState ( Desired . isDead ( ) ) ) ) ; unsigned SBCrr = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( SBCrr ) ) . addReg ( StatusReg , RegState :: Define | RegState :: Dead ) . addReg ( DestHi , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredHi , getKillRegState ( Desired . isDead ( ) ) ) ; AddDefaultPred ( MIB ) ; MIB . addReg ( <STR_LIT> , RegState :: Kill ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ;


<s> case MachineOperand :: MO_TargetIndex : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_BlockAddress : return true ; case MachineOperand :: MO_RegisterMask : case MachineOperand :: MO_RegisterLiveOut : return false ; case MachineOperand :: MO_Metadata : case MachineOperand :: MO_MCSymbol : return true ;


<s> BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addDef ( <STR_LIT> , RegState :: Dead ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else { BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; } } MachineInstrBuilder MIB ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( LdrexOp ) , Dest . getReg ( ) ) ; MIB . addReg ( AddrReg ) ; if ( LdrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( Dest . getReg ( ) , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredReg ) . add ( predOps ( <STR_LIT> ) ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; MIB = BuildMI ( StoreBB , DL , TII -> get ( StrexOp ) , StatusReg ) . addReg ( NewReg ) . addReg ( AddrReg ) ; if ( StrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( StatusReg , getKillRegState ( StatusDead ) ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ;


<s> LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; unsigned STREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( StoreBB , DL , TII -> get ( STREXD ) , StatusReg ) ; addExclusiveRegPair ( MIB , New , <NUM_LIT> , IsThumb , TRI ) ; MIB . addReg ( AddrReg ) . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( StatusReg , getKillRegState ( StatusDead ) ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoadCmpBB ) ; NextMBBI = MBB . end ( ) ; MI . eraseFromParent ( ) ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; LivePhysRegs LiveRegs ; computeLiveIns ( LiveRegs , MRI , * DoneBB ) ; computeLiveIns ( LiveRegs , MRI , * StoreBB ) ; computeLiveIns ( LiveRegs , MRI , * LoadCmpBB ) ;


<s> void <ISA_LIT>ExpandPseudo :: ExpandLaneOp ( MachineBasicBlock :: iterator & MBBI ) { MachineInstr & MI = * MBBI ; MachineBasicBlock & MBB = * MI . getParent ( ) ; const NEONLdStTableEntry * TableEntry = LookupNEONLdSt ( MI . getOpcode ( ) ) ; assert ( TableEntry && <STR_LIT> ) ; NEONRegSpacing RegSpc = TableEntry -> RegSpacing ; unsigned NumRegs = TableEntry -> NumRegs ; unsigned RegElts = TableEntry -> RegElts ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TableEntry -> RealOpc ) ) ; unsigned OpIdx = <NUM_LIT> ; unsigned Lane = MI . getOperand ( MI . getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) . getImm ( ) ; assert ( RegSpc != OddDblSpc && <STR_LIT> ) ; if ( RegSpc == EvenDblSpc && Lane >= RegElts ) { RegSpc = OddDblSpc ; Lane -= RegElts ; } assert ( Lane < RegElts && <STR_LIT> ) ; unsigned D0 = <NUM_LIT> , D1 = <NUM_LIT> , D2 = <NUM_LIT> , D3 = <NUM_LIT> ; unsigned DstReg = <NUM_LIT> ;


<s> HI16Opc = <STR_LIT> ; } LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( LO16Opc ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( HI16Opc ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; if ( MO . isImm ( ) ) { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; } ( * LO16 ) . setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; ( * HI16 ) . setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; LO16 . addImm ( Pred ) . addReg ( PredReg ) ; HI16 . addImm ( Pred ) . addReg ( PredReg ) ;


<s> const TargetMachine & TM = MF . getTarget ( ) ; TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( TM . getInstrInfo ( ) ) ; TRI = TM . getRegisterInfo ( ) ; STI = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool Modified = false ;

for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ;


<s> MachineInstrBuilder LO16 , HI16 ; if ( ! STI -> hasV6T2Ops ( ) && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) { assert ( ! STI -> isTargetWindows ( ) && <STR_LIT> ) ; LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; unsigned ImmVal = ( unsigned ) MO . getImm ( ) ; unsigned SOImmValV1 = <STR_LIT> ( ImmVal ) ; unsigned SOImmValV2 = <STR_LIT> ( ImmVal ) ; LO16 = LO16 . addImm ( SOImmValV1 ) ; HI16 = HI16 . addImm ( SOImmValV2 ) ; LO16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; HI16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; LO16 . addImm ( Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; HI16 . addImm ( Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; TransferImpOps ( MI , LO16 , HI16 ) ; MI . eraseFromParent ( ) ; return ; } unsigned LO16Opc = <NUM_LIT> ; unsigned HI16Opc = <NUM_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } else { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } if ( RequiresBundling ) BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TargetOpcode :: BUNDLE ) ) ; LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( LO16Opc ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( HI16Opc ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { const char * ES = MO . getSymbolName ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ; HI16 = HI16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ;


<s> bool <ISA_LIT>ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; TRI = TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; STI = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ;


<s> MIB . add ( VdSrc ) ; } bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , SingleSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 ) ; MachineOperand VmSrc ( MI . getOperand ( OpIdx ++ ) ) ; VmSrc . setIsRenamable ( false ) ; MIB . add ( VmSrc ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ;

MIB . addReg ( SrcReg , RegState :: Implicit | getKillRegState ( SrcIsKill ) ) ;


<s> case MachineOperand :: MO_MachineBasicBlock : return true ; case MachineOperand :: MO_FrameIndex : return false ; case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_TargetIndex : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_BlockAddress : return true ; case MachineOperand :: MO_RegisterMask : case MachineOperand :: MO_RegisterLiveOut : return false ; case MachineOperand :: MO_Metadata : case MachineOperand :: MO_MCSymbol : return true ; case MachineOperand :: MO_CFIIndex : return false ; case MachineOperand :: MO_IntrinsicID : case MachineOperand :: MO_Predicate :


<s> return false ; case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_TargetIndex : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_BlockAddress : return true ; case MachineOperand :: MO_RegisterMask :

case MachineOperand :: MO_RegisterLiveOut :


<s> unsigned HI16Opc = <NUM_LIT> ; bool isThumb2 = ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; if ( isThumb2 ) { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } else { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } const bool ShouldUseMOV16PIC = ! STI -> useConstIslands ( ) && IsRelocPIC && ( MO . isCPI ( ) || MO . isJTI ( ) || MO . isGlobal ( ) ) ; if ( ShouldUseMOV16PIC ) { if ( isThumb2 ) llvm_unreachable ( <STR_LIT> ) ; LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( LO16Opc ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( HI16Opc ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , RegState :: Kill ) ; if ( MO . isImm ( ) ) { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; } else if ( MO . isGlobal ( ) ) { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; } else if ( MO . isCPI ( ) ) { int i = MO . getIndex ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addConstantPoolIndex ( i , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addConstantPoolIndex ( i , MO . getOffset ( ) , TF | <STR_LIT> ) ; } else if ( MO . isJTI ( ) ) { unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addJumpTableIndex ( MO . getIndex ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addJumpTableIndex ( MO . getIndex ( ) , TF | <STR_LIT> ) ; } else {


<s> LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; } else if ( MO . isGlobal ( ) ) { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; } else if ( MO . isCPI ( ) ) { int i = MO . getIndex ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addConstantPoolIndex ( i , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addConstantPoolIndex ( i , MO . getOffset ( ) , TF | <STR_LIT> ) ; } else if ( MO . isJTI ( ) ) { unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addJumpTableIndex ( MO . getIndex ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addJumpTableIndex ( MO . getIndex ( ) , TF | <STR_LIT> ) ; } else { assert ( <NUM_LIT> && <STR_LIT> ) ; } if ( ShouldUseMOV16PIC ) { AddPICADD_MOVi16_PICID ( MI , MBB , MBBI , ! isThumb2 , PredReg , Pred , DstReg , DstIsDead , LO16 , HI16 ) ; } LO16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; HI16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; LO16 . addImm ( Pred ) . addReg ( PredReg ) ;

HI16 . addImm ( Pred ) . addReg ( PredReg ) ;


<s> HI16Opc = <STR_LIT> ; } LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( LO16Opc ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( HI16Opc ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , RegState :: Kill ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { const char * ES = MO . getSymbolName ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ; HI16 = HI16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ; break ; } default : { if ( MO . isGlobal ( ) ) { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; } else if ( MO . isCPI ( ) ) { int i = MO . getIndex ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addConstantPoolIndex ( i , MO . getOffset ( ) , TF | <STR_LIT> ) ;

HI16 = HI16 . addConstantPoolIndex ( i , MO . getOffset ( ) , TF | <STR_LIT> ) ;