<s> Value * <ISA_LIT>TargetLowering :: emitStoreConditional ( IRBuilder < > & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Function * Strex = <STR_LIT> ( M , Int ) ; Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , <STR_LIT> ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , <NUM_LIT> ) , Int32Ty , <STR_LIT> ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall3 ( Strex , Lo , Hi , Addr ) ; } <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ;

Type * Tys [ ] = { Addr -> getType ( ) } ;


<s> EVT SrcVT = Op . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; assert ( ( SrcVT == <STR_LIT> || DstVT == <STR_LIT> ) && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && TLI . isTypeLegal ( DstVT ) ) { SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , DstVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( type == OtherModImm ) return SDValue ( ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } return SDValue ( ) ; case <NUM_LIT> : { if ( type != VMOVModImm ) return SDValue ( ) ; uint64_t BitMask = <NUM_LIT> ; uint64_t Val = <NUM_LIT> ; unsigned ImmMask = <NUM_LIT> ; Imm = <NUM_LIT> ; for ( int ByteNum = <NUM_LIT> ; ByteNum < <NUM_LIT> ; ++ ByteNum ) { if ( ( ( SplatBits | SplatUndef ) & BitMask ) == BitMask ) { Val |= BitMask ; Imm |= ImmMask ; } else if ( ( SplatBits & BitMask ) != <NUM_LIT> ) { return SDValue ( ) ; } BitMask <<= <NUM_LIT> ;


<s> SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return FrameAddr ;


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned FrameReg = ( Subtarget -> isThumb ( ) || Subtarget -> isTargetMachO ( ) ) ? <STR_LIT> : <STR_LIT> ;

SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ;


<s> assert ( Subtarget -> isTargetDarwin ( ) ) ; SDLoc dl ( Op ) ; SDValue Arg = Op . getOperand ( <NUM_LIT> ) ; EVT ArgVT = Arg . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; StructType * RetTy = StructType :: get ( ArgTy , ArgTy , NULL ) ; const uint64_t ByteSize = TLI . getDataLayout ( ) -> getTypeAllocSize ( RetTy ) ; const unsigned StackAlign = TLI . getDataLayout ( ) -> getPrefTypeAlignment ( RetTy ) ; int FrameIdx = FrameInfo -> CreateStackObject ( ByteSize , StackAlign , false ) ; SDValue SRet = DAG . getFrameIndex ( FrameIdx , TLI . getPointerTy ( ) ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = SRet ; Entry . Ty = RetTy -> getPointerTo ( ) ; Entry . isSExt = false ; Entry . isZExt = false ; Entry . isSRet = true ; Args . push_back ( Entry ) ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ;

const char * LibcallName = ( ArgVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ;


<s> Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; const char * LibcallName = ( ArgVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , getPointerTy ( ) ) ; TargetLowering :: CallLoweringInfo CLI ( DAG . getEntryNode ( ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , CallingConv :: C , false , false , false , Callee , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; SDValue LoadSin = DAG . getLoad ( ArgVT , dl , CallResult . second , SRet , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , SRet , DAG . getIntPtrConstant ( ArgVT . getStoreSize ( ) ) ) ; SDValue LoadCos = DAG . getLoad ( ArgVT , dl , LoadSin . getValue ( <NUM_LIT> ) , Add , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;

SDVTList Tys = DAG . getVTList ( ArgVT , ArgVT ) ;


<s> unsigned Wrapper = RelocM == Reloc :: PIC_ ? <STR_LIT> : <STR_LIT> ; SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getNode ( Wrapper , dl , PtrVT , G ) ;

if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ;


<s> SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getNode ( Wrapper , dl , PtrVT , G ) ;


<s> assert ( NextVA . isMemLoc ( ) ) ; if ( ! StackPtr . getNode ( ) ) StackPtr = DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , getPointerTy ( ) ) ; MemOpChains . push_back ( LowerMemOpCallTo ( Chain , StackPtr , fmrrd . getValue ( <NUM_LIT> ) , dl , DAG , NextVA , Flags ) ) ;


<s> } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chains ) ; } if ( ! <STR_LIT> ( St ) ) return SDValue ( ) ; if ( StVal . getNode ( ) -> getOpcode ( ) == <STR_LIT> && StVal . getNode ( ) -> hasOneUse ( ) ) { SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( St ) ; SDValue BasePtr = St -> getBasePtr ( ) ; SDValue NewST1 = DAG . getStore ( St -> getChain ( ) , DL , StVal . getNode ( ) -> getOperand ( <NUM_LIT> ) , BasePtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , St -> getAlignment ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getStore ( NewST1 . getValue ( <NUM_LIT> ) , DL , StVal . getNode ( ) -> getOperand ( <NUM_LIT> ) , OffsetPtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , std :: min ( <NUM_LIT> , St -> getAlignment ( ) / <NUM_LIT> ) ) ; } if ( StVal . getValueType ( ) != <STR_LIT> || StVal . getNode ( ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc dl ( StVal ) ; SDValue IntVec = StVal . getOperand ( <NUM_LIT> ) ; EVT FloatVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , IntVec . getValueType ( ) . getVectorNumElements ( ) ) ; SDValue Vec = DAG . getNode ( <STR_LIT> , dl , FloatVT , IntVec ) ; SDValue ExtElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , StVal . getOperand ( <NUM_LIT> ) ) ; dl = SDLoc ( N ) ; SDValue V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ExtElt ) ; DCI . AddToWorklist ( Vec . getNode ( ) ) ;

DCI . AddToWorklist ( ExtElt . getNode ( ) ) ;


<s> assert ( StoreVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue ShuffWide = DAG . getNode ( <STR_LIT> , DL , StoreVecVT , Shuff ) ; SmallVector < SDValue , <NUM_LIT> > Chains ; SDValue Increment = DAG . getConstant ( StoreType . getSizeInBits ( ) / <NUM_LIT> , TLI . getPointerTy ( ) ) ; SDValue BasePtr = St -> getBasePtr ( ) ; unsigned E = ( ToEltSz * NumElems ) / StoreType . getSizeInBits ( ) ; for ( unsigned I = <NUM_LIT> ; I < E ; I ++ ) { SDValue SubVec = DAG . getNode ( <STR_LIT> , DL , StoreType , ShuffWide , DAG . getIntPtrConstant ( I ) ) ; SDValue Ch = DAG . getStore ( St -> getChain ( ) , DL , SubVec , BasePtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , St -> getAlignment ( ) ) ; BasePtr = DAG . getNode ( <STR_LIT> , DL , BasePtr . getValueType ( ) , BasePtr , Increment ) ; Chains . push_back ( Ch ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chains ) ; } if ( ! <STR_LIT> ( St ) ) return SDValue ( ) ; if ( StVal . getNode ( ) -> getOpcode ( ) == <STR_LIT> && StVal . getNode ( ) -> hasOneUse ( ) ) { SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( St ) ; SDValue BasePtr = St -> getBasePtr ( ) ; SDValue NewST1 = DAG . getStore ( St -> getChain ( ) , DL , StVal . getNode ( ) -> getOperand ( <NUM_LIT> ) , BasePtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , St -> getAlignment ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getStore ( NewST1 . getValue ( <NUM_LIT> ) , DL , StVal . getNode ( ) -> getOperand ( <NUM_LIT> ) , OffsetPtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , std :: min ( <NUM_LIT> , St -> getAlignment ( ) / <NUM_LIT> ) ) ;


<s> if ( StoreInst * SI = dyn_cast < StoreInst > ( Inst ) ) return SI -> getValueOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ;

else if ( LoadInst * LI = dyn_cast < LoadInst > ( Inst ) ) return LI -> getType ( ) -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ;


<s> else if ( LoadInst * LI = dyn_cast < LoadInst > ( Inst ) ) return LI -> getType ( ) -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ; return Inst -> getType ( ) -> getPrimitiveSizeInBits ( ) <= <NUM_LIT> ;


<s> const TargetRegisterClass * <ISA_LIT>TargetLowering :: getRegClassFor ( MVT VT , bool isDivergent ) const { ( void ) isDivergent ; if ( Subtarget -> hasNEON ( ) ) { if ( VT == <STR_LIT> ) return & <STR_LIT> ; if ( VT == <STR_LIT> ) return & <STR_LIT> ; }

return TargetLowering :: getRegClassFor ( VT ) ;


<s> break ; case <STR_LIT> : Scale = <NUM_LIT> ; break ; } if ( ( V & ( Scale - <NUM_LIT> ) ) != <NUM_LIT> ) return false ;

return isUInt < <NUM_LIT> > ( V / Scale ) ;


<s> bool IsNeg = false ; if ( V < <NUM_LIT> ) { IsNeg = true ; V = - V ; } unsigned NumBytes = std :: max ( VT . getSizeInBits ( ) / <NUM_LIT> , <NUM_LIT> ) ; if ( ( VT . isFloatingPoint ( ) && Subtarget -> hasVFP2Base ( ) ) || NumBytes == <NUM_LIT> ) return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( V ) ; if ( NumBytes == <NUM_LIT> || NumBytes == <NUM_LIT> || NumBytes == <NUM_LIT> ) {

if ( IsNeg ) return isUInt < <NUM_LIT> > ( V ) ;


<s> SDValue Value , OverflowCmp ; SDValue <ISA_LIT>cc ; std :: tie ( Value , OverflowCmp ) = get<ISA_LIT>XALUOOp ( LHS . getValue ( <NUM_LIT> ) , DAG , <ISA_LIT>cc ) ; if ( ( CC == <STR_LIT> ) != isOneConstant ( RHS ) ) { <STR_LIT> CondCode = ( <STR_LIT> ) cast < const ConstantSDNode > ( <ISA_LIT>cc ) -> getZExtValue ( ) ; CondCode = <STR_LIT> ( CondCode ) ; <ISA_LIT>cc = DAG . getConstant ( CondCode , SDLoc ( <ISA_LIT>cc ) , <STR_LIT> ) ; } SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , OverflowCmp ) ; } if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } if ( getTargetMachine ( ) . Options . UnsafeFPMath && ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue Result = OptimizeVFPBrcond ( Op , DAG ) ) return Result ; } <STR_LIT> CondCode , CondCode2 ; bool InvalidOnQNaN ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 , InvalidOnQNaN ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl , InvalidOnQNaN ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Dest , <ISA_LIT>cc , CCR , Cmp } ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , VTList , Ops ) ; if ( CondCode2 != <STR_LIT> ) { <ISA_LIT>cc = DAG . getConstant ( CondCode2 , dl , <STR_LIT> ) ;

SDValue Ops [ ] = { Res , Dest , <ISA_LIT>cc , CCR , Res . getValue ( <NUM_LIT> ) } ;


<s> SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; if ( ! Subtarget -> hasFP64 ( ) && LHS . getValueType ( ) == <STR_LIT> ) { DAG . getTargetLoweringInfo ( ) . softenSetCCOperands ( DAG , <STR_LIT> , LHS , RHS , CC , dl ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } unsigned Opc = LHS . getOpcode ( ) ; bool OptimizeMul = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ! Subtarget -> isThumb1Only ( ) ; if ( LHS . getResNo ( ) == <NUM_LIT> && ( isOneConstant ( RHS ) || isNullConstant ( RHS ) ) && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || OptimizeMul ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( LHS -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue Value , OverflowCmp ; SDValue <ISA_LIT>cc ; std :: tie ( Value , OverflowCmp ) = get<ISA_LIT>XALUOOp ( LHS . getValue ( <NUM_LIT> ) , DAG , <ISA_LIT>cc ) ; if ( ( CC == <STR_LIT> ) != isOneConstant ( RHS ) ) { <STR_LIT> CondCode = ( <STR_LIT> ) cast < const ConstantSDNode > ( <ISA_LIT>cc ) -> getZExtValue ( ) ; CondCode = <STR_LIT> ( CondCode ) ; <ISA_LIT>cc = DAG . getConstant ( CondCode , SDLoc ( <ISA_LIT>cc ) , <STR_LIT> ) ; } SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , OverflowCmp ) ; } if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ;


<s> RTLIB :: Libcall LC ; LC = RTLIB :: getFPEXT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ;

SDValue SrcVal = Op . getOperand ( <NUM_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP_EXTEND ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getValueType ( ) == <STR_LIT> && ! Subtarget -> hasFP64 ( ) && <STR_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP_ROUND ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && ! Subtarget -> hasFP64 ( ) && <STR_LIT> ) ; RTLIB :: Libcall LC ; LC = RTLIB :: getFPROUND ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; SDValue SrcVal = Op . getOperand ( <NUM_LIT> ) ; return makeLibCall ( DAG , LC , Op . getValueType ( ) , SrcVal , false , SDLoc ( Op ) ) . first ;


<s> SDValue SrcVal = Op . getOperand ( <NUM_LIT> ) ; return makeLibCall ( DAG , LC , Op . getValueType ( ) , SrcVal , false , SDLoc ( Op ) ) . first ;


<s> if ( VT . isVector ( ) ) return LowerVectorFP_TO_INT ( Op , DAG ) ; if ( ! Subtarget -> hasFP64 ( ) && Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { RTLIB :: Libcall LC ;

if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ;


<s> if ( ! Subtarget -> hasFP64 ( ) && Op . getValueType ( ) == <STR_LIT> ) { RTLIB :: Libcall LC ;

if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getSINTTOFP ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerINT_TO_FP ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; if ( VT . isVector ( ) ) return LowerVectorINT_TO_FP ( Op , DAG ) ; if ( ! Subtarget -> hasFP64 ( ) && Op . getValueType ( ) == <STR_LIT> ) { RTLIB :: Libcall LC ; if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getSINTTOFP ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ;

else LC = RTLIB :: getUINTTOFP ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ;


<s> if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { CC = <STR_LIT> ( CC , true ) ; std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; bool InvalidOnQNaN ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 , InvalidOnQNaN ) ; if ( Subtarget -> hasFP<ISA_LIT>v8Base ( ) && ! ( isFloatingPointZero ( RHS ) && TrueVal . getValueType ( ) != <STR_LIT> ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { bool swpCmpOps = false ; bool swpVselOps = false ; checkVSELConstraints ( CC , CondCode , swpCmpOps , swpVselOps ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { if ( swpCmpOps ) std :: swap ( LHS , RHS ) ; if ( swpVselOps ) std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl , InvalidOnQNaN ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Result = getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; if ( CondCode2 != <STR_LIT> ) { SDValue <ISA_LIT>cc2 = DAG . getConstant ( CondCode2 , dl , <STR_LIT> ) ; SDValue Cmp2 = getVFPCmp ( LHS , RHS , DAG , dl , InvalidOnQNaN ) ;

Result = getCMOV ( dl , VT , Result , TrueVal , <ISA_LIT>cc2 , CCR , Cmp2 , DAG ) ;


<s> if ( isV_UNDEF ) V2 = V1 ; return DAG . getNode ( ShuffleOpc , dl , DAG . getVTList ( VT , VT ) , V1 , V2 ) . getValue ( WhichResult ) ; } if ( V1 -> getOpcode ( ) == <STR_LIT> && V2 -> isUndef ( ) ) { SDValue SubV1 = V1 -> getOperand ( <NUM_LIT> ) ; SDValue SubV2 = V1 -> getOperand ( <NUM_LIT> ) ; EVT SubVT = SubV1 . getValueType ( ) ; assert ( llvm :: all_of ( ShuffleMask , [ & ] ( int i ) { return i < ( int ) VT . getVectorNumElements ( ) ; } ) && <STR_LIT> ) ; if ( unsigned ShuffleOpc = isNEONTwoResultShuffleMask ( ShuffleMask , SubVT , WhichResult , isV_UNDEF ) ) { if ( isV_UNDEF ) SubV2 = SubV1 ; assert ( ( WhichResult == <NUM_LIT> ) && <STR_LIT> ) ; SDValue Res = DAG . getNode ( ShuffleOpc , dl , DAG . getVTList ( SubVT , SubVT ) , SubV1 , SubV2 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res . getValue ( <NUM_LIT> ) , Res . getValue ( <NUM_LIT> ) ) ; } } } unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == <NUM_LIT> ) { unsigned PFIndexes [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ; else PFIndexes [ i ] = ShuffleMask [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; } if ( EltSize >= <NUM_LIT> ) { EVT EltVT = EVT :: getFloatingPointVT ( EltSize ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumElts ) ; V1 = DAG . getNode ( <STR_LIT> , dl , VecVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , VecVT , V2 ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) Ops . push_back ( DAG . getUNDEF ( EltVT ) ) ; else Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , ShuffleMask [ i ] < ( int ) NumElts ? V1 : V2 , DAG . getConstant ( ShuffleMask [ i ] & ( NumElts - <NUM_LIT> ) , dl , <STR_LIT> ) ) ) ;


<s> case <STR_LIT> : return PerformCMOVCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformBRCONDCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformLOADCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformVLDCombine ( N , DCI ) ; case <STR_LIT> : return Perform<ISA_LIT>BUILD_VECTORCombine ( N , DCI ) ; case <STR_LIT> : { unsigned BitWidth = N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ; APInt DemandedMask = APInt :: getLowBitsSet ( BitWidth , <NUM_LIT> ) ; if ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , DemandedMask , DCI ) ) return SDValue ( ) ; break ; } case <STR_LIT> : { unsigned BitWidth = N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ; APInt DemandedMask = APInt :: getHighBitsSet ( BitWidth , <NUM_LIT> ) ; if ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , DemandedMask , DCI ) ) return SDValue ( ) ; break ; } case <STR_LIT> : { unsigned BitWidth = N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ; APInt DemandedMask = APInt :: getLowBitsSet ( BitWidth , <NUM_LIT> ) ; if ( ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , DemandedMask , DCI ) ) || ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , DemandedMask , DCI ) ) ) return SDValue ( ) ; break ; } case <STR_LIT> : { unsigned LowWidth = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits ( ) ; APInt LowMask = APInt :: getLowBitsSet ( LowWidth , <NUM_LIT> ) ; unsigned HighWidth = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits ( ) ; APInt HighMask = APInt :: getHighBitsSet ( HighWidth , <NUM_LIT> ) ; if ( ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , LowMask , DCI ) ) || ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , HighMask , DCI ) ) ) return SDValue ( ) ; break ; } case <STR_LIT> : { unsigned HighWidth = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits ( ) ; APInt HighMask = APInt :: getHighBitsSet ( HighWidth , <NUM_LIT> ) ;


<s> if ( ! ShiftAmtNode ) return SDValue ( ) ; uint32_t ShiftAmt = static_cast < uint32_t > ( ShiftAmtNode -> getZExtValue ( ) ) ; ConstantSDNode * AndMaskNode = dyn_cast < ConstantSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; if ( ! AndMaskNode ) return SDValue ( ) ; uint32_t AndMask = static_cast < uint32_t > ( AndMaskNode -> getZExtValue ( ) ) ; if ( AndMask == <NUM_LIT> || AndMask == <NUM_LIT> ) return SDValue ( ) ; if ( isMask_32 ( AndMask ) ) { uint32_t MaskedBits = countLeadingZeros ( AndMask ) ; if ( MaskedBits > ShiftAmt ) { SDLoc DL ( N ) ; SDValue SHL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( MaskedBits , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SHL , DAG . getConstant ( MaskedBits - ShiftAmt , DL , <STR_LIT> ) ) ; } } } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! VT . isVector ( ) || ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; assert ( ST -> hasNEON ( ) && <STR_LIT> ) ; int64_t Cnt ;


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * ShiftAmtNode = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! ShiftAmtNode ) return SDValue ( ) ; uint32_t ShiftAmt = static_cast < uint32_t > ( ShiftAmtNode -> getZExtValue ( ) ) ; ConstantSDNode * AndMaskNode = dyn_cast < ConstantSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; if ( ! AndMaskNode ) return SDValue ( ) ; uint32_t AndMask = static_cast < uint32_t > ( AndMaskNode -> getZExtValue ( ) ) ; if ( AndMask == <NUM_LIT> || AndMask == <NUM_LIT> ) return SDValue ( ) ; if ( isMask_32 ( AndMask ) ) { uint32_t MaskedBits = countLeadingZeros ( AndMask ) ; if ( MaskedBits > ShiftAmt ) { SDLoc DL ( N ) ; SDValue SHL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( MaskedBits , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SHL , DAG . getConstant ( MaskedBits - ShiftAmt , DL , <STR_LIT> ) ) ; } } } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! VT . isVector ( ) || ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; assert ( ST -> hasNEON ( ) && <STR_LIT> ) ;


<s> SDLoc DL ( LD ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; SDValue NewLD1 = DAG . getLoad ( <STR_LIT> , DL , LD -> getChain ( ) , BasePtr , LD -> getPointerInfo ( ) , LD -> getAlignment ( ) , LD -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue NewLD2 = DAG . getLoad ( <STR_LIT> , DL , NewLD1 . getValue ( <NUM_LIT> ) , OffsetPtr , LD -> getPointerInfo ( ) , std :: min ( <NUM_LIT> , LD -> getAlignment ( ) / <NUM_LIT> ) , LD -> getMemOperand ( ) -> getFlags ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , NewLD2 . getValue ( <NUM_LIT> ) ) ; if ( DCI . DAG . getDataLayout ( ) . isBigEndian ( ) ) std :: swap ( NewLD1 , NewLD2 ) ; SDValue Result = DCI . CombineTo ( N , NewLD1 , NewLD2 ) ; return Result ;


<s> case <STR_LIT> : case <STR_LIT> : Res = LowerDivRem ( SDValue ( N , <NUM_LIT> ) , DAG ) ; assert ( Res . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; return ; case <STR_LIT> : ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ; return ; case <STR_LIT> : case <STR_LIT> : assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; return ExpandDIV_Windows ( SDValue ( N , <NUM_LIT> ) , DAG , N -> getOpcode ( ) == <STR_LIT> , Results ) ;


<s> case <STR_LIT> : break ; default : return SDValue ( ) ; } ShuffleVectorSDNode * Op0 = dyn_cast < ShuffleVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; ShuffleVectorSDNode * Op1 = dyn_cast < ShuffleVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! Op0 || ! Op1 || ! Op0 -> getOperand ( <NUM_LIT> ) . isUndef ( ) || ! Op1 -> getOperand ( <NUM_LIT> ) . isUndef ( ) || Op0 -> getMask ( ) != Op1 -> getMask ( ) || Op0 -> getOperand ( <NUM_LIT> ) . getValueType ( ) != VT ) return SDValue ( ) ;

ArrayRef < int > NMask = N -> getMask ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : return SDValue ( ) ; } ShuffleVectorSDNode * Op0 = dyn_cast < ShuffleVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; ShuffleVectorSDNode * Op1 = dyn_cast < ShuffleVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! Op0 || ! Op1 || ! Op0 -> getOperand ( <NUM_LIT> ) . isUndef ( ) || ! Op1 -> getOperand ( <NUM_LIT> ) . isUndef ( ) || Op0 -> getMask ( ) != Op1 -> getMask ( ) || Op0 -> getOperand ( <NUM_LIT> ) . getValueType ( ) != VT ) return SDValue ( ) ; ArrayRef < int > NMask = N -> getMask ( ) ; ArrayRef < int > OpMask = Op0 -> getMask ( ) ; for ( int i = <NUM_LIT> , e = NMask . size ( ) ; i != e ; i ++ ) { if ( NMask [ i ] > <NUM_LIT> && OpMask [ NMask [ i ] ] > <NUM_LIT> && OpMask [ NMask [ i ] ] != i ) return SDValue ( ) ;


<s> Register LsrDestReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpEntry , Dl , TII -> get ( <STR_LIT> ) , LsrDestReg ) . addUse ( BicDestReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . addReg ( <NUM_LIT> ) ; Register TotalIterationsReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpEntry , Dl , TII -> get ( <STR_LIT> ) , TotalIterationsReg ) . addUse ( LsrDestReg , RegState :: Kill ) ;

BuildMI ( TpEntry , Dl , TII -> get ( <STR_LIT> ) ) . addUse ( TotalIterationsReg ) . addMBB ( TpExit ) ;


<s> BuildMI ( TpEntry , Dl , TII -> get ( <STR_LIT> ) , AddDestReg ) . addUse ( OpSizeReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . addReg ( <NUM_LIT> ) ; Register BicDestReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpEntry , Dl , TII -> get ( <STR_LIT> ) , BicDestReg ) . addUse ( AddDestReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . addReg ( <NUM_LIT> ) ; Register LsrDestReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpEntry , Dl , TII -> get ( <STR_LIT> ) , LsrDestReg ) . addUse ( BicDestReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . addReg ( <NUM_LIT> ) ; Register TotalIterationsReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpEntry , Dl , TII -> get ( <STR_LIT> ) , TotalIterationsReg ) . addUse ( LsrDestReg , RegState :: Kill ) ; BuildMI ( TpEntry , Dl , TII -> get ( <STR_LIT> ) ) . addUse ( TotalIterationsReg ) . addMBB ( TpExit ) ; return TotalIterationsReg ;


<s> case CallingConv :: <ISA_LIT>_APCS : case CallingConv :: GHC : case CallingConv :: CFGuard_Check : return CC ; case CallingConv :: PreserveMost : return CallingConv :: PreserveMost ; case CallingConv :: <ISA_LIT>_AAPCS_VFP : case CallingConv :: Swift : case CallingConv :: SwiftTail : return isVarArg ? CallingConv :: <ISA_LIT>_AAPCS : CallingConv :: <ISA_LIT>_AAPCS_VFP ; case CallingConv :: C : if ( ! Subtarget -> isAAPCS_ABI ( ) ) return CallingConv :: <ISA_LIT>_APCS ; else if ( Subtarget -> hasVFP2Base ( ) && ! Subtarget -> isThumb1Only ( ) && getTargetMachine ( ) . Options . FloatABIType == FloatABI :: Hard && ! isVarArg ) return CallingConv :: <ISA_LIT>_AAPCS_VFP ; else return CallingConv :: <ISA_LIT>_AAPCS ; case CallingConv :: Fast : case CallingConv :: CXX_FAST_TLS : if ( ! Subtarget -> isAAPCS_ABI ( ) ) {

if ( Subtarget -> hasVFP2Base ( ) && ! Subtarget -> isThumb1Only ( ) && ! isVarArg ) return CallingConv :: Fast ;


<s> bool Fast ; if ( Op . size ( ) >= <NUM_LIT> && ( Op . isAligned ( Align ( <NUM_LIT> ) ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , Align ( <NUM_LIT> ) , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return <STR_LIT> ; } else if ( Op . size ( ) >= <NUM_LIT> && ( Op . isAligned ( Align ( <NUM_LIT> ) ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , Align ( <NUM_LIT> ) , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) {


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { if ( ( Op . isMemcpy ( ) || Op . isZeroMemset ( ) ) && Subtarget -> hasNEON ( ) && ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Op . size ( ) >= <NUM_LIT> && ( Op . isAligned ( Align ( <NUM_LIT> ) ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , Align ( <NUM_LIT> ) , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return <STR_LIT> ; } else if ( Op . size ( ) >= <NUM_LIT> && ( Op . isAligned ( Align ( <NUM_LIT> ) ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , Align ( <NUM_LIT> ) , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return <STR_LIT> ; } } return <STR_LIT> ;


<s> assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; SDValue Op = N . getOperand ( <NUM_LIT> ) ; EVT FromVT = Op . getValueType ( ) ; SDLoc DL ( N ) ; SDValue And = DAG . getNode ( <STR_LIT> , DL , FromVT , Op , DAG . getConstant ( <NUM_LIT> , DL , FromVT ) ) ;

return DAG . getNode ( <STR_LIT> , DL , VT , And , DAG . getConstant ( <NUM_LIT> , DL , FromVT ) , DAG . getCondCode ( <STR_LIT> ) ) ;


<s> EVT FromVT = Op . getValueType ( ) ; SDLoc DL ( N ) ; SDValue And = DAG . getNode ( <STR_LIT> , DL , FromVT , Op , DAG . getConstant ( <NUM_LIT> , DL , FromVT ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , And , DAG . getConstant ( <NUM_LIT> , DL , FromVT ) , DAG . getCondCode ( <STR_LIT> ) ) ;


<s> if ( X . getValueType ( ) == VT ) return X ; } if ( Op0 . getValueType ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { SDValue BV = Op0 . getOperand ( <NUM_LIT> ) ; unsigned Offset = N -> getConstantOperandVal ( <NUM_LIT> ) ; SDValue MOV = BV . getOperand ( Offset < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( MOV . getOpcode ( ) == <STR_LIT> ) return MOV . getOperand ( ST -> isLittle ( ) ? Offset % <NUM_LIT> : <NUM_LIT> - Offset % <NUM_LIT> ) ; } if ( SDValue R = PerformExtractEltToVMOVRRD ( N , DCI ) ) return R ;


<s> EVT FromEltVT = FromVT . getVectorElementType ( ) ; unsigned NumElements = <NUM_LIT> ; if ( FromEltVT == <STR_LIT> && ( ToEltVT == <STR_LIT> || ToEltVT == <STR_LIT> ) ) NumElements = <NUM_LIT> ; if ( FromEltVT == <STR_LIT> && ToEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( FromEltVT == <STR_LIT> && ToEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( NumElements == <NUM_LIT> || ( FromEltVT != <STR_LIT> && FromVT . getVectorNumElements ( ) == NumElements ) || FromVT . getVectorNumElements ( ) % NumElements != <NUM_LIT> ) return SDValue ( ) ; auto isVMOVNShuffle = [ & ] ( ShuffleVectorSDNode * SVN , bool Rev ) { ArrayRef < int > M = SVN -> getMask ( ) ; unsigned NumElts = ToVT . getVectorNumElements ( ) ; if ( SVN -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) NumElts /= <NUM_LIT> ; unsigned Off0 = Rev ? NumElts : <NUM_LIT> ; unsigned Off1 = Rev ? <NUM_LIT> : NumElts ; for ( unsigned I = <NUM_LIT> ; I < NumElts ; I += <NUM_LIT> ) { if ( M [ I ] >= <NUM_LIT> && M [ I ] != ( int ) ( Off0 + I / <NUM_LIT> ) ) return false ; if ( M [ I + <NUM_LIT> ] >= <NUM_LIT> && M [ I + <NUM_LIT> ] != ( int ) ( Off1 + I / <NUM_LIT> ) ) return false ; } return true ; } ; if ( Trunc . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { if ( SDValue U = PerformVQDMULHCombine ( Trunc . getOperand ( <NUM_LIT> ) . getNode ( ) , DAG ) ) { DAG . ReplaceAllUsesWith ( Trunc . getOperand ( <NUM_LIT> ) , U ) ; return SDValue ( ) ; } } if ( auto * Shuffle = dyn_cast < ShuffleVectorSDNode > ( Trunc . getOperand ( <NUM_LIT> ) ) ) if ( isVMOVNShuffle ( Shuffle , false ) || isVMOVNShuffle ( Shuffle , true ) ) return SDValue ( ) ; LLVMContext & C = * DAG . getContext ( ) ; SDLoc DL ( St ) ; SDValue Ch = St -> getChain ( ) ; SDValue BasePtr = St -> getBasePtr ( ) ; Align Alignment = St -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = St -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = St -> getAAInfo ( ) ; EVT NewFromVT = EVT :: getVectorVT ( C , FromEltVT , NumElements ) ; EVT NewToVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , ToEltVT . getSizeInBits ( ) ) , NumElements ) ;

SmallVector < SDValue , <NUM_LIT> > Stores ;


<s> SDLoc DL ( St ) ; SDValue BasePtr = St -> getBasePtr ( ) ; SDValue NewST1 = DAG . getStore ( St -> getChain ( ) , DL , StVal . getNode ( ) -> getOperand ( isBigEndian ? <NUM_LIT> : <NUM_LIT> ) , BasePtr , St -> getPointerInfo ( ) , St -> getOriginalAlign ( ) , St -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getStore ( NewST1 . getValue ( <NUM_LIT> ) , DL , StVal . getNode ( ) -> getOperand ( isBigEndian ? <NUM_LIT> : <NUM_LIT> ) , OffsetPtr , St -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , St -> getOriginalAlign ( ) , St -> getMemOperand ( ) -> getFlags ( ) ) ; } if ( StVal . getValueType ( ) == <STR_LIT> && StVal . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { SelectionDAG & DAG = DCI . DAG ; SDLoc dl ( StVal ) ; SDValue IntVec = StVal . getOperand ( <NUM_LIT> ) ; EVT FloatVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , IntVec . getValueType ( ) . getVectorNumElements ( ) ) ; SDValue Vec = DAG . getNode ( <STR_LIT> , dl , FloatVT , IntVec ) ; SDValue ExtElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , StVal . getOperand ( <NUM_LIT> ) ) ;


<s> static SDValue PerformSTORECombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { StoreSDNode * St = cast < StoreSDNode > ( N ) ; if ( St -> isVolatile ( ) ) return SDValue ( ) ; SDValue StVal = St -> getValue ( ) ; EVT VT = StVal . getValueType ( ) ; if ( Subtarget -> hasNEON ( ) ) if ( SDValue Store = PerformTruncatingStoreCombine ( St , DCI . DAG ) ) return Store ; if ( Subtarget -> hasMVEIntegerOps ( ) ) { if ( SDValue NewToken = PerformSplittingToNarrowingStores ( St , DCI . DAG ) ) return NewToken ; if ( SDValue NewChain = PerformExtractFpToIntStores ( St , DCI . DAG ) ) return NewChain ; } if ( ! <STR_LIT> ( St ) ) return SDValue ( ) ; if ( StVal . getNode ( ) -> getOpcode ( ) == <STR_LIT> && StVal . getNode ( ) -> hasOneUse ( ) ) { SelectionDAG & DAG = DCI . DAG ; bool isBigEndian = DAG . getDataLayout ( ) . isBigEndian ( ) ; SDLoc DL ( St ) ; SDValue BasePtr = St -> getBasePtr ( ) ; SDValue NewST1 = DAG . getStore ( St -> getChain ( ) , DL , StVal . getNode ( ) -> getOperand ( isBigEndian ? <NUM_LIT> : <NUM_LIT> ) , BasePtr , St -> getPointerInfo ( ) , St -> getOriginalAlign ( ) , St -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getStore ( NewST1 . getValue ( <NUM_LIT> ) , DL , StVal . getNode ( ) -> getOperand ( isBigEndian ? <NUM_LIT> : <NUM_LIT> ) , OffsetPtr , St -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , St -> getOriginalAlign ( ) , St -> getMemOperand ( ) -> getFlags ( ) ) ; } if ( StVal . getValueType ( ) == <STR_LIT> && StVal . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { SelectionDAG & DAG = DCI . DAG ; SDLoc dl ( StVal ) ; SDValue IntVec = StVal . getOperand ( <NUM_LIT> ) ; EVT FloatVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , IntVec . getValueType ( ) . getVectorNumElements ( ) ) ; SDValue Vec = DAG . getNode ( <STR_LIT> , dl , FloatVT , IntVec ) ; SDValue ExtElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , StVal . getOperand ( <NUM_LIT> ) ) ; dl = SDLoc ( N ) ;

SDValue V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ExtElt ) ;


<s> if ( ! Subtarget -> hasMVEIntegerOps ( ) || ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) ) return SDValue ( ) ; SDValue VDup = N -> getOperand ( <NUM_LIT> ) ; if ( VDup -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue VMov = N -> getOperand ( <NUM_LIT> ) ; if ( VMov -> getOpcode ( ) == <STR_LIT> ) VMov = VMov -> getOperand ( <NUM_LIT> ) ; if ( VMov -> getOpcode ( ) != <STR_LIT> || ! isZeroVector ( VMov ) ) return SDValue ( ) ; SDLoc dl ( N ) ; SDValue Negate = DCI . DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DCI . DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , VDup -> getOperand ( <NUM_LIT> ) ) ;

return DCI . DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , Negate ) ;


<s> SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N1 . getNode ( ) -> hasOneUse ( ) ) if ( SDValue Result = combineSelectAndUse ( N , N1 , N0 , DCI ) ) return Result ; if ( SDValue R = PerformSubCSINCCombine ( N , DCI ) ) return R ; if ( ! Subtarget -> hasMVEIntegerOps ( ) || ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) ) return SDValue ( ) ; SDValue VDup = N -> getOperand ( <NUM_LIT> ) ; if ( VDup -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue VMov = N -> getOperand ( <NUM_LIT> ) ; if ( VMov -> getOpcode ( ) == <STR_LIT> ) VMov = VMov -> getOperand ( <NUM_LIT> ) ; if ( VMov -> getOpcode ( ) != <STR_LIT> || ! isZeroVector ( VMov ) ) return SDValue ( ) ; SDLoc dl ( N ) ;

SDValue Negate = DCI . DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DCI . DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , VDup -> getOperand ( <NUM_LIT> ) ) ;


<s> static SDValue PerformSubCSINCCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI ) { if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> || ! isNullConstant ( N -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue CSINC = N -> getOperand ( <NUM_LIT> ) ; if ( CSINC . getOpcode ( ) != <STR_LIT> || ! CSINC . hasOneUse ( ) ) return SDValue ( ) ;

ConstantSDNode * X = dyn_cast < ConstantSDNode > ( CSINC . getOperand ( <NUM_LIT> ) ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; SDLoc dl ( N ) ; if ( ST -> isLittle ( ) ) return DCI . DAG . getNode ( <STR_LIT> , dl , VT , Op ) ; if ( Op . isUndef ( ) ) return DCI . DAG . getUNDEF ( VT ) ; if ( Op -> getOpcode ( ) == <STR_LIT> ) { if ( Op -> getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) return Op -> getOperand ( <NUM_LIT> ) ; return DCI . DAG . getNode ( <STR_LIT> , dl , VT , Op -> getOperand ( <NUM_LIT> ) ) ;


<s> SDValue NewConcat = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 . getOperand ( <NUM_LIT> ) , Op1 . getOperand ( <NUM_LIT> ) ) ; SmallVector < int , <NUM_LIT> > NewMask ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned HalfElts = NumElts / <NUM_LIT> ; ShuffleVectorSDNode * SVN = cast < ShuffleVectorSDNode > ( N ) ; for ( unsigned n = <NUM_LIT> ; n < NumElts ; ++ n ) { int MaskElt = SVN -> getMaskElt ( n ) ; int NewElt = - <NUM_LIT> ; if ( MaskElt < ( int ) HalfElts ) NewElt = MaskElt ; else if ( MaskElt >= ( int ) NumElts && MaskElt < ( int ) ( NumElts + HalfElts ) ) NewElt = HalfElts + MaskElt - NumElts ; NewMask . push_back ( NewElt ) ; } return DAG . getVectorShuffle ( VT , SDLoc ( N ) , NewConcat , DAG . getUNDEF ( VT ) , NewMask ) ;


<s> if ( SDValue R = FlattenVectorShuffle ( cast < ShuffleVectorSDNode > ( N ) , DAG ) ) return R ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> || Op1 . getOpcode ( ) != <STR_LIT> || Op0 . getNumOperands ( ) != <NUM_LIT> || Op1 . getNumOperands ( ) != <NUM_LIT> ) return SDValue ( ) ; SDValue Concat0Op1 = Op0 . getOperand ( <NUM_LIT> ) ; SDValue Concat1Op1 = Op1 . getOperand ( <NUM_LIT> ) ; if ( ! Concat0Op1 . isUndef ( ) || ! Concat1Op1 . isUndef ( ) ) return SDValue ( ) ;

const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ;


<s> SDValue Load = DCI . DAG . getExtLoad ( <STR_LIT> , SDLoc ( N ) , VT , LN0 -> getChain ( ) , LN0 -> getBasePtr ( ) , <STR_LIT> , LN0 -> getMemOperand ( ) ) ; DCI . DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; DCI . DAG . ReplaceAllUsesOfValueWith ( N0 . getValue ( <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; return Load ;


<s> } if ( Shft . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * N1 = isConstOrConstSplat ( Shft . getOperand ( <NUM_LIT> ) ) ; if ( ! N1 || N1 -> getSExtValue ( ) != ShftAmt ) return SDValue ( ) ; SDValue Mul = Shft . getOperand ( <NUM_LIT> ) ; if ( Mul . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Ext0 = Mul . getOperand ( <NUM_LIT> ) ; SDValue Ext1 = Mul . getOperand ( <NUM_LIT> ) ; if ( Ext0 . getOpcode ( ) != <STR_LIT> || Ext1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT VecVT = Ext0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( VecVT != <STR_LIT> && VecVT != <STR_LIT> && VecVT != <STR_LIT> ) return SDValue ( ) ;

if ( Ext1 . getOperand ( <NUM_LIT> ) . getValueType ( ) != VecVT || VecVT . getScalarType ( ) != ScalarType || VT . getScalarSizeInBits ( ) < ScalarType . getScalarSizeInBits ( ) * <NUM_LIT> ) return SDValue ( ) ;


<s> Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; bool isInt = OpVT . isInteger ( ) ; CC = <STR_LIT> ( CC , isInt ) ; if ( ! TLI . isCondCodeLegal ( CC , OpVT ) ) return SDValue ( ) ; DoXform = true ; InvCC = true ; } if ( DoXform ) { SDValue Result = DAG . getNode ( Opc , RHS . getDebugLoc ( ) , VT , OtherOp , RHS ) ; if ( isSlctCC ) return DAG . getSelectCC ( N -> getDebugLoc ( ) , OtherOp , Result , Slct . getOperand ( <NUM_LIT> ) , Slct . getOperand ( <NUM_LIT> ) , CC ) ; SDValue CCOp = Slct . getOperand ( <NUM_LIT> ) ; if ( InvCC ) CCOp = DAG . getSetCC ( Slct . getDebugLoc ( ) , CCOp . getValueType ( ) , CCOp . getOperand ( <NUM_LIT> ) , CCOp . getOperand ( <NUM_LIT> ) , CC ) ; return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , VT , CCOp , OtherOp , Result ) ; }


<s> MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addMBB ( sinkMBB ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; for ( MachineBasicBlock :: succ_iterator i = BB -> succ_begin ( ) , e = BB -> succ_end ( ) ; i != e ; ++ i ) sinkMBB -> addSuccessor ( * i ) ; while ( ! BB -> succ_empty ( ) ) BB -> removeSuccessor ( BB -> succ_begin ( ) ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ;


<s> EmittedNumMemOps += i ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; unsigned BytesLeftSave = BytesLeft ; i = <NUM_LIT> ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , <STR_LIT> ) ) , SrcSV , SrcSVOff + SrcOff ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; ++ i ; SrcOff += VTSize ; BytesLeft -= VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & TFOps [ <NUM_LIT> ] , i ) ; i = <NUM_LIT> ; BytesLeft = BytesLeftSave ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } TFOps [ i ] = DAG . getStore ( Chain , dl , Loads [ i ] , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Dst , DAG . getConstant ( DstOff , <STR_LIT> ) ) , DstSV , DstSVOff + DstOff ) ; ++ i ; DstOff += VTSize ; BytesLeft -= VTSize ; }

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & TFOps [ <NUM_LIT> ] , i ) ;


<s> SDValue Op = N -> getOperand ( <NUM_LIT> ) ; DebugLoc dl = N -> getDebugLoc ( ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; } SDValue Cvt = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Op , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cvt , Cvt . getValue ( <NUM_LIT> ) ) ;


<s> SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; unsigned Opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Hi = DAG . getNode ( Opc , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Hi , <NUM_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi . getValue ( <NUM_LIT> ) ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ;


<s> case <STR_LIT> : CondCode = <STR_LIT> ; Invert = true ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; CondCode2 = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; CondCode2 = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CondCode = <STR_LIT> ; break ;


<s> static bool FPCCTo<ISA_LIT>CC ( <STR_LIT> CC , <STR_LIT> & CondCode , <STR_LIT> & CondCode2 ) { bool Invert = false ; CondCode2 = <STR_LIT> ; switch ( CC ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; Invert = true ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; CondCode2 = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; CondCode2 = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ;


<s> if ( isLegalCmpImmediate ( C - <NUM_LIT> , isThumb ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C - <NUM_LIT> , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C > <NUM_LIT> && isLegalCmpImmediate ( C - <NUM_LIT> , isThumb ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C - <NUM_LIT> , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( isLegalCmpImmediate ( C + <NUM_LIT> , isThumb ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C < <NUM_LIT> && isLegalCmpImmediate ( C + <NUM_LIT> , isThumb ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , <STR_LIT> ) ; } break ; } } } <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; <STR_LIT> CompareType ; switch ( CondCode ) { default : CompareType = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CompareType = <STR_LIT> ; break ; }

<ISA_LIT>CC = DAG . getConstant ( CondCode , <STR_LIT> ) ;


<s> switch ( CC ) { default : break ; case <STR_LIT> : case <STR_LIT> : if ( isLegalCmpImmediate ( C - <NUM_LIT> , isThumb ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C - <NUM_LIT> , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C > <NUM_LIT> && isLegalCmpImmediate ( C - <NUM_LIT> , isThumb ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C - <NUM_LIT> , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( isLegalCmpImmediate ( C + <NUM_LIT> , isThumb ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C < <NUM_LIT> && isLegalCmpImmediate ( C + <NUM_LIT> , isThumb ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , <STR_LIT> ) ; } break ; }


<s> Offset = DAG . getConstant ( - RHSC , RHS -> getValueType ( <NUM_LIT> ) ) ; Base = Ptr -> getOperand ( <NUM_LIT> ) ; return true ; } } if ( Ptr -> getOpcode ( ) == <STR_LIT> ) { isInc = true ; <STR_LIT> ShOpcVal = <STR_LIT> ( Ptr -> getOperand ( <NUM_LIT> ) ) ; if ( ShOpcVal != <STR_LIT> ) { Base = Ptr -> getOperand ( <NUM_LIT> ) ; Offset = Ptr -> getOperand ( <NUM_LIT> ) ; } else { Base = Ptr -> getOperand ( <NUM_LIT> ) ; Offset = Ptr -> getOperand ( <NUM_LIT> ) ; } return true ; } isInc = ( Ptr -> getOpcode ( ) == <STR_LIT> ) ; Base = Ptr -> getOperand ( <NUM_LIT> ) ;


<s> isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; } else return false ; bool isInc ; bool isLegal = getIndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( isLegal ) { AM = isInc ? <STR_LIT> : <STR_LIT> ; return true ; }


<s> VT = LD -> getMemoryVT ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; } else return false ; bool isInc ; bool isLegal = getIndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( isLegal ) { AM = isInc ? <STR_LIT> : <STR_LIT> ; return true ; }


<s> SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; } else return false ; bool isInc ; bool isLegal = getIndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ;


<s> switch ( Constraint [ <NUM_LIT> ] ) { case 'l' : case 'r' : return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; case 'w' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; break ; }


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> if ( GV -> hasHiddenVisibility ( ) && ( ! isDecl && ! GV -> hasCommonLinkage ( ) ) ) return false ;

return RelocM != Reloc :: Static && ( isDecl || GV -> isWeakForLinker ( ) ) ;


<s> bool isDecl = GV -> isDeclaration ( ) && ! GV -> hasNotBeenReadFromBitcode ( ) ; if ( GV -> hasHiddenVisibility ( ) && ( ! isDecl && ! GV -> hasCommonLinkage ( ) ) ) return false ;


<s> switch ( ObjectVT . getSimpleVT ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( firstGPR < <NUM_LIT> ) NeededGPRs = <NUM_LIT> ; else NeededStackSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : if ( firstGPR < <NUM_LIT> ) NeededGPRs = <NUM_LIT> ; else if ( firstGPR == <NUM_LIT> ) { NeededGPRs = <NUM_LIT> ;


<s> GPRPad = NumGPRs % ( ( align + <NUM_LIT> ) / <NUM_LIT> ) ; StackPad = StackOffset % align ; unsigned firstGPR = NumGPRs + GPRPad ; switch ( ObjectVT . getSimpleVT ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( firstGPR < <NUM_LIT> ) NeededGPRs = <NUM_LIT> ; else NeededStackSize = <NUM_LIT> ; break ;


<s> break ; case <STR_LIT> : Scale = <NUM_LIT> ; break ; } if ( ( V & ( Scale - <NUM_LIT> ) ) != <NUM_LIT> ) return false ; V /= Scale ; return V == ( V & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) ; } if ( V < <NUM_LIT> ) V = - V ; switch ( VT . getSimpleVT ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return V == ( V & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) ; case <STR_LIT> : return V == ( V & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( ( V & <NUM_LIT> ) != <NUM_LIT> ) return false ; V >>= <NUM_LIT> ; return V == ( V & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) ;


<s> case <STR_LIT> : if ( Scale < <NUM_LIT> ) Scale = - Scale ; if ( Scale == <NUM_LIT> ) return true ; return isPowerOf2_32 ( Scale & ~ <NUM_LIT> ) ; case <STR_LIT> : if ( ( ( unsigned ) AM . HasBaseReg + Scale ) <= <NUM_LIT> ) return true ; return false ; case <STR_LIT> : if ( AM . Scale & <NUM_LIT> ) return false ; return isPowerOf2_32 ( AM . Scale ) ; } break ; }


<s> return ( isThumb && ( C & ~ <NUM_LIT> ) == <NUM_LIT> ) || ( ! isThumb && <STR_LIT> ( C ) != - <NUM_LIT> ) ;


<s> return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>CC , CCR , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; <STR_LIT> CondCode , CondCode2 ; if ( FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ) std :: swap ( LHS , RHS ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue <ISA_LIT>CC = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Dest , <ISA_LIT>CC , CCR , Cmp } ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , VTList , Ops , <NUM_LIT> ) ; if ( CondCode2 != <STR_LIT> ) { <ISA_LIT>CC = DAG . getConstant ( CondCode2 , <STR_LIT> ) ; SDValue Ops [ ] = { Res , Dest , <ISA_LIT>CC , CCR , Res . getValue ( <NUM_LIT> ) } ;


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>CC ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>CC , DAG , ST -> isThumb ( ) , dl ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>CC , CCR , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; <STR_LIT> CondCode , CondCode2 ; if ( FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ) std :: swap ( LHS , RHS ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue <ISA_LIT>CC = DAG . getConstant ( CondCode , <STR_LIT> ) ;


<s> bool isPIC = getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; Addr = DAG . getLoad ( isPIC ? ( MVT ) <STR_LIT> : PTy , dl , Chain , Addr , NULL , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; if ( isPIC ) Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Addr , Table ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , JTI , UId ) ;


<s> SDValue Table = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; MVT PTy = getPointerTy ( ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Table ) ; <ISA_LIT>FunctionInfo * AFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; SDValue UId = DAG . getConstant ( AFI -> createJumpTableUId ( ) , PTy ) ;

SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PTy ) ;


<s> static SDValue LowerConstantPool ( SDValue Op , SelectionDAG & DAG ) { MVT PtrVT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; ConstantPoolSDNode * CP = cast < ConstantPoolSDNode > ( Op ) ; SDValue Res ; if ( CP -> isMachineConstantPoolEntry ( ) ) Res = DAG . getTargetConstantPool ( CP -> getMachineCPVal ( ) , PtrVT , CP -> getAlignment ( ) ) ; else Res = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlignment ( ) ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res ) ;


<s> SDValue AbsVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp0 ) ; SDValue Cmp = getVFPCmp ( Tmp1 , DAG . getConstantFP ( <NUM_LIT> , SrcVT ) , DAG , dl ) ; SDValue <ISA_LIT>CC = DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , AbsVal , AbsVal , <ISA_LIT>CC , CCR , Cmp ) ;


<s> SDValue AbsVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp0 ) ; SDValue Cmp = getVFPCmp ( Tmp1 , DAG . getConstantFP ( <NUM_LIT> , SrcVT ) , DAG , dl ) ; SDValue <ISA_LIT>CC = DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , AbsVal , AbsVal , <ISA_LIT>CC , CCR , Cmp ) ;


<s> RegInfo . addLiveIn ( GPRArgRegs [ NumGPRs ] , VReg ) ; ArgValue = DAG . getCopyFromReg ( Root , dl , VReg , <STR_LIT> ) ; VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( GPRArgRegs [ NumGPRs + <NUM_LIT> ] , VReg ) ; SDValue ArgValue2 = DAG . getCopyFromReg ( Root , dl , VReg , <STR_LIT> ) ; assert ( ObjectVT != <STR_LIT> && <STR_LIT> ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue2 ) ; } NumGPRs += ObjGPRs ; if ( ObjSize ) { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int FI = MFI -> CreateFixedObject ( ObjSize , ArgOffset ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; if ( ObjGPRs == <NUM_LIT> ) ArgValue = DAG . getLoad ( ObjectVT , dl , Root , FIN , NULL , <NUM_LIT> ) ; else { SDValue ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Root , FIN , NULL , <NUM_LIT> ) ; assert ( ObjectVT != <STR_LIT> && <STR_LIT> ) ;


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; unsigned VARegSize = ( <NUM_LIT> - NumGPRs ) * <NUM_LIT> ; unsigned VARegSaveSize = ( VARegSize + Align - <NUM_LIT> ) & ~ ( Align - <NUM_LIT> ) ; if ( VARegSaveSize ) { AFI -> setVarArgsRegSaveSize ( VARegSaveSize ) ; VarArgsFrameIndex = MFI -> CreateFixedObject ( VARegSaveSize , ArgOffset + VARegSaveSize - VARegSize ) ; SDValue FIN = DAG . getFrameIndex ( VarArgsFrameIndex , getPointerTy ( ) ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; for ( ; NumGPRs < <NUM_LIT> ; ++ NumGPRs ) { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( GPRArgRegs [ NumGPRs ] , VReg ) ; SDValue Val = DAG . getCopyFromReg ( Root , dl , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , NULL , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FIN , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ) ; }

if ( ! MemOps . empty ( ) ) Root = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOps [ <NUM_LIT> ] , MemOps . size ( ) ) ;


<s> Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; bool IsIndirect = GVIsIndirectSymbol ( GV , RelocM ) ; SDValue CPAddr ; if ( RelocM == Reloc :: Static ) CPAddr = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> ) ; else { unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <STR_LIT> Kind = IsIndirect ? <STR_LIT> : <STR_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , <ISA_LIT>PCLabelIndex , Kind , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , NULL , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; if ( RelocM == Reloc :: PIC_ ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex ++ , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ;


<s> GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; if ( RelocM == Reloc :: PIC_ ) { bool UseGOTOFF = GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , <STR_LIT> , UseGOTOFF ? <STR_LIT> : <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , NULL , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , GOT ) ; if ( ! UseGOTOFF ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , NULL , <NUM_LIT> ) ; return Result ; } else { SDValue CPAddr = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , NULL , <NUM_LIT> ) ; }


<s> SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ;

SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , NULL , <NUM_LIT> ) ;


<s> static SDValue LowerINTRINSIC_WO_CHAIN ( SDValue Op , SelectionDAG & DAG ) { MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) {


<s> static SDValue LowerINTRINSIC_WO_CHAIN ( SDValue Op , SelectionDAG & DAG ) { MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ;

unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Opc = Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ;

return DAG . getNode ( Opc , dl , VT , Op ) ;


<s> static SDValue LowerINT_TO_FP ( SDValue Op , SelectionDAG & DAG ) { MVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Opc = Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( Opc , dl , VT , Op ) ;


<s> case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , VarArgsFrameIndex ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerFORMAL_ARGUMENTS ( Op , DAG ) ; case <STR_LIT> : break ; case <STR_LIT> : break ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return ExpandBIT_CONVERT ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : return ExpandSRx ( Op . getNode ( ) , DAG , Subtarget ) ;


<s> } else if ( Op . getValueType ( ) == <STR_LIT> ) { Op = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Op , <NUM_LIT> ) ; SDValue Sign = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Op , Sign , Op . getValue ( <NUM_LIT> ) , Sign ) ; } Copy = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Op , SDValue ( ) ) ; if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( <STR_LIT> ) ; break ; case <NUM_LIT> : Copy = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; Copy = DAG . getCopyToReg ( Copy , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Copy . getValue ( <NUM_LIT> ) ) ; if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( <STR_LIT> ) ; DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( <STR_LIT> ) ; } break ; case <NUM_LIT> : Copy = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; Copy = DAG . getCopyToReg ( Copy , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Copy . getValue ( <NUM_LIT> ) ) ;


<s> SDValue <ISA_LIT>CC = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , <ISA_LIT>CC , CCR , Cmp ) ; if ( CondCode2 != <STR_LIT> ) { SDValue <ISA_LIT>CC2 = DAG . getConstant ( CondCode2 , <STR_LIT> ) ; SDValue Cmp2 = getVFPCmp ( LHS , RHS , DAG , dl ) ;

Result = DAG . getNode ( <STR_LIT> , dl , VT , Result , TrueVal , <ISA_LIT>CC2 , CCR , Cmp2 ) ;


<s> } <STR_LIT> CondCode , CondCode2 ; if ( FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ) std :: swap ( TrueVal , FalseVal ) ; SDValue <ISA_LIT>CC = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , <ISA_LIT>CC , CCR , Cmp ) ; if ( CondCode2 != <STR_LIT> ) { SDValue <ISA_LIT>CC2 = DAG . getConstant ( CondCode2 , <STR_LIT> ) ; SDValue Cmp2 = getVFPCmp ( LHS , RHS , DAG , dl ) ;


<s> Chain = Offset . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex ++ , <STR_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT , Offset , PICLabel ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , NULL , <NUM_LIT> ) ; } else { <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , <STR_LIT> , <STR_LIT> ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , NULL , <NUM_LIT> ) ; } return DAG . getNode ( <STR_LIT> , dl , PtrVT , ThreadPointer , Offset ) ;


<s> unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , NULL , <NUM_LIT> ) ; SDValue Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex ++ , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Argument ; Entry . Ty = ( const Type * ) Type :: Int32Ty ; Args . push_back ( Entry ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( Chain , ( const Type * ) Type :: Int32Ty , false , false , false , false , CallingConv :: C , false , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , Args , DAG , dl ) ; return CallResult . first ;


<s> Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , NULL , <NUM_LIT> ) ; SDValue Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex ++ , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ;


<s> static SDValue LowerVASTART ( SDValue Op , SelectionDAG & DAG , unsigned VarArgsFrameIndex ) { DebugLoc dl = Op . getDebugLoc ( ) ;

MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ;


<s> MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue FR = DAG . getFrameIndex ( VarArgsFrameIndex , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;

return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FR , Op . getOperand ( <NUM_LIT> ) , SV , <NUM_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : return PerformADDCombine ( N , DCI ) ;

case <STR_LIT> : return PerformSUBCombine ( N , DCI ) ;


<s> case <STR_LIT> : return PerformSUBCombine ( N , DCI ) ; case <STR_LIT> : return PerformFMRRDCombine ( N , DCI ) ; } return SDValue ( ) ;


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; return ; case <STR_LIT> : Results . push_back ( ExpandBIT_CONVERT ( N , DAG ) ) ; return ; case <STR_LIT> : case <STR_LIT> : { SDValue Res = ExpandSRx ( N , DAG , Subtarget ) ; if ( Res . getNode ( ) ) Results . push_back ( Res ) ;


<s> unsigned dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned incr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ord = static_cast < AtomicOrdering > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; bool isThumb2 = Subtarget -> isThumb2 ( ) ; MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; if ( isThumb2 ) { MRI . constrainRegClass ( dest , & <STR_LIT> ) ; MRI . constrainRegClass ( ptr , & <STR_LIT> ) ; MRI . constrainRegClass ( incr , & <STR_LIT> ) ; } unsigned ldrOpc , strOpc ; getExclusiveOperation ( Size , Ord , isThumb2 , ldrOpc , strOpc ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; const TargetRegisterClass * TRC = isThumb2 ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned scratch = MRI . createVirtualRegister ( TRC ) ; unsigned scratch2 = ( ! BinOpcode ) ? incr : MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; MachineInstrBuilder MIB = BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( ldrOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; if ( BinOpcode ) { if ( BinOpcode == <STR_LIT> || BinOpcode == <STR_LIT> ) AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( incr ) . addReg ( dest ) ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( dest ) . addReg ( incr ) ) . addReg ( <NUM_LIT> ) ; } MIB = BuildMI ( BB , dl , TII -> get ( strOpc ) , scratch ) . addReg ( scratch2 ) . addReg ( ptr ) ; if ( strOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( scratch ) . addImm ( <NUM_LIT> ) ) ;

BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( loopMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> getExclusiveOperation ( Size , Ord , isThumb2 , ldrOpc , strOpc ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; const TargetRegisterClass * TRC = isThumb2 ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned scratch = MRI . createVirtualRegister ( TRC ) ; unsigned scratch2 = ( ! BinOpcode ) ? incr : MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; MachineInstrBuilder MIB = BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( ldrOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; if ( BinOpcode ) { if ( BinOpcode == <STR_LIT> || BinOpcode == <STR_LIT> ) AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( incr ) . addReg ( dest ) ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( dest ) . addReg ( incr ) ) . addReg ( <NUM_LIT> ) ; } MIB = BuildMI ( BB , dl , TII -> get ( strOpc ) , scratch ) . addReg ( scratch2 ) . addReg ( ptr ) ; if ( strOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( scratch ) . addImm ( <NUM_LIT> ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( loopMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor ( loopMBB ) ; BB -> addSuccessor ( exitMBB ) ;


<s> BB = loopMBB ; MachineInstrBuilder MIB = BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( ldrOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; if ( signExtend && extendOpc ) { oldval = MRI . createVirtualRegister ( isThumb2 ? & <STR_LIT> : & <STR_LIT> ) ; if ( ! isThumb2 ) MRI . constrainRegClass ( dest , & <STR_LIT> ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( extendOpc ) , oldval ) . addReg ( dest ) . addImm ( <NUM_LIT> ) ) ; } AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( oldval ) . addReg ( incr ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) , scratch2 ) . addReg ( incr ) . addReg ( oldval ) . addImm ( Cond ) . addReg ( <STR_LIT> ) ; MIB = BuildMI ( BB , dl , TII -> get ( strOpc ) , scratch ) . addReg ( scratch2 ) . addReg ( ptr ) ; if ( strOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( scratch ) . addImm ( <NUM_LIT> ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( loopMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor ( loopMBB ) ; BB -> addSuccessor ( exitMBB ) ; BB = exitMBB ; MI -> eraseFromParent ( ) ; return BB ;


<s> MRI . constrainRegClass ( newval , & <STR_LIT> ) ; } unsigned ldrOpc , strOpc ; getExclusiveOperation ( Size , Ord , isThumb2 , ldrOpc , strOpc ) ; MachineFunction * MF = BB -> getParent ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; BB = loop1MBB ; MachineInstrBuilder MIB = BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( ldrOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( dest ) . addReg ( oldval ) ) ;

BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( exitMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> AtomicOrdering Ord = static_cast < AtomicOrdering > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; bool isThumb2 = Subtarget -> isThumb2 ( ) ; MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; if ( isThumb2 ) { MRI . constrainRegClass ( destlo , & <STR_LIT> ) ; MRI . constrainRegClass ( desthi , & <STR_LIT> ) ; MRI . constrainRegClass ( ptr , & <STR_LIT> ) ; } unsigned ldrOpc , strOpc ; getExclusiveOperation ( <NUM_LIT> , Ord , isThumb2 , ldrOpc , strOpc ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , dl , TII -> get ( ldrOpc ) ) ; if ( isThumb2 ) { MIB . addReg ( destlo , RegState :: Define ) . addReg ( desthi , RegState :: Define ) . addReg ( ptr ) ; } else { unsigned GPRPair0 = MRI . createVirtualRegister ( & <STR_LIT> ) ; MIB . addReg ( GPRPair0 , RegState :: Define ) . addReg ( ptr ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , destlo ) . addReg ( GPRPair0 , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , desthi ) . addReg ( GPRPair0 , <NUM_LIT> , <STR_LIT> ) ; } AddDefaultPred ( MIB ) ; MI -> eraseFromParent ( ) ;


<s> static const unsigned LoadAcqs [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; static const unsigned StoreBares [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; static const unsigned StoreRels [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ;

const unsigned ( * LoadOps ) [ <NUM_LIT> ] , ( * StoreOps ) [ <NUM_LIT> ] ;


<s> static void getExclusiveOperation ( unsigned Size , AtomicOrdering Ord , bool isThumb2 , unsigned & LdrOpc , unsigned & StrOpc ) { static const unsigned LoadBares [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; static const unsigned LoadAcqs [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; static const unsigned StoreBares [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ;

static const unsigned StoreRels [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ;


<s> static <STR_LIT> getInverseCCForVSEL ( <STR_LIT> CC ) {

if ( CC == <STR_LIT> ) return <STR_LIT> ;


<s> static SDValue LowerInterruptReturn ( SmallVectorImpl < SDValue > & RetOps , SDLoc DL , SelectionDAG & DAG ) { const MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * F = MF . getFunction ( ) ; StringRef IntKind = F -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; int64_t LROffset ; if ( IntKind == <STR_LIT> || IntKind == <STR_LIT> || IntKind == <STR_LIT> || IntKind == <STR_LIT> ) LROffset = <NUM_LIT> ; else if ( IntKind == <STR_LIT> || IntKind == <STR_LIT> ) LROffset = <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return LowerSDIV ( Op , DAG ) ; case <STR_LIT> : return LowerUDIV ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerAtomicLoadStore ( Op , DAG ) ;

case <STR_LIT> : return LowerFSINCOS ( Op , DAG ) ;


<s> RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Arg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } SDValue fmrrd = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Arg , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd . getValue ( <NUM_LIT> ) , Flag ) ;

} else Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Arg , Flag ) ;


<s> Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( i ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; } SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getAtomic ( Node -> getOpcode ( ) , dl , <STR_LIT> , Tys , Ops . data ( ) , Ops . size ( ) , cast < MemSDNode > ( Node ) -> getMemOperand ( ) , AN -> getOrdering ( ) , AN -> getSynchScope ( ) ) ;

SDValue OpsF [ ] = { Result . getValue ( <NUM_LIT> ) , Result . getValue ( <NUM_LIT> ) } ;


<s> Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i < Node -> getNumOperands ( ) ; i ++ ) { Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( i ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( i ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; } SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getAtomic ( Node -> getOpcode ( ) , dl , <STR_LIT> , Tys , Ops . data ( ) , Ops . size ( ) , cast < MemSDNode > ( Node ) -> getMemOperand ( ) , AN -> getOrdering ( ) , AN -> getSynchScope ( ) ) ; SDValue OpsF [ ] = { Result . getValue ( <NUM_LIT> ) , Result . getValue ( <NUM_LIT> ) } ;

Results . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OpsF , <NUM_LIT> ) ) ;


<s> MCID = & TII -> get ( NewOpc ) ; assert ( MCID -> getNumOperands ( ) == MI . getDesc ( ) . getNumOperands ( ) + <NUM_LIT> - MI . getDesc ( ) . getSize ( ) && <STR_LIT> <STR_LIT> ) ; MI . setDesc ( * MCID ) ; MI . addOperand ( MachineOperand :: CreateReg ( <NUM_LIT> , true ) ) ; if ( Subtarget -> isThumb1Only ( ) ) { for ( unsigned c = MCID -> getNumOperands ( ) - <NUM_LIT> ; c -- ; ) { MI . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; MI . removeOperand ( <NUM_LIT> ) ; } for ( unsigned i = MI . getNumOperands ( ) ; i -- ; ) { const MachineOperand & op = MI . getOperand ( i ) ; if ( op . isReg ( ) && op . isUse ( ) ) { int DefIdx = MCID -> getOperandConstraint ( i , MCOI :: TIED_TO ) ; if ( DefIdx != - <NUM_LIT> ) MI . tieOperands ( DefIdx , i ) ; } } MI . addOperand ( MachineOperand :: CreateImm ( <STR_LIT> ) ) ; MI . addOperand ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; ccOutIdx = <NUM_LIT> ; } else ccOutIdx = MCID -> getNumOperands ( ) - <NUM_LIT> ;


<s> static bool checkAndUpdateCPSRKill ( MachineBasicBlock :: iterator SelectItr , MachineBasicBlock * BB , const TargetRegisterInfo * TRI ) { MachineBasicBlock :: iterator miI ( std :: next ( SelectItr ) ) ; for ( MachineBasicBlock :: iterator miE = BB -> end ( ) ; miI != miE ; ++ miI ) { const MachineInstr & mi = * miI ; if ( mi . readsRegister ( <STR_LIT> ) ) return false ; if ( mi . definesRegister ( <STR_LIT> ) ) break ; } if ( miI == BB -> end ( ) ) {

for ( MachineBasicBlock * Succ : BB -> successors ( ) ) if ( Succ -> isLiveIn ( <STR_LIT> ) ) return false ;


<s> if ( findPointerConstIncrement ( Addr . getNode ( ) , & Base , & CInc ) ) { unsigned Offset = getPointerConstIncrement ( Addr -> getOpcode ( ) , Base , CInc , DCI . DAG ) ; for ( SDNode :: use_iterator UI = Base -> use_begin ( ) , UE = Base -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; if ( UI . getUse ( ) . getResNo ( ) != Base . getResNo ( ) || User == Addr . getNode ( ) || User -> getNumOperands ( ) != <NUM_LIT> ) continue ; SDValue UserInc = User -> getOperand ( UI . getOperandNo ( ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; unsigned UserOffset = getPointerConstIncrement ( User -> getOpcode ( ) , Base , UserInc , DCI . DAG ) ; if ( ! UserOffset || UserOffset <= Offset ) continue ; unsigned NewConstInc = UserOffset - Offset ; SDValue NewInc = DCI . DAG . getConstant ( NewConstInc , SDLoc ( N ) , <STR_LIT> ) ; BaseUpdates . push_back ( { User , NewInc , NewConstInc } ) ; } } unsigned NumValidUpd = BaseUpdates . size ( ) ; for ( unsigned I = <NUM_LIT> ; I < NumValidUpd ; ) { BaseUpdateUser & User = BaseUpdates [ I ] ; if ( ! isValidBaseUpdate ( N , User . N ) ) {


<s> Value * LoHi = Builder . CreateCall ( Ldrex , Addr , <STR_LIT> ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Lo = Builder . CreateZExt ( Lo , ValueTy , <STR_LIT> ) ; Hi = Builder . CreateZExt ( Hi , ValueTy , <STR_LIT> ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValueTy , <NUM_LIT> ) ) , <STR_LIT> ) ; }

Type * Tys [ ] = { Addr -> getType ( ) } ;


<s> Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = isReleaseOrStronger ( Ord ) ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Function * Strex = <STR_LIT> ( M , Int ) ; Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , <STR_LIT> ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , <NUM_LIT> ) , Int32Ty , <STR_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Strex , { Lo , Hi , Addr } ) ;


<s> Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , <STR_LIT> ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , <NUM_LIT> ) , Int32Ty , <STR_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Strex , { Lo , Hi , Addr } ) ; } <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Strex = <STR_LIT> ( M , Int , Tys ) ; CallInst * CI = Builder . CreateCall ( Strex , { Builder . CreateZExtOrBitCast ( Val , Strex -> getFunctionType ( ) -> getParamType ( <NUM_LIT> ) ) , Addr } ) ;

CI -> addParamAttr ( <NUM_LIT> , Attribute :: get ( M -> getContext ( ) , Attribute :: ElementType , Val -> getType ( ) ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : return SDValue ( ) ; } ShuffleVectorSDNode * Op0 = dyn_cast < ShuffleVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; ShuffleVectorSDNode * Op1 = dyn_cast < ShuffleVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! Op0 || ! Op1 || ! Op0 -> getOperand ( <NUM_LIT> ) . isUndef ( ) || ! Op1 -> getOperand ( <NUM_LIT> ) . isUndef ( ) || Op0 -> getMask ( ) != Op1 -> getMask ( ) || Op0 -> getOperand ( <NUM_LIT> ) . getValueType ( ) != VT ) return SDValue ( ) ; ArrayRef < int > NMask = N -> getMask ( ) ; ArrayRef < int > OpMask = Op0 -> getMask ( ) ; for ( int i = <NUM_LIT> , e = NMask . size ( ) ; i != e ; i ++ ) { if ( NMask [ i ] > <NUM_LIT> && OpMask [ NMask [ i ] ] > <NUM_LIT> && OpMask [ NMask [ i ] ] != i ) return SDValue ( ) ; } return DAG . getNode ( Op . getOpcode ( ) , SDLoc ( Op ) , Op . getValueType ( ) , Op0 -> getOperand ( <NUM_LIT> ) , Op1 -> getOperand ( <NUM_LIT> ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : return SDValue ( ) ; } ShuffleVectorSDNode * Op0 = dyn_cast < ShuffleVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; ShuffleVectorSDNode * Op1 = dyn_cast < ShuffleVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! Op0 || ! Op1 || ! Op0 -> getOperand ( <NUM_LIT> ) . isUndef ( ) || ! Op1 -> getOperand ( <NUM_LIT> ) . isUndef ( ) || Op0 -> getMask ( ) != Op1 -> getMask ( ) || Op0 -> getOperand ( <NUM_LIT> ) . getValueType ( ) != VT ) return SDValue ( ) ; ArrayRef < int > NMask = N -> getMask ( ) ; ArrayRef < int > OpMask = Op0 -> getMask ( ) ;

for ( int i = <NUM_LIT> , e = NMask . size ( ) ; i != e ; i ++ ) {


<s> if ( NextVA . isMemLoc ( ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( <NUM_LIT> , NextVA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Root , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ; } else { Reg = MF . addLiveIn ( NextVA . getLocReg ( ) , RC ) ; ArgValue2 = DAG . getCopyFromReg ( Root , dl , Reg , <STR_LIT> ) ;


<s> if ( ( Subtarget -> hasMVEIntegerOps ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasMVEFloatOps ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) ) return <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) ) ;

return VT . changeVectorElementTypeToInteger ( ) ;


<s> if ( ! VT . isVector ( ) ) return getPointerTy ( DL ) ; if ( ( Subtarget -> hasMVEIntegerOps ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasMVEFloatOps ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) ) return <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) ) ; return VT . changeVectorElementTypeToInteger ( ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default :


<s> bool <ISA_LIT>TargetLowering :: IsEligibleForTailCallOptimization ( SDValue Callee , CallingConv :: ID CalleeCC , bool isVarArg , bool isCalleeStructRet , bool isCallerStructRet , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SmallVectorImpl < <STR_LIT> > & Ins , SelectionDAG & DAG , const bool isIndirect ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function & CallerF = MF . getFunction ( ) ; CallingConv :: ID CallerCC = CallerF . getCallingConv ( ) ; assert ( Subtarget -> supportsTailCall ( ) ) ; if ( Outs . size ( ) >= <NUM_LIT> && ( ! isa < GlobalAddressSDNode > ( Callee . getNode ( ) ) || isIndirect ) ) { if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> shouldSignReturnAddress ( true ) ) return false ; } if ( CallerF . hasFnAttribute ( <STR_LIT> ) ) return false ; if ( canGuaranteeTCO ( CalleeCC , getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) ) return CalleeCC == CallerCC ; if ( isCalleeStructRet || isCallerStructRet ) return false ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } LLVMContext & C = * DAG . getContext ( ) ;

if ( ! CCState :: resultsCompatible ( getEffectiveCallingConv ( CalleeCC , isVarArg ) , getEffectiveCallingConv ( CallerCC , CallerF . isVarArg ( ) ) , MF , C , Ins , CCAssignFnForReturn ( CalleeCC , isVarArg ) , CCAssignFnForReturn ( CallerCC , CallerF . isVarArg ( ) ) ) ) return false ;