<s> unsigned <ISA_LIT>BaseInstrInfo :: GetInstSizeInBytes ( const MachineInstr * MI ) const { const MachineBasicBlock & MBB = * MI -> getParent ( ) ; const MachineFunction * MF = MBB . getParent ( ) ; const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . getSize ( ) ) return MCID . getSize ( ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) return getInlineAsmLength ( MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MAI ) ; if ( MI -> isLabel ( ) ) return <NUM_LIT> ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: PROLOG_LABEL : case TargetOpcode :: EH_LABEL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: BUNDLE : return getInstBundleLength ( MI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned EntrySize = ( Opc == <STR_LIT> ) ? <NUM_LIT> : ( ( Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned NumOps = MCID . getNumOperands ( ) ; MachineOperand JTOP = MI -> getOperand ( NumOps - ( MI -> isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOP . getIndex ( ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ;


<s> const MachineFunction * MF = MBB . getParent ( ) ; const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . getSize ( ) ) return MCID . getSize ( ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) return getInlineAsmLength ( MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MAI ) ; if ( MI -> isLabel ( ) ) return <NUM_LIT> ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: PROLOG_LABEL : case TargetOpcode :: EH_LABEL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: BUNDLE : return getInstBundleLength ( MI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> :


<s> <STR_LIT> getPredicate ( const MachineInstr * MI ) const { int PIdx = MI -> findFirstPredOperandIdx ( ) ;

return PIdx != - <NUM_LIT> ? ( <STR_LIT> ) MI -> getOperand ( PIdx ) . getImm ( ) : <STR_LIT> ;


<s> <STR_LIT> getPredicate ( const MachineInstr * MI ) const { int PIdx = MI -> findFirstPredOperandIdx ( ) ; return PIdx != - <NUM_LIT> ? ( <STR_LIT> ) MI -> getOperand ( PIdx ) . getImm ( ) : <STR_LIT> ;


<s> static inline bool isCondBranchOpcode ( int Opc ) { return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> bool isFpMLxInstruction ( unsigned Opcode ) const { return MLxEntryMap . count ( Opcode ) ;


<s> return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> static inline bool isPopOpcode ( int Opc ) { return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> if ( ( MI -> getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) { <ISA_LIT>FunctionInfo * AFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; return AFI -> isThumb2Function ( ) ; }


<s> <ISA_LIT>FunctionInfo * AFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; return AFI -> isThumb2Function ( ) ; } return true ;


<s> bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , BranchProbability Probability ) const override { return NumCycles == <NUM_LIT> ;


<s> return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> while ( ++ I != MBB -> end ( ) && I -> isDebugValue ( ) ) ; if ( I != MBB -> end ( ) && I -> getOpcode ( ) == <STR_LIT> ) return true ; if ( ! MI -> isCall ( ) && MI -> definesRegister ( <STR_LIT> ) ) return true ; return false ;


<s> if ( SrcReg == MI -> getOperand ( CommonUse ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ) return true ; break ; case <STR_LIT> : { const MachineInstr & Copy = * MI ; MachineBasicBlock :: iterator AND ( llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) ) ; if ( AND == MI -> getParent ( ) -> end ( ) ) return false ; MI = AND ;

return isSuitableForMask ( MI , Copy . getOperand ( <NUM_LIT> ) . getReg ( ) , CmpMask , true ) ;


<s> static inline bool isUncondBranchOpcode ( int Opc ) { return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . addOperand ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( <STR_LIT> ( <STR_LIT> ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMI -> hasOptionalDef ( ) ) AddDefaultCC ( NewMI ) ; MachineOperand FalseReg = MI -> getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ;


<s> const MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MachineInstr * DefMI = canFoldIntoMOVCC ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; bool Invert = ! DefMI ; if ( ! DefMI ) DefMI = canFoldIntoMOVCC ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; if ( ! DefMI ) return <NUM_LIT> ; MachineInstrBuilder NewMI = BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , DefMI -> getDesc ( ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . addOperand ( DefMI -> getOperand ( i ) ) ;

unsigned CondCode = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> const MachineOperand & MO1 = MI1 -> getOperand ( <NUM_LIT> ) ; if ( MO0 . getOffset ( ) != MO1 . getOffset ( ) ) return false ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return MO0 . getGlobal ( ) == MO1 . getGlobal ( ) ; const MachineFunction * MF = MI0 -> getParent ( ) -> getParent ( ) ; const MachineConstantPool * MCP = MF -> getConstantPool ( ) ; int CPI0 = MO0 . getIndex ( ) ; int CPI1 = MO1 . getIndex ( ) ; const MachineConstantPoolEntry & MCPE0 = MCP -> getConstants ( ) [ CPI0 ] ; const MachineConstantPoolEntry & MCPE1 = MCP -> getConstants ( ) [ CPI1 ] ; bool is<ISA_LIT>CP0 = MCPE0 . isMachineConstantPoolEntry ( ) ; bool is<ISA_LIT>CP1 = MCPE1 . isMachineConstantPoolEntry ( ) ; if ( is<ISA_LIT>CP0 && is<ISA_LIT>CP1 ) { <ISA_LIT>ConstantPoolValue * ACPV0 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE0 . Val . MachineCPVal ) ; <ISA_LIT>ConstantPoolValue * ACPV1 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE1 . Val . MachineCPVal ) ; return ACPV0 -> hasSameValue ( ACPV1 ) ; } else if ( ! is<ISA_LIT>CP0 && ! is<ISA_LIT>CP1 ) { return MCPE0 . Val . ConstVal == MCPE1 . Val . ConstVal ; } return false ; } else if ( Opcode == <STR_LIT> ) { if ( MI1 -> getOpcode ( ) != Opcode ) return false ; if ( MI0 -> getNumOperands ( ) != MI1 -> getNumOperands ( ) ) return false ; unsigned Addr0 = MI0 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Addr1 = MI1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Addr0 != Addr1 ) { if ( ! MRI || ! TargetRegisterInfo :: isVirtualRegister ( Addr0 ) || ! TargetRegisterInfo :: isVirtualRegister ( Addr1 ) ) return false ; MachineInstr * Def0 = MRI -> getVRegDef ( Addr0 ) ; MachineInstr * Def1 = MRI -> getVRegDef ( Addr1 ) ; if ( ! produceSameValue ( Def0 , Def1 , MRI ) ) return false ; } for ( unsigned i = <NUM_LIT> , e = MI0 -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO0 = MI0 -> getOperand ( i ) ; const MachineOperand & MO1 = MI1 -> getOperand ( i ) ; if ( ! MO0 . isIdenticalTo ( MO1 ) ) return false ; } return true ; } return MI0 -> isIdenticalTo ( MI1 , MachineInstr :: IgnoreVRegDefs ) ;


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return MO0 . getGlobal ( ) == MO1 . getGlobal ( ) ; const MachineFunction * MF = MI0 -> getParent ( ) -> getParent ( ) ; const MachineConstantPool * MCP = MF -> getConstantPool ( ) ; int CPI0 = MO0 . getIndex ( ) ; int CPI1 = MO1 . getIndex ( ) ; const MachineConstantPoolEntry & MCPE0 = MCP -> getConstants ( ) [ CPI0 ] ; const MachineConstantPoolEntry & MCPE1 = MCP -> getConstants ( ) [ CPI1 ] ; bool is<ISA_LIT>CP0 = MCPE0 . isMachineConstantPoolEntry ( ) ; bool is<ISA_LIT>CP1 = MCPE1 . isMachineConstantPoolEntry ( ) ; if ( is<ISA_LIT>CP0 && is<ISA_LIT>CP1 ) { <ISA_LIT>ConstantPoolValue * ACPV0 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE0 . Val . MachineCPVal ) ; <ISA_LIT>ConstantPoolValue * ACPV1 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE1 . Val . MachineCPVal ) ; return ACPV0 -> hasSameValue ( ACPV1 ) ; } else if ( ! is<ISA_LIT>CP0 && ! is<ISA_LIT>CP1 ) { return MCPE0 . Val . ConstVal == MCPE1 . Val . ConstVal ; } return false ; } else if ( Opcode == <STR_LIT> ) { if ( MI1 -> getOpcode ( ) != Opcode ) return false ; if ( MI0 -> getNumOperands ( ) != MI1 -> getNumOperands ( ) ) return false ; unsigned Addr0 = MI0 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Addr1 = MI1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Addr0 != Addr1 ) { if ( ! MRI || ! TargetRegisterInfo :: isVirtualRegister ( Addr0 ) || ! TargetRegisterInfo :: isVirtualRegister ( Addr1 ) ) return false ; MachineInstr * Def0 = MRI -> getVRegDef ( Addr0 ) ; MachineInstr * Def1 = MRI -> getVRegDef ( Addr1 ) ; if ( ! produceSameValue ( Def0 , Def1 , MRI ) ) return false ; } for ( unsigned i = <NUM_LIT> , e = MI0 -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO0 = MI0 -> getOperand ( i ) ; const MachineOperand & MO1 = MI1 -> getOperand ( i ) ; if ( ! MO0 . isIdenticalTo ( MO1 ) ) return false ; }


<s> if ( Load1 -> getMachineOpcode ( ) != Load2 -> getMachineOpcode ( ) ) return false ; if ( NumLoads >= <NUM_LIT> ) return false ; return true ;


<s> bool <ISA_LIT>BaseInstrInfo :: shouldScheduleLoadsNear ( SDNode * Load1 , SDNode * Load2 , int64_t Offset1 , int64_t Offset2 , unsigned NumLoads ) const { if ( Subtarget . isThumb1Only ( ) ) return false ; assert ( Offset2 > Offset1 ) ; if ( ( Offset2 - Offset1 ) / <NUM_LIT> > <NUM_LIT> ) return false ; if ( Load1 -> getMachineOpcode ( ) != Load2 -> getMachineOpcode ( ) ) return false ; if ( NumLoads >= <NUM_LIT> ) return false ; return true ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned ShAmt = DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ShAmt == <NUM_LIT> || ShAmt == <NUM_LIT> ) -- Adjust ; break ; } } } else if ( Subtarget . isSwift ( ) ) { switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned ShOpVal = DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; bool isSub = <STR_LIT> ( ShOpVal ) == <STR_LIT> ; unsigned ShImm = <STR_LIT> ( ShOpVal ) ; if ( ! isSub && ( ShImm == <NUM_LIT> || ( ( ShImm == <NUM_LIT> || ShImm == <NUM_LIT> || ShImm == <NUM_LIT> ) && <STR_LIT> ( ShOpVal ) == <STR_LIT> ) ) ) Adjust -= <NUM_LIT> ; else if ( ! isSub && ShImm == <NUM_LIT> && <STR_LIT> ( ShOpVal ) == <STR_LIT> ) -- Adjust ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned ShAmt = DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ShAmt == <NUM_LIT> || ShAmt == <NUM_LIT> || ShAmt == <NUM_LIT> || ShAmt == <NUM_LIT> ) Adjust -= <NUM_LIT> ; break ; } } } if ( DefAlign < <NUM_LIT> && Subtarget . checkVLDnAccessAlignment ( ) ) { switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> } if ( isIndirectBranchOpcode ( I -> getOpcode ( ) ) || isJumpTableBranchOpcode ( I -> getOpcode ( ) ) ) { CantAnalyze = true ; } else if ( isUncondBranchOpcode ( I -> getOpcode ( ) ) ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; } else if ( isCondBranchOpcode ( I -> getOpcode ( ) ) ) { if ( ! Cond . empty ( ) ) return true ; assert ( ! FBB && <STR_LIT> ) ; FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; } else if ( I -> isReturn ( ) ) { CantAnalyze = ! isPredicated ( * I ) ; } else { return true ; } if ( ! isPredicated ( * I ) && ( isUncondBranchOpcode ( I -> getOpcode ( ) ) || isIndirectBranchOpcode ( I -> getOpcode ( ) ) || isJumpTableBranchOpcode ( I -> getOpcode ( ) ) || I -> isReturn ( ) ) ) { Cond . clear ( ) ; FBB = nullptr ; if ( AllowModify ) { MachineBasicBlock :: iterator DI = std :: next ( I ) ; while ( DI != MBB . end ( ) ) { MachineInstr & InstToDelete = * DI ; ++ DI ; InstToDelete . eraseFromParent ( ) ; } } } if ( CantAnalyze ) return true ; if ( I == MBB . begin ( ) ) return false ; -- I ;


<s> bool CantAnalyze = false ; while ( I -> isDebugValue ( ) || ! I -> isTerminator ( ) ) { if ( I == MBB . begin ( ) ) return false ; -- I ; } if ( isIndirectBranchOpcode ( I -> getOpcode ( ) ) || isJumpTableBranchOpcode ( I -> getOpcode ( ) ) ) { CantAnalyze = true ; } else if ( isUncondBranchOpcode ( I -> getOpcode ( ) ) ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; } else if ( isCondBranchOpcode ( I -> getOpcode ( ) ) ) { if ( ! Cond . empty ( ) ) return true ;


<s> SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = ~ <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ;

CmpMask = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> assert ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; TrueOp = <NUM_LIT> ;


<s> TrueOp = <NUM_LIT> ; FalseOp = <NUM_LIT> ; Cond . push_back ( MI . getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( MI . getOperand ( <NUM_LIT> ) ) ; Optimizable = true ;


<s> <ISA_LIT>BaseInstrInfo :: <ISA_LIT>BaseInstrInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , Subtarget ( STI ) { for ( unsigned i = <NUM_LIT> , e = array_lengthof ( <ISA_LIT>_MLxTable ) ; i != e ; ++ i ) { if ( ! MLxEntryMap . insert ( std :: make_pair ( <ISA_LIT>_MLxTable [ i ] . MLxOpc , i ) ) . second ) llvm_unreachable ( <STR_LIT> ) ; MLxHazardOpcodes . insert ( <ISA_LIT>_MLxTable [ i ] . AddSubOpc ) ; MLxHazardOpcodes . insert ( <ISA_LIT>_MLxTable [ i ] . MulOpc ) ; }


<s> for ( unsigned i = <NUM_LIT> , e = array_lengthof ( <ISA_LIT>_MLxTable ) ; i != e ; ++ i ) { if ( ! MLxEntryMap . insert ( std :: make_pair ( <ISA_LIT>_MLxTable [ i ] . MLxOpc , i ) ) . second ) llvm_unreachable ( <STR_LIT> ) ; MLxHazardOpcodes . insert ( <ISA_LIT>_MLxTable [ i ] . AddSubOpc ) ; MLxHazardOpcodes . insert ( <ISA_LIT>_MLxTable [ i ] . MulOpc ) ;


<s> unsigned Reg = MO . getReg ( ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) && <STR_LIT> ) ; unsigned DReg = Reg ; if ( <STR_LIT> . contains ( Reg ) ) { DReg = <STR_LIT> + ( Reg - <STR_LIT> ) / <NUM_LIT> ;

assert ( TRI -> isSuperRegister ( Reg , DReg ) && <STR_LIT> ) ;


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) return nullptr ; if ( ! MRI . hasOneNonDBGUse ( Reg ) ) return nullptr ; MachineInstr * MI = MRI . getVRegDef ( Reg ) ; if ( ! MI ) return nullptr ; if ( ! MI -> isPredicable ( ) ) return nullptr ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) {

const MachineOperand & MO = MI -> getOperand ( i ) ;


<s> case <STR_LIT> : case <STR_LIT> : { unsigned PredReg = <NUM_LIT> ; <STR_LIT> CC = getInstrPredicate ( MI , PredReg ) ; if ( CC == <STR_LIT> || PredReg != <STR_LIT> ) return nullptr ; MachineInstr * CommutedMI = TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ; if ( ! CommutedMI ) return nullptr ; CommutedMI -> getOperand ( CommutedMI -> findFirstPredOperandIdx ( ) ) . setImm ( <STR_LIT> ( CC ) ) ; return CommutedMI ;


<s> static inline MachineOperand condCodeOp ( unsigned CCReg = <NUM_LIT> ) { return MachineOperand :: CreateReg ( CCReg , false ) ;


<s> MachineInstrBuilder MIB = BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( Opc ) , DestReg ) ; if ( Subtarget . isMClass ( ) ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ;

MIB . addReg ( <STR_LIT> , RegState :: Implicit | getKillRegState ( KillSrc ) ) ;


<s> MachineInstrBuilder MIB = BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( Opc ) , DestReg ) ;

if ( Subtarget . isMClass ( ) ) MIB . addImm ( <NUM_LIT> ) ;


<s> SubRegs = <NUM_LIT> ; Spacing = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) && Subtarget . isFPOnlySP ( ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( SrcReg == <STR_LIT> ) { copyFromCPSR ( MBB , I , DestReg , KillSrc , Subtarget ) ; return ; } else if ( DestReg == <STR_LIT> ) { copyToCPSR ( MBB , I , SrcReg , KillSrc , Subtarget ) ; return ; } assert ( Opc && <STR_LIT> ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; MachineInstrBuilder Mov ; if ( TRI -> regsOverlap ( SrcReg , TRI -> getSubReg ( DestReg , BeginIdx ) ) ) { BeginIdx = BeginIdx + ( ( SubRegs - <NUM_LIT> ) * Spacing ) ; Spacing = - Spacing ; } SmallSet < unsigned , <NUM_LIT> > DstRegs ; for ( unsigned i = <NUM_LIT> ; i != SubRegs ; ++ i ) { unsigned Dst = TRI -> getSubReg ( DestReg , BeginIdx + i * Spacing ) ; unsigned Src = TRI -> getSubReg ( SrcReg , BeginIdx + i * Spacing ) ; assert ( Dst && Src && <STR_LIT> ) ; assert ( ! DstRegs . count ( Src ) && <STR_LIT> ) ; DstRegs . insert ( Dst ) ; Mov = BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( Opc ) , Dst ) . addReg ( Src ) ; if ( Opc == <STR_LIT> ) Mov . addReg ( Src ) ; Mov = AddDefaultPred ( Mov ) ; if ( Opc == <STR_LIT> ) Mov = AddDefaultCC ( Mov ) ;


<s> MachineInstrBuilder MIB = BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( Opc ) ) ; if ( Subtarget . isMClass ( ) ) MIB . addImm ( <NUM_LIT> ) ;


<s> void <ISA_LIT>BaseInstrInfo :: copyToCPSR ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool KillSrc , const <ISA_LIT>Subtarget & Subtarget ) const { unsigned Opc = Subtarget . isThumb ( ) ? ( Subtarget . isMClass ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ;

MachineInstrBuilder MIB = BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( Opc ) ) ;


<s> const InstrItineraryData * II = static_cast < const <ISA_LIT>Subtarget * > ( STI ) -> getInstrItineraryData ( ) ; return new ScoreboardHazardRecognizer ( II , DAG , <STR_LIT> ) ; } return TargetInstrInfo :: CreateTargetHazardRecognizer ( STI , DAG ) ;


<s> unsigned CPI = Orig . getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; Orig . getOperand ( <NUM_LIT> ) . setIndex ( CPI ) ; Orig . getOperand ( <NUM_LIT> ) . setImm ( PCLabelId ) ;


<s> case <STR_LIT> : { unsigned CPI = Orig . getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; Orig . getOperand ( <NUM_LIT> ) . setIndex ( CPI ) ; Orig . getOperand ( <NUM_LIT> ) . setImm ( PCLabelId ) ; break ;


<s> const MachineConstantPoolEntry & MCPE = MCP -> getConstants ( ) [ CPI ] ; assert ( MCPE . isMachineConstantPoolEntry ( ) && <STR_LIT> ) ; <ISA_LIT>ConstantPoolValue * ACPV = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE . Val . MachineCPVal ) ; unsigned PCLabelId = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * NewCPV = nullptr ; if ( ACPV -> isGlobalValue ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getGV ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> , ACPV -> getModifier ( ) , ACPV -> mustAddCurrentAddress ( ) ) ; else if ( ACPV -> isExtSymbol ( ) ) NewCPV = <ISA_LIT>ConstantPoolSymbol ::

Create ( MF . getFunction ( ) -> getContext ( ) , cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) , PCLabelId , <NUM_LIT> ) ;


<s> unsigned PCLabelId = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * NewCPV = nullptr ; if ( ACPV -> isGlobalValue ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getGV ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> , ACPV -> getModifier ( ) , ACPV -> mustAddCurrentAddress ( ) ) ; else if ( ACPV -> isExtSymbol ( ) ) NewCPV = <ISA_LIT>ConstantPoolSymbol :: Create ( MF . getFunction ( ) -> getContext ( ) , cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) , PCLabelId , <NUM_LIT> ) ; else if ( ACPV -> isBlockAddress ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getBlockAddress ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isLSDA ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isMachineBasicBlock ( ) ) NewCPV = <ISA_LIT>ConstantPoolMBB :: Create ( MF . getFunction ( ) -> getContext ( ) , cast < <ISA_LIT>ConstantPoolMBB > ( ACPV ) -> getMBB ( ) , PCLabelId , <NUM_LIT> ) ;


<s> NumBytes &= ~ ThisVal ; assert ( <STR_LIT> ( ThisVal ) != - <NUM_LIT> && <STR_LIT> ) ; unsigned Opc = isSub ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ThisVal ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; BaseReg = DestReg ; }


<s> if ( Subtarget . isGVIndirectSymbol ( GV ) ) { MIB = BuildMI ( MBB , MI , DL , get ( LoadOpc ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; unsigned Flag = MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( * MBB . getParent ( ) ) , Flag , <NUM_LIT> , <NUM_LIT> ) ; MIB . addMemOperand ( MMO ) ; AddDefaultPred ( MIB ) ;


<s> bool isThumb2 = Subtarget . isThumb2 ( ) ; const <ISA_LIT>BaseInstrInfo * TII = Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineBasicBlock * BB = MI -> getParent ( ) ; MachineInstrBuilder LDM , STM ; if ( isThumb1 || ! MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) { LDM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; } else { LDM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) ; } if ( isThumb1 || ! MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) { STM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; } else { STM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) ;


<s> MI . getParent ( ) -> erase ( MI ) ; return true ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { expandMEMCPY ( MI ) ; return true ; } if ( ! MI . isCopy ( ) || Subtarget . dontWidenVMOVS ( ) || Subtarget . isFPOnlySP ( ) ) return false ; unsigned DstRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ;

if ( ! DstRegD || ! SrcRegD ) return false ;


<s> } const MCInstrDesc & UseMCID = UseMI . getDesc ( ) ; if ( UseMCID . hasOptionalDef ( ) ) { unsigned NumOps = UseMCID . getNumOperands ( ) ; if ( UseMI . getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; } unsigned UseOpc = UseMI . getOpcode ( ) ; unsigned NewUseOpc = <NUM_LIT> ; uint32_t ImmVal = ( uint32_t ) DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; uint32_t SOImmValV1 = <NUM_LIT> , SOImmValV2 = <NUM_LIT> ; bool Commute = false ; switch ( UseOpc ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Commute = UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) != Reg ; switch ( UseOpc ) { default : break ; case <STR_LIT> : case <STR_LIT> : { if ( UseOpc == <STR_LIT> && Commute ) return false ; if ( <STR_LIT> ( ImmVal ) ) NewUseOpc = UseOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> ( - ImmVal ) ) { ImmVal = - ImmVal ; NewUseOpc = UseOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; break ; } case <STR_LIT> : case <STR_LIT> : { if ( ! <STR_LIT> ( ImmVal ) ) return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; switch ( UseOpc ) { default : break ;

case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ;


<s> if ( ! DefMI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; if ( ! MRI -> hasOneNonDBGUse ( Reg ) ) return false ; const MCInstrDesc & DefMCID = DefMI . getDesc ( ) ; if ( DefMCID . hasOptionalDef ( ) ) { unsigned NumOps = DefMCID . getNumOperands ( ) ; const MachineOperand & MO = DefMI . getOperand ( NumOps - <NUM_LIT> ) ; if ( MO . getReg ( ) == <STR_LIT> && ! MO . isDead ( ) ) return false ; } const MCInstrDesc & UseMCID = UseMI . getDesc ( ) ; if ( UseMCID . hasOptionalDef ( ) ) { unsigned NumOps = UseMCID . getNumOperands ( ) ; if ( UseMI . getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; } unsigned UseOpc = UseMI . getOpcode ( ) ; unsigned NewUseOpc = <NUM_LIT> ; uint32_t ImmVal = ( uint32_t ) DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; uint32_t SOImmValV1 = <NUM_LIT> , SOImmValV2 = <NUM_LIT> ; bool Commute = false ; switch ( UseOpc ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Commute = UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) != Reg ; switch ( UseOpc ) { default : break ; case <STR_LIT> : case <STR_LIT> : { if ( UseOpc == <STR_LIT> && Commute ) return false ;

if ( <STR_LIT> ( ImmVal ) ) NewUseOpc = UseOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ;


<s> int Scale = <NUM_LIT> ; unsigned ImmOp ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : ImmOp = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : ImmOp = <NUM_LIT> ;


<s> inline int getAddSubImmediate ( MachineInstr & MI ) { int Scale = <NUM_LIT> ; unsigned ImmOp ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : ImmOp = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : ImmOp = <NUM_LIT> ; Scale = - <NUM_LIT> ; break ;


<s> MachineBasicBlock :: const_instr_iterator II = ++ MI . getIterator ( ) ; assert ( II -> isInsideBundle ( ) && <STR_LIT> ) ; MachineBasicBlock :: const_instr_iterator E = MI . getParent ( ) -> instr_end ( ) ; int Idx = - <NUM_LIT> ; while ( II != E && II -> isInsideBundle ( ) ) { Idx = II -> findRegisterUseOperandIdx ( Reg , false , TRI ) ; if ( Idx != - <NUM_LIT> ) break ; if ( II -> getOpcode ( ) != <STR_LIT> ) ++ Dist ; ++ II ; } if ( Idx == - <NUM_LIT> ) { Dist = <NUM_LIT> ; return nullptr ; } UseIdx = Idx ;


<s> unsigned Domain = MI . getDesc ( ) . TSFlags & <STR_LIT> ; if ( Domain & <STR_LIT> ) return std :: make_pair ( ExeNEON , <NUM_LIT> ) ; if ( ( Domain & <STR_LIT> ) && Subtarget . isCortexA8 ( ) ) return std :: make_pair ( ExeNEON , <NUM_LIT> ) ; if ( Domain & <STR_LIT> ) return std :: make_pair ( ExeVFP , <NUM_LIT> ) ; return std :: make_pair ( ExeGeneric , <NUM_LIT> ) ;


<s> bool <ISA_LIT>BaseInstrInfo :: getExtractSubregLikeInputs ( const MachineInstr & MI , unsigned DefIdx , RegSubRegPairAndIdx & InputReg ) const { assert ( DefIdx < MI . getDesc ( ) . getNumDefs ( ) && <STR_LIT> ) ; assert ( MI . isExtractSubregLike ( ) && <STR_LIT> ) ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : const MachineOperand & MOReg = MI . getOperand ( <NUM_LIT> ) ; InputReg . Reg = MOReg . getReg ( ) ; InputReg . SubReg = MOReg . getSubReg ( ) ; InputReg . SubIdx = DefIdx == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; return true ;


<s> unsigned getFramePred ( const MachineInstr & MI ) const {


<s> MachineBasicBlock :: LivenessQueryResult LQR = MI . getParent ( ) -> computeRegisterLiveness ( TRI , ImplicitSReg , MI ) ; if ( LQR == MachineBasicBlock :: LQR_Live ) return true ; else if ( LQR == MachineBasicBlock :: LQR_Unknown ) return false ; ImplicitSReg = <NUM_LIT> ;


<s> const MachineOperand & MOInsertedReg = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & MOIndex = MI . getOperand ( <NUM_LIT> ) ; BaseReg . Reg = MOBaseReg . getReg ( ) ; BaseReg . SubReg = MOBaseReg . getSubReg ( ) ; InsertedReg . Reg = MOInsertedReg . getReg ( ) ; InsertedReg . SubReg = MOInsertedReg . getSubReg ( ) ; InsertedReg . SubIdx = MOIndex . getImm ( ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; return true ; } llvm_unreachable ( <STR_LIT> ) ;


<s> MachineBasicBlock :: const_instr_iterator I = MI . getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI . getParent ( ) -> instr_end ( ) ;

while ( ++ I != E && I -> isInsideBundle ( ) ) {


<s> if ( I -> getOpcode ( ) != <STR_LIT> ) Latency += getInstrLatency ( ItinData , * I , PredCost ) ; } return Latency ; } const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( PredCost && ( MCID . isCall ( ) || MCID . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) ) { * PredCost = <NUM_LIT> ; } if ( ! ItinData ) return MI . mayLoad ( ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Class = MCID . getSchedClass ( ) ; if ( ! ItinData -> isEmpty ( ) && ItinData -> getNumMicroOps ( Class ) < <NUM_LIT> ) return getNumMicroOps ( ItinData , MI ) ; unsigned Latency = ItinData -> getStageLatency ( Class ) ; unsigned DefAlign = MI . hasOneMemOperand ( ) ? ( * MI . memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; int Adj = adjustDefLatency ( Subtarget , MI , MCID , DefAlign ) ; if ( Adj >= <NUM_LIT> || ( int ) Latency > - Adj ) {


<s> if ( PIdx == - <NUM_LIT> ) { PredReg = <NUM_LIT> ; return <STR_LIT> ; }

PredReg = MI . getOperand ( PIdx + <NUM_LIT> ) . getReg ( ) ;


<s> const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( MCID . getSize ( ) ) return MCID . getSize ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) return getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MAI ) ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { default : return <NUM_LIT> ; case TargetOpcode :: BUNDLE : return getInstBundleLength ( MI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> :


<s> int RegNo = ( int ) ( DefIdx + <NUM_LIT> ) - DefMCID . getNumOperands ( ) + <NUM_LIT> ; if ( RegNo <= <NUM_LIT> ) return ItinData -> getOperandCycle ( DefClass , DefIdx ) ; int DefCycle ; if ( Subtarget . isCortexA8 ( ) || Subtarget . isCortexA7 ( ) ) { DefCycle = RegNo / <NUM_LIT> ; if ( DefCycle < <NUM_LIT> ) DefCycle = <NUM_LIT> ; DefCycle += <NUM_LIT> ; } else if ( Subtarget . isLikeA9 ( ) || Subtarget . isSwift ( ) ) { DefCycle = ( RegNo / <NUM_LIT> ) ; if ( ( RegNo % <NUM_LIT> ) || DefAlign < <NUM_LIT> ) ++ DefCycle ;


<s> int RegNo = ( int ) ( DefIdx + <NUM_LIT> ) - DefMCID . getNumOperands ( ) + <NUM_LIT> ; if ( RegNo <= <NUM_LIT> ) return ItinData -> getOperandCycle ( DefClass , DefIdx ) ; int DefCycle ; if ( Subtarget . isCortexA8 ( ) || Subtarget . isCortexA7 ( ) ) { DefCycle = RegNo / <NUM_LIT> ; if ( DefCycle < <NUM_LIT> ) DefCycle = <NUM_LIT> ; DefCycle += <NUM_LIT> ; } else if ( Subtarget . isLikeA9 ( ) || Subtarget . isSwift ( ) ) { DefCycle = ( RegNo / <NUM_LIT> ) ; if ( ( RegNo % <NUM_LIT> ) || DefAlign < <NUM_LIT> ) ++ DefCycle ; DefCycle += <NUM_LIT> ;


<s> unsigned llvm :: getMatchingCondBranchOpcode ( unsigned Opc ) { if ( Opc == <STR_LIT> ) return <STR_LIT> ; if ( Opc == <STR_LIT> ) return <STR_LIT> ; if ( Opc == <STR_LIT> ) return <STR_LIT> ;


<s> unsigned llvm :: getMatchingCondBranchOpcode ( unsigned Opc ) { if ( Opc == <STR_LIT> ) return <STR_LIT> ;


<s> I != E ; ++ I ) { Size += ( * I ) -> getSize ( ) ; } return Size / <NUM_LIT> ;


<s> for ( MachineInstr :: mmo_iterator I = MI . memoperands_begin ( ) , E = MI . memoperands_end ( ) ; I != E ; ++ I ) { Size += ( * I ) -> getSize ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ++ UOps ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : UOps += <NUM_LIT> ; break ; } return UOps ;


<s> return Latency ; } if ( DefMO . isImplicit ( ) || UseMI . getOperand ( UseIdx ) . isImplicit ( ) ) return - <NUM_LIT> ; unsigned DefAlign = DefMI . hasOneMemOperand ( ) ? ( * DefMI . memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; unsigned UseAlign = UseMI . hasOneMemOperand ( ) ? ( * UseMI . memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; int Latency = getOperandLatency ( ItinData , DefMCID , DefIdx , DefAlign , UseMCID , UseIdx , UseAlign ) ; if ( Latency < <NUM_LIT> ) return Latency ; int Adj = DefAdj + UseAdj ; Adj += adjustDefLatency ( Subtarget , DefMI , DefMCID , DefAlign ) ; if ( Adj >= <NUM_LIT> || ( int ) Latency > - Adj ) { return Latency + Adj ; } return Latency ;


<s> UseOp = MI . findRegisterUseOperandIdx ( Reg , false , TRI ) ; break ; case <STR_LIT> : UseOp = <NUM_LIT> ; break ; default : return <NUM_LIT> ; } if ( UseOp != - <NUM_LIT> && MI . getOperand ( UseOp ) . readsReg ( ) ) return <NUM_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { if ( ! MO . getSubReg ( ) || MI . readsVirtualRegister ( Reg ) ) return <NUM_LIT> ;

} else if ( <STR_LIT> . contains ( Reg ) ) {


<s> case <STR_LIT> : case <STR_LIT> : UseOp = MI . findRegisterUseOperandIdx ( Reg , false , TRI ) ; break ; case <STR_LIT> : UseOp = <NUM_LIT> ; break ; default : return <NUM_LIT> ; } if ( UseOp != - <NUM_LIT> && MI . getOperand ( UseOp ) . readsReg ( ) ) return <NUM_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { if ( ! MO . getSubReg ( ) || MI . readsVirtualRegister ( Reg ) ) return <NUM_LIT> ; } else if ( <STR_LIT> . contains ( Reg ) ) {

unsigned DReg = TRI -> getMatchingSuperReg ( Reg , <STR_LIT> , & <STR_LIT> ) ;


<s> int PIdx = MI . findFirstPredOperandIdx ( ) ; return PIdx != - <NUM_LIT> ? ( <STR_LIT> ) MI . getOperand ( PIdx ) . getImm ( ) : <STR_LIT> ;


<s> <STR_LIT> getPredicate ( const MachineInstr & MI ) const { int PIdx = MI . findFirstPredOperandIdx ( ) ; return PIdx != - <NUM_LIT> ? ( <STR_LIT> ) MI . getOperand ( PIdx ) . getImm ( ) : <STR_LIT> ;


<s> unsigned <ISA_LIT>BaseInstrInfo :: getPredicationCost ( const MachineInstr & MI ) const { if ( MI . isCopyLike ( ) || MI . isInsertSubreg ( ) || MI . isRegSequence ( ) || MI . isImplicitDef ( ) ) return <NUM_LIT> ; if ( MI . isBundle ( ) ) return <NUM_LIT> ; const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( MCID . isCall ( ) || MCID . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) { return <NUM_LIT> ;


<s> bool <ISA_LIT>BaseInstrInfo :: getRegSequenceLikeInputs ( const MachineInstr & MI , unsigned DefIdx , SmallVectorImpl < RegSubRegPairAndIdx > & InputRegs ) const { assert ( DefIdx < MI . getDesc ( ) . getNumDefs ( ) && <STR_LIT> ) ;

assert ( MI . isRegSequenceLike ( ) && <STR_LIT> ) ;


<s> int <ISA_LIT>BaseInstrInfo :: getSTMUseCycle ( const InstrItineraryData * ItinData , const MCInstrDesc & UseMCID , unsigned UseClass , unsigned UseIdx , unsigned UseAlign ) const {

int RegNo = ( int ) ( UseIdx + <NUM_LIT> ) - UseMCID . getNumOperands ( ) + <NUM_LIT> ;


<s> switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : isSLoad = true ; break ; } if ( ( isSLoad && ( RegNo % <NUM_LIT> ) ) || DefAlign < <NUM_LIT> ) ++ DefCycle ; } else { DefCycle = RegNo + <NUM_LIT> ; }


<s> if ( RegNo % <NUM_LIT> ) ++ DefCycle ; } else if ( Subtarget . isLikeA9 ( ) || Subtarget . isSwift ( ) ) { DefCycle = RegNo ; bool isSLoad = false ; switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : isSLoad = true ; break ; } if ( ( isSLoad && ( RegNo % <NUM_LIT> ) ) || DefAlign < <NUM_LIT> ) ++ DefCycle ; } else { DefCycle = RegNo + <NUM_LIT> ; } return DefCycle ;


<s> } else if ( Subtarget . isLikeA9 ( ) || Subtarget . isSwift ( ) ) { UseCycle = RegNo ; bool isSStore = false ; switch ( UseMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : isSStore = true ; break ; } if ( ( isSStore && ( RegNo % <NUM_LIT> ) ) || UseAlign < <NUM_LIT> ) ++ UseCycle ; } else {


<s> if ( Subtarget . nonpipelinedVFP ( ) && ( DDomain == <STR_LIT> || UDomain == <STR_LIT> ) ) return true ; unsigned Latency = SchedModel . computeOperandLatency ( & DefMI , DefIdx , & UseMI , UseIdx ) ; if ( Latency <= <NUM_LIT> ) return false ;

return DDomain == <STR_LIT> || DDomain == <STR_LIT> || UDomain == <STR_LIT> || UDomain == <STR_LIT> ;


<s> unsigned Latency = SchedModel . computeOperandLatency ( & DefMI , DefIdx , & UseMI , UseIdx ) ; if ( Latency <= <NUM_LIT> ) return false ;


<s> if ( DDomain == <STR_LIT> ) { unsigned DefClass = DefMI . getDesc ( ) . getSchedClass ( ) ; int DefCycle = ItinData -> getOperandCycle ( DefClass , DefIdx ) ; return ( DefCycle != - <NUM_LIT> && DefCycle <= <NUM_LIT> ) ; }


<s> unsigned DDomain = DefMI . getDesc ( ) . TSFlags & <STR_LIT> ; if ( DDomain == <STR_LIT> ) { unsigned DefClass = DefMI . getDesc ( ) . getSchedClass ( ) ; int DefCycle = ItinData -> getOperandCycle ( DefClass , DefIdx ) ; return ( DefCycle != - <NUM_LIT> && DefCycle <= <NUM_LIT> ) ;


<s> bool <ISA_LIT>BaseInstrInfo :: hasNOP ( ) const { return Subtarget . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> bool <ISA_LIT>BaseInstrInfo :: hasNOP ( ) const {

return Subtarget . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> if ( isThumb ) BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else BuildMI ( & MBB , DL , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addOperand ( Cond [ <NUM_LIT> ] ) ; return <NUM_LIT> ; } BuildMI ( & MBB , DL , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addOperand ( Cond [ <NUM_LIT> ] ) ;

if ( isThumb ) BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( FBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ;


<s> for ( const auto & MO : MI -> operands ( ) ) if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> && MO . isDef ( ) && ! MO . isDead ( ) ) return true ;


<s> switch ( MI -> getOpcode ( ) ) { default : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> unsigned IntrinsicID = IntInst -> getIntrinsicID ( ) ;

return ( IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> ) ;


<s> if ( IntInst == nullptr ) return false ; return isGather ( IntInst ) || isScatter ( IntInst ) ;


<s> return isGather ( IntInst ) || isScatter ( IntInst ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( MI . isCall ( MachineInstr :: IgnoreBundle ) ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> int opc = MI . getOpcode ( ) ; return MI . isReturn ( ) || isIndirectBranchOpcode ( MI . getOpcode ( ) ) || isJumpTableBranchOpcode ( opc ) ;


<s> static inline bool isIndirectControlFlowNotComingBack ( const MachineInstr & MI ) { int opc = MI . getOpcode ( ) ; return MI . isReturn ( ) || isIndirectBranchOpcode ( MI . getOpcode ( ) ) || isJumpTableBranchOpcode ( opc ) ;


<s> case <STR_LIT> : return std :: abs ( Imm ) < ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) ; case <STR_LIT> : return std :: abs ( Imm ) < ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) && Imm % <NUM_LIT> == <NUM_LIT> ; case <STR_LIT> : return std :: abs ( Imm ) < ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) && Imm % <NUM_LIT> == <NUM_LIT> ; case <STR_LIT> : return std :: abs ( Imm ) < ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) ; case <STR_LIT> : return Imm >= <NUM_LIT> && Imm < ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) ; case <STR_LIT> :

return Imm < <NUM_LIT> && - Imm < ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) ;


<s> return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ;


return MI . mayLoad ( ) && hasLoadFromStackSlot ( MI , Dummy , FrameIndex ) ;


<s> return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> if ( ! isEligibleForITBlock ( & MI ) ) return false ; <ISA_LIT>FunctionInfo * AFI = MI . getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> isThumb2Function ( ) ) { if ( getSubtarget ( ) . restrictIT ( ) ) return isV8EligibleForIT ( & MI ) ; } else { if ( ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) return false ;


<s> while ( ++ I != E && I -> isInsideBundle ( ) ) { int PIdx = I -> findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> && I -> getOperand ( PIdx ) . getImm ( ) != <STR_LIT> ) return true ; } return false ; } int PIdx = MI . findFirstPredOperandIdx ( ) ; return PIdx != - <NUM_LIT> && MI . getOperand ( PIdx ) . getImm ( ) != <STR_LIT> ;


<s> unsigned TUnpredCost = Probability . scale ( TCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FCycles * ScalingUpFactor ) ; unsigned UnpredCost = TUnpredCost + FUnpredCost ;

UnpredCost += <NUM_LIT> * ScalingUpFactor ;


<s> return Subtarget . isProfitableToUnpredicate ( ) ;


<s> inline bool isScatter ( IntrinsicInst * IntInst ) { if ( IntInst == nullptr ) return false ; unsigned IntrinsicID = IntInst -> getIntrinsicID ( ) ;


<s> if ( MI . isDebugValue ( ) ) return false ; if ( MI . isTerminator ( ) || MI . isPosition ( ) ) return true ; MachineBasicBlock :: const_iterator I = MI ; while ( ++ I != MBB -> end ( ) && I -> isDebugValue ( ) ) ; if ( I != MBB -> end ( ) && I -> getOpcode ( ) == <STR_LIT> ) return true ; if ( ! MI . isCall ( ) && MI . definesRegister ( <STR_LIT> ) ) return true ;


<s> return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> :


<s> return MI . mayStore ( ) && hasStoreToStackSlot ( MI , Dummy , FrameIndex ) ;


return MI . mayStore ( ) && hasStoreToStackSlot ( MI , Dummy , FrameIndex ) ;


<s> return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : if ( CmpMask != MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) return false ; if ( SrcReg == MI -> getOperand ( CommonUse ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ) return true ; break ; } return false ;


<s> bool isUnspillableTerminatorImpl ( const MachineInstr * MI ) const override {

return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ;


<s> if ( featureBits [ <STR_LIT> ] && ( Num & <NUM_LIT> ) != <NUM_LIT> ) return false ;

if ( featureBits [ <STR_LIT> ] && ( ( Num & <NUM_LIT> ) == <NUM_LIT> || ( Num & <NUM_LIT> ) == <NUM_LIT> ) ) return false ;


<s> static inline bool isValidCoprocessorNumber ( unsigned Num , const FeatureBitset & featureBits ) {

if ( featureBits [ <STR_LIT> ] && ( Num & <NUM_LIT> ) != <NUM_LIT> ) return false ;


<s> static inline bool isVPTOpcode ( int Opc ) { return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> static inline bool isVPTOpcode ( int Opc ) {

return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SmallVector < std :: pair < MachineOperand * , <STR_LIT> > , <NUM_LIT> > OperandsToUpdate ; bool isSafe = false ; I = CmpInstr ; E = CmpInstr . getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } <STR_LIT> CC ; bool IsInstrVSel = true ; switch ( Instr . getOpcode ( ) ) { default : IsInstrVSel = false ; CC = ( <STR_LIT> ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; } if ( Sub ) { <STR_LIT> NewCC = getSwappedCondition ( CC ) ; if ( NewCC == <STR_LIT> ) return false ; if ( SrcReg2 != <NUM_LIT> && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) { if ( IsInstrVSel ) return false ; OperandsToUpdate . push_back ( std :: make_pair ( & ( ( * I ) . getOperand ( IO - <NUM_LIT> ) ) , NewCC ) ) ; } } else { switch ( CC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( ! DefMI ) DefMI = canFoldIntoMOVCC ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; if ( ! DefMI ) return nullptr ; MachineOperand FalseReg = MI . getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * PreviousClass = MRI . getRegClass ( FalseReg . getReg ( ) ) ; if ( ! MRI . constrainRegClass ( DestReg , PreviousClass ) ) return nullptr ; MachineInstrBuilder NewMI = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . addOperand ( DefMI -> getOperand ( i ) ) ;

unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MachineInstr * DefMI = canFoldIntoMOVCC ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; bool Invert = ! DefMI ; if ( ! DefMI ) DefMI = canFoldIntoMOVCC ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; if ( ! DefMI ) return nullptr ; MachineOperand FalseReg = MI . getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * PreviousClass = MRI . getRegClass ( FalseReg . getReg ( ) ) ; if ( ! MRI . constrainRegClass ( DestReg , PreviousClass ) ) return nullptr ; MachineInstrBuilder NewMI = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . addOperand ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( <STR_LIT> ( <STR_LIT> ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; if ( NewMI -> hasOptionalDef ( ) ) AddDefaultCC ( NewMI ) ; FalseReg . setImplicit ( ) ;


<s> if ( isUncondBranchOpcode ( Opc ) ) { MI . setDesc ( get ( getMatchingCondBranchOpcode ( Opc ) ) ) ;

MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ;


<s> static inline std :: array < MachineOperand , <NUM_LIT> > predOps ( <STR_LIT> Pred , unsigned PredReg = <NUM_LIT> ) {

return { { MachineOperand :: CreateImm ( static_cast < int64_t > ( Pred ) ) , MachineOperand :: CreateReg ( PredReg , false ) } } ;


<s> <ISA_LIT>ConstantPoolValue * ACPV0 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE0 . Val . MachineCPVal ) ; <ISA_LIT>ConstantPoolValue * ACPV1 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE1 . Val . MachineCPVal ) ; return ACPV0 -> hasSameValue ( ACPV1 ) ; } else if ( ! is<ISA_LIT>CP0 && ! is<ISA_LIT>CP1 ) { return MCPE0 . Val . ConstVal == MCPE1 . Val . ConstVal ; } return false ; } else if ( Opcode == <STR_LIT> ) { if ( MI1 . getOpcode ( ) != Opcode ) return false ; if ( MI0 . getNumOperands ( ) != MI1 . getNumOperands ( ) ) return false ; unsigned Addr0 = MI0 . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Addr1 = MI1 . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Addr0 != Addr1 ) { if ( ! MRI || ! TargetRegisterInfo :: isVirtualRegister ( Addr0 ) || ! TargetRegisterInfo :: isVirtualRegister ( Addr1 ) ) return false ; MachineInstr * Def0 = MRI -> getVRegDef ( Addr0 ) ; MachineInstr * Def1 = MRI -> getVRegDef ( Addr1 ) ; if ( ! produceSameValue ( * Def0 , * Def1 , MRI ) ) return false ; } for ( unsigned i = <NUM_LIT> , e = MI0 . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO0 = MI0 . getOperand ( i ) ; const MachineOperand & MO1 = MI1 . getOperand ( i ) ; if ( ! MO0 . isIdenticalTo ( MO1 ) ) return false ; }


<s> break ; } case <STR_LIT> : case <STR_LIT> : { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CPI = Orig . getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , Orig . getDebugLoc ( ) , get ( Opcode ) , DestReg ) . addConstantPoolIndex ( CPI ) . addImm ( PCLabelId ) ; MIB -> setMemRefs ( Orig . memoperands_begin ( ) , Orig . memoperands_end ( ) ) ;


<s> if ( I == MBB . end ( ) ) return <NUM_LIT> ; if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ;


<s> MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return <NUM_LIT> ; if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ;


<s> MIB . addReg ( DstReg , RegState :: Define | RegState :: Implicit ) ; if ( ImplicitSReg != <NUM_LIT> ) MIB . addReg ( ImplicitSReg , RegState :: Implicit ) ; break ; } case <STR_LIT> : { if ( Domain != ExeNEON ) break ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstLane = <NUM_LIT> , SrcLane = <NUM_LIT> , DDst , DSrc ; DDst = getCorrespondingDRegAndLane ( TRI , DstReg , DstLane ) ; DSrc = getCorrespondingDRegAndLane ( TRI , SrcReg , SrcLane ) ; unsigned ImplicitSReg ; if ( ! getImplicitSPRUseForDPRUse ( TRI , MI , DSrc , SrcLane , ImplicitSReg ) ) break ; for ( unsigned i = MI . getDesc ( ) . getNumOperands ( ) ; i ; -- i ) MI . RemoveOperand ( i - <NUM_LIT> ) ; if ( DSrc == DDst ) { MI . setDesc ( get ( <STR_LIT> ) ) ; MIB . addReg ( DDst , RegState :: Define ) . addReg ( DDst , getUndefRegState ( ! MI . readsRegister ( DDst , TRI ) ) ) . addImm ( SrcLane ) ; AddDefaultPred ( MIB ) ; MIB . addReg ( DstReg , RegState :: Implicit | RegState :: Define ) ; MIB . addReg ( SrcReg , RegState :: Implicit ) ; if ( ImplicitSReg != <NUM_LIT> ) MIB . addReg ( ImplicitSReg , RegState :: Implicit ) ; break ; } MachineInstrBuilder NewMIB ; NewMIB = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) , DDst ) ; unsigned CurReg = SrcLane == <NUM_LIT> && DstLane == <NUM_LIT> ? DSrc : DDst ; bool CurUndef = ! MI . readsRegister ( CurReg , TRI ) ; NewMIB . addReg ( CurReg , getUndefRegState ( CurUndef ) ) ; CurReg = SrcLane == <NUM_LIT> && DstLane == <NUM_LIT> ? DSrc : DDst ; CurUndef = ! MI . readsRegister ( CurReg , TRI ) ; NewMIB . addReg ( CurReg , getUndefRegState ( CurUndef ) ) ; NewMIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( NewMIB ) ; if ( SrcLane == DstLane ) NewMIB . addReg ( SrcReg , RegState :: Implicit ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; MIB . addReg ( DDst , RegState :: Define ) ; CurReg = SrcLane == <NUM_LIT> && DstLane == <NUM_LIT> ? DSrc : DDst ; CurUndef = CurReg == DSrc && ! MI . readsRegister ( CurReg , TRI ) ;


<s> static inline MachineOperand t1CondCodeOp ( bool isDead = false ) {

return MachineOperand :: CreateReg ( <STR_LIT> , true , false , false , isDead ) ;


<s> bool IsPop = isPopOpcode ( MI -> getOpcode ( ) ) ; bool IsPush = isPushOpcode ( MI -> getOpcode ( ) ) ; if ( ! IsPush && ! IsPop ) return false ; bool IsVFPPushPop = MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ; bool IsT1PushPop = MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ; assert ( ( IsT1PushPop || ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; if ( NumBytes % ( IsVFPPushPop ? <NUM_LIT> : <NUM_LIT> ) != <NUM_LIT> ) return false ; int RegListIdx = IsT1PushPop ? <NUM_LIT> : <NUM_LIT> ; unsigned FirstReg = MI -> getOperand ( RegListIdx ) . getReg ( ) ; unsigned RD0Reg , RegsNeeded ; if ( IsVFPPushPop ) { RD0Reg = <STR_LIT> ; RegsNeeded = NumBytes / <NUM_LIT> ; } else { RD0Reg = <STR_LIT> ; RegsNeeded = NumBytes / <NUM_LIT> ; } SmallVector < MachineOperand , <NUM_LIT> > RegList ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx ; -- i ) RegList . push_back ( MI -> getOperand ( i ) ) ; const TargetRegisterInfo * TRI = MF . getRegInfo ( ) . getTargetRegisterInfo ( ) ;

const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ;


<s> if ( convertAddSubFlagsOpcode ( MI . getOpcode ( ) ) ) { ErrInfo = <STR_LIT> ; return false ; } return true ;


<s> <STR_LIT> CC = getInstrPredicate ( MI , PredReg ) ; if ( CC == <STR_LIT> || PredReg != <STR_LIT> ) return nullptr ; MI = TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ; if ( ! MI ) return nullptr ; MI -> getOperand ( MI -> findFirstPredOperandIdx ( ) ) . setImm ( <STR_LIT> ( CC ) ) ; return MI ; } }

return TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ;


<s> SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = Subtarget . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; Spacing = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; Spacing = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; Spacing = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) && Subtarget . isFPOnlySP ( ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( SrcReg == <STR_LIT> ) { copyFromCPSR ( MBB , I , DestReg , KillSrc , Subtarget ) ; return ; } else if ( DestReg == <STR_LIT> ) { copyToCPSR ( MBB , I , SrcReg , KillSrc , Subtarget ) ; return ; } assert ( Opc && <STR_LIT> ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; MachineInstrBuilder Mov ; if ( TRI -> regsOverlap ( SrcReg , TRI -> getSubReg ( DestReg , BeginIdx ) ) ) { BeginIdx = BeginIdx + ( ( SubRegs - <NUM_LIT> ) * Spacing ) ; Spacing = - Spacing ; } SmallSet < unsigned , <NUM_LIT> > DstRegs ; for ( unsigned i = <NUM_LIT> ; i != SubRegs ; ++ i ) { unsigned Dst = TRI -> getSubReg ( DestReg , BeginIdx + i * Spacing ) ; unsigned Src = TRI -> getSubReg ( SrcReg , BeginIdx + i * Spacing ) ; assert ( Dst && Src && <STR_LIT> ) ; assert ( ! DstRegs . count ( Src ) && <STR_LIT> ) ; DstRegs . insert ( Dst ) ; Mov = BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( Opc ) , Dst ) . addReg ( Src ) ; if ( Opc == <STR_LIT> ) Mov . addReg ( Src ) ; Mov = AddDefaultPred ( Mov ) ;

if ( Opc == <STR_LIT> ) Mov = AddDefaultCC ( Mov ) ;


<s> AddDefaultPred ( LDM . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ) ; AddDefaultPred ( STM . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ) ; const TargetRegisterInfo & TRI = getRegisterInfo ( ) ; llvm :: SmallVector < unsigned , <NUM_LIT> > ScratchRegs ; for ( unsigned I = <NUM_LIT> ; I < MI -> getNumOperands ( ) ; ++ I ) ScratchRegs . push_back ( MI -> getOperand ( I ) . getReg ( ) ) ; std :: sort ( ScratchRegs . begin ( ) , ScratchRegs . end ( ) , [ & TRI ] ( const unsigned & Reg1 , const unsigned & Reg2 ) -> bool { return TRI . getEncodingValue ( Reg1 ) < TRI . getEncodingValue ( Reg2 ) ; } ) ; for ( const auto & Reg : ScratchRegs ) { LDM . addReg ( Reg , RegState :: Define ) ;

STM . addReg ( Reg , RegState :: Kill ) ;


<s> const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || ! SrcRegD ) return false ; if ( ! MI -> definesRegister ( DstRegD , TRI ) || MI -> readsRegister ( DstRegD , TRI ) ) return false ; if ( MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MachineInstrBuilder MIB ( * MI -> getParent ( ) -> getParent ( ) , MI ) ; int ImpDefIdx = MI -> findRegisterDefOperandIdx ( DstRegD ) ; if ( ImpDefIdx != - <NUM_LIT> ) MI -> RemoveOperand ( ImpDefIdx ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( DstRegD ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( SrcRegD ) ; AddDefaultPred ( MIB ) ; MI -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; MIB . addReg ( SrcRegS , RegState :: Implicit ) ;

if ( MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) {


<s> while ( II != E && II -> isInsideBundle ( ) ) { Idx = II -> findRegisterUseOperandIdx ( Reg , false , TRI ) ; if ( Idx != - <NUM_LIT> ) break ; if ( II -> getOpcode ( ) != <STR_LIT> ) ++ Dist ; ++ II ; } if ( Idx == - <NUM_LIT> ) { Dist = <NUM_LIT> ; return nullptr ; } UseIdx = Idx ;


<s> if ( Subtarget . hasNEON ( ) ) { if ( MI -> getOpcode ( ) == <STR_LIT> && ! isPredicated ( MI ) ) return std :: make_pair ( ExeVFP , ( <NUM_LIT> << ExeVFP ) | ( <NUM_LIT> << ExeNEON ) ) ;

if ( Subtarget . isCortexA9 ( ) && ! isPredicated ( MI ) && ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ) return std :: make_pair ( ExeVFP , ( <NUM_LIT> << ExeVFP ) | ( <NUM_LIT> << ExeNEON ) ) ;


<s> if ( Subtarget . isCortexA9 ( ) && ! isPredicated ( MI ) && ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ) return std :: make_pair ( ExeVFP , ( <NUM_LIT> << ExeVFP ) | ( <NUM_LIT> << ExeNEON ) ) ; } unsigned Domain = MI -> getDesc ( ) . TSFlags & <STR_LIT> ; if ( Domain & <STR_LIT> ) return std :: make_pair ( ExeNEON , <NUM_LIT> ) ; if ( ( Domain & <STR_LIT> ) && Subtarget . isCortexA8 ( ) ) return std :: make_pair ( ExeNEON , <NUM_LIT> ) ; if ( Domain & <STR_LIT> ) return std :: make_pair ( ExeVFP , <NUM_LIT> ) ;

return std :: make_pair ( ExeGeneric , <NUM_LIT> ) ;


<s> while ( ++ I != E && I -> isInsideBundle ( ) ) { assert ( ! I -> isBundle ( ) && <STR_LIT> ) ; Size += GetInstSizeInBytes ( & * I ) ;


<s> unsigned <ISA_LIT>BaseInstrInfo :: getInstBundleLength ( const MachineInstr * MI ) const { unsigned Size = <NUM_LIT> ; MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ;

while ( ++ I != E && I -> isInsideBundle ( ) ) {


<s> if ( MI -> isCopyLike ( ) || MI -> isInsertSubreg ( ) || MI -> isRegSequence ( ) || MI -> isImplicitDef ( ) ) return <NUM_LIT> ; if ( MI -> isBundle ( ) ) { unsigned Latency = <NUM_LIT> ; MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) { if ( I -> getOpcode ( ) != <STR_LIT> ) Latency += getInstrLatency ( ItinData , & * I , PredCost ) ; } return Latency ; } const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( PredCost && ( MCID . isCall ( ) || MCID . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumRegs = MI -> getNumOperands ( ) - Desc . getNumOperands ( ) ; return ( NumRegs / <NUM_LIT> ) + ( NumRegs % <NUM_LIT> ) + <NUM_LIT> ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumRegs = MI -> getNumOperands ( ) - Desc . getNumOperands ( ) + <NUM_LIT> ; if ( Subtarget . isSwift ( ) ) { int UOps = <NUM_LIT> + NumRegs ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ++ UOps ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : UOps += <NUM_LIT> ; break ; } return UOps ;

} else if ( Subtarget . isCortexA8 ( ) || Subtarget . isCortexA7 ( ) ) {


<s> else if ( ShImm == <NUM_LIT> && <STR_LIT> ( ShOpVal ) == <STR_LIT> ) -- Latency ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Latency -= <NUM_LIT> ; break ; } } } if ( DefAlign < <NUM_LIT> && Subtarget . isLikeA9 ( ) ) switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ++ Latency ; break ; }


<s> if ( Subtarget . isCortexA8 ( ) && ( DDomain == <STR_LIT> || UDomain == <STR_LIT> ) ) return true ; unsigned Latency = SchedModel . computeOperandLatency ( DefMI , DefIdx , UseMI , UseIdx ) ;

if ( Latency <= <NUM_LIT> ) return false ;


<s> bool <ISA_LIT>BaseInstrInfo :: hasHighOperandLatency ( const TargetSchedModel & SchedModel , const MachineRegisterInfo * MRI , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { unsigned DDomain = DefMI -> getDesc ( ) . TSFlags & <STR_LIT> ; unsigned UDomain = UseMI -> getDesc ( ) . TSFlags & <STR_LIT> ;

if ( Subtarget . isCortexA8 ( ) && ( DDomain == <STR_LIT> || UDomain == <STR_LIT> ) ) return true ;


<s> unsigned DDomain = DefMI -> getDesc ( ) . TSFlags & <STR_LIT> ; if ( DDomain == <STR_LIT> ) { unsigned DefClass = DefMI -> getDesc ( ) . getSchedClass ( ) ; int DefCycle = ItinData -> getOperandCycle ( DefClass , DefIdx ) ;

return ( DefCycle != - <NUM_LIT> && DefCycle <= <NUM_LIT> ) ;


<s> bool isThumb = AFI -> isThumbFunction ( ) || AFI -> isThumb2Function ( ) ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( ! FBB ) { if ( Cond . empty ( ) ) { if ( isThumb ) BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else BuildMI ( & MBB , DL , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addOperand ( Cond [ <NUM_LIT> ] ) ; return <NUM_LIT> ;


<s> if ( MBB . getParent ( ) -> getFunction ( ) -> optForSize ( ) ) { MachineBasicBlock * Pred = * MBB . pred_begin ( ) ; if ( ! Pred -> empty ( ) ) { MachineInstr * LastMI = & * Pred -> rbegin ( ) ; if ( LastMI -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator CmpMI = LastMI ; if ( CmpMI != Pred -> begin ( ) ) { -- CmpMI ; if ( CmpMI -> getOpcode ( ) == <STR_LIT> || CmpMI -> getOpcode ( ) == <STR_LIT> ) { unsigned Reg = CmpMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> P = getInstrPredicate ( CmpMI , PredReg ) ; if ( P == <STR_LIT> && CmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && is<ISA_LIT>LowRegister ( Reg ) ) return false ; } } } }


<s> if ( featureBits [ <STR_LIT> ] && ( Num & <NUM_LIT> ) == <NUM_LIT> ) return false ; if ( featureBits [ <STR_LIT> ] && ( ( Num & <NUM_LIT> ) == <NUM_LIT> || ( Num & <NUM_LIT> ) == <NUM_LIT> ) ) return false ; return true ;


<s> if ( featureBits [ <STR_LIT> ] && ( ( Num & <NUM_LIT> ) == <NUM_LIT> || ( Num & <NUM_LIT> ) == <NUM_LIT> ) ) return false ;


<s> MachineOperand FalseReg = MI -> getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * PreviousClass = MRI . getRegClass ( FalseReg . getReg ( ) ) ; if ( ! MRI . constrainRegClass ( DestReg , PreviousClass ) ) return nullptr ; MachineInstrBuilder NewMI = BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . addOperand ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( <STR_LIT> ( <STR_LIT> ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMI -> hasOptionalDef ( ) ) AddDefaultCC ( NewMI ) ; FalseReg . setImplicit ( ) ; NewMI . addOperand ( FalseReg ) ; NewMI -> tieOperands ( <NUM_LIT> , NewMI -> getNumOperands ( ) - <NUM_LIT> ) ;


<s> const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . addOperand ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( <STR_LIT> ( <STR_LIT> ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMI -> hasOptionalDef ( ) ) AddDefaultCC ( NewMI ) ; FalseReg . setImplicit ( ) ; NewMI . addOperand ( FalseReg ) ; NewMI -> tieOperands ( <NUM_LIT> , NewMI -> getNumOperands ( ) - <NUM_LIT> ) ; SeenMIs . insert ( NewMI ) ; SeenMIs . erase ( DefMI ) ; if ( DefMI -> getParent ( ) != MI -> getParent ( ) ) NewMI -> clearKillInfo ( ) ; DefMI -> eraseFromParent ( ) ; return NewMI ;


<s> unsigned Opc = MI -> getOpcode ( ) ; if ( isUncondBranchOpcode ( Opc ) ) { MI -> setDesc ( get ( getMatchingCondBranchOpcode ( Opc ) ) ) ; MachineInstrBuilder ( * MI -> getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; return true ; } int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) { MachineOperand & PMO = MI -> getOperand ( PIdx ) ; PMO . setImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) ; MI -> getOperand ( PIdx + <NUM_LIT> ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; return true ; }


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return MO0 . getGlobal ( ) == MO1 . getGlobal ( ) ; const MachineFunction * MF = MI0 -> getParent ( ) -> getParent ( ) ; const MachineConstantPool * MCP = MF -> getConstantPool ( ) ; int CPI0 = MO0 . getIndex ( ) ; int CPI1 = MO1 . getIndex ( ) ; const MachineConstantPoolEntry & MCPE0 = MCP -> getConstants ( ) [ CPI0 ] ; const MachineConstantPoolEntry & MCPE1 = MCP -> getConstants ( ) [ CPI1 ] ; bool is<ISA_LIT>CP0 = MCPE0 . isMachineConstantPoolEntry ( ) ; bool is<ISA_LIT>CP1 = MCPE1 . isMachineConstantPoolEntry ( ) ; if ( is<ISA_LIT>CP0 && is<ISA_LIT>CP1 ) { <ISA_LIT>ConstantPoolValue * ACPV0 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE0 . Val . MachineCPVal ) ; <ISA_LIT>ConstantPoolValue * ACPV1 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE1 . Val . MachineCPVal ) ; return ACPV0 -> hasSameValue ( ACPV1 ) ; } else if ( ! is<ISA_LIT>CP0 && ! is<ISA_LIT>CP1 ) { return MCPE0 . Val . ConstVal == MCPE1 . Val . ConstVal ; } return false ;


<s> return ACPV0 -> hasSameValue ( ACPV1 ) ; } else if ( ! is<ISA_LIT>CP0 && ! is<ISA_LIT>CP1 ) { return MCPE0 . Val . ConstVal == MCPE1 . Val . ConstVal ; } return false ; } else if ( Opcode == <STR_LIT> ) { if ( MI1 -> getOpcode ( ) != Opcode ) return false ; if ( MI0 -> getNumOperands ( ) != MI1 -> getNumOperands ( ) ) return false ; unsigned Addr0 = MI0 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Addr1 = MI1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Addr0 != Addr1 ) { if ( ! MRI || ! TargetRegisterInfo :: isVirtualRegister ( Addr0 ) || ! TargetRegisterInfo :: isVirtualRegister ( Addr1 ) ) return false ; MachineInstr * Def0 = MRI -> getVRegDef ( Addr0 ) ; MachineInstr * Def1 = MRI -> getVRegDef ( Addr1 ) ; if ( ! produceSameValue ( Def0 , Def1 , MRI ) ) return false ; } for ( unsigned i = <NUM_LIT> , e = MI0 -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO0 = MI0 -> getOperand ( i ) ;

const MachineOperand & MO1 = MI1 -> getOperand ( i ) ;


<s> MI -> setDesc ( get ( <STR_LIT> ) ) ; MIB . addReg ( DDst , RegState :: Define ) . addReg ( DDst , getUndefRegState ( ! MI -> readsRegister ( DDst , TRI ) ) ) . addImm ( SrcLane ) ; AddDefaultPred ( MIB ) ; MIB . addReg ( DstReg , RegState :: Implicit | RegState :: Define ) ; MIB . addReg ( SrcReg , RegState :: Implicit ) ; if ( ImplicitSReg != <NUM_LIT> ) MIB . addReg ( ImplicitSReg , RegState :: Implicit ) ; break ; } MachineInstrBuilder NewMIB ; NewMIB = BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DDst ) ; unsigned CurReg = SrcLane == <NUM_LIT> && DstLane == <NUM_LIT> ? DSrc : DDst ; bool CurUndef = ! MI -> readsRegister ( CurReg , TRI ) ; NewMIB . addReg ( CurReg , getUndefRegState ( CurUndef ) ) ; CurReg = SrcLane == <NUM_LIT> && DstLane == <NUM_LIT> ? DSrc : DDst ; CurUndef = ! MI -> readsRegister ( CurReg , TRI ) ; NewMIB . addReg ( CurReg , getUndefRegState ( CurUndef ) ) ; NewMIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( NewMIB ) ; if ( SrcLane == DstLane ) NewMIB . addReg ( SrcReg , RegState :: Implicit ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MIB . addReg ( DDst , RegState :: Define ) ; CurReg = SrcLane == <NUM_LIT> && DstLane == <NUM_LIT> ? DSrc : DDst ; CurUndef = CurReg == DSrc && ! MI -> readsRegister ( CurReg , TRI ) ; MIB . addReg ( CurReg , getUndefRegState ( CurUndef ) ) ; CurReg = SrcLane == <NUM_LIT> && DstLane == <NUM_LIT> ? DSrc : DDst ; CurUndef = CurReg == DSrc && ! MI -> readsRegister ( CurReg , TRI ) ; MIB . addReg ( CurReg , getUndefRegState ( CurUndef ) ) ; MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; if ( SrcLane != DstLane ) MIB . addReg ( SrcReg , RegState :: Implicit ) ; MIB . addReg ( DstReg , RegState :: Define | RegState :: Implicit ) ; if ( ImplicitSReg != <NUM_LIT> ) MIB . addReg ( ImplicitSReg , RegState :: Implicit ) ;


<s> DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( unsigned i = MI -> getDesc ( ) . getNumOperands ( ) ; i ; -- i ) MI -> RemoveOperand ( i - <NUM_LIT> ) ; DReg = getCorrespondingDRegAndLane ( TRI , SrcReg , Lane ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; AddDefaultPred ( MIB . addReg ( DstReg , RegState :: Define ) . addReg ( DReg , RegState :: Undef ) . addImm ( Lane ) ) ; MIB . addReg ( SrcReg , RegState :: Implicit ) ; break ; case <STR_LIT> : { if ( Domain != ExeNEON ) break ; assert ( ! isPredicated ( MI ) && <STR_LIT> ) ; DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; DReg = getCorrespondingDRegAndLane ( TRI , DstReg , Lane ) ; unsigned ImplicitSReg ; if ( ! getImplicitSPRUseForDPRUse ( TRI , MI , DReg , Lane , ImplicitSReg ) ) break ; for ( unsigned i = MI -> getDesc ( ) . getNumOperands ( ) ; i ; -- i ) MI -> RemoveOperand ( i - <NUM_LIT> ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MIB . addReg ( DReg , RegState :: Define ) . addReg ( DReg , getUndefRegState ( ! MI -> readsRegister ( DReg , TRI ) ) ) . addReg ( SrcReg ) . addImm ( Lane ) ; AddDefaultPred ( MIB ) ; MIB . addReg ( DstReg , RegState :: Define | RegState :: Implicit ) ; if ( ImplicitSReg != <NUM_LIT> ) MIB . addReg ( ImplicitSReg , RegState :: Implicit ) ; break ; } case <STR_LIT> : { if ( Domain != ExeNEON ) break ; DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstLane = <NUM_LIT> , SrcLane = <NUM_LIT> , DDst , DSrc ; DDst = getCorrespondingDRegAndLane ( TRI , DstReg , DstLane ) ; DSrc = getCorrespondingDRegAndLane ( TRI , SrcReg , SrcLane ) ; unsigned ImplicitSReg ;

if ( ! getImplicitSPRUseForDPRUse ( TRI , MI , DSrc , SrcLane , ImplicitSReg ) ) break ;


<s> if ( ! SubIdx ) return MIB . addReg ( Reg , State ) ;

if ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) return MIB . addReg ( TRI -> getSubReg ( Reg , SubIdx ) , State ) ;


<s> static const MachineInstrBuilder & AddDReg ( MachineInstrBuilder & MIB , unsigned Reg , unsigned SubIdx , unsigned State , const TargetRegisterInfo * TRI ) {

if ( ! SubIdx ) return MIB . addReg ( Reg , State ) ;


<s> return false ; } else { SecondLastInst = I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; } } } if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; if ( isCondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isUncondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } if ( ( isJumpTableBranchOpcode ( SecondLastOpc ) || isIndirectBranchOpcode ( SecondLastOpc ) ) && isUncondBranchOpcode ( LastOpc ) ) {


<s> if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( -- I ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else { SecondLastInst = I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; } } } if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; if ( isCondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isUncondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } if ( ( isJumpTableBranchOpcode ( SecondLastOpc ) || isIndirectBranchOpcode ( SecondLastOpc ) ) && isUncondBranchOpcode ( LastOpc ) ) { I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ;


<s> SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = ~ <NUM_LIT> ; CmpValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;

CmpMask = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( Load1 -> getOperand ( <NUM_LIT> ) != Load2 -> getOperand ( <NUM_LIT> ) || Load1 -> getOperand ( <NUM_LIT> ) != Load2 -> getOperand ( <NUM_LIT> ) ) return false ; if ( Load1 -> getOperand ( <NUM_LIT> ) != Load2 -> getOperand ( <NUM_LIT> ) ) return false ; if ( isa < ConstantSDNode > ( Load1 -> getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( Load2 -> getOperand ( <NUM_LIT> ) ) ) { Offset1 = cast < ConstantSDNode > ( Load1 -> getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; Offset2 = cast < ConstantSDNode > ( Load2 -> getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; return true ; } return false ;


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( Load1 -> getOperand ( <NUM_LIT> ) != Load2 -> getOperand ( <NUM_LIT> ) || Load1 -> getOperand ( <NUM_LIT> ) != Load2 -> getOperand ( <NUM_LIT> ) ) return false ; if ( Load1 -> getOperand ( <NUM_LIT> ) != Load2 -> getOperand ( <NUM_LIT> ) ) return false ; if ( isa < ConstantSDNode > ( Load1 -> getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( Load2 -> getOperand ( <NUM_LIT> ) ) ) { Offset1 = cast < ConstantSDNode > ( Load1 -> getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; Offset2 = cast < ConstantSDNode > ( Load2 -> getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; return true ;


<s> else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> , Spacing = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> , Spacing = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> , Spacing = <NUM_LIT> ; if ( Opc ) { const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; MachineInstrBuilder Mov ;

for ( unsigned i = <NUM_LIT> ; i != SubRegs ; ++ i ) {


<s> else if ( GPRDest && SPRSrc ) Opc = <STR_LIT> ; else if ( SPRDest && GPRSrc ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; if ( Opc ) { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) ; MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; if ( Opc == <STR_LIT> ) MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; AddDefaultPred ( MIB ) ; return ; } unsigned BeginIdx = <NUM_LIT> ; unsigned SubRegs = <NUM_LIT> ; unsigned Spacing = <NUM_LIT> ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> , Spacing = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> , Spacing = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> , Spacing = <NUM_LIT> ; if ( Opc ) { const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; MachineInstrBuilder Mov ; for ( unsigned i = <NUM_LIT> ; i != SubRegs ; ++ i ) { unsigned Dst = TRI -> getSubReg ( DestReg , BeginIdx + i * Spacing ) ; unsigned Src = TRI -> getSubReg ( SrcReg , BeginIdx + i * Spacing ) ; assert ( Dst && Src && <STR_LIT> ) ; Mov = AddDefaultPred ( BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( Opc ) , Dst ) . addReg ( Src ) ) ; if ( Opc == <STR_LIT> ) Mov . addReg ( Src ) ; } Mov -> addRegisterDefined ( DestReg , TRI ) ; if ( KillSrc ) Mov -> addRegisterKilled ( SrcReg , TRI ) ; return ; } llvm_unreachable ( <STR_LIT> ) ;


<s> const InstrItineraryData * II = TM -> getInstrItineraryData ( ) ; return new ScoreboardHazardRecognizer ( II , DAG , <STR_LIT> ) ;


<s> if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2 ( ) ) return ( ScheduleHazardRecognizer * ) new <ISA_LIT>HazardRecognizer ( II , * this , getRegisterInfo ( ) , Subtarget , DAG ) ; return TargetInstrInfoImpl :: CreateTargetPostRAHazardRecognizer ( II , DAG ) ;


<s> unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; Orig -> getOperand ( <NUM_LIT> ) . setIndex ( CPI ) ; Orig -> getOperand ( <NUM_LIT> ) . setImm ( PCLabelId ) ; break ; } } return MI ;


<s> MachineInstr * <ISA_LIT>BaseInstrInfo :: emitFrameIndexDebugValue ( MachineFunction & MF , int FrameIx , uint64_t Offset , const MDNode * MDPtr , DebugLoc DL ) const { MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIx ) . addImm ( <NUM_LIT> ) . addImm ( Offset ) . addMetadata ( MDPtr ) ; return & * MIB ;


<s> if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || ! SrcRegD ) return false ; if ( ! MI -> definesRegister ( DstRegD , TRI ) || MI -> readsRegister ( DstRegD , TRI ) ) return false ; if ( MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; int ImpDefIdx = MI -> findRegisterDefOperandIdx ( DstRegD ) ; if ( ImpDefIdx != - <NUM_LIT> ) MI -> RemoveOperand ( ImpDefIdx ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( DstRegD ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( SrcRegD ) ; AddDefaultPred ( MachineInstrBuilder ( MI ) ) ;

MI -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ;


<s> if ( ( Domain & <STR_LIT> ) && Subtarget . isCortexA8 ( ) ) return std :: make_pair ( ExeNEON , <NUM_LIT> ) ; if ( Domain & <STR_LIT> ) return std :: make_pair ( ExeVFP , <NUM_LIT> ) ;


<s> std :: pair < uint16_t , uint16_t > <ISA_LIT>BaseInstrInfo :: getExecutionDomain ( const MachineInstr * MI ) const { if ( MI -> getOpcode ( ) == <STR_LIT> && ! isPredicated ( MI ) ) return std :: make_pair ( ExeVFP , ( <NUM_LIT> << ExeVFP ) | ( <NUM_LIT> << ExeNEON ) ) ; unsigned Domain = MI -> getDesc ( ) . TSFlags & <STR_LIT> ; if ( Domain & <STR_LIT> ) return std :: make_pair ( ExeNEON , <NUM_LIT> ) ; if ( ( Domain & <STR_LIT> ) && Subtarget . isCortexA8 ( ) ) return std :: make_pair ( ExeNEON , <NUM_LIT> ) ; if ( Domain & <STR_LIT> ) return std :: make_pair ( ExeVFP , <NUM_LIT> ) ;


<s> while ( ++ I != E && I -> isInsideBundle ( ) ) { if ( I -> getOpcode ( ) != <STR_LIT> ) Latency += getInstrLatency ( ItinData , I , PredCost ) ; } return Latency ; } const MCInstrDesc & MCID = MI -> getDesc ( ) ; unsigned Class = MCID . getSchedClass ( ) ; unsigned UOps = ItinData -> Itineraries [ Class ] . NumMicroOps ;

if ( PredCost && ( MCID . isCall ( ) || MCID . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) ) * PredCost = <NUM_LIT> ;


<s> if ( MI -> isCopyLike ( ) || MI -> isInsertSubreg ( ) || MI -> isRegSequence ( ) || MI -> isImplicitDef ( ) ) return <NUM_LIT> ; if ( ! ItinData || ItinData -> isEmpty ( ) ) return <NUM_LIT> ; if ( MI -> isBundle ( ) ) { int Latency = <NUM_LIT> ; MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) { if ( I -> getOpcode ( ) != <STR_LIT> ) Latency += getInstrLatency ( ItinData , I , PredCost ) ; } return Latency ;


<s> if ( Subtarget . isCortexA8 ( ) ) { DefCycle = RegNo / <NUM_LIT> ; if ( DefCycle < <NUM_LIT> ) DefCycle = <NUM_LIT> ; DefCycle += <NUM_LIT> ; } else if ( Subtarget . isCortexA9 ( ) ) { DefCycle = ( RegNo / <NUM_LIT> ) ; if ( ( RegNo % <NUM_LIT> ) || DefAlign < <NUM_LIT> ) ++ DefCycle ; DefCycle += <NUM_LIT> ; } else { DefCycle = RegNo + <NUM_LIT> ; }


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumRegs = MI -> getNumOperands ( ) - Desc . getNumOperands ( ) ; return ( NumRegs / <NUM_LIT> ) + ( NumRegs % <NUM_LIT> ) + <NUM_LIT> ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumRegs = MI -> getNumOperands ( ) - Desc . getNumOperands ( ) + <NUM_LIT> ;


<s> unsigned <ISA_LIT>BaseInstrInfo :: getOutputLatency ( const InstrItineraryData * ItinData , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * DepMI ) const { unsigned Reg = DefMI -> getOperand ( DefIdx ) . getReg ( ) ;

if ( DepMI -> readsRegister ( Reg , & getRegisterInfo ( ) ) || ! isPredicated ( DepMI ) ) return <NUM_LIT> ;


<s> if ( RegNo <= <NUM_LIT> ) return ItinData -> getOperandCycle ( UseClass , UseIdx ) ; int UseCycle ; if ( Subtarget . isCortexA8 ( ) ) { UseCycle = RegNo / <NUM_LIT> ; if ( UseCycle < <NUM_LIT> ) UseCycle = <NUM_LIT> ; UseCycle += <NUM_LIT> ; } else if ( Subtarget . isCortexA9 ( ) ) { UseCycle = ( RegNo / <NUM_LIT> ) ; if ( ( RegNo % <NUM_LIT> ) || UseAlign < <NUM_LIT> ) ++ UseCycle ; } else { UseCycle = <NUM_LIT> ; }


<s> DefCycle = RegNo ; bool isSLoad = false ; switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : isSLoad = true ; break ; } if ( ( isSLoad && ( RegNo % <NUM_LIT> ) ) || DefAlign < <NUM_LIT> ) ++ DefCycle ; } else { DefCycle = RegNo + <NUM_LIT> ;


<s> int RegNo = ( int ) ( UseIdx + <NUM_LIT> ) - UseMCID . getNumOperands ( ) + <NUM_LIT> ; if ( RegNo <= <NUM_LIT> ) return ItinData -> getOperandCycle ( UseClass , UseIdx ) ; int UseCycle ; if ( Subtarget . isCortexA8 ( ) ) { UseCycle = RegNo / <NUM_LIT> + <NUM_LIT> ; if ( RegNo % <NUM_LIT> ) ++ UseCycle ; } else if ( Subtarget . isCortexA9 ( ) ) { UseCycle = RegNo ;


<s> bool <ISA_LIT>BaseInstrInfo :: hasHighOperandLatency ( const InstrItineraryData * ItinData , const MachineRegisterInfo * MRI , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const {

unsigned DDomain = DefMI -> getDesc ( ) . TSFlags & <STR_LIT> ;


<s> unsigned UDomain = UseMI -> getDesc ( ) . TSFlags & <STR_LIT> ; if ( Subtarget . isCortexA8 ( ) && ( DDomain == <STR_LIT> || UDomain == <STR_LIT> ) ) return true ; int Latency = getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; if ( Latency <= <NUM_LIT> ) return false ; return DDomain == <STR_LIT> || DDomain == <STR_LIT> || UDomain == <STR_LIT> || UDomain == <STR_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ;


<s> case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> :

if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) {


<s> case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> :


<s> MI -> setDesc ( get ( getMatchingCondBranchOpcode ( Opc ) ) ) ; MI -> addOperand ( MachineOperand :: CreateImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) ) ; MI -> addOperand ( MachineOperand :: CreateReg ( Pred [ <NUM_LIT> ] . getReg ( ) , false ) ) ; return true ; } int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) { MachineOperand & PMO = MI -> getOperand ( PIdx ) ; PMO . setImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) ; MI -> getOperand ( PIdx + <NUM_LIT> ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; return true ; } return false ;


<s> if ( PIdx != - <NUM_LIT> ) { MachineOperand & PMO = MI -> getOperand ( PIdx ) ; PMO . setImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) ; MI -> getOperand ( PIdx + <NUM_LIT> ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; return true ; } return false ;


<s> MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; AddDefaultPred ( MachineInstrBuilder ( MI ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ) ;