<s> unsigned Opc = Entry . NarrowOpc1 ; unsigned OpNum = <NUM_LIT> ; uint8_t ImmLimit = Entry . Imm1Limit ; switch ( Entry . WideOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : { unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg == <STR_LIT> ) { Opc = Entry . NarrowOpc2 ; ImmLimit = Entry . Imm2Limit ; HasOffReg = false ; } Scale = <NUM_LIT> ; HasImmOffset = true ; break ; } case <STR_LIT> : case <STR_LIT> : HasImmOffset = true ; break ; case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; HasImmOffset = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : HasShift = true ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : { unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; <STR_LIT> Mode = <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( ! is<ISA_LIT>LowRegister ( BaseReg ) || Mode != <STR_LIT> ) return false ; OpNum = <NUM_LIT> ; isLdStMul = true ; break ; } case <STR_LIT> : { unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg != <STR_LIT> ) return false ; Opc = Entry . NarrowOpc2 ; OpNum = <NUM_LIT> ; isLdStMul = true ; break ; } case <STR_LIT> : case <STR_LIT> : { OpNum = <NUM_LIT> ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; <STR_LIT> Mode = <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( BaseReg == <STR_LIT> && ( ( Entry . WideOpc == <STR_LIT> && Mode == <STR_LIT> ) || ( Entry . WideOpc == <STR_LIT> && Mode == <STR_LIT> ) ) ) { Opc = Entry . NarrowOpc2 ;


<s> } } else if ( Reg0 != Reg1 ) { unsigned CommOpIdx1 , CommOpIdx2 ; if ( ! TII -> findCommutedOpIndices ( MI , CommOpIdx1 , CommOpIdx2 ) || CommOpIdx1 != <NUM_LIT> || MI -> getOperand ( CommOpIdx2 ) . getReg ( ) != Reg0 ) return false ; MachineInstr * CommutedMI = TII -> commuteInstruction ( MI ) ; if ( ! CommutedMI ) return false ; } if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg0 ) ) return false ; if ( Entry . Imm2Limit ) { unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Limit = ( <NUM_LIT> << Entry . Imm2Limit ) - <NUM_LIT> ; if ( Imm > Limit ) return false ; } else { unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc2 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , true , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( MI , IsSelfLoop ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ;

MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl , NewMCID ) ;


<s> const TargetMachine & TM = MF . getTarget ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; STI = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AttributeSet FnAttrs = MF . getFunction ( ) -> getAttributes ( ) ; OptimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; MinimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ;

ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ;


<s> if ( ReduceLimitLdSt != - <NUM_LIT> && ( ( int ) NumLdSts >= ReduceLimitLdSt ) ) return false ; unsigned Scale = <NUM_LIT> ; bool HasImmOffset = false ; bool HasShift = false ; bool HasOffReg = true ; bool isLdStMul = false ; unsigned Opc = Entry . NarrowOpc1 ; unsigned OpNum = <NUM_LIT> ; uint8_t ImmLimit = Entry . Imm1Limit ; switch ( Entry . WideOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { Opc = Entry . NarrowOpc2 ; ImmLimit = Entry . Imm2Limit ; HasOffReg = false ; } Scale = <NUM_LIT> ; HasImmOffset = true ; HasOffReg = false ; break ; case <STR_LIT> : case <STR_LIT> : HasImmOffset = true ; HasOffReg = false ; break ; case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; HasImmOffset = true ; HasOffReg = false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : HasShift = true ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : { unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! is<ISA_LIT>LowRegister ( BaseReg ) || Entry . WideOpc != <STR_LIT> ) return false ; bool isOK = false ; for ( unsigned i = <NUM_LIT> ; i < MI -> getNumOperands ( ) ; ++ i ) { if ( MI -> getOperand ( i ) . getReg ( ) == BaseReg ) { isOK = true ; break ; } } if ( ! isOK ) return false ; OpNum = <NUM_LIT> ; isLdStMul = true ; break ; } case <STR_LIT> : { unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg != <STR_LIT> ) return false ; Opc = Entry . NarrowOpc2 ; OpNum = <NUM_LIT> ; isLdStMul = true ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { OpNum = <NUM_LIT> ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg == <STR_LIT> && ( Entry . WideOpc == <STR_LIT> || Entry . WideOpc == <STR_LIT> ) ) { Opc = Entry . NarrowOpc2 ; OpNum = <NUM_LIT> ; } else if ( ! is<ISA_LIT>LowRegister ( BaseReg ) || ( Entry . WideOpc != <STR_LIT> && Entry . WideOpc != <STR_LIT> ) ) { return false ; } isLdStMul = true ; break ; } } unsigned OffsetReg = <NUM_LIT> ; bool OffsetKill = false ; if ( HasShift ) { OffsetReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OffsetKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) return false ; }


<s> MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; goto ProcessNext ; } if ( Entry . NarrowOpc1 && ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ) { Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; } } ProcessNext : bool DefCPSR = false ; LiveCPSR = UpdateCPSRDef ( * MI , LiveCPSR , DefCPSR ) ; if ( MI -> getDesc ( ) . isCall ( ) ) { CPSRDef = <NUM_LIT> ; IsSelfLoop = false ; } else if ( DefCPSR ) { CPSRDef = MI ;


<s> } goto ProcessNext ; } if ( Entry . NarrowOpc2 && ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ) { Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; goto ProcessNext ; } if ( Entry . NarrowOpc1 && ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ) { Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; } } ProcessNext : bool DefCPSR = false ; LiveCPSR = UpdateCPSRDef ( * MI , LiveCPSR , DefCPSR ) ; if ( MI -> getDesc ( ) . isCall ( ) ) { CPSRDef = <NUM_LIT> ;


<s> unsigned PredReg = <NUM_LIT> ; if ( getInstrPredicate ( MI , PredReg ) == <STR_LIT> ) { switch ( Opc ) { default : break ; case <STR_LIT> : { if ( ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ) return true ; } case <STR_LIT> : return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ; } } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ; break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ; break ; case <STR_LIT> : { static const ReduceEntry NarrowEntry = { <STR_LIT> , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( ReduceToNarrow ( MBB , MI , NarrowEntry , LiveCPSR , CPSRDef , IsSelfLoop ) ) return true ;


<s> } else { unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc2 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , true , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( CPSRDef , MI , IsSelfLoop ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , dl , NewMCID ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ;


<s> if ( Entry . Imm2Limit ) { unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Limit = ( <NUM_LIT> << Entry . Imm2Limit ) - <NUM_LIT> ; if ( Imm > Limit ) return false ; } else { unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc2 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ;

HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ;


<s> MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef ( ) ) { if ( HasCC ) AddDefaultT1CC ( MIB , CCDead ) ; else AddNoT1CC ( MIB ) ; } unsigned NumOps = MCID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && MCID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( ( MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> ) && i == <NUM_LIT> ) continue ; bool isPred = ( i < NumOps && MCID . OpInfo [ i ] . isPredicate ( ) ) ; if ( SkipPred && isPred ) continue ; const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isImplicit ( ) && MO . getReg ( ) == <STR_LIT> ) continue ; MIB . addOperand ( MO ) ; } if ( ! MCID . isPredicable ( ) && NewMCID . isPredicable ( ) ) AddDefaultPred ( MIB ) ; MIB . setMIFlags ( MI -> getFlags ( ) ) ; DEBUG ( errs ( ) << <STR_LIT> << * MI << <STR_LIT> << * MIB ) ; MBB . erase ( MI ) ; ++ NumNarrows ; return true ;


<s> for ( unsigned i = <NUM_LIT> , e = Use -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = Use -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isUndef ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ;

if ( Defs . count ( Reg ) ) return false ;


<s> Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; } goto ProcessNext ; } if ( Entry . NarrowOpc2 && ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , CPSRDef ) ) { Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; goto ProcessNext ; } if ( Entry . NarrowOpc1 && ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef ) ) { Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; } } ProcessNext : bool DefCPSR = false ; LiveCPSR = UpdateCPSRDef ( * MI , LiveCPSR , DefCPSR ) ;

if ( MI -> getDesc ( ) . isCall ( ) ) CPSRDef = <NUM_LIT> ;


<s> if ( Opc == <STR_LIT> ) { if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) { if ( ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , CPSRDef ) ) return true ; return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef ) ; } unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Imm & <NUM_LIT> || Imm > <NUM_LIT> ) return false ; if ( ! is<ISA_LIT>LowRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> ) return false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) && MI -> getOperand ( MCID . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addImm ( Imm / <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; MIB . setMIFlags ( MI -> getFlags ( ) ) ; DEBUG ( errs ( ) << <STR_LIT> << * MI << <STR_LIT> << * MIB ) ; MBB . erase ( MI ) ; ++ NumNarrows ; return true ; } if ( Entry . LowRegs1 && ! VerifyLowRegs ( MI ) ) return false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . mayLoad ( ) || MCID . mayStore ( ) ) return ReduceLoadStore ( MBB , MI , Entry ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned PredReg = <NUM_LIT> ; if ( getInstrPredicate ( MI , PredReg ) == <STR_LIT> ) { switch ( Opc ) { default : break ; case <STR_LIT> : { if ( ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , CPSRDef ) ) return true ; } case <STR_LIT> : return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef ) ; } } break ;


<s> if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg0 ) ) return false ; if ( Entry . Imm2Limit ) { unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Limit = ( <NUM_LIT> << Entry . Imm2Limit ) - <NUM_LIT> ; if ( Imm > Limit ) return false ; } else { unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc2 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , true , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( CPSRDef , MI ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , dl , NewMCID ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ;


<s> if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , true , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( CPSRDef , MI ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , dl , NewMCID ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef ( ) ) { if ( HasCC ) AddDefaultT1CC ( MIB , CCDead ) ; else AddNoT1CC ( MIB ) ; } unsigned NumOps = MCID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && MCID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( SkipPred && MCID . OpInfo [ i ] . isPredicate ( ) ) continue ; MIB . addOperand ( MI -> getOperand ( i ) ) ; }

MIB . setMIFlags ( MI -> getFlags ( ) ) ;


<s> bool CCDead = false ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , false , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( CPSRDef , MI ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , dl , NewMCID ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef ( ) ) { if ( HasCC ) AddDefaultT1CC ( MIB , CCDead ) ; else AddNoT1CC ( MIB ) ; } unsigned NumOps = MCID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && MCID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( ( MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> ) && i == <NUM_LIT> ) continue ; bool isPred = ( i < NumOps && MCID . OpInfo [ i ] . isPredicate ( ) ) ; if ( SkipPred && isPred ) continue ;

const MachineOperand & MO = MI -> getOperand ( i ) ;


<s> } } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc1 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , false , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( CPSRDef , MI ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , dl , NewMCID ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef ( ) ) { if ( HasCC ) AddDefaultT1CC ( MIB , CCDead ) ; else AddNoT1CC ( MIB ) ; } unsigned NumOps = MCID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && MCID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( ( MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> ) && i == <NUM_LIT> ) continue ;

bool isPred = ( i < NumOps && MCID . OpInfo [ i ] . isPredicate ( ) ) ;


<s> HasOffReg = false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : HasShift = true ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : { if ( ! MinimizeSize ) return false ; if ( ! MI -> hasOneMemOperand ( ) || ( * MI -> memoperands_begin ( ) ) -> getAlignment ( ) < <NUM_LIT> ) return false ; bool IsStore = Entry . WideOpc == <STR_LIT> ; Register Rt = MI -> getOperand ( IsStore ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; Register Rn = MI -> getOperand ( IsStore ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; unsigned Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned PredImm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; Register PredReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( is<ISA_LIT>LowRegister ( Rt ) ) ; assert ( is<ISA_LIT>LowRegister ( Rn ) ) ; if ( Offset != <NUM_LIT> ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; auto MIB = BuildMI ( MBB , MI , dl , TII -> get ( Entry . NarrowOpc1 ) ) . addReg ( Rn , RegState :: Define ) . addReg ( Rn ) . addImm ( PredImm ) . addReg ( PredReg ) . addReg ( Rt , IsStore ? <NUM_LIT> : RegState :: Define ) ; MIB . setMemRefs ( MI -> memoperands ( ) ) ; MIB . setMIFlags ( MI -> getFlags ( ) ) ; MI -> eraseFromBundle ( ) ; ++ NumLdSts ; return true ; } case <STR_LIT> : { Register BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( is<ISA_LIT>LowRegister ( BaseReg ) ) ; bool isOK = false ; for ( unsigned i = <NUM_LIT> ; i < MI -> getNumOperands ( ) ; ++ i ) { if ( MI -> getOperand ( i ) . getReg ( ) == BaseReg ) { isOK = true ; break ; } } if ( ! isOK ) return false ; OpNum = <NUM_LIT> ; isLdStMul = true ; break ; } case <STR_LIT> : if ( ! MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) return false ; break ; case <STR_LIT> : { Register BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg != <STR_LIT> ) return false ; Opc = Entry . NarrowOpc2 ;


<s> const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc1 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , false , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( MI , IsSelfLoop ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl , NewMCID ) ; if ( MCID . getOpcode ( ) == <STR_LIT> ) { MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; MIB -> getOperand ( <NUM_LIT> ) . setIsDef ( true ) ; MIB -> getOperand ( <NUM_LIT> ) . setIsDead ( true ) ; if ( NewMCID . hasOptionalDef ( ) ) MIB . add ( HasCC ? t1CondCodeOp ( CCDead ) : condCodeOp ( ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; } else { MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef ( ) ) MIB . add ( HasCC ? t1CondCodeOp ( CCDead ) : condCodeOp ( ) ) ; } unsigned NumOps = MCID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && MCID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( ( MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> ) && i == <NUM_LIT> ) continue ;


<s> MinimizeSize = STI -> optForMinSize ( ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; bool Modified = false ;

for ( ReversePostOrderTraversal < MachineFunction * > :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I ) Modified |= ReduceMBB ( * * I ) ;


<s> if ( PredicateFtor && ! PredicateFtor ( MF . getFunction ( ) ) ) return false ; STI = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; if ( STI -> isThumb1Only ( ) || STI -> prefers32BitThumb ( ) ) return false ;

TII = static_cast < const Thumb2InstrInfo * > ( STI -> getInstrInfo ( ) ) ;


<s> TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; STI = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AttributeSet FnAttrs = MF . getFunction ( ) -> getAttributes ( ) ; OptimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; MinimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ;


<s> TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; STI = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AttributeSet FnAttrs = MF . getFunction ( ) -> getAttributes ( ) ; OptimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; MinimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ;


<s> Opc = Entry . NarrowOpc2 ; OpNum = <NUM_LIT> ; } else if ( ! is<ISA_LIT>LowRegister ( BaseReg ) || ( Entry . WideOpc != <STR_LIT> && Entry . WideOpc != <STR_LIT> ) ) { return false ; } isLdStMul = true ; break ; } } unsigned OffsetReg = <NUM_LIT> ; bool OffsetKill = false ; bool OffsetInternal = false ; if ( HasShift ) { OffsetReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OffsetKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; OffsetInternal = MI -> getOperand ( <NUM_LIT> ) . isInternalRead ( ) ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) return false ; } unsigned OffsetImm = <NUM_LIT> ; if ( HasImmOffset ) { OffsetImm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned MaxOffset = ( ( <NUM_LIT> << ImmLimit ) - <NUM_LIT> ) * Scale ; if ( ( OffsetImm & ( Scale - <NUM_LIT> ) ) || OffsetImm > MaxOffset ) return false ; } DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl , TII -> get ( Opc ) ) ; if ( Entry . WideOpc == <STR_LIT> ) MIB . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , RegState :: Define | RegState :: Dead ) ; if ( ! isLdStMul ) { MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( HasImmOffset ) MIB . addImm ( OffsetImm / Scale ) ; assert ( ( ! HasShift || OffsetReg ) && <STR_LIT> ) ; if ( HasOffReg ) MIB . addReg ( OffsetReg , getKillRegState ( OffsetKill ) | getInternalReadRegState ( OffsetInternal ) ) ; } for ( unsigned e = MI -> getNumOperands ( ) ; OpNum != e ; ++ OpNum ) MIB . add ( MI -> getOperand ( OpNum ) ) ; MIB . setMemRefs ( MI -> memoperands ( ) ) ; MIB . setMIFlags ( MI -> getFlags ( ) ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> << * MI << <STR_LIT> << * MIB ) ; MBB . erase_instr ( MI ) ;


<s> static bool HasImplicitCPSRDef ( const MCInstrDesc & MCID ) {

for ( const uint16_t * Regs = MCID . getImplicitDefs ( ) ; * Regs ; ++ Regs ) if ( * Regs == <STR_LIT> ) return true ;


<s> for ( unsigned i = <NUM_LIT> , e = array_lengthof ( ReduceTable ) ; i != e ; ++ i ) {

unsigned FromOpc = ReduceTable [ i ] . WideOpc ;


<s> static inline unsigned decodeImmShift ( unsigned bits2 , unsigned imm5 , <STR_LIT> & ShOp ) { assert ( imm5 < <NUM_LIT> && <STR_LIT> ) ; switch ( bits2 ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <NUM_LIT> : ShOp = <STR_LIT> ; return imm5 ; case <NUM_LIT> : ShOp = <STR_LIT> ; return ( imm5 == <NUM_LIT> ? <NUM_LIT> : imm5 ) ; case <NUM_LIT> : ShOp = <STR_LIT> ; return ( imm5 == <NUM_LIT> ? <NUM_LIT> : imm5 ) ; case <NUM_LIT> : ShOp = ( imm5 == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; return ( imm5 == <NUM_LIT> ? <NUM_LIT> : imm5 ) ; }


<s> case <STR_LIT> : return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; return <NUM_LIT> ; }


<s> assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) ) && <STR_LIT> ) ;

MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRt ( insn ) ) ) ) ;


<s> static bool DisassembleThumb1AddSPi ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { assert ( Opcode == <STR_LIT> && <STR_LIT> ) ; const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRt ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ;

MI . addOperand ( MCOperand :: CreateImm ( getT1Imm8 ( insn ) ) ) ;


<s> if ( ! OpInfo ) return false ; assert ( NumOps == <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && <STR_LIT> ) ;


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ;

assert ( NumOps == <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && OpInfo [ <NUM_LIT> ] . isPredicate ( ) && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ;


<s> MI . addOperand ( MCOperand :: CreateReg ( B -> InITBlock ( ) ? <NUM_LIT> : <STR_LIT> ) ) ; ++ OpIdx ; } assert ( OpIdx < NumOps && <STR_LIT> ) ; if ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , UseRt ? getT1tRt ( insn ) : getT1tRn ( insn ) ) ) ) ; ++ OpIdx ; } if ( OpIdx == NumOps ) return true ; if ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRm ( insn ) ) ) ) ;


<s> if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRt ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( getT1Imm8 ( insn ) << <NUM_LIT> ) ) ; NumOpsAdded = <NUM_LIT> ; return true ;


assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) ) && <STR_LIT> ) ;


<s> if ( OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) { MI . addOperand ( MCOperand :: CreateImm ( Imm5 ? getT1Imm5 ( insn ) : <NUM_LIT> ) ) ; ++ OpIdx ; } assert ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( Imm5 ? <NUM_LIT> : getRegisterEnum ( B , <STR_LIT> , getT1tRm ( insn ) ) ) ) ; ++ OpIdx ; return true ;


<s> static bool DisassembleThumb1LdSt ( unsigned opA , MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { const TargetInstrDesc & TID = <ISA_LIT>Insts [ Opcode ] ; const TargetOperandInfo * OpInfo = TID . OpInfo ; unsigned & OpIdx = NumOpsAdded ; bool Imm5 = ( opA != <NUM_LIT> ) ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRn ( insn ) ) ) ) ; OpIdx = <NUM_LIT> ; assert ( OpIdx < NumOps && <STR_LIT> ) ; if ( OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) { MI . addOperand ( MCOperand :: CreateImm ( Imm5 ? getT1Imm5 ( insn ) : <NUM_LIT> ) ) ;


<s> ++ OpIdx ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( <STR_LIT> ) ) ) ; ++ OpIdx ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ) ) ; MI . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; OpIdx += <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( ( RegListBits >> i ) & <NUM_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , i ) ) ) ; ++ OpIdx ; } }


<s> assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRt ( insn ) ) ) ) ;

MI . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ;


<s> MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( getT1Imm8 ( insn ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { unsigned Option = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | <NUM_LIT> << <NUM_LIT> ; MI . addOperand ( MCOperand :: CreateImm ( Option ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> || OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) && <STR_LIT> ) ;

MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRd ( insn ) ) ) ) ;


<s> unsigned & OpIdx = NumOpsAdded ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ) ) ; MI . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; OpIdx = <NUM_LIT> ; unsigned RegListBits = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << ( Opcode == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) | slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;

for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) {


<s> MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ) ) ; MI . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; OpIdx = <NUM_LIT> ; unsigned RegListBits = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << ( Opcode == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) | slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( ( RegListBits >> i ) & <NUM_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , i ) ) ) ;


<s> assert ( slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; if ( ( <STR_LIT> <= Opcode && Opcode <= <STR_LIT> ) || ( <STR_LIT> <= Opcode && Opcode <= <STR_LIT> ) ) { return DisassembleThumb2LdStEx ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { return DisassembleThumb2LdStDual ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { return DisassembleThumb2TB ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } } else if ( slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { return DisassembleThumb2DPSoReg ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } break ; case <NUM_LIT> : if ( op == <NUM_LIT> ) { if ( slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) {

return DisassembleThumb2DPModImm ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ;


<s> if ( NumOps == <NUM_LIT> ) return true ; if ( t2MiscCtrlInstr ( insn ) ) return true ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : break ; } if ( Opcode == <STR_LIT> ) { unsigned Option = slice ( insn , <NUM_LIT> , <NUM_LIT> ) | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; MI . addOperand ( MCOperand :: CreateImm ( Option ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } int Offset = <NUM_LIT> ; switch ( Opcode ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; return false ; case <STR_LIT> : Offset = decodeImm32_B_EncodingT4 ( insn ) ; break ; case <STR_LIT> : Offset = decodeImm32_B_EncodingT3 ( insn ) ; break ; case <STR_LIT> : Offset = decodeImm32_BL ( insn ) ; break ; case <STR_LIT> : Offset = decodeImm32_BLX ( insn ) ; break ; } MI . addOperand ( MCOperand :: CreateImm ( Offset + <NUM_LIT> ) ) ; NumOpsAdded = <NUM_LIT> ; return true ;


<s> MI . addOperand ( MI . getOperand ( Idx ) ) ; } else { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; } ++ OpIdx ; } assert ( OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; ++ OpIdx ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) MI . addOperand ( MCOperand :: CreateImm ( getIImm3Imm8 ( insn ) ) ) ; else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) MI . addOperand ( MCOperand :: CreateImm ( getImm16 ( insn ) ) ) ; else if ( Opcode == <STR_LIT> ) MI . addOperand ( MCOperand :: CreateImm ( getBitfieldInvMask ( insn ) ) ) ; else { assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateImm ( getLsb ( insn ) ) ) ; if ( Opcode == <STR_LIT> ) { if ( getMsb ( insn ) < getLsb ( insn ) ) { DEBUG ( errs ( ) << <STR_LIT> ) ;


<s> unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; bool TwoReg = ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) ; bool NoDstReg = ( decodeRs ( insn ) == <NUM_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , NoDstReg ? decodeRn ( insn ) : decodeRs ( insn ) ) ) ) ; ++ OpIdx ; if ( TwoReg ) { assert ( ! NoDstReg && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; ++ OpIdx ; } assert ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; unsigned imm12 = getIImm3Imm8 ( insn ) ; MI . addOperand ( MCOperand :: CreateImm ( ThumbExpandImm ( imm12 ) ) ) ;


<s> ++ OpIdx ; if ( TwoReg ) { assert ( ! NoDstReg && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; ++ OpIdx ; } assert ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; unsigned imm12 = getIImm3Imm8 ( insn ) ;

MI . addOperand ( MCOperand :: CreateImm ( ThumbExpandImm ( imm12 ) ) ) ;


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; ++ OpIdx ; if ( ThreeReg ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; ++ OpIdx ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; ++ OpIdx ;

if ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) {


<s> ++ OpIdx ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; ++ OpIdx ; if ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) { MI . addOperand ( MCOperand :: CreateImm ( decodeRotate ( insn ) ) ) ; ++ OpIdx ; }


<s> } OpIdx = <NUM_LIT> ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; bool ThreeReg = ( NumOps > <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) ; bool NoDstReg = ( decodeRs ( insn ) == <NUM_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , NoDstReg ? decodeRn ( insn ) : decodeRs ( insn ) ) ) ) ; ++ OpIdx ; if ( ThreeReg ) { int Idx ; if ( ( Idx = TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) ) != - <NUM_LIT> ) { MI . addOperand ( MI . getOperand ( Idx ) ) ; } else { assert ( ! NoDstReg && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; } ++ OpIdx ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; ++ OpIdx ; if ( NumOps == OpIdx ) return true ; if ( OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) { if ( Thumb2ShiftOpcode ( Opcode ) ) MI . addOperand ( MCOperand :: CreateImm ( getShiftAmtBits ( insn ) ) ) ; else { unsigned bits2 = getShiftTypeBits ( insn ) ; unsigned imm5 = getShiftAmtBits ( insn ) ; <STR_LIT> ShOp = <STR_LIT> ; unsigned ShAmt = decodeImmShift ( bits2 , imm5 , ShOp ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) MI . addOperand ( MCOperand :: CreateImm ( ShAmt ) ) ; else MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( ShOp , ShAmt ) ) ) ; } ++ OpIdx ; } return true ;


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ;

assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && <STR_LIT> ) ;


<s> if ( Load && Rn == <NUM_LIT> ) return DisassembleThumb2Ldpci ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; const TargetInstrDesc & TID = <ISA_LIT>Insts [ Opcode ] ; const TargetOperandInfo * OpInfo = TID . OpInfo ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; bool ThreeReg = ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) ; bool TIED_TO = ThreeReg && TID . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> ; bool Imm12 = ! ThreeReg && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned R0 , R1 , R2 = <NUM_LIT> ; unsigned Rd = decodeRd ( insn ) ; int Imm = <NUM_LIT> ; if ( ! Load && TIED_TO ) { R0 = Rn ; R1 = Rd ; } else { R0 = Rd ; R1 = Rn ; } if ( ThreeReg ) { if ( TIED_TO ) { R2 = Rn ; Imm = decodeImm8 ( insn ) ; } else { R2 = decodeRm ( insn ) ; Imm = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; } } else { if ( Imm12 ) Imm = getImm12 ( insn ) ; else Imm = decodeImm8 ( insn ) ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R0 ) ) ) ; ++ OpIdx ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R1 ) ) ) ; ++ OpIdx ; if ( ThreeReg ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R2 ) ) ) ; ++ OpIdx ; } assert ( OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateImm ( Imm ) ) ; ++ OpIdx ;


<s> if ( TIED_TO ) { R2 = Rn ; Imm = decodeImm8 ( insn ) ; } else { R2 = decodeRm ( insn ) ; Imm = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; } } else { if ( Imm12 ) Imm = getImm12 ( insn ) ; else Imm = decodeImm8 ( insn ) ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R0 ) ) ) ; ++ OpIdx ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R1 ) ) ) ; ++ OpIdx ; if ( ThreeReg ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R2 ) ) ) ; ++ OpIdx ; } assert ( OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateImm ( Imm ) ) ;


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; int Offset = getImm8 ( insn ) * <NUM_LIT> ; if ( getUBit ( insn ) == <NUM_LIT> ) Offset = - Offset ; MI . addOperand ( MCOperand :: CreateImm ( Offset ) ) ; NumOpsAdded = <NUM_LIT> ;


<s> static bool DisassembleThumb2LdStMul ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { if ( Thumb2SRSOpcode ( Opcode ) ) return DisassembleThumb2SRS ( MI , Opcode , insn , NumOps , NumOpsAdded ) ; if ( Thumb2RFEOpcode ( Opcode ) ) return DisassembleThumb2RFE ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; unsigned Base = getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( Base ) ) ; ++ OpIdx ; } MI . addOperand ( MCOperand :: CreateReg ( Base ) ) ;


<s> if ( FourReg ) MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ;

MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ;


<s> bool FourReg = NumOps > <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; if ( FourReg ) MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; NumOpsAdded = FourReg ? <NUM_LIT> : <NUM_LIT> ;


<s> assert ( OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; int Offset = <NUM_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { bool Negative = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned Imm12 = getImm12 ( insn ) ; Offset = Negative ? - <NUM_LIT> - Imm12 : <NUM_LIT> * Imm12 ; } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Imm8 = getImm8 ( insn ) ; Offset = - <NUM_LIT> - Imm8 ; } else Offset = decodeImm12 ( insn ) ; MI . addOperand ( MCOperand :: CreateImm ( Offset ) ) ;


<s> uint32_t Val = <NUM_LIT> ; assert ( lsb <= msb && <STR_LIT> ) ;

for ( uint32_t i = lsb ; i <= msb ; ++ i ) Val |= ( <NUM_LIT> << i ) ;


<s> assert ( lsb <= msb && <STR_LIT> ) ; for ( uint32_t i = lsb ; i <= msb ; ++ i ) Val |= ( <NUM_LIT> << i ) ;


<s> static inline bool IsGPR ( unsigned RegClass ) { return RegClass == <STR_LIT> ;


<s> static inline bool Thumb2PreloadOpcode ( unsigned Opcode ) { switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> static inline bool Thumb2SaturateOpcode ( unsigned Opcode ) { switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return false ;


<s> NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( getT1Imm8 ( insn ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { unsigned Option = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | <NUM_LIT> << <NUM_LIT> ; MI . addOperand ( MCOperand :: CreateImm ( Option ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> || OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRd ( insn ) ) ) ) ; if ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRn ( insn ) ) ) ) ;


<s> return DisassembleThumb2LdStMul ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } assert ( slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; if ( ( <STR_LIT> <= Opcode && Opcode <= <STR_LIT> ) || ( <STR_LIT> <= Opcode && Opcode <= <STR_LIT> ) ) { return DisassembleThumb2LdStEx ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { return DisassembleThumb2LdStDual ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { return DisassembleThumb2TB ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } } else if ( slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { return DisassembleThumb2DPSoReg ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } break ; case <NUM_LIT> : if ( op == <NUM_LIT> ) { if ( slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) return DisassembleThumb2DPModImm ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; if ( Thumb2SaturateOpcode ( Opcode ) ) return DisassembleThumb2Sat ( MI , Opcode , insn , NumOpsAdded , B ) ; return DisassembleThumb2DPBinImm ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } return DisassembleThumb2BrMiscCtrl ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; case <NUM_LIT> : switch ( slice ( op2 , <NUM_LIT> , <NUM_LIT> ) ) { case <NUM_LIT> : if ( slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { if ( slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { return DisassembleThumb2LdSt ( false , MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } else { ; } } else { return DisassembleThumb2LdSt ( true , MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } break ; case <NUM_LIT> : if ( slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { return DisassembleThumb2DPReg ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } else if ( slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { return DisassembleThumb2Mul ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } else { return DisassembleThumb2LongMul ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } break ; default : ; break ; } break ; default : assert ( <NUM_LIT> && <STR_LIT> ) ;


<s> return true ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } int Offset = <NUM_LIT> ; switch ( Opcode ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; return false ; case <STR_LIT> : Offset = decodeImm32_B_EncodingT4 ( insn ) ; break ; case <STR_LIT> : Offset = decodeImm32_B_EncodingT3 ( insn ) ; break ; case <STR_LIT> : Offset = decodeImm32_BL ( insn ) ; break ; case <STR_LIT> : Offset = decodeImm32_BLX ( insn ) ; break ;


<s> unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; unsigned Base = getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( Base ) ) ; ++ OpIdx ; } MI . addOperand ( MCOperand :: CreateReg ( Base ) ) ; ++ OpIdx ; <STR_LIT> SubMode = getAMSubModeForBits ( getPUBits ( insn ) ) ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( SubMode ) ) ) ; ++ OpIdx ; if ( B -> DoPredicateOperands ( MI , Opcode , insn , NumOps ) ) OpIdx += <NUM_LIT> ;


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { bool Negative = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned Imm12 = getImm12 ( insn ) ; Offset = Negative ? - <NUM_LIT> - Imm12 : <NUM_LIT> * Imm12 ; } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Imm8 = getImm8 ( insn ) ; Offset = - <NUM_LIT> - Imm8 ; } else Offset = decodeImm12 ( insn ) ; MI . addOperand ( MCOperand :: CreateImm ( Offset ) ) ; } ++ OpIdx ;

if ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) {


<s> assert ( NumOps == <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && <STR_LIT> ) ; unsigned Imm11 = getT1Imm11 ( insn ) ; MI . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Imm11 << <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ;


<s> const TargetOperandInfo * OpInfo = TID . OpInfo ; unsigned & OpIdx = NumOpsAdded ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRn ( insn ) ) ) ) ; OpIdx = <NUM_LIT> ; assert ( OpIdx < NumOps && <STR_LIT> ) ; if ( OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) { assert ( opA != <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateImm ( getT1Imm5 ( insn ) ) ) ; ++ OpIdx ;


<s> if ( t2MiscCtrlInstr ( insn ) ) return true ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : break ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; NumOpsAdded = <NUM_LIT> ;


<s> const TargetOperandInfo * OpInfo = TID . OpInfo ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass > <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass > <NUM_LIT> && <STR_LIT> ) ; bool ThreeReg = NumOps > <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass > <NUM_LIT> ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , OpInfo [ OpIdx ] . RegClass , decodeRs ( insn ) ) ) ) ; ++ OpIdx ; if ( ThreeReg ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , OpInfo [ OpIdx ] . RegClass , decodeRn ( insn ) ) ) ) ; ++ OpIdx ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , OpInfo [ OpIdx ] . RegClass , decodeRm ( insn ) ) ) ) ; ++ OpIdx ; if ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) { MI . addOperand ( MCOperand :: CreateImm ( decodeRotate ( insn ) ) ) ; ++ OpIdx ;


<s> static bool DisassembleThumb2LdSt ( bool Load , MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { unsigned Rn = decodeRn ( insn ) ; if ( Thumb2PreloadOpcode ( Opcode ) ) return DisassembleThumb2PreLoad ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; if ( Load && Rn == <NUM_LIT> ) return DisassembleThumb2Ldpci ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; const TargetInstrDesc & TID = <ISA_LIT>Insts [ Opcode ] ; const TargetOperandInfo * OpInfo = TID . OpInfo ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; bool ThreeReg = ( OpInfo [ <NUM_LIT> ] . RegClass > <NUM_LIT> ) ; bool TIED_TO = ThreeReg && TID . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> ; bool Imm12 = ! ThreeReg && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned R0 , R1 , R2 = <NUM_LIT> ; unsigned Rd = decodeRd ( insn ) ; int Imm = <NUM_LIT> ; if ( ! Load && TIED_TO ) { R0 = Rn ; R1 = Rd ; } else { R0 = Rd ; R1 = Rn ; } if ( ThreeReg ) { if ( TIED_TO ) { R2 = Rn ; Imm = decodeImm8 ( insn ) ;


<s> unsigned RegClassBase = OpInfo [ <NUM_LIT> ] . RegClass ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassPair , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassPair , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassBase , decodeRn ( insn ) ) ) ) ; int Offset = getImm8 ( insn ) * <NUM_LIT> ; if ( getUBit ( insn ) == <NUM_LIT> ) Offset = - Offset ; MI . addOperand ( MCOperand :: CreateImm ( Offset ) ) ;


<s> assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass > <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == OpInfo [ <NUM_LIT> ] . RegClass && OpInfo [ <NUM_LIT> ] . RegClass > <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && <STR_LIT> ) ; unsigned RegClassPair = OpInfo [ <NUM_LIT> ] . RegClass ; unsigned RegClassBase = OpInfo [ <NUM_LIT> ] . RegClass ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassPair , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassPair , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassBase , decodeRn ( insn ) ) ) ) ;

int Offset = getImm8 ( insn ) * <NUM_LIT> ;


<s> OpIdx = <NUM_LIT> ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass > <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass > <NUM_LIT> && <STR_LIT> ) ; bool isStore = ( <STR_LIT> <= Opcode && Opcode <= <STR_LIT> ) ; bool isSW = ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; bool isDW = ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; if ( isStore ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , OpInfo [ OpIdx ] . RegClass , isSW ? decodeRs ( insn ) : decodeRm ( insn ) ) ) ) ; ++ OpIdx ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , OpInfo [ OpIdx ] . RegClass , decodeRd ( insn ) ) ) ) ; ++ OpIdx ; if ( isDW ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , OpInfo [ OpIdx ] . RegClass , decodeRs ( insn ) ) ) ) ; ++ OpIdx ;


<s> assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; NumOpsAdded = <NUM_LIT> ; unsigned Base = getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) {

MI . addOperand ( MCOperand :: CreateReg ( Base ) ) ;


<s> ++ OpIdx ; if ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; } else { assert ( OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; int Offset = <NUM_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Imm8 = getImm8 ( insn ) ; Offset = - <NUM_LIT> * Imm8 ; } else Offset = decodeImm12 ( insn ) ;

MI . addOperand ( MCOperand :: CreateImm ( Offset ) ) ;


<s> unsigned Imm8 = getImm8 ( insn ) ; Offset = - <NUM_LIT> * Imm8 ; } else Offset = decodeImm12 ( insn ) ; MI . addOperand ( MCOperand :: CreateImm ( Offset ) ) ; } ++ OpIdx ; if ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; ++ OpIdx ;


<s> bool Imm12 = ! ThreeReg && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned R0 , R1 , R2 = <NUM_LIT> ; unsigned Rd = decodeRd ( insn ) ; int Imm = <NUM_LIT> ; if ( ! Load && TIED_TO ) { R0 = Rn ; R1 = Rd ; } else { R0 = Rd ; R1 = Rn ; } if ( ThreeReg ) { if ( TIED_TO ) { R2 = Rn ; Imm = decodeImm8 ( insn ) ; } else { R2 = decodeRm ( insn ) ; Imm = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; } } else { if ( Imm12 ) Imm = getImm12 ( insn ) ;


<s> static bool DisassembleThumb2LdSt ( bool Load , MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { unsigned Rn = decodeRn ( insn ) ; if ( Thumb2PreloadOpcode ( Opcode ) ) return DisassembleThumb2PreLoad ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; const TargetInstrDesc & TID = <ISA_LIT>Insts [ Opcode ] ; const TargetOperandInfo * OpInfo = TID . OpInfo ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; bool ThreeReg = ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) ; bool TIED_TO = ThreeReg && TID . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> ; bool Imm12 = ! ThreeReg && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned R0 , R1 , R2 = <NUM_LIT> ; unsigned Rd = decodeRd ( insn ) ; int Imm = <NUM_LIT> ; if ( ! Load && TIED_TO ) { R0 = Rn ; R1 = Rd ; } else { R0 = Rd ; R1 = Rn ; } if ( ThreeReg ) { if ( TIED_TO ) { R2 = Rn ; Imm = decodeImm8 ( insn ) ; } else { R2 = decodeRm ( insn ) ; Imm = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; } } else { if ( Imm12 ) Imm = getImm12 ( insn ) ; else Imm = decodeImm8 ( insn ) ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R0 ) ) ) ; ++ OpIdx ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R1 ) ) ) ; ++ OpIdx ; if ( ThreeReg ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R2 ) ) ) ; ++ OpIdx ; } assert ( OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ;

MI . addOperand ( MCOperand :: CreateImm ( Imm ) ) ;


<s> static inline int decodeImm32_BL ( uint32_t insn ) { unsigned S = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; bool I1 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == S ; bool I2 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == S ; unsigned Imm25 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( S ) Imm25 |= <NUM_LIT> << <NUM_LIT> ;


<s> unsigned S = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; bool I1 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == S ; bool I2 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == S ; unsigned Imm25 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( S ) Imm25 |= <NUM_LIT> << <NUM_LIT> ; if ( I1 ) Imm25 |= <NUM_LIT> << <NUM_LIT> ;


<s> bool I2 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == S ; unsigned Imm25 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( S ) Imm25 |= <NUM_LIT> << <NUM_LIT> ; if ( I1 ) Imm25 |= <NUM_LIT> << <NUM_LIT> ; if ( I2 ) Imm25 |= <NUM_LIT> << <NUM_LIT> ;

return SignExtend32 < <NUM_LIT> > ( Imm25 ) ;


<s> bool S = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; bool J1 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; bool J2 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Imm21 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ;

if ( S ) Imm21 |= <NUM_LIT> << <NUM_LIT> ;


<s> unsigned Imm25 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( S ) Imm25 |= <NUM_LIT> << <NUM_LIT> ; if ( I1 ) Imm25 |= <NUM_LIT> << <NUM_LIT> ; if ( I2 ) Imm25 |= <NUM_LIT> << <NUM_LIT> ;


<s> return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ? Offset : - Offset ;


<s> static inline unsigned decodeRotate ( uint32_t insn ) {

unsigned rotate = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> return DisassembleThumb1LdStSP ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; case <NUM_LIT> : if ( op3 <= <NUM_LIT> ) { return DisassembleThumb1AddPCi ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } else { return DisassembleThumb1AddSPi ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } default : return DisassembleThumb1Misc ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } break ; case <NUM_LIT> : switch ( op2 ) { case <NUM_LIT> : if ( op3 <= <NUM_LIT> ) { return DisassembleThumb1StMul ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } else { return DisassembleThumb1LdMul ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } case <NUM_LIT> : return DisassembleThumb1CondBr ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; case <NUM_LIT> : return DisassembleThumb1Br ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; } break ;


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) ) && <STR_LIT> ) ;

MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRt ( insn ) ) ) ) ;


<s> static bool DisassembleThumb1Br ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO ) { const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps == <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && <STR_LIT> ) ; unsigned Imm11 = getT1Imm11 ( insn ) ; MI . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Imm11 << <NUM_LIT> ) + <NUM_LIT> ) ) ; NumOpsAdded = <NUM_LIT> ; return true ;


<s> assert ( NumOps == <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && OpInfo [ <NUM_LIT> ] . isPredicate ( ) && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; unsigned Imm8 = getT1Imm8 ( insn ) ; MI . addOperand ( MCOperand :: CreateImm ( Opcode == <STR_LIT> ? SignExtend32 < <NUM_LIT> > ( Imm8 << <NUM_LIT> ) + <NUM_LIT> : ( int ) Imm8 ) ) ; NumOpsAdded = <NUM_LIT> ; return true ;


<s> assert ( NumOps == <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && OpInfo [ <NUM_LIT> ] . isPredicate ( ) && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; unsigned Imm8 = getT1Imm8 ( insn ) ; MI . addOperand ( MCOperand :: CreateImm ( Opcode == <STR_LIT> ? SignExtend32 < <NUM_LIT> > ( Imm8 << <NUM_LIT> ) + <NUM_LIT> : ( int ) Imm8 ) ) ; NumOpsAdded = <NUM_LIT> ;


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRd ( insn ) ) ) ) ; ++ OpIdx ; if ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) { assert ( OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( B -> InITBlock ( ) ? <NUM_LIT> : <STR_LIT> ) ) ; ++ OpIdx ; }

assert ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass == <STR_LIT> && <STR_LIT> ) ;


<s> assert ( OpIdx < NumOps && <STR_LIT> ) ; if ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , UseRt ? getT1tRt ( insn ) : getT1tRn ( insn ) ) ) ) ; ++ OpIdx ; } if ( OpIdx == NumOps ) return true ; if ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRm ( insn ) ) ) ) ; } else { assert ( OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ;

MI . addOperand ( MCOperand :: CreateImm ( UseRt ? getT1Imm8 ( insn ) : ( Imm3 ? getT1Imm3 ( insn ) : getT1Imm5 ( insn ) ) ) ) ;


<s> return DisassembleThumb1LdStMul ( true , MI , Opcode , insn , NumOps , NumOpsAdded , B ) ;


<s> static bool DisassembleThumb1LdPC ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) ) && <STR_LIT> ) ;


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRt ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( getT1Imm8 ( insn ) << <NUM_LIT> ) ) ;


<s> assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRn ( insn ) ) ) ) ; OpIdx = <NUM_LIT> ; assert ( OpIdx < NumOps && <STR_LIT> ) ;

if ( OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) {


<s> static bool DisassembleThumb1LdStMul ( bool Ld , MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; unsigned tRt = getT1tRt ( insn ) ; NumOpsAdded = <NUM_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , tRt ) ) ) ; ++ NumOpsAdded ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , tRt ) ) ) ; ++ NumOpsAdded ; if ( B -> DoPredicateOperands ( MI , Opcode , insn , NumOps ) ) {


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ;

assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) ) && <STR_LIT> ) ;


<s> NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( getT1Imm8 ( insn ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> + slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> || OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRd ( insn ) ) ) ) ; if ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRn ( insn ) ) ) ) ; } else { assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ;

MI . addOperand ( MCOperand :: CreateImm ( getT1Imm6 ( insn ) * <NUM_LIT> ) ) ;


<s> static bool DisassembleThumb1PushPop ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; unsigned & OpIdx = NumOpsAdded ; if ( B -> DoPredicateOperands ( MI , Opcode , insn , NumOps ) ) OpIdx += <NUM_LIT> ; else { DEBUG ( errs ( ) << <STR_LIT> ) ; return false ; } unsigned RegListBits = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << ( Opcode == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) | slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( ( RegListBits >> i ) & <NUM_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , i ) ) ) ;


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1Rm ( insn ) ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } const TargetInstrDesc & TID = <ISA_LIT>Insts [ Opcode ] ; const TargetOperandInfo * OpInfo = TID . OpInfo ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; unsigned RegClass = OpInfo [ OpIdx ] . RegClass ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClass , IsGPR ( RegClass ) ? getT1Rd ( insn ) : getT1tRd ( insn ) ) ) ) ; ++ OpIdx ; assert ( OpIdx < NumOps && <STR_LIT> ) ; int Idx ; if ( ( Idx = TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) ) != - <NUM_LIT> ) { MI . addOperand ( MI . getOperand ( Idx ) ) ; ++ OpIdx ; }


<s> static bool DisassembleThumb1StMul ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { return DisassembleThumb1LdStMul ( false , MI , Opcode , insn , NumOps , NumOpsAdded , B ) ;


<s> return DisassembleThumb1LdStMul ( false , MI , Opcode , insn , NumOps , NumOpsAdded , B ) ;


<s> if ( slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { return DisassembleThumb2LdStMul ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } assert ( slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; if ( ( <STR_LIT> <= Opcode && Opcode <= <STR_LIT> ) || ( <STR_LIT> <= Opcode && Opcode <= <STR_LIT> ) ) { return DisassembleThumb2LdStEx ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { return DisassembleThumb2LdStDual ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { return DisassembleThumb2TB ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } } else if ( slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { return DisassembleThumb2DPSoReg ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } break ; case <NUM_LIT> : if ( op == <NUM_LIT> ) { if ( slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) return DisassembleThumb2DPModImm ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; if ( Thumb2SaturateOpcode ( Opcode ) ) return DisassembleThumb2Sat ( MI , Opcode , insn , NumOpsAdded , B ) ; return DisassembleThumb2DPBinImm ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } return DisassembleThumb2BrMiscCtrl ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; case <NUM_LIT> : switch ( slice ( op2 , <NUM_LIT> , <NUM_LIT> ) ) { case <NUM_LIT> : if ( slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { if ( slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { return DisassembleThumb2LdSt ( false , MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } else { ; } } else { return DisassembleThumb2LdSt ( true , MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } break ; case <NUM_LIT> : if ( slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { return DisassembleThumb2DPReg ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } else if ( slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { return DisassembleThumb2Mul ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } else { return DisassembleThumb2LongMul ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } break ; default : ; break ; } break ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; break ;


<s> MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ;


<s> OpIdx = <NUM_LIT> ; unsigned RdRegClassID = OpInfo [ <NUM_LIT> ] . RegClass ; assert ( NumOps >= <NUM_LIT> && ( RdRegClassID == <STR_LIT> || RdRegClassID == <STR_LIT> ) && <STR_LIT> ) ; unsigned RnRegClassID = OpInfo [ <NUM_LIT> ] . RegClass ; bool TwoReg = ( RnRegClassID == <STR_LIT> || RnRegClassID == <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RdRegClassID , decodeRs ( insn ) ) ) ) ; ++ OpIdx ; if ( TwoReg ) { assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; int Idx ; if ( ( Idx = TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) ) != - <NUM_LIT> ) { MI . addOperand ( MI . getOperand ( Idx ) ) ; } else {

MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RnRegClassID , decodeRn ( insn ) ) ) ) ;


<s> unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; unsigned RdRegClassID = OpInfo [ <NUM_LIT> ] . RegClass ; assert ( NumOps >= <NUM_LIT> && ( RdRegClassID == <STR_LIT> || RdRegClassID == <STR_LIT> ) && <STR_LIT> ) ; unsigned RnRegClassID = OpInfo [ <NUM_LIT> ] . RegClass ; bool TwoReg = ( RnRegClassID == <STR_LIT> || RnRegClassID == <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RdRegClassID , decodeRs ( insn ) ) ) ) ; ++ OpIdx ; if ( TwoReg ) { assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; int Idx ; if ( ( Idx = TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) ) != - <NUM_LIT> ) { MI . addOperand ( MI . getOperand ( Idx ) ) ; } else { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RnRegClassID , decodeRn ( insn ) ) ) ) ; } ++ OpIdx ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RnRegClassID , decodeRn ( insn ) ) ) ) ; ++ OpIdx ; } assert ( OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; ++ OpIdx ;

if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) MI . addOperand ( MCOperand :: CreateImm ( getIImm3Imm8 ( insn ) ) ) ;


<s> const TargetInstrDesc & TID = <ISA_LIT>Insts [ Opcode ] ; const TargetOperandInfo * OpInfo = TID . OpInfo ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; bool ThreeReg = NumOps > <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; ++ OpIdx ; if ( ThreeReg ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; ++ OpIdx ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; ++ OpIdx ; if ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) { MI . addOperand ( MCOperand :: CreateImm ( decodeRotate ( insn ) ) ) ; ++ OpIdx ; } return true ;


<s> MI . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; MI . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; MI . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } OpIdx = <NUM_LIT> ; assert ( NumOps >= <NUM_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> || OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) && ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> || OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) && <STR_LIT> ) ; bool ThreeReg = ( NumOps > <NUM_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> || OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) ) ; bool NoDstReg = ( decodeRs ( insn ) == <NUM_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , OpInfo [ <NUM_LIT> ] . RegClass , NoDstReg ? decodeRn ( insn ) : decodeRs ( insn ) ) ) ) ; ++ OpIdx ; if ( ThreeReg ) { int Idx ; if ( ( Idx = TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) ) != - <NUM_LIT> ) { MI . addOperand ( MI . getOperand ( Idx ) ) ; ++ OpIdx ; } else if ( ! NoDstReg ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , OpInfo [ <NUM_LIT> ] . RegClass , decodeRn ( insn ) ) ) ) ; ++ OpIdx ; } else { DEBUG ( errs ( ) << <STR_LIT> ) ; return false ; } } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , OpInfo [ OpIdx ] . RegClass , decodeRm ( insn ) ) ) ) ; ++ OpIdx ; if ( NumOps == OpIdx ) return true ; if ( OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) { if ( Thumb2ShiftOpcode ( Opcode ) ) MI . addOperand ( MCOperand :: CreateImm ( getShiftAmtBits ( insn ) ) ) ; else {

unsigned bits2 = getShiftTypeBits ( insn ) ;


<s> if ( ThreeReg ) { int Idx ; if ( ( Idx = TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) ) != - <NUM_LIT> ) { MI . addOperand ( MI . getOperand ( Idx ) ) ; ++ OpIdx ; } else if ( ! NoDstReg ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , OpInfo [ <NUM_LIT> ] . RegClass , decodeRn ( insn ) ) ) ) ; ++ OpIdx ; } else { DEBUG ( errs ( ) << <STR_LIT> ) ; return false ; } } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , OpInfo [ OpIdx ] . RegClass , decodeRm ( insn ) ) ) ) ; ++ OpIdx ; if ( NumOps == OpIdx ) return true ; if ( OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) { if ( Thumb2ShiftOpcode ( Opcode ) ) MI . addOperand ( MCOperand :: CreateImm ( getShiftAmtBits ( insn ) ) ) ; else { unsigned bits2 = getShiftTypeBits ( insn ) ; unsigned imm5 = getShiftAmtBits ( insn ) ; <STR_LIT> ShOp = <STR_LIT> ; unsigned ShAmt = decodeImmShift ( bits2 , imm5 , ShOp ) ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( ShOp , ShAmt ) ) ) ;


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( decodeImm12 ( insn ) ) ) ;


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( decodeImm12 ( insn ) ) ) ;


<s> if ( Thumb2PreloadOpcode ( Opcode ) ) return DisassembleThumb2PreLoad ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; if ( Load && Rn == <NUM_LIT> ) return DisassembleThumb2Ldpci ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; const TargetInstrDesc & TID = <ISA_LIT>Insts [ Opcode ] ; const TargetOperandInfo * OpInfo = TID . OpInfo ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; bool ThreeReg = ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) ; bool TIED_TO = ThreeReg && TID . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> ; bool Imm12 = ! ThreeReg && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned R0 , R1 , R2 = <NUM_LIT> ; unsigned Rd = decodeRd ( insn ) ; int Imm = <NUM_LIT> ; if ( ! Load && TIED_TO ) { R0 = Rn ; R1 = Rd ; } else { R0 = Rd ; R1 = Rn ; } if ( ThreeReg ) { if ( TIED_TO ) { R2 = Rn ; Imm = decodeImm8 ( insn ) ; } else { R2 = decodeRm ( insn ) ; Imm = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; } } else { if ( Imm12 ) Imm = getImm12 ( insn ) ; else Imm = decodeImm8 ( insn ) ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R0 ) ) ) ;


<s> bool ThreeReg = ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) ; bool TIED_TO = ThreeReg && TID . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> ; bool Imm12 = ! ThreeReg && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned R0 , R1 , R2 = <NUM_LIT> ; unsigned Rd = decodeRd ( insn ) ; int Imm = <NUM_LIT> ; if ( ! Load && TIED_TO ) { R0 = Rn ; R1 = Rd ; } else { R0 = Rd ; R1 = Rn ; } if ( ThreeReg ) { if ( TIED_TO ) { R2 = Rn ; Imm = decodeImm8 ( insn ) ; } else { R2 = decodeRm ( insn ) ; Imm = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; } } else { if ( Imm12 ) Imm = getImm12 ( insn ) ; else Imm = decodeImm8 ( insn ) ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R0 ) ) ) ; ++ OpIdx ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R1 ) ) ) ; ++ OpIdx ;


<s> assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; int Offset = getImm8 ( insn ) * <NUM_LIT> ; if ( getUBit ( insn ) == <NUM_LIT> ) Offset = - Offset ; MI . addOperand ( MCOperand :: CreateImm ( Offset ) ) ;


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; int Offset = getImm8 ( insn ) * <NUM_LIT> ; if ( getUBit ( insn ) == <NUM_LIT> ) Offset = - Offset ; MI . addOperand ( MCOperand :: CreateImm ( Offset ) ) ; NumOpsAdded = <NUM_LIT> ; return true ;


<s> assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; NumOpsAdded = <NUM_LIT> ; unsigned Base = getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) {


<s> static bool DisassembleThumb2LdStMul ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { if ( Thumb2SRSOpcode ( Opcode ) ) return DisassembleThumb2SRS ( MI , Opcode , insn , NumOps , NumOpsAdded ) ; if ( Thumb2RFEOpcode ( Opcode ) ) return DisassembleThumb2RFE ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; NumOpsAdded = <NUM_LIT> ; unsigned Base = getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( Base ) ) ;


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; bool FourReg = NumOps > <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ; if ( FourReg ) MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; if ( FourReg ) NumOpsAdded = <NUM_LIT> ; else NumOpsAdded = <NUM_LIT> ; return true ;


<s> if ( FourReg ) MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; if ( FourReg ) NumOpsAdded = <NUM_LIT> ;


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ;

if ( FourReg ) MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ;


<s> assert ( OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; int Offset = <NUM_LIT> ; if ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { bool Negative = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned Imm12 = getImm12 ( insn ) ; Offset = Negative ? - <NUM_LIT> - Imm12 : <NUM_LIT> * Imm12 ; } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Imm8 = getImm8 ( insn ) ; Offset = - <NUM_LIT> - Imm8 ;


<s> static bool DisassembleThumb2RFE ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ;


<s> <STR_LIT> Opc = ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; unsigned ShAmt = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ShAmt == <NUM_LIT> ) { if ( Opc == <STR_LIT> ) ShAmt = <NUM_LIT> ; else Opc = <STR_LIT> ; } MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( Opc , ShAmt ) ) ) ; }


<s> assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ;

MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ;


<s> static bool DisassembleThumbFrm ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO Builder ) { uint16_t HalfWord = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( HalfWord == <NUM_LIT> ) { uint16_t op = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;

return DisassembleThumb1 ( op , MI , Opcode , insn , NumOps , NumOpsAdded , Builder ) ;


<s> } for ( uint32_t i = lsb ; i <= msb ; ++ i ) Val |= ( <NUM_LIT> << i ) ;


<s> return slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | getImm3 ( insn ) << <NUM_LIT> | getImm8 ( insn ) ;


<s> static inline unsigned getIImm3Imm8 ( uint32_t insn ) {

return slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | getImm3 ( insn ) << <NUM_LIT> | getImm8 ( insn ) ;


<s> return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> static inline unsigned getImm16 ( uint32_t insn ) { return getImm4 ( insn ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | getImm3 ( insn ) << <NUM_LIT> | getImm8 ( insn ) ;


<s> static inline unsigned getImm2 ( uint32_t insn ) { return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> static inline unsigned getImm3 ( uint32_t insn ) {

return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> static inline unsigned getImm4 ( uint32_t insn ) { return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> static inline unsigned getImm4 ( uint32_t insn ) {


<s> static inline unsigned getMsb ( uint32_t insn ) { return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> static inline unsigned getShiftAmtBits ( uint32_t insn ) { return getImm3 ( insn ) << <NUM_LIT> | getImm2 ( insn ) ;


<s> static inline unsigned getT1Imm3 ( uint32_t insn ) {


<s> static inline unsigned getT1Imm5 ( uint32_t insn ) {


<s> static inline unsigned getT1Imm6 ( uint32_t insn ) {

return slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> return slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> static inline unsigned getT1Imm8 ( uint32_t insn ) { return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> static inline unsigned getT1Rd ( uint32_t insn ) { return slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> static inline unsigned getT1Rd ( uint32_t insn ) {


<s> static inline unsigned getT1Rm ( uint32_t insn ) { return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> static inline unsigned getT1tRd ( uint32_t insn ) {


<s> static inline unsigned getT1tRm ( uint32_t insn ) { return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> static inline unsigned getT1tRm ( uint32_t insn ) {


<s> static inline unsigned getT1tRn ( uint32_t insn ) {


<s> return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> static inline unsigned getWidthMinus1 ( uint32_t insn ) { return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> static inline bool IsGPR ( unsigned RegClass ) {

return RegClass == <STR_LIT> || RegClass == <STR_LIT> ;


<s> return RegClass == <STR_LIT> || RegClass == <STR_LIT> ;


<s> static inline bool t2MiscCtrlInstr ( uint32_t insn ) { if ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) return true ; return false ;


<s> if ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) return true ;


<s> switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ;


<s> default : return false ; case <STR_LIT> : case <STR_LIT> :


<s> switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default :


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> return false ; case <STR_LIT> : case <STR_LIT> :