<s> unsigned ObjSize = VA . getLocVT ( ) . getStoreSize ( ) ; int FI = MFI . CreateFixedObject ( ObjSize , Offset , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , OutVals [ i ] , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ) ; } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOpChains ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; if ( ! VA . isRegLoc ( ) ) continue ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ;


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FVal = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ;

<STR_LIT> ArcCC = ISDCCto<ISA_LIT>CC ( CC ) ;


<s> SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned Width = cast < VTSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getVT ( ) . getSizeInBits ( ) ; if ( Width == <NUM_LIT> || Width == <NUM_LIT> ) return Op ; if ( Width >= <NUM_LIT> ) { return { } ; } SDValue LS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 , DAG . getConstant ( <NUM_LIT> - Width , dl , <STR_LIT> ) ) ; SDValue SR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LS , DAG . getConstant ( <NUM_LIT> - Width , dl , <STR_LIT> ) ) ;


<s> assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned Width = cast < VTSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getVT ( ) . getSizeInBits ( ) ; if ( Width == <NUM_LIT> || Width == <NUM_LIT> ) return Op ; if ( Width >= <NUM_LIT> ) { return { } ;


<s> SDLoc dl ( Op ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ;

const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const {


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { return false ;


<s> SDValue <ISA_LIT>TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { return { } ;


<s> SDValue <ISA_LIT>TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const {


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : ReturnStackOffsetSet ( false ) , VarArgsFrameIndex ( <NUM_LIT> ) , ReturnStackOffset ( - <NUM_LIT> ) , MaxCallStackReq ( <NUM_LIT> ) { MF . setAlignment ( <NUM_LIT> ) ;


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : ReturnStackOffsetSet ( false ) , VarArgsFrameIndex ( <NUM_LIT> ) , ReturnStackOffset ( - <NUM_LIT> ) , MaxCallStackReq ( <NUM_LIT> ) {


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : ReturnStackOffsetSet ( false ) , VarArgsFrameIndex ( <NUM_LIT> ) , ReturnStackOffset ( - <NUM_LIT> ) , MaxCallStackReq ( <NUM_LIT> ) { MF . setAlignment ( Align ( <NUM_LIT> ) ) ;


<s> void <ISA_LIT>FunctionInfo :: anchor ( ) {


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : ReturnStackOffsetSet ( false ) , VarArgsFrameIndex ( <NUM_LIT> ) , VarArgFrameBytes ( <NUM_LIT> ) , ReturnStackOffset ( - <NUM_LIT> ) , MaxCallStackReq ( <NUM_LIT> ) {


<s> int getVarArgsFrameIndex ( ) const { return VarArgsFrameIndex ;


<s> void setReturnStackOffset ( unsigned value ) { assert ( ! ReturnStackOffsetSet && <STR_LIT> ) ; ReturnStackOffset = value ;


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = nullptr ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ;


<s> AllowAtInName = true ; HiddenVisibilityAttr = MCSA_Invalid ; HiddenDeclarationVisibilityAttr = MCSA_Invalid ; ProtectedVisibilityAttr = MCSA_Invalid ; ExceptionsType = ExceptionHandling :: DwarfCFI ;


<s> for ( const MachineOperand & MO : MI -> operands ( ) ) { MCOperand MCOp = LowerOperand ( MO ) ; if ( MCOp . isValid ( ) ) OutMI . addOperand ( MCOp ) ; }


<s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( MCContext * C , AsmPrinter & AsmPrinter ) : Ctx ( C ) , Printer ( AsmPrinter ) {


<s> void <ISA_LIT>MCInstLower :: Lower ( const MachineInstr * MI , MCInst & OutMI ) const {

OutMI . setOpcode ( MI -> getOpcode ( ) ) ;


<s> OutMI . setOpcode ( MI -> getOpcode ( ) ) ;

for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) {


<s> if ( MO . isImplicit ( ) ) break ; return MCOperand :: createReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) + Offset ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_BlockAddress : return LowerSymbolOperand ( MO , MOTy , Offset ) ; case MachineOperand :: MO_RegisterMask :


<s> switch ( MOTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) break ; return MCOperand :: createReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) + Offset ) ;

case MachineOperand :: MO_MachineBasicBlock :


<s> case MachineOperand :: MO_GlobalAddress : Symbol = Printer . getSymbol ( MO . getGlobal ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_BlockAddress : Symbol = Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_ExternalSymbol : Symbol = Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_JumpTableIndex : Symbol = Printer . GetJTISymbol ( MO . getIndex ( ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : Symbol = Printer . GetCPISymbol ( MO . getIndex ( ) ) ; Offset += MO . getOffset ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } assert ( Symbol && <STR_LIT> ) ;

const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: create ( Symbol , Kind , * Ctx ) ;


<s> MCCFIInstruction Inst = MCCFIInstruction :: cfiDefCfa ( nullptr , <STR_LIT> , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI ;


<s> Target & The<ISA_LIT>Target = getThe<ISA_LIT>Target ( ) ; RegisterMCAsmInfoFn X ( The<ISA_LIT>Target , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ;

TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ;


<s> auto * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X ;


<s> MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ;

MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , <STR_LIT> , <NUM_LIT> ) ;


<s> <ISA_LIT>TargetStreamer :: <ISA_LIT>TargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) {


<s> MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , <STR_LIT> , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI ;


<s> MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , <STR_LIT> , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) {

return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;


Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ;


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , FS ) ;


<s> static MCTargetStreamer * createTargetAsmStreamer ( MCStreamer & S , formatted_raw_ostream & OS , MCInstPrinter * InstPrint , bool isVerboseAsm ) { return new <ISA_LIT>TargetStreamer ( S ) ;


<s> TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ;

TargetRegistry :: RegisterAsmTargetStreamer ( The<ISA_LIT>Target , createTargetAsmStreamer ) ;


<s> RegisterMCAsmInfoFn X ( The<ISA_LIT>Target , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ;


<s> if ( IsStore ) { Src = Ldst . getOperand ( BasePos - <NUM_LIT> ) ; Ldst . RemoveOperand ( BasePos - <NUM_LIT> ) ; } Ldst . setDesc ( AST -> getInstrInfo ( ) -> get ( NewOpcode ) ) ; Ldst . addOperand ( MachineOperand :: CreateReg ( NewBase , true ) ) ; if ( IsStore ) Ldst . addOperand ( Src ) ; Ldst . addOperand ( MachineOperand :: CreateReg ( BaseReg , false ) ) ;


<s> Register BaseReg = Ldst . getOperand ( BasePos ) . getReg ( ) ; Ldst . RemoveOperand ( OffPos ) ; Ldst . RemoveOperand ( BasePos ) ; if ( IsStore ) { Src = Ldst . getOperand ( BasePos - <NUM_LIT> ) ; Ldst . RemoveOperand ( BasePos - <NUM_LIT> ) ; } Ldst . setDesc ( AST -> getInstrInfo ( ) -> get ( NewOpcode ) ) ; Ldst . addOperand ( MachineOperand :: CreateReg ( NewBase , true ) ) ; if ( IsStore ) Ldst . addOperand ( Src ) ; Ldst . addOperand ( MachineOperand :: CreateReg ( BaseReg , false ) ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } if ( Offset . getImm ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } for ( auto & Add : MRI -> use_nodbg_instructions ( B ) ) { int64_t Incr ; if ( ! isAddConstantOp ( Add , Incr ) ) continue ; if ( ! isValidLoadStoreOffset ( Incr ) ) continue ; SmallVector < MachineInstr * , <NUM_LIT> > Uses ; MachineInstr * MoveTo = canJoinInstructions ( & Ldst , & Add , & Uses ) ; if ( ! MoveTo ) continue ; if ( ! canFixPastUses ( Uses , Add . getOperand ( <NUM_LIT> ) , B ) ) continue ; LLVM_DEBUG ( MachineInstr * First = & Ldst ; MachineInstr * Last = & Add ; if ( MDT -> dominates ( Last , First ) ) std :: swap ( First , Last ) ; dbgs ( ) << <STR_LIT> << * First << <STR_LIT> << * Last << <STR_LIT> ; ) ; MachineInstr * Result = Ldst . getNextNode ( ) ; if ( MoveTo == & Add ) {


<s> Register B = Base . getReg ( ) ; if ( Register :: isStackSlot ( B ) || ! Register :: isVirtualRegister ( B ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } if ( Offset . getImm ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } for ( auto & Add : MRI -> use_nodbg_instructions ( B ) ) { int64_t Incr ; if ( ! isAddConstantOp ( Add , Incr ) ) continue ; if ( ! isValidLoadStoreOffset ( Incr ) ) continue ; SmallVector < MachineInstr * , <NUM_LIT> > Uses ; MachineInstr * MoveTo = canJoinInstructions ( & Ldst , & Add , & Uses ) ; if ( ! MoveTo ) continue ; if ( ! canFixPastUses ( Uses , Add . getOperand ( <NUM_LIT> ) , B ) ) continue ; LLVM_DEBUG ( MachineInstr * First = & Ldst ; MachineInstr * Last = & Add ; if ( MDT -> dominates ( Last , First ) ) std :: swap ( First , Last ) ;

dbgs ( ) << <STR_LIT> << * First << <STR_LIT> << * Last << <STR_LIT> ;


<s> return nullptr ; } } SmallVector < MachineInstr * , <NUM_LIT> > UsesAfterLdst ; SmallVector < MachineInstr * , <NUM_LIT> > UsesAfterAdd ; for ( MachineInstr & MI : MRI -> use_nodbg_instructions ( BaseReg ) ) { if ( & MI == Ldst || & MI == Add ) continue ; if ( & MI != Add && MDT -> dominates ( Ldst , & MI ) ) UsesAfterLdst . push_back ( & MI ) ; else if ( ! MDT -> dominates ( & MI , Ldst ) ) return nullptr ; if ( MDT -> dominates ( Add , & MI ) ) UsesAfterAdd . push_back ( & MI ) ; } MachineInstr * Result = nullptr ; if ( First == Add ) { if ( noUseOfAddBeforeLoadOrStore ( First , Last ) ) { Result = Last ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else if ( canHoistLoadStoreTo ( Ldst , Add ) ) { Result = First ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } } else {


<s> MachineInstr * First = Add ; MachineInstr * Last = Ldst ; if ( MDT -> dominates ( Ldst , Add ) ) std :: swap ( First , Last ) ; else if ( ! MDT -> dominates ( Add , Ldst ) ) return nullptr ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * First << * Last ) ; unsigned BasePos , OffPos ; if ( ! AII -> getBaseAndOffsetPosition ( * Ldst , BasePos , OffPos ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } Register BaseReg = Ldst -> getOperand ( BasePos ) . getReg ( ) ; if ( Ldst -> mayStore ( ) && Ldst -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { Register StReg = Ldst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Add -> getOperand ( <NUM_LIT> ) . getReg ( ) == StReg || BaseReg == StReg ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } } SmallVector < MachineInstr * , <NUM_LIT> > UsesAfterLdst ; SmallVector < MachineInstr * , <NUM_LIT> > UsesAfterAdd ; for ( MachineInstr & MI : MRI -> use_nodbg_instructions ( BaseReg ) ) { if ( & MI == Ldst || & MI == Add ) continue ; if ( & MI != Add && MDT -> dominates ( Ldst , & MI ) ) UsesAfterLdst . push_back ( & MI ) ; else if ( ! MDT -> dominates ( & MI , Ldst ) ) return nullptr ; if ( MDT -> dominates ( Add , & MI ) ) UsesAfterAdd . push_back ( & MI ) ; } MachineInstr * Result = nullptr ; if ( First == Add ) {

if ( noUseOfAddBeforeLoadOrStore ( First , Last ) ) {


<s> Ldst . setDesc ( AST -> getInstrInfo ( ) -> get ( NewOpcode ) ) ; Ldst . addOperand ( MachineOperand :: CreateReg ( NewBase , true ) ) ; if ( IsStore ) Ldst . addOperand ( Src ) ; Ldst . addOperand ( MachineOperand :: CreateReg ( BaseReg , false ) ) ; Ldst . addOperand ( NewOffset ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Ldst ) ;


<s> MachineBasicBlock * MBB = User -> getOperand ( BBOperandIdx ) . getMBB ( ) ; if ( MBB -> empty ( ) ) { const MachineBasicBlock * InstBB = MI -> getParent ( ) ; assert ( InstBB != MBB && <STR_LIT> ) ; if ( ! MDT -> dominates ( InstBB , MBB ) ) return false ; continue ; }


<s> bool <ISA_LIT>OptAddrMode :: noUseOfAddBeforeLoadOrStore ( const MachineInstr * Add , const MachineInstr * Ldst ) { Register R = Add -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return dominatesAllUsesOf ( Ldst , R , MDT , MRI ) ;


<s> AII = AST -> getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; bool Changed = false ; for ( auto & MBB : MF ) Changed |= processBasicBlock ( MBB ) ; if ( DUMP_AFTER ( ) ) MF . dump ( ) ; if ( VIEW_AFTER ( ) ) MF . viewCFG ( ) ;


<s> for ( auto & MBB : MF ) Changed |= processBasicBlock ( MBB ) ; if ( DUMP_AFTER ( ) ) MF . dump ( ) ; if ( VIEW_AFTER ( ) ) MF . viewCFG ( ) ;


<s> } MachineOperand & Base = Ldst . getOperand ( BasePos ) ; MachineOperand & Offset = Ldst . getOperand ( OffsetPos ) ; assert ( Base . isReg ( ) && <STR_LIT> ) ; if ( ! Offset . isImm ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } Register B = Base . getReg ( ) ; if ( Register :: isStackSlot ( B ) || ! Register :: isVirtualRegister ( B ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } if ( Offset . getImm ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } for ( auto & Add : MRI -> use_nodbg_instructions ( B ) ) { int64_t Incr ; if ( ! isAddConstantOp ( Add , Incr ) ) continue ; if ( ! isValidLoadStoreOffset ( Incr ) ) continue ; SmallVector < MachineInstr * , <NUM_LIT> > Uses ; MachineInstr * MoveTo = canJoinInstructions ( & Ldst , & Add , & Uses ) ; if ( ! MoveTo ) continue ; if ( ! canFixPastUses ( Uses , Add . getOperand ( <NUM_LIT> ) , B ) ) continue ; LLVM_DEBUG ( MachineInstr * First = & Ldst ; MachineInstr * Last = & Add ; if ( MDT -> dominates ( Last , First ) ) std :: swap ( First , Last ) ; dbgs ( ) << <STR_LIT> << * First << <STR_LIT> << * Last << <STR_LIT> ;


<s> assert ( Base . isReg ( ) && <STR_LIT> ) ; if ( ! Offset . isImm ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } Register B = Base . getReg ( ) ; if ( Register :: isStackSlot ( B ) || ! Register :: isVirtualRegister ( B ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } if ( Offset . getImm ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } for ( auto & Add : MRI -> use_nodbg_instructions ( B ) ) { int64_t Incr ; if ( ! isAddConstantOp ( Add , Incr ) ) continue ; if ( ! isValidLoadStoreOffset ( Incr ) ) continue ; SmallVector < MachineInstr * , <NUM_LIT> > Uses ; MachineInstr * MoveTo = canJoinInstructions ( & Ldst , & Add , & Uses ) ; if ( ! MoveTo ) continue ; if ( ! canFixPastUses ( Uses , Add . getOperand ( <NUM_LIT> ) , B ) ) continue ; LLVM_DEBUG ( MachineInstr * First = & Ldst ; MachineInstr * Last = & Add ; if ( MDT -> dominates ( Last , First ) ) std :: swap ( First , Last ) ; dbgs ( ) << <STR_LIT> << * First << <STR_LIT> << * Last << <STR_LIT> ; ) ; MachineInstr * Result = Ldst . getNextNode ( ) ; if ( MoveTo == & Add ) { Ldst . removeFromParent ( ) ; Add . getParent ( ) -> insertAfter ( Add . getIterator ( ) , & Ldst ) ; } if ( Result == & Add ) Result = Result -> getNextNode ( ) ; fixPastUses ( Uses , B , Incr ) ;

int NewOpcode = <STR_LIT> ( Ldst . getOpcode ( ) ) ;


<s> unsigned ValReg = IsLoad ? Ldst -> getOperand ( <NUM_LIT> ) . getReg ( ) : <NUM_LIT> ; for ( ; MI != ME && MI != End ; ++ MI ) { if ( MI -> isDebugValue ( ) ) continue ; if ( MI -> mayStore ( ) || MI -> isCall ( ) || MI -> isInlineAsm ( ) || MI -> hasUnmodeledSideEffects ( ) ) return false ; if ( IsStore && MI -> mayLoad ( ) ) return false ; if ( ValReg && MI -> readsVirtualRegister ( ValReg ) ) return false ; }


<s> Sign = - <NUM_LIT> ; case <STR_LIT> : assert ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; Amount = Sign * MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ;


<s> <ISA_LIT>OptAddrMode ( ) : MachineFunctionPass ( ID ) {


<s> int64_t Dummy ; if ( isAddConstantOp ( * MI , Dummy ) ) { if ( isValidIncrementOffset ( Dummy + NewOffset ) ) continue ; return false ; } if ( isLoadStoreThatCanHandleDisplacement ( AII , * MI , - NewOffset ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << - NewOffset << <STR_LIT> << * MI ) ; return false ;


<s> MachineBasicBlock :: const_iterator MI ( To ) , ME ( Ldst ) , End ( Ldst -> getParent ( ) -> end ( ) ) ; bool IsStore = Ldst -> mayStore ( ) ; for ( ; MI != ME && MI != End ; ++ MI ) { if ( MI -> isDebugValue ( ) ) continue ; if ( MI -> mayStore ( ) || MI -> isCall ( ) || MI -> isInlineAsm ( ) || MI -> hasUnmodeledSideEffects ( ) ) return false ; if ( IsStore && MI -> mayLoad ( ) ) return false ; } for ( auto & O : Ldst -> explicit_operands ( ) ) { if ( ! O . isReg ( ) || ! O . isUse ( ) ) continue ; MachineInstr * OpDef = MRI -> getVRegDef ( O . getReg ( ) ) ; if ( ! OpDef || ! MDT -> dominates ( OpDef , To ) ) return false ; }


<s> if ( & MI != Add && MDT -> dominates ( Ldst , & MI ) ) UsesAfterLdst . push_back ( & MI ) ; else if ( ! MDT -> dominates ( & MI , Ldst ) ) return nullptr ; if ( MDT -> dominates ( Add , & MI ) ) UsesAfterAdd . push_back ( & MI ) ; } MachineInstr * Result = nullptr ; if ( First == Add ) { if ( noUseOfAddBeforeLoadOrStore ( First , Last ) ) { Result = Last ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else if ( canHoistLoadStoreTo ( Ldst , Add ) ) { Result = First ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } } else { Result = First ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> unsigned BasePos , OffPos ; if ( ! AII -> getBaseAndOffsetPosition ( * Ldst , BasePos , OffPos ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } unsigned BaseReg = Ldst -> getOperand ( BasePos ) . getReg ( ) ; if ( Ldst -> mayStore ( ) && Ldst -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { unsigned StReg = Ldst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Add -> getOperand ( <NUM_LIT> ) . getReg ( ) == StReg || BaseReg == StReg ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } } SmallVector < MachineInstr * , <NUM_LIT> > UsesAfterLdst ; SmallVector < MachineInstr * , <NUM_LIT> > UsesAfterAdd ; for ( MachineInstr & MI : MRI -> use_nodbg_instructions ( BaseReg ) ) { if ( & MI == Ldst || & MI == Add ) continue ; if ( & MI != Add && MDT -> dominates ( Ldst , & MI ) ) UsesAfterLdst . push_back ( & MI ) ; else if ( ! MDT -> dominates ( & MI , Ldst ) ) return nullptr ;

if ( MDT -> dominates ( Add , & MI ) ) UsesAfterAdd . push_back ( & MI ) ;


<s> MachineBasicBlock :: const_iterator MI ( Ldst ) , ME ( To ) , End ( Ldst -> getParent ( ) -> end ( ) ) ; bool IsStore = Ldst -> mayStore ( ) ; bool IsLoad = Ldst -> mayLoad ( ) ; Register ValReg = IsLoad ? Ldst -> getOperand ( <NUM_LIT> ) . getReg ( ) : Register ( ) ; for ( ; MI != ME && MI != End ; ++ MI ) { if ( MI -> isDebugValue ( ) ) continue ; if ( MI -> mayStore ( ) || MI -> isCall ( ) || MI -> isInlineAsm ( ) || MI -> hasUnmodeledSideEffects ( ) ) return false ;

if ( IsStore && MI -> mayLoad ( ) ) return false ;


<s> void <ISA_LIT>OptAddrMode :: changeToAddrMode ( MachineInstr & Ldst , unsigned NewOpcode , unsigned NewBase , MachineOperand & NewOffset ) { bool IsStore = Ldst . mayStore ( ) ; unsigned BasePos , OffPos ; MachineOperand Src = MachineOperand :: CreateImm ( <NUM_LIT> ) ; AII -> getBaseAndOffsetPosition ( Ldst , BasePos , OffPos ) ; unsigned BaseReg = Ldst . getOperand ( BasePos ) . getReg ( ) ; Ldst . RemoveOperand ( OffPos ) ; Ldst . RemoveOperand ( BasePos ) ; if ( IsStore ) { Src = Ldst . getOperand ( BasePos - <NUM_LIT> ) ; Ldst . RemoveOperand ( BasePos - <NUM_LIT> ) ; } Ldst . setDesc ( AST -> getInstrInfo ( ) -> get ( NewOpcode ) ) ; Ldst . addOperand ( MachineOperand :: CreateReg ( NewBase , true ) ) ; if ( IsStore ) Ldst . addOperand ( Src ) ; Ldst . addOperand ( MachineOperand :: CreateReg ( BaseReg , false ) ) ; Ldst . addOperand ( NewOffset ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Ldst ) ;


<s> Ldst . RemoveOperand ( OffPos ) ; Ldst . RemoveOperand ( BasePos ) ; if ( IsStore ) { Src = Ldst . getOperand ( BasePos - <NUM_LIT> ) ; Ldst . RemoveOperand ( BasePos - <NUM_LIT> ) ; } Ldst . setDesc ( AST -> getInstrInfo ( ) -> get ( NewOpcode ) ) ; Ldst . addOperand ( MachineOperand :: CreateReg ( NewBase , true ) ) ; if ( IsStore ) Ldst . addOperand ( Src ) ;

Ldst . addOperand ( MachineOperand :: CreateReg ( BaseReg , false ) ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>OptAddrMode ( ) { return new <ISA_LIT>OptAddrMode ( ) ;


<s> const MachineBasicBlock * InstBB = MI -> getParent ( ) ; assert ( InstBB != MBB && <STR_LIT> ) ; if ( ! MDT -> dominates ( InstBB , MBB ) ) return false ; continue ; } User = & * MBB -> rbegin ( ) ; } if ( ! MDT -> dominates ( MI , User ) ) return false ;


<s> OffPos = <NUM_LIT> ; } else if ( AII -> getBaseAndOffsetPosition ( * MI , BasePos , OffPos ) ) { MachineOperand & MO = MI -> getOperand ( OffPos ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; NewOffset += MO . getImm ( ) ; assert ( isValidLoadStoreOffset ( NewOffset ) && <STR_LIT> ) ;


<s> assert ( isValidIncrementOffset ( NewOffset ) && <STR_LIT> ) ; BasePos = <NUM_LIT> ; OffPos = <NUM_LIT> ; } else if ( AII -> getBaseAndOffsetPosition ( * MI , BasePos , OffPos ) ) { MachineOperand & MO = MI -> getOperand ( OffPos ) ;

assert ( MO . isImm ( ) && <STR_LIT> ) ;


<s> AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;

AU . addRequired < MachineDominatorTree > ( ) ;


<s> StringRef getPassName ( ) const override { return OPTADDRMODE_DESC ;


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : Sign = - <NUM_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : assert ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ;

Amount = Sign * MI . getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> if ( ! MO . isImm ( ) ) return false ; int64_t Offset = MO . getImm ( ) + Disp ;

return isValidLoadStoreOffset ( Offset ) ;


<s> return isUInt < <NUM_LIT> > ( Off ) ;


<s> static bool isValidLoadStoreOffset ( int64_t Off ) { return isInt < <NUM_LIT> > ( Off ) ;


<s> bool <ISA_LIT>OptAddrMode :: noUseOfAddBeforeLoadOrStore ( const MachineInstr * Add , const MachineInstr * Ldst ) {

unsigned R = Add -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> bool <ISA_LIT>OptAddrMode :: noUseOfAddBeforeLoadOrStore ( const MachineInstr * Add , const MachineInstr * Ldst ) { unsigned R = Add -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return dominatesAllUsesOf ( Ldst , R , MDT , MRI ) ;


<s> bool <ISA_LIT>OptAddrMode :: processBasicBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; for ( auto MI = MBB . begin ( ) , ME = MBB . end ( ) ; MI != ME ; ++ MI ) { if ( MI -> isDebugValue ( ) ) continue ; if ( ! MI -> mayLoad ( ) && ! MI -> mayStore ( ) ) continue ; if ( <STR_LIT> ( MI -> getOpcode ( ) ) < <NUM_LIT> ) continue ; MachineInstr * Res = tryToCombine ( * MI ) ; if ( Res ) { Changed = true ; MI = std :: prev ( Res -> getIterator ( ) ) ; } }


<s> if ( ! MI -> mayLoad ( ) && ! MI -> mayStore ( ) ) continue ; if ( <STR_LIT> ( MI -> getOpcode ( ) ) < <NUM_LIT> ) continue ; MachineInstr * Res = tryToCombine ( * MI ) ; if ( Res ) { Changed = true ; MI = std :: prev ( Res -> getIterator ( ) ) ; }


<s> bool <ISA_LIT>OptAddrMode :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; AST = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AII = AST -> getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ;

MDT = & getAnalysis < MachineDominatorTree > ( ) ;


<s> MDT = & getAnalysis < MachineDominatorTree > ( ) ; bool Changed = false ; for ( auto & MBB : MF ) Changed |= processBasicBlock ( MBB ) ; return Changed ;


<s> MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>InstrInfo & TII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) ; int ObjSize = MF . getFrameInfo ( ) . getObjectSize ( FrameIndex ) ; int StackSize = MF . getFrameInfo ( ) . getStackSize ( ) ; int LocalFrameSize = MF . getFrameInfo ( ) . getLocalFrameSize ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << MI << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FrameIndex << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ObjSize << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Offset << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << StackSize << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << LocalFrameSize << <STR_LIT> ) ; ( void ) LocalFrameSize ; if ( MI . isDebugValue ( ) ) { unsigned FrameReg = getFrameRegister ( MF ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( <STR_LIT> . contains ( Reg ) && <STR_LIT> ) ; if ( ! TFI -> hasFP ( MF ) ) { Offset = StackSize + Offset ; if ( FrameIndex >= <NUM_LIT> ) assert ( ( Offset >= <NUM_LIT> && Offset < StackSize ) && <STR_LIT> ) ; } else { if ( FrameIndex >= <NUM_LIT> ) {

assert ( ( Offset < <NUM_LIT> && - Offset <= StackSize ) && <STR_LIT> ) ;


<s> BuildMI ( MBB , II , dl , TII . get ( MI . getOpcode ( ) ) , Reg ) . addReg ( BaseReg , KillState ) . addImm ( Offset ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; break ; case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; case <STR_LIT> : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( MI . getOpcode ( ) ) ) . addReg ( Reg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) . addReg ( BaseReg , KillState ) . addImm ( Offset ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; break ; case <STR_LIT> : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( isUInt < <NUM_LIT> > ( Offset ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( Reg , RegState :: Define ) . addReg ( FrameReg ) . addImm ( Offset ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> MachineOperand & FrameOp = MI . getOperand ( FIOperandNum ) ; int FrameIndex = FrameOp . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>InstrInfo & TII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) ; int ObjSize = MF . getFrameInfo ( ) . getObjectSize ( FrameIndex ) ; int StackSize = MF . getFrameInfo ( ) . getStackSize ( ) ; int LocalFrameSize = MF . getFrameInfo ( ) . getLocalFrameSize ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << MI << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << FrameIndex << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ObjSize << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << Offset << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << StackSize << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << LocalFrameSize << <STR_LIT> ) ; ( void ) LocalFrameSize ; if ( MI . isDebugValue ( ) ) { unsigned FrameReg = getFrameRegister ( MF ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( <STR_LIT> . contains ( Reg ) && <STR_LIT> ) ; if ( ! TFI -> hasFP ( MF ) ) { Offset = StackSize + Offset ; if ( FrameIndex >= <NUM_LIT> ) assert ( ( Offset >= <NUM_LIT> && Offset < StackSize ) && <STR_LIT> ) ; } else { if ( FrameIndex >= <NUM_LIT> ) { assert ( ( Offset < <NUM_LIT> && - Offset <= StackSize ) && <STR_LIT> ) ; } }

ReplaceFrameIndex ( II , TII , Reg , getFrameRegister ( MF ) , Offset , StackSize , ObjSize , RS , SPAdj ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const {

const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ;


<s> const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ;

return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ;


<s> } if ( MI . getOpcode ( ) != <STR_LIT> && ( Offset >= <NUM_LIT> || Offset < - <NUM_LIT> ) ) { BaseReg = RS -> FindUnusedReg ( & <STR_LIT> ) ; if ( ! BaseReg ) { const TargetRegisterInfo * TRI = MBB . getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; BaseReg = RS -> scavengeRegister ( & <STR_LIT> , II , SPAdj ) ; assert ( BaseReg && <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( BaseReg , TRI ) << <STR_LIT> << printReg ( FrameReg , TRI ) << <STR_LIT> << Offset << <STR_LIT> ) ; ( void ) TRI ; RS -> setRegUsed ( BaseReg ) ; } unsigned AddOpc = isUInt < <NUM_LIT> > ( Offset ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , II , dl , TII . get ( AddOpc ) ) . addReg ( BaseReg , RegState :: Define ) . addReg ( FrameReg ) . addImm ( Offset ) ; Offset = <NUM_LIT> ; KillState = RegState :: Kill ; } switch ( MI . getOpcode ( ) ) { case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( MI . getOpcode ( ) ) , Reg ) . addReg ( BaseReg , KillState ) . addImm ( Offset ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; break ; case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; case <STR_LIT> :


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const <ISA_LIT>Subtarget & ST ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , ST ( ST ) {


<s> void <ISA_LIT>RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; MachineInstr & MI = * II ; MachineOperand & FrameOp = MI . getOperand ( FIOperandNum ) ; int FrameIndex = FrameOp . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>InstrInfo & TII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) ; int ObjSize = MF . getFrameInfo ( ) . getObjectSize ( FrameIndex ) ; int StackSize = MF . getFrameInfo ( ) . getStackSize ( ) ; int LocalFrameSize = MF . getFrameInfo ( ) . getLocalFrameSize ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << MI << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FrameIndex << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ObjSize << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Offset << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << StackSize << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << LocalFrameSize << <STR_LIT> ) ; ( void ) LocalFrameSize ; if ( MI . isDebugValue ( ) ) { Register FrameReg = getFrameRegister ( MF ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; Register Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( <STR_LIT> . contains ( Reg ) && <STR_LIT> ) ; if ( ! TFI -> hasFP ( MF ) ) { Offset = StackSize + Offset ; if ( FrameIndex >= <NUM_LIT> ) assert ( ( Offset >= <NUM_LIT> && Offset < StackSize ) && <STR_LIT> ) ; } else { if ( FrameIndex >= <NUM_LIT> ) { assert ( ( Offset < <NUM_LIT> && - Offset <= StackSize ) && <STR_LIT> ) ; } } replaceFrameIndex ( II , TII , Reg , getFrameRegister ( MF ) , Offset , StackSize , ObjSize , RS , SPAdj ) ;


<s> BaseReg = RS -> FindUnusedReg ( & <STR_LIT> ) ; if ( ! BaseReg ) { const TargetRegisterInfo * TRI = MBB . getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; BaseReg = RS -> scavengeRegister ( & <STR_LIT> , II , SPAdj ) ; assert ( BaseReg && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( BaseReg , TRI ) << <STR_LIT> << printReg ( FrameReg , TRI ) << <STR_LIT> << Offset << <STR_LIT> ) ; ( void ) TRI ; RS -> setRegUsed ( BaseReg ) ; } unsigned AddOpc = isUInt < <NUM_LIT> > ( Offset ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , II , DL , TII . get ( AddOpc ) ) . addReg ( BaseReg , RegState :: Define ) . addReg ( FrameReg ) . addImm ( Offset ) ; Offset = <NUM_LIT> ; KillState = RegState :: Kill ; } switch ( MI . getOpcode ( ) ) { case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII . get ( MI . getOpcode ( ) ) , Reg ) . addReg ( BaseReg , KillState ) . addImm ( Offset ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; break ; case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII . get ( MI . getOpcode ( ) ) ) . addReg ( Reg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) . addReg ( BaseReg , KillState ) . addImm ( Offset ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; break ; case <STR_LIT> : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII . get ( isUInt < <NUM_LIT> > ( Offset ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( Reg , RegState :: Define ) . addReg ( FrameReg ) . addImm ( Offset ) ; break ; default :


<s> if ( MI . getOpcode ( ) != <STR_LIT> && ( Offset >= <NUM_LIT> || Offset < - <NUM_LIT> ) ) { BaseReg = RS -> FindUnusedReg ( & <STR_LIT> ) ; if ( ! BaseReg ) { const TargetRegisterInfo * TRI = MBB . getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; BaseReg = RS -> scavengeRegister ( & <STR_LIT> , II , SPAdj ) ; assert ( BaseReg && <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( BaseReg , TRI ) << <STR_LIT> << PrintReg ( FrameReg , TRI ) << <STR_LIT> << Offset << <STR_LIT> ) ; ( void ) TRI ; RS -> setRegUsed ( BaseReg ) ; } unsigned AddOpc = isUInt < <NUM_LIT> > ( Offset ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , II , dl , TII . get ( AddOpc ) ) . addReg ( BaseReg , RegState :: Define ) . addReg ( FrameReg ) . addImm ( Offset ) ; Offset = <NUM_LIT> ; KillState = RegState :: Kill ; } switch ( MI . getOpcode ( ) ) { case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( MI . getOpcode ( ) ) , Reg ) . addReg ( BaseReg , KillState ) . addImm ( Offset ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; break ; case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; case <STR_LIT> : DEBUG ( dbgs ( ) << <STR_LIT> ) ;

BuildMI ( MBB , II , dl , TII . get ( MI . getOpcode ( ) ) ) . addReg ( Reg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) . addReg ( BaseReg , KillState ) . addImm ( Offset ) . addMemOperand ( * MI . memoperands_begin ( ) ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) {


<s> MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( <STR_LIT> . contains ( Reg ) && <STR_LIT> ) ; if ( ! TFI -> hasFP ( MF ) ) { Offset = StackSize + Offset ; if ( FrameIndex >= <NUM_LIT> ) assert ( ( Offset >= <NUM_LIT> && Offset < StackSize ) && <STR_LIT> ) ; } else { if ( FrameIndex >= <NUM_LIT> ) { assert ( ( Offset < <NUM_LIT> && - Offset <= StackSize ) && <STR_LIT> ) ; }


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const {


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CSR_<ISA_LIT>_RegMask ;


<s> Register <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ;


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;


<s> return MF . getMMI ( ) . hasDebugInfo ( ) || MF . getFunction ( ) . needsUnwindTableEntry ( ) ;


<s> ( void ) TRI ; RS -> setRegUsed ( BaseReg ) ; } unsigned AddOpc = isUInt < <NUM_LIT> > ( Offset ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , II , dl , TII . get ( AddOpc ) ) . addReg ( BaseReg , RegState :: Define ) . addReg ( FrameReg ) . addImm ( Offset ) ; Offset = <NUM_LIT> ; KillState = RegState :: Kill ; } switch ( MI . getOpcode ( ) ) { case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( MI . getOpcode ( ) ) , Reg ) . addReg ( BaseReg , KillState ) . addImm ( Offset ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; break ; case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( MI . getOpcode ( ) ) ) . addReg ( Reg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) . addReg ( BaseReg , KillState ) . addImm ( Offset ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; break ; case <STR_LIT> : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;

BuildMI ( MBB , II , dl , TII . get ( isUInt < <NUM_LIT> > ( Offset ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( Reg , RegState :: Define ) . addReg ( FrameReg ) . addImm ( Offset ) ;


<s> bool <ISA_LIT>RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ;


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ;


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const {


<s> bool <ISA_LIT>RegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { return true ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , InstrInfo ( * this ) , FrameLowering ( * this ) , TLInfo ( TM , * this ) {


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , FrameLowering ( * this ) , TLInfo ( TM , * this ) {


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , FrameLowering ( * this ) , TLInfo ( TM , * this ) {


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const override {


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override {


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ;


<s> const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const override { return & TSInfo ;


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override {


<s> bool hasNorm ( ) const { return Xnorm ;


<s> RegisterTarget < Triple :: arc > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> ) ;


<s> Target & llvm :: getThe<ISA_LIT>Target ( ) { static Target The<ISA_LIT>Target ; return The<ISA_LIT>Target ;


<s> return RM . getValueOr ( Reloc :: Static ) ;


<s> void <ISA_LIT>PassConfig :: addPreRegAlloc ( ) {

addPass ( create<ISA_LIT>ExpandPseudosPass ( ) ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , <STR_LIT> <STR_LIT> , TT , CPU , FS , Options , getRelocModel ( RM ) , getEffectiveCodeModel ( CM ) , OL ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) , Subtarget ( TT , CPU , FS , * this ) {


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , <STR_LIT> <STR_LIT> , TT , CPU , FS , Options , getRelocModel ( RM ) , getEffectiveCodeModel ( CM ) , OL ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo ( ) ;


<s> static CodeModel :: Model getEffectiveCodeModel ( Optional < CodeModel :: Model > CM ) {


<s> void LLVMInitialize<ISA_LIT>Target ( ) {

RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ;


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) {

addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ;


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) {

addPass ( create<ISA_LIT>BranchFinalizePass ( ) ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , <STR_LIT> <STR_LIT> , TT , CPU , FS , Options , getRelocModel ( RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( std :: make_unique < TargetLoweringObjectFileELF > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo ( ) ;


<s> return new <ISA_LIT>PassConfig ( * this , PM ) ;


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( * this , PM ) ;


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override {


<s> static Reloc :: Model getRelocModel ( Optional < Reloc :: Model > RM ) { if ( ! RM . hasValue ( ) ) return Reloc :: Static ; return * RM ;


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & ) const override {


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> <ISA_LIT>TTIImpl ( <ISA_LIT>TTIImpl && Arg ) : BaseT ( std :: move ( static_cast < BaseT & > ( Arg ) ) ) , ST ( std :: move ( Arg . ST ) ) , TLI ( std :: move ( Arg . TLI ) ) {