<s> if ( ! Neg . getNode ( ) ) return false ; Src = Src . getOperand ( <NUM_LIT> ) ; Neg = DAG . getTargetConstant ( <NUM_LIT> , SDLoc ( ParentNode ) , <STR_LIT> ) ; return true ; case <STR_LIT> : if ( ! Abs . getNode ( ) ) return false ; Src = Src . getOperand ( <NUM_LIT> ) ; Abs = DAG . getTargetConstant ( <NUM_LIT> , SDLoc ( ParentNode ) , <STR_LIT> ) ; return true ; case <STR_LIT> : { unsigned Opcode = ParentNode -> getMachineOpcode ( ) ; bool HasDst = TII -> getOperandIdx ( Opcode , <STR_LIT> :: dst ) > - <NUM_LIT> ; if ( ! Sel . getNode ( ) ) return false ; SDValue CstOffset = Src . getOperand ( <NUM_LIT> ) ; if ( ParentNode -> getValueType ( <NUM_LIT> ) . isVector ( ) ) return false ; int SrcIndices [ ] = { TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0 ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1 ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src2 ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_X ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_Y ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_Z ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_W ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_X ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_Y ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_Z ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_W ) } ; std :: vector < unsigned > Consts ; for ( int OtherSrcIdx : SrcIndices ) { int OtherSelIdx = TII -> getSelIdx ( Opcode , OtherSrcIdx ) ; if ( OtherSrcIdx < <NUM_LIT> || OtherSelIdx < <NUM_LIT> ) continue ; if ( HasDst ) { OtherSrcIdx -- ; OtherSelIdx -- ; } if ( RegisterSDNode * Reg = dyn_cast < RegisterSDNode > ( ParentNode -> getOperand ( OtherSrcIdx ) ) ) { if ( Reg -> getReg ( ) == <STR_LIT> ) { ConstantSDNode * Cst = cast < ConstantSDNode > ( ParentNode -> getOperand ( OtherSelIdx ) ) ; Consts . push_back ( Cst -> getZExtValue ( ) ) ; } } } ConstantSDNode * Cst = cast < ConstantSDNode > ( CstOffset ) ; Consts . push_back ( Cst -> getZExtValue ( ) ) ; if ( ! TII -> fitsConstReadLimitations ( Consts ) ) { return false ; } Sel = CstOffset ; Src = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return true ; } case <STR_LIT> :

if ( cast < ConstantSDNode > ( Imm ) -> getZExtValue ( ) ) return false ;


<s> const <ISA_LIT>Subtarget * <ISA_LIT>TargetLowering :: getSubtarget ( ) const {

return static_cast < const <ISA_LIT>Subtarget * > ( Subtarget ) ;


<s> return static_cast < const <ISA_LIT>Subtarget * > ( Subtarget ) ;


<s> if ( std :: next ( I ) == I -> getParent ( ) -> end ( ) ) return false ;

return std :: next ( I ) -> getOpcode ( ) == <STR_LIT> ;


<s> static inline bool isEOP ( MachineBasicBlock :: iterator I ) { if ( std :: next ( I ) == I -> getParent ( ) -> end ( ) ) return false ;


<s> bool <ISA_LIT>TargetLowering :: isHWFalseValue ( SDValue Op ) const { if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Op ) ) { return CFP -> getValueAPF ( ) . isZero ( ) ; }


<s> bool <ISA_LIT>TargetLowering :: isHWTrueValue ( SDValue Op ) const { if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Op ) ) { return CFP -> isExactlyValue ( <NUM_LIT> ) ;


<s> SDLoc DL ( Op ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op , DAG . getConstantFP ( - <NUM_LIT> , DL , <STR_LIT> ) , DAG . getCondCode ( <STR_LIT> ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerFrameIndex ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ;

const <ISA_LIT>FrameLowering * TFL = getSubtarget ( ) -> getFrameLowering ( ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerFrameIndex ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>FrameLowering * TFL = getSubtarget ( ) -> getFrameLowering ( ) ; FrameIndexSDNode * FIN = cast < FrameIndexSDNode > ( Op ) ; unsigned FrameIndex = FIN -> getIndex ( ) ; unsigned IgnoredFrameReg ;

unsigned Offset = TFL -> getFrameIndexReference ( MF , FrameIndex , IgnoredFrameReg ) ;


<s> const DataLayout & DL = DAG . getDataLayout ( ) ; const GlobalValue * GV = GSD -> getGlobal ( ) ; MVT ConstPtrVT = getPointerTy ( DL , AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , SDLoc ( GSD ) , ConstPtrVT ) ;

return DAG . getNode ( <STR_LIT> , SDLoc ( GSD ) , ConstPtrVT , GA ) ;


<s> GlobalAddressSDNode * GSD = cast < GlobalAddressSDNode > ( Op ) ; if ( GSD -> getAddressSpace ( ) != AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS ) return <ISA_LIT>TargetLowering :: LowerGlobalAddress ( MFI , Op , DAG ) ; const DataLayout & DL = DAG . getDataLayout ( ) ;

const GlobalValue * GV = GSD -> getGlobal ( ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerImplicitParameter ( SelectionDAG & DAG , EVT VT , const SDLoc & DL , unsigned DwordOffset ) const { unsigned ByteOffset = DwordOffset * <NUM_LIT> ; PointerType * PtrType = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , AMDGPUA<ISA_LIT> . CONSTANT_BUFFER_0 ) ; assert ( isInt < <NUM_LIT> > ( ByteOffset ) ) ;

return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getConstant ( ByteOffset , DL , <STR_LIT> ) , MachinePointerInfo ( ConstantPointerNull :: get ( PtrType ) ) ) ;


<s> LoadSDNode * LoadNode = cast < LoadSDNode > ( Op ) ; unsigned AS = LoadNode -> getAddressSpace ( ) ; EVT MemVT = LoadNode -> getMemoryVT ( ) ; <STR_LIT> ExtType = LoadNode -> getExtensionType ( ) ; if ( AS == AMDGPUA<ISA_LIT> . PRIVATE_ADDRESS && ExtType != <STR_LIT> && MemVT . bitsLT ( <STR_LIT> ) ) { return lowerPrivateExtLoad ( Op , DAG ) ; } SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; SDValue Chain = LoadNode -> getChain ( ) ; SDValue Ptr = LoadNode -> getBasePtr ( ) ; if ( ( LoadNode -> getAddressSpace ( ) == AMDGPUA<ISA_LIT> . LOCAL_ADDRESS || LoadNode -> getAddressSpace ( ) == AMDGPUA<ISA_LIT> . PRIVATE_ADDRESS ) && VT . isVector ( ) ) { return scalarizeVectorLoad ( LoadNode , DAG ) ; } int ConstantBlock = ConstantAddressBlock ( LoadNode -> getAddressSpace ( ) , AMDGPUA<ISA_LIT> ) ; if ( ConstantBlock > - <NUM_LIT> && ( ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) || ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) ) ) { SDValue Result ; if ( isa < ConstantExpr > ( LoadNode -> getMemOperand ( ) -> getValue ( ) ) || isa < Constant > ( LoadNode -> getMemOperand ( ) -> getValue ( ) ) || isa < ConstantSDNode > ( Ptr ) ) { SDValue Slots [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { SDValue NewPtr = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( <NUM_LIT> * i + ConstantBlock * <NUM_LIT> , DL , <STR_LIT> ) ) ; Slots [ i ] = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewPtr ) ; } EVT NewVT = <STR_LIT> ; unsigned NumElements = <NUM_LIT> ; if ( VT . isVector ( ) ) { NewVT = VT ; NumElements = VT . getVectorNumElements ( ) ;


<s> if ( ! Offset . isUndef ( ) ) { LoadPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , Offset ) ; } SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Read = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , MachinePointerInfo ( ) ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Ret = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Read , ShiftAmt ) ; EVT MemEltVT = MemVT . getScalarType ( ) ; if ( ExtType == <STR_LIT> ) { SDValue MemEltVTNode = DAG . getValueType ( MemEltVT ) ; Ret = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ret , MemEltVTNode ) ; } else { Ret = DAG . getZeroExtendInReg ( Ret , DL , MemEltVT ) ; } SDValue Ops [ ] = { Ret , Read . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( Ops , DL ) ;


<s> SDValue LoadPtr = BasePtr ; if ( ! Offset . isUndef ( ) ) { LoadPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , Offset ) ; } SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Read = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , MachinePointerInfo ( ) ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Ret = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Read , ShiftAmt ) ; EVT MemEltVT = MemVT . getScalarType ( ) ; if ( ExtType == <STR_LIT> ) { SDValue MemEltVTNode = DAG . getValueType ( MemEltVT ) ; Ret = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ret , MemEltVTNode ) ; } else { Ret = DAG . getZeroExtendInReg ( Ret , DL , MemEltVT ) ;


<s> <STR_LIT> CCInv = <STR_LIT> ( CCOpcode , CompareVT . isInteger ( ) ) ; CCSwapped = <STR_LIT> ( CCInv ) ; if ( isCondCodeLegal ( CCSwapped , CompareVT . getSimpleVT ( ) ) ) { std :: swap ( True , False ) ; std :: swap ( LHS , RHS ) ; CC = DAG . getCondCode ( CCSwapped ) ; } } } if ( isZero ( RHS ) ) { SDValue Cond = LHS ; SDValue Zero = RHS ; <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; if ( CompareVT != VT ) { True = DAG . getNode ( <STR_LIT> , DL , CompareVT , True ) ; False = DAG . getNode ( <STR_LIT> , DL , CompareVT , False ) ; } switch ( CCOpcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CCOpcode = <STR_LIT> ( CCOpcode , CompareVT == <STR_LIT> ) ; Temp = True ; True = False ; False = Temp ; break ; default : break ; } SDValue SelectNode = DAG . getNode ( <STR_LIT> , DL , CompareVT , Cond , Zero , True , False , DAG . getCondCode ( CCOpcode ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SelectNode ) ; } SDValue HWTrue , HWFalse ; if ( CompareVT == <STR_LIT> ) { HWTrue = DAG . getConstantFP ( <NUM_LIT> , DL , CompareVT ) ; HWFalse = DAG . getConstantFP ( <NUM_LIT> , DL , CompareVT ) ; } else if ( CompareVT == <STR_LIT> ) { HWTrue = DAG . getConstant ( - <NUM_LIT> , DL , CompareVT ) ; HWFalse = DAG . getConstant ( <NUM_LIT> , DL , CompareVT ) ; } else {


<s> } SDValue DWordAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; if ( AS == AMDGPUA<ISA_LIT> . GLOBAL_ADDRESS ) { if ( StoreNode -> isTruncatingStore ( ) ) { assert ( VT . bitsLE ( <STR_LIT> ) ) ; SDValue MaskConstant ; if ( MemVT == <STR_LIT> ) { MaskConstant = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } else { assert ( MemVT == <STR_LIT> ) ; assert ( StoreNode -> getAlignment ( ) >= <NUM_LIT> ) ; MaskConstant = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } SDValue ByteIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue BitShift = DAG . getNode ( <STR_LIT> , DL , VT , ByteIndex , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , VT , MaskConstant , BitShift ) ; SDValue TruncValue = DAG . getNode ( <STR_LIT> , DL , VT , Value , MaskConstant ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , VT , TruncValue , BitShift ) ; SDValue Src [ <NUM_LIT> ] = { ShiftedValue , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Mask } ; SDValue Input = DAG . getBuildVector ( <STR_LIT> , DL , Src ) ; SDValue Args [ <NUM_LIT> ] = { Chain , Input , DWordAddr } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Args , MemVT , StoreNode -> getMemOperand ( ) ) ; } else if ( Ptr -> getOpcode ( ) != <STR_LIT> && VT . bitsGE ( <STR_LIT> ) ) { Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , DWordAddr ) ;

if ( StoreNode -> isTruncatingStore ( ) || StoreNode -> isIndexed ( ) ) {


<s> SDValue FractPart = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Arg , DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ; unsigned TrigNode ; switch ( Op . getOpcode ( ) ) { case <STR_LIT> : TrigNode = <STR_LIT> ; break ;


<s> SDLoc DL ( Op ) ; SDValue FractPart = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Arg , DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ; unsigned TrigNode ; switch ( Op . getOpcode ( ) ) { case <STR_LIT> : TrigNode = <STR_LIT> ; break ; case <STR_LIT> : TrigNode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } SDValue TrigVal = DAG . getNode ( TrigNode , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , FractPart , DAG . getConstantFP ( - <NUM_LIT> , DL , <STR_LIT> ) ) ) ;

if ( Gen >= <ISA_LIT>Subtarget :: R700 ) return TrigVal ;


<s> BuildVector = ReorganizeVector ( DAG , BuildVector , SwizzleRemap ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { unsigned Idx = cast < ConstantSDNode > ( Swz [ i ] ) -> getZExtValue ( ) ;

if ( SwizzleRemap . find ( Idx ) != SwizzleRemap . end ( ) ) Swz [ i ] = DAG . getConstant ( SwizzleRemap [ Idx ] , DL , <STR_LIT> ) ;


<s> SDValue & Abs = Ops [ AbsIdx [ i ] - <NUM_LIT> ] ; bool HasDst = TII -> getOperandIdx ( Opcode , <STR_LIT> :: dst ) > - <NUM_LIT> ; int SelIdx = TII -> getSelIdx ( Opcode , OperandIdx [ i ] ) ; if ( HasDst ) SelIdx -- ; SDValue & Sel = ( SelIdx > - <NUM_LIT> ) ? Ops [ SelIdx ] : FakeOp ; if ( FoldOperand ( Node , i , Src , Neg , Abs , Sel , FakeOp , DAG ) ) return DAG . getMachineNode ( Opcode , SDLoc ( Node ) , Node -> getVTList ( ) , Ops ) ; } } else if ( Opcode == <STR_LIT> ) { for ( unsigned i = <NUM_LIT> , e = Node -> getNumOperands ( ) ; i < e ; i += <NUM_LIT> ) { SDValue & Src = Ops [ i ] ; if ( FoldOperand ( Node , i , Src , FakeOp , FakeOp , FakeOp , FakeOp , DAG ) ) return DAG . getMachineNode ( Opcode , SDLoc ( Node ) , Node -> getVTList ( ) , Ops ) ; } } else if ( Opcode == <STR_LIT> ) { SDValue Src = Node -> getOperand ( <NUM_LIT> ) ; if ( ! Src . isMachineOpcode ( ) || ! TII -> hasInstrModifiers ( Src . getMachineOpcode ( ) ) ) return Node ; int ClampIdx = TII -> getOperandIdx ( Src . getMachineOpcode ( ) , <STR_LIT> :: clamp ) ; if ( ClampIdx < <NUM_LIT> ) return Node ; SDLoc DL ( Node ) ; std :: vector < SDValue > Ops ( Src -> op_begin ( ) , Src -> op_end ( ) ) ; Ops [ ClampIdx - <NUM_LIT> ] = DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; return DAG . getMachineNode ( Src . getMachineOpcode ( ) , DL , Node -> getVTList ( ) , Ops ) ; } else { if ( ! TII -> hasInstrModifiers ( Opcode ) ) return Node ; int OperandIdx [ ] = { TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0 ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1 ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src2 ) } ;


<s> for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( NewBldVec [ i ] . getOpcode ( ) == <STR_LIT> ) { unsigned Idx = dyn_cast < ConstantSDNode > ( NewBldVec [ i ] . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( isUnmovable [ Idx ] ) continue ; std :: swap ( NewBldVec [ Idx ] , NewBldVec [ i ] ) ; std :: swap ( RemapSwizzle [ i ] , RemapSwizzle [ Idx ] ) ;


<s> Results . push_back ( lowerFP_TO_<ISA_LIT>NT ( N -> getOperand ( <NUM_LIT> ) , DAG ) ) ; return ; } SDValue Result ; if ( expandFP_TO_<ISA_LIT>NT ( N , Result , DAG ) ) Results . push_back ( Result ) ; return ; } case <STR_LIT> : { SDValue Op = SDValue ( N , <NUM_LIT> ) ; SDValue RES = LowerSDIVREM ( Op , DAG ) ; Results . push_back ( RES ) ; Results . push_back ( RES . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { SDValue Op = SDValue ( N , <NUM_LIT> ) ; LowerUDIVREM64 ( Op , DAG , Results ) ;


<s> if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { Results . push_back ( lowerFP_TO_UINT ( N -> getOperand ( <NUM_LIT> ) , DAG ) ) ; return ; } LLVM_FALLTHROUGH ; case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { Results . push_back ( lowerFP_TO_<ISA_LIT>NT ( N -> getOperand ( <NUM_LIT> ) , DAG ) ) ; return ; } SDValue Result ; if ( expandFP_TO_<ISA_LIT>NT ( N , Result , DAG ) ) Results . push_back ( Result ) ; return ; } case <STR_LIT> : { SDValue Op = SDValue ( N , <NUM_LIT> ) ; SDValue RES = LowerSDIVREM ( Op , DAG ) ; Results . push_back ( RES ) ; Results . push_back ( RES . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { SDValue Op = SDValue ( N , <NUM_LIT> ) ; LowerUDIVREM64 ( Op , DAG , Results ) ; break ;


<s> SmallVector < SDValue , <NUM_LIT> > Args ; for ( unsigned i = <NUM_LIT> , e = VecVT . getVectorNumElements ( ) ; i != e ; ++ i ) { Args . push_back ( DAG . getNode ( <STR_LIT> , DL , EltVT , Vector , DAG . getConstant ( i , DL , getVectorIdxTy ( DAG . getDataLayout ( ) ) ) ) ) ; } return DAG . getNode ( <STR_LIT> , DL , VecVT , Args ) ;


<s> SDValue NewBldVec [ <NUM_LIT> ] = { VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( NewBldVec [ i ] . getOpcode ( ) == <STR_LIT> ) RemapSwizzle [ i ] = <NUM_LIT> ; if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( NewBldVec [ i ] ) ) {


<s> assert ( RemapSwizzle . empty ( ) ) ; SDValue NewBldVec [ <NUM_LIT> ] = { VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( NewBldVec [ i ] . getOpcode ( ) == <STR_LIT> ) RemapSwizzle [ i ] = <NUM_LIT> ; if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( NewBldVec [ i ] ) ) { if ( C -> isZero ( ) ) { RemapSwizzle [ i ] = <NUM_LIT> ; NewBldVec [ i ] = DAG . getUNDEF ( <STR_LIT> ) ; } else if ( C -> isExactlyValue ( <NUM_LIT> ) ) {


<s> return true ; } case <STR_LIT> : case <STR_LIT> : { unsigned ImmReg = <STR_LIT> ; uint64_t ImmValue = <NUM_LIT> ; if ( Src . getMachineOpcode ( ) == <STR_LIT> ) { ConstantFPSDNode * FPC = dyn_cast < ConstantFPSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ; float FloatValue = FPC -> getValueAPF ( ) . convertToFloat ( ) ; if ( FloatValue == <NUM_LIT> ) { ImmReg = <STR_LIT> ; } else if ( FloatValue == <NUM_LIT> ) { ImmReg = <STR_LIT> ; } else if ( FloatValue == <NUM_LIT> ) { ImmReg = <STR_LIT> ; } else { ImmValue = FPC -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ; } } else { ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ; uint64_t Value = C -> getZExtValue ( ) ; if ( Value == <NUM_LIT> ) { ImmReg = <STR_LIT> ; } else if ( Value == <NUM_LIT> ) { ImmReg = <STR_LIT> ; } else { ImmValue = Value ; } } if ( ImmReg == <STR_LIT> ) { if ( ! Imm . getNode ( ) ) return false ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Imm ) ; assert ( C ) ; if ( C -> getZExtValue ( ) ) return false ; Imm = DAG . getTargetConstant ( ImmValue , SDLoc ( ParentNode ) , <STR_LIT> ) ; } Src = DAG . getRegister ( ImmReg , <STR_LIT> ) ; return true ; } default : return false ;


<s> if ( ! VT . isVector ( ) ) return <STR_LIT> ;

return VT . changeVectorElementTypeToInteger ( ) ;


<s> switch ( StackWidth ) { default : case <NUM_LIT> : Channel = <NUM_LIT> ; if ( ElemIdx > <NUM_LIT> ) { PtrIncr = <NUM_LIT> ; } else { PtrIncr = <NUM_LIT> ; }


<s> static inline bool isEOP ( MachineBasicBlock :: iterator I ) { return std :: next ( I ) -> getOpcode ( ) == <STR_LIT> ;


<s> if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Op ) ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerBRCOND ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDValue Jump = Op . getOperand ( <NUM_LIT> ) ;

return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Chain , Jump , Cond ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerBRCOND ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDValue Jump = Op . getOperand ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Chain , Jump , Cond ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerEXTRACT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; SDValue Vector = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ;

if ( isa < ConstantSDNode > ( Index ) || Vector . getOpcode ( ) == <STR_LIT> ) return Op ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SmallVector < <STR_LIT> , <NUM_LIT> > LocalIns ; getOriginalFunctionArgs ( DAG , MF . getFunction ( ) , Ins , LocalIns ) ; AnalyzeFormalArguments ( CCInfo , LocalIns ) ; for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i < e ; ++ i ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerFPTOUINT ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op , DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getCondCode ( <STR_LIT> ) ) ;


<s> assert ( isInt < <NUM_LIT> > ( ByteOffset ) ) ; return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getConstant ( ByteOffset , DL , <STR_LIT> ) , MachinePointerInfo ( ConstantPointerNull :: get ( PtrType ) ) , false , false , false , <NUM_LIT> ) ;


<s> unsigned ByteOffset = DwordOffset * <NUM_LIT> ; PointerType * PtrType = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_BUFFER_0 ) ;

assert ( isInt < <NUM_LIT> > ( ByteOffset ) ) ;


<s> SDValue Vector = Op . getOperand ( <NUM_LIT> ) ; SDValue Value = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Index ) || Vector . getOpcode ( ) == <STR_LIT> ) return Op ; Vector = vectorToVerticalVector ( DAG , Vector ) ; SDValue Insert = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Vector , Value , Index ) ;

return vectorToVerticalVector ( DAG , Insert ) ;


<s> SDValue MergedValues [ <NUM_LIT> ] = { Result , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } if ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) { EVT MemVT = LoadNode -> getMemoryVT ( ) ; assert ( ! MemVT . isVector ( ) && ( MemVT == <STR_LIT> || MemVT == <STR_LIT> ) ) ; SDValue NewLoad = DAG . getExtLoad ( <STR_LIT> , DL , VT , Chain , Ptr , LoadNode -> getPointerInfo ( ) , MemVT , LoadNode -> isVolatile ( ) , LoadNode -> isNonTemporal ( ) , LoadNode -> isInvariant ( ) , LoadNode -> getAlignment ( ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , NewLoad , DAG . getValueType ( MemVT ) ) ; SDValue MergedValues [ <NUM_LIT> ] = { Res , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } if ( LoadNode -> getAddressSpace ( ) != <ISA_LIT>AS :: PRIVATE_ADDRESS ) { return SDValue ( ) ; } const MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>FrameLowering * TFL = static_cast < const <ISA_LIT>FrameLowering * > ( Subtarget -> getFrameLowering ( ) ) ; unsigned StackWidth = TFL -> getStackWidth ( MF ) ; Ptr = stackPtrToRegIndex ( Ptr , StackWidth , DAG ) ; if ( VT . isVector ( ) ) { unsigned NumElemVT = VT . getVectorNumElements ( ) ; EVT ElemVT = VT . getVectorElementType ( ) ; SDValue Loads [ <NUM_LIT> ] ; assert ( NumElemVT >= StackWidth && <STR_LIT> <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElemVT ; ++ i ) { unsigned Channel , PtrIncr ; getStackAddress ( StackWidth , i , Channel , PtrIncr ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( PtrIncr , DL , <STR_LIT> ) ) ; Loads [ i ] = DAG . getNode ( <STR_LIT> , DL , ElemVT , Chain , Ptr , DAG . getTargetConstant ( Channel , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } for ( unsigned i = NumElemVT ; i < <NUM_LIT> ; ++ i ) { Loads [ i ] = DAG . getUNDEF ( ElemVT ) ; } EVT TargetVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ElemVT , <NUM_LIT> ) ; LoweredLoad = DAG . getNode ( <STR_LIT> , DL , TargetVT , Loads ) ; } else { LoweredLoad = DAG . getNode ( <STR_LIT> , DL , VT , Chain , Ptr , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } SDValue Ops [ <NUM_LIT> ] = { LoweredLoad , Chain } ; return DAG . getMergeValues ( Ops , DL ) ;


<s> if ( SDValue Ret = <ISA_LIT>TargetLowering :: LowerLOAD ( Op , DAG ) ) return Ret ; if ( LoadNode -> getAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS && isa < GlobalVariable > ( GetUnderlyingObject ( LoadNode -> getMemOperand ( ) -> getValue ( ) , DAG . getDataLayout ( ) ) ) ) { SDValue Ptr = DAG . getZExtOrTrunc ( LoadNode -> getBasePtr ( ) , DL , getPointerTy ( DAG . getDataLayout ( ) , <ISA_LIT>AS :: PRIVATE_ADDRESS ) ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , Op -> getVTList ( ) , LoadNode -> getChain ( ) , Ptr , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } if ( LoadNode -> getAddressSpace ( ) == <ISA_LIT>AS :: LOCAL_ADDRESS && VT . isVector ( ) ) { SDValue MergedValues [ <NUM_LIT> ] = { ScalarizeVectorLoad ( Op , DAG ) , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } int ConstantBlock = ConstantAddressBlock ( LoadNode -> getAddressSpace ( ) ) ; if ( ConstantBlock > - <NUM_LIT> && ( ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) || ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) ) ) { SDValue Result ; if ( isa < ConstantExpr > ( LoadNode -> getMemOperand ( ) -> getValue ( ) ) || isa < Constant > ( LoadNode -> getMemOperand ( ) -> getValue ( ) ) || isa < ConstantSDNode > ( Ptr ) ) { SDValue Slots [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { SDValue NewPtr = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( <NUM_LIT> * i + ConstantBlock * <NUM_LIT> , DL , <STR_LIT> ) ) ; Slots [ i ] = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewPtr ) ; } EVT NewVT = <STR_LIT> ; unsigned NumElements = <NUM_LIT> ; if ( VT . isVector ( ) ) { NewVT = VT ; NumElements = VT . getVectorNumElements ( ) ; } Result = DAG . getNode ( <STR_LIT> , DL , NewVT , makeArrayRef ( Slots , NumElements ) ) ; } else { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstant ( LoadNode -> getAddressSpace ( ) - <ISA_LIT>AS :: CONSTANT_BUFFER_0 , DL , <STR_LIT> ) ) ; } if ( ! VT . isVector ( ) ) {

Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> EVT VT = Op . getValueType ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue True = Op . getOperand ( <NUM_LIT> ) ; SDValue False = Op . getOperand ( <NUM_LIT> ) ; SDValue CC = Op . getOperand ( <NUM_LIT> ) ; SDValue Temp ; if ( VT == <STR_LIT> ) { DAGCombinerInfo DCI ( DAG , AfterLegalizeVectorOps , true , nullptr ) ; SDValue MinMax = CombineFMinMaxLegacy ( DL , VT , LHS , RHS , True , False , CC , DCI ) ; if ( MinMax ) return MinMax ; } EVT CompareVT = LHS . getValueType ( ) ; <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; <STR_LIT> InverseCC = <STR_LIT> ( CCOpcode , CompareVT == <STR_LIT> ) ; if ( isHWTrueValue ( False ) && isHWFalseValue ( True ) ) { if ( isCondCodeLegal ( InverseCC , CompareVT . getSimpleVT ( ) ) ) { std :: swap ( False , True ) ; CC = DAG . getCondCode ( InverseCC ) ; } else { <STR_LIT> SwapInvCC = <STR_LIT> ( InverseCC ) ; if ( isCondCodeLegal ( SwapInvCC , CompareVT . getSimpleVT ( ) ) ) { std :: swap ( False , True ) ; std :: swap ( LHS , RHS ) ; CC = DAG . getCondCode ( SwapInvCC ) ; } } } if ( isHWTrueValue ( True ) && isHWFalseValue ( False ) && ( CompareVT == VT || VT == <STR_LIT> ) ) { return DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS , True , False , CC ) ; } if ( isZero ( LHS ) ) { <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; <STR_LIT> CCSwapped = <STR_LIT> ( CCOpcode ) ; if ( isCondCodeLegal ( CCSwapped , CompareVT . getSimpleVT ( ) ) ) { std :: swap ( LHS , RHS ) ; CC = DAG . getCondCode ( CCSwapped ) ; } else { <STR_LIT> CCInv = <STR_LIT> ( CCOpcode , CompareVT . isInteger ( ) ) ; CCSwapped = <STR_LIT> ( CCInv ) ; if ( isCondCodeLegal ( CCSwapped , CompareVT . getSimpleVT ( ) ) ) { std :: swap ( True , False ) ; std :: swap ( LHS , RHS ) ; CC = DAG . getCondCode ( CCSwapped ) ; } } } if ( isZero ( RHS ) ) { SDValue Cond = LHS ; SDValue Zero = RHS ; <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; if ( CompareVT != VT ) { True = DAG . getNode ( <STR_LIT> , DL , CompareVT , True ) ; False = DAG . getNode ( <STR_LIT> , DL , CompareVT , False ) ;


<s> SDValue Overflow = DAG . getNode ( <STR_LIT> , DL , VT , Lo , CompShift ) ; Overflow = DAG . getNode ( <STR_LIT> , DL , VT , Overflow , One ) ; SDValue HiSmall = DAG . getNode ( <STR_LIT> , DL , VT , Hi , Shift ) ; HiSmall = DAG . getNode ( <STR_LIT> , DL , VT , HiSmall , Overflow ) ; SDValue LoSmall = DAG . getNode ( <STR_LIT> , DL , VT , Lo , Shift ) ; SDValue HiBig = DAG . getNode ( <STR_LIT> , DL , VT , Lo , BigShift ) ; SDValue LoBig = Zero ;

Hi = DAG . getSelectCC ( DL , Shift , Width , HiSmall , HiBig , <STR_LIT> ) ;


<s> SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Shift = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Width = DAG . getConstant ( VT . getSizeInBits ( ) , DL , VT ) ; SDValue Width1 = DAG . getConstant ( VT . getSizeInBits ( ) - <NUM_LIT> , DL , VT ) ; SDValue BigShift = DAG . getNode ( <STR_LIT> , DL , VT , Shift , Width ) ; SDValue CompShift = DAG . getNode ( <STR_LIT> , DL , VT , Width1 , Shift ) ; SDValue Overflow = DAG . getNode ( <STR_LIT> , DL , VT , Lo , CompShift ) ; Overflow = DAG . getNode ( <STR_LIT> , DL , VT , Overflow , One ) ; SDValue HiSmall = DAG . getNode ( <STR_LIT> , DL , VT , Hi , Shift ) ;

HiSmall = DAG . getNode ( <STR_LIT> , DL , VT , HiSmall , Overflow ) ;


<s> SDValue Shift = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; const bool SRA = Op . getOpcode ( ) == <STR_LIT> ; SDValue Width = DAG . getConstant ( VT . getSizeInBits ( ) , DL , VT ) ; SDValue Width1 = DAG . getConstant ( VT . getSizeInBits ( ) - <NUM_LIT> , DL , VT ) ; SDValue BigShift = DAG . getNode ( <STR_LIT> , DL , VT , Shift , Width ) ; SDValue CompShift = DAG . getNode ( <STR_LIT> , DL , VT , Width1 , Shift ) ; SDValue Overflow = DAG . getNode ( <STR_LIT> , DL , VT , Hi , CompShift ) ; Overflow = DAG . getNode ( <STR_LIT> , DL , VT , Overflow , One ) ; SDValue HiSmall = DAG . getNode ( SRA ? <STR_LIT> : <STR_LIT> , DL , VT , Hi , Shift ) ; SDValue LoSmall = DAG . getNode ( <STR_LIT> , DL , VT , Lo , Shift ) ; LoSmall = DAG . getNode ( <STR_LIT> , DL , VT , LoSmall , Overflow ) ; SDValue LoBig = DAG . getNode ( SRA ? <STR_LIT> : <STR_LIT> , DL , VT , Hi , BigShift ) ;

SDValue HiBig = SRA ? DAG . getNode ( <STR_LIT> , DL , VT , Hi , Width1 ) : Zero ;


<s> SDValue TruncValue = DAG . getNode ( <STR_LIT> , DL , VT , Value , MaskConstant ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , VT , ByteIndex , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , VT , TruncValue , Shift ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , VT , MaskConstant , Shift ) ; SDValue Src [ <NUM_LIT> ] = { ShiftedValue , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Mask } ; SDValue Input = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ; SDValue Args [ <NUM_LIT> ] = { Chain , Input , DWordAddr } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Args , MemVT , StoreNode -> getMemOperand ( ) ) ; } else if ( Ptr -> getOpcode ( ) != <STR_LIT> && Value . getValueType ( ) . bitsGE ( <STR_LIT> ) ) { Ptr = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ; if ( StoreNode -> isTruncatingStore ( ) || StoreNode -> isIndexed ( ) ) { llvm_unreachable ( <STR_LIT> ) ; } else { Chain = DAG . getStore ( Chain , DL , Value , Ptr , StoreNode -> getMemOperand ( ) ) ; } return Chain ; } } EVT ValueVT = Value . getValueType ( ) ; if ( StoreNode -> getAddressSpace ( ) != <ISA_LIT>AS :: PRIVATE_ADDRESS ) { return SDValue ( ) ; } SDValue Ret = <ISA_LIT>TargetLowering :: LowerSTORE ( Op , DAG ) ; if ( Ret . getNode ( ) ) { return Ret ; } const MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>FrameLowering * TFL = static_cast < const <ISA_LIT>FrameLowering * > ( Subtarget -> getFrameLowering ( ) ) ; unsigned StackWidth = TFL -> getStackWidth ( MF ) ; Ptr = stackPtrToRegIndex ( Ptr , StackWidth , DAG ) ; if ( ValueVT . isVector ( ) ) { unsigned NumElemVT = ValueVT . getVectorNumElements ( ) ; EVT ElemVT = ValueVT . getVectorElementType ( ) ;

SmallVector < SDValue , <NUM_LIT> > Stores ( NumElemVT ) ;


<s> } SDValue TrigVal = DAG . getNode ( TrigNode , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , FractPart , DAG . getConstantFP ( - <NUM_LIT> , DL , <STR_LIT> ) ) ) ; if ( Gen >= <ISA_LIT>Subtarget :: R700 ) return TrigVal ;

return DAG . getNode ( <STR_LIT> , DL , VT , TrigVal , DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> SDValue Arg = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; SDValue FractPart = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Arg , DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ; unsigned TrigNode ; switch ( Op . getOpcode ( ) ) { case <STR_LIT> : TrigNode = <STR_LIT> ; break ; case <STR_LIT> : TrigNode = <STR_LIT> ; break ; default :


<s> SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue OVF = DAG . getNode ( ovf , DL , VT , Lo , Hi ) ; OVF = DAG . getNode ( <STR_LIT> , DL , VT , OVF , DAG . getValueType ( <STR_LIT> ) ) ; SDValue Res = DAG . getNode ( mainop , DL , VT , Lo , Hi ) ; return DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , VT ) , Res , OVF ) ;


<s> EVT VT = Op . getValueType ( ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue OVF = DAG . getNode ( ovf , DL , VT , Lo , Hi ) ; OVF = DAG . getNode ( <STR_LIT> , DL , VT , OVF , DAG . getValueType ( <STR_LIT> ) ) ; SDValue Res = DAG . getNode ( mainop , DL , VT , Lo , Hi ) ; return DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , VT ) , Res , OVF ) ;


<s> BuildVector = CompactSwizzlableVector ( DAG , BuildVector , SwizzleRemap ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { unsigned Idx = cast < ConstantSDNode > ( Swz [ i ] ) -> getZExtValue ( ) ; if ( SwizzleRemap . find ( Idx ) != SwizzleRemap . end ( ) ) Swz [ i ] = DAG . getConstant ( SwizzleRemap [ Idx ] , DL , <STR_LIT> ) ; }


<s> BuildVector = ReorganizeVector ( DAG , BuildVector , SwizzleRemap ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { unsigned Idx = cast < ConstantSDNode > ( Swz [ i ] ) -> getZExtValue ( ) ; if ( SwizzleRemap . find ( Idx ) != SwizzleRemap . end ( ) ) Swz [ i ] = DAG . getConstant ( SwizzleRemap [ Idx ] , DL , <STR_LIT> ) ; } return BuildVector ;


<s> SDValue FakeOp ; std :: vector < SDValue > Ops ( Node -> op_begin ( ) , Node -> op_end ( ) ) ; if ( Opcode == <STR_LIT> ) { int OperandIdx [ ] = { TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_X ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_Y ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_Z ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_W ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_X ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_Y ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_Z ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_W ) } ; int NegIdx [ ] = { TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_neg_X ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_neg_Y ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_neg_Z ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_neg_W ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_neg_X ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_neg_Y ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_neg_Z ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_neg_W ) } ; int AbsIdx [ ] = { TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_abs_X ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_abs_Y ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_abs_Z ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_abs_W ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_abs_X ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_abs_Y ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_abs_Z ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_abs_W ) } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( OperandIdx [ i ] < <NUM_LIT> ) return Node ; SDValue & Src = Ops [ OperandIdx [ i ] - <NUM_LIT> ] ; SDValue & Neg = Ops [ NegIdx [ i ] - <NUM_LIT> ] ; SDValue & Abs = Ops [ AbsIdx [ i ] - <NUM_LIT> ] ; bool HasDst = TII -> getOperandIdx ( Opcode , <STR_LIT> :: dst ) > - <NUM_LIT> ; int SelIdx = TII -> getSelIdx ( Opcode , OperandIdx [ i ] ) ; if ( HasDst ) SelIdx -- ; SDValue & Sel = ( SelIdx > - <NUM_LIT> ) ? Ops [ SelIdx ] : FakeOp ; if ( FoldOperand ( Node , i , Src , Neg , Abs , Sel , FakeOp , DAG ) ) return DAG . getMachineNode ( Opcode , SDLoc ( Node ) , Node -> getVTList ( ) , Ops ) ;


<s> static SDValue ReorganizeVector ( SelectionDAG & DAG , SDValue VectorEntry , DenseMap < unsigned , unsigned > & RemapSwizzle ) { assert ( VectorEntry . getOpcode ( ) == <STR_LIT> ) ; assert ( RemapSwizzle . empty ( ) ) ; SDValue NewBldVec [ <NUM_LIT> ] = { VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) } ; bool isUnmovable [ <NUM_LIT> ] = { false , false , false , false } ;

for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) {


<s> break ; default : llvm_unreachable ( <STR_LIT> ) ; } SDLoc DL ( Ptr ) ;

return DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( SRLPad , DL , <STR_LIT> ) ) ;


<s> EVT EltVT = VecVT . getVectorElementType ( ) ; SmallVector < SDValue , <NUM_LIT> > Args ; for ( unsigned i = <NUM_LIT> , e = VecVT . getVectorNumElements ( ) ; i != e ; ++ i ) { Args . push_back ( DAG . getNode ( <STR_LIT> , DL , EltVT , Vector , DAG . getConstant ( i , DL , getVectorIdxTy ( DAG . getDataLayout ( ) ) ) ) ) ; }

return DAG . getNode ( <STR_LIT> , DL , VecVT , Args ) ;


<s> EVT VecVT = Vector . getValueType ( ) ; EVT EltVT = VecVT . getVectorElementType ( ) ; SmallVector < SDValue , <NUM_LIT> > Args ; for ( unsigned i = <NUM_LIT> , e = VecVT . getVectorNumElements ( ) ; i != e ; ++ i ) {

Args . push_back ( DAG . getNode ( <STR_LIT> , DL , EltVT , Vector , DAG . getConstant ( i , DL , getVectorIdxTy ( DAG . getDataLayout ( ) ) ) ) ) ;


<s> if ( ! VT . isSimple ( ) || VT == <STR_LIT> ) return false ; if ( VT . bitsLT ( <STR_LIT> ) ) return false ; if ( IsFast ) * IsFast = true ;

return VT . bitsGT ( <STR_LIT> ) && Align % <NUM_LIT> == <NUM_LIT> ;


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , MachineMemOperand :: Flags Flags , bool * IsFast ) const { if ( IsFast ) * IsFast = false ; if ( ! VT . isSimple ( ) || VT == <STR_LIT> ) return false ; if ( VT . bitsLT ( <STR_LIT> ) ) return false ; if ( IsFast ) * IsFast = true ;


<s> if ( ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS || AS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) ) { return ( MemVT . getSizeInBits ( ) <= <NUM_LIT> ) ; } return true ;


<s> case CallingConv :: <ISA_LIT>_KERNEL : case CallingConv :: SPIR_KERNEL : case CallingConv :: C : case CallingConv :: Fast : case CallingConv :: Cold : llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: <ISA_LIT>_VS : case CallingConv :: <ISA_LIT>_GS :


<s> RemapSwizzle [ i ] = <NUM_LIT> ; NewBldVec [ i ] = DAG . getUNDEF ( <STR_LIT> ) ; } else if ( C -> isExactlyValue ( <NUM_LIT> ) ) { RemapSwizzle [ i ] = <NUM_LIT> ; NewBldVec [ i ] = DAG . getUNDEF ( <STR_LIT> ) ; } } if ( NewBldVec [ i ] . isUndef ( ) ) continue ; if ( i >= <NUM_LIT> ) continue ; for ( unsigned j = <NUM_LIT> ; j < i ; j ++ ) { if ( NewBldVec [ i ] == NewBldVec [ j ] ) { NewBldVec [ i ] = DAG . getUNDEF ( NewBldVec [ i ] . getValueType ( ) ) ; RemapSwizzle [ i ] = j ; break ; } } } return DAG . getBuildVector ( VectorEntry . getValueType ( ) , SDLoc ( VectorEntry ) , NewBldVec ) ;


<s> for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) NewBldVec [ i ] = DAG . getNode ( <STR_LIT> , DL , EltTy , VectorEntry , DAG . getIntPtrConstant ( i , DL ) ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( NewBldVec [ i ] . isUndef ( ) ) RemapSwizzle [ i ] = <NUM_LIT> ; if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( NewBldVec [ i ] ) ) { if ( C -> isZero ( ) ) { RemapSwizzle [ i ] = <NUM_LIT> ; NewBldVec [ i ] = DAG . getUNDEF ( <STR_LIT> ) ;

} else if ( C -> isExactlyValue ( <NUM_LIT> ) ) {


<s> } EVT NewVT = <STR_LIT> ; unsigned NumElements = <NUM_LIT> ; if ( VT . isVector ( ) ) { NewVT = VT ; NumElements = VT . getVectorNumElements ( ) ; } SDValue Result = DAG . getBuildVector ( NewVT , DL , makeArrayRef ( Slots , NumElements ) ) ; if ( ! VT . isVector ( ) ) { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } SDValue MergedValues [ <NUM_LIT> ] = {


<s> } case <STR_LIT> : if ( cast < ConstantSDNode > ( Imm ) -> getZExtValue ( ) ) return false ; Imm = Src . getOperand ( <NUM_LIT> ) ; Src = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : { unsigned ImmReg = <STR_LIT> ; uint64_t ImmValue = <NUM_LIT> ; if ( Src . getMachineOpcode ( ) == <STR_LIT> ) { ConstantFPSDNode * FPC = dyn_cast < ConstantFPSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ; float FloatValue = FPC -> getValueAPF ( ) . convertToFloat ( ) ; if ( FloatValue == <NUM_LIT> ) { ImmReg = <STR_LIT> ; } else if ( FloatValue == <NUM_LIT> ) { ImmReg = <STR_LIT> ; } else if ( FloatValue == <NUM_LIT> ) { ImmReg = <STR_LIT> ; } else { ImmValue = FPC -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ; } } else { ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ; uint64_t Value = C -> getZExtValue ( ) ; if ( Value == <NUM_LIT> ) { ImmReg = <STR_LIT> ; } else if ( Value == <NUM_LIT> ) { ImmReg = <STR_LIT> ; } else { ImmValue = Value ; } } if ( ImmReg == <STR_LIT> ) { if ( ! Imm . getNode ( ) ) return false ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Imm ) ; assert ( C ) ; if ( C -> getZExtValue ( ) ) return false ; Imm = DAG . getTargetConstant ( ImmValue , SDLoc ( ParentNode ) , <STR_LIT> ) ; } Src = DAG . getRegister ( ImmReg , <STR_LIT> ) ; return true ; } default : return false ;


<s> if ( std :: next ( I ) == I -> getParent ( ) -> end ( ) ) return false ; return std :: next ( I ) -> getOpcode ( ) == <STR_LIT> ;


<s> if ( std :: next ( I ) == I -> getParent ( ) -> end ( ) ) return false ;

return std :: next ( I ) -> getOpcode ( ) == <STR_LIT> ;


<s> EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( <STR_LIT> ( CallConv ) ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & <STR_LIT> ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: PARAM_I_ADDRESS ) ; <STR_LIT> Ext = <STR_LIT> ; if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { Ext = <STR_LIT> ; } unsigned ValBase = ArgLocs [ In . getOrigArgIndex ( ) ] . getLocMemOffset ( ) ; unsigned PartOffset = VA . getLocMemOffset ( ) ; unsigned Alignment = MinAlign ( VT . getStoreSize ( ) , PartOffset ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) , PartOffset - ValBase ) ; SDValue Arg = DAG . getLoad ( <STR_LIT> , Ext , VT , DL , Chain , DAG . getConstant ( PartOffset , DL , <STR_LIT> ) , DAG . getUNDEF ( <STR_LIT> ) , PtrInfo , MemVT , Alignment , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; InVals . push_back ( Arg ) ;


<s> } else { analyzeFormalArgumentsCompute ( CCInfo , Ins ) ; } for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const <STR_LIT> & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( <STR_LIT> ( CallConv ) ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & <STR_LIT> ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: PARAM_I_ADDRESS ) ; <STR_LIT> Ext = <STR_LIT> ; if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { Ext = <STR_LIT> ; } unsigned ValBase = ArgLocs [ In . getOrigArgIndex ( ) ] . getLocMemOffset ( ) ; unsigned PartOffset = VA . getLocMemOffset ( ) ; unsigned Alignment = MinAlign ( VT . getStoreSize ( ) , PartOffset ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) , PartOffset - ValBase ) ; SDValue Arg = DAG . getLoad ( <STR_LIT> , Ext , VT , DL , Chain , DAG . getConstant ( PartOffset , DL , <STR_LIT> ) , DAG . getUNDEF ( <STR_LIT> ) , PtrInfo , MemVT , Alignment , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ;


<s> FrameIndexSDNode * FIN = cast < FrameIndexSDNode > ( Op ) ; unsigned FrameIndex = FIN -> getIndex ( ) ; unsigned IgnoredFrameReg ; unsigned Offset = TFL -> getFrameIndexReference ( MF , FrameIndex , IgnoredFrameReg ) ; return DAG . getConstant ( Offset * <NUM_LIT> * TFL -> getStackWidth ( MF ) , SDLoc ( Op ) , Op . getValueType ( ) ) ;


<s> GlobalAddressSDNode * GSD = cast < GlobalAddressSDNode > ( Op ) ; if ( GSD -> getAddressSpace ( ) != <ISA_LIT>AS :: CONSTANT_ADDRESS ) return <ISA_LIT>TargetLowering :: LowerGlobalAddress ( MFI , Op , DAG ) ; const DataLayout & DL = DAG . getDataLayout ( ) ; const GlobalValue * GV = GSD -> getGlobal ( ) ; MVT ConstPtrVT = getPointerTy ( DL , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , SDLoc ( GSD ) , ConstPtrVT ) ;

return DAG . getNode ( <STR_LIT> , SDLoc ( GSD ) , ConstPtrVT , GA ) ;


<s> const GlobalValue * GV = GSD -> getGlobal ( ) ; MVT ConstPtrVT = getPointerTy ( DL , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , SDLoc ( GSD ) , ConstPtrVT ) ;


<s> PointerType * PtrType = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: PARAM_I_ADDRESS ) ; assert ( isInt < <NUM_LIT> > ( ByteOffset ) ) ;

return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getConstant ( ByteOffset , DL , <STR_LIT> ) , MachinePointerInfo ( ConstantPointerNull :: get ( PtrType ) ) ) ;


<s> unsigned ByteOffset = DwordOffset * <NUM_LIT> ;

PointerType * PtrType = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: PARAM_I_ADDRESS ) ;


<s> Result , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } if ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) { EVT MemVT = LoadNode -> getMemoryVT ( ) ; assert ( ! MemVT . isVector ( ) && ( MemVT == <STR_LIT> || MemVT == <STR_LIT> ) ) ; SDValue NewLoad = DAG . getExtLoad ( <STR_LIT> , DL , VT , Chain , Ptr , LoadNode -> getPointerInfo ( ) , MemVT , LoadNode -> getAlignment ( ) , LoadNode -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , NewLoad , DAG . getValueType ( MemVT ) ) ; SDValue MergedValues [ <NUM_LIT> ] = { Res , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } if ( LoadNode -> getAddressSpace ( ) != <ISA_LIT>AS :: PRIVATE_ADDRESS ) { return SDValue ( ) ; } if ( Ptr . getOpcode ( ) != <STR_LIT> ) { assert ( VT == <STR_LIT> ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr ) ; return DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , LoadNode -> getMemOperand ( ) ) ; }


<s> if ( AS == <ISA_LIT>AS :: PRIVATE_ADDRESS && ExtType != <STR_LIT> && MemVT . bitsLT ( <STR_LIT> ) ) { return lowerPrivateExtLoad ( Op , DAG ) ; } SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; SDValue Chain = LoadNode -> getChain ( ) ; SDValue Ptr = LoadNode -> getBasePtr ( ) ; if ( ( LoadNode -> getAddressSpace ( ) == <ISA_LIT>AS :: LOCAL_ADDRESS || LoadNode -> getAddressSpace ( ) == <ISA_LIT>AS :: PRIVATE_ADDRESS ) && VT . isVector ( ) ) { return scalarizeVectorLoad ( LoadNode , DAG ) ; } int ConstantBlock = ConstantAddressBlock ( LoadNode -> getAddressSpace ( ) ) ; if ( ConstantBlock > - <NUM_LIT> && ( ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) || ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) ) ) { SDValue Result ; if ( isa < Constant > ( LoadNode -> getMemOperand ( ) -> getValue ( ) ) || isa < ConstantSDNode > ( Ptr ) ) { return constBufferLoad ( LoadNode , LoadNode -> getAddressSpace ( ) , DAG ) ; } else { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstant ( LoadNode -> getAddressSpace ( ) - <ISA_LIT>AS :: CONSTANT_BUFFER_0 , DL , <STR_LIT> ) ) ; } if ( ! VT . isVector ( ) ) { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } SDValue MergedValues [ <NUM_LIT> ] = { Result , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } if ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) { EVT MemVT = LoadNode -> getMemoryVT ( ) ; assert ( ! MemVT . isVector ( ) && ( MemVT == <STR_LIT> || MemVT == <STR_LIT> ) ) ; SDValue NewLoad = DAG . getExtLoad ( <STR_LIT> , DL , VT , Chain , Ptr , LoadNode -> getPointerInfo ( ) , MemVT , LoadNode -> getAlignment ( ) , LoadNode -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , NewLoad , DAG . getValueType ( MemVT ) ) ; SDValue MergedValues [ <NUM_LIT> ] = { Res , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } if ( LoadNode -> getAddressSpace ( ) != <ISA_LIT>AS :: PRIVATE_ADDRESS ) { return SDValue ( ) ;


<s> assert ( VT . bitsLE ( <STR_LIT> ) ) ; SDValue MaskConstant ; if ( MemVT == <STR_LIT> ) { MaskConstant = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } else { assert ( MemVT == <STR_LIT> ) ; assert ( StoreNode -> getAlignment ( ) >= <NUM_LIT> ) ; MaskConstant = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } SDValue ByteIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue BitShift = DAG . getNode ( <STR_LIT> , DL , VT , ByteIndex , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , VT , MaskConstant , BitShift ) ; SDValue TruncValue = DAG . getNode ( <STR_LIT> , DL , VT , Value , MaskConstant ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , VT , TruncValue , BitShift ) ; SDValue Src [ <NUM_LIT> ] = { ShiftedValue , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Mask } ; SDValue Input = DAG . getBuildVector ( <STR_LIT> , DL , Src ) ; SDValue Args [ <NUM_LIT> ] = { Chain , Input , DWordAddr } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Args , MemVT , StoreNode -> getMemOperand ( ) ) ; } else if ( Ptr -> getOpcode ( ) != <STR_LIT> && VT . bitsGE ( <STR_LIT> ) ) { Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , DWordAddr ) ; if ( StoreNode -> isIndexed ( ) ) { llvm_unreachable ( <STR_LIT> ) ; } else { Chain = DAG . getStore ( Chain , DL , Value , Ptr , StoreNode -> getMemOperand ( ) ) ; }


<s> SDValue <ISA_LIT>TargetLowering :: LowerTrig ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; SDValue Arg = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; SDValue FractPart = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Arg , DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ; unsigned TrigNode ; switch ( Op . getOpcode ( ) ) { case <STR_LIT> : TrigNode = <STR_LIT> ; break ; case <STR_LIT> : TrigNode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } SDValue TrigVal = DAG . getNode ( TrigNode , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , FractPart , DAG . getConstantFP ( - <NUM_LIT> , DL , <STR_LIT> ) ) ) ; if ( Gen >= <ISA_LIT>Subtarget :: R700 ) return TrigVal ; return DAG . getNode ( <STR_LIT> , DL , VT , TrigVal , DAG . getConstantFP ( numbers :: pif , DL , <STR_LIT> ) ) ;


<s> DenseMap < unsigned , unsigned > SwizzleRemap ; BuildVector = CompactSwizzlableVector ( DAG , BuildVector , SwizzleRemap ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { unsigned Idx = cast < ConstantSDNode > ( Swz [ i ] ) -> getZExtValue ( ) ; if ( SwizzleRemap . find ( Idx ) != SwizzleRemap . end ( ) ) Swz [ i ] = DAG . getConstant ( SwizzleRemap [ Idx ] , DL , <STR_LIT> ) ; } SwizzleRemap . clear ( ) ;

BuildVector = ReorganizeVector ( DAG , BuildVector , SwizzleRemap ) ;


<s> BuildVector = ReorganizeVector ( DAG , BuildVector , SwizzleRemap ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { unsigned Idx = cast < ConstantSDNode > ( Swz [ i ] ) -> getZExtValue ( ) ; if ( SwizzleRemap . find ( Idx ) != SwizzleRemap . end ( ) ) Swz [ i ] = DAG . getConstant ( SwizzleRemap [ Idx ] , DL , <STR_LIT> ) ; } return BuildVector ;


<s> if ( HasDst ) SelIdx -- ; SDValue & Sel = ( SelIdx > - <NUM_LIT> ) ? Ops [ SelIdx ] : FakeOp ; if ( FoldOperand ( Node , i , Src , Neg , Abs , Sel , FakeOp , DAG ) ) return DAG . getMachineNode ( Opcode , SDLoc ( Node ) , Node -> getVTList ( ) , Ops ) ; } } else if ( Opcode == <STR_LIT> ) { for ( unsigned i = <NUM_LIT> , e = Node -> getNumOperands ( ) ; i < e ; i += <NUM_LIT> ) { SDValue & Src = Ops [ i ] ; if ( FoldOperand ( Node , i , Src , FakeOp , FakeOp , FakeOp , FakeOp , DAG ) ) return DAG . getMachineNode ( Opcode , SDLoc ( Node ) , Node -> getVTList ( ) , Ops ) ; } } else { if ( ! TII -> hasInstrModifiers ( Opcode ) ) return Node ; int OperandIdx [ ] = { TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0 ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1 ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src2 ) } ; int NegIdx [ ] = { TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_neg ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_neg ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src2_neg ) } ; int AbsIdx [ ] = { TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_abs ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_abs ) , - <NUM_LIT> } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( OperandIdx [ i ] < <NUM_LIT> ) return Node ; SDValue & Src = Ops [ OperandIdx [ i ] - <NUM_LIT> ] ; SDValue & Neg = Ops [ NegIdx [ i ] - <NUM_LIT> ] ; SDValue FakeAbs ; SDValue & Abs = ( AbsIdx [ i ] > - <NUM_LIT> ) ? Ops [ AbsIdx [ i ] - <NUM_LIT> ] : FakeAbs ; bool HasDst = TII -> getOperandIdx ( Opcode , <STR_LIT> :: dst ) > - <NUM_LIT> ; int SelIdx = TII -> getSelIdx ( Opcode , OperandIdx [ i ] ) ; int ImmIdx = TII -> getOperandIdx ( Opcode , <STR_LIT> :: literal ) ; if ( HasDst ) { SelIdx -- ; ImmIdx -- ;


<s> if ( FoldOperand ( Node , i , Src , Neg , Abs , Sel , FakeOp , DAG ) ) return DAG . getMachineNode ( Opcode , SDLoc ( Node ) , Node -> getVTList ( ) , Ops ) ; } } else if ( Opcode == <STR_LIT> ) { for ( unsigned i = <NUM_LIT> , e = Node -> getNumOperands ( ) ; i < e ; i += <NUM_LIT> ) { SDValue & Src = Ops [ i ] ; if ( FoldOperand ( Node , i , Src , FakeOp , FakeOp , FakeOp , FakeOp , DAG ) ) return DAG . getMachineNode ( Opcode , SDLoc ( Node ) , Node -> getVTList ( ) , Ops ) ; } } else { if ( ! TII -> hasInstrModifiers ( Opcode ) ) return Node ; int OperandIdx [ ] = { TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0 ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1 ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src2 ) } ; int NegIdx [ ] = { TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_neg ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_neg ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src2_neg ) } ; int AbsIdx [ ] = { TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_abs ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_abs ) , - <NUM_LIT> } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( OperandIdx [ i ] < <NUM_LIT> ) return Node ; SDValue & Src = Ops [ OperandIdx [ i ] - <NUM_LIT> ] ; SDValue & Neg = Ops [ NegIdx [ i ] - <NUM_LIT> ] ; SDValue FakeAbs ; SDValue & Abs = ( AbsIdx [ i ] > - <NUM_LIT> ) ? Ops [ AbsIdx [ i ] - <NUM_LIT> ] : FakeAbs ; bool HasDst = TII -> getOperandIdx ( Opcode , <STR_LIT> :: dst ) > - <NUM_LIT> ; int SelIdx = TII -> getSelIdx ( Opcode , OperandIdx [ i ] ) ; int ImmIdx = TII -> getOperandIdx ( Opcode , <STR_LIT> :: literal ) ; if ( HasDst ) { SelIdx -- ; ImmIdx -- ;


<s> assert ( RemapSwizzle . empty ( ) ) ; SDLoc DL ( VectorEntry ) ; EVT EltTy = VectorEntry . getValueType ( ) . getVectorElementType ( ) ; SDValue NewBldVec [ <NUM_LIT> ] ; bool isUnmovable [ <NUM_LIT> ] = { false , false , false , false } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) NewBldVec [ i ] = DAG . getNode ( <STR_LIT> , DL , EltTy , VectorEntry , DAG . getIntPtrConstant ( i , DL ) ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { RemapSwizzle [ i ] = i ; if ( NewBldVec [ i ] . getOpcode ( ) == <STR_LIT> ) { unsigned Idx = dyn_cast < ConstantSDNode > ( NewBldVec [ i ] . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( i == Idx ) isUnmovable [ Idx ] = true ; } }


<s> EVT EltTy = VectorEntry . getValueType ( ) . getVectorElementType ( ) ; SDValue NewBldVec [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) NewBldVec [ i ] = DAG . getNode ( <STR_LIT> , DL , EltTy , VectorEntry , DAG . getIntPtrConstant ( i , DL ) ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( NewBldVec [ i ] . isUndef ( ) ) RemapSwizzle [ i ] = <NUM_LIT> ;

if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( NewBldVec [ i ] ) ) {


<s> if ( <STR_LIT> ( CallConv ) ) { CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , isVarArg ) ) ; } else { analyzeFormalArgumentsCompute ( CCInfo , Ins ) ; } for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const <STR_LIT> & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( <STR_LIT> ( CallConv ) ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & <STR_LIT> ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ;


<s> LoadSDNode * Load = cast < LoadSDNode > ( Op ) ; <STR_LIT> ExtType = Load -> getExtensionType ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; assert ( Load -> getAlignment ( ) >= MemVT . getStoreSize ( ) ) ; SDValue BasePtr = Load -> getBasePtr ( ) ; SDValue Chain = Load -> getChain ( ) ; SDValue Offset = Load -> getOffset ( ) ; SDValue LoadPtr = BasePtr ; if ( ! Offset . isUndef ( ) ) { LoadPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , Offset ) ; } SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; MachinePointerInfo PtrInfo ( <ISA_LIT>AS :: PRIVATE_ADDRESS ) ; SDValue Read = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , PtrInfo ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;

SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> SDValue Chain = VectorTrunc ? OldChain -> getOperand ( <NUM_LIT> ) : OldChain ; SDValue BasePtr = Store -> getBasePtr ( ) ; SDValue Offset = Store -> getOffset ( ) ; EVT MemVT = Store -> getMemoryVT ( ) ; SDValue LoadPtr = BasePtr ; if ( ! Offset . isUndef ( ) ) { LoadPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , Offset ) ; } SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; MachinePointerInfo PtrInfo ( <ISA_LIT>AS :: PRIVATE_ADDRESS ) ; SDValue Dst = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , PtrInfo ) ; Chain = Dst . getValue ( <NUM_LIT> ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;

SDValue SExtValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Store -> getValue ( ) ) ;


<s> } } if ( isHWTrueValue ( True ) && isHWFalseValue ( False ) && ( CompareVT == VT || VT == <STR_LIT> ) ) { return DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS , True , False , CC ) ; } if ( isZero ( LHS ) ) { <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; <STR_LIT> CCSwapped = <STR_LIT> ( CCOpcode ) ; if ( isCondCodeLegal ( CCSwapped , CompareVT . getSimpleVT ( ) ) ) { std :: swap ( LHS , RHS ) ; CC = DAG . getCondCode ( CCSwapped ) ; } else { <STR_LIT> CCInv = <STR_LIT> ( CCOpcode , CompareVT ) ; CCSwapped = <STR_LIT> ( CCInv ) ; if ( isCondCodeLegal ( CCSwapped , CompareVT . getSimpleVT ( ) ) ) { std :: swap ( True , False ) ; std :: swap ( LHS , RHS ) ; CC = DAG . getCondCode ( CCSwapped ) ; } } } if ( isZero ( RHS ) ) { SDValue Cond = LHS ; SDValue Zero = RHS ; <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; if ( CompareVT != VT ) { True = DAG . getNode ( <STR_LIT> , DL , CompareVT , True ) ; False = DAG . getNode ( <STR_LIT> , DL , CompareVT , False ) ; } switch ( CCOpcode ) {


<s> SDValue False = Op . getOperand ( <NUM_LIT> ) ; SDValue CC = Op . getOperand ( <NUM_LIT> ) ; SDValue Temp ; if ( VT == <STR_LIT> ) { DAGCombinerInfo DCI ( DAG , AfterLegalizeVectorOps , true , nullptr ) ; SDValue MinMax = combineFMinMaxLegacy ( DL , VT , LHS , RHS , True , False , CC , DCI ) ; if ( MinMax ) return MinMax ; } EVT CompareVT = LHS . getValueType ( ) ; if ( isHWTrueValue ( False ) && isHWFalseValue ( True ) ) { <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; <STR_LIT> InverseCC = <STR_LIT> ( CCOpcode , CompareVT ) ; if ( isCondCodeLegal ( InverseCC , CompareVT . getSimpleVT ( ) ) ) { std :: swap ( False , True ) ; CC = DAG . getCondCode ( InverseCC ) ; } else { <STR_LIT> SwapInvCC = <STR_LIT> ( InverseCC ) ; if ( isCondCodeLegal ( SwapInvCC , CompareVT . getSimpleVT ( ) ) ) { std :: swap ( False , True ) ; std :: swap ( LHS , RHS ) ; CC = DAG . getCondCode ( SwapInvCC ) ; } } } if ( isHWTrueValue ( True ) && isHWFalseValue ( False ) && ( CompareVT == VT || VT == <STR_LIT> ) ) { return DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS , True , False , CC ) ; } if ( isZero ( LHS ) ) { <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; <STR_LIT> CCSwapped = <STR_LIT> ( CCOpcode ) ; if ( isCondCodeLegal ( CCSwapped , CompareVT . getSimpleVT ( ) ) ) { std :: swap ( LHS , RHS ) ; CC = DAG . getCondCode ( CCSwapped ) ; } else { <STR_LIT> CCInv = <STR_LIT> ( CCOpcode , CompareVT ) ; CCSwapped = <STR_LIT> ( CCInv ) ; if ( isCondCodeLegal ( CCSwapped , CompareVT . getSimpleVT ( ) ) ) { std :: swap ( True , False ) ; std :: swap ( LHS , RHS ) ; CC = DAG . getCondCode ( CCSwapped ) ; } } } if ( isZero ( RHS ) ) { SDValue Cond = LHS ; SDValue Zero = RHS ; <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; if ( CompareVT != VT ) { True = DAG . getNode ( <STR_LIT> , DL , CompareVT , True ) ; False = DAG . getNode ( <STR_LIT> , DL , CompareVT , False ) ; } switch ( CCOpcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CCOpcode = <STR_LIT> ( CCOpcode , CompareVT ) ; Temp = True ; True = False ; False = Temp ;


<s> SDLoc DL ( Vector ) ; EVT VecVT = Vector . getValueType ( ) ; EVT EltVT = VecVT . getVectorElementType ( ) ; SmallVector < SDValue , <NUM_LIT> > Args ; for ( unsigned i = <NUM_LIT> , e = VecVT . getVectorNumElements ( ) ; i != e ; ++ i ) { Args . push_back ( DAG . getNode ( <STR_LIT> , DL , EltVT , Vector , DAG . getVectorIdxConstant ( i , DL ) ) ) ;


<s> Args . push_back ( DAG . getNode ( <STR_LIT> , DL , EltVT , Vector , DAG . getVectorIdxConstant ( i , DL ) ) ) ; } return DAG . getNode ( <STR_LIT> , DL , VecVT , Args ) ;


<s> return isTruncStoreLegal ( ValVT , MemVT ) ;


<s> virtual bool canCombineTruncStore ( EVT ValVT , EVT MemVT , bool LegalOperations ) const override { return isTruncStoreLegal ( ValVT , MemVT ) ;


<s> if ( ( AS == AMDGPUA<ISA_LIT> . LOCAL_ADDRESS || AS == AMDGPUA<ISA_LIT> . PRIVATE_ADDRESS ) ) { return ( MemVT . getSizeInBits ( ) <= <NUM_LIT> ) ; } return true ;


<s> return ( MemVT . getSizeInBits ( ) <= <NUM_LIT> ) ; } return true ;


<s> } else { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstant ( LoadNode -> getAddressSpace ( ) - AMDGPUA<ISA_LIT> . CONSTANT_BUFFER_0 , DL , <STR_LIT> ) ) ; } if ( ! VT . isVector ( ) ) { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } SDValue MergedValues [ <NUM_LIT> ] = { Result , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } if ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) { EVT MemVT = LoadNode -> getMemoryVT ( ) ; assert ( ! MemVT . isVector ( ) && ( MemVT == <STR_LIT> || MemVT == <STR_LIT> ) ) ; SDValue NewLoad = DAG . getExtLoad ( <STR_LIT> , DL , VT , Chain , Ptr , LoadNode -> getPointerInfo ( ) , MemVT , LoadNode -> getAlignment ( ) , LoadNode -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , NewLoad , DAG . getValueType ( MemVT ) ) ; SDValue MergedValues [ <NUM_LIT> ] = { Res , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } if ( LoadNode -> getAddressSpace ( ) != AMDGPUA<ISA_LIT> . PRIVATE_ADDRESS ) { return SDValue ( ) ; } if ( Ptr . getOpcode ( ) != <STR_LIT> ) {


<s> SDLoc DL ( Op ) ; LoadSDNode * Load = cast < LoadSDNode > ( Op ) ; <STR_LIT> ExtType = Load -> getExtensionType ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; assert ( Load -> getAlignment ( ) >= MemVT . getStoreSize ( ) ) ; SDValue BasePtr = Load -> getBasePtr ( ) ; SDValue Chain = Load -> getChain ( ) ; SDValue Offset = Load -> getOffset ( ) ; SDValue LoadPtr = BasePtr ; if ( ! Offset . isUndef ( ) ) { LoadPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , Offset ) ; } SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( Type :: getInt32PtrTy ( * DAG . getContext ( ) , AMDGPUA<ISA_LIT> . PRIVATE_ADDRESS ) ) ) ; SDValue Read = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , PtrInfo ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Ret = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Read , ShiftAmt ) ; EVT MemEltVT = MemVT . getScalarType ( ) ; if ( ExtType == <STR_LIT> ) { SDValue MemEltVTNode = DAG . getValueType ( MemEltVT ) ; Ret = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ret , MemEltVTNode ) ; } else { Ret = DAG . getZeroExtendInReg ( Ret , DL , MemEltVT ) ; } SDValue Ops [ ] = {


<s> assert ( Store -> isTruncatingStore ( ) || Store -> getValue ( ) . getValueType ( ) == <STR_LIT> ) ; assert ( Store -> getAddressSpace ( ) == AMDGPUA<ISA_LIT> . PRIVATE_ADDRESS ) ; SDValue Mask ; if ( Store -> getMemoryVT ( ) == <STR_LIT> ) { assert ( Store -> getAlignment ( ) >= <NUM_LIT> ) ; Mask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } else if ( Store -> getMemoryVT ( ) == <STR_LIT> ) { assert ( Store -> getAlignment ( ) >= <NUM_LIT> ) ; Mask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } SDValue OldChain = Store -> getChain ( ) ; bool VectorTrunc = ( OldChain . getOpcode ( ) == <STR_LIT> ) ; SDValue Chain = VectorTrunc ? OldChain -> getOperand ( <NUM_LIT> ) : OldChain ; SDValue BasePtr = Store -> getBasePtr ( ) ; SDValue Offset = Store -> getOffset ( ) ; EVT MemVT = Store -> getMemoryVT ( ) ; SDValue LoadPtr = BasePtr ; if ( ! Offset . isUndef ( ) ) { LoadPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , Offset ) ; } SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( Type :: getInt32PtrTy ( * DAG . getContext ( ) , AMDGPUA<ISA_LIT> . PRIVATE_ADDRESS ) ) ) ; SDValue Dst = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , PtrInfo ) ; Chain = Dst . getValue ( <NUM_LIT> ) ;

SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> if ( VT . bitsLT ( <STR_LIT> ) ) return false ; if ( IsFast ) * IsFast = true ;

return VT . bitsGT ( <STR_LIT> ) && Alignment >= Align ( <NUM_LIT> ) ;


<s> if ( ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS || AS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) ) { return ( MemVT . getSizeInBits ( ) <= <NUM_LIT> ) ; } return true ;


<s> const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; if ( ! Src . isMachineOpcode ( ) ) return false ; switch ( Src . getMachineOpcode ( ) ) { case <STR_LIT> : if ( ! Neg . getNode ( ) ) return false ; Src = Src . getOperand ( <NUM_LIT> ) ; Neg = DAG . getTargetConstant ( <NUM_LIT> , SDLoc ( ParentNode ) , <STR_LIT> ) ; return true ; case <STR_LIT> : if ( ! Abs . getNode ( ) ) return false ; Src = Src . getOperand ( <NUM_LIT> ) ; Abs = DAG . getTargetConstant ( <NUM_LIT> , SDLoc ( ParentNode ) , <STR_LIT> ) ; return true ; case <STR_LIT> : { unsigned Opcode = ParentNode -> getMachineOpcode ( ) ; bool HasDst = TII -> getOperandIdx ( Opcode , <STR_LIT> :: dst ) > - <NUM_LIT> ; if ( ! Sel . getNode ( ) ) return false ; SDValue CstOffset = Src . getOperand ( <NUM_LIT> ) ; if ( ParentNode -> getValueType ( <NUM_LIT> ) . isVector ( ) ) return false ; int SrcIndices [ ] = { TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0 ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1 ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src2 ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_X ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_Y ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_Z ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_W ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_X ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_Y ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_Z ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_W ) } ; std :: vector < unsigned > Consts ; for ( int OtherSrcIdx : SrcIndices ) { int OtherSelIdx = TII -> getSelIdx ( Opcode , OtherSrcIdx ) ; if ( OtherSrcIdx < <NUM_LIT> || OtherSelIdx < <NUM_LIT> ) continue ; if ( HasDst ) { OtherSrcIdx -- ; OtherSelIdx -- ; }

if ( RegisterSDNode * Reg = dyn_cast < RegisterSDNode > ( ParentNode -> getOperand ( OtherSrcIdx ) ) ) {


<s> return true ; case <STR_LIT> : { unsigned Opcode = ParentNode -> getMachineOpcode ( ) ; bool HasDst = TII -> getOperandIdx ( Opcode , <STR_LIT> :: dst ) > - <NUM_LIT> ; if ( ! Sel . getNode ( ) ) return false ; SDValue CstOffset = Src . getOperand ( <NUM_LIT> ) ; if ( ParentNode -> getValueType ( <NUM_LIT> ) . isVector ( ) ) return false ; int SrcIndices [ ] = { TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0 ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1 ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src2 ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_X ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_Y ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_Z ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_W ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_X ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_Y ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_Z ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_W ) } ; std :: vector < unsigned > Consts ; for ( int OtherSrcIdx : SrcIndices ) { int OtherSelIdx = TII -> getSelIdx ( Opcode , OtherSrcIdx ) ; if ( OtherSrcIdx < <NUM_LIT> || OtherSelIdx < <NUM_LIT> ) continue ; if ( HasDst ) { OtherSrcIdx -- ; OtherSelIdx -- ; } if ( RegisterSDNode * Reg = dyn_cast < RegisterSDNode > ( ParentNode -> getOperand ( OtherSrcIdx ) ) ) { if ( Reg -> getReg ( ) == <STR_LIT> ) { ConstantSDNode * Cst = cast < ConstantSDNode > ( ParentNode -> getOperand ( OtherSelIdx ) ) ; Consts . push_back ( Cst -> getZExtValue ( ) ) ; } } } ConstantSDNode * Cst = cast < ConstantSDNode > ( CstOffset ) ; Consts . push_back ( Cst -> getZExtValue ( ) ) ; if ( ! TII -> fitsConstReadLimitations ( Consts ) ) { return false ; } Sel = CstOffset ; Src = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ;


<s> if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Op ) ) { return Cst -> isZero ( ) ; } else if ( ConstantFPSDNode * CstFP = dyn_cast < ConstantFPSDNode > ( Op ) ) { return CstFP -> isZero ( ) ;


<s> analyzeFormalArgumentsCompute ( CCInfo , Ins ) ; } for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const <STR_LIT> & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( <STR_LIT> ( CallConv ) ) { Register Reg = MF . addLiveIn ( VA . getLocReg ( ) , & <STR_LIT> ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } <STR_LIT> Ext = <STR_LIT> ;

if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) {


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; SmallVector < <STR_LIT> , <NUM_LIT> > LocalIns ; if ( <STR_LIT> ( CallConv ) ) { CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , isVarArg ) ) ; } else { analyzeFormalArgumentsCompute ( CCInfo , Ins ) ; } for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const <STR_LIT> & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( <STR_LIT> ( CallConv ) ) { Register Reg = MF . addLiveIn ( VA . getLocReg ( ) , & <STR_LIT> ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } <STR_LIT> Ext = <STR_LIT> ; if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { Ext = <STR_LIT> ; } unsigned PartOffset = VA . getLocMemOffset ( ) ; unsigned Alignment = MinAlign ( VT . getStoreSize ( ) , PartOffset ) ; MachinePointerInfo PtrInfo ( <ISA_LIT>AS :: PARAM_I_ADDRESS ) ;

SDValue Arg = DAG . getLoad ( <STR_LIT> , Ext , VT , DL , Chain , DAG . getConstant ( PartOffset , DL , <STR_LIT> ) , DAG . getUNDEF ( <STR_LIT> ) , PtrInfo , MemVT , Alignment , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ;


<s> const <ISA_LIT>FrameLowering * TFL = Subtarget -> getFrameLowering ( ) ; FrameIndexSDNode * FIN = cast < FrameIndexSDNode > ( Op ) ;

unsigned FrameIndex = FIN -> getIndex ( ) ;


<s> SDValue Lo , Hi ; expandShiftParts ( Op . getNode ( ) , Lo , Hi , DAG ) ; return DAG . getMergeValues ( { Lo , Hi } , SDLoc ( Op ) ) ;


<s> return DAG . getMergeValues ( { Lo , Hi } , SDLoc ( Op ) ) ;


<s> static SDValue ReorganizeVector ( SelectionDAG & DAG , SDValue VectorEntry , DenseMap < unsigned , unsigned > & RemapSwizzle ) { assert ( RemapSwizzle . empty ( ) ) ; SDLoc DL ( VectorEntry ) ; EVT EltTy = VectorEntry . getValueType ( ) . getVectorElementType ( ) ; SDValue NewBldVec [ <NUM_LIT> ] ; bool isUnmovable [ <NUM_LIT> ] = { false , false , false , false } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) NewBldVec [ i ] = DAG . getNode ( <STR_LIT> , DL , EltTy , VectorEntry , DAG . getIntPtrConstant ( i , DL ) ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { RemapSwizzle [ i ] = i ; if ( NewBldVec [ i ] . getOpcode ( ) == <STR_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( NewBldVec [ i ] . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( i == Idx ) isUnmovable [ Idx ] = true ; } } for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) {


<s> SDValue Mask ; if ( Store -> getMemoryVT ( ) == <STR_LIT> ) { assert ( Store -> getAlignment ( ) >= <NUM_LIT> ) ; Mask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } else if ( Store -> getMemoryVT ( ) == <STR_LIT> ) { assert ( Store -> getAlignment ( ) >= <NUM_LIT> ) ; Mask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ; } else { llvm_unreachable ( <STR_LIT> ) ; } SDValue OldChain = Store -> getChain ( ) ; bool VectorTrunc = ( OldChain . getOpcode ( ) == <STR_LIT> ) ; SDValue Chain = VectorTrunc ? OldChain -> getOperand ( <NUM_LIT> ) : OldChain ; SDValue BasePtr = Store -> getBasePtr ( ) ; SDValue Offset = Store -> getOffset ( ) ; EVT MemVT = Store -> getMemoryVT ( ) ; SDValue LoadPtr = BasePtr ; if ( ! Offset . isUndef ( ) ) { LoadPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , Offset ) ; } SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Dst = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , MachinePointerInfo ( ) ) ; Chain = Dst . getValue ( <NUM_LIT> ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SExtValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Store -> getValue ( ) ) ;

SDValue MaskedValue = DAG . getZeroExtendInReg ( SExtValue , DL , MemVT ) ;


<s> assert ( Store -> getAlignment ( ) >= <NUM_LIT> ) ; Mask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ; } else { llvm_unreachable ( <STR_LIT> ) ; } SDValue OldChain = Store -> getChain ( ) ; bool VectorTrunc = ( OldChain . getOpcode ( ) == <STR_LIT> ) ; SDValue Chain = VectorTrunc ? OldChain -> getOperand ( <NUM_LIT> ) : OldChain ; SDValue BasePtr = Store -> getBasePtr ( ) ; SDValue Offset = Store -> getOffset ( ) ; EVT MemVT = Store -> getMemoryVT ( ) ; SDValue LoadPtr = BasePtr ; if ( ! Offset . isUndef ( ) ) { LoadPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , Offset ) ; } SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Dst = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , MachinePointerInfo ( ) ) ; Chain = Dst . getValue ( <NUM_LIT> ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SExtValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Store -> getValue ( ) ) ; SDValue MaskedValue = DAG . getZeroExtendInReg ( SExtValue , DL , MemVT ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MaskedValue , ShiftAmt ) ; SDValue DstMask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mask , ShiftAmt ) ; DstMask = DAG . getNOT ( DL , DstMask , <STR_LIT> ) ; Dst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Dst , DstMask ) ; SDValue Value = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Dst , ShiftedValue ) ; SDValue NewStore = DAG . getStore ( Chain , DL , Value , Ptr , MachinePointerInfo ( ) ) ; if ( VectorTrunc ) { Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewStore ) ;

DAG . ReplaceAllUsesOfValueWith ( OldChain , Chain ) ;


<s> assert ( StoreNode -> getAlignment ( ) >= <NUM_LIT> ) ; MaskConstant = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } SDValue ByteIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue BitShift = DAG . getNode ( <STR_LIT> , DL , VT , ByteIndex , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , VT , MaskConstant , BitShift ) ; SDValue TruncValue = DAG . getNode ( <STR_LIT> , DL , VT , Value , MaskConstant ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , VT , TruncValue , BitShift ) ; SDValue Src [ <NUM_LIT> ] = { ShiftedValue , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Mask } ; SDValue Input = DAG . getBuildVector ( <STR_LIT> , DL , Src ) ; SDValue Args [ <NUM_LIT> ] = { Chain , Input , DWordAddr } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Args , MemVT , StoreNode -> getMemOperand ( ) ) ; } else if ( Ptr -> getOpcode ( ) != <STR_LIT> && VT . bitsGE ( <STR_LIT> ) ) { Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , DWordAddr ) ; if ( StoreNode -> isTruncatingStore ( ) || StoreNode -> isIndexed ( ) ) { llvm_unreachable ( <STR_LIT> ) ;


<s> SmallVector < <STR_LIT> , <NUM_LIT> > LocalIns ; if ( <STR_LIT> ( CallConv ) ) { AnalyzeFormalArguments ( CCInfo , Ins ) ; } else { analyzeFormalArgumentsCompute ( CCInfo , Ins ) ; } for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const <STR_LIT> & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( <STR_LIT> ( CallConv ) ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & <STR_LIT> ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_BUFFER_0 ) ;


<s> PointerType * PtrType = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_BUFFER_0 ) ; assert ( isInt < <NUM_LIT> > ( ByteOffset ) ) ; return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getConstant ( ByteOffset , DL , <STR_LIT> ) , MachinePointerInfo ( ConstantPointerNull :: get ( PtrType ) ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerImplicitParameter ( SelectionDAG & DAG , EVT VT , const SDLoc & DL , unsigned DwordOffset ) const { unsigned ByteOffset = DwordOffset * <NUM_LIT> ; PointerType * PtrType = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_BUFFER_0 ) ;

assert ( isInt < <NUM_LIT> > ( ByteOffset ) ) ;


<s> if ( ConstantBlock > - <NUM_LIT> && ( ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) || ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) ) ) { SDValue Result ; if ( isa < ConstantExpr > ( LoadNode -> getMemOperand ( ) -> getValue ( ) ) || isa < Constant > ( LoadNode -> getMemOperand ( ) -> getValue ( ) ) || isa < ConstantSDNode > ( Ptr ) ) { SDValue Slots [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { SDValue NewPtr = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( <NUM_LIT> * i + ConstantBlock * <NUM_LIT> , DL , <STR_LIT> ) ) ; Slots [ i ] = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewPtr ) ; } EVT NewVT = <STR_LIT> ; unsigned NumElements = <NUM_LIT> ; if ( VT . isVector ( ) ) { NewVT = VT ; NumElements = VT . getVectorNumElements ( ) ; } Result = DAG . getBuildVector ( NewVT , DL , makeArrayRef ( Slots , NumElements ) ) ; } else { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstant ( LoadNode -> getAddressSpace ( ) - <ISA_LIT>AS :: CONSTANT_BUFFER_0 , DL , <STR_LIT> ) ) ; } if ( ! VT . isVector ( ) ) { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } SDValue MergedValues [ <NUM_LIT> ] = { Result , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; }

if ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) {


<s> Chain = Dst . getValue ( <NUM_LIT> ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SExtValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Store -> getValue ( ) ) ; SDValue MaskedValue = DAG . getZeroExtendInReg ( SExtValue , DL , MemVT ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MaskedValue , ShiftAmt ) ; SDValue DstMask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mask , ShiftAmt ) ; DstMask = DAG . getNOT ( DL , DstMask , <STR_LIT> ) ; Dst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Dst , DstMask ) ; SDValue Value = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Dst , ShiftedValue ) ; SDValue NewStore = DAG . getStore ( Chain , DL , Value , Ptr , MachinePointerInfo ( ) ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; } SDValue OldChain = Store -> getChain ( ) ; bool VectorTrunc = ( OldChain . getOpcode ( ) == <STR_LIT> ) ; SDValue Chain = VectorTrunc ? OldChain -> getOperand ( <NUM_LIT> ) : OldChain ; SDValue BasePtr = Store -> getBasePtr ( ) ; SDValue Offset = Store -> getOffset ( ) ; EVT MemVT = Store -> getMemoryVT ( ) ; SDValue LoadPtr = BasePtr ; if ( ! Offset . isUndef ( ) ) { LoadPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , Offset ) ; } SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Dst = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , MachinePointerInfo ( ) ) ; Chain = Dst . getValue ( <NUM_LIT> ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SExtValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Store -> getValue ( ) ) ; SDValue MaskedValue = DAG . getZeroExtendInReg ( SExtValue , DL , MemVT ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MaskedValue , ShiftAmt ) ; SDValue DstMask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mask , ShiftAmt ) ; DstMask = DAG . getNOT ( DL , DstMask , <STR_LIT> ) ; Dst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Dst , DstMask ) ; SDValue Value = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Dst , ShiftedValue ) ; SDValue NewStore = DAG . getStore ( Chain , DL , Value , Ptr , MachinePointerInfo ( ) ) ; if ( VectorTrunc ) { Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewStore ) ;


<s> BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( MI . getOpcode ( ) ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( isEOP ( I ) ) ; break ; case <STR_LIT> : BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : { MachineInstr * NewMI = BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; TII -> addFlag ( * NewMI , <NUM_LIT> , MO_FLAG_PUSH ) ; BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; break ; } case <STR_LIT> : { MachineInstr * NewMI = BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; TII -> addFlag ( * NewMI , <NUM_LIT> , MO_FLAG_PUSH ) ; BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; break ; } case <STR_LIT> : case <STR_LIT> : { bool isLastInstructionOfItsType = true ; unsigned InstExportType = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; for ( MachineBasicBlock :: iterator NextExportInst = std :: next ( I ) , EndBlock = BB -> end ( ) ; NextExportInst != EndBlock ; NextExportInst = std :: next ( NextExportInst ) ) { if ( NextExportInst -> getOpcode ( ) == <STR_LIT> || NextExportInst -> getOpcode ( ) == <STR_LIT> ) {

unsigned CurrentInstExportType = NextExportInst -> getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> } Align Alignment = StoreNode -> getAlign ( ) ; if ( Alignment < MemVT . getStoreSize ( ) && ! allowsMisalignedMemoryAccesses ( MemVT , AS , Alignment . value ( ) , StoreNode -> getMemOperand ( ) -> getFlags ( ) , nullptr ) ) { return expandUnalignedStore ( StoreNode , DAG ) ; } SDValue DWordAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; if ( AS == <ISA_LIT>AS :: GLOBAL_ADDRESS ) { if ( TruncatingStore ) { assert ( VT . bitsLE ( <STR_LIT> ) ) ; SDValue MaskConstant ; if ( MemVT == <STR_LIT> ) { MaskConstant = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } else { assert ( MemVT == <STR_LIT> ) ; assert ( StoreNode -> getAlignment ( ) >= <NUM_LIT> ) ; MaskConstant = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } SDValue ByteIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue BitShift = DAG . getNode ( <STR_LIT> , DL , VT , ByteIndex , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , VT , MaskConstant , BitShift ) ; SDValue TruncValue = DAG . getNode ( <STR_LIT> , DL , VT , Value , MaskConstant ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , VT , TruncValue , BitShift ) ; SDValue Src [ <NUM_LIT> ] = { ShiftedValue , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Mask } ; SDValue Input = DAG . getBuildVector ( <STR_LIT> , DL , Src ) ; SDValue Args [ <NUM_LIT> ] = { Chain , Input , DWordAddr } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Args , MemVT , StoreNode -> getMemOperand ( ) ) ; } else if ( Ptr -> getOpcode ( ) != <STR_LIT> && VT . bitsGE ( <STR_LIT> ) ) { Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , DWordAddr ) ; if ( StoreNode -> isIndexed ( ) ) { llvm_unreachable ( <STR_LIT> ) ; } else { Chain = DAG . getStore ( Chain , DL , Value , Ptr , StoreNode -> getMemOperand ( ) ) ; } return Chain ;


<s> break ; } case <STR_LIT> : { MachineInstr * NewMI = TII -> buildDefaultInstruction ( * BB , MI , <STR_LIT> , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> ) ; TII -> setImmOperand ( * NewMI , <STR_LIT> :: src0_sel , MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( MI . getOpcode ( ) ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( isEOP ( I ) ) ; break ; } case <STR_LIT> : { BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( MI . getOpcode ( ) ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( isEOP ( I ) ) ; break ; } case <STR_LIT> : BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( <STR_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : { MachineInstr * NewMI = BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( OPCODE_IS_NOT_ZERO ) . addImm ( <NUM_LIT> ) ; TII -> addFlag ( * NewMI , <NUM_LIT> , MO_FLAG_PUSH ) ; BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( <STR_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; break ; } case <STR_LIT> : { MachineInstr * NewMI = BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( OPCODE_IS_NOT_ZERO_INT ) . addImm ( <NUM_LIT> ) ; TII -> addFlag ( * NewMI , <NUM_LIT> , MO_FLAG_PUSH ) ; BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( <STR_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; break ;


<s> CCValAssign & VA = ArgLocs [ i ] ; const <STR_LIT> & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( <STR_LIT> ( CallConv ) ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & <STR_LIT> ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_BUFFER_0 ) ;


<s> if ( VT . isVector ( ) ) { NewVT = VT ; NumElements = VT . getVectorNumElements ( ) ; } Result = DAG . getBuildVector ( NewVT , DL , makeArrayRef ( Slots , NumElements ) ) ; } else { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstant ( LoadNode -> getAddressSpace ( ) - <ISA_LIT>AS :: CONSTANT_BUFFER_0 , DL , <STR_LIT> ) ) ; } if ( ! VT . isVector ( ) ) { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } SDValue MergedValues [ <NUM_LIT> ] = { Result , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } SDValue LoweredLoad ; if ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) { EVT MemVT = LoadNode -> getMemoryVT ( ) ; assert ( ! MemVT . isVector ( ) && ( MemVT == <STR_LIT> || MemVT == <STR_LIT> ) ) ; SDValue NewLoad = DAG . getExtLoad ( <STR_LIT> , DL , VT , Chain , Ptr , LoadNode -> getPointerInfo ( ) , MemVT , LoadNode -> getAlignment ( ) , LoadNode -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , NewLoad , DAG . getValueType ( MemVT ) ) ; SDValue MergedValues [ <NUM_LIT> ] = { Res , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } if ( LoadNode -> getAddressSpace ( ) != <ISA_LIT>AS :: PRIVATE_ADDRESS ) { return SDValue ( ) ; } const MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>FrameLowering * TFL = getSubtarget ( ) -> getFrameLowering ( ) ; unsigned StackWidth = TFL -> getStackWidth ( MF ) ; Ptr = stackPtrToRegIndex ( Ptr , StackWidth , DAG ) ; if ( VT . isVector ( ) ) { unsigned NumElemVT = VT . getVectorNumElements ( ) ; EVT ElemVT = VT . getVectorElementType ( ) ; SDValue Loads [ <NUM_LIT> ] ; assert ( NumElemVT <= <NUM_LIT> ) ; assert ( NumElemVT >= StackWidth && <STR_LIT> <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElemVT ; ++ i ) {


<s> <STR_LIT> ExtType = Load -> getExtensionType ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Load -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Ret = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Load -> getChain ( ) , Ptr , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Load -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Ret = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ret , ShiftAmt ) ; EVT MemEltVT = MemVT . getScalarType ( ) ;


<s> EVT MemVT = Store -> getMemoryVT ( ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Dst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , Ptr , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SExtValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Store -> getValue ( ) ) ; SDValue MaskedValue = DAG . getZeroExtendInReg ( SExtValue , DL , MemVT ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MaskedValue , ShiftAmt ) ; SDValue DstMask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( Mask , DL , <STR_LIT> ) , ShiftAmt ) ;

DstMask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DstMask , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SExtValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Store -> getValue ( ) ) ; SDValue MaskedValue = DAG . getZeroExtendInReg ( SExtValue , DL , MemVT ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MaskedValue , ShiftAmt ) ; SDValue DstMask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( Mask , DL , <STR_LIT> ) , ShiftAmt ) ; DstMask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DstMask , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Dst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Dst , DstMask ) ; SDValue Value = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Dst , ShiftedValue ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , Value , Ptr , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;