<s> Optional < ValueAndVReg > ConstSelect = getIConstantVRegValWithLookThrough ( LaneSelect , * MRI ) ; if ( ConstSelect ) { MIB . addReg ( Val ) ; MIB . addImm ( ConstSelect -> Value . getSExtValue ( ) & maskTrailingOnes < uint64_t > ( STI . getWavefrontSizeLog2 ( ) ) ) ; } else { Optional < ValueAndVReg > ConstVal = getIConstantVRegValWithLookThrough ( Val , * MRI ) ; if ( ConstVal && <STR_LIT> ( ConstVal -> Value . getSExtValue ( ) , STI . hasInv2PiInlineImm ( ) ) ) { MIB . addImm ( ConstVal -> Value . getSExtValue ( ) ) ; MIB . addReg ( LaneSelect ) ; } else { MIB . addReg ( Val ) ; RBI . constrainGenericRegister ( LaneSelect , <STR_LIT> , * MRI ) ; BuildMI ( * MBB , * MIB , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( LaneSelect ) ; MIB . addReg ( <STR_LIT> ) ;


<s> void <ISA_LIT>InstructionSelector :: setupMF ( MachineFunction & MF , GISelKnownBits * KB , CodeGenCoverage & CoverageInfo , ProfileSummaryInfo * P<ISA_LIT> , BlockFrequencyInfo * BFI ) { MRI = & MF . getRegInfo ( ) ;

Subtarget = & MF . getSubtarget < GCNSubtarget > ( ) ;


<s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const <ISA_LIT>Subtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI , const <ISA_LIT>TargetMachine & TM ) : InstructionSelector ( ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , RBI ( RBI ) , TM ( TM ) , STI ( STI ) , EnableLateStructurizeCFG ( <ISA_LIT>TargetMachine :: EnableLateStructurizeCFG ) , , AMDGPUA<ISA_LIT> ( STI . get<ISA_LIT>AS ( ) ) {


<s> assert ( PtrMI ) ; if ( PtrMI -> getOpcode ( ) != TargetOpcode :: G_GEP ) return ; GEPInfo GEPInfo ( * PtrMI ) ; for ( unsigned i = <NUM_LIT> , e = <NUM_LIT> ; i < e ; ++ i ) { const MachineOperand & GEPOp = PtrMI -> getOperand ( i ) ; const MachineInstr * OpDef = MRI . getUniqueVRegDef ( GEPOp . getReg ( ) ) ; assert ( OpDef ) ; if ( isConstant ( * OpDef ) ) { assert ( GEPInfo . Imm == <NUM_LIT> ) ; GEPInfo . Imm = OpDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ; continue ; } const RegisterBank * OpBank = RBI . getRegBank ( GEPOp . getReg ( ) , MRI , TRI ) ; if ( OpBank -> getID ( ) == <STR_LIT> ) GEPInfo . SgprParts . push_back ( GEPOp . getReg ( ) ) ; else GEPInfo . VgprParts . push_back ( GEPOp . getReg ( ) ) ; }


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } break ; case <STR_LIT> : switch ( LoadSize ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } break ; case <STR_LIT> : switch ( LoadSize ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ;


<s> MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned DstReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; if ( MO . isReg ( ) ) { unsigned ComposedSubIdx = TRI . composeSubRegIndices ( MO . getSubReg ( ) , SubIdx ) ; unsigned Reg = MO . getReg ( ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( Reg , <NUM_LIT> , ComposedSubIdx ) ; return MachineOperand :: CreateReg ( DstReg , MO . isDef ( ) , MO . isImplicit ( ) , MO . isKill ( ) , MO . isDead ( ) , MO . isUndef ( ) , MO . isEarlyClobber ( ) , <NUM_LIT> , MO . isDebug ( ) , MO . isInternalRead ( ) ) ; } assert ( MO . isImm ( ) ) ; APInt Imm ( <NUM_LIT> , MO . getImm ( ) ) ;


<s> MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned DstReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; if ( MO . isReg ( ) ) { unsigned ComposedSubIdx = TRI . composeSubRegIndices ( MO . getSubReg ( ) , SubIdx ) ; unsigned Reg = MO . getReg ( ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( Reg , <NUM_LIT> , ComposedSubIdx ) ; return MachineOperand :: CreateReg ( DstReg , MO . isDef ( ) , MO . isImplicit ( ) , MO . isKill ( ) , MO . isDead ( ) , MO . isUndef ( ) , MO . isEarlyClobber ( ) , <NUM_LIT> , MO . isDebug ( ) , MO . isInternalRead ( ) ) ;


<s> const Value * Ptr = MMO -> getValue ( ) ; if ( ! Ptr || isa < UndefValue > ( Ptr ) || isa < Argument > ( Ptr ) || isa < Constant > ( Ptr ) || isa < GlobalValue > ( Ptr ) ) return true ;

if ( MMO -> getAddrSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) return true ;


<s> if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) return true ; switch ( I . getOpcode ( ) ) { default : break ; case TargetOpcode :: G_FPTOUI : case TargetOpcode :: G_OR : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_ADD : return selectG_ADD ( I ) ; case TargetOpcode :: G_BITCAST : return selectCOPY ( I ) ; case TargetOpcode :: G_CONSTANT : case TargetOpcode :: G_FCONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_GEP : return selectG_GEP ( I ) ; case TargetOpcode :: G_LOAD : return selectG_LOAD ( I ) ; case TargetOpcode :: G_STORE :


<s> if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) return true ; switch ( I . getOpcode ( ) ) { default : break ; case TargetOpcode :: G_FPTOUI : case TargetOpcode :: G_OR : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_ADD : return selectG_ADD ( I ) ; case TargetOpcode :: G_BITCAST : return selectCOPY ( I ) ; case TargetOpcode :: G_CONSTANT : case TargetOpcode :: G_FCONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_GEP : return selectG_GEP ( I ) ;


<s> bool <ISA_LIT>InstructionSelector :: selectCOPY ( MachineInstr & I ) const { MachineBasicBlock * BB = I . getParent ( ) ; MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; I . setDesc ( TII . get ( TargetOpcode :: COPY ) ) ; for ( const MachineOperand & MO : I . operands ( ) ) { if ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) continue ; const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( MO , MRI ) ; if ( ! RC ) continue ; RBI . constrainGenericRegister ( MO . getReg ( ) , * RC , MRI ) ; }


<s> MachineOperand Hi2 ( getSubOperand64 ( I . getOperand ( <NUM_LIT> ) , <STR_LIT> ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstHi ) . add ( Hi1 ) . add ( Hi2 ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( DstLo ) . addImm ( <STR_LIT> ) . addReg ( DstHi ) . addImm ( <STR_LIT> ) ; for ( MachineOperand & MO : I . explicit_operands ( ) ) { if ( ! MO . isReg ( ) || TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) continue ; RBI . constrainGenericRegister ( MO . getReg ( ) , <STR_LIT> , MRI ) ; } I . eraseFromParent ( ) ;


<s> BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstHi ) . add ( Hi1 ) . add ( Hi2 ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( DstLo ) . addImm ( <STR_LIT> ) . addReg ( DstHi ) . addImm ( <STR_LIT> ) ; for ( MachineOperand & MO : I . explicit_operands ( ) ) { if ( ! MO . isReg ( ) || TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) continue ;

RBI . constrainGenericRegister ( MO . getReg ( ) , <STR_LIT> , MRI ) ;


<s> bool <ISA_LIT>InstructionSelector :: selectG_CONSTANT ( MachineInstr & I ) const { MachineBasicBlock * BB = I . getParent ( ) ; MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MachineOperand & ImmOp = I . getOperand ( <NUM_LIT> ) ; if ( ImmOp . isFPImm ( ) ) { const APInt & Imm = ImmOp . getFPImm ( ) -> getValueAPF ( ) . bitcastToAPInt ( ) ; ImmOp . ChangeToImmediate ( Imm . getZExtValue ( ) ) ; } else if ( ImmOp . isCImm ( ) ) { ImmOp . ChangeToImmediate ( ImmOp . getCImm ( ) -> getZExtValue ( ) ) ; } unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Size ; bool IsSgpr ; const RegisterBank * RB = MRI . getRegBankOrNull ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( RB ) { IsSgpr = RB -> getID ( ) == <STR_LIT> ; Size = MRI . getType ( DstReg ) . getSizeInBits ( ) ; } else { const TargetRegisterClass * RC = TRI . getRegClassForReg ( MRI , DstReg ) ; IsSgpr = TRI . isSGPRClass ( RC ) ; Size = TRI . getRegSizeInBits ( * RC ) ; } if ( Size != <NUM_LIT> && Size != <NUM_LIT> ) return false ; unsigned Opcode = IsSgpr ? <STR_LIT> : <STR_LIT> ; if ( Size == <NUM_LIT> ) { I . setDesc ( TII . get ( Opcode ) ) ; I . addImplicitDefUseOperands ( * MF ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } DebugLoc DL = I . getDebugLoc ( ) ; const TargetRegisterClass * RC = IsSgpr ? & <STR_LIT> : & <STR_LIT> ; unsigned LoReg = MRI . createVirtualRegister ( RC ) ; unsigned HiReg = MRI . createVirtualRegister ( RC ) ; const APInt & Imm = APInt ( Size , I . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , LoReg ) . addImm ( Imm . trunc ( <NUM_LIT> ) . getZExtValue ( ) ) ; BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , HiReg ) . addImm ( Imm . ashr ( <NUM_LIT> ) . getZExtValue ( ) ) ; const MachineInstr * RS = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( LoReg ) . addImm ( <STR_LIT> ) . addReg ( HiReg ) . addImm ( <STR_LIT> ) ; I . eraseFromParent ( ) ;

const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand ( RS -> getOperand ( <NUM_LIT> ) , MRI ) ;


<s> IsSgpr = TRI . isSGPRClass ( RC ) ; Size = TRI . getRegSizeInBits ( * RC ) ; } if ( Size != <NUM_LIT> && Size != <NUM_LIT> ) return false ; unsigned Opcode = IsSgpr ? <STR_LIT> : <STR_LIT> ; if ( Size == <NUM_LIT> ) { I . setDesc ( TII . get ( Opcode ) ) ; I . addImplicitDefUseOperands ( * MF ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } DebugLoc DL = I . getDebugLoc ( ) ; const TargetRegisterClass * RC = IsSgpr ? & <STR_LIT> : & <STR_LIT> ; unsigned LoReg = MRI . createVirtualRegister ( RC ) ; unsigned HiReg = MRI . createVirtualRegister ( RC ) ; const APInt & Imm = APInt ( Size , I . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , LoReg ) . addImm ( Imm . trunc ( <NUM_LIT> ) . getZExtValue ( ) ) ; BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , HiReg ) . addImm ( Imm . ashr ( <NUM_LIT> ) . getZExtValue ( ) ) ; const MachineInstr * RS = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( LoReg ) . addImm ( <STR_LIT> ) . addReg ( HiReg ) . addImm ( <STR_LIT> ) ; I . eraseFromParent ( ) ;


<s> MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; DebugLoc DL = I . getDebugLoc ( ) ; unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned PtrReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LoadSize = RBI . getSizeInBits ( DstReg , MRI , TRI ) ;


<s> } MachineInstr * Flat = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addReg ( PtrReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; bool Ret = constrainSelectedInstRegOperands ( * Flat , TII , TRI , RBI ) ; I . eraseFromParent ( ) ;


<s> case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; } MachineInstr * Flat = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; bool Ret = constrainSelectedInstRegOperands ( * Flat , TII , TRI , RBI ) ; I . eraseFromParent ( ) ;


<s> DebugLoc DL = I . getDebugLoc ( ) ; unsigned StoreSize = RBI . getSizeInBits ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , TRI ) ; unsigned Opcode ; switch ( StoreSize ) { default : return false ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ;


<s> MachineFunction * MF = BB -> getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; unsigned Opcode ; unsigned LoadSize = RBI . getSizeInBits ( DstReg , MRI , TRI ) ; if ( ! AddrInfo . empty ( ) && AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) == <NUM_LIT> ) { const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; int64_t EncodedImm = <STR_LIT> ( Subtarget , GEPInfo . Imm ) ; if ( <STR_LIT> ( Subtarget , GEPInfo . Imm ) ) { Opcode = getSmrdOpcode ( <STR_LIT> , LoadSize ) ; MachineInstr * SMRD = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , DstReg ) . addReg ( PtrReg ) . addImm ( EncodedImm ) . addImm ( <NUM_LIT> ) ; return constrainSelectedInstRegOperands ( * SMRD , TII , TRI , RBI ) ; } if ( Subtarget . getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS && isUInt < <NUM_LIT> > ( EncodedImm ) ) { Opcode = getSmrdOpcode ( <STR_LIT> , LoadSize ) ; MachineInstr * SMRD = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , DstReg ) . addReg ( PtrReg ) . addImm ( EncodedImm ) . addImm ( <NUM_LIT> ) ; return constrainSelectedInstRegOperands ( * SMRD , TII , TRI , RBI ) ; } if ( isUInt < <NUM_LIT> > ( GEPInfo . Imm ) ) { Opcode = getSmrdOpcode ( <STR_LIT> , LoadSize ) ; unsigned OffsetReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , OffsetReg ) . addImm ( GEPInfo . Imm ) ; MachineInstr * SMRD = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , DstReg ) . addReg ( PtrReg ) . addReg ( OffsetReg ) . addImm ( <NUM_LIT> ) ; return constrainSelectedInstRegOperands ( * SMRD , TII , TRI , RBI ) ;


<s> const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; unsigned Opcode ; unsigned LoadSize = RBI . getSizeInBits ( DstReg , MRI , TRI ) ; if ( ! AddrInfo . empty ( ) && AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) == <NUM_LIT> ) { const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; int64_t EncodedImm = <STR_LIT> ( Subtarget , GEPInfo . Imm ) ; if ( <STR_LIT> ( Subtarget , GEPInfo . Imm ) ) { Opcode = getSmrdOpcode ( <STR_LIT> , LoadSize ) ; MachineInstr * SMRD = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , DstReg ) . addReg ( PtrReg ) . addImm ( EncodedImm ) . addImm ( <NUM_LIT> ) ; return constrainSelectedInstRegOperands ( * SMRD , TII , TRI , RBI ) ; } if ( Subtarget . getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS && isUInt < <NUM_LIT> > ( EncodedImm ) ) { Opcode = getSmrdOpcode ( <STR_LIT> , LoadSize ) ; MachineInstr * SMRD = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , DstReg ) . addReg ( PtrReg ) . addImm ( EncodedImm ) . addImm ( <NUM_LIT> ) ; return constrainSelectedInstRegOperands ( * SMRD , TII , TRI , RBI ) ; } if ( isUInt < <NUM_LIT> > ( GEPInfo . Imm ) ) { Opcode = getSmrdOpcode ( <STR_LIT> , LoadSize ) ; unsigned OffsetReg = MRI . createVirtualRegister ( & <STR_LIT> ) ;

BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , OffsetReg ) . addImm ( GEPInfo . Imm ) ;


<s> [ = ] ( MachineInstrBuilder & MIB ) { MIB . add ( Root ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } } } ;


<s> unsigned Opcode = Done ? <STR_LIT> : <STR_LIT> ;

return BuildMI ( BB , Insert , DL , TII . get ( Opcode ) ) . addImm ( Tgt ) . addReg ( Reg0 ) . addReg ( Reg1 ) . addReg ( Reg2 ) . addReg ( Reg3 ) . addImm ( VM ) . addImm ( Compr ) . addImm ( Enabled ) ;


<s> static int64_t getConstant ( const MachineInstr * MI ) { return MI -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ;


<s> return MI -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ;


<s> bool <ISA_LIT>InstructionSelector :: select ( MachineInstr & I , CodeGenCoverage & CoverageInfo ) const { if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { if ( I . isCopy ( ) ) return selectCOPY ( I ) ; return true ; } switch ( I . getOpcode ( ) ) { default : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_ADD : return selectG_ADD ( I ) ; case TargetOpcode :: G_INTTOPTR : case TargetOpcode :: G_BITCAST :


<s> bool <ISA_LIT>InstructionSelector :: select ( MachineInstr & I , CodeGenCoverage & CoverageInfo ) const { if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { if ( I . isCopy ( ) ) return selectCOPY ( I ) ; return true ; } switch ( I . getOpcode ( ) ) { default : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_ADD : return selectG_ADD ( I ) ; case TargetOpcode :: G_INTTOPTR : case TargetOpcode :: G_BITCAST : return selectCOPY ( I ) ; case TargetOpcode :: G_CONSTANT : case TargetOpcode :: G_FCONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_GEP : return selectG_GEP ( I ) ; case TargetOpcode :: G_IMPLICIT_DEF : return selectG_IMPLICIT_DEF ( I ) ; case TargetOpcode :: G_INTRIN<ISA_LIT>C : return selectG_INTRIN<ISA_LIT>C ( I , CoverageInfo ) ;


<s> MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const MachineOperand & MO = I . getOperand ( <NUM_LIT> ) ; const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( MO , MRI ) ; if ( RC ) RBI . constrainGenericRegister ( MO . getReg ( ) , * RC , MRI ) ; I . setDesc ( TII . get ( TargetOpcode :: IMPLICIT_DEF ) ) ;


<s> const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( MO , MRI ) ; if ( RC ) RBI . constrainGenericRegister ( MO . getReg ( ) , * RC , MRI ) ; I . setDesc ( TII . get ( TargetOpcode :: IMPLICIT_DEF ) ) ; return true ;


<s> default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return selectImpl ( I , CoverageInfo ) ; case <STR_LIT> : { MachineFunction * MF = I . getParent ( ) -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const ArgDescriptor * InputPtrReg ; const TargetRegisterClass * RC ; const DebugLoc & DL = I . getDebugLoc ( ) ; std :: tie ( InputPtrReg , RC ) = MFI -> getPreloadedValue ( <STR_LIT> ) ; if ( ! InputPtrReg ) report_fatal_error ( <STR_LIT> ) ; BuildMI ( * I . getParent ( ) , & I , DL , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addReg ( MRI . getLiveInVirtReg ( InputPtrReg -> getRegister ( ) ) ) ;


<s> MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned IntrinsicID = I . getOperand ( <NUM_LIT> ) . getIntrinsicID ( ) ; switch ( IntrinsicID ) { case <STR_LIT> : { int64_t Tgt = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; int64_t Enabled = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; int64_t Done = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; int64_t VM = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; MachineInstr * Exp = buildEXP ( TII , & I , Tgt , I . getOperand ( <NUM_LIT> ) . getReg ( ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) , VM , false , Enabled , Done ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * Exp , TII , TRI , RBI ) ; } case <STR_LIT> : { const DebugLoc & DL = I . getDebugLoc ( ) ; int64_t Tgt = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; int64_t Enabled = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; unsigned Reg0 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg1 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ;

unsigned Undef = MRI . createVirtualRegister ( & <STR_LIT> ) ;


<s> } case <STR_LIT> : { const DebugLoc & DL = I . getDebugLoc ( ) ; int64_t Tgt = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; int64_t Enabled = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; unsigned Reg0 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg1 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Undef = MRI . createVirtualRegister ( & <STR_LIT> ) ; int64_t Done = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; int64_t VM = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , Undef ) ; MachineInstr * Exp = buildEXP ( TII , & I , Tgt , Reg0 , Reg1 , Undef , Undef , VM , true , Enabled , Done ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * Exp , TII , TRI , RBI ) ; } } return false ;


<s> unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; int64_t EncodedImm = <STR_LIT> ( Subtarget , GEPInfo . Imm ) ; if ( <STR_LIT> ( Subtarget , GEPInfo . Imm ) ) { Opcode = getSmrdOpcode ( <STR_LIT> , LoadSize ) ; MachineInstr * SMRD = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , DstReg ) . addReg ( PtrReg ) . addImm ( EncodedImm ) . addImm ( <NUM_LIT> ) ; return constrainSelectedInstRegOperands ( * SMRD , TII , TRI , RBI ) ; } if ( Subtarget . getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS && isUInt < <NUM_LIT> > ( EncodedImm ) ) { Opcode = getSmrdOpcode ( <STR_LIT> , LoadSize ) ; MachineInstr * SMRD = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , DstReg ) . addReg ( PtrReg ) . addImm ( EncodedImm ) . addImm ( <NUM_LIT> ) ; return constrainSelectedInstRegOperands ( * SMRD , TII , TRI , RBI ) ; } if ( isUInt < <NUM_LIT> > ( GEPInfo . Imm ) ) { Opcode = getSmrdOpcode ( <STR_LIT> , LoadSize ) ; unsigned OffsetReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , OffsetReg ) . addImm ( GEPInfo . Imm ) ; MachineInstr * SMRD = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , DstReg ) . addReg ( PtrReg ) . addReg ( OffsetReg ) . addImm ( <NUM_LIT> ) ; return constrainSelectedInstRegOperands ( * SMRD , TII , TRI , RBI ) ; }


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectVOP3Mods ( MachineOperand & Root ) const { return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . add ( Root ) ; } , [ = ] ( MachineInstrBuilder & MIB ) {


<s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const <ISA_LIT>Subtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI ) : InstructionSelector ( ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , RBI ( RBI ) , AMDGPUA<ISA_LIT> ( STI . get<ISA_LIT>AS ( ) ) {


<s> break ; case TargetOpcode :: G_ADD : return selectG_ADD ( I ) ; case TargetOpcode :: G_CONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_GEP : return selectG_GEP ( I ) ; case TargetOpcode :: G_LOAD : return selectG_LOAD ( I ) ;


<s> case TargetOpcode :: G_GEP : return selectG_GEP ( I ) ; case TargetOpcode :: G_LOAD : return selectG_LOAD ( I ) ; case TargetOpcode :: G_STORE : return selectG_STORE ( I ) ; }


<s> BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , LoReg ) . addImm ( Imm . trunc ( <NUM_LIT> ) . getZExtValue ( ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , HiReg ) . addImm ( Imm . ashr ( <NUM_LIT> ) . getZExtValue ( ) ) ;

BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( LoReg ) . addImm ( <STR_LIT> ) . addReg ( HiReg ) . addImm ( <STR_LIT> ) ;


<s> unsigned LoReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned HiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; const APInt & Imm = I . getOperand ( <NUM_LIT> ) . getCImm ( ) -> getValue ( ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , LoReg ) . addImm ( Imm . trunc ( <NUM_LIT> ) . getZExtValue ( ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , HiReg ) . addImm ( Imm . ashr ( <NUM_LIT> ) . getZExtValue ( ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( LoReg ) . addImm ( <STR_LIT> ) . addReg ( HiReg ) . addImm ( <STR_LIT> ) ; I . eraseFromParent ( ) ; return RBI . constrainGenericRegister ( DstReg , <STR_LIT> , MRI ) ;


<s> MachineInstr * Flat = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;

bool Ret = constrainSelectedInstRegOperands ( * Flat , TII , TRI , RBI ) ;


<s> MachineInstr * Flat = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; bool Ret = constrainSelectedInstRegOperands ( * Flat , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return Ret ;


<s> const TargetRegisterClass & RegRC = IsVGPR ? <STR_LIT> : <STR_LIT> ; LLT Ty = MRI -> getType ( DstReg ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForTypeOnBank ( Ty , * DstRB , * MRI ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForTypeOnBank ( Ty , * SrcRB , * MRI ) ; if ( ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) || ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; const DebugLoc & DL = I . getDebugLoc ( ) ; Register ImmReg = MRI -> createVirtualRegister ( & RegRC ) ; BuildMI ( * BB , & I , DL , TII . get ( MovOpc ) , ImmReg ) . addImm ( Mask ) ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) { BuildMI ( * BB , & I , DL , TII . get ( NewOpc ) , DstReg ) . addReg ( SrcReg ) . addReg ( ImmReg ) ; I . eraseFromParent ( ) ; return true ; } Register HiReg = MRI -> createVirtualRegister ( & RegRC ) ; Register LoReg = MRI -> createVirtualRegister ( & RegRC ) ; Register MaskLo = MRI -> createVirtualRegister ( & RegRC ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , LoReg ) . addReg ( SrcReg , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , HiReg ) . addReg ( SrcReg , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( NewOpc ) , MaskLo ) . addReg ( LoReg ) . addReg ( ImmReg ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( MaskLo ) . addImm ( <STR_LIT> ) . addReg ( HiReg ) . addImm ( <STR_LIT> ) ;


<s> const uint64_t Mask = * MaskVal ; MachineBasicBlock * BB = I . getParent ( ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const RegisterBank * DstRB = RBI . getRegBank ( DstReg , * MRI , TRI ) ; const RegisterBank * SrcRB = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; const bool IsVGPR = DstRB -> getID ( ) == <STR_LIT> ; unsigned NewOpc = IsVGPR ? <STR_LIT> : <STR_LIT> ; unsigned MovOpc = IsVGPR ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass & RegRC = IsVGPR ? <STR_LIT> : <STR_LIT> ; LLT Ty = MRI -> getType ( DstReg ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForTypeOnBank ( Ty , * DstRB , * MRI ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForTypeOnBank ( Ty , * SrcRB , * MRI ) ; if ( ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) || ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; const DebugLoc & DL = I . getDebugLoc ( ) ; Register ImmReg = MRI -> createVirtualRegister ( & RegRC ) ;

BuildMI ( * BB , & I , DL , TII . get ( MovOpc ) , ImmReg ) . addImm ( Mask ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { const MachineOperand & GEPOp = PtrMI -> getOperand ( i ) ; const MachineInstr * OpDef = MRI . getUniqueVRegDef ( GEPOp . getReg ( ) ) ; assert ( OpDef ) ; if ( i == <NUM_LIT> && isConstant ( * OpDef ) ) { assert ( GEPInfo . Imm == <NUM_LIT> ) ; GEPInfo . Imm = OpDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ; continue ; } const RegisterBank * OpBank = RBI . getRegBank ( GEPOp . getReg ( ) , MRI , TRI ) ;

if ( OpBank -> getID ( ) == <STR_LIT> ) GEPInfo . SgprParts . push_back ( GEPOp . getReg ( ) ) ;


<s> assert ( OpDef ) ; if ( i == <NUM_LIT> && isConstant ( * OpDef ) ) { assert ( GEPInfo . Imm == <NUM_LIT> ) ; GEPInfo . Imm = OpDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ; continue ; } const RegisterBank * OpBank = RBI . getRegBank ( GEPOp . getReg ( ) , MRI , TRI ) ; if ( OpBank -> getID ( ) == <STR_LIT> ) GEPInfo . SgprParts . push_back ( GEPOp . getReg ( ) ) ;

else GEPInfo . VgprParts . push_back ( GEPOp . getReg ( ) ) ;


<s> Register Reg = MO . getReg ( ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( Reg , <NUM_LIT> , ComposedSubIdx ) ; return MachineOperand :: CreateReg ( DstReg , MO . isDef ( ) , MO . isImplicit ( ) , MO . isKill ( ) , MO . isDead ( ) , MO . isUndef ( ) , MO . isEarlyClobber ( ) , <NUM_LIT> , MO . isDebug ( ) , MO . isInternalRead ( ) ) ; } assert ( MO . isImm ( ) ) ; APInt Imm ( <NUM_LIT> , MO . getImm ( ) ) ; switch ( SubIdx ) { default :


<s> if ( ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS || AS == <ISA_LIT>AS :: REGION_ADDRESS ) && STI . ldsRequiresM0Init ( ) ) { BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; }


<s> void <ISA_LIT>InstructionSelector :: initM0 ( MachineInstr & I ) const { MachineBasicBlock * BB = I . getParent ( ) ; MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const LLT PtrTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned AS = PtrTy . getAddressSpace ( ) ;

if ( ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS || AS == <ISA_LIT>AS :: REGION_ADDRESS ) && STI . ldsRequiresM0Init ( ) ) {


<s> bool <ISA_LIT>InstructionSelector :: isDSOffsetLegal ( const MachineRegisterInfo & MRI , const MachineOperand & Base , int64_t Offset , unsigned OffsetBits ) const { if ( ( OffsetBits == <NUM_LIT> && ! isUInt < <NUM_LIT> > ( Offset ) ) || ( OffsetBits == <NUM_LIT> && ! isUInt < <NUM_LIT> > ( Offset ) ) ) return false ;

if ( STI . hasUsableDSOffset ( ) || STI . unsafeDSOffsetFoldingEnabled ( ) ) return true ;


<s> if ( STI . hasUsableDSOffset ( ) || STI . unsafeDSOffsetFoldingEnabled ( ) ) return true ; return signBitIsZero ( Base , MRI ) ;


<s> const LLT Ty = MRI . getType ( Reg ) ; return Ty . isValid ( ) && Ty . getSizeInBits ( ) == <NUM_LIT> ; } const RegisterBank * RB = RegClassOrBank . get < const RegisterBank * > ( ) ; return RB -> getID ( ) == <STR_LIT> ;


<s> int64_t ConstAddr = <NUM_LIT> ; if ( isBaseWithConstantOffset ( Root , MRI ) ) { const MachineOperand & LHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineOperand & RHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineInstr * LHSDef = MRI . getVRegDef ( LHS . getReg ( ) ) ; const MachineInstr * RHSDef = MRI . getVRegDef ( RHS . getReg ( ) ) ; if ( LHSDef && RHSDef ) { int64_t PossibleOffset = RHSDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ; if ( isDSOffsetLegal ( MRI , LHS , PossibleOffset , <NUM_LIT> ) ) { return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . add ( LHS ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( PossibleOffset ) ; } } } ; } } } else if ( RootDef -> getOpcode ( ) == <STR_LIT> ) { } else if ( mi_match ( Root . getReg ( ) , MRI , m_ICst ( ConstAddr ) ) ) { } return { {

[ = ] ( MachineInstrBuilder & MIB ) { MIB . add ( Root ) ; } , [ = ] ( MachineInstrBuilder & MIB ) {


<s> return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . add ( Root ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } } } ; } int64_t ConstAddr = <NUM_LIT> ; if ( isBaseWithConstantOffset ( Root , MRI ) ) { const MachineOperand & LHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineOperand & RHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineInstr * LHSDef = MRI . getVRegDef ( LHS . getReg ( ) ) ; const MachineInstr * RHSDef = MRI . getVRegDef ( RHS . getReg ( ) ) ; if ( LHSDef && RHSDef ) { int64_t PossibleOffset = RHSDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ; if ( isDSOffsetLegal ( MRI , LHS , PossibleOffset , <NUM_LIT> ) ) { return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . add ( LHS ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( PossibleOffset ) ; } } } ; } } } else if ( RootDef -> getOpcode ( ) == <STR_LIT> ) { } else if ( mi_match ( Root . getReg ( ) , MRI , m_ICst ( ConstAddr ) ) ) { } return { {


<s> MachineInstr * MI = Root . getParent ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; InstructionSelector :: ComplexRendererFns Default = { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Root . getReg ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } } } ; if ( ! STI . hasFlatInstOffsets ( ) ) return Default ; const MachineInstr * OpDef = MRI . getVRegDef ( Root . getReg ( ) ) ; if ( ! OpDef || OpDef -> getOpcode ( ) != <STR_LIT> ) return Default ; Optional < int64_t > Offset = getConstantVRegVal ( OpDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! Offset . hasValue ( ) ) return Default ;

unsigned AddrSpace = ( * MI -> memoperands_begin ( ) ) -> getAddrSpace ( ) ;


<s> I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * Add , TII , TRI , RBI ) ; } assert ( ! Sub && <STR_LIT> ) ; const TargetRegisterClass & RC = IsSALU ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass & HalfRC = IsSALU ? <STR_LIT> : <STR_LIT> ; MachineOperand Lo1 ( getSubOperand64 ( I . getOperand ( <NUM_LIT> ) , HalfRC , <STR_LIT> ) ) ; MachineOperand Lo2 ( getSubOperand64 ( I . getOperand ( <NUM_LIT> ) , HalfRC , <STR_LIT> ) ) ; MachineOperand Hi1 ( getSubOperand64 ( I . getOperand ( <NUM_LIT> ) , HalfRC , <STR_LIT> ) ) ; MachineOperand Hi2 ( getSubOperand64 ( I . getOperand ( <NUM_LIT> ) , HalfRC , <STR_LIT> ) ) ; Register DstLo = MRI . createVirtualRegister ( & HalfRC ) ; Register DstHi = MRI . createVirtualRegister ( & HalfRC ) ; if ( IsSALU ) { BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstLo ) . add ( Lo1 ) . add ( Lo2 ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstHi ) . add ( Hi1 ) . add ( Hi2 ) ; } else { const TargetRegisterClass * CarryRC = TRI . getWaveMaskRegClass ( ) ; Register CarryReg = MRI . createVirtualRegister ( CarryRC ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstLo ) . addDef ( CarryReg ) . add ( Lo1 ) . add ( Lo2 ) . addImm ( <NUM_LIT> ) ; MachineInstr * Addc = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstHi ) . addDef ( MRI . createVirtualRegister ( CarryRC ) , RegState :: Dead ) . add ( Hi1 ) . add ( Hi2 ) . addReg ( CarryReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; if ( ! constrainSelectedInstRegOperands ( * Addc , TII , TRI , RBI ) ) return false ; } BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( DstLo ) . addImm ( <STR_LIT> ) . addReg ( DstHi ) . addImm ( <STR_LIT> ) ; if ( ! RBI . constrainGenericRegister ( DstReg , RC , MRI ) ) return false ; I . eraseFromParent ( ) ; return true ;


<s> unsigned Size = RBI . getSizeInBits ( DstReg , MRI , TRI ) ; const RegisterBank * DstRB = RBI . getRegBank ( DstReg , MRI , TRI ) ; if ( DstRB -> getID ( ) == <STR_LIT> ) { const TargetRegisterClass * RC = TRI . getBoolRC ( ) ; unsigned InstOpc = getLogicalBitOpcode ( I . getOpcode ( ) , RC == & <STR_LIT> ) ; I . setDesc ( TII . get ( InstOpc ) ) ; if ( Src0 . isUndef ( ) && ! MRI . getRegClassOrNull ( Src0 . getReg ( ) ) ) MRI . setRegClass ( Src0 . getReg ( ) , RC ) ; if ( Src1 . isUndef ( ) && ! MRI . getRegClassOrNull ( Src1 . getReg ( ) ) ) MRI . setRegClass ( Src1 . getReg ( ) , RC ) ; return RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ; } if ( DstRB -> getID ( ) == <STR_LIT> ) { unsigned InstOpc = getLogicalBitOpcode ( I . getOpcode ( ) , Size > <NUM_LIT> ) ;


<s> if ( ! MRI . getRegClassOrNull ( CondReg ) ) MRI . setRegClass ( CondReg , ConstrainRC ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , CondPhysReg ) . addReg ( CondReg ) ;

BuildMI ( * BB , & I , DL , TII . get ( BrOpcode ) ) . addMBB ( I . getOperand ( <NUM_LIT> ) . getMBB ( ) ) ;


<s> } else if ( isVCC ( CondReg , MRI ) ) { CondPhysReg = TRI . getVCC ( ) ; BrOpcode = <STR_LIT> ; ConstrainRC = TRI . getBoolRC ( ) ; } else return false ; if ( ! MRI . getRegClassOrNull ( CondReg ) ) MRI . setRegClass ( CondReg , ConstrainRC ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , CondPhysReg ) . addReg ( CondReg ) ; BuildMI ( * BB , & I , DL , TII . get ( BrOpcode ) ) . addMBB ( I . getOperand ( <NUM_LIT> ) . getMBB ( ) ) ;


<s> IsSgpr = TRI . isSGPRClass ( RC ) ; Size = TRI . getRegSizeInBits ( * RC ) ; } if ( Size != <NUM_LIT> && Size != <NUM_LIT> ) return false ; unsigned Opcode = IsSgpr ? <STR_LIT> : <STR_LIT> ; if ( Size == <NUM_LIT> ) { I . setDesc ( TII . get ( Opcode ) ) ; I . addImplicitDefUseOperands ( * MF ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } DebugLoc DL = I . getDebugLoc ( ) ; const TargetRegisterClass * RC = IsSgpr ? & <STR_LIT> : & <STR_LIT> ; Register LoReg = MRI . createVirtualRegister ( RC ) ; Register HiReg = MRI . createVirtualRegister ( RC ) ; const APInt & Imm = APInt ( Size , I . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , LoReg ) . addImm ( Imm . trunc ( <NUM_LIT> ) . getZExtValue ( ) ) ; BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , HiReg ) . addImm ( Imm . ashr ( <NUM_LIT> ) . getZExtValue ( ) ) ; const MachineInstr * RS = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( LoReg ) . addImm ( <STR_LIT> ) . addReg ( HiReg ) . addImm ( <STR_LIT> ) ; I . eraseFromParent ( ) ; const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand ( RS -> getOperand ( <NUM_LIT> ) , MRI ) ; if ( ! DstRC ) return true ;

return RBI . constrainGenericRegister ( DstReg , * DstRC , MRI ) ;


<s> bool <ISA_LIT>InstructionSelector :: selectG_EXTRACT ( MachineInstr & I ) const { MachineBasicBlock * BB = I . getParent ( ) ; MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; assert ( I . getOperand ( <NUM_LIT> ) . getImm ( ) % <NUM_LIT> == <NUM_LIT> ) ;

unsigned SubReg = TRI . getSubRegFromChannel ( I . getOperand ( <NUM_LIT> ) . getImm ( ) / <NUM_LIT> ) ;


<s> bool <ISA_LIT>InstructionSelector :: selectG_FRAME_INDEX ( MachineInstr & I ) const { MachineBasicBlock * BB = I . getParent ( ) ; MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const RegisterBank * DstRB = RBI . getRegBank ( DstReg , MRI , TRI ) ; const bool IsVGPR = DstRB -> getID ( ) == <STR_LIT> ;

I . setDesc ( TII . get ( IsVGPR ? <STR_LIT> : <STR_LIT> ) ) ;


<s> int Opcode = getV_CMPOpcode ( Pred , Size ) ; if ( Opcode == - <NUM_LIT> ) return false ; MachineInstr * ICmp = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; RBI . constrainGenericRegister ( ICmp -> getOperand ( <NUM_LIT> ) . getReg ( ) , * TRI . getBoolRC ( ) , MRI ) ; bool Ret = constrainSelectedInstRegOperands ( * ICmp , TII , TRI , RBI ) ; I . eraseFromParent ( ) ;


<s> MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const MachineOperand & MO = I . getOperand ( <NUM_LIT> ) ; const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( MO , MRI ) ; if ( ( ! RC && ! MRI . getRegBankOrNull ( MO . getReg ( ) ) ) || ( RC && RBI . constrainGenericRegister ( MO . getReg ( ) , * RC , MRI ) ) ) { I . setDesc ( TII . get ( TargetOpcode :: IMPLICIT_DEF ) ) ; return true ; }


<s> for ( const MachineOperand & MO : Ins -> operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) continue ; const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( MO , MRI ) ; if ( ! RC ) continue ; RBI . constrainGenericRegister ( MO . getReg ( ) , * RC , MRI ) ; }


<s> DebugLoc DL = I . getDebugLoc ( ) ; MachineInstr * Ins = BuildMI ( * BB , & I , DL , TII . get ( TargetOpcode :: INSERT_SUBREG ) ) . addDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( SubReg ) ; for ( const MachineOperand & MO : Ins -> operands ( ) ) { if ( ! MO . isReg ( ) ) continue ;

if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) continue ;


<s> MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ;

Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> int64_t Done = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; int64_t VM = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , Undef ) ; MachineInstr * Exp = buildEXP ( TII , & I , Tgt , Reg0 , Reg1 , Undef , Undef , VM , true , Enabled , Done ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * Exp , TII , TRI , RBI ) ; } case <STR_LIT> : { BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ; if ( ! MRI . getRegClassOrNull ( Reg ) ) MRI . setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ; return true ; } default : return selectImpl ( I , * CoverageInfo ) ;


<s> int64_t Enabled = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; int64_t Done = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; int64_t VM = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; MachineInstr * Exp = buildEXP ( TII , & I , Tgt , I . getOperand ( <NUM_LIT> ) . getReg ( ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) , VM , false , Enabled , Done ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * Exp , TII , TRI , RBI ) ; } case <STR_LIT> : { const DebugLoc & DL = I . getDebugLoc ( ) ; int64_t Tgt = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ;


<s> const unsigned SrcSize = SrcTy . getSizeInBits ( ) ; if ( SrcSize < <NUM_LIT> ) return false ; const DebugLoc & DL = MI . getDebugLoc ( ) ; const RegisterBank * DstBank = RBI . getRegBank ( DstReg , MRI , TRI ) ; const unsigned DstSize = DstTy . getSizeInBits ( ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForSizeOnBank ( DstSize , * DstBank , MRI ) ; if ( ! DstRC ) return false ; ArrayRef < int16_t > SubRegs = TRI . getRegSplitParts ( DstRC , SrcSize / <NUM_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * BB , & MI , DL , TII . get ( TargetOpcode :: REG_SEQUENCE ) , DstReg ) ; for ( int I = <NUM_LIT> , E = MI . getNumOperands ( ) - <NUM_LIT> ; I != E ; ++ I ) { MachineOperand & Src = MI . getOperand ( I + <NUM_LIT> ) ; MIB . addReg ( Src . getReg ( ) , getUndefRegState ( Src . isUndef ( ) ) ) ; MIB . addImm ( SubRegs [ I ] ) ; const TargetRegisterClass * SrcRC = TRI . getConstrainedRegClassForOperand ( Src , MRI ) ; if ( SrcRC && ! RBI . constrainGenericRegister ( Src . getReg ( ) , * SrcRC , MRI ) ) return false ; }

if ( ! RBI . constrainGenericRegister ( DstReg , * DstRC , MRI ) ) return false ;


<s> if ( isSCC ( CCReg , MRI ) ) { unsigned SelectOpcode = Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; MachineInstr * CopySCC = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( CCReg ) ; if ( ! MRI . getRegClassOrNull ( CCReg ) ) MRI . setRegClass ( CCReg , TRI . getConstrainedRegClassForOperand ( CCOp , MRI ) ) ; MachineInstr * Select = BuildMI ( * BB , & I , DL , TII . get ( SelectOpcode ) , DstReg ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; bool Ret = constrainSelectedInstRegOperands ( * Select , TII , TRI , RBI ) | constrainSelectedInstRegOperands ( * CopySCC , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return Ret ; } if ( Size > <NUM_LIT> ) return false ; MachineInstr * Select = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . add ( I . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ;

bool Ret = constrainSelectedInstRegOperands ( * Select , TII , TRI , RBI ) ;


<s> const RegisterBank * DstRB = RBI . getRegBank ( DstReg , MRI , TRI ) ; const RegisterBank * SrcRB = RBI . getRegBank ( SrcReg , MRI , TRI ) ; if ( SrcRB != DstRB ) return false ; unsigned DstSize = DstTy . getSizeInBits ( ) ; unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForSizeOnBank ( SrcSize , * SrcRB , MRI ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForSizeOnBank ( DstSize , * DstRB , MRI ) ; if ( SrcSize > <NUM_LIT> ) { int SubRegIdx = sizeToSubRegIndex ( DstSize ) ; if ( SubRegIdx == - <NUM_LIT> ) return false ; SrcRC = TRI . getSubClassWithSubReg ( SrcRC , SubRegIdx ) ; if ( ! SrcRC ) return false ; I . getOperand ( <NUM_LIT> ) . setSubReg ( SubRegIdx ) ;


<s> LLT DstTy = MRI . getType ( DstReg0 ) ; LLT SrcTy = MRI . getType ( SrcReg ) ; const unsigned DstSize = DstTy . getSizeInBits ( ) ; const unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; const RegisterBank * SrcBank = RBI . getRegBank ( SrcReg , MRI , TRI ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForSizeOnBank ( SrcSize , * SrcBank , MRI ) ; if ( ! SrcRC || ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , MRI ) ) return false ; const unsigned SrcFlags = getUndefRegState ( Src . isUndef ( ) ) ; ArrayRef < int16_t > SubRegs = TRI . getRegSplitParts ( SrcRC , DstSize / <NUM_LIT> ) ; for ( int I = <NUM_LIT> , E = NumDst ; I != E ; ++ I ) { MachineOperand & Dst = MI . getOperand ( I ) ; BuildMI ( * BB , & MI , DL , TII . get ( TargetOpcode :: COPY ) , Dst . getReg ( ) ) . addReg ( SrcReg , SrcFlags , SubRegs [ I ] ) ; const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand ( Dst , MRI ) ;

if ( DstRC && ! RBI . constrainGenericRegister ( Dst . getReg ( ) , * DstRC , MRI ) ) return false ;


<s> assert ( Offset == <NUM_LIT> ) ; Optional < int > FI ; Register VAddr = Root . getReg ( ) ; if ( const MachineInstr * RootDef = MRI . getVRegDef ( Root . getReg ( ) ) ) { if ( isBaseWithConstantOffset ( Root , MRI ) ) { const MachineOperand & LHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineOperand & RHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineInstr * LHSDef = MRI . getVRegDef ( LHS . getReg ( ) ) ; const MachineInstr * RHSDef = MRI . getVRegDef ( RHS . getReg ( ) ) ; if ( LHSDef && RHSDef ) { int64_t PossibleOffset = RHSDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ; if ( <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( PossibleOffset ) && ( ! STI . privateMemoryResourceIsRangeChecked ( ) || signBitIsZero ( LHS , MRI ) ) ) { if ( LHSDef -> getOpcode ( ) == <STR_LIT> ) FI = LHSDef -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; else VAddr = LHS . getReg ( ) ; Offset = PossibleOffset ; } } } else if ( RootDef -> getOpcode ( ) == <STR_LIT> ) { FI = RootDef -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; } } Register SOffset = FI . hasValue ( ) ? Info -> getStackPtrOffsetReg ( ) : Info -> getScratchWaveOffsetReg ( ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Info -> getScratchRSrcReg ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { if ( FI . hasValue ( ) ) MIB . addFrameIndex ( FI . getValue ( ) ) ; else MIB . addReg ( VAddr ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( SOffset ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset ) ; } } } ;


<s> const MachineMemOperand * MMO = * MI -> memoperands_begin ( ) ; const MachinePointerInfo & PtrInfo = MMO -> getPointerInfo ( ) ; Register SOffsetReg = isStackPtrRelative ( PtrInfo ) ? Info -> getStackPtrOffsetReg ( ) : Info -> getScratchWaveOffsetReg ( ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Info -> getScratchRSrcReg ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( SOffsetReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset ) ;


<s> const TargetRegisterClass * DefRC = RegClassOrBank . dyn_cast < const TargetRegisterClass * > ( ) ; if ( ! DefRC ) { if ( ! DefTy . isValid ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } const RegisterBank & RB = * RegClassOrBank . get < const RegisterBank * > ( ) ; if ( RB . getID ( ) == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; }

DefRC = TRI . getRegClassForTypeOnBank ( DefTy , RB , MRI ) ;


<s> const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; if ( ! <STR_LIT> ( STI , GEPInfo . Imm ) ) return None ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; int64_t EncodedImm = <STR_LIT> ( STI , GEPInfo . Imm ) ; return { {

[ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) {


<s> const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; if ( ! <STR_LIT> ( STI , GEPInfo . Imm ) ) return None ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; int64_t EncodedImm = <STR_LIT> ( STI , GEPInfo . Imm ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( EncodedImm ) ;


<s> SmallVector < GEPInfo , <NUM_LIT> > AddrInfo ; getAddrModeInfo ( * Root . getParent ( ) , MRI , AddrInfo ) ; if ( AddrInfo . empty ( ) || AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) != <NUM_LIT> ) return None ; const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; int64_t EncodedImm = <STR_LIT> ( STI , GEPInfo . Imm ) ; if ( ! isUInt < <NUM_LIT> > ( EncodedImm ) ) return None ;


<s> SmallVector < GEPInfo , <NUM_LIT> > AddrInfo ; getAddrModeInfo ( * Root . getParent ( ) , MRI , AddrInfo ) ; if ( AddrInfo . empty ( ) || AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) != <NUM_LIT> ) return None ; const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; int64_t EncodedImm = <STR_LIT> ( STI , GEPInfo . Imm ) ; if ( ! isUInt < <NUM_LIT> > ( EncodedImm ) ) return None ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( EncodedImm ) ;


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectSmrdSgpr ( MachineOperand & Root ) const { MachineInstr * MI = Root . getParent ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; SmallVector < GEPInfo , <NUM_LIT> > AddrInfo ; getAddrModeInfo ( * MI , MRI , AddrInfo ) ; if ( AddrInfo . empty ( ) || AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) != <NUM_LIT> ) return None ; const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; if ( ! GEPInfo . Imm || ! isUInt < <NUM_LIT> > ( GEPInfo . Imm ) ) return None ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; Register OffsetReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , OffsetReg ) . addImm ( GEPInfo . Imm ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( OffsetReg ) ;


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectSmrdSgpr ( MachineOperand & Root ) const { MachineInstr * MI = Root . getParent ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; SmallVector < GEPInfo , <NUM_LIT> > AddrInfo ; getAddrModeInfo ( * MI , MRI , AddrInfo ) ; if ( AddrInfo . empty ( ) || AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) != <NUM_LIT> ) return None ; const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; if ( ! GEPInfo . Imm || ! isUInt < <NUM_LIT> > ( GEPInfo . Imm ) ) return None ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; Register OffsetReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , OffsetReg ) . addImm ( GEPInfo . Imm ) ; return { {


<s> [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Src ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Mods ) ; }


<s> unsigned Mods ; std :: tie ( Src , Mods ) = selectVOP3ModsImpl ( Root . getReg ( ) , MRI ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Src ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Mods ) ; } } } ;


<s> unsigned Mods ; std :: tie ( Src , Mods ) = selectVOP3ModsImpl ( Root . getReg ( ) , MRI ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Src ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Mods ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } } } ;


<s> MI = MRI . getVRegDef ( Src ) ; } if ( MI && MI -> getOpcode ( ) == <STR_LIT> ) { Src = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Mods |= <STR_LIT> ; } return std :: make_pair ( Src , Mods ) ;


<s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const GCNSubtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI , const <ISA_LIT>TargetMachine & TM ) : TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , RBI ( RBI ) , TM ( TM ) , STI ( STI ) , EnableLateStructurizeCFG ( <ISA_LIT>TargetMachine :: EnableLateStructurizeCFG ) , {


<s> const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ; const TargetRegisterClass * SrcRC = TRI . getConstrainedRegClassForOperand ( Src , * MRI ) ; if ( ! DstRC || DstRC != SrcRC ) return false ; return RBI . constrainGenericRegister ( Dst . getReg ( ) , * DstRC , * MRI ) && RBI . constrainGenericRegister ( Src . getReg ( ) , * SrcRC , * MRI ) ;


<s> MI . addOperand ( * MF , MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; if ( MRI -> getType ( Dst . getReg ( ) ) == LLT :: scalar ( <NUM_LIT> ) ) return false ; const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ;

const TargetRegisterClass * SrcRC = TRI . getConstrainedRegClassForOperand ( Src , * MRI ) ;


<s> return Def -> getOpcode ( ) == <STR_LIT> ? Def -> getOperand ( <NUM_LIT> ) . getReg ( ) : Register ( ) ;


<s> static bool parseTexFail ( uint64_t TexFailCtrl , bool & TFE , bool & LWE , bool & IsTexFail ) { if ( TexFailCtrl ) IsTexFail = true ; TFE = ( TexFailCtrl & <NUM_LIT> ) ? true : false ; TexFailCtrl &= ~ ( uint64_t ) <NUM_LIT> ; LWE = ( TexFailCtrl & <NUM_LIT> ) ? true : false ; TexFailCtrl &= ~ ( uint64_t ) <NUM_LIT> ;


<s> bool <ISA_LIT>InstructionSelector :: selectBVHIntrinsic ( MachineInstr & MI ) const { MI . setDesc ( TII . get ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . addImplicitDefUseOperands ( * MI . getParent ( ) -> getParent ( ) ) ; return true ;


<s> MI . setDesc ( TII . get ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . addImplicitDefUseOperands ( * MI . getParent ( ) -> getParent ( ) ) ;


<s> const RegisterBank * DstBank = RBI . getRegBank ( Dst , * MRI , TRI ) ; if ( DstBank -> getID ( ) != <STR_LIT> ) return false ; Register Src0 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI -> getType ( Src0 ) != S32 ) return false ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineBasicBlock * BB = MI . getParent ( ) ; auto ConstSrc1 = getAnyConstantVRegValWithLookThrough ( Src1 , * MRI , true , true ) ; if ( ConstSrc1 ) { auto ConstSrc0 = getAnyConstantVRegValWithLookThrough ( Src0 , * MRI , true , true ) ; if ( ConstSrc0 ) { const int64_t K0 = ConstSrc0 -> Value . getSExtValue ( ) ; const int64_t K1 = ConstSrc1 -> Value . getSExtValue ( ) ; uint32_t Lo16 = static_cast < uint32_t > ( K0 ) & <NUM_LIT> ; uint32_t Hi16 = static_cast < uint32_t > ( K1 ) & <NUM_LIT> ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , Dst ) . addImm ( Lo16 | ( Hi16 << <NUM_LIT> ) ) ; MI . eraseFromParent ( ) ; return RBI . constrainGenericRegister ( Dst , <STR_LIT> , * MRI ) ; } } MachineInstr * Src1Def = getDefIgnoringCopies ( Src1 , * MRI ) ; if ( Src1Def && Src1Def -> getOpcode ( ) == <STR_LIT> ) { MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . removeOperand ( <NUM_LIT> ) ; return RBI . constrainGenericRegister ( Dst , <STR_LIT> , * MRI ) && RBI . constrainGenericRegister ( Src0 , <STR_LIT> , * MRI ) ; } Register ShiftSrc0 ; Register ShiftSrc1 ; bool Shift0 = mi_match ( Src0 , * MRI , m_OneUse ( m_GLShr ( m_Reg ( ShiftSrc0 ) , m_SpecificICst ( <NUM_LIT> ) ) ) ) ; bool Shift1 = mi_match ( Src1 , * MRI , m_OneUse ( m_GLShr ( m_Reg ( ShiftSrc1 ) , m_SpecificICst ( <NUM_LIT> ) ) ) ) ; unsigned Opc = <STR_LIT> ; if ( Shift0 && Shift1 ) { Opc = <STR_LIT> ; MI . getOperand ( <NUM_LIT> ) . setReg ( ShiftSrc0 ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( ShiftSrc1 ) ; } else if ( Shift1 ) { Opc = <STR_LIT> ; MI . getOperand ( <NUM_LIT> ) . setReg ( ShiftSrc1 ) ; } else if ( Shift0 && ConstSrc1 && ConstSrc1 -> Value == <NUM_LIT> ) { auto MIB = BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , Dst ) . addReg ( ShiftSrc0 ) . addImm ( <NUM_LIT> ) ; MI . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ; }


<s> return selectInterpP1F16 ( I ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : return selectWritelane ( I ) ; case <STR_LIT> : return selectDivScale ( I ) ; case <STR_LIT> : return selectIntrinsicIcmp ( I ) ; case <STR_LIT> : return selectBallot ( I ) ; case <STR_LIT> : return selectRelocConstant ( I ) ; case <STR_LIT> : return selectGroupStaticSize ( I ) ; case <STR_LIT> : return selectReturnAddress ( I ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> I . eraseFromParent ( ) ; return true ; } Register HiReg = MRI -> createVirtualRegister ( & RegRC ) ; Register LoReg = MRI -> createVirtualRegister ( & RegRC ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , LoReg ) . addReg ( SrcReg , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , HiReg ) . addReg ( SrcReg , <NUM_LIT> , <STR_LIT> ) ; Register MaskedLo , MaskedHi ; if ( CanCopyLow32 ) { MaskedLo = LoReg ; } else { Register MaskLo = MRI -> createVirtualRegister ( & RegRC ) ; MaskedLo = MRI -> createVirtualRegister ( & RegRC ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , MaskLo ) . addReg ( MaskReg , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( NewOpc ) , MaskedLo ) . addReg ( LoReg ) . addReg ( MaskLo ) ; } if ( CanCopyHi32 ) { MaskedHi = HiReg ; } else { Register MaskHi = MRI -> createVirtualRegister ( & RegRC ) ; MaskedHi = MRI -> createVirtualRegister ( & RegRC ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , MaskHi ) . addReg ( MaskReg , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( NewOpc ) , MaskedHi ) . addReg ( HiReg ) . addReg ( MaskHi ) ; } BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( MaskedLo ) . addImm ( <STR_LIT> ) . addReg ( MaskedHi ) . addImm ( <STR_LIT> ) ;


<s> if ( Opcode == - <NUM_LIT> ) return false ; MachineInstr * ICmp = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , Dst ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; RBI . constrainGenericRegister ( ICmp -> getOperand ( <NUM_LIT> ) . getReg ( ) , * TRI . getBoolRC ( ) , * MRI ) ; bool Ret = constrainSelectedInstRegOperands ( * ICmp , TII , TRI , RBI ) ;


<s> return true ; } int Opcode = getV_CMPOpcode ( Pred , Size ) ; if ( Opcode == - <NUM_LIT> ) return false ; MachineInstr * ICmp = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , Dst ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; RBI . constrainGenericRegister ( ICmp -> getOperand ( <NUM_LIT> ) . getReg ( ) , * TRI . getBoolRC ( ) , * MRI ) ; bool Ret = constrainSelectedInstRegOperands ( * ICmp , TII , TRI , RBI ) ; I . eraseFromParent ( ) ;


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectMUBUFScratchOffset ( MachineOperand & Root ) const { Register Reg = Root . getReg ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const MachineInstr * Def = MRI -> getVRegDef ( Reg ) ; if ( Register WaveBase = getWaveAddress ( Def ) ) { return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Info -> getScratchRSrcReg ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( WaveBase ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } } } ; } int64_t Offset = <NUM_LIT> ; Register BasePtr ; if ( mi_match ( Reg , * MRI , m_GPtrAdd ( m_Reg ( BasePtr ) , m_Copy ( m_ICst ( Offset ) ) ) ) ) { if ( ! <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( Offset ) ) return { } ; const MachineInstr * BasePtrDef = MRI -> getVRegDef ( BasePtr ) ; Register WaveBase = getWaveAddress ( BasePtrDef ) ;


<s> Register RHS = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RBI . getRegBank ( RHS , * MRI , TRI ) -> getID ( ) != <STR_LIT> ) return None ; Register LHS = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto LHSDef = getDefSrcRegIgnoringCopies ( LHS , * MRI ) ; if ( LHSDef && LHSDef -> MI -> getOpcode ( ) == <STR_LIT> ) { int FI = LHSDef -> MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return { {

[ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( RHS ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addFrameIndex ( FI ) ; } , [ = ] ( MachineInstrBuilder & MIB ) {


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } auto VDst_In = MI . getOperand ( <NUM_LIT> ) ;


<s> MI . setDesc ( TII . get ( Opc ) ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . addOperand ( VDst_In ) ; MI . addImplicitDefUseOperands ( * MI . getParent ( ) -> getParent ( ) ) ; return true ;


<s> MachineRegisterInfo & MRI = Root . getParent ( ) -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; Register Src ; unsigned Mods ; std :: tie ( Src , Mods ) = selectVOP3PModsImpl ( Root . getReg ( ) , MRI , true ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Src ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Mods ) ; }


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectVOP3PModsDOT ( MachineOperand & Root ) const { MachineRegisterInfo & MRI = Root . getParent ( ) -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; Register Src ;


<s> if ( MI && MI -> getOpcode ( ) == <STR_LIT> && MRI . getType ( Src ) == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Mods ^= ( <STR_LIT> | <STR_LIT> ) ; Src = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MI = MRI . getVRegDef ( Src ) ;


<s> const bool IsVALU = DstRB -> getID ( ) == <STR_LIT> ; MachineBasicBlock * MBB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; if ( IsVALU ) { BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( Subtarget -> getWavefrontSizeLog2 ( ) ) . addReg ( SrcReg ) ; } else { BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addImm ( Subtarget -> getWavefrontSizeLog2 ( ) ) ;


<s> if ( IsVALU ) { BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( Subtarget -> getWavefrontSizeLog2 ( ) ) . addReg ( SrcReg ) ; } else { BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addImm ( Subtarget -> getWavefrontSizeLog2 ( ) ) ; } const TargetRegisterClass & RC = IsVALU ? <STR_LIT> : <STR_LIT> ; if ( ! RBI . constrainGenericRegister ( DstReg , RC , * MRI ) ) return false ; MI . eraseFromParent ( ) ;


<s> const LLT Ty = MRI . getType ( Reg ) ; if ( ! Ty . isValid ( ) || Ty . getSizeInBits ( ) != <NUM_LIT> ) return false ; return MRI . getVRegDef ( Reg ) -> getOpcode ( ) != <STR_LIT> && RC -> hasSuperClassEq ( TRI . getBoolRC ( ) ) ; } const RegisterBank * RB = RegClassOrBank . get < const RegisterBank * > ( ) ;


<s> assert ( OffsetDef ) ; unsigned ImmOffset ; MachineBasicBlock * MBB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineInstr * Readfirstlane = nullptr ; if ( OffsetDef -> getOpcode ( ) == <STR_LIT> ) { Readfirstlane = OffsetDef ; BaseOffset = OffsetDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OffsetDef = getDefIgnoringCopies ( BaseOffset , * MRI ) ; } if ( OffsetDef -> getOpcode ( ) == <STR_LIT> ) { ImmOffset = OffsetDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } else { std :: tie ( BaseOffset , ImmOffset ) = <STR_LIT> ( * MRI , BaseOffset ) ; if ( Readfirstlane ) { if ( ! RBI . constrainGenericRegister ( BaseOffset , <STR_LIT> , * MRI ) ) return false ; Readfirstlane -> getOperand ( <NUM_LIT> ) . setReg ( BaseOffset ) ; BaseOffset = Readfirstlane -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } else { if ( ! RBI . constrainGenericRegister ( BaseOffset , <STR_LIT> , * MRI ) ) return false ; } Register M0Base = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , M0Base ) . addReg ( BaseOffset ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( M0Base ) ; } auto MIB = BuildMI ( * MBB , & MI , DL , TII . get ( gwsIntrinToOpcode ( IID ) ) ) ; if ( HasVSrc ) { Register VSrc = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MIB . addReg ( VSrc ) ; if ( ! RBI . constrainGenericRegister ( VSrc , <STR_LIT> , * MRI ) ) return false ;


<s> if ( ! RBI . constrainGenericRegister ( BaseOffset , <STR_LIT> , * MRI ) ) return false ; Readfirstlane -> getOperand ( <NUM_LIT> ) . setReg ( BaseOffset ) ; BaseOffset = Readfirstlane -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } else { if ( ! RBI . constrainGenericRegister ( BaseOffset , <STR_LIT> , * MRI ) ) return false ; } Register M0Base = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , M0Base ) . addReg ( BaseOffset ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( M0Base ) ; } auto MIB = BuildMI ( * MBB , & MI , DL , TII . get ( gwsIntrinToOpcode ( IID ) ) ) ; if ( HasVSrc ) {

Register VSrc = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> Addr = AddrDef -> Reg ; } else if ( AddrDef -> MI -> getOpcode ( ) == <STR_LIT> ) { Register SAddr = getSrcRegIgnoringCopies ( AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , * MRI ) ; if ( SAddr && isSGPR ( SAddr ) ) { Register PtrBaseOffset = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Register Off = matchZeroExtendFromS32 ( * MRI , PtrBaseOffset ) ) { Addr = SAddr ; VOffset = Off ; } } } } if ( isSGPR ( Addr ) ) { Opc = <STR_LIT> ( Opc ) ; if ( ! VOffset ) { VOffset = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , VOffset ) . addImm ( <NUM_LIT> ) ; } } auto MIB = BuildMI ( * MBB , & MI , DL , TII . get ( Opc ) ) . addReg ( Addr ) ; if ( isSGPR ( Addr ) ) MIB . addReg ( VOffset ) ; MIB . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; MachineMemOperand * LoadMMO = * MI . memoperands_begin ( ) ; MachinePointerInfo LoadPtrI = LoadMMO -> getPointerInfo ( ) ; LoadPtrI . Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; MachinePointerInfo StorePtrI = LoadPtrI ; LoadPtrI . AddrSpace = <ISA_LIT>AS :: GLOBAL_ADDRESS ; StorePtrI . AddrSpace = <ISA_LIT>AS :: LOCAL_ADDRESS ; auto F = LoadMMO -> getFlags ( ) & ~ ( MachineMemOperand :: MOStore | MachineMemOperand :: MOLoad ) ; LoadMMO = MF -> getMachineMemOperand ( LoadPtrI , F | MachineMemOperand :: MOLoad , Size , LoadMMO -> getBaseAlign ( ) ) ;

MachineMemOperand * StoreMMO = MF -> getMachineMemOperand ( StorePtrI , F | MachineMemOperand :: MOStore , sizeof ( int32_t ) , Align ( <NUM_LIT> ) ) ;


<s> auto PtrBaseDef = getDefSrcRegIgnoringCopies ( PtrBase , * MRI ) ; if ( isSGPR ( PtrBaseDef -> Reg ) ) { if ( ConstOffset > <NUM_LIT> ) { int64_t SplitImmOffset , RemainderOffset ; std :: tie ( SplitImmOffset , RemainderOffset ) = TII . splitFlatOffset ( ConstOffset , <ISA_LIT>AS :: GLOBAL_ADDRESS , <STR_LIT> ) ; if ( isUInt < <NUM_LIT> > ( RemainderOffset ) ) { MachineInstr * MI = Root . getParent ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; Register HighBits = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , HighBits ) . addImm ( RemainderOffset ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrBase ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( HighBits ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( SplitImmOffset ) ; } , } } ; } } unsigned NumLiterals = ! TII . isInlineConstant ( APInt ( <NUM_LIT> , ConstOffset & <NUM_LIT> ) ) + ! TII . isInlineConstant ( APInt ( <NUM_LIT> , ConstOffset >> <NUM_LIT> ) ) ; if ( STI . getConstantBusLimit ( <STR_LIT> ) > NumLiterals ) return None ;


<s> MachineBasicBlock * BB = I . getParent ( ) ; MachineFunction * MF = BB -> getParent ( ) ; const bool IsUnsigned = I . getOpcode ( ) == <STR_LIT> ;

I . setDesc ( TII . get ( IsUnsigned ? <STR_LIT> : <STR_LIT> ) ) ;


<s> const unsigned SrcSize = SrcTy . getSizeInBits ( ) ; unsigned DstSize = DstTy . getSizeInBits ( ) ; unsigned Offset = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Offset % <NUM_LIT> != <NUM_LIT> || DstSize > <NUM_LIT> ) return false ; if ( DstSize == <NUM_LIT> ) DstSize = <NUM_LIT> ; const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand ( I . getOperand ( <NUM_LIT> ) , * MRI ) ; if ( ! DstRC || ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) ) return false ; const RegisterBank * SrcBank = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForSizeOnBank ( SrcSize , * SrcBank ) ; if ( ! SrcRC ) return false ; unsigned SubReg = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( Offset / <NUM_LIT> , DstSize / <NUM_LIT> ) ; SrcRC = TRI . getSubClassWithSubReg ( SrcRC , SubReg ) ; if ( ! SrcRC ) return false ; SrcReg = constrainOperandRegClass ( * MF , TRI , * MRI , TII , RBI , I , * SrcRC , I . getOperand ( <NUM_LIT> ) ) ;

const DebugLoc & DL = I . getDebugLoc ( ) ;


<s> Register IdxReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DstTy = MRI -> getType ( DstReg ) ; LLT SrcTy = MRI -> getType ( SrcReg ) ; const RegisterBank * DstRB = RBI . getRegBank ( DstReg , * MRI , TRI ) ; const RegisterBank * SrcRB = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; const RegisterBank * IdxRB = RBI . getRegBank ( IdxReg , * MRI , TRI ) ; if ( IdxRB -> getID ( ) != <STR_LIT> ) return false ; const TargetRegisterClass * SrcRC = TRI . getRegClassForTypeOnBank ( SrcTy , * SrcRB ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForTypeOnBank ( DstTy , * DstRB ) ; if ( ! SrcRC || ! DstRC ) return false ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) || ! RBI . constrainGenericRegister ( IdxReg , <STR_LIT> , * MRI ) ) return false ; MachineBasicBlock * BB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; const bool Is64 = DstTy . getSizeInBits ( ) == <NUM_LIT> ; unsigned SubReg ; std :: tie ( IdxReg , SubReg ) = computeIndirectRegIndex ( * MRI , TRI , SrcRC , IdxReg , DstTy . getSizeInBits ( ) / <NUM_LIT> ) ; if ( SrcRB -> getID ( ) == <STR_LIT> ) { if ( DstTy . getSizeInBits ( ) != <NUM_LIT> && ! Is64 ) return false ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( IdxReg ) ; unsigned Opc = Is64 ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & MI , DL , TII . get ( Opc ) , DstReg ) . addReg ( SrcReg , <NUM_LIT> , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) ; MI . eraseFromParent ( ) ; return true ; } if ( SrcRB -> getID ( ) != <STR_LIT> || DstTy . getSizeInBits ( ) != <NUM_LIT> ) return false ; if ( ! STI . useVGPRIndexMode ( ) ) { BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( IdxReg ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , <NUM_LIT> , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) ; MI . eraseFromParent ( ) ;


<s> MachineBasicBlock * BB = I . getParent ( ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Src1Ty = MRI -> getType ( Src1Reg ) ; unsigned DstSize = MRI -> getType ( DstReg ) . getSizeInBits ( ) ; unsigned InsSize = Src1Ty . getSizeInBits ( ) ; int64_t Offset = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Offset % <NUM_LIT> != <NUM_LIT> || InsSize % <NUM_LIT> != <NUM_LIT> ) return false ; if ( InsSize > <NUM_LIT> ) return false ; unsigned SubReg = TRI . getSubRegFromChannel ( Offset / <NUM_LIT> , InsSize / <NUM_LIT> ) ;

if ( SubReg == <STR_LIT> ) return false ;


<s> unsigned ValSize = ValTy . getSizeInBits ( ) ; const RegisterBank * VecRB = RBI . getRegBank ( VecReg , * MRI , TRI ) ; const RegisterBank * ValRB = RBI . getRegBank ( ValReg , * MRI , TRI ) ; const RegisterBank * IdxRB = RBI . getRegBank ( IdxReg , * MRI , TRI ) ; assert ( VecTy . getElementType ( ) == ValTy ) ; if ( IdxRB -> getID ( ) != <STR_LIT> ) return false ; const TargetRegisterClass * VecRC = TRI . getRegClassForTypeOnBank ( VecTy , * VecRB ) ; const TargetRegisterClass * ValRC = TRI . getRegClassForTypeOnBank ( ValTy , * ValRB ) ; if ( ! RBI . constrainGenericRegister ( VecReg , * VecRC , * MRI ) || ! RBI . constrainGenericRegister ( DstReg , * VecRC , * MRI ) || ! RBI . constrainGenericRegister ( ValReg , * ValRC , * MRI ) || ! RBI . constrainGenericRegister ( IdxReg , <STR_LIT> , * MRI ) ) return false ; if ( VecRB -> getID ( ) == <STR_LIT> && ValSize != <NUM_LIT> ) return false ; unsigned SubReg ; std :: tie ( IdxReg , SubReg ) = computeIndirectRegIndex ( * MRI , TRI , VecRC , IdxReg , ValSize / <NUM_LIT> ) ; const bool IndexMode = VecRB -> getID ( ) == <STR_LIT> && STI . useVGPRIndexMode ( ) ; MachineBasicBlock * BB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; if ( ! IndexMode ) { BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( IdxReg ) ; const MCInstrDesc & RegWriteOp = TII . getIndirectRegWriteMovRelPseudo ( VecSize , ValSize , VecRB -> getID ( ) == <STR_LIT> ) ; BuildMI ( * BB , MI , DL , RegWriteOp , DstReg ) . addReg ( VecReg ) . addReg ( ValReg ) . addImm ( SubReg ) ; MI . eraseFromParent ( ) ; return true ; } const MCInstrDesc & GPRIDXDesc = TII . getIndirectGPRIDXPseudo ( TRI . getRegSizeInBits ( * VecRC ) , false ) ; BuildMI ( * BB , MI , DL , GPRIDXDesc , DstReg ) . addReg ( VecReg ) . addReg ( ValReg ) . addReg ( IdxReg ) . addImm ( SubReg ) ;


<s> return selectEndCfIntrinsic ( I ) ; case <STR_LIT> : case <STR_LIT> : return selectDSOrderedIntrinsic ( I , IntrinsicID ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return selectDSGW<ISA_LIT>ntrinsic ( I , IntrinsicID ) ; case <STR_LIT> : return selectDSAppendConsume ( I , true ) ; case <STR_LIT> : return selectDSAppendConsume ( I , false ) ; case <STR_LIT> : return selectSBarrier ( I ) ; case <STR_LIT> : return selectGlobalAtomicFadd ( I , I . getOperand ( <NUM_LIT> ) , I . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return selectBufferLoadLds ( I ) ;


<s> const DebugLoc & DL = MI . getDebugLoc ( ) ; const RegisterBank * DstBank = RBI . getRegBank ( DstReg , * MRI , TRI ) ; const unsigned DstSize = DstTy . getSizeInBits ( ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForSizeOnBank ( DstSize , * DstBank ) ; if ( ! DstRC ) return false ; ArrayRef < int16_t > SubRegs = TRI . getRegSplitParts ( DstRC , SrcSize / <NUM_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * BB , & MI , DL , TII . get ( TargetOpcode :: REG_SEQUENCE ) , DstReg ) ; for ( int I = <NUM_LIT> , E = MI . getNumOperands ( ) - <NUM_LIT> ; I != E ; ++ I ) { MachineOperand & Src = MI . getOperand ( I + <NUM_LIT> ) ; MIB . addReg ( Src . getReg ( ) , getUndefRegState ( Src . isUndef ( ) ) ) ; MIB . addImm ( SubRegs [ I ] ) ; const TargetRegisterClass * SrcRC = TRI . getConstrainedRegClassForOperand ( Src , * MRI ) ;

if ( SrcRC && ! RBI . constrainGenericRegister ( Src . getReg ( ) , * SrcRC , * MRI ) ) return false ;


<s> } unsigned NewOpc = IsVGPR ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass & RegRC = IsVGPR ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * DstRC = TRI . getRegClassForTypeOnBank ( Ty , * DstRB ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForTypeOnBank ( Ty , * SrcRB ) ; const TargetRegisterClass * MaskRC = TRI . getRegClassForTypeOnBank ( MaskTy , * MaskRB ) ; if ( ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) || ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) || ! RBI . constrainGenericRegister ( MaskReg , * MaskRC , * MRI ) ) return false ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) { assert ( MaskTy . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( NewOpc ) , DstReg ) . addReg ( SrcReg ) . addReg ( MaskReg ) ; I . eraseFromParent ( ) ; return true ; } Register HiReg = MRI -> createVirtualRegister ( & RegRC ) ; Register LoReg = MRI -> createVirtualRegister ( & RegRC ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , LoReg ) . addReg ( SrcReg , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , HiReg ) . addReg ( SrcReg , <NUM_LIT> , <STR_LIT> ) ; Register MaskedLo , MaskedHi ; if ( CanCopyLow32 ) { MaskedLo = LoReg ; } else { Register MaskLo = MRI -> createVirtualRegister ( & RegRC ) ; MaskedLo = MRI -> createVirtualRegister ( & RegRC ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , MaskLo ) . addReg ( MaskReg , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( NewOpc ) , MaskedLo ) . addReg ( LoReg ) . addReg ( MaskLo ) ; } if ( CanCopyHi32 ) { MaskedHi = HiReg ; } else { Register MaskHi = MRI -> createVirtualRegister ( & RegRC ) ; MaskedHi = MRI -> createVirtualRegister ( & RegRC ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , MaskHi ) . addReg ( MaskReg , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( NewOpc ) , MaskedHi ) . addReg ( HiReg ) . addReg ( MaskHi ) ; }

BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( MaskedLo ) . addImm ( <STR_LIT> ) . addReg ( MaskedHi ) . addImm ( <STR_LIT> ) ;


<s> I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * ExtI , TII , TRI , RBI ) ; } if ( SrcBank -> getID ( ) == <STR_LIT> && DstSize <= <NUM_LIT> ) { const TargetRegisterClass & SrcRC = InReg && DstSize > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( ! RBI . constrainGenericRegister ( SrcReg , SrcRC , * MRI ) ) return false ; if ( Signed && DstSize == <NUM_LIT> && ( SrcSize == <NUM_LIT> || SrcSize == <NUM_LIT> ) ) { const unsigned SextOpc = SrcSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , TII . get ( SextOpc ) , DstReg ) . addReg ( SrcReg ) ; I . eraseFromParent ( ) ; return RBI . constrainGenericRegister ( DstReg , <STR_LIT> , * MRI ) ; } const unsigned BFE64 = Signed ? <STR_LIT> : <STR_LIT> ; const unsigned BFE32 = Signed ? <STR_LIT> : <STR_LIT> ; if ( DstSize > <NUM_LIT> && ( SrcSize <= <NUM_LIT> || InReg ) ) { Register ExtReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; Register UndefReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; unsigned SubReg = InReg ? <STR_LIT> : <NUM_LIT> ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , UndefReg ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , ExtReg ) . addReg ( SrcReg , <NUM_LIT> , SubReg ) . addImm ( <STR_LIT> ) . addReg ( UndefReg ) . addImm ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( BFE64 ) , DstReg ) . addReg ( ExtReg ) . addImm ( SrcSize << <NUM_LIT> ) ; I . eraseFromParent ( ) ; return RBI . constrainGenericRegister ( DstReg , <STR_LIT> , * MRI ) ; } unsigned Mask ; if ( ! Signed && shouldUseAndMask ( SrcSize , Mask ) ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addImm ( Mask ) ; } else { BuildMI ( MBB , I , DL , TII . get ( BFE32 ) , DstReg ) . addReg ( SrcReg ) . addImm ( SrcSize << <NUM_LIT> ) ; } I . eraseFromParent ( ) ;


<s> Register DstReg0 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DstTy = MRI -> getType ( DstReg0 ) ; LLT SrcTy = MRI -> getType ( SrcReg ) ; const unsigned DstSize = DstTy . getSizeInBits ( ) ; const unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; const RegisterBank * SrcBank = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForSizeOnBank ( SrcSize , * SrcBank ) ; if ( ! SrcRC || ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; ArrayRef < int16_t > SubRegs = TRI . getRegSplitParts ( SrcRC , DstSize / <NUM_LIT> ) ; for ( int I = <NUM_LIT> , E = NumDst ; I != E ; ++ I ) { MachineOperand & Dst = MI . getOperand ( I ) ; BuildMI ( * BB , & MI , DL , TII . get ( TargetOpcode :: COPY ) , Dst . getReg ( ) ) . addReg ( SrcReg , <NUM_LIT> , SubRegs [ I ] ) ;

SrcRC = TRI . getSubClassWithSubReg ( SrcRC , SubRegs [ I ] ) ;


<s> ArrayRef < int16_t > SubRegs = TRI . getRegSplitParts ( SrcRC , DstSize / <NUM_LIT> ) ; for ( int I = <NUM_LIT> , E = NumDst ; I != E ; ++ I ) { MachineOperand & Dst = MI . getOperand ( I ) ; BuildMI ( * BB , & MI , DL , TII . get ( TargetOpcode :: COPY ) , Dst . getReg ( ) ) . addReg ( SrcReg , <NUM_LIT> , SubRegs [ I ] ) ; SrcRC = TRI . getSubClassWithSubReg ( SrcRC , SubRegs [ I ] ) ; if ( ! SrcRC || ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ; if ( DstRC && ! RBI . constrainGenericRegister ( Dst . getReg ( ) , * DstRC , * MRI ) ) return false ; } MI . eraseFromParent ( ) ; return true ;


<s> } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } const RegClassOrRegBank & RegClassOrBank = MRI -> getRegClassOrRegBank ( DefReg ) ; const TargetRegisterClass * DefRC = RegClassOrBank . dyn_cast < const TargetRegisterClass * > ( ) ; if ( ! DefRC ) { if ( ! DefTy . isValid ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ;


<s> Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const RegisterBank * DstBank = RBI . getRegBank ( DstReg , * MRI , TRI ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForSizeOnBank ( <NUM_LIT> , * DstBank ) ; if ( ! DstRC || ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) ) return false ;

const bool IsVALU = DstBank -> getID ( ) == <STR_LIT> ;


<s> ImmOffset = ConstOffset ; } auto AddrDef = getDefSrcRegIgnoringCopies ( Addr , * MRI ) ; if ( AddrDef -> MI -> getOpcode ( ) == <STR_LIT> ) { int FI = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addFrameIndex ( FI ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( ImmOffset ) ; } } } ; } Register SAddr = AddrDef -> Reg ; if ( AddrDef -> MI -> getOpcode ( ) == <STR_LIT> ) { Register LHS = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RHS = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto LHSDef = getDefSrcRegIgnoringCopies ( LHS , * MRI ) ; auto RHSDef = getDefSrcRegIgnoringCopies ( RHS , * MRI ) ; if ( LHSDef -> MI -> getOpcode ( ) == <STR_LIT> && isSGPR ( RHSDef -> Reg ) ) { int FI = LHSDef -> MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; MachineInstr & I = * Root . getParent ( ) ; MachineBasicBlock * BB = I . getParent ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; SAddr = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , SAddr ) . addFrameIndex ( FI ) . addReg ( RHSDef -> Reg ) ; } } if ( ! isSGPR ( SAddr ) ) return None ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( SAddr ) ; } , [ = ] ( MachineInstrBuilder & MIB ) {


<s> [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( RHS ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addFrameIndex ( FI ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( ImmOffset ) ; } } } ; } if ( ! isSGPR ( LHS ) ) return None ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( RHS ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( LHS ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( ImmOffset ) ; } } } ;


<s> if ( ConstOffset != <NUM_LIT> && TII . isLegalFLATOffset ( ConstOffset , <ISA_LIT>AS :: PRIVATE_ADDRESS , true ) ) { Addr = PtrBase ; ImmOffset = ConstOffset ; } auto AddrDef = getDefSrcRegIgnoringCopies ( Addr , * MRI ) ; if ( AddrDef -> MI -> getOpcode ( ) != <STR_LIT> ) return None ; Register RHS = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RBI . getRegBank ( RHS , * MRI , TRI ) -> getID ( ) != <STR_LIT> ) return None ; Register LHS = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto LHSDef = getDefSrcRegIgnoringCopies ( LHS , * MRI ) ; if ( LHSDef -> MI -> getOpcode ( ) == <STR_LIT> ) { int FI = LHSDef -> MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( RHS ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addFrameIndex ( FI ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( ImmOffset ) ; } } } ; } if ( ! isSGPR ( LHS ) ) return None ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( RHS ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( LHS ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( ImmOffset ) ;


<s> if ( ! OffsetVal || ! isInt < <NUM_LIT> > ( * OffsetVal ) ) return None ;


<s> MachineInstr * RootI = getDefIgnoringCopies ( Root , MRI ) ; if ( RootI -> getOpcode ( ) != TargetOpcode :: G_PTR_ADD ) return { Root , <NUM_LIT> } ; MachineOperand & RHS = RootI -> getOperand ( <NUM_LIT> ) ;

Optional < ValueAndVReg > MaybeOffset = getConstantVRegValWithLookThrough ( RHS . getReg ( ) , MRI , true ) ;


<s> MachineBasicBlock * BB = I . getParent ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned Size = MRI -> getType ( DstReg ) . getSizeInBits ( ) ; const bool Is64 = Size == <NUM_LIT> ; if ( Size != STI . getWavefrontSize ( ) ) return false ; Optional < ValueAndVReg > Arg = getConstantVRegValWithLookThrough ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , * MRI , true ) ;


<s> const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ; if ( ! RC ) return true ; return RBI . constrainGenericRegister ( DstReg , * RC , * MRI ) ; } if ( ! isVCC ( SrcReg , * MRI ) ) { if ( ! RBI . constrainGenericRegister ( DstReg , * TRI . getBoolRC ( ) , * MRI ) ) return false ; const TargetRegisterClass * SrcRC = TRI . getConstrainedRegClassForOperand ( Src , * MRI ) ; Optional < ValueAndVReg > ConstVal = getConstantVRegValWithLookThrough ( SrcReg , * MRI , true , true ) ; if ( ConstVal ) { unsigned MovOpc = STI . isWave64 ( ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & I , DL , TII . get ( MovOpc ) , DstReg ) . addImm ( ConstVal -> Value . getBoolValue ( ) ? - <NUM_LIT> : <NUM_LIT> ) ; } else { Register MaskedReg = MRI -> createVirtualRegister ( SrcRC ) ; unsigned AndOpc = TRI . isSGPRClass ( SrcRC ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & I , DL , TII . get ( AndOpc ) , MaskedReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( MaskedReg ) ; } if ( ! MRI -> getRegClassOrNull ( SrcReg ) ) MRI -> setRegClass ( SrcReg , SrcRC ) ; I . eraseFromParent ( ) ; return true ; } const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ; if ( RC && ! RBI . constrainGenericRegister ( DstReg , * RC , * MRI ) ) return false ; return true ; } for ( const MachineOperand & MO : I . operands ( ) ) { if ( MO . getReg ( ) . isPhysical ( ) ) continue ; const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( MO , * MRI ) ; if ( ! RC ) continue ;

RBI . constrainGenericRegister ( MO . getReg ( ) , * RC , * MRI ) ;


<s> if ( DstBank -> getID ( ) != <STR_LIT> ) return false ; Register Src0 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI -> getType ( Src0 ) != S32 ) return false ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineBasicBlock * BB = MI . getParent ( ) ; auto ConstSrc1 = getConstantVRegValWithLookThrough ( Src1 , * MRI , true , true , true ) ; if ( ConstSrc1 ) { auto ConstSrc0 = getConstantVRegValWithLookThrough ( Src0 , * MRI , true , true , true ) ; if ( ConstSrc0 ) { const int64_t K0 = ConstSrc0 -> Value . getSExtValue ( ) ; const int64_t K1 = ConstSrc1 -> Value . getSExtValue ( ) ; uint32_t Lo16 = static_cast < uint32_t > ( K0 ) & <NUM_LIT> ; uint32_t Hi16 = static_cast < uint32_t > ( K1 ) & <NUM_LIT> ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , Dst ) . addImm ( Lo16 | ( Hi16 << <NUM_LIT> ) ) ; MI . eraseFromParent ( ) ; return RBI . constrainGenericRegister ( Dst , <STR_LIT> , * MRI ) ; } } MachineInstr * Src1Def = getDefIgnoringCopies ( Src1 , * MRI ) ; if ( Src1Def && Src1Def -> getOpcode ( ) == <STR_LIT> ) { MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . RemoveOperand ( <NUM_LIT> ) ; return RBI . constrainGenericRegister ( Dst , <STR_LIT> , * MRI ) && RBI . constrainGenericRegister ( Src0 , <STR_LIT> , * MRI ) ; } Register ShiftSrc0 ; Register ShiftSrc1 ; bool Shift0 = mi_match ( Src0 , * MRI , m_OneUse ( m_GLShr ( m_Reg ( ShiftSrc0 ) , m_SpecificICst ( <NUM_LIT> ) ) ) ) ; bool Shift1 = mi_match ( Src1 , * MRI , m_OneUse ( m_GLShr ( m_Reg ( ShiftSrc1 ) , m_SpecificICst ( <NUM_LIT> ) ) ) ) ; unsigned Opc = <STR_LIT> ; if ( Shift0 && Shift1 ) { Opc = <STR_LIT> ; MI . getOperand ( <NUM_LIT> ) . setReg ( ShiftSrc0 ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( ShiftSrc1 ) ;


<s> Register VDstIn = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto MIB = BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , VDst ) ; Optional < ValueAndVReg > ConstSelect = getConstantVRegValWithLookThrough ( LaneSelect , * MRI , true , true ) ; if ( ConstSelect ) { MIB . addReg ( Val ) ; MIB . addImm ( ConstSelect -> Value . getSExtValue ( ) & maskTrailingOnes < uint64_t > ( STI . getWavefrontSizeLog2 ( ) ) ) ; } else { Optional < ValueAndVReg > ConstVal = getConstantVRegValWithLookThrough ( Val , * MRI , true , true ) ; if ( ConstVal && <STR_LIT> ( ConstVal -> Value . getSExtValue ( ) , STI . hasInv2PiInlineImm ( ) ) ) { MIB . addImm ( ConstVal -> Value . getSExtValue ( ) ) ; MIB . addReg ( LaneSelect ) ; } else { MIB . addReg ( Val ) ; RBI . constrainGenericRegister ( LaneSelect , <STR_LIT> , * MRI ) ; BuildMI ( * MBB , * MIB , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( LaneSelect ) ; MIB . addReg ( <STR_LIT> ) ; } } MIB . addReg ( VDstIn ) ; MI . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ;


<s> case CmpInst :: ICMP_SGE : return <STR_LIT> ; case CmpInst :: ICMP_SLT : return <STR_LIT> ; case CmpInst :: ICMP_SLE : return <STR_LIT> ; case CmpInst :: ICMP_UGT : return <STR_LIT> ; case CmpInst :: ICMP_UGE : return <STR_LIT> ; case CmpInst :: ICMP_ULT : return <STR_LIT> ; case CmpInst :: ICMP_ULE : return <STR_LIT> ;


<s> assert ( Size == <NUM_LIT> || Size == <NUM_LIT> ) ; switch ( P ) { default : llvm_unreachable ( <STR_LIT> ) ; case CmpInst :: ICMP_NE : return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; case CmpInst :: ICMP_EQ : return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; case CmpInst :: ICMP_SGT : return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; case CmpInst :: ICMP_SGE : return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; case CmpInst :: ICMP_SLT : return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; case CmpInst :: ICMP_SLE : return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; case CmpInst :: ICMP_UGT : return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; case CmpInst :: ICMP_UGE : return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; case CmpInst :: ICMP_ULT :


<s> if ( RC ) return RC -> getID ( ) == <STR_LIT> && MRI . getType ( Reg ) . getSizeInBits ( ) == <NUM_LIT> ; const RegisterBank * RB = RegClassOrBank . get < const RegisterBank * > ( ) ; return RB -> getID ( ) == <STR_LIT> ;


<s> MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; I . setDesc ( TII . get ( TargetOpcode :: COPY ) ) ; const MachineOperand & Src = I . getOperand ( <NUM_LIT> ) ; unsigned SrcReg = Src . getReg ( ) ; if ( ! TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && isSCC ( SrcReg , MRI ) ) { unsigned DstReg = TRI . getRegSizeInBits ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; unsigned DstSize = TRI . getRegSizeInBits ( DstReg , MRI ) ; if ( DstSize == <NUM_LIT> ) { const DebugLoc & DL = I . getDebugLoc ( ) ;

BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) ;


<s> assert ( Size == <NUM_LIT> || Size == <NUM_LIT> ) ; unsigned Opcode = getV_CMPOpcode ( ( CmpInst :: Predicate ) I . getOperand ( <NUM_LIT> ) . getPredicate ( ) , Size ) ; MachineInstr * ICmp = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; RBI . constrainGenericRegister ( ICmp -> getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> , MRI ) ; bool Ret = constrainSelectedInstRegOperands ( * ICmp , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return Ret ;


<s> DebugLoc DL = I . getDebugLoc ( ) ; unsigned SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Size = RBI . getSizeInBits ( SrcReg , MRI , TRI ) ; assert ( Size == <NUM_LIT> ) ; unsigned CCReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isSCC ( CCReg , MRI ) ) { unsigned Opcode = getS_CMPOpcode ( ( CmpInst :: Predicate ) I . getOperand ( <NUM_LIT> ) . getPredicate ( ) , Size ) ; MachineInstr * ICmp = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , CCReg ) . addReg ( <STR_LIT> ) ; bool Ret = constrainSelectedInstRegOperands ( * ICmp , TII , TRI , RBI ) && RBI . constrainGenericRegister ( CCReg , <STR_LIT> , MRI ) ; I . eraseFromParent ( ) ;


<s> MachineBasicBlock * BB = I . getParent ( ) ; MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned SubReg = TRI . getSubRegFromChannel ( I . getOperand ( <NUM_LIT> ) . getImm ( ) / <NUM_LIT> ) ; DebugLoc DL = I . getDebugLoc ( ) ; MachineInstr * Ins = BuildMI ( * BB , & I , DL , TII . get ( TargetOpcode :: INSERT_SUBREG ) ) . addDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( SubReg ) ; for ( const MachineOperand & MO : Ins -> operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; if ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) continue ; const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( MO , MRI ) ; if ( ! RC ) continue ; RBI . constrainGenericRegister ( MO . getReg ( ) , * RC , MRI ) ; }


<s> return selectImpl ( I , CoverageInfo ) ; case <STR_LIT> : { MachineFunction * MF = I . getParent ( ) -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const ArgDescriptor * InputPtrReg ; const TargetRegisterClass * RC ; const DebugLoc & DL = I . getDebugLoc ( ) ; std :: tie ( InputPtrReg , RC ) = MFI -> getPreloadedValue ( <STR_LIT> ) ; if ( ! InputPtrReg ) report_fatal_error ( <STR_LIT> ) ; BuildMI ( * I . getParent ( ) , & I , DL , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addReg ( MRI . getLiveInVirtReg ( InputPtrReg -> getRegister ( ) ) ) ;


<s> const TargetRegisterClass * RC ; const DebugLoc & DL = I . getDebugLoc ( ) ; std :: tie ( InputPtrReg , RC ) = MFI -> getPreloadedValue ( <STR_LIT> ) ; if ( ! InputPtrReg ) report_fatal_error ( <STR_LIT> ) ; BuildMI ( * I . getParent ( ) , & I , DL , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addReg ( MRI . getLiveInVirtReg ( InputPtrReg -> getRegister ( ) ) ) ;


<s> switch ( LoadSize ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; } MachineInstr * Flat = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addReg ( PtrReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; bool Ret = constrainSelectedInstRegOperands ( * Flat , TII , TRI , RBI ) ;


<s> break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; } MachineInstr * Flat = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addReg ( PtrReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; bool Ret = constrainSelectedInstRegOperands ( * Flat , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return Ret ;


<s> if ( isSCC ( CCReg , MRI ) ) { unsigned SelectOpcode = Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; MachineInstr * CopySCC = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( CCReg ) ; if ( ! MRI . getRegClassOrNull ( CCReg ) ) MRI . setRegClass ( CCReg , TRI . getConstrainedRegClassForOperand ( CCOp , MRI ) ) ;

MachineInstr * Select = BuildMI ( * BB , & I , DL , TII . get ( SelectOpcode ) , DstReg ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ;