<s> if ( DestVT == <STR_LIT> && ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) ) { SDLoc DL ( Op ) ; SDValue FpToInt32 = DAG . getNode ( OpOpcode , DL , <STR_LIT> , Src ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FpToInt32 ) ; } if ( SrcVT == <STR_LIT> || ( SrcVT == <STR_LIT> && Src . getOpcode ( ) == <STR_LIT> ) ) { SDLoc DL ( Op ) ;


<s> K0 = DAG . getConstantFP ( BitsToFloat ( UINT32_C ( <NUM_LIT> ) ) , SL , SrcVT ) ; K1 = DAG . getConstantFP ( BitsToFloat ( UINT32_C ( <NUM_LIT> ) ) , SL , SrcVT ) ; } SDValue Mul = DAG . getNode ( <STR_LIT> , SL , SrcVT , Trunc , K0 ) ; SDValue FloorMul = DAG . getNode ( <STR_LIT> , SL , SrcVT , Mul ) ; SDValue Fma = DAG . getNode ( <STR_LIT> , SL , SrcVT , FloorMul , K1 , Trunc ) ; SDValue Hi = DAG . getNode ( ( Signed && SrcVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> , SL , <STR_LIT> , FloorMul ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Fma ) ;

SDValue Result = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DAG . getBuildVector ( <STR_LIT> , SL , { Lo , Hi } ) ) ;


<s> SDValue Div = DAG . getNode ( <STR_LIT> , SL , VT , X , Y , Flags ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , SL , VT , Div , Flags ) ;

SDValue Neg = DAG . getNode ( <STR_LIT> , SL , VT , Trunc , Flags ) ;


<s> SDValue CopySign = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , C1 , Src ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src , CopySign ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Tmp1 , CopySign ) ; SDValue Fabs = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; APFloat C2Val ( APFloat :: IEEEdouble ( ) , <STR_LIT> ) ; SDValue C2 = DAG . getConstantFP ( C2Val , SL , <STR_LIT> ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) ; SDValue Cond = DAG . getSetCC ( SL , SetCCVT , Fabs , C2 , <STR_LIT> ) ; return DAG . getSelect ( SL , <STR_LIT> , Cond , Src , Tmp2 ) ;


<s> SDValue Fabs = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; APFloat C2Val ( APFloat :: IEEEdouble ( ) , <STR_LIT> ) ; SDValue C2 = DAG . getConstantFP ( C2Val , SL , <STR_LIT> ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) ;

SDValue Cond = DAG . getSetCC ( SL , SetCCVT , Fabs , C2 , <STR_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFROUND ( SDValue Op , SelectionDAG & DAG ) const { SDLoc SL ( Op ) ; SDValue X = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; SDValue T = DAG . getNode ( <STR_LIT> , SL , VT , X ) ; SDValue Diff = DAG . getNode ( <STR_LIT> , SL , VT , X , T ) ; SDValue AbsDiff = DAG . getNode ( <STR_LIT> , SL , VT , Diff ) ; const SDValue Zero = DAG . getConstantFP ( <NUM_LIT> , SL , VT ) ; const SDValue One = DAG . getConstantFP ( <NUM_LIT> , SL , VT ) ; const SDValue Half = DAG . getConstantFP ( <NUM_LIT> , SL , VT ) ; SDValue SignOne = DAG . getNode ( <STR_LIT> , SL , VT , One , X ) ;

EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ;


<s> const SDValue FractMask = DAG . getConstant ( ( UINT64_C ( <NUM_LIT> ) << FractBits ) - <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Shr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , FractMask , Exp ) ; SDValue Not = DAG . getNOT ( SL , Shr , <STR_LIT> ) ; SDValue Tmp0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BcInt , Not ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) ; const SDValue FiftyOne = DAG . getConstant ( FractBits - <NUM_LIT> , SL , <STR_LIT> ) ; SDValue ExpLt0 = DAG . getSetCC ( SL , SetCCVT , Exp , Zero , <STR_LIT> ) ; SDValue ExpGt51 = DAG . getSetCC ( SL , SetCCVT , Exp , FiftyOne , <STR_LIT> ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , ExpLt0 , SignBit64 , Tmp0 ) ;

SDValue Tmp2 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , ExpGt51 , BcInt , Tmp1 ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( <ISA_LIT>MachineFunction * MFI , SDValue Op , SelectionDAG & DAG ) const { const DataLayout & DL = DAG . getDataLayout ( ) ; GlobalAddressSDNode * G = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = G -> getGlobal ( ) ; if ( G -> getAddressSpace ( ) == <ISA_LIT>AS :: LOCAL_ADDRESS || G -> getAddressSpace ( ) == <ISA_LIT>AS :: REGION_ADDRESS ) { if ( ! MFI -> isModuleEntryFunction ( ) && ! GV -> getName ( ) . equals ( <STR_LIT> ) ) { SDLoc DL ( Op ) ;

const Function & Fn = DAG . getMachineFunction ( ) . getFunction ( ) ;


<s> if ( ! MFI -> isModuleEntryFunction ( ) && ! GV -> getName ( ) . equals ( <STR_LIT> ) ) { SDLoc DL ( Op ) ; const Function & Fn = DAG . getMachineFunction ( ) . getFunction ( ) ; DiagnosticInfoUnsupported BadLDSDecl ( Fn , <STR_LIT> , DL . getDebugLoc ( ) , DS_Warning ) ; DAG . getContext ( ) -> diagnose ( BadLDSDecl ) ; SDValue Trap = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getEntryNode ( ) ) ; SDValue OutputChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Trap , DAG . getRoot ( ) ) ; DAG . setRoot ( OutputChain ) ; return DAG . getUNDEF ( Op . getValueType ( ) ) ; } assert ( G -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ;

unsigned Offset = MFI -> allocateLDSGlobal ( DL , * cast < GlobalVariable > ( GV ) ) ;


<s> if ( Signed ) { Sign = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue Abs = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src , Sign ) , Sign ) ; std :: tie ( Lo , Hi ) = split64BitValue ( Abs , DAG ) ; } ShAmt = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi ) ; } SDValue Norm = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src , ShAmt ) ; std :: tie ( Lo , Hi ) = split64BitValue ( Norm , DAG ) ; SDValue Adjust = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) , Lo ) ; Norm = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi , Adjust ) ; unsigned Opc = ( Signed && Subtarget -> isGCN ( ) ) ? <STR_LIT> : <STR_LIT> ; SDValue FVal = DAG . getNode ( Opc , SL , <STR_LIT> , Norm ) ; ShAmt = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) , ShAmt ) ; if ( Subtarget -> isGCN ( ) ) return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , FVal , ShAmt ) ; SDValue Exp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , ShAmt , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue IVal = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , FVal ) , Exp ) ; if ( Signed ) { Sign = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Sign ) , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; IVal = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , IVal , Sign ) ; }

return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , IVal ) ;


<s> std :: tie ( Lo , Hi ) = split64BitValue ( Norm , DAG ) ; SDValue Adjust = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) , Lo ) ; Norm = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi , Adjust ) ; unsigned Opc = ( Signed && Subtarget -> isGCN ( ) ) ? <STR_LIT> : <STR_LIT> ; SDValue FVal = DAG . getNode ( Opc , SL , <STR_LIT> , Norm ) ; ShAmt = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) , ShAmt ) ; if ( Subtarget -> isGCN ( ) ) return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , FVal , ShAmt ) ; SDValue Exp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , ShAmt , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue IVal = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , FVal ) , Exp ) ; if ( Signed ) { Sign = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Sign ) , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ;

IVal = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , IVal , Sign ) ;


<s> std :: tie ( Lo , Hi ) = split64BitValue ( Src , DAG ) ; SDValue CvtHi = DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT> , SL , <STR_LIT> , Hi ) ; SDValue CvtLo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo ) ; SDValue LdExp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , CvtHi , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ;

return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LdExp , CvtLo ) ;


<s> case <STR_LIT> : return LowerFTRUNC ( Op , DAG ) ; case <STR_LIT> : return LowerFRINT ( Op , DAG ) ; case <STR_LIT> : return LowerFNEARBYINT ( Op , DAG ) ; case <STR_LIT> : return LowerFROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFFLOOR ( Op , DAG ) ; case <STR_LIT> : return LowerFLOG ( Op , DAG , numbers :: ln2f ) ; case <STR_LIT> : return LowerFLOG ( Op , DAG , numbers :: ln2f / numbers :: ln10f ) ; case <STR_LIT> : return lowerFEXP ( Op , DAG ) ; case <STR_LIT> : return Lower<ISA_LIT>NT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_FP16 ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerCTLZ_CTTZ ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; } return Op ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & DL , SelectionDAG & DAG ) const {

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain ) ;


<s> SDValue LHS_Lo = DAG . getNode ( <STR_LIT> , DL , HalfVT , LHS , Zero ) ; SDValue RHS_Lo = DAG . getNode ( <STR_LIT> , DL , HalfVT , RHS , Zero ) ; SDValue DIVREM = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( HalfVT , HalfVT ) , LHS_Lo , RHS_Lo ) ; SDValue Res [ <NUM_LIT> ] = { DAG . getNode ( <STR_LIT> , DL , VT , DIVREM . getValue ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , VT , DIVREM . getValue ( <NUM_LIT> ) ) } ; return DAG . getMergeValues ( Res , DL ) ; } SDValue LHSign = DAG . getSelectCC ( DL , LHS , Zero , NegOne , Zero , <STR_LIT> ) ; SDValue RHSign = DAG . getSelectCC ( DL , RHS , Zero , NegOne , Zero , <STR_LIT> ) ; SDValue DSign = DAG . getNode ( <STR_LIT> , DL , VT , LHSign , RHSign ) ; SDValue RSign = LHSign ; LHS = DAG . getNode ( <STR_LIT> , DL , VT , LHS , LHSign ) ; RHS = DAG . getNode ( <STR_LIT> , DL , VT , RHS , RHSign ) ; LHS = DAG . getNode ( <STR_LIT> , DL , VT , LHS , LHSign ) ; RHS = DAG . getNode ( <STR_LIT> , DL , VT , RHS , RHSign ) ; SDValue Div = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , VT ) , LHS , RHS ) ; SDValue Rem = Div . getValue ( <NUM_LIT> ) ; Div = DAG . getNode ( <STR_LIT> , DL , VT , Div , DSign ) ; Rem = DAG . getNode ( <STR_LIT> , DL , VT , Rem , RSign ) ;


<s> SDValue VTOp = DAG . getValueType ( ExtraVT . getScalarType ( ) ) ; for ( unsigned I = <NUM_LIT> ; I < NElts ; ++ I ) Args [ I ] = DAG . getNode ( <STR_LIT> , DL , ScalarVT , Args [ I ] , VTOp ) ;

return DAG . getBuildVector ( VT , DL , Args ) ;


<s> MVT VT = Op . getSimpleValueType ( ) ; MVT ScalarVT = VT . getScalarType ( ) ; assert ( VT . isVector ( ) ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; unsigned NElts = VT . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > Args ;

DAG . ExtractVectorElements ( Src , Args , <NUM_LIT> , NElts ) ;


<s> SDLoc DL ( Op ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ; return DAG . getNode ( <STR_LIT> , DL , DestVT , Ext ) ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; if ( Subtarget -> has16BitInsts ( ) && DestVT == <STR_LIT> ) { SDLoc DL ( Op ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue IntToFp32 = DAG . getNode ( Op . getOpcode ( ) , DL , <STR_LIT> , Src ) ; SDValue FPRoundFlag = DAG . getIntPtrConstant ( <NUM_LIT> , SDLoc ( Op ) ) ; SDValue FPRound = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , IntToFp32 , FPRoundFlag ) ; return FPRound ; } if ( DestVT == <STR_LIT> ) return LowerINT_TO_FP32 ( Op , DAG , true ) ;


<s> SDValue Cond = DAG . getSetCC ( DL , CCVT , R , Y , <STR_LIT> ) ; Q = DAG . getNode ( <STR_LIT> , DL , VT , Cond , DAG . getNode ( <STR_LIT> , DL , VT , Q , One ) , Q ) ; R = DAG . getNode ( <STR_LIT> , DL , VT , Cond , DAG . getNode ( <STR_LIT> , DL , VT , R , Y ) , R ) ; Cond = DAG . getSetCC ( DL , CCVT , R , Y , <STR_LIT> ) ; Q = DAG . getNode ( <STR_LIT> , DL , VT , Cond , DAG . getNode ( <STR_LIT> , DL , VT , Q , One ) , Q ) ;


<s> EVT VT = Op . getValueType ( ) ; if ( VT == <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > Results ; LowerUDIVREM64 ( Op , DAG , Results ) ; return DAG . getMergeValues ( Results , DL ) ; } if ( VT == <STR_LIT> ) { if ( SDValue Res = LowerDIVREM24 ( Op , DAG , false ) ) return Res ; } SDValue X = Op . getOperand ( <NUM_LIT> ) ; SDValue Y = Op . getOperand ( <NUM_LIT> ) ; SDValue Z = DAG . getNode ( <STR_LIT> , DL , VT , Y ) ; SDValue NegY = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Y ) ; SDValue NegYZ = DAG . getNode ( <STR_LIT> , DL , VT , NegY , Z ) ; Z = DAG . getNode ( <STR_LIT> , DL , VT , Z , DAG . getNode ( <STR_LIT> , DL , VT , Z , NegYZ ) ) ; SDValue Q = DAG . getNode ( <STR_LIT> , DL , VT , X , Z ) ; SDValue R = DAG . getNode ( <STR_LIT> , DL , VT , X , DAG . getNode ( <STR_LIT> , DL , VT , Q , Y ) ) ; EVT CCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Cond = DAG . getSetCC ( DL , CCVT , R , Y , <STR_LIT> ) ; Q = DAG . getNode ( <STR_LIT> , DL , VT , Cond , DAG . getNode ( <STR_LIT> , DL , VT , Q , One ) , Q ) ; R = DAG . getNode ( <STR_LIT> , DL , VT , Cond , DAG . getNode ( <STR_LIT> , DL , VT , R , Y ) , R ) ; Cond = DAG . getSetCC ( DL , CCVT , R , Y , <STR_LIT> ) ; Q = DAG . getNode ( <STR_LIT> , DL , VT , Cond , DAG . getNode ( <STR_LIT> , DL , VT , Q , One ) , Q ) ; R = DAG . getNode ( <STR_LIT> , DL , VT , Cond , DAG . getNode ( <STR_LIT> , DL , VT , R , Y ) , R ) ; return DAG . getMergeValues ( { Q , R } , DL ) ;


<s> EVT SrcVT = Src . getValueType ( ) ; if ( SrcVT == <STR_LIT> ) { if ( DestVT == <STR_LIT> ) return Op ; SDLoc DL ( Op ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ; return DAG . getNode ( <STR_LIT> , DL , DestVT , Ext ) ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; if ( Subtarget -> has16BitInsts ( ) && DestVT == <STR_LIT> ) { SDLoc DL ( Op ) ; SDValue IntToFp32 = DAG . getNode ( Op . getOpcode ( ) , DL , <STR_LIT> , Src ) ; SDValue FPRoundFlag = DAG . getIntPtrConstant ( <NUM_LIT> , SDLoc ( Op ) ) ; SDValue FPRound = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , IntToFp32 , FPRoundFlag ) ; return FPRound ; } if ( DestVT == <STR_LIT> ) return LowerINT_TO_FP32 ( Op , DAG , false ) ; assert ( DestVT == <STR_LIT> ) ;

return LowerINT_TO_FP64 ( Op , DAG , false ) ;


<s> EVT DestVT = Op . getValueType ( ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; if ( SrcVT == <STR_LIT> ) { if ( DestVT == <STR_LIT> ) return Op ; SDLoc DL ( Op ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ;

return DAG . getNode ( <STR_LIT> , DL , DestVT , Ext ) ;


<s> StringRef FuncName ( <STR_LIT> ) ; if ( const ExternalSymbolSDNode * G = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) FuncName = G -> getSymbol ( ) ; else if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) FuncName = G -> getGlobal ( ) -> getName ( ) ; DiagnosticInfoUnsupported NoCalls ( Fn , Reason + FuncName , CLI . DL . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( NoCalls ) ;


<s> const auto Flags = Op . getNode ( ) -> getFlags ( ) ;

if ( Flags . hasNoSignedZeros ( ) ) return true ;


<s> return DAG . ComputeMaxSignificantBits ( Op ) ;


<s> unsigned <ISA_LIT>TargetLowering :: numBitsSigned ( SDValue Op , SelectionDAG & DAG ) { return DAG . ComputeMaxSignificantBits ( Op ) ;


<s> unsigned <ISA_LIT>TargetLowering :: numBitsUnsigned ( SDValue Op , SelectionDAG & DAG ) {

return DAG . computeKnownBits ( Op ) . countMaxActiveBits ( ) ;


<s> return N -> getNumOperands ( ) > <NUM_LIT> || VT == <STR_LIT> ;


<s> LLVM_READONLY static bool opMustUseVOP3Encoding ( const SDNode * N , MVT VT ) { return N -> getNumOperands ( ) > <NUM_LIT> || VT == <STR_LIT> ;


<s> SDValue <ISA_LIT>TargetLowering :: performAssertSZExtCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> ) { SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; EVT ExtVT = cast < VTSDNode > ( N1 ) -> getVT ( ) ; SDLoc SL ( N ) ; SDValue Src = N0 . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; if ( SrcVT . bitsGE ( ExtVT ) ) { SDValue NewInReg = DAG . getNode ( N -> getOpcode ( ) , SL , SrcVT , Src , N1 ) ; return DAG . getNode ( <STR_LIT> , SL , N -> getValueType ( <NUM_LIT> ) , NewInReg ) ; } }


<s> if ( ! CmpRhs || ! CmpRhs -> isZero ( ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue CmpLHS = Cond . getOperand ( <NUM_LIT> ) ; if ( CCOpcode == <STR_LIT> && ( isCtlzOpc ( RHS . getOpcode ( ) ) || isCttzOpc ( RHS . getOpcode ( ) ) ) && RHS . getOperand ( <NUM_LIT> ) == CmpLHS && isNegativeOne ( LHS ) ) { unsigned Opc = isCttzOpc ( RHS . getOpcode ( ) ) ? <STR_LIT> : <STR_LIT> ; return getFFBX_U32 ( DAG , CmpLHS , SL , Opc ) ; }

if ( CCOpcode == <STR_LIT> && ( isCtlzOpc ( LHS . getOpcode ( ) ) || isCttzOpc ( LHS . getOpcode ( ) ) ) && LHS . getOperand ( <NUM_LIT> ) == CmpLHS && isNegativeOne ( RHS ) ) {


<s> if ( ! N0 . hasOneUse ( ) ) return SDValue ( ) ; switch ( N0 . getOpcode ( ) ) { case <STR_LIT> : { assert ( ! Subtarget -> has16BitInsts ( ) && <STR_LIT> ) ; SDLoc SL ( N ) ; SDValue Src = N0 . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; SDValue IntFAbs = DAG . getNode ( <STR_LIT> , SL , SrcVT , Src , DAG . getConstant ( <NUM_LIT> , SL , SrcVT ) ) ; return DAG . getNode ( <STR_LIT> , SL , N -> getValueType ( <NUM_LIT> ) , IntFAbs ) ; }


<s> SDLoc SL ( N ) ; SDValue Src = N0 . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ;

SDValue IntFAbs = DAG . getNode ( <STR_LIT> , SL , SrcVT , Src , DAG . getConstant ( <NUM_LIT> , SL , SrcVT ) ) ;


<s> EVT VT = LN -> getMemoryVT ( ) ; unsigned Size = VT . getStoreSize ( ) ; Align Alignment = LN -> getAlign ( ) ; if ( Alignment < Size && isTypeLegal ( VT ) ) { bool IsFast ; unsigned AS = LN -> getAddressSpace ( ) ; if ( ! allowsMisalignedMemoryAccesses ( VT , AS , Alignment , LN -> getMemOperand ( ) -> getFlags ( ) , & IsFast ) ) { if ( VT . isVector ( ) ) return SplitVectorLoad ( SDValue ( LN , <NUM_LIT> ) , DAG ) ; SDValue Ops [ <NUM_LIT> ] ;

std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = expandUnalignedLoad ( LN , DAG ) ;


<s> if ( ! Subtarget -> hasMulI24 ( ) || VT . isVector ( ) ) return SDValue ( ) ; if ( Subtarget -> hasSMulHi ( ) && ! N -> isDivergent ( ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ;

SDValue N0 = N -> getOperand ( <NUM_LIT> ) ;


<s> if ( Subtarget -> hasSMulHi ( ) && ! N -> isDivergent ( ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ;

if ( ! isI24 ( N0 , DAG ) || ! isI24 ( N1 , DAG ) ) return SDValue ( ) ;


<s> if ( ! Subtarget -> hasMulU24 ( ) || VT . isVector ( ) || VT . getSizeInBits ( ) > <NUM_LIT> ) return SDValue ( ) ; if ( Subtarget -> hasSMulHi ( ) && ! N -> isDivergent ( ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ;


<s> if ( N1 . getOpcode ( ) == <STR_LIT> ) N1 = N1 . getOperand ( <NUM_LIT> ) ; unsigned LoOpcode , HiOpcode ; if ( Subtarget -> hasMulU24 ( ) && isU24 ( N0 , DAG ) && isU24 ( N1 , DAG ) ) { N0 = DAG . getZExtOrTrunc ( N0 , DL , <STR_LIT> ) ; N1 = DAG . getZExtOrTrunc ( N1 , DL , <STR_LIT> ) ; LoOpcode = <STR_LIT> ; HiOpcode = <STR_LIT> ; } else if ( Subtarget -> hasMulI24 ( ) && isI24 ( N0 , DAG ) && isI24 ( N1 , DAG ) ) {

N0 = DAG . getSExtOrTrunc ( N0 , DL , <STR_LIT> ) ;


<s> APFloat One ( Val . getSemantics ( ) , <STR_LIT> ) ;

return DCI . DAG . getConstantFP ( One / Val , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ;


<s> const auto * CFP = dyn_cast < ConstantFPSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! CFP ) return SDValue ( ) ;

const APFloat & Val = CFP -> getValueAPF ( ) ;


<s> if ( VT == <STR_LIT> && RHSVal == <NUM_LIT> && X . getValueType ( ) == <STR_LIT> && isOperationLegal ( <STR_LIT> , <STR_LIT> ) ) { SDValue Vec = DAG . getBuildVector ( <STR_LIT> , SL , { DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) , LHS -> getOperand ( <NUM_LIT> ) } ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Vec ) ; } if ( VT != <STR_LIT> ) break ; KnownBits Known = DAG . computeKnownBits ( X ) ; unsigned LZ = Known . countMinLeadingZeros ( ) ; if ( LZ < RHSVal ) break ; EVT XVT = X . getValueType ( ) ; SDValue Shl = DAG . getNode ( <STR_LIT> , SL , XVT , X , SDValue ( RHS , <NUM_LIT> ) ) ; return DAG . getZExtOrTrunc ( Shl , SL , VT ) ; } } if ( VT != <STR_LIT> ) return SDValue ( ) ; if ( RHSVal < <NUM_LIT> ) return SDValue ( ) ; SDValue ShiftAmt = DAG . getConstant ( RHSVal - <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LHS ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo , ShiftAmt ) ; const SDValue Zero = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Vec = DAG . getBuildVector ( <STR_LIT> , SL , { Zero , NewShift } ) ;


<s> if ( ! RHS ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc SL ( N ) ; unsigned RHSVal = RHS -> getZExtValue ( ) ; if ( RHSVal == <NUM_LIT> ) { SDValue Hi = getHiHalf64 ( N -> getOperand ( <NUM_LIT> ) , DAG ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ;

SDValue BuildVec = DAG . getBuildVector ( <STR_LIT> , SL , { Hi , NewShift } ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; unsigned ShiftAmt = RHS -> getZExtValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc SL ( N ) ; if ( LHS . getOpcode ( ) == <STR_LIT> ) { if ( auto * Mask = dyn_cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) ) { unsigned MaskIdx , MaskLen ; if ( Mask -> getAPIntValue ( ) . isShiftedMask ( MaskIdx , MaskLen ) && MaskIdx == ShiftAmt ) { return DAG . getNode ( <STR_LIT> , SL , VT , DAG . getNode ( <STR_LIT> , SL , VT , LHS . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , SL , VT , LHS . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ) ;


<s> if ( auto * Mask = dyn_cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) ) { unsigned MaskIdx , MaskLen ; if ( Mask -> getAPIntValue ( ) . isShiftedMask ( MaskIdx , MaskLen ) && MaskIdx == ShiftAmt ) { return DAG . getNode ( <STR_LIT> , SL , VT , DAG . getNode ( <STR_LIT> , SL , VT , LHS . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , SL , VT , LHS . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ) ; } } } if ( VT != <STR_LIT> ) return SDValue ( ) ; if ( ShiftAmt < <NUM_LIT> ) return SDValue ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Hi = getHiHalf64 ( LHS , DAG ) ; SDValue NewConst = DAG . getConstant ( ShiftAmt - <NUM_LIT> , SL , <STR_LIT> ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi , NewConst ) ; SDValue BuildPair = DAG . getBuildVector ( <STR_LIT> , SL , { NewShift , Zero } ) ;

return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BuildPair ) ;


<s> EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue Val = SN -> getValue ( ) ; bool OtherUses = ! Val . hasOneUse ( ) ; SDValue CastVal = DAG . getNode ( <STR_LIT> , SL , NewVT , Val ) ; if ( OtherUses ) { SDValue CastBack = DAG . getNode ( <STR_LIT> , SL , VT , CastVal ) ; DAG . ReplaceAllUsesOfValueWith ( Val , CastBack ) ; }

return DAG . getStore ( SN -> getChain ( ) , SL , CastVal , SN -> getBasePtr ( ) , SN -> getMemOperand ( ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: performStoreCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { if ( ! DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; StoreSDNode * SN = cast < StoreSDNode > ( N ) ; if ( ! SN -> isSimple ( ) || ! <STR_LIT> ( SN ) ) return SDValue ( ) ; EVT VT = SN -> getMemoryVT ( ) ; unsigned Size = VT . getStoreSize ( ) ; SDLoc SL ( N ) ; SelectionDAG & DAG = DCI . DAG ; Align Alignment = SN -> getAlign ( ) ; if ( Alignment < Size && isTypeLegal ( VT ) ) { bool IsFast ; unsigned AS = SN -> getAddressSpace ( ) ; if ( ! allowsMisalignedMemoryAccesses ( VT , AS , Alignment , SN -> getMemOperand ( ) -> getFlags ( ) , & IsFast ) ) { if ( VT . isVector ( ) ) return SplitVectorStore ( SDValue ( SN , <NUM_LIT> ) , DAG ) ; return expandUnalignedStore ( SN , DAG ) ; } if ( ! IsFast ) return SDValue ( ) ; }

if ( ! shouldCombineMemoryType ( VT ) ) return SDValue ( ) ;


<s> SDValue Vec = Src . getOperand ( <NUM_LIT> ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) { SDValue Elt0 = Vec . getOperand ( <NUM_LIT> ) ; EVT EltVT = Elt0 . getValueType ( ) ; if ( VT . getFixedSizeInBits ( ) <= EltVT . getFixedSizeInBits ( ) ) { if ( EltVT . isFloatingPoint ( ) ) { Elt0 = DAG . getNode ( <STR_LIT> , SL , EltVT . changeTypeToInteger ( ) , Elt0 ) ; } return DAG . getNode ( <STR_LIT> , SL , VT , Elt0 ) ; } } } if ( Src . getOpcode ( ) == <STR_LIT> && ! VT . isVector ( ) ) { if ( auto K = isConstOrConstSplat ( Src . getOperand ( <NUM_LIT> ) ) ) { if ( <NUM_LIT> * K -> getZExtValue ( ) == Src . getValueType ( ) . getScalarSizeInBits ( ) ) { SDValue BV = stripBitcast ( Src . getOperand ( <NUM_LIT> ) ) ; if ( BV . getOpcode ( ) == <STR_LIT> && BV . getValueType ( ) . getVectorNumElements ( ) == <NUM_LIT> ) { SDValue SrcElt = BV . getOperand ( <NUM_LIT> ) ; EVT SrcEltVT = SrcElt . getValueType ( ) ;


<s> if ( ( Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> ) && ! VT . isVector ( ) ) return false ; if ( Size == <NUM_LIT> || ( Size > <NUM_LIT> && ( Size % <NUM_LIT> != <NUM_LIT> ) ) ) return false ; return true ;


<s> if ( ! VT . isByteSized ( ) ) return false ; unsigned Size = VT . getStoreSize ( ) ; if ( ( Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> ) && ! VT . isVector ( ) ) return false ; if ( Size == <NUM_LIT> || ( Size > <NUM_LIT> && ( Size % <NUM_LIT> != <NUM_LIT> ) ) ) return false ; return true ;


<s> case AtomicRMWInst :: FSub : return AtomicExpansionKind :: CmpXChg ; default :


<s> MemSDNode * MN = cast < MemSDNode > ( N ) ; unsigned AS = MN -> getAddressSpace ( ) ;

if ( OldSize >= <NUM_LIT> && NewSize < <NUM_LIT> && MN -> getAlignment ( ) >= <NUM_LIT> && ( AS == <ISA_LIT>AS :: CONSTANT_ADDRESS || AS == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT || ( isa < LoadSDNode > ( N ) && AS == <ISA_LIT>AS :: GLOBAL_ADDRESS && MN -> isInvariant ( ) ) ) && <ISA_LIT>InstrInfo :: isUniformMMO ( MN -> getMemOperand ( ) ) ) return false ;


<s> switch ( IID ) { case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } APInt Demanded = APInt :: getLowBitsSet ( LHS . getValueSizeInBits ( ) , <NUM_LIT> ) ; SDValue DemandedLHS = TLI . SimplifyMultipleUseDemandedBits ( LHS , Demanded , DAG ) ; SDValue DemandedRHS = TLI . SimplifyMultipleUseDemandedBits ( RHS , Demanded , DAG ) ;

if ( DemandedLHS || DemandedRHS ) return DAG . getNode ( NewOpcode , SDLoc ( Node24 ) , Node24 -> getVTList ( ) , DemandedLHS ? DemandedLHS : LHS , DemandedRHS ? DemandedRHS : RHS ) ;


<s> SDLoc SL ( Op ) ; SDValue Vec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Op ) ; const SDValue Zero = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ;

const SDValue One = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ;


<s> SDValue HiRHS = DAG . getConstant ( ValHi , SL , <STR_LIT> ) ; SDValue LoAnd = DAG . getNode ( Opc , SL , <STR_LIT> , Lo , LoRHS ) ; SDValue HiAnd = DAG . getNode ( Opc , SL , <STR_LIT> , Hi , HiRHS ) ; DCI . AddToWorklist ( Lo . getNode ( ) ) ; DCI . AddToWorklist ( Hi . getNode ( ) ) ; SDValue Vec = DAG . getBuildVector ( <STR_LIT> , SL , { LoAnd , HiAnd } ) ;


<s> assert ( LoVT . getVectorNumElements ( ) + ( HiVT . isVector ( ) ? HiVT . getVectorNumElements ( ) : <NUM_LIT> ) <= N . getValueType ( ) . getVectorNumElements ( ) && <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , LoVT , N , DAG . getVectorIdxConstant ( <NUM_LIT> , DL ) ) ;

SDValue Hi = DAG . getNode ( HiVT . isVector ( ) ? <STR_LIT> : <STR_LIT> , DL , HiVT , N , DAG . getVectorIdxConstant ( LoVT . getVectorNumElements ( ) , DL ) ) ;


<s> std :: pair < SDValue , SDValue > <ISA_LIT>TargetLowering :: splitVector ( const SDValue & N , const SDLoc & DL , const EVT & LoVT , const EVT & HiVT , SelectionDAG & DAG ) const { assert ( LoVT . getVectorNumElements ( ) + ( HiVT . isVector ( ) ? HiVT . getVectorNumElements ( ) : <NUM_LIT> ) <= N . getValueType ( ) . getVectorNumElements ( ) && <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , LoVT , N , DAG . getVectorIdxConstant ( <NUM_LIT> , DL ) ) ;


<s> SDValue Ops [ <NUM_LIT> ] ; std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = scalarizeVectorLoad ( Load , DAG ) ; return DAG . getMergeValues ( Ops , SL ) ; } SDValue BasePtr = Load -> getBasePtr ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; const MachinePointerInfo & SrcValue = Load -> getMemOperand ( ) -> getPointerInfo ( ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = getSplitDestVTs ( VT , DAG ) ; std :: tie ( LoMemVT , HiMemVT ) = getSplitDestVTs ( MemVT , DAG ) ; std :: tie ( Lo , Hi ) = splitVector ( Op , SL , LoVT , HiVT , DAG ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned BaseAlign = Load -> getAlignment ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , LoVT , Load -> getChain ( ) , BasePtr , SrcValue , LoMemVT , BaseAlign , Load -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue HiPtr = DAG . getObjectPtrOffset ( SL , BasePtr , TypeSize :: Fixed ( Size ) ) ; SDValue HiLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , HiVT , Load -> getChain ( ) , HiPtr , SrcValue . getWithOffset ( LoMemVT . getStoreSize ( ) ) , HiMemVT , HiAlign , Load -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Join ; if ( LoVT == HiVT ) { Join = DAG . getNode ( <STR_LIT> , SL , VT , LoLoad , HiLoad ) ; } else { Join = DAG . getNode ( <STR_LIT> , SL , VT , DAG . getUNDEF ( VT ) , LoLoad , DAG . getVectorIdxConstant ( <NUM_LIT> , SL ) ) ; Join = DAG . getNode ( HiVT . isVector ( ) ? <STR_LIT> : <STR_LIT> , SL , VT , Join , HiLoad , DAG . getVectorIdxConstant ( LoVT . getVectorNumElements ( ) , SL ) ) ; } SDValue Ops [ ] = { Join , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LoLoad . getValue ( <NUM_LIT> ) , HiLoad . getValue ( <NUM_LIT> ) ) } ; return DAG . getMergeValues ( Ops , SL ) ;


<s> if ( VT . getVectorNumElements ( ) == <NUM_LIT> ) { SDValue Ops [ <NUM_LIT> ] ; std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = scalarizeVectorLoad ( Load , DAG ) ; return DAG . getMergeValues ( Ops , SL ) ; } SDValue BasePtr = Load -> getBasePtr ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; const MachinePointerInfo & SrcValue = Load -> getMemOperand ( ) -> getPointerInfo ( ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = getSplitDestVTs ( VT , DAG ) ; std :: tie ( LoMemVT , HiMemVT ) = getSplitDestVTs ( MemVT , DAG ) ; std :: tie ( Lo , Hi ) = splitVector ( Op , SL , LoVT , HiVT , DAG ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned BaseAlign = Load -> getAlignment ( ) ;

unsigned HiAlign = MinAlign ( BaseAlign , Size ) ;


<s> std :: tie ( Lo , Hi ) = splitVector ( Val , SL , LoVT , HiVT , DAG ) ; SDValue HiPtr = DAG . getObjectPtrOffset ( SL , BasePtr , LoMemVT . getStoreSize ( ) ) ; const MachinePointerInfo & SrcValue = Store -> getMemOperand ( ) -> getPointerInfo ( ) ; unsigned BaseAlign = Store -> getAlignment ( ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoStore = DAG . getTruncStore ( Chain , SL , Lo , BasePtr , SrcValue , LoMemVT , BaseAlign , Store -> getMemOperand ( ) -> getFlags ( ) ) ;

SDValue HiStore = DAG . getTruncStore ( Chain , SL , Hi , HiPtr , SrcValue . getWithOffset ( Size ) , HiMemVT , HiAlign , Store -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> SDValue SP = DAG . getCopyFromReg ( Chain , SL , Info -> getStackPtrOffsetReg ( ) , <STR_LIT> ) ; Ptr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , SP , Ptr ) ; SDValue Store = DAG . getStore ( Chain , SL , ArgVal , Ptr , DstInfo , Align ( <NUM_LIT> ) , MachineMemOperand :: MODereferenceable ) ; return Store ;


<s> SDValue <ISA_LIT>TargetLowering :: WidenOrSplitVectorLoad ( SDValue Op , SelectionDAG & DAG ) const { LoadSDNode * Load = cast < LoadSDNode > ( Op ) ; EVT VT = Op . getValueType ( ) ; SDValue BasePtr = Load -> getBasePtr ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; SDLoc SL ( Op ) ; const MachinePointerInfo & SrcValue = Load -> getMemOperand ( ) -> getPointerInfo ( ) ; unsigned BaseAlign = Load -> getAlignment ( ) ; unsigned NumElements = MemVT . getVectorNumElements ( ) ; if ( NumElements != <NUM_LIT> || ( BaseAlign < <NUM_LIT> && ! SrcValue . isDereferenceable ( <NUM_LIT> , * DAG . getContext ( ) , DAG . getDataLayout ( ) ) ) ) return SplitVectorLoad ( Op , DAG ) ; assert ( NumElements == <NUM_LIT> ) ; EVT WideVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , <NUM_LIT> ) ; EVT WideMemVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MemVT . getVectorElementType ( ) , <NUM_LIT> ) ;

SDValue WideLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , WideVT , Load -> getChain ( ) , BasePtr , SrcValue , WideMemVT , BaseAlign , Load -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> switch ( ID ) { case <STR_LIT> : return <NUM_LIT> ;


<s> int64_t LastByte = FirstByte + MFI . getObjectSize ( ClobberedFI ) - <NUM_LIT> ; ArgChains . push_back ( Chain ) ; for ( SDNode :: use_iterator U = DAG . getEntryNode ( ) . getNode ( ) -> use_begin ( ) , UE = DAG . getEntryNode ( ) . getNode ( ) -> use_end ( ) ; U != UE ; ++ U ) { if ( LoadSDNode * L = dyn_cast < LoadSDNode > ( * U ) ) { if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( L -> getBasePtr ( ) ) ) { if ( FI -> getIndex ( ) < <NUM_LIT> ) { int64_t InFirstByte = MFI . getObjectOffset ( FI -> getIndex ( ) ) ; int64_t InLastByte = InFirstByte ; InLastByte += MFI . getObjectSize ( FI -> getIndex ( ) ) - <NUM_LIT> ; if ( ( InFirstByte <= FirstByte && FirstByte <= InLastByte ) || ( FirstByte <= InFirstByte && InFirstByte <= LastByte ) ) ArgChains . push_back ( SDValue ( L , <NUM_LIT> ) ) ;


<s> ComputeValueVTs ( * this , DL , BaseArgTy , ValueVTs , & Offsets , ArgOffset ) ; for ( unsigned Value = <NUM_LIT> , NumValues = ValueVTs . size ( ) ; Value != NumValues ; ++ Value ) { uint64_t BasePartOffset = Offsets [ Value ] ; EVT ArgVT = ValueVTs [ Value ] ; EVT MemVT = ArgVT ; MVT RegisterVT = getRegisterTypeForCallingConv ( Ctx , CC , ArgVT ) ; unsigned NumRegs = getNumRegistersForCallingConv ( Ctx , CC , ArgVT ) ; if ( NumRegs == <NUM_LIT> ) { if ( ArgVT . isExtended ( ) ) { MemVT = RegisterVT ; } else { MemVT = ArgVT ; } } else if ( ArgVT . isVector ( ) && RegisterVT . isVector ( ) && ArgVT . getScalarType ( ) == RegisterVT . getScalarType ( ) ) { assert ( ArgVT . getVectorNumElements ( ) > RegisterVT . getVectorNumElements ( ) ) ; MemVT = RegisterVT ; } else if ( ArgVT . isVector ( ) && ArgVT . getVectorNumElements ( ) == NumRegs ) { MemVT = ArgVT . getScalarType ( ) ; } else if ( ArgVT . isExtended ( ) ) { MemVT = RegisterVT ; } else { unsigned MemoryBits = ArgVT . getStoreSizeInBits ( ) / NumRegs ; assert ( ArgVT . getStoreSizeInBits ( ) % NumRegs == <NUM_LIT> ) ; if ( RegisterVT . isInteger ( ) ) { MemVT = EVT :: getIntegerVT ( State . getContext ( ) , MemoryBits ) ; } else if ( RegisterVT . isVector ( ) ) { assert ( ! RegisterVT . getScalarType ( ) . isFloatingPoint ( ) ) ; unsigned NumElements = RegisterVT . getVectorNumElements ( ) ; assert ( MemoryBits % NumElements == <NUM_LIT> ) ; EVT ScalarVT = EVT :: getIntegerVT ( State . getContext ( ) , MemoryBits / NumElements ) ; MemVT = EVT :: getVectorVT ( State . getContext ( ) , ScalarVT , NumElements ) ; } else { llvm_unreachable ( <STR_LIT> ) ; }


<s> case CallingConv :: <ISA_LIT>_GS : case CallingConv :: <ISA_LIT>_PS : case CallingConv :: <ISA_LIT>_CS : case CallingConv :: <ISA_LIT>_HS : case CallingConv :: <ISA_LIT>_ES : case CallingConv :: <ISA_LIT>_LS : return RetCC_<ISA_LIT>_Shader ; case CallingConv :: C :


<s> if ( ! MRI . isLiveIn ( Reg ) ) { VReg = MRI . createVirtualRegister ( RC ) ; MRI . addLiveIn ( Reg , VReg ) ; } else { VReg = MRI . getLiveInVirtReg ( Reg ) ;


<s> uint32_t <ISA_LIT>TargetLowering :: getImplicitParameterOffset ( const MachineFunction & MF , const ImplicitParameter Param ) const { const <ISA_LIT>MachineFunction * MFI = MF . getInfo < <ISA_LIT>MachineFunction > ( ) ; const <ISA_LIT>Subtarget & ST = <ISA_LIT>Subtarget :: get ( getTargetMachine ( ) , MF . getFunction ( ) ) ; unsigned ExplicitArgOffset = ST . getExplicitKernelArgOffset ( MF . getFunction ( ) ) ; unsigned Alignment = ST . getAlignmentForImplicitArgPtr ( ) ; uint64_t ArgOffset = alignTo ( MFI -> getExplicitKernArgSize ( ) , Alignment ) + ExplicitArgOffset ;


<s> unsigned ExplicitArgOffset = ST . getExplicitKernelArgOffset ( MF . getFunction ( ) ) ; unsigned Alignment = ST . getAlignmentForImplicitArgPtr ( ) ; uint64_t ArgOffset = alignTo ( MFI -> getExplicitKernArgSize ( ) , Alignment ) + ExplicitArgOffset ;


<s> unsigned MulOpc = Signed ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( MulOpc , SL , <STR_LIT> , N0 , N1 ) ; } unsigned MulOpc = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Mul = DAG . getNode ( MulOpc , SL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , N0 , N1 ) ;

return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Mul . getValue ( <NUM_LIT> ) , Mul . getValue ( <NUM_LIT> ) ) ;


<s> const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVar || ! GVar -> hasInitializer ( ) ) return false ; return ! isa < UndefValue > ( GVar -> getInitializer ( ) ) ;


<s> if ( isa < MemSDNode > ( N ) ) return false ; switch ( N -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>TargetLowering :: isFNegFree ( EVT VT ) const {


return VT . getSizeInBits ( ) >= <NUM_LIT> && <ISA_LIT>TargetLowering :: numBitsSigned ( Op , DAG ) < <NUM_LIT> ;


<s> static bool isI24 ( SDValue Op , SelectionDAG & DAG ) { EVT VT = Op . getValueType ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return false ; } case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SNaN ; case <STR_LIT> : case <STR_LIT> : { return SNaN ; } case <STR_LIT> : { unsigned IntrinsicID = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntrinsicID ) { case <STR_LIT> : return true ; case <STR_LIT> : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ; } case <STR_LIT> : {


<s> if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Val ) ) return C -> isAllOnesValue ( ) ;


<s> return true ; } } break ; case <STR_LIT> : { if ( cast < LoadSDNode > ( N ) -> getMemOperand ( ) -> getAddrSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) return true ; return false ; } break ; }


<s> int FI = getOrCreateFixedStackObject ( MFI , VT . getStoreSize ( ) , Offset ) ; auto SrcPtrInfo = MachinePointerInfo :: getStack ( MF , Offset ) ;

SDValue Ptr = DAG . getFrameIndex ( FI , <STR_LIT> ) ;


<s> auto SrcPtrInfo = MachinePointerInfo :: getStack ( MF , Offset ) ; SDValue Ptr = DAG . getFrameIndex ( FI , <STR_LIT> ) ; return DAG . getLoad ( VT , SL , DAG . getEntryNode ( ) , Ptr , SrcPtrInfo , <NUM_LIT> , MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ;


<s> NewOpc = <STR_LIT> ; } else if ( isCttzOpc ( Op . getOpcode ( ) ) ) { ISDOpc = <STR_LIT> ; NewOpc = <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; if ( ZeroUndef && Src . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( NewOpc , SL , <STR_LIT> , Src ) ; SDValue Vec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; const SDValue Zero = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; const SDValue One = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Vec , Zero ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Vec , One ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) ; SDValue HiOrLo = isCtlzOpc ( Op . getOpcode ( ) ) ? Hi : Lo ; SDValue Hi0orLo0 = DAG . getSetCC ( SL , SetCCVT , HiOrLo , Zero , <STR_LIT> ) ; SDValue OprLo = DAG . getNode ( ISDOpc , SL , <STR_LIT> , Lo ) ; SDValue OprHi = DAG . getNode ( ISDOpc , SL , <STR_LIT> , Hi ) ;

const SDValue Bits32 = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ;


<s> SDValue fa = DAG . getNode ( ToFp , DL , FltVT , ia ) ; SDValue fb = DAG . getNode ( ToFp , DL , FltVT , ib ) ; SDValue fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fa , DAG . getNode ( <STR_LIT> , DL , FltVT , fb ) ) ; fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ; SDValue fqneg = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ; unsigned OpCode = Subtarget -> hasFP32Denormals ( ) ? ( unsigned ) <STR_LIT> : ( unsigned ) <STR_LIT> ; SDValue fr = DAG . getNode ( OpCode , DL , FltVT , fqneg , fb , fa ) ; SDValue iq = DAG . getNode ( ToInt , DL , IntVT , fq ) ; fr = DAG . getNode ( <STR_LIT> , DL , FltVT , fr ) ; fb = DAG . getNode ( <STR_LIT> , DL , FltVT , fb ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue cv = DAG . getSetCC ( DL , SetCCVT , fr , fb , <STR_LIT> ) ; jq = DAG . getNode ( <STR_LIT> , DL , VT , cv , jq , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Div = DAG . getNode ( <STR_LIT> , DL , VT , iq , jq ) ; SDValue Rem = DAG . getNode ( <STR_LIT> , DL , VT , Div , RHS ) ; Rem = DAG . getNode ( <STR_LIT> , DL , VT , LHS , Rem ) ; if ( Sign ) { SDValue InRegSize = DAG . getValueType ( EVT :: getIntegerVT ( * DAG . getContext ( ) , DivBits ) ) ; Div = DAG . getNode ( <STR_LIT> , DL , VT , Div , InRegSize ) ; Rem = DAG . getNode ( <STR_LIT> , DL , VT , Rem , InRegSize ) ; } else { SDValue TruncMask = DAG . getConstant ( ( UINT64_C ( <NUM_LIT> ) << DivBits ) - <NUM_LIT> , DL , VT ) ; Div = DAG . getNode ( <STR_LIT> , DL , VT , Div , TruncMask ) ; Rem = DAG . getNode ( <STR_LIT> , DL , VT , Rem , TruncMask ) ;


<s> EVT VT = Op . getValueType ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; MVT IntVT = <STR_LIT> ; MVT FltVT = <STR_LIT> ; unsigned LHSSignBits = DAG . ComputeNumSignBits ( LHS ) ; if ( LHSSignBits < <NUM_LIT> ) return SDValue ( ) ; unsigned RHSSignBits = DAG . ComputeNumSignBits ( RHS ) ; if ( RHSSignBits < <NUM_LIT> ) return SDValue ( ) ; unsigned BitSize = VT . getSizeInBits ( ) ; unsigned SignBits = std :: min ( LHSSignBits , RHSSignBits ) ; unsigned DivBits = BitSize - SignBits ; if ( Sign ) ++ DivBits ; <STR_LIT> ToFp = Sign ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ToInt = Sign ? <STR_LIT> : <STR_LIT> ; SDValue jq = DAG . getConstant ( <NUM_LIT> , DL , IntVT ) ; if ( Sign ) { jq = DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS ) ; jq = DAG . getNode ( <STR_LIT> , DL , VT , jq , DAG . getConstant ( BitSize - <NUM_LIT> , DL , VT ) ) ; jq = DAG . getNode ( <STR_LIT> , DL , VT , jq , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; } SDValue ia = LHS ; SDValue ib = RHS ; SDValue fa = DAG . getNode ( ToFp , DL , FltVT , ia ) ; SDValue fb = DAG . getNode ( ToFp , DL , FltVT , ib ) ; SDValue fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fa , DAG . getNode ( <STR_LIT> , DL , FltVT , fb ) ) ; fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ;

SDValue fqneg = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ;


<s> DAG . ExtractVectorElements ( Op . getOperand ( <NUM_LIT> ) , Args , Start , VT . getVectorNumElements ( ) ) ; return DAG . getBuildVector ( Op . getValueType ( ) , SDLoc ( Op ) , Args ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerEXTRACT_SUBVECTOR ( SDValue Op , SelectionDAG & DAG ) const { SmallVector < SDValue , <NUM_LIT> > Args ; unsigned Start = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Op . getValueType ( ) ; DAG . ExtractVectorElements ( Op . getOperand ( <NUM_LIT> ) , Args , Start , VT . getVectorNumElements ( ) ) ; return DAG . getBuildVector ( Op . getValueType ( ) , SDLoc ( Op ) , Args ) ;


<s> SDLoc SL ( Op ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; SDValue K0 = DAG . getConstantFP ( BitsToDouble ( UINT64_C ( <NUM_LIT> ) ) , SL , <STR_LIT> ) ; SDValue K1 = DAG . getConstantFP ( BitsToDouble ( UINT64_C ( <NUM_LIT> ) ) , SL , <STR_LIT> ) ;

SDValue Mul = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Trunc , K0 ) ;


<s> SDValue FpToInt32 = DAG . getNode ( Op . getOpcode ( ) , DL , <STR_LIT> , FPExtend ) ; return FpToInt32 ; } if ( Op . getValueType ( ) == <STR_LIT> && Src . getValueType ( ) == <STR_LIT> ) return LowerFP64_TO_INT ( Op , DAG , true ) ; return SDValue ( ) ;


<s> if ( Subtarget -> has16BitInsts ( ) && SrcVT == <STR_LIT> ) { SDLoc DL ( Op ) ; SDValue FPExtend = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ; SDValue FpToInt32 = DAG . getNode ( Op . getOpcode ( ) , DL , <STR_LIT> , FPExtend ) ; return FpToInt32 ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFROUND ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return LowerFROUND32_16 ( Op , DAG ) ;

if ( VT == <STR_LIT> ) return LowerFROUND64 ( Op , DAG ) ;


<s> if ( VT == <STR_LIT> || VT == <STR_LIT> ) return LowerFROUND32_16 ( Op , DAG ) ; if ( VT == <STR_LIT> ) return LowerFROUND64 ( Op , DAG ) ;


<s> const SDValue Half = DAG . getConstantFP ( <NUM_LIT> , SL , VT ) ; SDValue SignOne = DAG . getNode ( <STR_LIT> , SL , VT , One , X ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue Cmp = DAG . getSetCC ( SL , SetCCVT , AbsDiff , Half , <STR_LIT> ) ; SDValue Sel = DAG . getNode ( <STR_LIT> , SL , VT , Cmp , SignOne , Zero ) ; return DAG . getNode ( <STR_LIT> , SL , VT , T , Sel ) ;


<s> const SDValue Zero = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; const SDValue One = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue VecSrc = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , VecSrc , One ) ; SDValue Exp = extractF64Exponent ( Hi , SL , DAG ) ; const unsigned FractBits = <NUM_LIT> ; const SDValue SignBitMask = DAG . getConstant ( UINT32_C ( <NUM_LIT> ) << <NUM_LIT> , SL , <STR_LIT> ) ; SDValue SignBit = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi , SignBitMask ) ; SDValue SignBit64 = DAG . getBuildVector ( <STR_LIT> , SL , { Zero , SignBit } ) ; SignBit64 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , SignBit64 ) ; SDValue BcInt = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; const SDValue FractMask = DAG . getConstant ( ( UINT64_C ( <NUM_LIT> ) << FractBits ) - <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Shr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , FractMask , Exp ) ;

SDValue Not = DAG . getNOT ( SL , Shr , <STR_LIT> ) ;


<s> assert ( Op . getValueType ( ) == <STR_LIT> ) ; const SDValue Zero = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; const SDValue One = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue VecSrc = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , VecSrc , One ) ; SDValue Exp = extractF64Exponent ( Hi , SL , DAG ) ; const unsigned FractBits = <NUM_LIT> ; const SDValue SignBitMask = DAG . getConstant ( UINT32_C ( <NUM_LIT> ) << <NUM_LIT> , SL , <STR_LIT> ) ; SDValue SignBit = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi , SignBitMask ) ; SDValue SignBit64 = DAG . getBuildVector ( <STR_LIT> , SL , { Zero , SignBit } ) ; SignBit64 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , SignBit64 ) ; SDValue BcInt = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; const SDValue FractMask = DAG . getConstant ( ( UINT64_C ( <NUM_LIT> ) << FractBits ) - <NUM_LIT> , SL , <STR_LIT> ) ;

SDValue Shr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , FractMask , Exp ) ;


<s> GlobalAddressSDNode * G = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = G -> getGlobal ( ) ; if ( G -> getAddressSpace ( ) == <ISA_LIT>AS :: LOCAL_ADDRESS || G -> getAddressSpace ( ) == <ISA_LIT>AS :: REGION_ADDRESS ) { if ( ! MFI -> isEntryFunction ( ) ) { const Function & Fn = DAG . getMachineFunction ( ) . getFunction ( ) ; DiagnosticInfoUnsupported BadLDSDecl ( Fn , <STR_LIT> , SDLoc ( Op ) . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( BadLDSDecl ) ; } assert ( G -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ! hasDefinedInitializer ( GV ) ) { unsigned Offset = MFI -> allocateLDSGlobal ( DL , * GV ) ;

return DAG . getConstant ( Offset , SDLoc ( Op ) , Op . getValueType ( ) ) ;


<s> SDValue LZ = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , L ) ; LZ = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LZ ) ; SDValue K = DAG . getConstant ( <NUM_LIT> + <NUM_LIT> , SL , <STR_LIT> ) ; SDValue E = DAG . getSelect ( SL , <STR_LIT> , DAG . getSetCC ( SL , SetCCVT , L , ZeroI64 , <STR_LIT> ) , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , K , LZ ) , ZeroI32 ) ; SDValue U = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , L , LZ ) , DAG . getConstant ( ( - <NUM_LIT> ) >> <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue T = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , U , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue UShl = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , U , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue V = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , E , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , UShl ) ) ; SDValue C = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue RCmp = DAG . getSetCC ( SL , SetCCVT , T , C , <STR_LIT> ) ; SDValue TCmp = DAG . getSetCC ( SL , SetCCVT , T , C , <STR_LIT> ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue VTrunc1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , V , One ) ; SDValue R = DAG . getSelect ( SL , <STR_LIT> , RCmp , One , DAG . getSelect ( SL , <STR_LIT> , TCmp , VTrunc1 , ZeroI32 ) ) ; R = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , V , R ) ; R = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , R ) ;


<s> case <STR_LIT> : return LowerFCEIL ( Op , DAG ) ; case <STR_LIT> : return LowerFTRUNC ( Op , DAG ) ; case <STR_LIT> : return LowerFRINT ( Op , DAG ) ; case <STR_LIT> : return LowerFNEARBYINT ( Op , DAG ) ; case <STR_LIT> : return LowerFROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFFLOOR ( Op , DAG ) ; case <STR_LIT> : return LowerFLOG ( Op , DAG , <NUM_LIT> / numbers :: log2ef ) ; case <STR_LIT> : return LowerFLOG ( Op , DAG , numbers :: ln2f / numbers :: ln10f ) ; case <STR_LIT> : return lowerFEXP ( Op , DAG ) ; case <STR_LIT> : return Lower<ISA_LIT>NT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_FP16 ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_<ISA_LIT>NT ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> case <STR_LIT> : return LowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerFREM ( Op , DAG ) ; case <STR_LIT> : return LowerFCEIL ( Op , DAG ) ; case <STR_LIT> : return LowerFTRUNC ( Op , DAG ) ; case <STR_LIT> : return LowerFRINT ( Op , DAG ) ; case <STR_LIT> : return LowerFNEARBYINT ( Op , DAG ) ; case <STR_LIT> : return LowerFROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFFLOOR ( Op , DAG ) ; case <STR_LIT> : return LowerFLOG ( Op , DAG , <NUM_LIT> / numbers :: log2ef ) ; case <STR_LIT> : return LowerFLOG ( Op , DAG , numbers :: ln2f / numbers :: ln10f ) ; case <STR_LIT> : return lowerFEXP ( Op , DAG ) ; case <STR_LIT> : return Lower<ISA_LIT>NT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_FP16 ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_<ISA_LIT>NT ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerCTLZ_CTTZ ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; }


<s> SDValue FPRoundFlag = DAG . getIntPtrConstant ( <NUM_LIT> , SDLoc ( Op ) ) ; SDValue FPRound = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , IntToFp32 , FPRoundFlag ) ; return FPRound ; }

if ( DestVT == <STR_LIT> ) return LowerINT_TO_FP32 ( Op , DAG , true ) ;


<s> SDValue Tmp1 = DAG . getNode ( <STR_LIT> , DL , VT , Remainder_GE_Den , Remainder_GE_Zero ) ; SDValue Quotient_A_One = DAG . getNode ( <STR_LIT> , DL , VT , Quotient , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Quotient_S_One = DAG . getNode ( <STR_LIT> , DL , VT , Quotient , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Div = DAG . getSelectCC ( DL , Tmp1 , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Quotient , Quotient_A_One , <STR_LIT> ) ; Div = DAG . getSelectCC ( DL , Remainder_GE_Zero , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Quotient_S_One , Div , <STR_LIT> ) ; SDValue Remainder_S_Den = DAG . getNode ( <STR_LIT> , DL , VT , Remainder , Den ) ; SDValue Remainder_A_Den = DAG . getNode ( <STR_LIT> , DL , VT , Remainder , Den ) ; SDValue Rem = DAG . getSelectCC ( DL , Tmp1 , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Remainder , Remainder_S_Den , <STR_LIT> ) ; Rem = DAG . getSelectCC ( DL , Remainder_GE_Zero , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Remainder_A_Den , Rem , <STR_LIT> ) ; SDValue Ops [ <NUM_LIT> ] = {


<s> SDValue <ISA_LIT>TargetLowering :: LowerUINT_TO_FP ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; EVT DestVT = Op . getValueType ( ) ; if ( Subtarget -> has16BitInsts ( ) && DestVT == <STR_LIT> ) { SDLoc DL ( Op ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue IntToFp32 = DAG . getNode ( Op . getOpcode ( ) , DL , <STR_LIT> , Src ) ; SDValue FPRoundFlag = DAG . getIntPtrConstant ( <NUM_LIT> , SDLoc ( Op ) ) ;

SDValue FPRound = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , IntToFp32 , FPRoundFlag ) ;


<s> EVT VT = Op . getValueType ( ) ; return VT . getSizeInBits ( ) - DAG . ComputeNumSignBits ( Op ) ;


<s> unsigned <ISA_LIT>TargetLowering :: numBitsUnsigned ( SDValue Op , SelectionDAG & DAG ) { EVT VT = Op . getValueType ( ) ;

KnownBits Known = DAG . computeKnownBits ( Op ) ;


<s> unsigned <ISA_LIT>TargetLowering :: numBitsUnsigned ( SDValue Op , SelectionDAG & DAG ) { EVT VT = Op . getValueType ( ) ; KnownBits Known = DAG . computeKnownBits ( Op ) ;

return VT . getSizeInBits ( ) - Known . countMinLeadingZeros ( ) ;


<s> ConstantSDNode * CmpRhs = dyn_cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ; if ( ! CmpRhs || ! CmpRhs -> isNullValue ( ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue CmpLHS = Cond . getOperand ( <NUM_LIT> ) ; unsigned Opc = isCttzOpc ( RHS . getOpcode ( ) ) ? <STR_LIT> : <STR_LIT> ; if ( CCOpcode == <STR_LIT> && ( isCtlzOpc ( RHS . getOpcode ( ) ) || isCttzOpc ( RHS . getOpcode ( ) ) ) && RHS . getOperand ( <NUM_LIT> ) == CmpLHS && isNegativeOne ( LHS ) ) { return getFFBX_U32 ( DAG , CmpLHS , SL , Opc ) ; } if ( CCOpcode == <STR_LIT> && ( isCtlzOpc ( LHS . getOpcode ( ) ) || isCttzOpc ( RHS . getOpcode ( ) ) ) && LHS . getOperand ( <NUM_LIT> ) == CmpLHS && isNegativeOne ( RHS ) ) { return getFFBX_U32 ( DAG , CmpLHS , SL , Opc ) ; } return SDValue ( ) ;


<s> bool Signed = N -> getOpcode ( ) == <STR_LIT> ; if ( OffsetVal == <NUM_LIT> ) { unsigned SignBits = Signed ? ( <NUM_LIT> - WidthVal + <NUM_LIT> ) : ( <NUM_LIT> - WidthVal ) ; unsigned OpSignBits = DAG . ComputeNumSignBits ( BitsFrom ) ; if ( OpSignBits >= SignBits ) return BitsFrom ; EVT SmallVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , WidthVal ) ; if ( Signed ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BitsFrom , DAG . getValueType ( SmallVT ) ) ; } return DAG . getZeroExtendInReg ( BitsFrom , DL , SmallVT ) ; } if ( ConstantSDNode * CVal = dyn_cast < ConstantSDNode > ( BitsFrom ) ) { if ( Signed ) { return constantFoldBFE < int32_t > ( DAG , CVal -> getSExtValue ( ) , OffsetVal , WidthVal , DL ) ; } return constantFoldBFE < uint32_t > ( DAG , CVal -> getZExtValue ( ) , OffsetVal , WidthVal , DL ) ; } if ( ( OffsetVal + WidthVal ) >= <NUM_LIT> && ! ( Subtarget -> hasSDWA ( ) && OffsetVal == <NUM_LIT> && WidthVal == <NUM_LIT> ) ) { SDValue ShiftVal = DAG . getConstant ( OffsetVal , DL , <STR_LIT> ) ; return DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , BitsFrom , ShiftVal ) ; } if ( BitsFrom . hasOneUse ( ) ) { APInt Demanded = APInt :: getBitsSet ( <NUM_LIT> , OffsetVal , OffsetVal + WidthVal ) ; KnownBits Known ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . ShrinkDemandedConstant ( BitsFrom , Demanded , TLO ) || TLI . SimplifyDemandedBits ( BitsFrom , Demanded , Known , TLO ) ) { DCI . CommitTargetLoweringOpt ( TLO ) ; } } break ; } case <STR_LIT> : return performLoadCombine ( N , DCI ) ; case <STR_LIT> : return performStoreCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return performRcpCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return performAssertSZExtCombine ( N , DCI ) ; case <STR_LIT> : return performIntrinsicWOChainCombine ( N , DCI ) ; } return SDValue ( ) ;


<s> unsigned IID = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IID ) { case <STR_LIT> : case <STR_LIT> :


<s> EVT VT = LN -> getMemoryVT ( ) ; unsigned Size = VT . getStoreSize ( ) ; unsigned Align = LN -> getAlignment ( ) ; if ( Align < Size && isTypeLegal ( VT ) ) { bool IsFast ; unsigned AS = LN -> getAddressSpace ( ) ; if ( ! allowsMisalignedMemoryAccesses ( VT , AS , Align , LN -> getMemOperand ( ) -> getFlags ( ) , & IsFast ) ) { if ( VT . isVector ( ) ) return scalarizeVectorLoad ( LN , DAG ) ; SDValue Ops [ <NUM_LIT> ] ; std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = expandUnalignedLoad ( LN , DAG ) ; return DAG . getMergeValues ( Ops , SDLoc ( N ) ) ; } if ( ! IsFast ) return SDValue ( ) ; } if ( ! shouldCombineMemoryType ( VT ) ) return SDValue ( ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue NewLoad = DAG . getLoad ( NewVT , SL , LN -> getChain ( ) , LN -> getBasePtr ( ) , LN -> getMemOperand ( ) ) ; SDValue BC = DAG . getNode ( <STR_LIT> , SL , VT , NewLoad ) ; DCI . CombineTo ( N , BC , NewLoad . getValue ( <NUM_LIT> ) ) ;


<s> if ( VT . isVector ( ) ) return scalarizeVectorLoad ( LN , DAG ) ; SDValue Ops [ <NUM_LIT> ] ; std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = expandUnalignedLoad ( LN , DAG ) ; return DAG . getMergeValues ( Ops , SDLoc ( N ) ) ; } if ( ! IsFast ) return SDValue ( ) ; } if ( ! shouldCombineMemoryType ( VT ) ) return SDValue ( ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue NewLoad = DAG . getLoad ( NewVT , SL , LN -> getChain ( ) , LN -> getBasePtr ( ) , LN -> getMemOperand ( ) ) ; SDValue BC = DAG . getNode ( <STR_LIT> , SL , VT , NewLoad ) ; DCI . CombineTo ( N , BC , NewLoad . getValue ( <NUM_LIT> ) ) ;


<s> if ( VT . isVector ( ) || Size > <NUM_LIT> ) return SDValue ( ) ; if ( Subtarget -> has16BitInsts ( ) && VT . getScalarType ( ) . bitsLE ( <STR_LIT> ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> ) N0 = N0 . getOperand ( <NUM_LIT> ) ; if ( N1 . getOpcode ( ) == <STR_LIT> ) N1 = N1 . getOperand ( <NUM_LIT> ) ; SDValue Mul ; if ( Subtarget -> hasMulU24 ( ) && isU24 ( N0 , DAG ) && isU24 ( N1 , DAG ) ) { N0 = DAG . getZExtOrTrunc ( N0 , DL , <STR_LIT> ) ; N1 = DAG . getZExtOrTrunc ( N1 , DL , <STR_LIT> ) ; Mul = getMul24 ( DAG , DL , N0 , N1 , Size , false ) ; } else if ( Subtarget -> hasMulI24 ( ) && isI24 ( N0 , DAG ) && isI24 ( N1 , DAG ) ) { N0 = DAG . getSExtOrTrunc ( N0 , DL , <STR_LIT> ) ; N1 = DAG . getSExtOrTrunc ( N1 , DL , <STR_LIT> ) ; Mul = getMul24 ( DAG , DL , N0 , N1 , Size , true ) ;


<s> if ( ! Subtarget -> hasMulI24 ( ) || VT . isVector ( ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( ! isI24 ( N0 , DAG ) || ! isI24 ( N1 , DAG ) ) return SDValue ( ) ; N0 = DAG . getSExtOrTrunc ( N0 , DL , <STR_LIT> ) ; N1 = DAG . getSExtOrTrunc ( N1 , DL , <STR_LIT> ) ; SDValue Mulhi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 , N1 ) ; DCI . AddToWorklist ( Mulhi . getNode ( ) ) ;

return DAG . getSExtOrTrunc ( Mulhi , DL , VT ) ;


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( ! isI24 ( N0 , DAG ) || ! isI24 ( N1 , DAG ) ) return SDValue ( ) ;

N0 = DAG . getSExtOrTrunc ( N0 , DL , <STR_LIT> ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! Subtarget -> hasMulU24 ( ) || VT . isVector ( ) || VT . getSizeInBits ( ) > <NUM_LIT> ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ;

if ( ! isU24 ( N0 , DAG ) || ! isU24 ( N1 , DAG ) ) return SDValue ( ) ;


<s> SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( ! isU24 ( N0 , DAG ) || ! isU24 ( N1 , DAG ) ) return SDValue ( ) ; N0 = DAG . getZExtOrTrunc ( N0 , DL , <STR_LIT> ) ; N1 = DAG . getZExtOrTrunc ( N1 , DL , <STR_LIT> ) ; SDValue Mulhi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 , N1 ) ; DCI . AddToWorklist ( Mulhi . getNode ( ) ) ;

return DAG . getZExtOrTrunc ( Mulhi , DL , VT ) ;


<s> SDValue <ISA_LIT>TargetLowering :: performMulLoHi24Combine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; if ( SDValue V = simplifyI24 ( N , DCI ) ) return V ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; bool Signed = ( N -> getOpcode ( ) == <STR_LIT> ) ; unsigned MulLoOpc = Signed ? <STR_LIT> : <STR_LIT> ; unsigned MulHiOpc = Signed ? <STR_LIT> : <STR_LIT> ; SDLoc SL ( N ) ; SDValue MulLo = DAG . getNode ( MulLoOpc , SL , <STR_LIT> , N0 , N1 ) ;

SDValue MulHi = DAG . getNode ( MulHiOpc , SL , <STR_LIT> , N0 , N1 ) ;


<s> SDValue CC = Cond . getOperand ( <NUM_LIT> ) ; SDValue True = N -> getOperand ( <NUM_LIT> ) ; SDValue False = N -> getOperand ( <NUM_LIT> ) ; if ( Cond . hasOneUse ( ) ) { SelectionDAG & DAG = DCI . DAG ; if ( DAG . isConstantValueOfAnyType ( True ) && ! DAG . isConstantValueOfAnyType ( False ) ) { SDLoc SL ( N ) ; <STR_LIT> NewCC = getSetCCInverse ( cast < CondCodeSDNode > ( CC ) -> get ( ) , LHS . getValueType ( ) . isInteger ( ) ) ; SDValue NewCond = DAG . getSetCC ( SL , Cond . getValueType ( ) , LHS , RHS , NewCC ) ; return DAG . getNode ( <STR_LIT> , SL , VT , NewCond , False , True ) ; }

if ( VT == <STR_LIT> && Subtarget -> hasFminFmaxLegacy ( ) ) {


<s> bool IsFast ; unsigned AS = SN -> getAddressSpace ( ) ; if ( ! allowsMisalignedMemoryAccesses ( VT , AS , Align , SN -> getMemOperand ( ) -> getFlags ( ) , & IsFast ) ) { if ( VT . isVector ( ) ) return scalarizeVectorStore ( SN , DAG ) ; return expandUnalignedStore ( SN , DAG ) ; } if ( ! IsFast ) return SDValue ( ) ; } if ( ! shouldCombineMemoryType ( VT ) ) return SDValue ( ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue Val = SN -> getValue ( ) ; bool OtherUses = ! Val . hasOneUse ( ) ;

SDValue CastVal = DAG . getNode ( <STR_LIT> , SL , NewVT , Val ) ;


<s> bool <ISA_LIT>TargetLowering :: SelectFlatOffset ( bool IsSigned , SelectionDAG & DAG , SDNode * N , SDValue Addr , SDValue & VAddr , SDValue & Offset , SDValue & SLC ) const { const GCNSubtarget & ST = DAG . getMachineFunction ( ) . getSubtarget < GCNSubtarget > ( ) ; int64_t OffsetVal = <NUM_LIT> ; if ( ST . hasFlatInstOffsets ( ) && ( ! ST . hasFlatSegmentOffsetBug ( ) || findMemSDNode ( N ) -> getAddressSpace ( ) != <ISA_LIT>AS :: FLAT_ADDRESS ) && DAG . isBaseWithConstantOffset ( Addr ) ) {

SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ;


<s> int64_t OffsetVal = <NUM_LIT> ; if ( ST . hasFlatInstOffsets ( ) && ( ! ST . hasFlatSegmentOffsetBug ( ) || findMemSDNode ( N ) -> getAddressSpace ( ) != <ISA_LIT>AS :: FLAT_ADDRESS ) && DAG . isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; int64_t COffsetVal = cast < ConstantSDNode > ( N1 ) -> getSExtValue ( ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; if ( TII -> isLegalFLATOffset ( COffsetVal , findMemSDNode ( N ) -> getAddressSpace ( ) , IsSigned ) ) { Addr = N0 ; OffsetVal = COffsetVal ; } }


<s> if ( ! TargetLoweringBase :: shouldReduceLoadWidth ( N , ExtTy , NewVT ) ) return false ; unsigned NewSize = NewVT . getStoreSizeInBits ( ) ; if ( NewSize == <NUM_LIT> ) return true ; EVT OldVT = N -> getValueType ( <NUM_LIT> ) ; unsigned OldSize = OldVT . getStoreSizeInBits ( ) ; MemSDNode * MN = cast < MemSDNode > ( N ) ;

unsigned AS = MN -> getAddressSpace ( ) ;


<s> bool <ISA_LIT>TargetLowering :: shouldReduceLoadWidth ( SDNode * N , <STR_LIT> ExtTy , EVT NewVT ) const { if ( ! TargetLoweringBase :: shouldReduceLoadWidth ( N , ExtTy , NewVT ) ) return false ; unsigned NewSize = NewVT . getStoreSizeInBits ( ) ; if ( NewSize == <NUM_LIT> ) return true ; EVT OldVT = N -> getValueType ( <NUM_LIT> ) ; unsigned OldSize = OldVT . getStoreSizeInBits ( ) ;

MemSDNode * MN = cast < MemSDNode > ( N ) ;


<s> bool IsIntrin = Node24 -> getOpcode ( ) == <STR_LIT> ; SDValue LHS = IsIntrin ? Node24 -> getOperand ( <NUM_LIT> ) : Node24 -> getOperand ( <NUM_LIT> ) ; SDValue RHS = IsIntrin ? Node24 -> getOperand ( <NUM_LIT> ) : Node24 -> getOperand ( <NUM_LIT> ) ; unsigned NewOpcode = Node24 -> getOpcode ( ) ; if ( IsIntrin ) { unsigned IID = cast < ConstantSDNode > ( Node24 -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; NewOpcode = IID == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } APInt Demanded = APInt :: getLowBitsSet ( LHS . getValueSizeInBits ( ) , <NUM_LIT> ) ; SDValue DemandedLHS = DAG . GetDemandedBits ( LHS , Demanded ) ; SDValue DemandedRHS = DAG . GetDemandedBits ( RHS , Demanded ) ;

if ( DemandedLHS || DemandedRHS ) return DAG . getNode ( NewOpcode , SDLoc ( Node24 ) , Node24 -> getVTList ( ) , DemandedLHS ? DemandedLHS : LHS , DemandedRHS ? DemandedRHS : RHS ) ;


<s> assert ( LoVT . getVectorNumElements ( ) + ( HiVT . isVector ( ) ? HiVT . getVectorNumElements ( ) : <NUM_LIT> ) <= N . getValueType ( ) . getVectorNumElements ( ) && <STR_LIT> ) ; auto IdxTy = getVectorIdxTy ( DAG . getDataLayout ( ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , LoVT , N , DAG . getConstant ( <NUM_LIT> , DL , IdxTy ) ) ; SDValue Hi = DAG . getNode ( HiVT . isVector ( ) ? <STR_LIT> : <STR_LIT> , DL , HiVT , N , DAG . getConstant ( LoVT . getVectorNumElements ( ) , DL , IdxTy ) ) ;


<s> const MachinePointerInfo & SrcValue = Load -> getMemOperand ( ) -> getPointerInfo ( ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = getSplitDestVTs ( VT , DAG ) ; std :: tie ( LoMemVT , HiMemVT ) = getSplitDestVTs ( MemVT , DAG ) ; std :: tie ( Lo , Hi ) = splitVector ( Op , SL , LoVT , HiVT , DAG ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned BaseAlign = Load -> getAlignment ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , LoVT , Load -> getChain ( ) , BasePtr , SrcValue , LoMemVT , BaseAlign , Load -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue HiPtr = DAG . getObjectPtrOffset ( SL , BasePtr , Size ) ; SDValue HiLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , HiVT , Load -> getChain ( ) , HiPtr , SrcValue . getWithOffset ( LoMemVT . getStoreSize ( ) ) , HiMemVT , HiAlign , Load -> getMemOperand ( ) -> getFlags ( ) ) ;

auto IdxTy = getVectorIdxTy ( DAG . getDataLayout ( ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: storeStackInputValue ( SelectionDAG & DAG , const SDLoc & SL , SDValue Chain , SDValue ArgVal , int64_t Offset ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachinePointerInfo DstInfo = MachinePointerInfo :: getStack ( MF , Offset ) ; SDValue Ptr = DAG . getConstant ( Offset , SL , <STR_LIT> ) ;

SDValue Store = DAG . getStore ( Chain , SL , ArgVal , Ptr , DstInfo , <NUM_LIT> , MachineMemOperand :: MODereferenceable ) ;


<s> SDValue Ptr = DAG . getConstant ( Offset , SL , <STR_LIT> ) ;


<s> const MachinePointerInfo & SrcValue = Load -> getMemOperand ( ) -> getPointerInfo ( ) ; unsigned BaseAlign = Load -> getAlignment ( ) ; EVT WideVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , <NUM_LIT> ) ;

EVT WideMemVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MemVT . getVectorElementType ( ) , <NUM_LIT> ) ;


<s> SDLoc SL ( Op ) ; const MachinePointerInfo & SrcValue = Load -> getMemOperand ( ) -> getPointerInfo ( ) ; unsigned BaseAlign = Load -> getAlignment ( ) ; EVT WideVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , <NUM_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: aggressivelyPreferBuildVectorSources ( EVT VecVT ) const {


<s> unsigned Offset = State . AllocateStack ( ValVT . getStoreSize ( ) , ArgFlags . getOrigAlign ( ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return true ;


<s> static bool allocateStack ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { unsigned Offset = State . AllocateStack ( ValVT . getStoreSize ( ) , ArgFlags . getOrigAlign ( ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ;


<s> void <ISA_LIT>TargetLowering :: AnalyzeFormalArguments ( CCState & State , const SmallVectorImpl < <STR_LIT> > & Ins ) const {

State . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ;


<s> void <ISA_LIT>TargetLowering :: AnalyzeFormalArguments ( CCState & State , const SmallVectorImpl < <STR_LIT> > & Ins ) const { State . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG && ! DCI . isCalledByLegalizer ( ) ) return SDValue ( ) ; if ( LHS == True ) return DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS ) ; return DAG . getNode ( <STR_LIT> , DL , VT , RHS , LHS ) ; } case <STR_LIT> : case <STR_LIT> : { if ( LHS == True ) return DAG . getNode ( <STR_LIT> , DL , VT , RHS , LHS ) ; return DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : {


<s> static void computeKnownBitsForMinMax ( const SDValue Op0 , const SDValue Op1 , APInt & KnownZero , APInt & KnownOne , const SelectionDAG & DAG , unsigned Depth ) { APInt Op0Zero , Op0One ; APInt Op1Zero , Op1One ; DAG . computeKnownBits ( Op0 , Op0Zero , Op0One , Depth ) ; DAG . computeKnownBits ( Op1 , Op1Zero , Op1One , Depth ) ;


<s> computeKnownBitsForMinMax ( Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , KnownZero , KnownOne , DAG , Depth ) ; break ; default : break ; } break ; } case <STR_LIT> : case <STR_LIT> : { KnownZero = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : { ConstantSDNode * CWidth = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! CWidth ) return ; unsigned BitWidth = <NUM_LIT> ; uint32_t Width = CWidth -> getZExtValue ( ) & <NUM_LIT> ;

if ( Opc == <STR_LIT> ) KnownZero = APInt :: getHighBitsSet ( BitWidth , BitWidth - Width ) ;


<s> KnownZero = KnownOne = APInt ( KnownOne . getBitWidth ( ) , <NUM_LIT> ) ; APInt KnownZero2 ; APInt KnownOne2 ; unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : { switch ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : computeKnownBitsForMinMax ( Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , KnownZero , KnownOne , DAG , Depth ) ; break ; default : break ; } break ; } case <STR_LIT> : case <STR_LIT> : { KnownZero = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ;


<s> case <STR_LIT> : { ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) return <NUM_LIT> ; unsigned SignBits = <NUM_LIT> - Width -> getZExtValue ( ) + <NUM_LIT> ; if ( ! isNullConstant ( Op . getOperand ( <NUM_LIT> ) ) ) return SignBits ; unsigned Op0SignBits = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; return std :: max ( SignBits , Op0SignBits ) ;


<s> if ( Width + Offset < <NUM_LIT> ) { uint32_t Shl = static_cast < uint32_t > ( Src0 ) << ( <NUM_LIT> - Offset - Width ) ; IntTy Result = static_cast < IntTy > ( Shl ) >> ( <NUM_LIT> - Width ) ; return DAG . getConstant ( Result , DL , <STR_LIT> ) ; } return DAG . getConstant ( Src0 >> Offset , DL , <STR_LIT> ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned VirtualRegister ; if ( ! MRI . isLiveIn ( Reg ) ) { VirtualRegister = MRI . createVirtualRegister ( RC ) ; MRI . addLiveIn ( Reg , VirtualRegister ) ; } else { VirtualRegister = MRI . getLiveInVirtReg ( Reg ) ; }

return DAG . getRegister ( VirtualRegister , VT ) ;


<s> const unsigned FractBits = <NUM_LIT> ; const unsigned ExpBits = <NUM_LIT> ; SDValue ExpPart = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi , DAG . getConstant ( FractBits - <NUM_LIT> , SL , <STR_LIT> ) , DAG . getConstant ( ExpBits , SL , <STR_LIT> ) ) ; SDValue Exp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , ExpPart , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ;


<s> SDValue ExpPart = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi , DAG . getConstant ( FractBits - <NUM_LIT> , SL , <STR_LIT> ) , DAG . getConstant ( ExpBits , SL , <STR_LIT> ) ) ; SDValue Exp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , ExpPart , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ;


<s> if ( StoreSize <= <NUM_LIT> ) return EVT :: getIntegerVT ( Ctx , <NUM_LIT> ) ;

return EVT :: getVectorVT ( Ctx , <STR_LIT> , StoreSize / <NUM_LIT> ) ;


<s> unsigned StoreSize = VT . getStoreSizeInBits ( ) ; if ( StoreSize <= <NUM_LIT> ) return EVT :: getIntegerVT ( Ctx , <NUM_LIT> ) ; return EVT :: getVectorVT ( Ctx , <STR_LIT> , StoreSize / <NUM_LIT> ) ;


<s> unsigned StoreSize = VT . getStoreSizeInBits ( ) ; if ( StoreSize <= <NUM_LIT> ) return EVT :: getIntegerVT ( Ctx , StoreSize ) ; assert ( StoreSize % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ;


<s> uint32_t <ISA_LIT>TargetLowering :: getImplicitParameterOffset ( const <ISA_LIT>MachineFunction * MFI , const ImplicitParameter Param ) const { uint64_t ArgOffset = MFI -> ABIArgOffset ; switch ( Param ) { case GRID_DIM : return ArgOffset ; case GRID_OFFSET :


<s> void <ISA_LIT>TargetLowering :: getOriginalFunctionArgs ( SelectionDAG & DAG , const Function * F , const SmallVectorImpl < <STR_LIT> > & Ins , SmallVectorImpl < <STR_LIT> > & OrigIns ) const { for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i < e ; ++ i ) { if ( Ins [ i ] . ArgVT == Ins [ i ] . VT ) { OrigIns . push_back ( Ins [ i ] ) ; continue ; } EVT VT ; if ( Ins [ i ] . ArgVT . isVector ( ) && ! Ins [ i ] . VT . isVector ( ) ) { VT = Ins [ i ] . ArgVT . getVectorElementType ( ) ;

} else if ( Ins [ i ] . VT . isVector ( ) && Ins [ i ] . ArgVT . isVector ( ) && Ins [ i ] . ArgVT . getVectorElementType ( ) != Ins [ i ] . VT . getVectorElementType ( ) ) {


<s> SDValue <ISA_LIT>TargetLowering :: getRecipEstimate ( SDValue Operand , DAGCombinerInfo & DCI , unsigned & RefinementSteps ) const { SelectionDAG & DAG = DCI . DAG ; EVT VT = Operand . getValueType ( ) ;


<s> if ( VT == <STR_LIT> ) { RefinementSteps = <NUM_LIT> ;

return DAG . getNode ( <STR_LIT> , SDLoc ( Operand ) , VT , Operand ) ;


<s> MVT <ISA_LIT>TargetLowering :: getVectorIdxTy ( const DataLayout & ) const { return <STR_LIT> ;


<s> const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ;

if ( ! GVar || ! GVar -> hasInitializer ( ) ) return false ;


<s> bool <ISA_LIT>TargetLowering :: isCheapToSpeculateCtlz ( ) const {


<s> bool <ISA_LIT>TargetLowering :: isCheapToSpeculateCttz ( ) const { return true ;


<s> bool <ISA_LIT>TargetLowering :: isFAbsFree ( EVT VT ) const { assert ( VT . isFloatingPoint ( ) ) ;

return VT == <STR_LIT> || VT == <STR_LIT> ;


<s> bool <ISA_LIT>TargetLowering :: isFNegFree ( EVT VT ) const { assert ( VT . isFloatingPoint ( ) ) ; return VT == <STR_LIT> || VT == <STR_LIT> ;


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { EVT ScalarVT = VT . getScalarType ( ) ;

return ( ScalarVT == <STR_LIT> || ScalarVT == <STR_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { EVT ScalarVT = VT . getScalarType ( ) ; return ( ScalarVT == <STR_LIT> || ScalarVT == <STR_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: isHWFalseValue ( SDValue Op ) const { if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Op ) ) { return CFP -> getValueAPF ( ) . isZero ( ) ; } return isNullConstant ( Op ) ;


<s> bool <ISA_LIT>TargetLowering :: isHWFalseValue ( SDValue Op ) const { if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Op ) ) { return CFP -> getValueAPF ( ) . isZero ( ) ;


<s> bool <ISA_LIT>TargetLowering :: isHWTrueValue ( SDValue Op ) const { if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Op ) ) {

return CFP -> isExactlyValue ( <NUM_LIT> ) ;


<s> return CFP -> isExactlyValue ( <NUM_LIT> ) ; }


<s> static bool isI24 ( SDValue Op , SelectionDAG & DAG ) { EVT VT = Op . getValueType ( ) ; return VT . getSizeInBits ( ) >= <NUM_LIT> && ( VT . getSizeInBits ( ) - DAG . ComputeNumSignBits ( Op ) ) < <NUM_LIT> ;


return VT . getSizeInBits ( ) >= <NUM_LIT> && ( VT . getSizeInBits ( ) - DAG . ComputeNumSignBits ( Op ) ) < <NUM_LIT> ;


<s> if ( LoadTy . getSizeInBits ( ) != CastTy . getSizeInBits ( ) ) return true ; unsigned LScalarSize = LoadTy . getScalarType ( ) . getSizeInBits ( ) ; unsigned CastScalarSize = CastTy . getScalarType ( ) . getSizeInBits ( ) ; return ( ( LScalarSize <= CastScalarSize ) || ( CastScalarSize >= <NUM_LIT> ) || ( LScalarSize < <NUM_LIT> ) ) ;


<s> return SrcVT . getSizeInBits ( ) > <NUM_LIT> && DestVT . getSizeInBits ( ) == <NUM_LIT> ;


<s> bool <ISA_LIT>TargetLowering :: isSelectSupported ( SelectSupportKind SelType ) const { return true ;


<s> return Dest -> getPrimitiveSizeInBits ( ) < Source -> getPrimitiveSizeInBits ( ) && ( Dest -> getPrimitiveSizeInBits ( ) % <NUM_LIT> == <NUM_LIT> ) ;


<s> DAG . computeKnownBits ( Op , KnownZero , KnownOne ) ; return ( VT . getSizeInBits ( ) - KnownZero . countLeadingOnes ( ) ) <= <NUM_LIT> ;


<s> bool <ISA_LIT>TargetLowering :: isZExtFree ( SDValue Val , EVT VT2 ) const { return isZExtFree ( Val . getValueType ( ) , VT2 ) ;


<s> else if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) FuncName = G -> getGlobal ( ) -> getName ( ) ; DiagnosticInfoUnsupported NoCalls ( Fn , <STR_LIT> + FuncName ) ; DAG . getContext ( ) -> diagnose ( NoCalls ) ;


<s> const Function & Fn = * DAG . getMachineFunction ( ) . getFunction ( ) ; StringRef FuncName ( <STR_LIT> ) ; if ( const ExternalSymbolSDNode * G = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) FuncName = G -> getSymbol ( ) ; else if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) FuncName = G -> getGlobal ( ) -> getName ( ) ;

DiagnosticInfoUnsupported NoCalls ( Fn , <STR_LIT> + FuncName ) ;


<s> for ( const SDUse & U : Op -> ops ( ) ) DAG . ExtractVectorElements ( U . get ( ) , Args ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Args ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerCONCAT_VECTORS ( SDValue Op , SelectionDAG & DAG ) const { SmallVector < SDValue , <NUM_LIT> > Args ;

for ( const SDUse & U : Op -> ops ( ) ) DAG . ExtractVectorElements ( U . get ( ) , Args ) ;


<s> } if ( SequentialType * SeqTy = dyn_cast < SequentialType > ( InitTy ) ) { EVT PtrVT = InitPtr . getValueType ( ) ; unsigned NumElements ; if ( ArrayType * AT = dyn_cast < ArrayType > ( SeqTy ) ) NumElements = AT -> getNumElements ( ) ; else if ( VectorType * VT = dyn_cast < VectorType > ( SeqTy ) ) NumElements = VT -> getNumElements ( ) ; else llvm_unreachable ( <STR_LIT> ) ; unsigned EltSize = TD . getTypeAllocSize ( SeqTy -> getElementType ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Chains ; for ( unsigned i = <NUM_LIT> ; i < NumElements ; ++ i ) { SDValue Offset = DAG . getConstant ( i * EltSize , DL , PtrVT ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , InitPtr , Offset ) ; Constant * Elt = Init -> getAggregateElement ( i ) ; Chains . push_back ( LowerConstantInitializer ( Elt , GV , Ptr , Chain , DAG ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chains ) ; } if ( isa < UndefValue > ( Init ) ) {


<s> if ( ArrayType * AT = dyn_cast < ArrayType > ( SeqTy ) ) NumElements = AT -> getNumElements ( ) ; else if ( VectorType * VT = dyn_cast < VectorType > ( SeqTy ) ) NumElements = VT -> getNumElements ( ) ; else llvm_unreachable ( <STR_LIT> ) ; unsigned EltSize = TD . getTypeAllocSize ( SeqTy -> getElementType ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Chains ; for ( unsigned i = <NUM_LIT> ; i < NumElements ; ++ i ) { SDValue Offset = DAG . getConstant ( i * EltSize , DL , PtrVT ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , InitPtr , Offset ) ; Constant * Elt = Init -> getAggregateElement ( i ) ; Chains . push_back ( LowerConstantInitializer ( Elt , GV , Ptr , Chain , DAG ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chains ) ; } if ( isa < UndefValue > ( Init ) ) { EVT VT = EVT :: getEVT ( InitTy ) ; PointerType * PtrTy = PointerType :: get ( InitTy , <ISA_LIT>AS :: PRIVATE_ADDRESS ) ; return DAG . getStore ( Chain , DL , DAG . getUNDEF ( VT ) , InitPtr , MachinePointerInfo ( UndefValue :: get ( PtrTy ) ) , false , false , TD . getPrefTypeAlignment ( InitTy ) ) ; } Init -> dump ( ) ; llvm_unreachable ( <STR_LIT> ) ;


<s> SDValue ib = sign ? DAG . getSExtOrTrunc ( RHS , DL , IntVT ) : DAG . getZExtOrTrunc ( RHS , DL , IntVT ) ; SDValue fa = DAG . getNode ( ToFp , DL , FltVT , ia ) ; SDValue fb = DAG . getNode ( ToFp , DL , FltVT , ib ) ; SDValue fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fa , DAG . getNode ( <STR_LIT> , DL , FltVT , fb ) ) ; fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ; SDValue fqneg = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ; SDValue fr = DAG . getNode ( <STR_LIT> , DL , FltVT , DAG . getNode ( <STR_LIT> , DL , FltVT , fqneg , fb ) , fa ) ; SDValue iq = DAG . getNode ( ToInt , DL , IntVT , fq ) ; fr = DAG . getNode ( <STR_LIT> , DL , FltVT , fr ) ; fb = DAG . getNode ( <STR_LIT> , DL , FltVT , fb ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue cv = DAG . getSetCC ( DL , SetCCVT , fr , fb , <STR_LIT> ) ;

jq = DAG . getNode ( <STR_LIT> , DL , VT , cv , jq , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ;


<s> if ( sign ) { jq = DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS ) ; jq = DAG . getNode ( <STR_LIT> , DL , VT , jq , DAG . getConstant ( BitSize - <NUM_LIT> , DL , VT ) ) ; jq = DAG . getNode ( <STR_LIT> , DL , VT , jq , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; jq = DAG . getSExtOrTrunc ( jq , DL , IntVT ) ; } SDValue ia = sign ? DAG . getSExtOrTrunc ( LHS , DL , IntVT ) : DAG . getZExtOrTrunc ( LHS , DL , IntVT ) ; SDValue ib = sign ? DAG . getSExtOrTrunc ( RHS , DL , IntVT ) : DAG . getZExtOrTrunc ( RHS , DL , IntVT ) ; SDValue fa = DAG . getNode ( ToFp , DL , FltVT , ia ) ; SDValue fb = DAG . getNode ( ToFp , DL , FltVT , ib ) ; SDValue fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fa , DAG . getNode ( <STR_LIT> , DL , FltVT , fb ) ) ; fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ; SDValue fqneg = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ; SDValue fr = DAG . getNode ( <STR_LIT> , DL , FltVT , DAG . getNode ( <STR_LIT> , DL , FltVT , fqneg , fb ) , fa ) ; SDValue iq = DAG . getNode ( ToInt , DL , IntVT , fq ) ; fr = DAG . getNode ( <STR_LIT> , DL , FltVT , fr ) ; fb = DAG . getNode ( <STR_LIT> , DL , FltVT , fb ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue cv = DAG . getSetCC ( DL , SetCCVT , fr , fb , <STR_LIT> ) ; jq = DAG . getNode ( <STR_LIT> , DL , VT , cv , jq , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ;

iq = sign ? DAG . getSExtOrTrunc ( iq , DL , VT ) : DAG . getZExtOrTrunc ( iq , DL , VT ) ;


<s> const Function & Fn = * DAG . getMachineFunction ( ) . getFunction ( ) ; DiagnosticInfoUnsupported NoDynamicAlloca ( Fn , <STR_LIT> ) ; DAG . getContext ( ) -> diagnose ( NoDynamicAlloca ) ; return SDValue ( ) ;


<s> SmallVector < SDValue , <NUM_LIT> > Args ; unsigned Start = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Op . getValueType ( ) ;

DAG . ExtractVectorElements ( Op . getOperand ( <NUM_LIT> ) , Args , Start , VT . getVectorNumElements ( ) ) ;


<s> SDValue Lt0 = DAG . getSetCC ( SL , SetCCVT , Src , Zero , <STR_LIT> ) ; SDValue NeTrunc = DAG . getSetCC ( SL , SetCCVT , Src , Trunc , <STR_LIT> ) ; SDValue And = DAG . getNode ( <STR_LIT> , SL , SetCCVT , Lt0 , NeTrunc ) ;

SDValue Add = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , And , One , Zero ) ;


<s> const SDValue One = DAG . getConstantFP ( <NUM_LIT> , SL , <STR_LIT> ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) ; SDValue Lt0 = DAG . getSetCC ( SL , SetCCVT , Src , Zero , <STR_LIT> ) ; SDValue NeTrunc = DAG . getSetCC ( SL , SetCCVT , Src , Trunc , <STR_LIT> ) ; SDValue And = DAG . getNode ( <STR_LIT> , SL , SetCCVT , Lt0 , NeTrunc ) ;


<s> const SDValue Zero = DAG . getConstantFP ( <NUM_LIT> , SL , <STR_LIT> ) ; const SDValue NegOne = DAG . getConstantFP ( - <NUM_LIT> , SL , <STR_LIT> ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) ; SDValue Lt0 = DAG . getSetCC ( SL , SetCCVT , Src , Zero , <STR_LIT> ) ; SDValue NeTrunc = DAG . getSetCC ( SL , SetCCVT , Src , Trunc , <STR_LIT> ) ; SDValue And = DAG . getNode ( <STR_LIT> , SL , SetCCVT , Lt0 , NeTrunc ) ;

SDValue Add = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , And , NegOne , Zero ) ;


<s> SDLoc SL ( Op ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; const SDValue Zero = DAG . getConstantFP ( <NUM_LIT> , SL , <STR_LIT> ) ; const SDValue NegOne = DAG . getConstantFP ( - <NUM_LIT> , SL , <STR_LIT> ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) ; SDValue Lt0 = DAG . getSetCC ( SL , SetCCVT , Src , Zero , <STR_LIT> ) ; SDValue NeTrunc = DAG . getSetCC ( SL , SetCCVT , Src , Trunc , <STR_LIT> ) ; SDValue And = DAG . getNode ( <STR_LIT> , SL , SetCCVT , Lt0 , NeTrunc ) ; SDValue Add = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , And , NegOne , Zero ) ;

return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Trunc , Add ) ;


<s> SDValue K1 = DAG . getConstantFP ( BitsToDouble ( UINT64_C ( <NUM_LIT> ) ) , SL , <STR_LIT> ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Trunc , K0 ) ; SDValue FloorMul = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Mul ) ; SDValue Fma = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , FloorMul , K1 , Trunc ) ; SDValue Hi = DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT> , SL , <STR_LIT> , FloorMul ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Fma ) ; SDValue Result = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo , Hi ) ;

return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Result ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP64_TO_INT ( SDValue Op , SelectionDAG & DAG , bool Signed ) const { SDLoc SL ( Op ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; SDValue K0 = DAG . getConstantFP ( BitsToDouble ( UINT64_C ( <NUM_LIT> ) ) , SL , <STR_LIT> ) ; SDValue K1 = DAG . getConstantFP ( BitsToDouble ( UINT64_C ( <NUM_LIT> ) ) , SL , <STR_LIT> ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Trunc , K0 ) ; SDValue FloorMul = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Mul ) ; SDValue Fma = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , FloorMul , K1 , Trunc ) ; SDValue Hi = DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT> , SL , <STR_LIT> , FloorMul ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Fma ) ; SDValue Result = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo , Hi ) ;


<s> if ( Op . getValueType ( ) == <STR_LIT> && Src . getValueType ( ) == <STR_LIT> ) return LowerFP64_TO_INT ( Op , DAG , true ) ; return SDValue ( ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP_TO_<ISA_LIT>NT ( SDValue Op , SelectionDAG & DAG ) const { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> && Src . getValueType ( ) == <STR_LIT> ) return LowerFP64_TO_INT ( Op , DAG , true ) ;


<s> if ( Op . getValueType ( ) == <STR_LIT> && Src . getValueType ( ) == <STR_LIT> ) return LowerFP64_TO_INT ( Op , DAG , false ) ; return SDValue ( ) ;


<s> unsigned IgnoredFrameReg ; unsigned Offset = TFL -> getFrameIndexReference ( MF , FrameIndex , IgnoredFrameReg ) ; return DAG . getConstant ( Offset * <NUM_LIT> * TFL -> getStackWidth ( MF ) , SDLoc ( Op ) , Op . getValueType ( ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFrameIndex ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>FrameLowering * TFL = Subtarget -> getFrameLowering ( ) ; FrameIndexSDNode * FIN = cast < FrameIndexSDNode > ( Op ) ; unsigned FrameIndex = FIN -> getIndex ( ) ; unsigned IgnoredFrameReg ; unsigned Offset = TFL -> getFrameIndexReference ( MF , FrameIndex , IgnoredFrameReg ) ;

return DAG . getConstant ( Offset * <NUM_LIT> * TFL -> getStackWidth ( MF ) , SDLoc ( Op ) , Op . getValueType ( ) ) ;


<s> SDValue Floor = DAG . getNode ( <STR_LIT> , SL , VT , Div ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , SL , VT , Floor , Y ) ;

return DAG . getNode ( <STR_LIT> , SL , VT , X , Mul ) ;


<s> SDValue X = Op . getOperand ( <NUM_LIT> ) ; SDValue Y = Op . getOperand ( <NUM_LIT> ) ; SDValue Div = DAG . getNode ( <STR_LIT> , SL , VT , X , Y ) ; SDValue Floor = DAG . getNode ( <STR_LIT> , SL , VT , Div ) ;

SDValue Mul = DAG . getNode ( <STR_LIT> , SL , VT , Floor , Y ) ;


<s> SDValue C1 = DAG . getConstantFP ( C1Val , SL , <STR_LIT> ) ; SDValue CopySign = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , C1 , Src ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src , CopySign ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Tmp1 , CopySign ) ; SDValue Fabs = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; APFloat C2Val ( APFloat :: IEEEdouble , <STR_LIT> ) ; SDValue C2 = DAG . getConstantFP ( C2Val , SL , <STR_LIT> ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) ; SDValue Cond = DAG . getSetCC ( SL , SetCCVT , Fabs , C2 , <STR_LIT> ) ; return DAG . getSelect ( SL , <STR_LIT> , Cond , Src , Tmp2 ) ;


<s> SDValue C1 = DAG . getConstantFP ( C1Val , SL , <STR_LIT> ) ; SDValue CopySign = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , C1 , Src ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src , CopySign ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Tmp1 , CopySign ) ; SDValue Fabs = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; APFloat C2Val ( APFloat :: IEEEdouble , <STR_LIT> ) ; SDValue C2 = DAG . getConstantFP ( C2Val , SL , <STR_LIT> ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) ;

SDValue Cond = DAG . getSetCC ( SL , SetCCVT , Fabs , C2 , <STR_LIT> ) ;


<s> if ( VT == <STR_LIT> ) return LowerFROUND32 ( Op , DAG ) ;

if ( VT == <STR_LIT> ) return LowerFROUND64 ( Op , DAG ) ;


<s> EVT VT = Op . getValueType ( ) ; if ( VT == <STR_LIT> ) return LowerFROUND32 ( Op , DAG ) ; if ( VT == <STR_LIT> ) return LowerFROUND64 ( Op , DAG ) ;


<s> const SDValue Half = DAG . getConstantFP ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue SignOne = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , One , X ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) ; SDValue Cmp = DAG . getSetCC ( SL , SetCCVT , AbsDiff , Half , <STR_LIT> ) ; SDValue Sel = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Cmp , SignOne , Zero ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , T , Sel ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFROUND64 ( SDValue Op , SelectionDAG & DAG ) const { SDLoc SL ( Op ) ; SDValue X = Op . getOperand ( <NUM_LIT> ) ; SDValue L = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , X ) ; const SDValue Zero = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; const SDValue One = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; const SDValue NegOne = DAG . getConstant ( - <NUM_LIT> , SL , <STR_LIT> ) ; const SDValue FiftyOne = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) ; SDValue BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , X ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BC , One ) ; SDValue Exp = extractF64Exponent ( Hi , SL , DAG ) ; const SDValue Mask = DAG . getConstant ( INT64_C ( <NUM_LIT> ) , SL , <STR_LIT> ) ; SDValue M = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Mask , Exp ) ; SDValue D = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DAG . getConstant ( INT64_C ( <NUM_LIT> ) , SL , <STR_LIT> ) , Exp ) ; SDValue Tmp0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , L , M ) ; SDValue Tmp1 = DAG . getSetCC ( SL , SetCCVT , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) , Tmp0 , <STR_LIT> ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Tmp1 , D , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue K = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , L , Tmp2 ) ; K = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , K , DAG . getNOT ( SL , M , <STR_LIT> ) ) ; K = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , K ) ; SDValue ExpLt0 = DAG . getSetCC ( SL , SetCCVT , Exp , Zero , <STR_LIT> ) ; SDValue ExpGt51 = DAG . getSetCC ( SL , SetCCVT , Exp , FiftyOne , <STR_LIT> ) ; SDValue ExpEqNegOne = DAG . getSetCC ( SL , SetCCVT , NegOne , Exp , <STR_LIT> ) ; SDValue Mag = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , ExpEqNegOne , DAG . getConstantFP ( <NUM_LIT> , SL , <STR_LIT> ) , DAG . getConstantFP ( <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue S = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Mag , X ) ; K = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , ExpLt0 , S , K ) ;

K = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , ExpGt51 , X , K ) ;


<s> SDValue K = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , L , Tmp2 ) ; K = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , K , DAG . getNOT ( SL , M , <STR_LIT> ) ) ; K = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , K ) ; SDValue ExpLt0 = DAG . getSetCC ( SL , SetCCVT , Exp , Zero , <STR_LIT> ) ; SDValue ExpGt51 = DAG . getSetCC ( SL , SetCCVT , Exp , FiftyOne , <STR_LIT> ) ; SDValue ExpEqNegOne = DAG . getSetCC ( SL , SetCCVT , NegOne , Exp , <STR_LIT> ) ; SDValue Mag = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , ExpEqNegOne , DAG . getConstantFP ( <NUM_LIT> , SL , <STR_LIT> ) , DAG . getConstantFP ( <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue S = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Mag , X ) ;

K = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , ExpLt0 , S , K ) ;


<s> SignBit64 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , SignBit64 ) ; SDValue BcInt = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; const SDValue FractMask = DAG . getConstant ( ( UINT64_C ( <NUM_LIT> ) << FractBits ) - <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Shr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , FractMask , Exp ) ; SDValue Not = DAG . getNOT ( SL , Shr , <STR_LIT> ) ; SDValue Tmp0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BcInt , Not ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) ; const SDValue FiftyOne = DAG . getConstant ( FractBits - <NUM_LIT> , SL , <STR_LIT> ) ; SDValue ExpLt0 = DAG . getSetCC ( SL , SetCCVT , Exp , Zero , <STR_LIT> ) ;

SDValue ExpGt51 = DAG . getSetCC ( SL , SetCCVT , Exp , FiftyOne , <STR_LIT> ) ;


<s> WorkList . push_back ( * I ) ; } SDValue Chain = LowerConstantInitializer ( Init , GV , InitPtr , DAG . getEntryNode ( ) , DAG ) ; for ( SmallVector < SDNode * , <NUM_LIT> > :: iterator I = WorkList . begin ( ) , E = WorkList . end ( ) ; I != E ; ++ I ) { SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; for ( unsigned i = <NUM_LIT> ; i < ( * I ) -> getNumOperands ( ) ; ++ i ) { Ops . push_back ( ( * I ) -> getOperand ( i ) ) ; } DAG . UpdateNodeOperands ( * I , Ops ) ; } return DAG . getZExtOrTrunc ( InitPtr , SDLoc ( Op ) , ConstPtrVT ) ; } } const Function & Fn = * DAG . getMachineFunction ( ) . getFunction ( ) ; DiagnosticInfoUnsupported BadInit ( Fn , <STR_LIT> ) ; DAG . getContext ( ) -> diagnose ( BadInit ) ; return SDValue ( ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerIntrinsicIABS ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; SDValue Neg = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Neg , Op . getOperand ( <NUM_LIT> ) ) ;