<s> } else if ( ! LHS -> isDivergent ( ) && COffsetVal > <NUM_LIT> ) { SDLoc SL ( N ) ; int64_t SplitImmOffset , RemainderOffset ; std :: tie ( SplitImmOffset , RemainderOffset ) = TII -> splitFlatOffset ( COffsetVal , <ISA_LIT>AS :: GLOBAL_ADDRESS , true ) ; if ( isUInt < <NUM_LIT> > ( RemainderOffset ) ) { SDNode * VMov = CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , CurDAG -> getTargetConstant ( RemainderOffset , SDLoc ( ) , <STR_LIT> ) ) ; VOffset = SDValue ( VMov , <NUM_LIT> ) ; SAddr = LHS ; Offset = CurDAG -> getTargetConstant ( SplitImmOffset , SDLoc ( ) , <STR_LIT> ) ; return true ; } } } if ( Addr . getOpcode ( ) != <STR_LIT> ) { if ( Addr -> isDivergent ( ) || Addr . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Addr ) ) return false ; SAddr = Addr ; SDNode * VMov = CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( Addr ) , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( ) , <STR_LIT> ) ) ; VOffset = SDValue ( VMov , <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( ImmOffset , SDLoc ( ) , <STR_LIT> ) ; return true ; } LHS = Addr . getOperand ( <NUM_LIT> ) ; RHS = Addr . getOperand ( <NUM_LIT> ) ; if ( ! LHS -> isDivergent ( ) ) { if ( SDValue ZextRHS = matchZExtFromI32 ( RHS ) ) { SAddr = LHS ; VOffset = ZextRHS ; } } if ( ! SAddr && ! RHS -> isDivergent ( ) ) { if ( SDValue ZextLHS = matchZExtFromI32 ( LHS ) ) {


<s> if ( TII -> isLegalFLATOffset ( COffsetVal , <ISA_LIT>AS :: GLOBAL_ADDRESS , true ) ) { Addr = LHS ; ImmOffset = COffsetVal ; } else if ( ! LHS -> isDivergent ( ) && COffsetVal > <NUM_LIT> ) { SDLoc SL ( N ) ; int64_t SplitImmOffset , RemainderOffset ; std :: tie ( SplitImmOffset , RemainderOffset ) = TII -> splitFlatOffset ( COffsetVal , <ISA_LIT>AS :: GLOBAL_ADDRESS , true ) ; if ( isUInt < <NUM_LIT> > ( RemainderOffset ) ) { SDNode * VMov = CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , CurDAG -> getTargetConstant ( RemainderOffset , SDLoc ( ) , <STR_LIT> ) ) ; VOffset = SDValue ( VMov , <NUM_LIT> ) ; SAddr = LHS ; Offset = CurDAG -> getTargetConstant ( SplitImmOffset , SDLoc ( ) , <STR_LIT> ) ;


<s> SAddr = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( SAddr ) , <STR_LIT> , TFI , SAddr . getOperand ( <NUM_LIT> ) ) , <NUM_LIT> ) ; } const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; if ( ! TII -> isLegalFLATOffset ( COffsetVal , <ISA_LIT>AS :: PRIVATE_ADDRESS , true ) ) { int64_t RemainderOffset = COffsetVal ; int64_t ImmField = <NUM_LIT> ; const unsigned NumBits = <STR_LIT> ( * Subtarget , true ) ; int64_t D = <NUM_LIT> << ( NumBits - <NUM_LIT> ) ; RemainderOffset = ( COffsetVal / D ) * D ; ImmField = COffsetVal - RemainderOffset ; assert ( TII -> isLegalFLATOffset ( ImmField , <ISA_LIT>AS :: PRIVATE_ADDRESS , true ) ) ; assert ( RemainderOffset + ImmField == COffsetVal ) ; COffsetVal = ImmField ; SDLoc DL ( N ) ; SDValue AddOffset = getMaterializedScalarImm32 ( Lo_32 ( RemainderOffset ) , DL ) ; SAddr = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , SAddr , AddOffset ) , <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( COffsetVal , SDLoc ( ) , <STR_LIT> ) ; return true ;


<s> uint64_t Rsrc = TII -> getDefaultRsrcDataFormat ( ) | APInt :: getAllOnesValue ( <NUM_LIT> ) . getZExtValue ( ) ; SDLoc DL ( Addr ) ; const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; SRsrc = SDValue ( Lowering . buildRSRC ( * CurDAG , DL , Ptr , <NUM_LIT> , Rsrc ) , <NUM_LIT> ) ;


<s> if ( In . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * Idx = dyn_cast < ConstantSDNode > ( In . getOperand ( <NUM_LIT> ) ) ) { if ( Idx -> isNullValue ( ) && In . getValueSizeInBits ( ) <= <NUM_LIT> ) return In . getOperand ( <NUM_LIT> ) ; }


<s> if ( In . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * Idx = dyn_cast < ConstantSDNode > ( In . getOperand ( <NUM_LIT> ) ) ) { if ( Idx -> isNullValue ( ) && In . getValueSizeInBits ( ) <= <NUM_LIT> ) return In . getOperand ( <NUM_LIT> ) ; } } if ( In . getOpcode ( ) == <STR_LIT> ) { SDValue Src = In . getOperand ( <NUM_LIT> ) ; if ( Src . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> ) return stripBitcast ( Src ) ;


<s> bool Sel2 = SelectVOP3PMadMixModsImpl ( Src2 , Src2 , Src2Mods ) ; assert ( ( IsFMA || ! Mode . FP32Denormals ) && <STR_LIT> ) ; if ( Sel0 || Sel1 || Sel2 ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { CurDAG -> getTargetConstant ( Src0Mods , SDLoc ( ) , <STR_LIT> ) , Src0 , CurDAG -> getTargetConstant ( Src1Mods , SDLoc ( ) , <STR_LIT> ) , Src1 , CurDAG -> getTargetConstant ( Src2Mods , SDLoc ( ) , <STR_LIT> ) , Src2 , CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( ) , <STR_LIT> ) , Zero , Zero } ; CurDAG -> SelectNodeTo ( N , IsFMA ? <STR_LIT> : <STR_LIT> , <STR_LIT> , Ops ) ;


<s> Base = N0 ; Offset0 = CurDAG -> getTargetConstant ( DWordOffset0 , DL , <STR_LIT> ) ; Offset1 = CurDAG -> getTargetConstant ( DWordOffset1 , DL , <STR_LIT> ) ; return true ; } } else if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { unsigned DWordOffset0 = C -> getZExtValue ( ) / <NUM_LIT> ; unsigned DWordOffset1 = DWordOffset0 + <NUM_LIT> ; if ( isUInt < <NUM_LIT> > ( DWordOffset0 ) ) { SDLoc DL ( Addr ) ; SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Sub = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , Zero , Addr . getOperand ( <NUM_LIT> ) ) ; if ( isDSOffsetLegal ( Sub , DWordOffset1 , <NUM_LIT> ) ) { SmallVector < SDValue , <NUM_LIT> > Opnds ; Opnds . push_back ( Zero ) ; Opnds . push_back ( Addr . getOperand ( <NUM_LIT> ) ) ; unsigned SubOp = <STR_LIT> ; if ( Subtarget -> hasAddNoCarry ( ) ) { SubOp = <STR_LIT> ; Opnds . push_back ( CurDAG -> getTargetConstant ( <NUM_LIT> , { } , <STR_LIT> ) ) ; } MachineSDNode * MachineSub = CurDAG -> getMachineNode ( SubOp , DL , <STR_LIT> , Opnds ) ; Base = SDValue ( MachineSub , <NUM_LIT> ) ; Offset0 = CurDAG -> getTargetConstant ( DWordOffset0 , DL , <STR_LIT> ) ; Offset1 = CurDAG -> getTargetConstant ( DWordOffset1 , DL , <STR_LIT> ) ; return true ; }


<s> bool <ISA_LIT>DAGToDAGISel :: SelectFlatOffset ( SDNode * N , SDValue Addr , SDValue & VAddr , SDValue & Offset , SDValue & SLC ) const { int64_t OffsetVal = <NUM_LIT> ; if ( Subtarget -> hasFlatInstOffsets ( ) && ( ! Subtarget -> hasFlatSegmentOffsetBug ( ) || findMemSDNode ( N ) -> getAddressSpace ( ) != <ISA_LIT>AS :: FLAT_ADDRESS ) && CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; int64_t COffsetVal = cast < ConstantSDNode > ( N1 ) -> getSExtValue ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; if ( TII -> isLegalFLATOffset ( COffsetVal , findMemSDNode ( N ) -> getAddressSpace ( ) , IsSigned ) ) { Addr = N0 ; OffsetVal = COffsetVal ; } } VAddr = Addr ; Offset = CurDAG -> getTargetConstant ( OffsetVal , SDLoc ( ) , <STR_LIT> ) ; SLC = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( ) , <STR_LIT> ) ; return true ;


<s> if ( Subtarget -> hasFlatInstOffsets ( ) && ( ! Subtarget -> hasFlatSegmentOffsetBug ( ) || findMemSDNode ( N ) -> getAddressSpace ( ) != <ISA_LIT>AS :: FLAT_ADDRESS ) && CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; int64_t COffsetVal = cast < ConstantSDNode > ( N1 ) -> getSExtValue ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; if ( TII -> isLegalFLATOffset ( COffsetVal , findMemSDNode ( N ) -> getAddressSpace ( ) , IsSigned ) ) { Addr = N0 ; OffsetVal = COffsetVal ; } }


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ;


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> :


<s> bool <ISA_LIT>DAGToDAGISel :: SelectDS128Bit8ByteAligned ( SDValue Addr , SDValue & Base , SDValue & Offset0 , SDValue & Offset1 ) const {

return SelectDSReadWrite2 ( Addr , Base , Offset0 , Offset1 , true ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectDS64Bit4ByteAligned ( SDValue Addr , SDValue & Base , SDValue & Offset0 , SDValue & Offset1 ) const { return SelectDSReadWrite2 ( Addr , Base , Offset0 , Offset1 , false ) ;


<s> if ( TII -> isLegalFLATOffset ( COffsetVal , <ISA_LIT>AS :: GLOBAL_ADDRESS , true ) ) { Addr = LHS ; ImmOffset = COffsetVal ; } } if ( Addr . getOpcode ( ) != <STR_LIT> ) return false ; SDValue LHS = Addr . getOperand ( <NUM_LIT> ) ; SDValue RHS = Addr . getOperand ( <NUM_LIT> ) ; if ( ! LHS -> isDivergent ( ) ) { if ( SDValue ZextRHS = matchZExtFromI32 ( RHS ) ) { SAddr = LHS ; VOffset = ZextRHS ;


<s> ImmOffset = COffsetVal ; } } if ( Addr . getOpcode ( ) != <STR_LIT> ) return false ; SDValue LHS = Addr . getOperand ( <NUM_LIT> ) ; SDValue RHS = Addr . getOperand ( <NUM_LIT> ) ; if ( ! LHS -> isDivergent ( ) ) { if ( SDValue ZextRHS = matchZExtFromI32 ( RHS ) ) { SAddr = LHS ; VOffset = ZextRHS ; } } if ( ! SAddr && ! RHS -> isDivergent ( ) ) { if ( SDValue ZextLHS = matchZExtFromI32 ( LHS ) ) { SAddr = RHS ; VOffset = ZextLHS ; } } if ( ! SAddr ) return false ; Offset = CurDAG -> getTargetConstant ( ImmOffset , SDLoc ( ) , <STR_LIT> ) ; return true ;


<s> case <STR_LIT> : case <STR_LIT> : { SelectUADDO_USUBO ( N ) ; return ; } case <STR_LIT> : { SelectFMUL_W_CHAIN ( N ) ; return ; } case <STR_LIT> : { SelectFMA_W_CHAIN ( N ) ; return ; } case <STR_LIT> : case <STR_LIT> : { EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned NumVectorElts = VT . getVectorNumElements ( ) ; if ( VT . getScalarSizeInBits ( ) == <NUM_LIT> ) { if ( Opc == <STR_LIT> && NumVectorElts == <NUM_LIT> ) { uint32_t LHSVal , RHSVal ; if ( getConstantValue ( N -> getOperand ( <NUM_LIT> ) , LHSVal ) && getConstantValue ( N -> getOperand ( <NUM_LIT> ) , RHSVal ) ) { uint32_t K = LHSVal | ( RHSVal << <NUM_LIT> ) ; CurDAG -> SelectNodeTo ( N , <STR_LIT> , VT , CurDAG -> getTargetConstant ( K , SDLoc ( N ) , <STR_LIT> ) ) ; return ; } } break ; } assert ( VT . getVectorElementType ( ) . bitsEq ( <STR_LIT> ) ) ; unsigned RegClassID = selectSGPRVectorRegClassID ( NumVectorElts ) ; SelectBuildVector ( N , RegClassID ) ; return ; } case <STR_LIT> : { SDValue RC , SubReg0 , SubReg1 ; SDLoc DL ( N ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } const SDValue Ops [ ] = { RC , N -> getOperand ( <NUM_LIT> ) , SubReg0 , N -> getOperand ( <NUM_LIT> ) , SubReg1 } ; ReplaceNode ( N , CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : {

if ( N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) != <NUM_LIT> || isInlineImmediate ( N ) ) break ;


<s> void <ISA_LIT>DAGToDAGISel :: SelectBRCOND ( SDNode * N ) { SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; if ( Cond . isUndef ( ) ) { CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; return ; } bool UseSCCBr = isCBranchSCC ( N ) && isUniformBr ( N ) ; unsigned BrOp = UseSCCBr ? <STR_LIT> : <STR_LIT> ; unsigned CondReg = UseSCCBr ? <STR_LIT> : <STR_LIT> ; SDLoc SL ( N ) ;

SDValue VCC = CurDAG -> getCopyToReg ( N -> getOperand ( <NUM_LIT> ) , SL , CondReg , Cond ) ;


<s> unsigned Imm = CAddr -> getZExtValue ( ) ; SDValue HighBits = CurDAG -> getTargetConstant ( Imm & ~ <NUM_LIT> , DL , <STR_LIT> ) ; MachineSDNode * MovHighBits = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , HighBits ) ; VAddr = SDValue ( MovHighBits , <NUM_LIT> ) ; const MachinePointerInfo & PtrInfo = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) ; unsigned SOffsetReg = isStackPtrRelative ( PtrInfo ) ? Info -> getStackPtrOffsetReg ( ) : Info -> getScratchWaveOffsetReg ( ) ; SOffset = CurDAG -> getRegister ( SOffsetReg , <STR_LIT> ) ; ImmOffset = CurDAG -> getTargetConstant ( Imm & <NUM_LIT> , DL , <STR_LIT> ) ; return true ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ;

if ( <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( C1 -> getZExtValue ( ) ) && CurDAG -> SignBitIsZero ( N0 ) ) {


<s> return SelectFlatOffset ( Addr , VAddr , Offset , SLC ) ;


<s> SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; uint64_t COffsetVal = cast < ConstantSDNode > ( N1 ) -> getZExtValue ( ) ; if ( isUInt < <NUM_LIT> > ( COffsetVal ) ) { Addr = N0 ; OffsetVal = COffsetVal ; } } VAddr = Addr ;

Offset = CurDAG -> getTargetConstant ( OffsetVal , SDLoc ( ) , <STR_LIT> ) ;


<s> uint64_t COffsetVal = cast < ConstantSDNode > ( N1 ) -> getZExtValue ( ) ; if ( isUInt < <NUM_LIT> > ( COffsetVal ) ) { Addr = N0 ; OffsetVal = COffsetVal ; } } VAddr = Addr ;


<s> SOffset = CurDAG -> getRegister ( SOffsetReg , <STR_LIT> ) ; ImmOffset = CurDAG -> getTargetConstant ( Imm & <NUM_LIT> , DL , <STR_LIT> ) ; return true ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( isLegalMUBUFImmOffset ( C1 ) ) { std :: tie ( VAddr , SOffset ) = foldFrameIndex ( N0 ) ; ImmOffset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectMUBUFScratchOffset ( SDNode * Root , SDValue Addr , SDValue & SRsrc , SDValue & SOffset , SDValue & Offset ) const { ConstantSDNode * CAddr = dyn_cast < ConstantSDNode > ( Addr ) ; if ( ! CAddr || ! isLegalMUBUFImmOffset ( CAddr ) ) return false ; SDLoc DL ( Addr ) ;

MachineFunction & MF = CurDAG -> getMachineFunction ( ) ;


<s> if ( ! N -> readMem ( ) ) return false ; const Value * MemVal = N -> getMemOperand ( ) -> getValue ( ) ;

if ( CbId == - <NUM_LIT> ) return checkType ( MemVal , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: isConstantLoad ( const MemSDNode * N , int CbId ) const { if ( ! N -> readMem ( ) ) return false ; const Value * MemVal = N -> getMemOperand ( ) -> getValue ( ) ; if ( CbId == - <NUM_LIT> ) return checkType ( MemVal , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ;

return checkType ( MemVal , <ISA_LIT>AS :: CONSTANT_BUFFER_0 + CbId ) ;


<s> return checkType ( N -> getMemOperand ( ) -> getValue ( ) , <ISA_LIT>AS :: FLAT_ADDRESS ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: isFlatStore ( const MemSDNode * N ) {

if ( ! N -> writeMem ( ) ) return false ;


<s> if ( N -> getAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS ) {

if ( Subtarget -> getGeneration ( ) < <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) return ! isa < GlobalValue > ( GetUnderlyingObject ( N -> getMemOperand ( ) -> getValue ( ) , CurDAG -> getDataLayout ( ) ) ) ;


<s> if ( ! N -> writeMem ( ) ) return false ; return checkType ( N -> getMemOperand ( ) -> getValue ( ) , <ISA_LIT>AS :: GLOBAL_ADDRESS ) ;


<s> if ( ! N -> writeMem ( ) ) return false ;

return checkType ( N -> getMemOperand ( ) -> getValue ( ) , <ISA_LIT>AS :: GLOBAL_ADDRESS ) ;


<s> int64_t ByteOffset = C -> getSExtValue ( ) ; if ( isUInt < <NUM_LIT> > ( ByteOffset ) ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Sub = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , Zero , Addr . getOperand ( <NUM_LIT> ) ) ; if ( isDSOffsetLegal ( Sub , ByteOffset , <NUM_LIT> ) ) { MachineSDNode * MachineSub = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Zero , Addr . getOperand ( <NUM_LIT> ) ) ; Base = SDValue ( MachineSub , <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) ; return true ; } } }

} else if ( const ConstantSDNode * CAddr = dyn_cast < ConstantSDNode > ( Addr ) ) {


<s> if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( isDSOffsetLegal ( N0 , C1 -> getSExtValue ( ) , <NUM_LIT> ) ) { Base = N0 ; Offset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ; return true ; } } else if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { int64_t ByteOffset = C -> getSExtValue ( ) ; if ( isUInt < <NUM_LIT> > ( ByteOffset ) ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Sub = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , Zero , Addr . getOperand ( <NUM_LIT> ) ) ; if ( isDSOffsetLegal ( Sub , ByteOffset , <NUM_LIT> ) ) { MachineSDNode * MachineSub = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Zero , Addr . getOperand ( <NUM_LIT> ) ) ; Base = SDValue ( MachineSub , <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) ; return true ; } } } } else if ( const ConstantSDNode * CAddr = dyn_cast < ConstantSDNode > ( Addr ) ) { SDLoc DL ( Addr ) ; if ( isUInt < <NUM_LIT> > ( CAddr -> getZExtValue ( ) ) ) {


<s> Idxen = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Offen = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( N0 . getOpcode ( ) == <STR_LIT> ) { SDValue N2 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N3 = N0 . getOperand ( <NUM_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = N2 ; VAddr = N3 ; } else { VAddr = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = N0 ; } if ( isLegalMUBUFImmOffset ( C1 ) ) { Offset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ; return true ; } else if ( isUInt < <NUM_LIT> > ( C1 -> getZExtValue ( ) ) ) { Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SOffset = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; return true ; } } if ( Addr . getOpcode ( ) == <STR_LIT> ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = N0 ; VAddr = N1 ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; return true ; } VAddr = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = Addr ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectMUBUF ( SDValue Addr , SDValue & Ptr , SDValue & VAddr , SDValue & SOffset , SDValue & Offset , SDValue & Offen , SDValue & Idxen , SDValue & Addr64 , SDValue & GLC , SDValue & SLC , SDValue & TFE ) const { if ( Subtarget -> useFlatForGlobal ( ) ) return false ; SDLoc DL ( Addr ) ; if ( ! GLC . getNode ( ) ) GLC = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; if ( ! SLC . getNode ( ) ) SLC = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; TFE = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Idxen = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Offen = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( N0 . getOpcode ( ) == <STR_LIT> ) {

SDValue N2 = N0 . getOperand ( <NUM_LIT> ) ;


<s> if ( Imm >= <NUM_LIT> ) { if ( Imm <= <NUM_LIT> + <NUM_LIT> ) { Overflow = Imm - <NUM_LIT> ; Imm = <NUM_LIT> ; } else { uint32_t High = ( Imm + <NUM_LIT> ) & ~ <NUM_LIT> ; uint32_t Low = ( Imm + <NUM_LIT> ) & <NUM_LIT> ; Imm = Low ; Overflow = High - <NUM_LIT> ; } }

ImmOffset = CurDAG -> getTargetConstant ( Imm , DL , <STR_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectMUBUFIntrinsicOffset ( SDValue Offset , SDValue & SOffset , SDValue & ImmOffset ) const {


<s> SDLoc DL ( Offset ) ; if ( ! isa < ConstantSDNode > ( Offset ) ) return false ; SelectMUBUFConstant ( Offset , SOffset , ImmOffset ) ; return true ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectMUBUFIntrinsicVOffset ( SDValue Offset , SDValue & SOffset , SDValue & ImmOffset , SDValue & VOffset ) const { SDLoc DL ( Offset ) ; if ( isa < ConstantSDNode > ( Offset ) ) return false ; if ( CurDAG -> isBaseWithConstantOffset ( Offset ) ) {

SDValue N0 = Offset . getOperand ( <NUM_LIT> ) ;


<s> } else { SOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ImmOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; VOffset = Offset ; } return true ;


<s> if ( checkPrivateAddress ( N -> getMemOperand ( ) ) ) { if ( MMO ) { const PseudoSourceValue * PSV = MMO -> getPseudoValue ( ) ; if ( PSV && PSV == PseudoSourceValue :: getConstantPool ( ) ) { return true ; } }


<s> } } SDLoc DL ( Addr ) ; if ( const ConstantSDNode * CAddr = dyn_cast < ConstantSDNode > ( Addr ) ) { if ( isUInt < <NUM_LIT> > ( CAddr -> getZExtValue ( ) ) ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; MachineSDNode * MovZero = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Zero ) ; Base = SDValue ( MovZero , <NUM_LIT> ) ; Offset = Addr ; return true ; } } Base = Addr ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ;


<s> SDLoc DL ( Addr ) ; if ( const ConstantSDNode * CAddr = dyn_cast < ConstantSDNode > ( Addr ) ) { if ( isUInt < <NUM_LIT> > ( CAddr -> getZExtValue ( ) ) ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ;

MachineSDNode * MovZero = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Zero ) ;


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( N -> getOperand ( i ) ) ;


<s> SDValue Glue = M0 . getValue ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ;

for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( N -> getOperand ( i ) ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( VT == <STR_LIT> || VT == <STR_LIT> ) ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue CarryIn = N -> getOperand ( <NUM_LIT> ) ; SDValue VCC = CurDAG -> getCopyToReg ( CurDAG -> getEntryNode ( ) , SL , <STR_LIT> , CarryIn , SDValue ( ) ) ; SDValue Ops [ <NUM_LIT> ] ;

SelectVOP3Mods0 ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ;


<s> assert ( VT == <STR_LIT> || VT == <STR_LIT> ) ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue CarryIn = N -> getOperand ( <NUM_LIT> ) ; SDValue VCC = CurDAG -> getCopyToReg ( CurDAG -> getEntryNode ( ) , SL , <STR_LIT> , CarryIn , SDValue ( ) ) ; SDValue Ops [ <NUM_LIT> ] ;


<s> return ; } unsigned Opc = IntrID == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Ptr = N -> getOperand ( <NUM_LIT> ) ; MemIntrinsicSDNode * M = cast < MemIntrinsicSDNode > ( N ) ; bool IsGDS = M -> getAddressSpace ( ) == <ISA_LIT>AS :: REGION_ADDRESS ; SDValue Offset ; if ( CurDAG -> isBaseWithConstantOffset ( Ptr ) ) { SDValue PtrBase = Ptr . getOperand ( <NUM_LIT> ) ; SDValue PtrOffset = Ptr . getOperand ( <NUM_LIT> ) ; const APInt & OffsetVal = cast < ConstantSDNode > ( PtrOffset ) -> getAPIntValue ( ) ; if ( isDSOffsetLegal ( PtrBase , OffsetVal . getZExtValue ( ) , <NUM_LIT> ) ) { N = glueCopyToM0 ( N , PtrBase ) ; Offset = CurDAG -> getTargetConstant ( OffsetVal , SDLoc ( ) , <STR_LIT> ) ; } } if ( ! Offset ) { N = glueCopyToM0 ( N , Ptr ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( ) , <STR_LIT> ) ;


<s> bool IsGDS = M -> getAddressSpace ( ) == <ISA_LIT>AS :: REGION_ADDRESS ; SDValue Offset ; if ( CurDAG -> isBaseWithConstantOffset ( Ptr ) ) { SDValue PtrBase = Ptr . getOperand ( <NUM_LIT> ) ; SDValue PtrOffset = Ptr . getOperand ( <NUM_LIT> ) ; const APInt & OffsetVal = cast < ConstantSDNode > ( PtrOffset ) -> getAPIntValue ( ) ; if ( isDSOffsetLegal ( PtrBase , OffsetVal . getZExtValue ( ) , <NUM_LIT> ) ) { N = glueCopyToM0 ( N , PtrBase ) ; Offset = CurDAG -> getTargetConstant ( OffsetVal , SDLoc ( ) , <STR_LIT> ) ; } }


<s> auto FI = cast < FrameIndexSDNode > ( SAddr . getOperand ( <NUM_LIT> ) ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI -> getIndex ( ) , FI -> getValueType ( <NUM_LIT> ) ) ; SAddr = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( SAddr ) , <STR_LIT> , TFI , SAddr . getOperand ( <NUM_LIT> ) ) , <NUM_LIT> ) ; } return SAddr ;


<s> SAddr = CurDAG -> getTargetFrameIndex ( FI -> getIndex ( ) , FI -> getValueType ( <NUM_LIT> ) ) ; } else if ( SAddr . getOpcode ( ) == <STR_LIT> && isa < FrameIndexSDNode > ( SAddr . getOperand ( <NUM_LIT> ) ) ) { auto FI = cast < FrameIndexSDNode > ( SAddr . getOperand ( <NUM_LIT> ) ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI -> getIndex ( ) , FI -> getValueType ( <NUM_LIT> ) ) ; SAddr = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( SAddr ) , <STR_LIT> , TFI , SAddr . getOperand ( <NUM_LIT> ) ) , <NUM_LIT> ) ;


<s> SAddr = SelectSAddrFI ( CurDAG , SAddr ) ; const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; if ( ! TII -> isLegalFLATOffset ( COffsetVal , <ISA_LIT>AS :: PRIVATE_ADDRESS , <STR_LIT> ) ) { int64_t SplitImmOffset , RemainderOffset ; std :: tie ( SplitImmOffset , RemainderOffset ) = TII -> splitFlatOffset ( COffsetVal , <ISA_LIT>AS :: PRIVATE_ADDRESS , <STR_LIT> ) ;


<s> if ( ! TII -> isLegalFLATOffset ( COffsetVal , <ISA_LIT>AS :: PRIVATE_ADDRESS , <STR_LIT> ) ) { int64_t SplitImmOffset , RemainderOffset ; std :: tie ( SplitImmOffset , RemainderOffset ) = TII -> splitFlatOffset ( COffsetVal , <ISA_LIT>AS :: PRIVATE_ADDRESS , <STR_LIT> ) ; COffsetVal = SplitImmOffset ; SDLoc DL ( N ) ; SDValue AddOffset = getMaterializedScalarImm32 ( Lo_32 ( RemainderOffset ) , DL ) ; SAddr = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , SAddr , AddOffset ) , <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( COffsetVal , SDLoc ( ) , <STR_LIT> ) ; return true ;


<s> SelectVOP3BMods0 ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; SelectVOP3BMods ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ;


<s> assert ( VT == <STR_LIT> || VT == <STR_LIT> ) ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ <NUM_LIT> ] ;

SelectVOP3BMods0 ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ;


<s> SAddr = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( SAddr ) , <STR_LIT> , TFI , SAddr . getOperand ( <NUM_LIT> ) ) , <NUM_LIT> ) ; } const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; if ( ! TII -> isLegalFLATOffset ( COffsetVal , <ISA_LIT>AS :: PRIVATE_ADDRESS , true ) ) { int64_t RemainderOffset = COffsetVal ; int64_t ImmField = <NUM_LIT> ; const unsigned NumBits = TII -> getNumFlatOffsetBits ( true ) ; int64_t D = <NUM_LIT> << ( NumBits - <NUM_LIT> ) ; RemainderOffset = ( COffsetVal / D ) * D ; ImmField = COffsetVal - RemainderOffset ; assert ( TII -> isLegalFLATOffset ( ImmField , <ISA_LIT>AS :: PRIVATE_ADDRESS , true ) ) ; assert ( RemainderOffset + ImmField == COffsetVal ) ; COffsetVal = ImmField ; SDLoc DL ( N ) ; SDValue AddOffset = getMaterializedScalarImm32 ( Lo_32 ( RemainderOffset ) , DL ) ;

SAddr = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , SAddr , AddOffset ) , <NUM_LIT> ) ;


<s> COffsetVal = cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; SAddr = Addr . getOperand ( <NUM_LIT> ) ; } if ( auto FI = dyn_cast < FrameIndexSDNode > ( SAddr ) ) { SAddr = CurDAG -> getTargetFrameIndex ( FI -> getIndex ( ) , FI -> getValueType ( <NUM_LIT> ) ) ; } else if ( SAddr . getOpcode ( ) == <STR_LIT> && isa < FrameIndexSDNode > ( SAddr . getOperand ( <NUM_LIT> ) ) ) { auto FI = cast < FrameIndexSDNode > ( SAddr . getOperand ( <NUM_LIT> ) ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI -> getIndex ( ) , FI -> getValueType ( <NUM_LIT> ) ) ; SAddr = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( SAddr ) , <STR_LIT> , TFI , SAddr . getOperand ( <NUM_LIT> ) ) , <NUM_LIT> ) ; } const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; if ( ! TII -> isLegalFLATOffset ( COffsetVal , <ISA_LIT>AS :: PRIVATE_ADDRESS , true ) ) { int64_t RemainderOffset = COffsetVal ; int64_t ImmField = <NUM_LIT> ; const unsigned NumBits = TII -> getNumFlatOffsetBits ( true ) ; int64_t D = <NUM_LIT> << ( NumBits - <NUM_LIT> ) ; RemainderOffset = ( COffsetVal / D ) * D ; ImmField = COffsetVal - RemainderOffset ; assert ( TII -> isLegalFLATOffset ( ImmField , <ISA_LIT>AS :: PRIVATE_ADDRESS , true ) ) ;

assert ( RemainderOffset + ImmField == COffsetVal ) ;


<s> static bool isNullConstantOrUndef ( SDValue V ) { if ( V . isUndef ( ) ) return true ; ConstantSDNode * Const = dyn_cast < ConstantSDNode > ( V ) ;

return Const != nullptr && Const -> isZero ( ) ;


<s> ConstantSDNode * Const = dyn_cast < ConstantSDNode > ( V ) ;


<s> RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } const SDValue Ops [ ] = { RC , N -> getOperand ( <NUM_LIT> ) , SubReg0 , N -> getOperand ( <NUM_LIT> ) , SubReg1 } ; ReplaceNode ( N , CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) != <NUM_LIT> || isInlineImmediate ( N ) ) break ; uint64_t Imm ; if ( ConstantFPSDNode * FP = dyn_cast < ConstantFPSDNode > ( N ) ) Imm = FP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ; else { ConstantSDNode * C = cast < ConstantSDNode > ( N ) ; Imm = C -> getZExtValue ( ) ; } SDLoc DL ( N ) ; ReplaceNode ( N , buildSMovImm64 ( DL , Imm , N -> getValueType ( <NUM_LIT> ) ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) break ; bool Signed = Opc == <STR_LIT> ; uint32_t OffsetVal = Offset -> getZExtValue ( ) ; uint32_t WidthVal = Width -> getZExtValue ( ) ; ReplaceNode ( N , getBFE32 ( Signed , SDLoc ( N ) , N -> getOperand ( <NUM_LIT> ) , OffsetVal , WidthVal ) ) ; return ; } case <STR_LIT> : { SelectDIV_SCALE ( N ) ; return ; } case <STR_LIT> : case <STR_LIT> : { SelectMAD_64_32 ( N ) ; return ; } case <STR_LIT> : case <STR_LIT> : return SelectMUL_LOHI ( N ) ; case <STR_LIT> : { const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; N = Lowering . legalizeTargetIndependentNode ( N , * CurDAG ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) break ; SelectS_BFE ( N ) ; return ; case <STR_LIT> : SelectBRCOND ( N ) ; return ; case <STR_LIT> : case <STR_LIT> :


<s> void <ISA_LIT>DAGToDAGISel :: SelectINTRIN<ISA_LIT>C_W_CHAIN ( SDNode * N ) { unsigned IntrID = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;


<s> unsigned PtrIdx = M -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( OpIdx == PtrIdx ) continue ; unsigned OpN = M -> getNumOperands ( ) ; SDValue NewOps [ <NUM_LIT> ] ; assert ( OpN < array_lengthof ( NewOps ) ) ; for ( unsigned Op = <NUM_LIT> ; Op != OpN ; ++ Op ) { if ( Op != OpIdx ) { NewOps [ Op ] = M -> getOperand ( Op ) ; continue ; } MachineSDNode * Mov = CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( M ) , <STR_LIT> , FI ) ; NewOps [ Op ] = SDValue ( Mov , <NUM_LIT> ) ; }

CurDAG -> UpdateNodeOperands ( M , makeArrayRef ( NewOps , OpN ) ) ;


<s> break ; } assert ( VT . getVectorElementType ( ) . bitsEq ( <STR_LIT> ) ) ; unsigned RegClassID = selectSGPRVectorRegClassID ( NumVectorElts ) ; SelectBuildVector ( N , RegClassID ) ; return ; } case <STR_LIT> : { SDValue RC , SubReg0 , SubReg1 ; SDLoc DL ( N ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } const SDValue Ops [ ] = { RC , N -> getOperand ( <NUM_LIT> ) , SubReg0 , N -> getOperand ( <NUM_LIT> ) , SubReg1 } ; ReplaceNode ( N , CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) != <NUM_LIT> || isInlineImmediate ( N ) ) break ; uint64_t Imm ; if ( ConstantFPSDNode * FP = dyn_cast < ConstantFPSDNode > ( N ) ) Imm = FP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ; else { ConstantSDNode * C = cast < ConstantSDNode > ( N ) ; Imm = C -> getZExtValue ( ) ; } SDLoc DL ( N ) ; SDNode * Lo = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getConstant ( Imm & <NUM_LIT> , DL , <STR_LIT> ) ) ;

SDNode * Hi = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getConstant ( Imm >> <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> uint64_t COffsetVal = cast < ConstantSDNode > ( N1 ) -> getSExtValue ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; unsigned AS = findMemSDNode ( N ) -> getAddressSpace ( ) ; if ( TII -> isLegalFLATOffset ( COffsetVal , AS , IsSigned ) ) { Addr = N0 ; OffsetVal = COffsetVal ; } else { SDLoc DL ( N ) ; uint64_t RemainderOffset = COffsetVal ; uint64_t ImmField = <NUM_LIT> ; const unsigned NumBits = TII -> getNumFlatOffsetBits ( IsSigned ) ; if ( IsSigned ) { int64_t D = <NUM_LIT> << ( NumBits - <NUM_LIT> ) ; RemainderOffset = ( static_cast < int64_t > ( COffsetVal ) / D ) * D ; ImmField = COffsetVal - RemainderOffset ; } else if ( static_cast < int64_t > ( COffsetVal ) >= <NUM_LIT> ) { ImmField = COffsetVal & maskTrailingOnes < uint64_t > ( NumBits ) ; RemainderOffset = COffsetVal - ImmField ; } assert ( TII -> isLegalFLATOffset ( ImmField , AS , IsSigned ) ) ; assert ( RemainderOffset + ImmField == COffsetVal ) ; OffsetVal = ImmField ; SDValue Sub0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ;

SDValue Sub1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ;


<s> } else if ( getBaseWithOffsetUsingSplitOR ( * CurDAG , Addr , N0 , N1 ) ) { assert ( N0 && N1 && isa < ConstantSDNode > ( N1 ) ) ; } if ( N0 && N1 ) { uint64_t COffsetVal = cast < ConstantSDNode > ( N1 ) -> getSExtValue ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; unsigned AS = findMemSDNode ( N ) -> getAddressSpace ( ) ; if ( TII -> isLegalFLATOffset ( COffsetVal , AS , IsSigned ) ) { Addr = N0 ; OffsetVal = COffsetVal ; } else { SDLoc DL ( N ) ; uint64_t RemainderOffset = COffsetVal ; uint64_t ImmField = <NUM_LIT> ; const unsigned NumBits = TII -> getNumFlatOffsetBits ( IsSigned ) ; if ( IsSigned ) { int64_t D = <NUM_LIT> << ( NumBits - <NUM_LIT> ) ; RemainderOffset = ( static_cast < int64_t > ( COffsetVal ) / D ) * D ; ImmField = COffsetVal - RemainderOffset ; } else if ( static_cast < int64_t > ( COffsetVal ) >= <NUM_LIT> ) { ImmField = COffsetVal & maskTrailingOnes < uint64_t > ( NumBits ) ; RemainderOffset = COffsetVal - ImmField ; } assert ( TII -> isLegalFLATOffset ( ImmField , AS , IsSigned ) ) ; assert ( RemainderOffset + ImmField == COffsetVal ) ; OffsetVal = ImmField ; SDValue Sub0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Sub1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDNode * N0Lo = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , N0 , Sub0 ) ; SDNode * N0Hi = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , N0 , Sub1 ) ; SDValue AddOffsetLo = getMaterializedScalarImm32 ( Lo_32 ( RemainderOffset ) , DL ) ; SDValue AddOffsetHi = getMaterializedScalarImm32 ( Hi_32 ( RemainderOffset ) , DL ) ; SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Clamp = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDNode * Add = CurDAG -> getMachineNode ( <STR_LIT> , DL , VTs , { AddOffsetLo , SDValue ( N0Lo , <NUM_LIT> ) , Clamp } ) ; SDNode * Addc = CurDAG -> getMachineNode ( <STR_LIT> , DL , VTs , { AddOffsetHi , SDValue ( N0Hi , <NUM_LIT> ) , SDValue ( Add , <NUM_LIT> ) , Clamp } ) ; SDValue RegSequenceArgs [ ] = {

CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , SDValue ( Add , <NUM_LIT> ) , Sub0 , SDValue ( Addc , <NUM_LIT> ) , Sub1 } ;


<s> if ( Subtarget -> getGeneration ( ) < <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) return ! isa < GlobalValue > ( GetUnderlyingObject ( N -> getMemOperand ( ) -> getValue ( ) , CurDAG -> getDataLayout ( ) ) ) ; if ( N -> getMemoryVT ( ) . bitsLT ( <STR_LIT> ) ) return true ;


<s> AMDGPUA<ISA_LIT> = <STR_LIT> ( * TM ) ; EnableLateStructurizeCFG = <ISA_LIT>TargetMachine :: EnableLateStructurizeCFG ;


<s> MachineSDNode * <ISA_LIT>DAGToDAGISel :: buildSMovImm64 ( SDLoc & DL , uint64_t Imm , EVT VT ) const { SDNode * Lo = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getConstant ( Imm & <NUM_LIT> , DL , <STR_LIT> ) ) ; SDNode * Hi = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getConstant ( Imm >> <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( TargetMachine * TM , CodeGenOpt :: Level OptLevel ) {

return new <ISA_LIT>DAGToDAGISel ( TM , OptLevel ) ;


CurDAG -> getTargetConstant ( <STR_LIT> , SL , <STR_LIT> ) , Addr , CurDAG -> getTargetConstant ( <STR_LIT> , SL , <STR_LIT> ) , SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , AddrHi ) , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <STR_LIT> , SL , <STR_LIT> ) , } ;


<s> SDValue AddrHi = CurDAG -> getTargetConstant ( AddrHiVal , SL , <STR_LIT> ) ; const SDValue Ops [ ] = { CurDAG -> getTargetConstant ( <STR_LIT> , SL , <STR_LIT> ) , Addr , CurDAG -> getTargetConstant ( <STR_LIT> , SL , <STR_LIT> ) , SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , AddrHi ) , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <STR_LIT> , SL , <STR_LIT> ) , } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , Ops ) , <NUM_LIT> ) ;


<s> SDValue TFI = CurDAG -> getTargetFrameIndex ( FI -> getIndex ( ) , FI -> getValueType ( <NUM_LIT> ) ) ; return std :: make_pair ( TFI , CurDAG -> getRegister ( Info -> getFrameOffsetReg ( ) , <STR_LIT> ) ) ;


<s> const MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( auto FI = dyn_cast < FrameIndexSDNode > ( N ) ) { SDValue TFI = CurDAG -> getTargetFrameIndex ( FI -> getIndex ( ) , FI -> getValueType ( <NUM_LIT> ) ) ; return std :: make_pair ( TFI , CurDAG -> getRegister ( Info -> getFrameOffsetReg ( ) , <STR_LIT> ) ) ; } return std :: make_pair ( N , CurDAG -> getRegister ( Info -> getScratchWaveOffsetReg ( ) , <STR_LIT> ) ) ;


<s> AU . addRequired < <ISA_LIT>ArgumentUsageInfo > ( ) ;

AU . addRequired < <ISA_LIT>PerfHintAnalysis > ( ) ;


<s> AU . addRequired < <ISA_LIT>ArgumentUsageInfo > ( ) ; AU . addRequired < <ISA_LIT>PerfHintAnalysis > ( ) ; AU . addRequired < DivergenceAnalysis > ( ) ;

SelectionDAGISel :: getAnalysisUsage ( AU ) ;


<s> } if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N ) ) { Out = C -> getAPIntValue ( ) . getSExtValue ( ) ; return true ; } if ( const ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( N ) ) { Out = C -> getValueAPF ( ) . bitcastToAPInt ( ) . getSExtValue ( ) ; return true ; } return false ;


<s> Out = C -> getAPIntValue ( ) . getSExtValue ( ) ; return true ; }

if ( const ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( N ) ) {


<s> return MRI . getRegClass ( Reg ) ; } const <ISA_LIT>RegisterInfo * TRI = static_cast < const GCNSubtarget * > ( Subtarget ) -> getRegisterInfo ( ) ; return TRI -> getPhysRegClass ( Reg ) ; } return nullptr ; } switch ( N -> getMachineOpcode ( ) ) { default : { const MCInstrDesc & Desc = Subtarget -> getInstrInfo ( ) -> get ( N -> getMachineOpcode ( ) ) ; unsigned OpIdx = Desc . getNumDefs ( ) + OpNo ; if ( OpIdx >= Desc . getNumOperands ( ) ) return nullptr ; int RegClass = Desc . OpInfo [ OpIdx ] . RegClass ; if ( RegClass == - <NUM_LIT> ) return nullptr ; return Subtarget -> getRegisterInfo ( ) -> getRegClass ( RegClass ) ; } case <STR_LIT> : { unsigned RCID = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;

const TargetRegisterClass * SuperRC = Subtarget -> getRegisterInfo ( ) -> getRegClass ( RCID ) ;


<s> if ( ! N -> isMachineOpcode ( ) ) { if ( N -> getOpcode ( ) == <STR_LIT> ) { unsigned Reg = cast < RegisterSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { MachineRegisterInfo & MRI = CurDAG -> getMachineFunction ( ) . getRegInfo ( ) ; return MRI . getRegClass ( Reg ) ; } const <ISA_LIT>RegisterInfo * TRI = static_cast < const GCNSubtarget * > ( Subtarget ) -> getRegisterInfo ( ) ; return TRI -> getPhysRegClass ( Reg ) ; } return nullptr ; } switch ( N -> getMachineOpcode ( ) ) { default : { const MCInstrDesc & Desc = Subtarget -> getInstrInfo ( ) -> get ( N -> getMachineOpcode ( ) ) ; unsigned OpIdx = Desc . getNumDefs ( ) + OpNo ; if ( OpIdx >= Desc . getNumOperands ( ) ) return nullptr ; int RegClass = Desc . OpInfo [ OpIdx ] . RegClass ; if ( RegClass == - <NUM_LIT> ) return nullptr ; return Subtarget -> getRegisterInfo ( ) -> getRegClass ( RegClass ) ; } case <STR_LIT> : { unsigned RCID = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; const TargetRegisterClass * SuperRC = Subtarget -> getRegisterInfo ( ) -> getRegClass ( RCID ) ; SDValue SubRegOp = N -> getOperand ( OpNo + <NUM_LIT> ) ; unsigned SubRegIdx = cast < ConstantSDNode > ( SubRegOp ) -> getZExtValue ( ) ; return Subtarget -> getRegisterInfo ( ) -> getSubClassWithSubReg ( SuperRC , SubRegIdx ) ; }


<s> uint32_t PackedVal = Offset | ( Width << <NUM_LIT> ) ; SDValue PackedConst = CurDAG -> getTargetConstant ( PackedVal , DL , <STR_LIT> ) ;

return CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , Val , PackedConst ) ;


<s> SDValue M0 = Lowering . copyToM0 ( * CurDAG , CurDAG -> getEntryNode ( ) , SDLoc ( N ) , CurDAG -> getTargetConstant ( - <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ) ; SDValue Glue = M0 . getValue ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { Ops . push_back ( N -> getOperand ( i ) ) ; } Ops . push_back ( Glue ) ;

return CurDAG -> MorphNodeTo ( N , N -> getOpcode ( ) , N -> getVTList ( ) , Ops ) ;


<s> SDValue M0 = Lowering . copyToM0 ( * CurDAG , CurDAG -> getEntryNode ( ) , SDLoc ( N ) , CurDAG -> getTargetConstant ( - <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ) ; SDValue Glue = M0 . getValue ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) {

Ops . push_back ( N -> getOperand ( i ) ) ;


<s> if ( VT == <STR_LIT> ) { auto ST = static_cast < const GCNSubtarget * > ( Subtarget ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) -> get ( ) ; return ( CC == <STR_LIT> || CC == <STR_LIT> ) && ST -> hasScalarCompareEq64 ( ) ; }


<s> MVT VT = Cond . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; if ( VT == <STR_LIT> ) return true ; if ( VT == <STR_LIT> ) { auto ST = static_cast < const GCNSubtarget * > ( Subtarget ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) -> get ( ) ; return ( CC == <STR_LIT> || CC == <STR_LIT> ) && ST -> hasScalarCompareEq64 ( ) ; } return false ;


<s> if ( ! N -> readMem ( ) ) return false ;

if ( CbId == - <NUM_LIT> ) return N -> getAddressSpace ( ) == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS || N -> getAddressSpace ( ) == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS_32BIT ;


<s> In = stripBitcast ( In ) ; if ( In . getOpcode ( ) != <STR_LIT> ) return false ; SDValue Srl = In . getOperand ( <NUM_LIT> ) ; if ( Srl . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * ShiftAmt = dyn_cast < ConstantSDNode > ( Srl . getOperand ( <NUM_LIT> ) ) ) {

if ( ShiftAmt -> getZExtValue ( ) == <NUM_LIT> ) {


<s> if ( In . getOpcode ( ) != <STR_LIT> ) return false ; SDValue Srl = In . getOperand ( <NUM_LIT> ) ; if ( Srl . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * ShiftAmt = dyn_cast < ConstantSDNode > ( Srl . getOperand ( <NUM_LIT> ) ) ) { if ( ShiftAmt -> getZExtValue ( ) == <NUM_LIT> ) { Out = stripBitcast ( Srl . getOperand ( <NUM_LIT> ) ) ; return true ; } } }


<s> return Subtarget -> getInstrInfo ( ) -> isInlineConstant ( Imm ) ;


<s> bool isInlineImmediate ( const APFloat & Imm ) const { return Subtarget -> getInstrInfo ( ) -> isInlineConstant ( Imm ) ;


<s> bool isInlineImmediate16 ( int64_t Imm ) const {

return <STR_LIT> ( Imm , Subtarget -> hasInv2PiInlineImm ( ) ) ;


<s> bool isInlineImmediate32 ( int64_t Imm ) const { return <STR_LIT> ( Imm , Subtarget -> hasInv2PiInlineImm ( ) ) ;


<s> if ( N -> getFlags ( ) . isDefined ( ) ) return N -> getFlags ( ) . hasNoNaNs ( ) ; return CurDAG -> isKnownNeverNaN ( N ) ;


<s> if ( TM . Options . NoNaNsFPMath ) return true ; if ( N -> getFlags ( ) . isDefined ( ) ) return N -> getFlags ( ) . hasNoNaNs ( ) ; return CurDAG -> isKnownNeverNaN ( N ) ;


<s> static inline bool isNullConstantOrUndef ( SDValue V ) {


<s> const BasicBlock * BB = FuncInfo -> MBB -> getBasicBlock ( ) ; const Instruction * Term = BB -> getTerminator ( ) ; return Term -> getMetadata ( <STR_LIT> ) || Term -> getMetadata ( <STR_LIT> ) ;


<s> static inline SDNode * packConstantV2I16 ( const SDNode * N , SelectionDAG & DAG , bool Negate = false ) { assert ( N -> getOpcode ( ) == <STR_LIT> && N -> getNumOperands ( ) == <NUM_LIT> ) ; uint32_t LHSVal , RHSVal ; if ( getConstantValue ( N -> getOperand ( <NUM_LIT> ) , LHSVal ) && getConstantValue ( N -> getOperand ( <NUM_LIT> ) , RHSVal ) ) { SDLoc SL ( N ) ; uint32_t K = Negate ? ( - LHSVal & <NUM_LIT> ) | ( - RHSVal << <NUM_LIT> ) : ( LHSVal & <NUM_LIT> ) | ( RHSVal << <NUM_LIT> ) ; return DAG . getMachineNode ( <STR_LIT> , SL , N -> getValueType ( <NUM_LIT> ) , DAG . getTargetConstant ( K , SL , <STR_LIT> ) ) ; } return nullptr ;


<s> bool IsModified = false ; do { IsModified = false ; SelectionDAG :: allnodes_iterator Position = CurDAG -> allnodes_begin ( ) ; while ( Position != CurDAG -> allnodes_end ( ) ) { SDNode * Node = & * Position ++ ; MachineSDNode * MachineNode = dyn_cast < MachineSDNode > ( Node ) ; if ( ! MachineNode ) continue ; SDNode * ResNode = Lowering . PostISelFolding ( MachineNode , * CurDAG ) ; if ( ResNode != Node ) { if ( ResNode ) ReplaceUses ( Node , ResNode ) ; IsModified = true ; } } CurDAG -> RemoveDeadNodes ( ) ;


<s> void <ISA_LIT>DAGToDAGISel :: PostprocessISelDAG ( ) { const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; bool IsModified = false ; do { IsModified = false ;

SelectionDAG :: allnodes_iterator Position = CurDAG -> allnodes_begin ( ) ;


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned NumVectorElts = VT . getVectorNumElements ( ) ; unsigned RegClassID ; switch ( NumVectorElts ) { case <NUM_LIT> : RegClassID = <STR_LIT> ; break ;


<s> if ( Addr . getOpcode ( ) == <STR_LIT> && ( IMMOffset = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && isInt < <NUM_LIT> > ( IMMOffset -> getZExtValue ( ) ) ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( IMMOffset -> getZExtValue ( ) , SDLoc ( Addr ) , <STR_LIT> ) ; return true ;

} else if ( ( IMMOffset = dyn_cast < ConstantSDNode > ( Addr ) ) && isInt < <NUM_LIT> > ( IMMOffset -> getZExtValue ( ) ) ) {


<s> AddLo = CurDAG -> getMachineNode ( Opc , DL , VTList , Args ) ; } else { SDValue Args [ ] = { SDValue ( Lo0 , <NUM_LIT> ) , SDValue ( Lo1 , <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; AddLo = CurDAG -> getMachineNode ( CarryOpc , DL , VTList , Args ) ; } SDValue AddHiArgs [ ] = { SDValue ( Hi0 , <NUM_LIT> ) , SDValue ( Hi1 , <NUM_LIT> ) , SDValue ( AddLo , <NUM_LIT> ) } ; SDNode * AddHi = CurDAG -> getMachineNode ( CarryOpc , DL , VTList , AddHiArgs ) ; SDValue RegSequenceArgs [ ] = { CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , SDValue ( AddLo , <NUM_LIT> ) , Sub0 , SDValue ( AddHi , <NUM_LIT> ) , Sub1 , } ; SDNode * RegSequence = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , RegSequenceArgs ) ; if ( ProduceCarry ) { ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( AddHi , <NUM_LIT> ) ) ; }


<s> unsigned Opc = IsAdd ? <STR_LIT> : <STR_LIT> ; unsigned CarryOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; SDNode * AddLo ; if ( ! ConsumeCarry ) { SDValue Args [ ] = { SDValue ( Lo0 , <NUM_LIT> ) , SDValue ( Lo1 , <NUM_LIT> ) } ; AddLo = CurDAG -> getMachineNode ( Opc , DL , VTList , Args ) ; } else { SDValue Args [ ] = { SDValue ( Lo0 , <NUM_LIT> ) , SDValue ( Lo1 , <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; AddLo = CurDAG -> getMachineNode ( CarryOpc , DL , VTList , Args ) ; } SDValue AddHiArgs [ ] = { SDValue ( Hi0 , <NUM_LIT> ) , SDValue ( Hi1 , <NUM_LIT> ) , SDValue ( AddLo , <NUM_LIT> ) } ; SDNode * AddHi = CurDAG -> getMachineNode ( CarryOpc , DL , VTList , AddHiArgs ) ; SDValue RegSequenceArgs [ ] = { CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , SDValue ( AddLo , <NUM_LIT> ) , Sub0 , SDValue ( AddHi , <NUM_LIT> ) , Sub1 , } ; SDNode * RegSequence = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , RegSequenceArgs ) ; if ( ProduceCarry ) { ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( AddHi , <NUM_LIT> ) ) ; } ReplaceNode ( N , RegSequence ) ;


<s> bool Is32 = ( VT == <STR_LIT> ) ; SDLoc SL ( N ) ; MachineSDNode * CmpSwap = nullptr ; if ( Subtarget -> hasAddr64 ( ) ) { SDValue SRsrc , VAddr , SOffset , Offset , SLC ; if ( SelectMUBUFAddr64 ( Mem -> getBasePtr ( ) , SRsrc , VAddr , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { CmpVal , VAddr , SRsrc , SOffset , Offset , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SDValue SRsrc , SOffset , Offset , SLC ; if ( SelectMUBUFOffset ( Mem -> getBasePtr ( ) , SRsrc , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { CmpVal , SRsrc , SOffset , Offset , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SelectCode ( N ) ;


<s> if ( Cond . isUndef ( ) ) { CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; return ; } bool UseSCCBr = isCBranchSCC ( N ) && isUniformBr ( N ) ; unsigned BrOp = UseSCCBr ? <STR_LIT> : <STR_LIT> ; unsigned CondReg = UseSCCBr ? <STR_LIT> : <STR_LIT> ;


<s> assert ( NumVectorElts <= <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> * <NUM_LIT> + <NUM_LIT> > RegSeqArgs ( NumVectorElts * <NUM_LIT> + <NUM_LIT> ) ; RegSeqArgs [ <NUM_LIT> ] = CurDAG -> getTargetConstant ( RegClassID , DL , <STR_LIT> ) ; bool IsRegSeq = true ; unsigned NOps = N -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NOps ; i ++ ) { if ( isa < RegisterSDNode > ( N -> getOperand ( i ) ) ) { IsRegSeq = false ; break ; } unsigned Sub = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( i ) ; RegSeqArgs [ <NUM_LIT> + ( <NUM_LIT> * i ) ] = N -> getOperand ( i ) ; RegSeqArgs [ <NUM_LIT> + ( <NUM_LIT> * i ) + <NUM_LIT> ] = CurDAG -> getTargetConstant ( Sub , DL , <STR_LIT> ) ;


<s> void <ISA_LIT>DAGToDAGISel :: SelectDIV_SCALE ( SDNode * N ) { SDLoc SL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( VT == <STR_LIT> || VT == <STR_LIT> ) ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ;

SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ;


<s> unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ;

CurDAG -> SelectNodeTo ( N , Opc , N -> getVTList ( ) , Ops ) ;


<s> int64_t ByteOffset = C -> getSExtValue ( ) ; if ( isUInt < <NUM_LIT> > ( ByteOffset ) ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Sub = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , Zero , Addr . getOperand ( <NUM_LIT> ) ) ; if ( isDSOffsetLegal ( Sub , ByteOffset , <NUM_LIT> ) ) { unsigned SubOp = Subtarget -> hasAddNoCarry ( ) ? <STR_LIT> : <STR_LIT> ; MachineSDNode * MachineSub = CurDAG -> getMachineNode ( SubOp , DL , <STR_LIT> , Zero , Addr . getOperand ( <NUM_LIT> ) ) ; Base = SDValue ( MachineSub , <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( ByteOffset , DL , <STR_LIT> ) ; return true ; } } } } else if ( const ConstantSDNode * CAddr = dyn_cast < ConstantSDNode > ( Addr ) ) { SDLoc DL ( Addr ) ; if ( isUInt < <NUM_LIT> > ( CAddr -> getZExtValue ( ) ) ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; MachineSDNode * MovZero = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Zero ) ; Base = SDValue ( MovZero , <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CAddr -> getZExtValue ( ) , DL , <STR_LIT> ) ; return true ; }


<s> bool <ISA_LIT>DAGToDAGISel :: SelectDS64Bit4ByteAligned ( SDValue Addr , SDValue & Base , SDValue & Offset0 , SDValue & Offset1 ) const { SDLoc DL ( Addr ) ; if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; unsigned DWordOffset0 = C1 -> getZExtValue ( ) / <NUM_LIT> ; unsigned DWordOffset1 = DWordOffset0 + <NUM_LIT> ; if ( isDSOffsetLegal ( N0 , DWordOffset1 , <NUM_LIT> ) ) { Base = N0 ; Offset0 = CurDAG -> getTargetConstant ( DWordOffset0 , DL , <STR_LIT> ) ; Offset1 = CurDAG -> getTargetConstant ( DWordOffset1 , DL , <STR_LIT> ) ; return true ; } } else if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { unsigned DWordOffset0 = C -> getZExtValue ( ) / <NUM_LIT> ; unsigned DWordOffset1 = DWordOffset0 + <NUM_LIT> ; if ( isUInt < <NUM_LIT> > ( DWordOffset0 ) ) { SDLoc DL ( Addr ) ; SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Sub = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , Zero , Addr . getOperand ( <NUM_LIT> ) ) ; if ( isDSOffsetLegal ( Sub , DWordOffset1 , <NUM_LIT> ) ) { unsigned SubOp = Subtarget -> hasAddNoCarry ( ) ? <STR_LIT> : <STR_LIT> ; MachineSDNode * MachineSub = CurDAG -> getMachineNode ( SubOp , DL , <STR_LIT> , Zero , Addr . getOperand ( <NUM_LIT> ) ) ;

Base = SDValue ( MachineSub , <NUM_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectFlatAtomic ( SDValue Addr , SDValue & VAddr , SDValue & Offset , SDValue & SLC ) const { return SelectFlatOffset < false > ( Addr , VAddr , Offset , SLC ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectFlatAtomic ( SDValue Addr , SDValue & VAddr , SDValue & Offset , SDValue & SLC ) const {

return SelectFlatOffset < false > ( Addr , VAddr , Offset , SLC ) ;


<s> return SelectFlatOffset < true > ( Addr , VAddr , Offset , SLC ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectFlatAtomicSigned ( SDValue Addr , SDValue & VAddr , SDValue & Offset , SDValue & SLC ) const { return SelectFlatOffset < true > ( Addr , VAddr , Offset , SLC ) ;


<s> int64_t COffsetVal = cast < ConstantSDNode > ( N1 ) -> getSExtValue ( ) ; if ( ( IsSigned && isInt < <NUM_LIT> > ( COffsetVal ) ) || ( ! IsSigned && isUInt < <NUM_LIT> > ( COffsetVal ) ) ) { Addr = N0 ; OffsetVal = COffsetVal ; } } VAddr = Addr ; Offset = CurDAG -> getTargetConstant ( OffsetVal , SDLoc ( ) , <STR_LIT> ) ; SLC = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( ) , <STR_LIT> ) ; return true ;


<s> int64_t OffsetVal = <NUM_LIT> ; if ( Subtarget -> hasFlatInstOffsets ( ) && CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; int64_t COffsetVal = cast < ConstantSDNode > ( N1 ) -> getSExtValue ( ) ; if ( ( IsSigned && isInt < <NUM_LIT> > ( COffsetVal ) ) || ( ! IsSigned && isUInt < <NUM_LIT> > ( COffsetVal ) ) ) { Addr = N0 ; OffsetVal = COffsetVal ; } } VAddr = Addr ;

Offset = CurDAG -> getTargetConstant ( OffsetVal , SDLoc ( ) , <STR_LIT> ) ;


<s> void <ISA_LIT>DAGToDAGISel :: SelectFMAD_FMA ( SDNode * N ) { MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; bool IsFMA = N -> getOpcode ( ) == <STR_LIT> ; if ( VT != <STR_LIT> || ( ! Subtarget -> hasMadMixInsts ( ) && ! Subtarget -> hasFmaMixInsts ( ) ) || ( ( IsFMA && Subtarget -> hasMadMixInsts ( ) ) || ( ! IsFMA && Subtarget -> hasFmaMixInsts ( ) ) ) ) { SelectCode ( N ) ; return ; } SDValue Src0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Src1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Src2 = N -> getOperand ( <NUM_LIT> ) ; unsigned Src0Mods , Src1Mods , Src2Mods ; bool Sel0 = SelectVOP3PMadMixModsImpl ( Src0 , Src0 , Src0Mods ) ; bool Sel1 = SelectVOP3PMadMixModsImpl ( Src1 , Src1 , Src1Mods ) ;


<s> SelectCode ( N ) ; return ; } SDValue Src0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Src1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Src2 = N -> getOperand ( <NUM_LIT> ) ; unsigned Src0Mods , Src1Mods , Src2Mods ; bool Sel0 = SelectVOP3PMadMixModsImpl ( Src0 , Src0 , Src0Mods ) ; bool Sel1 = SelectVOP3PMadMixModsImpl ( Src1 , Src1 , Src1Mods ) ; bool Sel2 = SelectVOP3PMadMixModsImpl ( Src2 , Src2 , Src2Mods ) ;

assert ( ( IsFMA || ! Subtarget -> hasFP32Denormals ( ) ) && <STR_LIT> ) ;


<s> Ops [ <NUM_LIT> ] = N -> getOperand ( <NUM_LIT> ) ; Ops [ <NUM_LIT> ] = N -> getOperand ( <NUM_LIT> ) ;

CurDAG -> SelectNodeTo ( N , <STR_LIT> , N -> getVTList ( ) , Ops ) ;


<s> SDLoc SL ( N ) ; SDValue Ops [ <NUM_LIT> ] ; SelectVOP3Mods0 ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ;

SelectVOP3Mods ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ;


<s> void <ISA_LIT>DAGToDAGISel :: SelectFMUL_W_CHAIN ( SDNode * N ) { SDLoc SL ( N ) ; SDValue Ops [ <NUM_LIT> ] ; SelectVOP3Mods0 ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectGlobalValueConstantOffset ( SDValue Addr , SDValue & IntPtr ) { if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Addr ) ) { IntPtr = CurDAG -> getIntPtrConstant ( Cst -> getZExtValue ( ) / <NUM_LIT> , SDLoc ( Addr ) , true ) ; return true ; }


<s> bool <ISA_LIT>DAGToDAGISel :: SelectGlobalValueConstantOffset ( SDValue Addr , SDValue & IntPtr ) { if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Addr ) ) { IntPtr = CurDAG -> getIntPtrConstant ( Cst -> getZExtValue ( ) / <NUM_LIT> , SDLoc ( Addr ) , true ) ;


<s> Offset = CurDAG -> getIntPtrConstant ( <NUM_LIT> , SDLoc ( Addr ) , true ) ; return true ; } return false ;


<s> SDValue K = CurDAG -> getTargetConstant ( C -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) << <NUM_LIT> , SL , <STR_LIT> ) ; MachineSDNode * MovK = CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , K ) ; Src = SDValue ( MovK , <NUM_LIT> ) ; return true ; } return isExtractHiElt ( In , Src ) ;


<s> bool Signed = N -> getOpcode ( ) == <STR_LIT> ; unsigned Opc = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Clamp = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Clamp } ;


<s> bool Signed = N -> getOpcode ( ) == <STR_LIT> ; unsigned Opc = Signed ? <STR_LIT> : <STR_LIT> ;

SDValue Clamp = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ;


<s> if ( CurDAG -> isBaseWithConstantOffset ( Index ) ) { SDValue N0 = Index . getOperand ( <NUM_LIT> ) ; SDValue N1 = Index . getOperand ( <NUM_LIT> ) ;

ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ;


<s> Base = N0 ; Offset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ; return true ; } if ( isa < ConstantSDNode > ( Index ) ) return false ; Base = Index ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; return true ;


<s> } else { uint32_t High = ( Imm + Align ) & ~ <NUM_LIT> ; uint32_t Low = ( Imm + Align ) & <NUM_LIT> ; Imm = Low ; Overflow = High - Align ; } } if ( Overflow > <NUM_LIT> && Subtarget -> getGeneration ( ) <= <ISA_LIT>Subtarget :: SEA_ISLANDS ) return false ; ImmOffset = CurDAG -> getTargetConstant ( Imm , DL , <STR_LIT> ) ; if ( Overflow <= <NUM_LIT> ) SOffset = CurDAG -> getTargetConstant ( Overflow , DL , <STR_LIT> ) ;

else SOffset = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getTargetConstant ( Overflow , DL , <STR_LIT> ) ) , <NUM_LIT> ) ;


<s> SDLoc DL ( Constant ) ; const uint32_t Align = <NUM_LIT> ; const uint32_t MaxImm = alignDown ( <NUM_LIT> , Align ) ; uint32_t Imm = cast < ConstantSDNode > ( Constant ) -> getZExtValue ( ) ; uint32_t Overflow = <NUM_LIT> ; if ( Imm > MaxImm ) { if ( Imm <= MaxImm + <NUM_LIT> ) { Overflow = Imm - MaxImm ; Imm = MaxImm ; } else { uint32_t High = ( Imm + Align ) & ~ <NUM_LIT> ; uint32_t Low = ( Imm + Align ) & <NUM_LIT> ; Imm = Low ; Overflow = High - Align ;


<s> SDLoc DL ( Offset ) ; if ( ! isa < ConstantSDNode > ( Offset ) ) return false ; return SelectMUBUFConstant ( Offset , SOffset , ImmOffset ) ;


<s> if ( cast < ConstantSDNode > ( N1 ) -> getSExtValue ( ) >= <NUM_LIT> && SelectMUBUFConstant ( N1 , SOffset , ImmOffset ) ) { VOffset = N0 ; return true ; } } SOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ImmOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ;


<s> if ( isa < ConstantSDNode > ( Offset ) ) { SDValue Tmp1 , Tmp2 ; if ( Subtarget -> getGeneration ( ) > <ISA_LIT>Subtarget :: SEA_ISLANDS || SelectMUBUFConstant ( Offset , Tmp1 , Tmp2 ) ) return false ; } if ( CurDAG -> isBaseWithConstantOffset ( Offset ) ) { SDValue N0 = Offset . getOperand ( <NUM_LIT> ) ;

SDValue N1 = Offset . getOperand ( <NUM_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectMUBUFOffset ( SDValue Addr , SDValue & SRsrc , SDValue & Soffset , SDValue & Offset , SDValue & SLC ) const { SDValue GLC , TFE ;

return SelectMUBUFOffset ( Addr , SRsrc , Soffset , Offset , GLC , SLC , TFE ) ;


<s> const MachinePointerInfo & PtrInfo = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) ; unsigned SOffsetReg = isStackPtrRelative ( PtrInfo ) ? Info -> getStackPtrOffsetReg ( ) : Info -> getScratchWaveOffsetReg ( ) ; SOffset = CurDAG -> getRegister ( SOffsetReg , <STR_LIT> ) ; ImmOffset = CurDAG -> getTargetConstant ( Imm & <NUM_LIT> , DL , <STR_LIT> ) ; return true ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( C1 -> getZExtValue ( ) ) && ( ! Subtarget -> privateMemoryResourceIsRangeChecked ( ) || CurDAG -> SignBitIsZero ( N0 ) ) ) { std :: tie ( VAddr , SOffset ) = foldFrameIndex ( N0 ) ; ImmOffset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ; return true ; } } std :: tie ( VAddr , SOffset ) = foldFrameIndex ( Addr ) ;

ImmOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ;


<s> const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SRsrc = CurDAG -> getRegister ( Info -> getScratchRSrcReg ( ) , <STR_LIT> ) ; const MachinePointerInfo & PtrInfo = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) ;

unsigned SOffsetReg = isStackPtrRelative ( PtrInfo ) ? Info -> getStackPtrOffsetReg ( ) : Info -> getScratchWaveOffsetReg ( ) ;


<s> const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SRsrc = CurDAG -> getRegister ( Info -> getScratchRSrcReg ( ) , <STR_LIT> ) ; const MachinePointerInfo & PtrInfo = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) ; unsigned SOffsetReg = isStackPtrRelative ( PtrInfo ) ? Info -> getStackPtrOffsetReg ( ) : Info -> getScratchWaveOffsetReg ( ) ; SOffset = CurDAG -> getRegister ( SOffsetReg , <STR_LIT> ) ;

Offset = CurDAG -> getTargetConstant ( CAddr -> getZExtValue ( ) , DL , <STR_LIT> ) ;


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ;


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectSMRD ( SDValue Addr , SDValue & SBase , SDValue & Offset , bool & Imm ) const { SDLoc SL ( Addr ) ; if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; if ( SelectSMRDOffset ( N1 , Offset , Imm ) ) { SBase = Expand32BitAddress ( N0 ) ; return true ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectSMRD ( SDValue Addr , SDValue & SBase , SDValue & Offset , bool & Imm ) const { SDLoc SL ( Addr ) ; if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; if ( SelectSMRDOffset ( N1 , Offset , Imm ) ) { SBase = Expand32BitAddress ( N0 ) ; return true ; } } SBase = Expand32BitAddress ( Addr ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; Imm = true ; return true ;


<s> Imm = true ; return true ; } if ( ! isUInt < <NUM_LIT> > ( EncodedOffset ) || ! isUInt < <NUM_LIT> > ( ByteOffset ) ) return false ; if ( Gen == <ISA_LIT>Subtarget :: SEA_ISLANDS && isUInt < <NUM_LIT> > ( EncodedOffset ) ) { Offset = CurDAG -> getTargetConstant ( EncodedOffset , SL , <STR_LIT> ) ; } else { SDValue C32Bit = CurDAG -> getTargetConstant ( ByteOffset , SL , <STR_LIT> ) ; Offset = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , C32Bit ) , <NUM_LIT> ) ; }


<s> uint32_t MaskVal = Mask -> getZExtValue ( ) ; if ( isMask_32 ( MaskVal ) ) { uint32_t WidthVal = countPopulation ( MaskVal ) ; ReplaceNode ( N , getS_BFE ( <STR_LIT> , SDLoc ( N ) , Srl . getOperand ( <NUM_LIT> ) , ShiftVal , WidthVal ) ) ; return ; } } } break ; case <STR_LIT> : if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { const SDValue & And = N -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * Shift = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * Mask = dyn_cast < ConstantSDNode > ( And -> getOperand ( <NUM_LIT> ) ) ; if ( Shift && Mask ) { uint32_t ShiftVal = Shift -> getZExtValue ( ) ; uint32_t MaskVal = Mask -> getZExtValue ( ) >> ShiftVal ; if ( isMask_32 ( MaskVal ) ) { uint32_t WidthVal = countPopulation ( MaskVal ) ; ReplaceNode ( N , getS_BFE ( <STR_LIT> , SDLoc ( N ) , And . getOperand ( <NUM_LIT> ) , ShiftVal , WidthVal ) ) ; return ; } } } else if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SelectS_BFEFromShifts ( N ) ; return ; } break ; case <STR_LIT> : if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SelectS_BFEFromShifts ( N ) ; return ; } break ;


<s> ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( B && C ) { uint32_t BVal = B -> getZExtValue ( ) ; uint32_t CVal = C -> getZExtValue ( ) ; if ( <NUM_LIT> < BVal && BVal <= CVal && CVal < <NUM_LIT> ) { bool Signed = N -> getOpcode ( ) == <STR_LIT> ;

unsigned Opcode = Signed ? <STR_LIT> : <STR_LIT> ;


<s> void <ISA_LIT>DAGToDAGISel :: SelectUADDO_USUBO ( SDNode * N ) { unsigned Opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; CurDAG -> SelectNodeTo ( N , Opc , N -> getVTList ( ) , { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ) ;


<s> CurDAG -> SelectNodeTo ( N , Opc , N -> getVTList ( ) , { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ) ;


<s> SrcMods = CurDAG -> getTargetConstant ( Mods , SDLoc ( In ) , <STR_LIT> ) ;


<s> if ( SelectVOP3ModsImpl ( In , Src , Mods ) ) { SrcMods = CurDAG -> getTargetConstant ( Mods , SDLoc ( In ) , <STR_LIT> ) ; return true ; } return false ;


<s> Mods = <NUM_LIT> ; Src = In ; if ( Src . getOpcode ( ) == <STR_LIT> ) { Mods |= <STR_LIT> ; Src = Src . getOperand ( <NUM_LIT> ) ; } if ( Src . getOpcode ( ) == <STR_LIT> ) { Mods |= <STR_LIT> ; Src = Src . getOperand ( <NUM_LIT> ) ; }


<s> bool <ISA_LIT>DAGToDAGISel :: SelectVOP3NoMods ( SDValue In , SDValue & Src ) const { if ( In . getOpcode ( ) == <STR_LIT> || In . getOpcode ( ) == <STR_LIT> ) return false ;


<s> if ( In . getOpcode ( ) == <STR_LIT> || In . getOpcode ( ) == <STR_LIT> ) return false ;


<s> SDLoc DL ( In ) ; Clamp = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Omod = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; return true ;


<s> SDLoc DL ( In ) ; Clamp = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ;

Omod = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectVOP3OpSel ( SDValue In , SDValue & Src , SDValue & SrcMods ) const { Src = In ;

SrcMods = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( In ) , <STR_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectVOP3OpSel0 ( SDValue In , SDValue & Src , SDValue & SrcMods , SDValue & Clamp ) const { SDLoc SL ( In ) ; Clamp = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ;

return SelectVOP3OpSel ( In , Src , SrcMods ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectVOP3OpSelMods ( SDValue In , SDValue & Src , SDValue & SrcMods ) const {

return SelectVOP3Mods ( In , Src , SrcMods ) ;


<s> return SelectVOP3Mods ( In , Src , SrcMods ) ;


<s> SDLoc SL ( In ) ; Clamp = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; return SelectVOP3OpSelMods ( In , Src , SrcMods ) ;


<s> unsigned Mods = <NUM_LIT> ; SelectVOP3PMadMixModsImpl ( In , Src , Mods ) ; SrcMods = CurDAG -> getTargetConstant ( Mods , SDLoc ( In ) , <STR_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectVOP3PMadMixMods ( SDValue In , SDValue & Src , SDValue & SrcMods ) const { unsigned Mods = <NUM_LIT> ; SelectVOP3PMadMixModsImpl ( In , Src , Mods ) ; SrcMods = CurDAG -> getTargetConstant ( Mods , SDLoc ( In ) , <STR_LIT> ) ;


<s> Src = Src . getOperand ( <NUM_LIT> ) ; assert ( Src . getValueType ( ) == <STR_LIT> ) ; Src = stripBitcast ( Src ) ; if ( ( Mods & <STR_LIT> ) == <NUM_LIT> ) { unsigned ModsTmp ; SelectVOP3ModsImpl ( Src , Src , ModsTmp ) ; if ( ( ModsTmp & <STR_LIT> ) != <NUM_LIT> ) Mods ^= <STR_LIT> ; if ( ( ModsTmp & <STR_LIT> ) != <NUM_LIT> ) Mods |= <STR_LIT> ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectVOP3PMods0 ( SDValue In , SDValue & Src , SDValue & SrcMods , SDValue & Clamp ) const { SDLoc SL ( In ) ;

Clamp = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ;


<s> return Val . getOpcode ( ) == <STR_LIT> ? Val . getOperand ( <NUM_LIT> ) : Val ;


<s> if ( Src . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> ) return stripBitcast ( Src ) ; }


<s> static SDValue stripExtractLoElt ( SDValue In ) { if ( In . getOpcode ( ) == <STR_LIT> ) {

SDValue Src = In . getOperand ( <NUM_LIT> ) ;


<s> for ( SDNode * U : DAG . getEntryNode ( ) . getNode ( ) -> uses ( ) ) { if ( LoadSDNode * L = dyn_cast < LoadSDNode > ( U ) ) { if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( L -> getBasePtr ( ) ) ) { if ( FI -> getIndex ( ) < <NUM_LIT> ) { int64_t InFirstByte = MFI . getObjectOffset ( FI -> getIndex ( ) ) ; int64_t InLastByte = InFirstByte ;

InLastByte += MFI . getObjectSize ( FI -> getIndex ( ) ) - <NUM_LIT> ;


<s> if ( ! hasSourceMods ( U ) ) return false ; if ( ! opMustUseVOP3Encoding ( U , VT ) ) { if ( ++ NumMayIncreaseSize > CostThreshold ) return false ; } }


<s> Align MaxAlign = Align ( <NUM_LIT> ) ; uint64_t ExplicitArgOffset = <NUM_LIT> ; const DataLayout & DL = Fn . getParent ( ) -> getDataLayout ( ) ; unsigned InIndex = <NUM_LIT> ; for ( const Argument & Arg : Fn . args ( ) ) { const bool IsByRef = Arg . hasByRefAttr ( ) ; Type * BaseArgTy = Arg . getType ( ) ; Type * MemArgTy = IsByRef ? Arg . getParamByRefType ( ) : BaseArgTy ; MaybeAlign Alignment = IsByRef ? Arg . getParamAlign ( ) : None ; if ( ! Alignment ) Alignment = DL . getABITypeAlign ( MemArgTy ) ; MaxAlign = max ( Alignment , MaxAlign ) ; uint64_t AllocSize = DL . getTypeAllocSize ( MemArgTy ) ; uint64_t ArgOffset = alignTo ( ExplicitArgOffset , Alignment ) + ExplicitOffset ; ExplicitArgOffset = alignTo ( ExplicitArgOffset , Alignment ) + AllocSize ; SmallVector < EVT , <NUM_LIT> > ValueVTs ; SmallVector < uint64_t , <NUM_LIT> > Offsets ; ComputeValueVTs ( * this , DL , BaseArgTy , ValueVTs , & Offsets , ArgOffset ) ; for ( unsigned Value = <NUM_LIT> , NumValues = ValueVTs . size ( ) ; Value != NumValues ; ++ Value ) { uint64_t BasePartOffset = Offsets [ Value ] ; EVT ArgVT = ValueVTs [ Value ] ; EVT MemVT = ArgVT ; MVT RegisterVT = getRegisterTypeForCallingConv ( Ctx , CC , ArgVT ) ; unsigned NumRegs = getNumRegistersForCallingConv ( Ctx , CC , ArgVT ) ; if ( NumRegs == <NUM_LIT> ) { if ( ArgVT . isExtended ( ) ) { MemVT = RegisterVT ; } else { MemVT = ArgVT ; } } else if ( ArgVT . isVector ( ) && RegisterVT . isVector ( ) && ArgVT . getScalarType ( ) == RegisterVT . getScalarType ( ) ) { assert ( ArgVT . getVectorNumElements ( ) > RegisterVT . getVectorNumElements ( ) ) ; MemVT = RegisterVT ; } else if ( ArgVT . isVector ( ) && ArgVT . getVectorNumElements ( ) == NumRegs ) { MemVT = ArgVT . getScalarType ( ) ; } else if ( ArgVT . isExtended ( ) ) { MemVT = RegisterVT ; } else { unsigned MemoryBits = ArgVT . getStoreSizeInBits ( ) / NumRegs ; assert ( ArgVT . getStoreSizeInBits ( ) % NumRegs == <NUM_LIT> ) ; if ( RegisterVT . isInteger ( ) ) { MemVT = EVT :: getIntegerVT ( State . getContext ( ) , MemoryBits ) ; } else if ( RegisterVT . isVector ( ) ) { assert ( ! RegisterVT . getScalarType ( ) . isFloatingPoint ( ) ) ; unsigned NumElements = RegisterVT . getVectorNumElements ( ) ; assert ( MemoryBits % NumElements == <NUM_LIT> ) ; EVT ScalarVT = EVT :: getIntegerVT ( State . getContext ( ) , MemoryBits / NumElements ) ; MemVT = EVT :: getVectorVT ( State . getContext ( ) , ScalarVT , NumElements ) ;


<s> return <ISA_LIT>CallLowering :: CCAssignFnForCall ( CC , IsVarArg ) ;


<s> if ( LHS == True ) return DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS ) ; return DAG . getNode ( <STR_LIT> , DL , VT , RHS , LHS ) ; } case <STR_LIT> : case <STR_LIT> : { if ( LHS == True ) return DAG . getNode ( <STR_LIT> , DL , VT , RHS , LHS ) ; return DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG && ! DCI . isCalledByLegalizer ( ) ) return SDValue ( ) ;


<s> case <STR_LIT> : { ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; return Width ? <NUM_LIT> - ( Width -> getZExtValue ( ) & <NUM_LIT> ) : <NUM_LIT> ; } case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; default :


<s> static SDValue constantFoldBFE ( SelectionDAG & DAG , IntTy Src0 , uint32_t Offset , uint32_t Width , const SDLoc & DL ) { if ( Width + Offset < <NUM_LIT> ) { uint32_t Shl = static_cast < uint32_t > ( Src0 ) << ( <NUM_LIT> - Offset - Width ) ; IntTy Result = static_cast < IntTy > ( Shl ) >> ( <NUM_LIT> - Width ) ; return DAG . getConstant ( Result , DL , <STR_LIT> ) ; } return DAG . getConstant ( Src0 >> Offset , DL , <STR_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: CreateLiveInRegister ( SelectionDAG & DAG , const TargetRegisterClass * RC , Register Reg , EVT VT , const SDLoc & SL , bool RawReg ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ;

MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


SDValue NewSelect = DAG . getNode ( <STR_LIT> , SL , VT , Cond , N1 . getOperand ( <NUM_LIT> ) , N2 . getOperand ( <NUM_LIT> ) ) ;


<s> static SDValue extractF64Exponent ( SDValue Hi , const SDLoc & SL , SelectionDAG & DAG ) { const unsigned FractBits = <NUM_LIT> ; const unsigned ExpBits = <NUM_LIT> ; SDValue ExpPart = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi , DAG . getConstant ( FractBits - <NUM_LIT> , SL , <STR_LIT> ) , DAG . getConstant ( ExpBits , SL , <STR_LIT> ) ) ;

SDValue Exp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , ExpPart , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default :


<s> if ( ( LHS . getOpcode ( ) == <STR_LIT> && RHS . getOpcode ( ) == <STR_LIT> ) || ( LHS . getOpcode ( ) == <STR_LIT> && RHS . getOpcode ( ) == <STR_LIT> ) ) { return distributeOpThroughSelect ( DCI , LHS . getOpcode ( ) , SDLoc ( N ) , Cond , LHS , RHS ) ; } bool Inv = false ; if ( RHS . getOpcode ( ) == <STR_LIT> || RHS . getOpcode ( ) == <STR_LIT> ) { std :: swap ( LHS , RHS ) ; Inv = true ; } ConstantFPSDNode * CRHS = dyn_cast < ConstantFPSDNode > ( RHS ) ; if ( ( LHS . getOpcode ( ) == <STR_LIT> || LHS . getOpcode ( ) == <STR_LIT> ) && CRHS ) { SDLoc SL ( N ) ; SDValue NewLHS = LHS . getOperand ( <NUM_LIT> ) ; SDValue NewRHS = RHS ; bool ShouldFoldNeg = true ; if ( NewLHS . hasOneUse ( ) ) { unsigned Opc = NewLHS . getOpcode ( ) ; if ( LHS . getOpcode ( ) == <STR_LIT> && fnegFoldsIntoOp ( Opc ) ) ShouldFoldNeg = false ; if ( LHS . getOpcode ( ) == <STR_LIT> && Opc == <STR_LIT> ) ShouldFoldNeg = false ; } if ( ShouldFoldNeg ) { if ( LHS . getOpcode ( ) == <STR_LIT> ) NewRHS = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; else if ( CRHS -> isNegative ( ) ) return SDValue ( ) ; if ( Inv ) std :: swap ( NewLHS , NewRHS ) ; SDValue NewSelect = DAG . getNode ( <STR_LIT> , SL , VT , Cond , NewLHS , NewRHS ) ; DCI . AddToWorklist ( NewSelect . getNode ( ) ) ; return DAG . getNode ( LHS . getOpcode ( ) , SL , VT , NewSelect ) ; }


<s> SDValue <ISA_LIT>TargetLowering :: getFFBX_U32 ( SelectionDAG & DAG , SDValue Op , const SDLoc & DL , unsigned Opc ) const { EVT VT = Op . getValueType ( ) ; EVT LegalVT = getTypeToTransformTo ( * DAG . getContext ( ) , VT ) ; if ( LegalVT != <STR_LIT> && ( Subtarget -> has16BitInsts ( ) && LegalVT != <STR_LIT> ) ) return SDValue ( ) ;

if ( VT != <STR_LIT> ) Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ;


<s> SDValue <ISA_LIT>TargetLowering :: getHiHalf64 ( SDValue Op , SelectionDAG & DAG ) const { SDLoc SL ( Op ) ;

SDValue Vec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Op ) ;


<s> SDValue <ISA_LIT>TargetLowering :: getLoHalf64 ( SDValue Op , SelectionDAG & DAG ) const { SDLoc SL ( Op ) ; SDValue Vec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Op ) ;

const SDValue Zero = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ;


<s> SDValue Vec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Op ) ; const SDValue Zero = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Vec , Zero ) ;


<s> if ( Size <= <NUM_LIT> ) { unsigned MulOpc = Signed ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( MulOpc , SL , <STR_LIT> , N0 , N1 ) ; } unsigned MulLoOpc = Signed ? <STR_LIT> : <STR_LIT> ; unsigned MulHiOpc = Signed ? <STR_LIT> : <STR_LIT> ; SDValue MulLo = DAG . getNode ( MulLoOpc , SL , <STR_LIT> , N0 , N1 ) ; SDValue MulHi = DAG . getNode ( MulHiOpc , SL , <STR_LIT> , N0 , N1 ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , MulLo , MulHi ) ;


<s> static SDValue getMul24 ( SelectionDAG & DAG , const SDLoc & SL , SDValue N0 , SDValue N1 , unsigned Size , bool Signed ) { if ( Size <= <NUM_LIT> ) { unsigned MulOpc = Signed ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( MulOpc , SL , <STR_LIT> , N0 , N1 ) ; } unsigned MulLoOpc = Signed ? <STR_LIT> : <STR_LIT> ; unsigned MulHiOpc = Signed ? <STR_LIT> : <STR_LIT> ; SDValue MulLo = DAG . getNode ( MulLoOpc , SL , <STR_LIT> , N0 , N1 ) ; SDValue MulHi = DAG . getNode ( MulHiOpc , SL , <STR_LIT> , N0 , N1 ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , MulLo , MulHi ) ;


<s> SDValue <ISA_LIT>TargetLowering :: getNegatedExpression ( SDValue Op , SelectionDAG & DAG , bool LegalOperations , bool ForCodeSize , NegatibleCost & Cost , unsigned Depth ) const { switch ( Op . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : { if ( ! allUsesHaveSourceMods ( Op . getNode ( ) ) ) return SDValue ( ) ; break ; } default : break ; }

return TargetLowering :: getNegatedExpression ( Op , DAG , LegalOperations , ForCodeSize , Cost , Depth ) ;


<s> static int getOrCreateFixedStackObject ( MachineFrameInfo & MFI , unsigned Size , int64_t Offset ) { for ( int I = MFI . getObjectIndexBegin ( ) ; I < <NUM_LIT> ; ++ I ) { if ( MFI . getObjectOffset ( I ) == Offset ) { assert ( MFI . getObjectSize ( I ) == Size ) ; return I ; } } return MFI . CreateFixedObject ( Size , Offset , true ) ;


<s> if ( MFI . getObjectOffset ( I ) == Offset ) {

assert ( MFI . getObjectSize ( I ) == Size ) ;


<s> RefinementSteps = <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , SDLoc ( Operand ) , VT , Operand ) ; } return SDValue ( ) ;


<s> EVT LoVT , HiVT ; EVT EltVT = VT . getVectorElementType ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned LoNumElts = PowerOf2Ceil ( ( NumElts + <NUM_LIT> ) / <NUM_LIT> ) ; LoVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , LoNumElts ) ; HiVT = NumElts - LoNumElts == <NUM_LIT> ? EltVT : EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumElts - LoNumElts ) ;

return std :: make_pair ( LoVT , HiVT ) ;


<s> EVT VT = Operand . getValueType ( ) ; if ( VT == <STR_LIT> ) { RefinementSteps = <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , SDLoc ( Operand ) , VT , Operand ) ; } return SDValue ( ) ;


<s> if ( Size <= <NUM_LIT> ) return <STR_LIT> ; return EVT :: getIntegerVT ( Context , <NUM_LIT> * ( ( Size + <NUM_LIT> ) / <NUM_LIT> ) ) ;


<s> if ( Size <= <NUM_LIT> ) return <STR_LIT> ;

return EVT :: getIntegerVT ( Context , <NUM_LIT> * ( ( Size + <NUM_LIT> ) / <NUM_LIT> ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; case <STR_LIT> : { switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; default : return true ;


<s> if ( M -> isVolatile ( ) ) return true ; } } return false ;


<s> for ( SDNode * U : Val -> uses ( ) ) { if ( MemSDNode * M = dyn_cast < MemSDNode > ( U ) ) { if ( M -> isVolatile ( ) ) return true ; } } return false ;


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> if ( const ConstantFPSDNode * C = isConstOrConstSplatFP ( N ) ) { if ( C -> isZero ( ) && ! C -> isNegative ( ) ) return true ;

if ( Subtarget -> hasInv2PiInlineImm ( ) && isInv2Pi ( C -> getValueAPF ( ) ) ) return true ;


<s> bool <ISA_LIT>TargetLowering :: isConstantUnsignedBitfieldExtractLegal ( unsigned Opc , LLT Ty1 , LLT Ty2 ) const { return ( Ty1 == LLT :: scalar ( <NUM_LIT> ) || Ty1 == LLT :: scalar ( <NUM_LIT> ) ) && Ty2 == LLT :: scalar ( <NUM_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: isFAbsFree ( EVT VT ) const { assert ( VT . isFloatingPoint ( ) ) ; return VT == <STR_LIT> || VT == <STR_LIT> || ( Subtarget -> has16BitInsts ( ) && VT == <STR_LIT> ) ;


<s> return VT == <STR_LIT> || VT == <STR_LIT> || ( Subtarget -> has16BitInsts ( ) && VT == <STR_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: isFNegFree ( EVT VT ) const { assert ( VT . isFloatingPoint ( ) ) ; VT = VT . getScalarType ( ) ;

return VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ;


<s> EVT ScalarVT = VT . getScalarType ( ) ; return ( ScalarVT == <STR_LIT> || ScalarVT == <STR_LIT> || ( ScalarVT == <STR_LIT> && Subtarget -> has16BitInsts ( ) ) ) ;


<s> static bool isI24 ( SDValue Op , SelectionDAG & DAG ) { EVT VT = Op . getValueType ( ) ;

return VT . getSizeInBits ( ) >= <NUM_LIT> && <ISA_LIT>TargetLowering :: numBitsSigned ( Op , DAG ) <= <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) && DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) && DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return false ; } case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SNaN ; case <STR_LIT> : case <STR_LIT> : { return SNaN ; } case <STR_LIT> : { unsigned IntrinsicID = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntrinsicID ) { case <STR_LIT> : return true ; case <STR_LIT> : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ; } case <STR_LIT> : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) && DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return false ; } case <STR_LIT> : case <STR_LIT> : return SNaN ; case <STR_LIT> : if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) && DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) && DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ; default : return false ;


<s> assert ( LoadTy . getSizeInBits ( ) == CastTy . getSizeInBits ( ) ) ; if ( LoadTy . getScalarType ( ) == <STR_LIT> ) return false ; unsigned LScalarSize = LoadTy . getScalarSizeInBits ( ) ;

unsigned CastScalarSize = CastTy . getScalarSizeInBits ( ) ;


<s> static bool isNegativeOne ( SDValue Val ) {

if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Val ) ) return C -> isAllOnes ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : return true ; } return false ; } case <STR_LIT> :

if ( cast < LoadSDNode > ( N ) -> getMemOperand ( ) -> getAddrSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) return true ;


<s> return true ; } return false ; } case <STR_LIT> : if ( cast < LoadSDNode > ( N ) -> getMemOperand ( ) -> getAddrSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) return true ; return false ;


<s> if ( DestSize == <NUM_LIT> && Subtarget -> has16BitInsts ( ) ) return SrcSize >= <NUM_LIT> ;

return DestSize < SrcSize && DestSize % <NUM_LIT> == <NUM_LIT> ;


<s> unsigned SrcSize = Source -> getScalarSizeInBits ( ) ; unsigned DestSize = Dest -> getScalarSizeInBits ( ) ; if ( DestSize == <NUM_LIT> && Subtarget -> has16BitInsts ( ) ) return SrcSize >= <NUM_LIT> ; return DestSize < SrcSize && DestSize % <NUM_LIT> == <NUM_LIT> ;


<s> return <ISA_LIT>TargetLowering :: numBitsUnsigned ( Op , DAG ) <= <NUM_LIT> ;


<s> if ( Src == <STR_LIT> ) return Dest == <STR_LIT> || Dest == <STR_LIT> ;

return Src == <STR_LIT> && Dest == <STR_LIT> ;


<s> bool <ISA_LIT>TargetLowering :: isZExtFree ( EVT Src , EVT Dest ) const { if ( Src == <STR_LIT> ) return Dest == <STR_LIT> || Dest == <STR_LIT> ;


<s> SDValue V = Arg . isRegister ( ) ? CreateLiveInRegister ( DAG , RC , Arg . getRegister ( ) , VT , SL ) : loadStackInputValue ( DAG , VT , SL , Arg . getStackOffset ( ) ) ; if ( ! Arg . isMasked ( ) ) return V ; unsigned Mask = Arg . getMask ( ) ; unsigned Shift = countTrailingZeros < unsigned > ( Mask ) ; V = DAG . getNode ( <STR_LIT> , SL , VT , V , DAG . getShiftAmountConstant ( Shift , VT , SL ) ) ; return DAG . getNode ( <STR_LIT> , SL , VT , V , DAG . getConstant ( Mask >> Shift , SL , VT ) ) ;


<s> SDValue V = Arg . isRegister ( ) ? CreateLiveInRegister ( DAG , RC , Arg . getRegister ( ) , VT , SL ) : loadStackInputValue ( DAG , VT , SL , Arg . getStackOffset ( ) ) ; if ( ! Arg . isMasked ( ) ) return V ; unsigned Mask = Arg . getMask ( ) ;

unsigned Shift = countTrailingZeros < unsigned > ( Mask ) ;


<s> SDValue <ISA_LIT>TargetLowering :: loadStackInputValue ( SelectionDAG & DAG , EVT VT , const SDLoc & SL , int64_t Offset ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;

int FI = getOrCreateFixedStackObject ( MFI , VT . getStoreSize ( ) , Offset ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerCall ( CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { return lowerUnhandledCall ( CLI , InVals , <STR_LIT> ) ;


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue BV = DAG . getBuildVector ( <STR_LIT> , SL , { Lo , Hi } ) ; return DAG . getNode ( <STR_LIT> , SL , VT , BV ) ; } for ( const SDUse & U : Op -> ops ( ) ) DAG . ExtractVectorElements ( U . get ( ) , Args ) ;

return DAG . getBuildVector ( Op . getValueType ( ) , SDLoc ( Op ) , Args ) ;


<s> SDLoc SL ( Op ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue BV = DAG . getBuildVector ( <STR_LIT> , SL , { Lo , Hi } ) ;

return DAG . getNode ( <STR_LIT> , SL , VT , BV ) ;


<s> unsigned NewOpc = Ctlz ? <STR_LIT> : <STR_LIT> ; bool ZeroUndef = Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ; if ( Src . getValueType ( ) == <STR_LIT> ) { SDValue NewOpr = DAG . getNode ( NewOpc , SL , <STR_LIT> , Src ) ; if ( ! ZeroUndef ) { const SDValue Const32 = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; NewOpr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NewOpr , Const32 ) ; } return NewOpr ; } SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = split64BitValue ( Src , DAG ) ; SDValue OprLo = DAG . getNode ( NewOpc , SL , <STR_LIT> , Lo ) ; SDValue OprHi = DAG . getNode ( NewOpc , SL , <STR_LIT> , Hi ) ; unsigned AddOpc = ZeroUndef ? <STR_LIT> : <STR_LIT> ; const SDValue Const32 = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; if ( Ctlz ) OprLo = DAG . getNode ( AddOpc , SL , <STR_LIT> , OprLo , Const32 ) ; else OprHi = DAG . getNode ( AddOpc , SL , <STR_LIT> , OprHi , Const32 ) ; SDValue NewOpr ; NewOpr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , OprLo , OprHi ) ;


<s> SDValue ia = LHS ; SDValue ib = RHS ; SDValue fa = DAG . getNode ( ToFp , DL , FltVT , ia ) ; SDValue fb = DAG . getNode ( ToFp , DL , FltVT , ib ) ; SDValue fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fa , DAG . getNode ( <STR_LIT> , DL , FltVT , fb ) ) ; fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ; SDValue fqneg = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>MachineFunction * MFI = MF . getInfo < <ISA_LIT>MachineFunction > ( ) ; unsigned OpCode = ! Subtarget -> hasMadMacF32Insts ( ) ? ( unsigned ) <STR_LIT> : ! MFI -> getMode ( ) . allFP32Denormals ( ) ? ( unsigned ) <STR_LIT> : ( unsigned ) <STR_LIT> ; SDValue fr = DAG . getNode ( OpCode , DL , FltVT , fqneg , fb , fa ) ; SDValue iq = DAG . getNode ( ToInt , DL , IntVT , fq ) ; fr = DAG . getNode ( <STR_LIT> , DL , FltVT , fr ) ; fb = DAG . getNode ( <STR_LIT> , DL , FltVT , fb ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue cv = DAG . getSetCC ( DL , SetCCVT , fr , fb , <STR_LIT> ) ; jq = DAG . getNode ( <STR_LIT> , DL , VT , cv , jq , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Div = DAG . getNode ( <STR_LIT> , DL , VT , iq , jq ) ; SDValue Rem = DAG . getNode ( <STR_LIT> , DL , VT , Div , RHS ) ; Rem = DAG . getNode ( <STR_LIT> , DL , VT , LHS , Rem ) ; if ( Sign ) { SDValue InRegSize = DAG . getValueType ( EVT :: getIntegerVT ( * DAG . getContext ( ) , DivBits ) ) ; Div = DAG . getNode ( <STR_LIT> , DL , VT , Div , InRegSize ) ; Rem = DAG . getNode ( <STR_LIT> , DL , VT , Rem , InRegSize ) ; } else { SDValue TruncMask = DAG . getConstant ( ( UINT64_C ( <NUM_LIT> ) << DivBits ) - <NUM_LIT> , DL , VT ) ; Div = DAG . getNode ( <STR_LIT> , DL , VT , Div , TruncMask ) ; Rem = DAG . getNode ( <STR_LIT> , DL , VT , Rem , TruncMask ) ; }

return DAG . getMergeValues ( { Div , Rem } , DL ) ;


<s> auto Ops = { DAG . getConstant ( <NUM_LIT> , SDLoc ( ) , Op . getValueType ( ) ) , Op . getOperand ( <NUM_LIT> ) } ; return DAG . getMergeValues ( Ops , SDLoc ( ) ) ;


<s> SmallVector < SDValue , <NUM_LIT> > Args ; unsigned Start = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Op . getValueType ( ) ; EVT SrcVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ( ( SrcVT == <STR_LIT> && VT == <STR_LIT> ) || ( SrcVT == <STR_LIT> && VT == <STR_LIT> ) ) && Start != <NUM_LIT> ) return Op ; if ( ( ( SrcVT == <STR_LIT> && VT == <STR_LIT> ) || ( SrcVT == <STR_LIT> && VT == <STR_LIT> ) ) && ( Start == <NUM_LIT> || Start == <NUM_LIT> ) ) return Op ; DAG . ExtractVectorElements ( Op . getOperand ( <NUM_LIT> ) , Args , Start , VT . getVectorNumElements ( ) ) ;


<s> SmallVector < SDValue , <NUM_LIT> > Args ; unsigned Start = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Op . getValueType ( ) ; EVT SrcVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ;

if ( ( ( SrcVT == <STR_LIT> && VT == <STR_LIT> ) || ( SrcVT == <STR_LIT> && VT == <STR_LIT> ) ) && Start != <NUM_LIT> ) return Op ;


<s> SDLoc SL ( Op ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; const SDValue K = DAG . getConstantFP ( numbers :: log2e , SL , VT ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , SL , VT , Src , K , Op -> getFlags ( ) ) ; return DAG . getNode ( <STR_LIT> , SL , VT , Mul , Op -> getFlags ( ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFLOG ( SDValue Op , SelectionDAG & DAG , double Log2BaseInverted ) const { EVT VT = Op . getValueType ( ) ;


<s> M = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , M , Lo40Set ) ; SDValue I = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getSelectCC ( DL , M , Zero , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Zero , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue N = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , M , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , E , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ; SDValue OneSubExp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , One , E ) ; SDValue B = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OneSubExp , Zero ) ; B = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , B , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SigSetHigh = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , M , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue D = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SigSetHigh , B ) ; SDValue D0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , D , B ) ; SDValue D1 = DAG . getSelectCC ( DL , D0 , SigSetHigh , One , Zero , <STR_LIT> ) ; D = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , D , D1 ) ; SDValue V = DAG . getSelectCC ( DL , E , One , D , N , <STR_LIT> ) ; SDValue VLow3 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue V0 = DAG . getSelectCC ( DL , VLow3 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , One , Zero , <STR_LIT> ) ; SDValue V1 = DAG . getSelectCC ( DL , VLow3 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , One , Zero , <STR_LIT> ) ; V1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V0 , V1 ) ; V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V , V1 ) ;

V = DAG . getSelectCC ( DL , E , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , V , <STR_LIT> ) ;


<s> } if ( SrcVT == <STR_LIT> || ( SrcVT == <STR_LIT> && Src . getOpcode ( ) == <STR_LIT> ) ) { SDLoc DL ( Op ) ; SDValue FpToInt32 = DAG . getNode ( OpOpcode , DL , <STR_LIT> , Src ) ; unsigned Ext = OpOpcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Ext , DL , <STR_LIT> , FpToInt32 ) ; } if ( DestVT == <STR_LIT> && ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) ) return LowerFP_TO_INT64 ( Op , DAG , OpOpcode == <STR_LIT> ) ;