<s> SDValue MulLHS = LHS . getOperand ( <NUM_LIT> ) ; SDValue MulRHS = LHS . getOperand ( <NUM_LIT> ) ; SDValue AddRHS = RHS ; if ( numBitsUnsigned ( MulLHS , DAG ) <= <NUM_LIT> && numBitsUnsigned ( MulRHS , DAG ) <= <NUM_LIT> ) { MulLHS = DAG . getZExtOrTrunc ( MulLHS , SL , <STR_LIT> ) ; MulRHS = DAG . getZExtOrTrunc ( MulRHS , SL , <STR_LIT> ) ; AddRHS = DAG . getZExtOrTrunc ( AddRHS , SL , <STR_LIT> ) ; return getMad64_32 ( DAG , SL , VT , MulLHS , MulRHS , AddRHS , false ) ; } if ( numBitsSigned ( MulLHS , DAG ) <= <NUM_LIT> && numBitsSigned ( MulRHS , DAG ) <= <NUM_LIT> ) { MulLHS = DAG . getSExtOrTrunc ( MulLHS , SL , <STR_LIT> ) ; MulRHS = DAG . getSExtOrTrunc ( MulRHS , SL , <STR_LIT> ) ; AddRHS = DAG . getSExtOrTrunc ( AddRHS , SL , <STR_LIT> ) ; return getMad64_32 ( DAG , SL , VT , MulLHS , MulRHS , AddRHS , true ) ; } return SDValue ( ) ; } if ( SDValue V = reassociateScalarOps ( N , DAG ) ) { return V ; } if ( VT != <STR_LIT> || ! DCI . isAfterLegalizeDAG ( ) ) return SDValue ( ) ; unsigned Opc = LHS . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) std :: swap ( RHS , LHS ) ; Opc = RHS . getOpcode ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { auto Cond = RHS . getOperand ( <NUM_LIT> ) ; if ( ! isBoolSGPR ( Cond ) ) break ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Args [ ] = { LHS , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) , Cond } ; Opc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , SL , VTList , Args ) ; } case <STR_LIT> : { auto C = dyn_cast < ConstantSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) ; if ( ! C || C -> getZExtValue ( ) != <NUM_LIT> ) break ;

SDValue Args [ ] = { LHS , RHS . getOperand ( <NUM_LIT> ) , RHS . getOperand ( <NUM_LIT> ) } ;


<s> const ConstantFPSDNode * C1 = dyn_cast < ConstantFPSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) ; if ( ! C1 || ! C1 -> isInfinity ( ) || C1 -> isNegative ( ) ) return SDValue ( ) ; const uint32_t Mask = <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> ; static_assert ( ( ( ~ ( <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> ) ) & <NUM_LIT> ) == Mask , <STR_LIT> ) ; SDLoc DL ( N ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X , DAG . getConstant ( Mask , DL , <STR_LIT> ) ) ; } } } if ( RHS . getOpcode ( ) == <STR_LIT> && LHS . getOpcode ( ) == <STR_LIT> ) std :: swap ( LHS , RHS ) ; if ( LHS . getOpcode ( ) == <STR_LIT> && RHS . getOpcode ( ) == <STR_LIT> && RHS . hasOneUse ( ) ) { <STR_LIT> LCC = cast < CondCodeSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) -> get ( ) ; const ConstantSDNode * Mask = dyn_cast < ConstantSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) ; if ( ( LCC == <STR_LIT> || LCC == <STR_LIT> ) && Mask && ( RHS . getOperand ( <NUM_LIT> ) == LHS . getOperand ( <NUM_LIT> ) && LHS . getOperand ( <NUM_LIT> ) == LHS . getOperand ( <NUM_LIT> ) ) ) { const unsigned OrdMask = <STR_LIT> | <STR_LIT> ; unsigned NewMask = LCC == <STR_LIT> ? Mask -> getZExtValue ( ) & ~ OrdMask : Mask -> getZExtValue ( ) & OrdMask ; SDLoc DL ( N ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RHS . getOperand ( <NUM_LIT> ) , DAG . getConstant ( NewMask , DL , <STR_LIT> ) ) ; } } if ( VT == <STR_LIT> && ( RHS . getOpcode ( ) == <STR_LIT> || LHS . getOpcode ( ) == <STR_LIT> ) ) { if ( RHS . getOpcode ( ) != <STR_LIT> ) std :: swap ( LHS , RHS ) ; if ( isBoolSGPR ( RHS . getOperand ( <NUM_LIT> ) ) ) return DAG . getSelect ( SDLoc ( N ) , <STR_LIT> , RHS . getOperand ( <NUM_LIT> ) , LHS , DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ) ; } const <ISA_LIT>InstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; if ( VT == <STR_LIT> && LHS . hasOneUse ( ) && RHS . hasOneUse ( ) && N -> isDivergent ( ) && TII -> pseudoToMCOpcode ( <STR_LIT> ) != - <NUM_LIT> ) {

uint32_t LHSMask = getPermuteMask ( DAG , LHS ) ;


<s> if ( F < Zero || ( F . isNaN ( ) && MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMode ( ) . DX10Clamp ) ) { return DCI . DAG . getConstantFP ( Zero , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; } APFloat One ( F . getSemantics ( ) , <STR_LIT> ) ; if ( F > One ) return DCI . DAG . getConstantFP ( One , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; return SDValue ( CSrc , <NUM_LIT> ) ;


<s> SelectionDAG & DAG = DCI . DAG ; SDValue Mask = N -> getOperand ( <NUM_LIT> ) ; if ( const ConstantSDNode * CMask = dyn_cast < ConstantSDNode > ( Mask ) ) { if ( CMask -> isZero ( ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ;


<s> SDValue Mask = N -> getOperand ( <NUM_LIT> ) ; if ( const ConstantSDNode * CMask = dyn_cast < ConstantSDNode > ( Mask ) ) {

if ( CMask -> isZero ( ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ;


<s> SDValue Shift = N -> getOperand ( <NUM_LIT> ) ; if ( Shift . getOpcode ( ) == <STR_LIT> ) Shift = Shift . getOperand ( <NUM_LIT> ) ; if ( Shift . getOpcode ( ) == <STR_LIT> || Shift . getOpcode ( ) == <STR_LIT> ) { if ( auto * C = dyn_cast < ConstantSDNode > ( Shift . getOperand ( <NUM_LIT> ) ) ) { SDValue Shifted = DAG . getZExtOrTrunc ( Shift . getOperand ( <NUM_LIT> ) , SDLoc ( Shift . getOperand ( <NUM_LIT> ) ) , <STR_LIT> ) ; unsigned ShiftOffset = <NUM_LIT> * Offset ; if ( Shift . getOpcode ( ) == <STR_LIT> ) ShiftOffset -= C -> getZExtValue ( ) ;

else ShiftOffset += C -> getZExtValue ( ) ;


<s> case <STR_LIT> : return performAddCarrySubCarryCombine ( N , DCI ) ; case <STR_LIT> : return performFAddCombine ( N , DCI ) ; case <STR_LIT> : return performFSubCombine ( N , DCI ) ; case <STR_LIT> : return performSetCCCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performMinMaxCombine ( N , DCI ) ; case <STR_LIT> : return performFMACombine ( N , DCI ) ; case <STR_LIT> : return performAndCombine ( N , DCI ) ; case <STR_LIT> : return performOrCombine ( N , DCI ) ; case <STR_LIT> : return performXorCombine ( N , DCI ) ; case <STR_LIT> : return performZeroExtendCombine ( N , DCI ) ; case <STR_LIT> : return performSignExtendInRegCombine ( N , DCI ) ; case <STR_LIT> : return performClassCombine ( N , DCI ) ; case <STR_LIT> : return performFCanonicalizeCombine ( N , DCI ) ; case <STR_LIT> : return performRcpCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . isUndef ( ) ) return Src ; break ; } case <STR_LIT> : case <STR_LIT> : return performUCharToFloatCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performCvtF32UByteNCombine ( N , DCI ) ; case <STR_LIT> : return performFMed3Combine ( N , DCI ) ; case <STR_LIT> : return performCvtPkRTZCombine ( N , DCI ) ; case <STR_LIT> : return performClampCombine ( N , DCI ) ; case <STR_LIT> : { SelectionDAG & DAG = DCI . DAG ;

EVT VT = N -> getValueType ( <NUM_LIT> ) ;


<s> SelectionDAG & DAG = DCI . DAG ; EVT VecVT = Vec . getValueType ( ) ; EVT EltVT = VecVT . getVectorElementType ( ) ; if ( ( Vec . getOpcode ( ) == <STR_LIT> || Vec . getOpcode ( ) == <STR_LIT> ) && allUsesHaveSourceMods ( N ) ) { SDLoc SL ( N ) ; EVT EltVT = N -> getValueType ( <NUM_LIT> ) ; SDValue Idx = N -> getOperand ( <NUM_LIT> ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , SL , EltVT , Vec . getOperand ( <NUM_LIT> ) , Idx ) ; return DAG . getNode ( Vec . getOpcode ( ) , SL , EltVT , Elt ) ; } if ( Vec . hasOneUse ( ) && DCI . isBeforeLegalize ( ) ) { SDLoc SL ( N ) ; EVT EltVT = N -> getValueType ( <NUM_LIT> ) ; SDValue Idx = N -> getOperand ( <NUM_LIT> ) ; unsigned Opc = Vec . getOpcode ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Elt0 = DAG . getNode ( <STR_LIT> , SL , EltVT , Vec . getOperand ( <NUM_LIT> ) , Idx ) ; SDValue Elt1 = DAG . getNode ( <STR_LIT> , SL , EltVT , Vec . getOperand ( <NUM_LIT> ) , Idx ) ; DCI . AddToWorklist ( Elt0 . getNode ( ) ) ; DCI . AddToWorklist ( Elt1 . getNode ( ) ) ; return DAG . getNode ( Opc , SL , EltVT , Elt0 , Elt1 , Vec -> getFlags ( ) ) ;


<s> SDValue Elt = DAG . getNode ( <STR_LIT> , SL , EltVT , Vec . getOperand ( <NUM_LIT> ) , Idx ) ; return DAG . getNode ( Vec . getOpcode ( ) , SL , EltVT , Elt ) ; } if ( Vec . hasOneUse ( ) && DCI . isBeforeLegalize ( ) ) { SDLoc SL ( N ) ; EVT EltVT = N -> getValueType ( <NUM_LIT> ) ; SDValue Idx = N -> getOperand ( <NUM_LIT> ) ; unsigned Opc = Vec . getOpcode ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Elt0 = DAG . getNode ( <STR_LIT> , SL , EltVT , Vec . getOperand ( <NUM_LIT> ) , Idx ) ; SDValue Elt1 = DAG . getNode ( <STR_LIT> , SL , EltVT , Vec . getOperand ( <NUM_LIT> ) , Idx ) ; DCI . AddToWorklist ( Elt0 . getNode ( ) ) ; DCI . AddToWorklist ( Elt1 . getNode ( ) ) ; return DAG . getNode ( Opc , SL , EltVT , Elt0 , Elt1 , Vec -> getFlags ( ) ) ; } } } unsigned VecSize = VecVT . getSizeInBits ( ) ; unsigned EltSize = EltVT . getSizeInBits ( ) ; if ( :: shouldExpandVectorDynExt ( N ) ) { SDLoc SL ( N ) ; SDValue Idx = N -> getOperand ( <NUM_LIT> ) ; SDValue V ; for ( unsigned I = <NUM_LIT> , E = VecVT . getVectorNumElements ( ) ; I < E ; ++ I ) { SDValue IC = DAG . getVectorIdxConstant ( I , SL ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , SL , EltVT , Vec , IC ) ; if ( I == <NUM_LIT> ) V = Elt ; else V = DAG . getSelectCC ( SL , Idx , IC , Elt , V , <STR_LIT> ) ;


<s> SDValue Idx1 = Op1 . getOperand ( <NUM_LIT> ) ; SDValue Vec2 = Op2 . getOperand ( <NUM_LIT> ) ; SDValue FMAOp1 = FMA . getOperand ( <NUM_LIT> ) ; SDValue FMAOp2 = FMA . getOperand ( <NUM_LIT> ) ; SDValue FMAAcc = FMA . getOperand ( <NUM_LIT> ) ; if ( FMAOp1 . getOpcode ( ) != <STR_LIT> || FMAOp2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; FMAOp1 = FMAOp1 . getOperand ( <NUM_LIT> ) ; FMAOp2 = FMAOp2 . getOperand ( <NUM_LIT> ) ; if ( FMAOp1 . getOpcode ( ) != <STR_LIT> || FMAOp2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Vec3 = FMAOp1 . getOperand ( <NUM_LIT> ) ; SDValue Vec4 = FMAOp2 . getOperand ( <NUM_LIT> ) ; SDValue Idx2 = FMAOp1 . getOperand ( <NUM_LIT> ) ;

if ( Idx1 != Op2 . getOperand ( <NUM_LIT> ) || Idx2 != FMAOp2 . getOperand ( <NUM_LIT> ) || Idx1 == Idx2 ) return SDValue ( ) ;


<s> if ( FMA . getOpcode ( ) != <STR_LIT> || Op1 . getOpcode ( ) != <STR_LIT> || Op2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; const TargetOptions & Options = DAG . getTarget ( ) . Options ; if ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath || ( N -> getFlags ( ) . hasAllowContract ( ) && FMA -> getFlags ( ) . hasAllowContract ( ) ) ) { Op1 = Op1 . getOperand ( <NUM_LIT> ) ; Op2 = Op2 . getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) != <STR_LIT> || Op2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Vec1 = Op1 . getOperand ( <NUM_LIT> ) ; SDValue Idx1 = Op1 . getOperand ( <NUM_LIT> ) ; SDValue Vec2 = Op2 . getOperand ( <NUM_LIT> ) ; SDValue FMAOp1 = FMA . getOperand ( <NUM_LIT> ) ; SDValue FMAOp2 = FMA . getOperand ( <NUM_LIT> ) ; SDValue FMAAcc = FMA . getOperand ( <NUM_LIT> ) ; if ( FMAOp1 . getOpcode ( ) != <STR_LIT> || FMAOp2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; FMAOp1 = FMAOp1 . getOperand ( <NUM_LIT> ) ; FMAOp2 = FMAOp2 . getOperand ( <NUM_LIT> ) ; if ( FMAOp1 . getOpcode ( ) != <STR_LIT> || FMAOp2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Vec3 = FMAOp1 . getOperand ( <NUM_LIT> ) ; SDValue Vec4 = FMAOp2 . getOperand ( <NUM_LIT> ) ; SDValue Idx2 = FMAOp1 . getOperand ( <NUM_LIT> ) ; if ( Idx1 != Op2 . getOperand ( <NUM_LIT> ) || Idx2 != FMAOp2 . getOperand ( <NUM_LIT> ) || Idx1 == Idx2 ) return SDValue ( ) ; if ( Vec1 == Vec2 || Vec3 == Vec4 ) return SDValue ( ) ; if ( Vec1 . getValueType ( ) != <STR_LIT> || Vec2 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ( Vec1 == Vec3 && Vec2 == Vec4 ) || ( Vec1 == Vec4 && Vec2 == Vec3 ) ) { return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Vec1 , Vec2 , FMAAcc , DAG . getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ;


<s> ConstantFPSDNode * K0 = getSplatConstantFP ( Op0 . getOperand ( <NUM_LIT> ) ) ; if ( ! K0 ) return SDValue ( ) ; if ( K0 -> getValueAPF ( ) > K1 -> getValueAPF ( ) ) return SDValue ( ) ; const MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; EVT VT = Op0 . getValueType ( ) ; if ( Info -> getMode ( ) . DX10Clamp ) { if ( K1 -> isExactlyValue ( <NUM_LIT> ) && K0 -> isExactlyValue ( <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , SL , VT , Op0 . getOperand ( <NUM_LIT> ) ) ;


<s> SDValue Ins = N -> getOperand ( <NUM_LIT> ) ; EVT IdxVT = Idx . getValueType ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned I = <NUM_LIT> , E = VecVT . getVectorNumElements ( ) ; I < E ; ++ I ) { SDValue IC = DAG . getConstant ( I , SL , IdxVT ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , SL , EltVT , Vec , IC ) ; SDValue V = DAG . getSelectCC ( SL , Idx , IC , Ins , Elt , <STR_LIT> ) ; Ops . push_back ( V ) ; }

return DAG . getBuildVector ( VecVT , SL , Ops ) ;


<s> if ( Signed ) { if ( K0 -> getAPIntValue ( ) . sge ( K1 -> getAPIntValue ( ) ) ) return SDValue ( ) ; } else { if ( K0 -> getAPIntValue ( ) . uge ( K1 -> getAPIntValue ( ) ) ) return SDValue ( ) ; } EVT VT = K0 -> getValueType ( <NUM_LIT> ) ; unsigned Med3Opc = Signed ? <STR_LIT> : <STR_LIT> ; if ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget -> hasMed3_16 ( ) ) ) { return DAG . getNode ( Med3Opc , SL , VT , Op0 . getOperand ( <NUM_LIT> ) , SDValue ( K0 , <NUM_LIT> ) , SDValue ( K1 , <NUM_LIT> ) ) ; } if ( VT == <STR_LIT> ) { MVT NVT = <STR_LIT> ; unsigned ExtOp = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Tmp1 = DAG . getNode ( ExtOp , SL , NVT , Op0 -> getOperand ( <NUM_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( ExtOp , SL , NVT , Op0 -> getOperand ( <NUM_LIT> ) ) ; SDValue Tmp3 = DAG . getNode ( ExtOp , SL , NVT , Op1 ) ;

SDValue Med3 = DAG . getNode ( Med3Opc , SL , NVT , Tmp1 , Tmp2 , Tmp3 ) ;


<s> SelectionDAG & DAG = DCI . DAG ; SDLoc SL ( N ) ; unsigned PtrIdx = getBasePtrIndex ( N ) ; SDValue Ptr = N -> getOperand ( PtrIdx ) ; if ( Ptr . getOpcode ( ) == <STR_LIT> ) { SDValue NewPtr = performSHLPtrCombine ( Ptr . getNode ( ) , N -> getAddressSpace ( ) , N -> getMemoryVT ( ) , DCI ) ; if ( NewPtr ) { SmallVector < SDValue , <NUM_LIT> > NewOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; NewOps [ PtrIdx ] = NewPtr ;

return SDValue ( DAG . UpdateNodeOperands ( N , NewOps ) , <NUM_LIT> ) ;


<s> if ( Ptr . getOpcode ( ) == <STR_LIT> ) { SDValue NewPtr = performSHLPtrCombine ( Ptr . getNode ( ) , N -> getAddressSpace ( ) , N -> getMemoryVT ( ) , DCI ) ; if ( NewPtr ) { SmallVector < SDValue , <NUM_LIT> > NewOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; NewOps [ PtrIdx ] = NewPtr ; return SDValue ( DAG . UpdateNodeOperands ( N , NewOps ) , <NUM_LIT> ) ; } } return SDValue ( ) ;


<s> } if ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) ) { if ( SDValue Med3 = performIntMed3ImmCombine ( DAG , SDLoc ( N ) , Op0 , Op1 , true ) ) return Med3 ; } if ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) ) { if ( SDValue Med3 = performIntMed3ImmCombine ( DAG , SDLoc ( N ) , Op0 , Op1 , false ) ) return Med3 ; }

if ( ( ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> ) || ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> ) || ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> ) ) && ( VT == <STR_LIT> || VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget -> has16BitInsts ( ) ) || ( VT == <STR_LIT> && Subtarget -> hasVOP3PInsts ( ) ) ) && Op0 . hasOneUse ( ) ) {


<s> if ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) ) { if ( SDValue Med3 = performIntMed3ImmCombine ( DAG , SDLoc ( N ) , Op0 , Op1 , false ) ) return Med3 ; } if ( ( ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> ) || ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> ) || ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> ) ) && ( VT == <STR_LIT> || VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget -> has16BitInsts ( ) ) || ( VT == <STR_LIT> && Subtarget -> hasVOP3PInsts ( ) ) ) && Op0 . hasOneUse ( ) ) {

if ( SDValue Res = performFPMed3ImmCombine ( DAG , SDLoc ( N ) , Op0 , Op1 ) ) return Res ;


<s> if ( Src != RHS . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; const ConstantSDNode * CLHS = dyn_cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) ; const ConstantSDNode * CRHS = dyn_cast < ConstantSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) ; if ( ! CLHS || ! CRHS ) return SDValue ( ) ; static const uint32_t MaxMask = <NUM_LIT> ; uint32_t NewMask = ( CLHS -> getZExtValue ( ) | CRHS -> getZExtValue ( ) ) & MaxMask ; SDLoc DL ( N ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src , DAG . getConstant ( NewMask , DL , <STR_LIT> ) ) ; } return SDValue ( ) ; } if ( isa < ConstantSDNode > ( RHS ) && LHS . hasOneUse ( ) && LHS . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) ) { uint32_t Sel = getConstantPermuteMask ( N -> getConstantOperandVal ( <NUM_LIT> ) ) ; if ( ! Sel ) return SDValue ( ) ; Sel |= LHS . getConstantOperandVal ( <NUM_LIT> ) ; SDLoc DL ( N ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS . getOperand ( <NUM_LIT> ) , LHS . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Sel , DL , <STR_LIT> ) ) ; } const <ISA_LIT>InstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; if ( VT == <STR_LIT> && LHS . hasOneUse ( ) && RHS . hasOneUse ( ) && N -> isDivergent ( ) && TII -> pseudoToMCOpcode ( <STR_LIT> ) != - <NUM_LIT> ) { uint32_t LHSMask = getPermuteMask ( DAG , LHS ) ; uint32_t RHSMask = getPermuteMask ( DAG , RHS ) ; if ( LHSMask != ~ <NUM_LIT> && RHSMask != ~ <NUM_LIT> ) { if ( LHSMask > RHSMask ) { std :: swap ( LHSMask , RHSMask ) ; std :: swap ( LHS , RHS ) ; } uint32_t LHSUsedLanes = ~ ( LHSMask & <NUM_LIT> ) & <NUM_LIT> ; uint32_t RHSUsedLanes = ~ ( RHSMask & <NUM_LIT> ) & <NUM_LIT> ; if ( ! ( LHSUsedLanes & RHSUsedLanes ) && ! ( LHSUsedLanes == <NUM_LIT> && RHSUsedLanes == <NUM_LIT> ) ) {


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . isUndef ( ) ) return N0 ; if ( VT == <STR_LIT> && ( N0 . getOpcode ( ) == <STR_LIT> || N0 . getOpcode ( ) == <STR_LIT> ) ) { return DCI . DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N0 , N -> getFlags ( ) ) ; } if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && N0 . getOpcode ( ) == <STR_LIT> ) {

return DCI . DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N0 . getOperand ( <NUM_LIT> ) , N -> getFlags ( ) ) ;


<s> AM . BaseOffs = Offset . getSExtValue ( ) ; if ( ! isLegalAddressingMode ( DCI . DAG . getDataLayout ( ) , AM , Ty , AddrSpace ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc SL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue ShlX = DAG . getNode ( <STR_LIT> , SL , VT , N0 . getOperand ( <NUM_LIT> ) , N1 ) ; SDValue COffset = DAG . getConstant ( Offset , SL , VT ) ; SDNodeFlags Flags ; Flags . setNoUnsignedWrap ( N -> getFlags ( ) . hasNoUnsignedWrap ( ) && ( N0 . getOpcode ( ) == <STR_LIT> || N0 -> getFlags ( ) . hasNoUnsignedWrap ( ) ) ) ;

return DAG . getNode ( <STR_LIT> , SL , VT , ShlX , COffset , Flags ) ;


<s> AddrMode AM ; AM . HasBaseReg = true ; AM . BaseOffs = Offset . getSExtValue ( ) ; if ( ! isLegalAddressingMode ( DCI . DAG . getDataLayout ( ) , AM , Ty , AddrSpace ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc SL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue ShlX = DAG . getNode ( <STR_LIT> , SL , VT , N0 . getOperand ( <NUM_LIT> ) , N1 ) ; SDValue COffset = DAG . getConstant ( Offset , SL , VT ) ; SDNodeFlags Flags ; Flags . setNoUnsignedWrap ( N -> getFlags ( ) . hasNoUnsignedWrap ( ) && ( N0 . getOpcode ( ) == <STR_LIT> || N0 -> getFlags ( ) . hasNoUnsignedWrap ( ) ) ) ;


<s> auto * VTSign = cast < VTSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ( ( Src . getOpcode ( ) == <STR_LIT> && VTSign -> getVT ( ) == <STR_LIT> ) || ( Src . getOpcode ( ) == <STR_LIT> && VTSign -> getVT ( ) == <STR_LIT> ) ) && Src . hasOneUse ( ) ) { auto * M = cast < MemSDNode > ( Src ) ; SDValue Ops [ ] = { Src . getOperand ( <NUM_LIT> ) , Src . getOperand ( <NUM_LIT> ) , Src . getOperand ( <NUM_LIT> ) , Src . getOperand ( <NUM_LIT> ) , Src . getOperand ( <NUM_LIT> ) , Src . getOperand ( <NUM_LIT> ) , Src . getOperand ( <NUM_LIT> ) , Src . getOperand ( <NUM_LIT> ) } ; SDVTList ResList = DCI . DAG . getVTList ( <STR_LIT> , Src . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ; unsigned Opc = ( Src . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ;

SDValue BufferLoadSignExt = DCI . DAG . getMemIntrinsicNode ( Opc , SDLoc ( N ) , ResList , Ops , M -> getMemoryVT ( ) , M -> getMemOperand ( ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: performSignExtendInRegCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SDValue Src = N -> getOperand ( <NUM_LIT> ) ; auto * VTSign = cast < VTSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ( ( Src . getOpcode ( ) == <STR_LIT> && VTSign -> getVT ( ) == <STR_LIT> ) || ( Src . getOpcode ( ) == <STR_LIT> && VTSign -> getVT ( ) == <STR_LIT> ) ) && Src . hasOneUse ( ) ) {


<s> SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; unsigned Opc = RHS . getOpcode ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { auto Cond = RHS . getOperand ( <NUM_LIT> ) ; if ( ! isBoolSGPR ( Cond ) ) break ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Args [ ] = { LHS , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) , Cond } ; Opc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , SL , VTList , Args ) ; } } if ( LHS . getOpcode ( ) == <STR_LIT> ) { auto C = dyn_cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) ;

if ( ! C || ! C -> isZero ( ) ) return SDValue ( ) ;


<s> if ( ! isBoolSGPR ( Cond ) ) break ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Args [ ] = { LHS , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) , Cond } ; Opc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , SL , VTList , Args ) ; } } if ( LHS . getOpcode ( ) == <STR_LIT> ) { auto C = dyn_cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) ; if ( ! C || ! C -> isZero ( ) ) return SDValue ( ) ; SDValue Args [ ] = { LHS . getOperand ( <NUM_LIT> ) , RHS , LHS . getOperand ( <NUM_LIT> ) } ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , LHS -> getVTList ( ) , Args ) ;


<s> SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; const ConstantSDNode * CRHS = dyn_cast < ConstantSDNode > ( RHS ) ; if ( CRHS ) { if ( SDValue Split = splitBinaryBitConstantOp ( DCI , SDLoc ( N ) , <STR_LIT> , LHS , CRHS ) ) return Split ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ;

SDValue Src = N -> getOperand ( <NUM_LIT> ) ;


<s> if ( ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) != <STR_LIT> ) && ( Src0 == Src1 || Src0 == Src2 ) ) break ; MVT VT = Src0 . getValueType ( ) . getSimpleVT ( ) ; const TargetRegisterClass * RC = getRegClassFor ( VT , Src0 . getNode ( ) -> isDivergent ( ) ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue UndefReg = DAG . getRegister ( MRI . createVirtualRegister ( RC ) , VT ) ; SDValue ImpDef = DAG . getCopyToReg ( DAG . getEntryNode ( ) , SDLoc ( Node ) , UndefReg , Src0 , SDValue ( ) ) ; if ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) == <STR_LIT> ) { if ( Src1 . isMachineOpcode ( ) && Src1 . getMachineOpcode ( ) != <STR_LIT> ) Src0 = Src1 ; else if ( Src2 . isMachineOpcode ( ) && Src2 . getMachineOpcode ( ) != <STR_LIT> ) Src0 = Src2 ; else { assert ( Src1 . getMachineOpcode ( ) == <STR_LIT> ) ; Src0 = UndefReg ; Src1 = UndefReg ; }


<s> static void processP<ISA_LIT>nputArgs ( SmallVectorImpl < <STR_LIT> > & Splits , CallingConv :: ID CallConv , ArrayRef < <STR_LIT> > Ins , BitVector & Skipped , FunctionType * FType , <ISA_LIT>MachineFunctionInfo * Info ) { for ( unsigned I = <NUM_LIT> , E = Ins . size ( ) , P<ISA_LIT>nputNum = <NUM_LIT> ; I != E ; ++ I ) { const <STR_LIT> * Arg = & Ins [ I ] ; assert ( ( ! Arg -> VT . isVector ( ) || Arg -> VT . getScalarSizeInBits ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( CallConv == CallingConv :: <ISA_LIT>_PS && ! Arg -> Flags . isInReg ( ) && P<ISA_LIT>nputNum <= <NUM_LIT> ) { bool SkipArg = ! Arg -> Used && ! Info -> isP<ISA_LIT>nputAllocated ( P<ISA_LIT>nputNum ) ; if ( Arg -> Flags . isSplit ( ) ) { while ( ! Arg -> Flags . isSplitEnd ( ) ) {


<s> case <STR_LIT> : { SDValue Src0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Src1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc SL ( N ) ; unsigned Opcode ; if ( IID == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( IID == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( IID == <STR_LIT> ) Opcode = <STR_LIT> ; else Opcode = <STR_LIT> ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( isTypeLegal ( VT ) ) Results . push_back ( DAG . getNode ( Opcode , SL , VT , Src0 , Src1 ) ) ; else { SDValue Cvt = DAG . getNode ( Opcode , SL , <STR_LIT> , Src0 , Src1 ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Cvt ) ) ; } return ; } } break ; } case <STR_LIT> : { if ( SDValue Res = LowerINTRIN<ISA_LIT>C_W_CHAIN ( SDValue ( N , <NUM_LIT> ) , DAG ) ) { if ( Res . getOpcode ( ) == <STR_LIT> ) { for ( unsigned I = <NUM_LIT> ; I < Res . getNumOperands ( ) ; I ++ ) { Results . push_back ( Res . getOperand ( I ) ) ; } } else { Results . push_back ( Res ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; } return ; } break ; } case <STR_LIT> : { SDLoc SL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue LHS = DAG . getNode ( <STR_LIT> , SL , NewVT , N -> getOperand ( <NUM_LIT> ) ) ;

SDValue RHS = DAG . getNode ( <STR_LIT> , SL , NewVT , N -> getOperand ( <NUM_LIT> ) ) ;


<s> if ( const CallInst * CI = dyn_cast < CallInst > ( V ) ) { if ( CI -> isInlineAsm ( ) ) { const <ISA_LIT>RegisterInfo * <ISA_LIT>RI = Subtarget -> getRegisterInfo ( ) ; TargetLowering :: AsmOperandInfoVector TargetConstraints = ParseConstraints ( MF . getDataLayout ( ) , Subtarget -> getRegisterInfo ( ) , * CI ) ; for ( auto & TC : TargetConstraints ) { if ( TC . Type == InlineAsm :: isOutput ) { ComputeConstraintToUse ( TC , SDValue ( ) ) ; const TargetRegisterClass * RC = getRegForInlineAsmConstraint ( <ISA_LIT>RI , TC . ConstraintCode , TC . ConstraintVT ) . second ; if ( RC && <ISA_LIT>RI -> isSGPRClass ( RC ) ) return true ; } } }


<s> Info . setScratchRSrcReg ( PrivateSegmentBufferReg ) ; } else { unsigned ReservedBufferReg = TRI . reservedPrivateSegmentBufferReg ( MF ) ; Info . setScratchRSrcReg ( ReservedBufferReg ) ; } } MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( ! MRI . isLiveIn ( <STR_LIT> ) ) { Info . setStackPtrOffsetReg ( <STR_LIT> ) ; } else { assert ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) ; if ( MFI . hasCalls ( ) ) report_fatal_error ( <STR_LIT> ) ; for ( unsigned Reg : <STR_LIT> ) { if ( ! MRI . isLiveIn ( Reg ) ) { Info . setStackPtrOffsetReg ( Reg ) ; break ; }


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; bool HasStackObjects = MFI . hasStackObjects ( ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; if ( HasStackObjects ) Info . setHasNonSpillStackObjects ( true ) ; if ( TM . getOptLevel ( ) == CodeGenOpt :: None ) HasStackObjects = true ; bool RequiresStackAccess = HasStackObjects || MFI . hasCalls ( ) ; if ( ! ST . enableFlatScratch ( ) ) { if ( RequiresStackAccess && ST . isAmdHsaOrMesa ( MF . getFunction ( ) ) ) { Register PrivateSegmentBufferReg = Info . getPreloadedReg ( <STR_LIT> ) ; Info . setScratchRSrcReg ( PrivateSegmentBufferReg ) ; } else { unsigned ReservedBufferReg = TRI . reservedPrivateSegmentBufferReg ( MF ) ; Info . setScratchRSrcReg ( ReservedBufferReg ) ; } } MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( ! MRI . isLiveIn ( <STR_LIT> ) ) { Info . setStackPtrOffsetReg ( <STR_LIT> ) ; } else { assert ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) ; if ( MFI . hasCalls ( ) ) report_fatal_error ( <STR_LIT> ) ; for ( unsigned Reg : <STR_LIT> ) { if ( ! MRI . isLiveIn ( Reg ) ) { Info . setStackPtrOffsetReg ( Reg ) ;


<s> SDValue N0 = CombinedOffset . getOperand ( <NUM_LIT> ) ; SDValue N1 = CombinedOffset . getOperand ( <NUM_LIT> ) ; uint32_t SOffset , ImmOffset ; int Offset = cast < ConstantSDNode > ( N1 ) -> getSExtValue ( ) ; if ( Offset >= <NUM_LIT> && <STR_LIT> ( Offset , SOffset , ImmOffset , Subtarget , Alignment ) ) { Offsets [ <NUM_LIT> ] = N0 ; Offsets [ <NUM_LIT> ] = DAG . getConstant ( SOffset , DL , <STR_LIT> ) ;

Offsets [ <NUM_LIT> ] = DAG . getTargetConstant ( ImmOffset , DL , <STR_LIT> ) ;


<s> MachineBasicBlock :: iterator I ( & MI ) ; const MachineOperand * Idx = TII -> getNamedOperand ( MI , <STR_LIT> :: idx ) ; assert ( Idx -> getReg ( ) != <STR_LIT> ) ; if ( Offset == <NUM_LIT> ) {

BuildMI ( * MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . add ( * Idx ) ;


<s> static void setM0ToIndexFromSGPR ( const <ISA_LIT>InstrInfo * TII , MachineRegisterInfo & MRI , MachineInstr & MI , int Offset ) { MachineBasicBlock * MBB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineBasicBlock :: iterator I ( & MI ) ; const MachineOperand * Idx = TII -> getNamedOperand ( MI , <STR_LIT> :: idx ) ; assert ( Idx -> getReg ( ) != <STR_LIT> ) ;


<s> return ( GV -> getAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS || GV -> getAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) && <STR_LIT> ( TT ) ;


<s> return ( GV -> getValueType ( ) -> isFunctionTy ( ) || ! isNonGlobalAddrSpace ( GV -> getAddressSpace ( ) ) ) && ! shouldEmitFixup ( GV ) && ! getTargetMachine ( ) . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ;


<s> if ( Ty -> isHalfTy ( ) ) return AtomicExpansionKind :: None ; if ( ! Ty -> isFloatTy ( ) && ( ! Subtarget -> hasGFX90AInsts ( ) || ! Ty -> isDoubleTy ( ) ) ) return AtomicExpansionKind :: CmpXChg ; unsigned AS = RMW -> getPointerAddressSpace ( ) ; if ( ( AS == <ISA_LIT>AS :: GLOBAL_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS ) && Subtarget -> hasAtomicFaddInsts ( ) ) { if ( Subtarget -> hasGFX940Insts ( ) ) return AtomicExpansionKind :: None ; if ( RMW -> getFunction ( ) -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) != <STR_LIT> ) return AtomicExpansionKind :: CmpXChg ; if ( Subtarget -> hasGFX90AInsts ( ) ) { if ( Ty -> isFloatTy ( ) && AS == <ISA_LIT>AS :: FLAT_ADDRESS ) return AtomicExpansionKind :: CmpXChg ; auto S<ISA_LIT>D = RMW -> getSyncScopeID ( ) ; if ( S<ISA_LIT>D == SyncScope :: System || S<ISA_LIT>D == RMW -> getContext ( ) . getOrInsertSyncScopeID ( <STR_LIT> ) ) return AtomicExpansionKind :: CmpXChg ; return ReportUnsafeHWInst ( AtomicExpansionKind :: None ) ; } if ( AS == <ISA_LIT>AS :: FLAT_ADDRESS ) return AtomicExpansionKind :: CmpXChg ; return RMW -> use_empty ( ) ? ReportUnsafeHWInst ( AtomicExpansionKind :: None ) : AtomicExpansionKind :: CmpXChg ; } if ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS && Subtarget -> hasLDSFPAtomicAdd ( ) ) { if ( ! Ty -> isDoubleTy ( ) ) return AtomicExpansionKind :: None ; if ( fpModeMatchesGlobalFPAtomicMode ( RMW ) ) return AtomicExpansionKind :: None ; return RMW -> getFunction ( ) -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ? ReportUnsafeHWInst ( AtomicExpansionKind :: None ) : AtomicExpansionKind :: CmpXChg ;


<s> if ( ! Ty -> isFloatTy ( ) && ( ! Subtarget -> hasGFX90AInsts ( ) || ! Ty -> isDoubleTy ( ) ) ) return AtomicExpansionKind :: CmpXChg ; unsigned AS = RMW -> getPointerAddressSpace ( ) ; if ( ( AS == <ISA_LIT>AS :: GLOBAL_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS ) && Subtarget -> hasAtomicFaddInsts ( ) ) { if ( Subtarget -> hasGFX940Insts ( ) ) return AtomicExpansionKind :: None ; if ( RMW -> getFunction ( ) -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) != <STR_LIT> ) return AtomicExpansionKind :: CmpXChg ; if ( Subtarget -> hasGFX90AInsts ( ) ) { if ( Ty -> isFloatTy ( ) && AS == <ISA_LIT>AS :: FLAT_ADDRESS ) return AtomicExpansionKind :: CmpXChg ; auto S<ISA_LIT>D = RMW -> getSyncScopeID ( ) ; if ( S<ISA_LIT>D == SyncScope :: System || S<ISA_LIT>D == RMW -> getContext ( ) . getOrInsertSyncScopeID ( <STR_LIT> ) ) return AtomicExpansionKind :: CmpXChg ; return ReportUnsafeHWInst ( AtomicExpansionKind :: None ) ; } if ( AS == <ISA_LIT>AS :: FLAT_ADDRESS ) return AtomicExpansionKind :: CmpXChg ; return RMW -> use_empty ( ) ? ReportUnsafeHWInst ( AtomicExpansionKind :: None ) : AtomicExpansionKind :: CmpXChg ; } if ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS && Subtarget -> hasLDSFPAtomicAdd ( ) ) { if ( ! Ty -> isDoubleTy ( ) ) return AtomicExpansionKind :: None ; if ( fpModeMatchesGlobalFPAtomicMode ( RMW ) ) return AtomicExpansionKind :: None ;

return RMW -> getFunction ( ) -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ? ReportUnsafeHWInst ( AtomicExpansionKind :: None ) : AtomicExpansionKind :: CmpXChg ;


<s> EVT VecVT = Vec . getValueType ( ) ; EVT EltVT = VecVT . getVectorElementType ( ) ; unsigned EltSize = EltVT . getSizeInBits ( ) ; unsigned NumElem = VecVT . getVectorNumElements ( ) ;

return <ISA_LIT>TargetLowering :: shouldExpandVectorDynExt ( EltSize , NumElem , Idx -> isDivergent ( ) ) ;


<s> static bool shouldExpandVectorDynExt ( SDNode * N ) { SDValue Idx = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Idx ) ) return false ; SDValue Vec = N -> getOperand ( <NUM_LIT> ) ; EVT VecVT = Vec . getValueType ( ) ; EVT EltVT = VecVT . getVectorElementType ( ) ; unsigned EltSize = EltVT . getSizeInBits ( ) ; unsigned NumElem = VecVT . getVectorNumElements ( ) ; return <ISA_LIT>TargetLowering :: shouldExpandVectorDynExt ( EltSize , NumElem , Idx -> isDivergent ( ) ) ;


<s> const auto OS = getTargetMachine ( ) . getTargetTriple ( ) . getOS ( ) ;

return OS == Triple :: AMDHSA || OS == Triple :: AMDPAL ;


<s> SDValue <ISA_LIT>TargetLowering :: splitBinaryVectorOp ( SDValue Op , SelectionDAG & DAG ) const { unsigned Opc = Op . getOpcode ( ) ; EVT VT = Op . getValueType ( ) ; assert ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ; SDValue Lo0 , Hi0 ; std :: tie ( Lo0 , Hi0 ) = DAG . SplitVectorOperand ( Op . getNode ( ) , <NUM_LIT> ) ; SDValue Lo1 , Hi1 ; std :: tie ( Lo1 , Hi1 ) = DAG . SplitVectorOperand ( Op . getNode ( ) , <NUM_LIT> ) ; SDLoc SL ( Op ) ; SDValue OpLo = DAG . getNode ( Opc , SL , Lo0 . getValueType ( ) , Lo0 , Lo1 , Op -> getFlags ( ) ) ; SDValue OpHi = DAG . getNode ( Opc , SL , Hi0 . getValueType ( ) , Hi0 , Hi1 , Op -> getFlags ( ) ) ;

return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , OpLo , OpHi ) ;


<s> MachineBasicBlock * LoopBB = MF -> CreateMachineBasicBlock ( ) ; MachineBasicBlock * RemainderBB = MF -> CreateMachineBasicBlock ( ) ; MachineFunction :: iterator MBBI ( MBB ) ; ++ MBBI ; MF -> insert ( MBBI , LoopBB ) ; MF -> insert ( MBBI , RemainderBB ) ; LoopBB -> addSuccessor ( LoopBB ) ; LoopBB -> addSuccessor ( RemainderBB ) ; RemainderBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; if ( InstInLoop ) { auto Next = std :: next ( I ) ; LoopBB -> splice ( LoopBB -> begin ( ) , & MBB , I , Next ) ; RemainderBB -> splice ( RemainderBB -> begin ( ) , & MBB , Next , MBB . end ( ) ) ; } else { RemainderBB -> splice ( RemainderBB -> begin ( ) , & MBB , I , MBB . end ( ) ) ;


<s> static std :: pair < MachineBasicBlock * , MachineBasicBlock * > splitBlockForLoop ( MachineInstr & MI , MachineBasicBlock & MBB , bool InstInLoop ) { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock :: iterator I ( & MI ) ; MachineBasicBlock * LoopBB = MF -> CreateMachineBasicBlock ( ) ; MachineBasicBlock * RemainderBB = MF -> CreateMachineBasicBlock ( ) ; MachineFunction :: iterator MBBI ( MBB ) ;


<s> std :: pair < SDValue , SDValue > <ISA_LIT>TargetLowering :: splitBufferOffsets ( SDValue Offset , SelectionDAG & DAG ) const { SDLoc DL ( Offset ) ; const unsigned MaxImm = <NUM_LIT> ; SDValue N0 = Offset ; ConstantSDNode * C1 = nullptr ; if ( ( C1 = dyn_cast < ConstantSDNode > ( N0 ) ) ) N0 = SDValue ( ) ; else if ( DAG . isBaseWithConstantOffset ( N0 ) ) { C1 = cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; N0 = N0 . getOperand ( <NUM_LIT> ) ;


<s> MI . setDesc ( TII -> getKillTerminatorFromPseudo ( MI . getOpcode ( ) ) ) ;


<s> const <ISA_LIT>InstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; MI . setDesc ( TII -> getKillTerminatorFromPseudo ( MI . getOpcode ( ) ) ) ;


<s> SDValue Lo0 , Hi0 ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; std :: tie ( Lo0 , Hi0 ) = Op0 . getValueType ( ) . isVector ( ) ? DAG . SplitVectorOperand ( Op . getNode ( ) , <NUM_LIT> ) : std :: make_pair ( Op0 , Op0 ) ; SDValue Lo1 , Hi1 ; std :: tie ( Lo1 , Hi1 ) = DAG . SplitVectorOperand ( Op . getNode ( ) , <NUM_LIT> ) ; SDValue Lo2 , Hi2 ; std :: tie ( Lo2 , Hi2 ) = DAG . SplitVectorOperand ( Op . getNode ( ) , <NUM_LIT> ) ; SDLoc SL ( Op ) ; auto ResVT = DAG . GetSplitDestVTs ( VT ) ; SDValue OpLo = DAG . getNode ( Opc , SL , ResVT . first , Lo0 , Lo1 , Lo2 , Op -> getFlags ( ) ) ; SDValue OpHi = DAG . getNode ( Opc , SL , ResVT . second , Hi0 , Hi1 , Hi2 , Op -> getFlags ( ) ) ;


<s> std :: tie ( Lo , Hi ) = DAG . SplitVectorOperand ( Op . getNode ( ) , <NUM_LIT> ) ; SDLoc SL ( Op ) ; SDValue OpLo = DAG . getNode ( Opc , SL , Lo . getValueType ( ) , Lo , Op -> getFlags ( ) ) ; SDValue OpHi = DAG . getNode ( Opc , SL , Hi . getValueType ( ) , Hi , Op -> getFlags ( ) ) ;


<s> switch ( Idx ) { default : return ~ <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; }


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ;


<s> static void updateBufferMMO ( MachineMemOperand * MMO , SDValue VOffset , SDValue SOffset , SDValue Offset , SDValue VIndex = SDValue ( ) ) { if ( ! isa < ConstantSDNode > ( VOffset ) || ! isa < ConstantSDNode > ( SOffset ) || ! isa < ConstantSDNode > ( Offset ) ) {

MMO -> setValue ( ( Value * ) nullptr ) ;


<s> MMO -> setValue ( ( Value * ) nullptr ) ; return ; } if ( VIndex && ( ! isa < ConstantSDNode > ( VIndex ) || ! cast < ConstantSDNode > ( VIndex ) -> isZero ( ) ) ) { MMO -> setValue ( ( Value * ) nullptr ) ; return ;


<s> MachineSDNode * <ISA_LIT>TargetLowering :: wrapAddr64Rsrc ( SelectionDAG & DAG , const SDLoc & DL , SDValue Ptr ) const { const <ISA_LIT>InstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; const SDValue Ops0 [ ] = { DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , buildSMovImm32 ( DAG , DL , <NUM_LIT> ) , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , buildSMovImm32 ( DAG , DL , TII -> getDefaultRsrcDataFormat ( ) >> <NUM_LIT> ) , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) } ;

SDValue SubRegHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops0 ) , <NUM_LIT> ) ;


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitInstrWithCustomInserter ( MachineInstr & MI , MachineBasicBlock * BB ) const { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : { const <ISA_LIT>InstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; BuildMI ( * BB , MI . getIterator ( ) , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; MI . eraseFromParent ( ) ; break ; } case <STR_LIT> : return BB ; case <STR_LIT> : { const <ISA_LIT>InstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; MachineFunction * MF = BB -> getParent ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( MFI -> LDSSize ) ; MI . eraseFromParent ( ) ; return BB ; } default : return <ISA_LIT>TargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; } return BB ;


<s> SDValue <ISA_LIT>TargetLowering :: getSegmentAperture ( unsigned AS , SelectionDAG & DAG ) const { SDLoc SL ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned UserSGPR = Info -> getQueuePtrUserSGPR ( ) ; assert ( UserSGPR != <STR_LIT> ) ;

SDValue QueuePtr = CreateLiveInRegister ( DAG , & <STR_LIT> , UserSGPR , <STR_LIT> ) ;


<s> SDValue QueuePtr = CreateLiveInRegister ( DAG , & <STR_LIT> , UserSGPR , <STR_LIT> ) ; uint32_t StructOffset = ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS ) ? <NUM_LIT> : <NUM_LIT> ; SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , QueuePtr , DAG . getConstant ( StructOffset , SL , <STR_LIT> ) ) ; Value * V = UndefValue :: get ( PointerType :: get ( Type :: getInt8Ty ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ) ; MachinePointerInfo PtrInfo ( V , StructOffset ) ;

return DAG . getLoad ( <STR_LIT> , SL , QueuePtr . getValue ( <NUM_LIT> ) , Ptr , PtrInfo , false , false , true , MinAlign ( <NUM_LIT> , StructOffset ) ) ;


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { if ( GA -> getAddressSpace ( ) != <ISA_LIT>AS :: GLOBAL_ADDRESS ) return false ;

return TargetLowering :: isOffsetFoldingLegal ( GA ) ;


<s> SDLoc SL ( Op ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; bool Unsafe = DAG . getTarget ( ) . Options . UnsafeFPMath ; if ( const ConstantFPSDNode * CLHS = dyn_cast < ConstantFPSDNode > ( LHS ) ) { if ( ( Unsafe || ( VT == <STR_LIT> && ! Subtarget -> hasFP32Denormals ( ) ) ) && CLHS -> isExactlyValue ( <NUM_LIT> ) ) { if ( RHS . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SL , VT , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; }


<s> return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , r3 , Mul ) ; } const SDValue One = DAG . getConstantFP ( <NUM_LIT> , SL , <STR_LIT> ) ; SDVTList ScaleVT = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue DenominatorScaled = DAG . getNode ( <STR_LIT> , SL , ScaleVT , RHS , RHS , LHS ) ; SDValue NumeratorScaled = DAG . getNode ( <STR_LIT> , SL , ScaleVT , LHS , RHS , LHS ) ; SDValue ApproxRcp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DenominatorScaled ) ; SDValue NegDivScale0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DenominatorScaled ) ; SDValue Fma0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , ApproxRcp , One ) ; SDValue Fma1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Fma0 , ApproxRcp , ApproxRcp ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NumeratorScaled , Fma1 ) ; SDValue Fma2 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Mul , NumeratorScaled ) ; SDValue Fma3 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Fma2 , Fma1 , Mul ) ;

SDValue Fma4 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Fma3 , NumeratorScaled ) ;


<s> SDValue Rcp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ; SDValue Fma0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Rcp , One ) ; SDValue Fma1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Rcp , Fma0 , Rcp ) ; SDValue Fma2 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Fma1 , One ) ; SDValue DivScale1 = DAG . getNode ( <STR_LIT> , SL , ScaleVT , X , Y , X ) ; SDValue Fma3 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Fma1 , Fma2 , Fma1 ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale1 , Fma3 ) ; SDValue Fma4 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Mul , DivScale1 ) ; SDValue Scale ; if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) { const SDValue Hi = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue NumBC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , X ) ; SDValue DenBC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Y ) ; SDValue Scale0BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ; SDValue Scale1BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale1 ) ; SDValue NumHi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NumBC , Hi ) ; SDValue DenHi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DenBC , Hi ) ;

SDValue Scale0Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Scale0BC , Hi ) ;


<s> SDValue Y = Op . getOperand ( <NUM_LIT> ) ; const SDValue One = DAG . getConstantFP ( <NUM_LIT> , SL , <STR_LIT> ) ; SDVTList ScaleVT = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue DivScale0 = DAG . getNode ( <STR_LIT> , SL , ScaleVT , Y , Y , X ) ; SDValue NegDivScale0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ; SDValue Rcp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ; SDValue Fma0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Rcp , One ) ; SDValue Fma1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Rcp , Fma0 , Rcp ) ; SDValue Fma2 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Fma1 , One ) ; SDValue DivScale1 = DAG . getNode ( <STR_LIT> , SL , ScaleVT , X , Y , X ) ; SDValue Fma3 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Fma1 , Fma2 , Fma1 ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale1 , Fma3 ) ; SDValue Fma4 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Mul , DivScale1 ) ; SDValue Scale ; if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) { const SDValue Hi = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue NumBC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , X ) ; SDValue DenBC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Y ) ; SDValue Scale0BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ; SDValue Scale1BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale1 ) ; SDValue NumHi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NumBC , Hi ) ; SDValue DenHi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DenBC , Hi ) ; SDValue Scale0Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Scale0BC , Hi ) ; SDValue Scale1Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Scale1BC , Hi ) ; SDValue CmpDen = DAG . getSetCC ( SL , <STR_LIT> , DenHi , Scale0Hi , <STR_LIT> ) ;

SDValue CmpNum = DAG . getSetCC ( SL , <STR_LIT> , NumHi , Scale1Hi , <STR_LIT> ) ;


<s> EVT PtrVT = Op . getValueType ( ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , GSD -> getOffset ( ) + <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , GA ) ;


<s> const DataLayout & DL = DAG . getDataLayout ( ) ; Type * Ty = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; MVT PtrVT = getPointerTy ( DL , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; PointerType * PtrTy = PointerType :: get ( Ty , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; SDValue PtrOffset = DAG . getUNDEF ( PtrVT ) ;

MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ) ;


<s> MachineSDNode * <ISA_LIT>TargetLowering :: buildScratchRSRC ( SelectionDAG & DAG , SDLoc DL , SDValue Ptr ) const { const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ;

uint64_t Rsrc = TII -> getDefaultRsrcDataFormat ( ) | <STR_LIT> | <NUM_LIT> ;


<s> const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ;


<s> case <NUM_LIT> : RC = & <STR_LIT> ; break ; case <NUM_LIT> : RC = & <STR_LIT> ; break ; } unsigned NewOpcode = TII -> getMaskedMIMGOp ( MI . getOpcode ( ) , BitsSet ) ; MI . setDesc ( TII -> get ( NewOpcode ) ) ; MRI . setRegClass ( VReg , RC ) ; return ; } int NoRetAtomicOp = <STR_LIT> ( MI . getOpcode ( ) ) ; if ( NoRetAtomicOp != - <NUM_LIT> ) { if ( ! Node -> hasAnyUseOfValue ( <NUM_LIT> ) ) { MI . setDesc ( TII -> get ( NoRetAtomicOp ) ) ; MI . RemoveOperand ( <NUM_LIT> ) ; return ; } if ( ( Node -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) && Node -> use_begin ( ) -> isMachineOpcode ( ) && Node -> use_begin ( ) -> getMachineOpcode ( ) == <STR_LIT> && ! Node -> use_begin ( ) -> hasAnyUseOfValue ( <NUM_LIT> ) ) ) { unsigned Def = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> } if ( ! Subtarget -> hasUnalignedScratchAccess ( ) && ( AddrSpace == <ISA_LIT>AS :: PRIVATE_ADDRESS || AddrSpace == <ISA_LIT>AS :: FLAT_ADDRESS ) ) { return false ; } if ( Subtarget -> hasUnalignedBufferAccess ( ) ) { if ( IsFast ) { * IsFast = ( AddrSpace == <ISA_LIT>AS :: CONSTANT_ADDRESS ) ? ( Align % <NUM_LIT> == <NUM_LIT> ) : true ; } return true ; } if ( VT . bitsLT ( <STR_LIT> ) ) return false ; if ( IsFast ) * IsFast = true ; return VT . bitsGT ( <STR_LIT> ) && Align % <NUM_LIT> == <NUM_LIT> ;


<s> SDValue PtrHi = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , Offset + <NUM_LIT> , GAFlags == <ISA_LIT>InstrInfo :: MO_NONE ? GAFlags : GAFlags + <NUM_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , PtrVT , PtrLo , PtrHi ) ;


<s> const DebugLoc & DL = MI . getDebugLoc ( ) ; if ( UseGPRIdxMode ) { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addReg ( SrcVec -> getReg ( ) , RegState :: Undef , SubReg ) . addOperand ( * Val ) . addReg ( Dst , RegState :: ImplicitDefine ) . addReg ( SrcVec -> getReg ( ) , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) ; } else { const MCInstrDesc & MovRelDesc = TII -> get ( getMOVRELDPseudo ( VecRC ) ) ; BuildMI ( MBB , I , DL , MovRelDesc ) . addReg ( Dst , RegState :: Define ) . addReg ( SrcVec -> getReg ( ) ) . addOperand ( * Val ) . addImm ( SubReg - <STR_LIT> ) ; } MI . eraseFromParent ( ) ; return & MBB ; } if ( Val -> isReg ( ) ) MRI . clearKillFlags ( Val -> getReg ( ) ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; if ( UseGPRIdxMode ) { MachineBasicBlock :: iterator I ( & MI ) ; MachineInstr * SetOn = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( VGPRIndexMode :: DST_ENABLE ) ;

SetOn -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ;


<s> MachineBasicBlock :: iterator I ( & MI ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; if ( UseGPRIdxMode ) { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( SrcReg , RegState :: Undef , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) ; } else { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( SrcReg , RegState :: Undef , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) ; } MI . eraseFromParent ( ) ; return & MBB ; } const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineBasicBlock :: iterator I ( & MI ) ; unsigned PhiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned InitReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , InitReg ) ; if ( UseGPRIdxMode ) { MachineInstr * SetOn = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( VGPRIndexMode :: SRC0_ENABLE ) ;


<s> BuildMI ( LoopBB , I , DL , TII -> get ( TargetOpcode :: PHI ) , PhiReg ) . addReg ( InitReg ) . addMBB ( & OrigBB ) . addReg ( ResultReg ) . addMBB ( & LoopBB ) ; BuildMI ( LoopBB , I , DL , TII -> get ( TargetOpcode :: PHI ) , PhiExec ) . addReg ( InitSaveExecReg ) . addMBB ( & OrigBB ) . addReg ( NewExec ) . addMBB ( & LoopBB ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , CurrentIdxReg ) . addReg ( IdxReg . getReg ( ) , getUndefRegState ( IdxReg . isUndef ( ) ) ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , CondReg ) . addReg ( CurrentIdxReg ) . addReg ( IdxReg . getReg ( ) , <NUM_LIT> , IdxReg . getSubReg ( ) ) ; if ( UseGPRIdxMode ) { unsigned IdxReg ; if ( Offset == <NUM_LIT> ) {


<s> BuildMI ( LoopBB , I , DL , TII -> get ( TargetOpcode :: PHI ) , PhiExec ) . addReg ( InitSaveExecReg ) . addMBB ( & OrigBB ) . addReg ( NewExec ) . addMBB ( & LoopBB ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , CurrentIdxReg ) . addReg ( IdxReg . getReg ( ) , getUndefRegState ( IdxReg . isUndef ( ) ) ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , CondReg ) . addReg ( CurrentIdxReg ) . addReg ( IdxReg . getReg ( ) , <NUM_LIT> , IdxReg . getSubReg ( ) ) ; if ( UseGPRIdxMode ) { unsigned IdxReg ; if ( Offset == <NUM_LIT> ) { IdxReg = CurrentIdxReg ; } else { IdxReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , IdxReg ) . addReg ( CurrentIdxReg , RegState :: Kill ) . addImm ( Offset ) ; } MachineInstr * SetIdx = BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) ) . addReg ( IdxReg , RegState :: Kill ) ; SetIdx -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; } else { if ( Offset == <NUM_LIT> ) { BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( CurrentIdxReg , RegState :: Kill ) ; } else { BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( CurrentIdxReg , RegState :: Kill ) . addImm ( Offset ) ;


<s> const TargetOptions & Options = DAG . getTarget ( ) . Options ;

if ( ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath || ( cast < BinaryWithFlagsSDNode > ( N0 ) -> Flags . hasUnsafeAlgebra ( ) && cast < BinaryWithFlagsSDNode > ( N1 ) -> Flags . hasUnsafeAlgebra ( ) ) ) && isFMAFasterThanFMulAndFAdd ( VT ) ) {


<s> if ( ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath || ( cast < BinaryWithFlagsSDNode > ( N0 ) -> Flags . hasUnsafeAlgebra ( ) && cast < BinaryWithFlagsSDNode > ( N1 ) -> Flags . hasUnsafeAlgebra ( ) ) ) && isFMAFasterThanFMulAndFAdd ( VT ) ) { return <STR_LIT> ; } return <NUM_LIT> ;


<s> switch ( VecRC -> getSize ( ) ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } case 'v' : switch ( VT . getSizeInBits ( ) ) { default : return std :: make_pair ( <NUM_LIT> , nullptr ) ; case <NUM_LIT> : case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } } if ( Constraint . size ( ) > <NUM_LIT> ) {

const TargetRegisterClass * RC = nullptr ;


<s> SDLoc SL ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned UserSGPR = Info -> getQueuePtrUserSGPR ( ) ; assert ( UserSGPR != <STR_LIT> ) ; SDValue QueuePtr = CreateLiveInRegister ( DAG , & <STR_LIT> , UserSGPR , <STR_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: getSegmentAperture ( unsigned AS , SelectionDAG & DAG ) const { SDLoc SL ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned UserSGPR = Info -> getQueuePtrUserSGPR ( ) ; assert ( UserSGPR != <STR_LIT> ) ; SDValue QueuePtr = CreateLiveInRegister ( DAG , & <STR_LIT> , UserSGPR , <STR_LIT> ) ; uint32_t StructOffset = ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS ) ? <NUM_LIT> : <NUM_LIT> ; SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , QueuePtr , DAG . getConstant ( StructOffset , SL , <STR_LIT> ) ) ; Value * V = UndefValue :: get ( PointerType :: get ( Type :: getInt8Ty ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ) ; MachinePointerInfo PtrInfo ( V , StructOffset ) ; return DAG . getLoad ( <STR_LIT> , SL , QueuePtr . getValue ( <NUM_LIT> ) , Ptr , PtrInfo , MinAlign ( <NUM_LIT> , StructOffset ) , MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ;


<s> if ( Intr -> getOpcode ( ) == <STR_LIT> ) { switch ( cast < ConstantSDNode > ( Intr -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>TargetLowering :: isCFIntrinsic ( const SDNode * Intr ) const { if ( Intr -> getOpcode ( ) == <STR_LIT> ) { switch ( cast < ConstantSDNode > ( Intr -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return false ; } } if ( Intr -> getOpcode ( ) == <STR_LIT> ) { switch ( cast < ConstantSDNode > ( Intr -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return false ; } } return false ;


<s> bool <ISA_LIT>TargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : return Subtarget -> hasFP32Denormals ( ) && Subtarget -> hasFastFMAF32 ( ) ; case <STR_LIT> :


<s> bool <ISA_LIT>TargetLowering :: isMemOpHasNoClobberedMemOperand ( const SDNode * N ) const { const MemSDNode * MemNode = cast < MemSDNode > ( N ) ;

const Value * Ptr = MemNode -> getMemOperand ( ) -> getValue ( ) ;


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return ( GA -> getAddressSpace ( ) == <ISA_LIT>AS :: GLOBAL_ADDRESS || GA -> getAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS ) && ! shouldEmitGOTReloc ( GA -> getGlobal ( ) ) ;


<s> MachineBasicBlock * RemainderBB = MF -> CreateMachineBasicBlock ( ) ; MachineFunction :: iterator MBBI ( MBB ) ; ++ MBBI ; MF -> insert ( MBBI , LoopBB ) ; MF -> insert ( MBBI , RemainderBB ) ; LoopBB -> addSuccessor ( LoopBB ) ; LoopBB -> addSuccessor ( RemainderBB ) ; RemainderBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; RemainderBB -> splice ( RemainderBB -> begin ( ) , & MBB , I , MBB . end ( ) ) ; MBB . addSuccessor ( LoopBB ) ;

const MachineOperand * Idx = TII -> getNamedOperand ( MI , <STR_LIT> :: idx ) ;


<s> if ( HaveChain ) Ops . push_back ( BRCOND . getOperand ( <NUM_LIT> ) ) ; Ops . append ( Intr -> op_begin ( ) + ( HaveChain ? <NUM_LIT> : <NUM_LIT> ) , Intr -> op_end ( ) ) ; Ops . push_back ( Target ) ; ArrayRef < EVT > Res ( Intr -> value_begin ( ) + <NUM_LIT> , Intr -> value_end ( ) ) ; SDNode * Result = DAG . getNode ( Res . size ( ) > <NUM_LIT> ? <STR_LIT> : <STR_LIT> , DL , DAG . getVTList ( Res ) , Ops ) . getNode ( ) ; if ( ! HaveChain ) { SDValue Ops [ ] = { SDValue ( Result , <NUM_LIT> ) , BRCOND . getOperand ( <NUM_LIT> ) } ; Result = DAG . getMergeValues ( Ops , DL ) . getNode ( ) ; } if ( BR ) { SDValue Ops [ ] = { BR -> getOperand ( <NUM_LIT> ) , BRCOND . getOperand ( <NUM_LIT> ) } ; SDValue NewBR = DAG . getNode ( <STR_LIT> , DL , BR -> getVTList ( ) , Ops ) ; DAG . ReplaceAllUsesWith ( BR , NewBR . getNode ( ) ) ; BR = NewBR . getNode ( ) ; } SDValue Chain = SDValue ( Result , Result -> getNumValues ( ) - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Intr -> getNumValues ( ) - <NUM_LIT> ; i != e ; ++ i ) { SDNode * CopyToReg = findUser ( SDValue ( Intr , i ) , <STR_LIT> ) ; if ( ! CopyToReg ) continue ;

Chain = DAG . getCopyToReg ( Chain , DL , CopyToReg -> getOperand ( <NUM_LIT> ) , SDValue ( Result , i - <NUM_LIT> ) , SDValue ( ) ) ;


<s> assert ( ! SetCC || ( SetCC -> getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> && cast < CondCodeSDNode > ( SetCC -> getOperand ( <NUM_LIT> ) . getNode ( ) ) -> get ( ) == <STR_LIT> ) ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( HaveChain ) Ops . push_back ( BRCOND . getOperand ( <NUM_LIT> ) ) ; Ops . append ( Intr -> op_begin ( ) + ( HaveChain ? <NUM_LIT> : <NUM_LIT> ) , Intr -> op_end ( ) ) ; Ops . push_back ( Target ) ; ArrayRef < EVT > Res ( Intr -> value_begin ( ) + <NUM_LIT> , Intr -> value_end ( ) ) ; SDNode * Result = DAG . getNode ( Res . size ( ) > <NUM_LIT> ? <STR_LIT> : <STR_LIT> , DL , DAG . getVTList ( Res ) , Ops ) . getNode ( ) ; if ( ! HaveChain ) { SDValue Ops [ ] = { SDValue ( Result , <NUM_LIT> ) , BRCOND . getOperand ( <NUM_LIT> ) } ; Result = DAG . getMergeValues ( Ops , DL ) . getNode ( ) ; } if ( BR ) { SDValue Ops [ ] = {

BR -> getOperand ( <NUM_LIT> ) , BRCOND . getOperand ( <NUM_LIT> ) } ;


<s> bool Unsafe = DAG . getTarget ( ) . Options . UnsafeFPMath ; if ( const ConstantFPSDNode * CLHS = dyn_cast < ConstantFPSDNode > ( LHS ) ) { if ( Unsafe || ( VT == <STR_LIT> && ! Subtarget -> hasFP32Denormals ( ) ) || VT == <STR_LIT> ) { if ( CLHS -> isExactlyValue ( <NUM_LIT> ) ) { if ( RHS . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SL , VT , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; } if ( CLHS -> isExactlyValue ( - <NUM_LIT> ) ) { SDValue FNegRHS = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; return DAG . getNode ( <STR_LIT> , SL , VT , FNegRHS ) ; } } } const SDNodeFlags * Flags = Op -> getFlags ( ) ; if ( Unsafe || Flags -> hasAllowReciprocal ( ) ) {


<s> if ( SrcVT != <STR_LIT> ) return Op ; SDLoc DL ( Op ) ; SDValue FpToFp16 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FpToFp16 ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Trunc ) ; ;


<s> assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ;


<s> else if ( shouldEmitPCReloc ( GV ) ) return buildPCRelGlobalAddress ( DAG , GV , DL , GSD -> getOffset ( ) , PtrVT , <ISA_LIT>InstrInfo :: MO_REL32 ) ; SDValue GOTAddr = buildPCRelGlobalAddress ( DAG , GV , DL , <NUM_LIT> , PtrVT , <ISA_LIT>InstrInfo :: MO_GOTPCREL32 ) ; Type * Ty = PtrVT . getTypeForEVT ( * DAG . getContext ( ) ) ; PointerType * PtrTy = PointerType :: get ( Ty , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; const DataLayout & DataLayout = DAG . getDataLayout ( ) ; unsigned Align = DataLayout . getABITypeAlignment ( PtrTy ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ) ;

return DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , GOTAddr , PtrInfo , Align , MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( <ISA_LIT>MachineFunction * MFI , SDValue Op , SelectionDAG & DAG ) const { GlobalAddressSDNode * GSD = cast < GlobalAddressSDNode > ( Op ) ; if ( GSD -> getAddressSpace ( ) != <ISA_LIT>AS :: CONSTANT_ADDRESS && GSD -> getAddressSpace ( ) != <ISA_LIT>AS :: GLOBAL_ADDRESS ) return <ISA_LIT>TargetLowering :: LowerGlobalAddress ( MFI , Op , DAG ) ; SDLoc DL ( GSD ) ; const GlobalValue * GV = GSD -> getGlobal ( ) ; EVT PtrVT = Op . getValueType ( ) ; if ( shouldEmitFixup ( GV ) ) return buildPCRelGlobalAddress ( DAG , GV , DL , GSD -> getOffset ( ) , PtrVT ) ; else if ( shouldEmitPCReloc ( GV ) ) return buildPCRelGlobalAddress ( DAG , GV , DL , GSD -> getOffset ( ) , PtrVT , <ISA_LIT>InstrInfo :: MO_REL32 ) ; SDValue GOTAddr = buildPCRelGlobalAddress ( DAG , GV , DL , <NUM_LIT> , PtrVT , <ISA_LIT>InstrInfo :: MO_GOTPCREL32 ) ; Type * Ty = PtrVT . getTypeForEVT ( * DAG . getContext ( ) ) ; PointerType * PtrTy = PointerType :: get ( Ty , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; const DataLayout & DataLayout = DAG . getDataLayout ( ) ; unsigned Align = DataLayout . getABITypeAlignment ( PtrTy ) ;


<s> Chain , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ; EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore , VT . getStoreSize ( ) , <NUM_LIT> ) ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Ops , VT , MMO ) ; } case <STR_LIT> : { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( const ConstantFPSDNode * K = dyn_cast < ConstantFPSDNode > ( Src ) ) { if ( ! K -> isNegative ( ) ) return Chain ; SDValue NegOne = DAG . getTargetConstant ( FloatToBits ( - <NUM_LIT> ) , DL , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , NegOne ) ;


<s> unsigned Opc = ( IntrID == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { M -> getOperand ( <NUM_LIT> ) , M -> getOperand ( <NUM_LIT> ) , M -> getOperand ( <NUM_LIT> ) } ; return DAG . getMemIntrinsicNode ( Opc , SDLoc ( Op ) , M -> getVTList ( ) , Ops , M -> getMemoryVT ( ) , M -> getMemOperand ( ) ) ; } case <STR_LIT> : case <STR_LIT> : { SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Opc = ( IntrID == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; EVT VT = Op . getValueType ( ) ; EVT IntVT = VT . changeTypeToInteger ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( MFI -> getBufferPSV ( ) ) , MachineMemOperand :: MOLoad , VT . getStoreSize ( ) , VT . getStoreSize ( ) ) ;

return DAG . getMemIntrinsicNode ( Opc , DL , Op -> getVTList ( ) , Ops , IntVT , MMO ) ;


<s> case <STR_LIT> : case <STR_LIT> : { MemSDNode * M = cast < MemSDNode > ( Op ) ; unsigned Opc = ( IntrID == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { M -> getOperand ( <NUM_LIT> ) , M -> getOperand ( <NUM_LIT> ) , M -> getOperand ( <NUM_LIT> ) } ; return DAG . getMemIntrinsicNode ( Opc , SDLoc ( Op ) , M -> getVTList ( ) , Ops , M -> getMemoryVT ( ) , M -> getMemOperand ( ) ) ; } case <STR_LIT> : case <STR_LIT> : { SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Opc = ( IntrID == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; EVT VT = Op . getValueType ( ) ; EVT IntVT = VT . changeTypeToInteger ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( MFI -> getBufferPSV ( ) ) , MachineMemOperand :: MOLoad , VT . getStoreSize ( ) , VT . getStoreSize ( ) ) ; return DAG . getMemIntrinsicNode ( Opc , DL , Op -> getVTList ( ) , Ops , IntVT , MMO ) ; } default : return SDValue ( ) ; }


<s> default : return <ISA_LIT>TargetLowering :: LowerOperation ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : { SDValue Result = LowerLOAD ( Op , DAG ) ; assert ( ( ! Result . getNode ( ) || Result . getNode ( ) -> getNumValues ( ) == <NUM_LIT> ) && <STR_LIT> ) ; return Result ; } case <STR_LIT> : case <STR_LIT> : return LowerTrig ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerFDIV ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_CMP_SWAP ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;

return LowerGlobalAddress ( MFI , Op , DAG ) ;


<s> SDValue Load = DAG . getLoad ( MemVT , SL , Chain , Ptr , PtrInfo , Align , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; SDValue Val = Load ; if ( Arg && ( Arg -> Flags . isSExt ( ) || Arg -> Flags . isZExt ( ) ) && VT . bitsLT ( MemVT ) ) { unsigned Opc = Arg -> Flags . isZExt ( ) ? <STR_LIT> : <STR_LIT> ; Val = DAG . getNode ( Opc , SL , MemVT , Val , DAG . getValueType ( VT ) ) ; } if ( MemVT . isFloatingPoint ( ) ) Val = getFPExtOrFPTrunc ( DAG , Val , SL , VT ) ; else if ( Signed ) Val = DAG . getSExtOrTrunc ( Val , SL , VT ) ;

else Val = DAG . getZExtOrTrunc ( Val , SL , VT ) ;


<s> SDLoc DL ( Op ) ; StoreSDNode * Store = cast < StoreSDNode > ( Op ) ; EVT VT = Store -> getMemoryVT ( ) ; if ( VT == <STR_LIT> ) { return DAG . getTruncStore ( Store -> getChain ( ) , DL , DAG . getSExtOrTrunc ( Store -> getValue ( ) , DL , <STR_LIT> ) , Store -> getBasePtr ( ) , <STR_LIT> , Store -> getMemOperand ( ) ) ; } assert ( VT . isVector ( ) && Store -> getValue ( ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> ) ; unsigned AS = Store -> getAddressSpace ( ) ; if ( ! allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , VT , AS , Store -> getAlignment ( ) ) ) { return expandUnalignedStore ( Store , DAG ) ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( AS == <ISA_LIT>AS :: FLAT_ADDRESS ) AS = MFI -> hasFlatScratchInit ( ) ? <ISA_LIT>AS :: PRIVATE_ADDRESS : <ISA_LIT>AS :: GLOBAL_ADDRESS ; unsigned NumElements = VT . getVectorNumElements ( ) ; switch ( AS ) { case <ISA_LIT>AS :: GLOBAL_ADDRESS : case <ISA_LIT>AS :: FLAT_ADDRESS :

if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ;


<s> if ( DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { const ConstantSDNode * CRHS = dyn_cast < ConstantSDNode > ( RHS ) ; if ( CRHS ) { if ( SDValue Split = splitBinaryBitConstantOp ( DCI , SDLoc ( N ) , <STR_LIT> , LHS , CRHS ) ) return Split ; } } if ( LHS . getOpcode ( ) == <STR_LIT> && RHS . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> LCC = cast < CondCodeSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) -> get ( ) ; <STR_LIT> RCC = cast < CondCodeSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue X = LHS . getOperand ( <NUM_LIT> ) ; SDValue Y = RHS . getOperand ( <NUM_LIT> ) ; if ( Y . getOpcode ( ) != <STR_LIT> || Y . getOperand ( <NUM_LIT> ) != X ) return SDValue ( ) ; if ( LCC == <STR_LIT> ) { if ( X != LHS . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; if ( RCC == <STR_LIT> ) { const ConstantFPSDNode * C1 = dyn_cast < ConstantFPSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) ; if ( ! C1 || ! C1 -> isInfinity ( ) || C1 -> isNegative ( ) ) return SDValue ( ) ; const uint32_t Mask = <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> ; static_assert ( ( ( ~ ( <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> ) ) & <NUM_LIT> ) == Mask , <STR_LIT> ) ;


<s> if ( X != LHS . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; if ( RCC == <STR_LIT> ) { const ConstantFPSDNode * C1 = dyn_cast < ConstantFPSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) ; if ( ! C1 || ! C1 -> isInfinity ( ) || C1 -> isNegative ( ) ) return SDValue ( ) ; const uint32_t Mask = <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> ; static_assert ( ( ( ~ ( <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> ) ) & <NUM_LIT> ) == Mask , <STR_LIT> ) ; SDLoc DL ( N ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X , DAG . getConstant ( Mask , DL , <STR_LIT> ) ) ;


<s> SDValue Srl = N -> getOperand ( <NUM_LIT> ) ; if ( Srl . getOpcode ( ) == <STR_LIT> ) Srl = Srl . getOperand ( <NUM_LIT> ) ; if ( Srl . getOpcode ( ) == <STR_LIT> ) { if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Srl . getOperand ( <NUM_LIT> ) ) ) { Srl = DAG . getZExtOrTrunc ( Srl . getOperand ( <NUM_LIT> ) , SDLoc ( Srl . getOperand ( <NUM_LIT> ) ) , EVT ( <STR_LIT> ) ) ; unsigned SrcOffset = C -> getZExtValue ( ) + <NUM_LIT> * Offset ; if ( SrcOffset < <NUM_LIT> && SrcOffset % <NUM_LIT> == <NUM_LIT> ) { return DAG . getNode ( <STR_LIT> + SrcOffset / <NUM_LIT> , SL , <STR_LIT> , Srl ) ; } } } APInt Demanded = APInt :: getBitsSet ( <NUM_LIT> , <NUM_LIT> * Offset , <NUM_LIT> * Offset + <NUM_LIT> ) ; APInt KnownZero , KnownOne ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ;

const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( DCI . isBeforeLegalize ( ) ) break ; return performMemSDNodeCombine ( cast < MemSDNode > ( N ) , DCI ) ; } case <STR_LIT> : return performAndCombine ( N , DCI ) ; case <STR_LIT> : return performOrCombine ( N , DCI ) ; case <STR_LIT> : return performXorCombine ( N , DCI ) ; case <STR_LIT> : return performClassCombine ( N , DCI ) ; case <STR_LIT> : return performFCanonicalizeCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . isUndef ( ) ) return Src ; break ; } case <STR_LIT> : case <STR_LIT> : return performUCharToFloatCombine ( N , DCI ) ; case <STR_LIT> :


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( DCI . isBeforeLegalize ( ) ) break ; return performMemSDNodeCombine ( cast < MemSDNode > ( N ) , DCI ) ; } case <STR_LIT> : return performAndCombine ( N , DCI ) ; case <STR_LIT> : return performOrCombine ( N , DCI ) ; case <STR_LIT> : return performXorCombine ( N , DCI ) ; case <STR_LIT> : return performClassCombine ( N , DCI ) ; case <STR_LIT> : return performFCanonicalizeCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Src = N -> getOperand ( <NUM_LIT> ) ;


<s> if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( ! VT . isVector ( ) ) ; SDLoc SL ( N ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> ) { SDValue A = LHS . getOperand ( <NUM_LIT> ) ;

if ( A == LHS . getOperand ( <NUM_LIT> ) ) {


<s> if ( VT == <STR_LIT> && ! Subtarget -> hasFP32Denormals ( ) ) return DAG . getConstantFP ( <NUM_LIT> , SDLoc ( N ) , VT ) ; if ( VT == <STR_LIT> && ! Subtarget -> hasFP64Denormals ( ) ) return DAG . getConstantFP ( <NUM_LIT> , SDLoc ( N ) , VT ) ; if ( VT == <STR_LIT> && ! Subtarget -> hasFP16Denormals ( ) ) return DAG . getConstantFP ( <NUM_LIT> , SDLoc ( N ) , VT ) ; } if ( C . isNaN ( ) ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; APFloat CanonicalQNaN = APFloat :: getQNaN ( C . getSemantics ( ) ) ; if ( C . isSignaling ( ) ) {

return DAG . getConstantFP ( CanonicalQNaN , SDLoc ( N ) , VT ) ;


<s> ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! CFP ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; const APFloat & C = CFP -> getValueAPF ( ) ; if ( C . isDenormal ( ) ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && ! Subtarget -> hasFP32Denormals ( ) ) return DAG . getConstantFP ( <NUM_LIT> , SDLoc ( N ) , VT ) ; if ( VT == <STR_LIT> && ! Subtarget -> hasFP64Denormals ( ) ) return DAG . getConstantFP ( <NUM_LIT> , SDLoc ( N ) , VT ) ; if ( VT == <STR_LIT> && ! Subtarget -> hasFP16Denormals ( ) ) return DAG . getConstantFP ( <NUM_LIT> , SDLoc ( N ) , VT ) ; } if ( C . isNaN ( ) ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; APFloat CanonicalQNaN = APFloat :: getQNaN ( C . getSemantics ( ) ) ; if ( C . isSignaling ( ) ) { return DAG . getConstantFP ( CanonicalQNaN , SDLoc ( N ) , VT ) ; } if ( C . bitcastToAPInt ( ) != CanonicalQNaN . bitcastToAPInt ( ) ) return DAG . getConstantFP ( CanonicalQNaN , SDLoc ( N ) , VT ) ;


<s> SDValue Ptr = N -> getBasePtr ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc SL ( N ) ; unsigned AS = N -> getAddressSpace ( ) ; if ( Ptr . getOpcode ( ) == <STR_LIT> && AS != <ISA_LIT>AS :: PRIVATE_ADDRESS ) { SDValue NewPtr = performSHLPtrCombine ( Ptr . getNode ( ) , AS , DCI ) ; if ( NewPtr ) { SmallVector < SDValue , <NUM_LIT> > NewOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; NewOps [ N -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ] = NewPtr ; return SDValue ( DAG . UpdateNodeOperands ( N , NewOps ) , <NUM_LIT> ) ; }


<s> const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ;

return GV -> getType ( ) -> getAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS && <STR_LIT> ( TT ) ;


<s> bool <ISA_LIT>TargetLowering :: shouldEmitFixup ( const GlobalValue * GV ) const {

const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ;


<s> return ( GV -> getType ( ) -> getAddressSpace ( ) == <ISA_LIT>AS :: GLOBAL_ADDRESS || GV -> getType ( ) -> getAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS ) && ! shouldEmitFixup ( GV ) && ! getTargetMachine ( ) . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ;


<s> bool <ISA_LIT>TargetLowering :: shouldEmitGOTReloc ( const GlobalValue * GV ) const { return ( GV -> getType ( ) -> getAddressSpace ( ) == <ISA_LIT>AS :: GLOBAL_ADDRESS || GV -> getType ( ) -> getAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS ) && ! shouldEmitFixup ( GV ) && ! getTargetMachine ( ) . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ;


<s> MachineBasicBlock :: iterator SplitPoint ( & MI ) ; ++ SplitPoint ; if ( SplitPoint == BB -> end ( ) ) { MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; return BB ; }

MachineFunction * MF = BB -> getParent ( ) ;


<s> if ( SplitPoint == BB -> end ( ) ) { MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; return BB ; } MachineFunction * MF = BB -> getParent ( ) ; MachineBasicBlock * SplitBB = MF -> CreateMachineBasicBlock ( BB -> getBasicBlock ( ) ) ; MF -> insert ( ++ MachineFunction :: iterator ( BB ) , SplitBB ) ; SplitBB -> splice ( SplitBB -> begin ( ) , BB , SplitPoint , BB -> end ( ) ) ; SplitBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( SplitBB ) ; MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; return SplitBB ;


<s> for ( unsigned i = <NUM_LIT> , Dmask = OldDmask ; i <= Lane ; i ++ ) { assert ( Dmask ) ; Comp = countTrailingZeros ( Dmask ) ; Dmask &= ~ ( <NUM_LIT> << Comp ) ; } if ( Users [ Lane ] ) return ; Users [ Lane ] = * I ; NewDmask |= <NUM_LIT> << Comp ; } if ( NewDmask == OldDmask ) return ; std :: vector < SDValue > Ops ; Ops . insert ( Ops . end ( ) , Node -> op_begin ( ) , Node -> op_begin ( ) + DmaskIdx ) ; Ops . push_back ( DAG . getTargetConstant ( NewDmask , SDLoc ( Node ) , <STR_LIT> ) ) ; Ops . insert ( Ops . end ( ) , Node -> op_begin ( ) + DmaskIdx + <NUM_LIT> , Node -> op_end ( ) ) ; Node = ( MachineSDNode * ) DAG . UpdateNodeOperands ( Node , Ops ) ; if ( NewDmask && ( NewDmask & ( NewDmask - <NUM_LIT> ) ) == <NUM_LIT> ) { SDValue RC = DAG . getTargetConstant ( <STR_LIT> , SDLoc ( ) , <STR_LIT> ) ; SDNode * Copy = DAG . getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , SDLoc ( ) , Users [ Lane ] -> getValueType ( <NUM_LIT> ) , SDValue ( Node , <NUM_LIT> ) , RC ) ; DAG . ReplaceAllUsesWith ( Users [ Lane ] , Copy ) ; return ; } for ( unsigned i = <NUM_LIT> , Idx = <STR_LIT> ; i < <NUM_LIT> ; ++ i ) {


<s> } if ( Info . hasDispatchPtr ( ) ) { unsigned DispatchPtrReg = Info . addDispatchPtr ( TRI ) ; MF . addLiveIn ( DispatchPtrReg , & <STR_LIT> ) ; CCInfo . AllocateReg ( DispatchPtrReg ) ; } if ( Info . hasQueuePtr ( ) ) { unsigned QueuePtrReg = Info . addQueuePtr ( TRI ) ; MF . addLiveIn ( QueuePtrReg , & <STR_LIT> ) ; CCInfo . AllocateReg ( QueuePtrReg ) ; } if ( Info . hasKernargSegmentPtr ( ) ) { unsigned InputPtrReg = Info . addKernargSegmentPtr ( TRI ) ; MF . addLiveIn ( InputPtrReg , & <STR_LIT> ) ; CCInfo . AllocateReg ( InputPtrReg ) ; }


<s> MF . addLiveIn ( Reg , & <STR_LIT> ) ; CCInfo . AllocateReg ( Reg ) ; } if ( Info . hasWorkItemIDY ( ) ) { unsigned Reg = TRI . getPreloadedValue ( MF , <ISA_LIT>RegisterInfo :: WORKITEM_ID_Y ) ; MF . addLiveIn ( Reg , & <STR_LIT> ) ; CCInfo . AllocateReg ( Reg ) ; } if ( Info . hasWorkItemIDZ ( ) ) { unsigned Reg = TRI . getPreloadedValue ( MF , <ISA_LIT>RegisterInfo :: WORKITEM_ID_Z ) ; MF . addLiveIn ( Reg , & <STR_LIT> ) ; CCInfo . AllocateReg ( Reg ) ; }


<s> if ( Info . hasWorkItemIDY ( ) ) { unsigned Reg = TRI . getPreloadedValue ( MF , <ISA_LIT>RegisterInfo :: WORKITEM_ID_Y ) ; MF . addLiveIn ( Reg , & <STR_LIT> ) ; CCInfo . AllocateReg ( Reg ) ; } if ( Info . hasWorkItemIDZ ( ) ) { unsigned Reg = TRI . getPreloadedValue ( MF , <ISA_LIT>RegisterInfo :: WORKITEM_ID_Z ) ; MF . addLiveIn ( Reg , & <STR_LIT> ) ;


<s> if ( Info . hasWorkGroupIDY ( ) ) { unsigned Reg = Info . addWorkGroupIDY ( ) ; MF . addLiveIn ( Reg , & <STR_LIT> ) ; CCInfo . AllocateReg ( Reg ) ; } if ( Info . hasWorkGroupIDZ ( ) ) { unsigned Reg = Info . addWorkGroupIDZ ( ) ; MF . addLiveIn ( Reg , & <STR_LIT> ) ; CCInfo . AllocateReg ( Reg ) ; } if ( Info . hasWorkGroupInfo ( ) ) { unsigned Reg = Info . addWorkGroupInfo ( ) ; MF . addLiveIn ( Reg , & <STR_LIT> ) ; CCInfo . AllocateReg ( Reg ) ; } if ( Info . hasPrivateSegmentWaveByteOffset ( ) ) { unsigned PrivateSegmentWaveByteOffsetReg ; if ( IsShader ) { PrivateSegmentWaveByteOffsetReg = findFirstFreeSGPR ( CCInfo ) ; Info . setPrivateSegmentWaveByteOffset ( PrivateSegmentWaveByteOffsetReg ) ; } else PrivateSegmentWaveByteOffsetReg = Info . addPrivateSegmentWaveByteOffset ( ) ; MF . addLiveIn ( PrivateSegmentWaveByteOffsetReg , & <STR_LIT> ) ; CCInfo . AllocateReg ( PrivateSegmentWaveByteOffsetReg ) ;


<s> return false ; } if ( Subtarget -> hasUnalignedBufferAccess ( ) ) { if ( IsFast ) { * IsFast = ( AddrSpace == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS ) ? ( Align % <NUM_LIT> == <NUM_LIT> ) : true ; } return true ; } if ( VT . bitsLT ( <STR_LIT> ) ) return false ;


<s> unsigned InitReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , InitReg ) ; if ( UseGPRIdxMode ) { MachineInstr * SetOn = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( VGPRIndexMode :: SRC0_ENABLE ) ; SetOn -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; BuildMI ( MBB , std :: next ( I ) , DL , TII -> get ( <STR_LIT> ) ) ; } auto InsPt = loadM0FromVGPR ( TII , MBB , MI , InitReg , PhiReg , Offset , UseGPRIdxMode ) ; MachineBasicBlock * LoopBB = InsPt -> getParent ( ) ; if ( UseGPRIdxMode ) {

BuildMI ( * LoopBB , InsPt , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( SrcReg , RegState :: Undef , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Implicit ) ;


<s> BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( SrcReg , RegState :: Undef , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) ; } else { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( SrcReg , RegState :: Undef , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) ; } MI . eraseFromParent ( ) ; return & MBB ; } const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineBasicBlock :: iterator I ( & MI ) ; unsigned PhiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned InitReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , InitReg ) ; if ( UseGPRIdxMode ) { MachineInstr * SetOn = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( VGPRIndexMode :: SRC0_ENABLE ) ;

SetOn -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ;


<s> return splitKillBlock ( MI , BB ) ; case <STR_LIT> : { MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src0 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned SrcCond = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstLo = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DstHi = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , DstLo ) . addReg ( Src0 , <NUM_LIT> , <STR_LIT> ) . addReg ( Src1 , <NUM_LIT> , <STR_LIT> ) . addReg ( SrcCond ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , DstHi ) . addReg ( Src0 , <NUM_LIT> , <STR_LIT> ) . addReg ( Src1 , <NUM_LIT> , <STR_LIT> ) . addReg ( SrcCond ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( DstLo ) . addImm ( <STR_LIT> ) . addReg ( DstHi ) . addImm ( <STR_LIT> ) ; MI . eraseFromParent ( ) ;


<s> DiagnosticInfoUnsupported BadIntrin ( * DAG . getMachineFunction ( ) . getFunction ( ) , <STR_LIT> , DL . getDebugLoc ( ) ) ;

DAG . getContext ( ) -> diagnose ( BadIntrin ) ;


<s> static SDValue emitRemovedIntrinsicError ( SelectionDAG & DAG , const SDLoc & DL , EVT VT ) { DiagnosticInfoUnsupported BadIntrin ( * DAG . getMachineFunction ( ) . getFunction ( ) , <STR_LIT> , DL . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( BadIntrin ) ;


<s> DiagnosticInfoUnsupported BadIntrin ( * DAG . getMachineFunction ( ) . getFunction ( ) , <STR_LIT> , DL . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( BadIntrin ) ;


<s> case <STR_LIT> : case <STR_LIT> : { Value * Ptr = II -> getArgOperand ( <NUM_LIT> ) ; AccessTy = II -> getType ( ) ; Ops . push_back ( Ptr ) ; return true ; } default :


<s> case 's' : case 'r' : switch ( VT . getSizeInBits ( ) ) { default : return std :: make_pair ( <NUM_LIT> , nullptr ) ; case <NUM_LIT> : case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } case 'v' : switch ( VT . getSizeInBits ( ) ) { default : return std :: make_pair ( <NUM_LIT> , nullptr ) ; case <NUM_LIT> : case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } } if ( Constraint . size ( ) > <NUM_LIT> ) { const TargetRegisterClass * RC = nullptr ; if ( Constraint [ <NUM_LIT> ] == 'v' ) { RC = & <STR_LIT> ; } else if ( Constraint [ <NUM_LIT> ] == 's' ) { RC = & <STR_LIT> ; } if ( RC ) { uint32_t Idx ;

bool Failed = Constraint . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , Idx ) ;


<s> uint32_t StructOffset = ( AS == AMDGPUA<ISA_LIT> . LOCAL_ADDRESS ) ? <NUM_LIT> : <NUM_LIT> ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , QueuePtr , DAG . getConstant ( StructOffset , DL , <STR_LIT> ) ) ; Value * V = UndefValue :: get ( PointerType :: get ( Type :: getInt8Ty ( * DAG . getContext ( ) ) , AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS ) ) ; MachinePointerInfo PtrInfo ( V , StructOffset ) ;

return DAG . getLoad ( <STR_LIT> , DL , QueuePtr . getValue ( <NUM_LIT> ) , Ptr , PtrInfo , MinAlign ( <NUM_LIT> , StructOffset ) , MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ;


<s> Info . ptrVal = CI . getOperand ( <NUM_LIT> ) ; Info . align = <NUM_LIT> ; const ConstantInt * Vol = dyn_cast < ConstantInt > ( CI . getOperand ( <NUM_LIT> ) ) ; Info . vol = ! Vol || ! Vol -> isNullValue ( ) ; Info . readMem = true ; Info . writeMem = true ; return true ; } default :


<s> Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getType ( ) ) ; Info . ptrVal = CI . getOperand ( <NUM_LIT> ) ; Info . align = <NUM_LIT> ; const ConstantInt * Vol = dyn_cast < ConstantInt > ( CI . getOperand ( <NUM_LIT> ) ) ; Info . vol = ! Vol || ! Vol -> isNullValue ( ) ; Info . readMem = true ; Info . writeMem = true ; return true ; } default : return false ;


<s> static bool isFlatGlobalAddrSpace ( unsigned AS , <ISA_LIT>AS AMDGPUA<ISA_LIT> ) {

return AS == AMDGPUA<ISA_LIT> . GLOBAL_ADDRESS || AS == AMDGPUA<ISA_LIT> . FLAT_ADDRESS || AS == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS ;


<s> bool <ISA_LIT>TargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { VT = VT . getScalarType ( ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : return Subtarget -> hasFP32Denormals ( ) && Subtarget -> hasFastFMAF32 ( ) ; case <STR_LIT> : return true ;


<s> } else if ( AS == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS ) { if ( AM . BaseOffs % <NUM_LIT> != <NUM_LIT> ) return isLegalMUBUFAddressingMode ( AM ) ; if ( DL . getTypeStoreSize ( Ty ) < <NUM_LIT> ) return isLegalMUBUFAddressingMode ( AM ) ; if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs / <NUM_LIT> ) ) return false ; } else if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs / <NUM_LIT> ) ) return false ; } else if ( Subtarget -> getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ; } else llvm_unreachable ( <STR_LIT> ) ; if ( AM . Scale == <NUM_LIT> ) return true ; if ( AM . Scale == <NUM_LIT> && AM . HasBaseReg ) return true ; return false ; } else if ( AS == AMDGPUA<ISA_LIT> . PRIVATE_ADDRESS ) { return isLegalMUBUFAddressingMode ( AM ) ; } else if ( AS == AMDGPUA<ISA_LIT> . LOCAL_ADDRESS || AS == AMDGPUA<ISA_LIT> . REGION_ADDRESS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ;


<s> if ( DL . getTypeStoreSize ( Ty ) < <NUM_LIT> ) return isLegalMUBUFAddressingMode ( AM ) ; if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs / <NUM_LIT> ) ) return false ; } else if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs / <NUM_LIT> ) ) return false ; } else if ( Subtarget -> getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ; } else llvm_unreachable ( <STR_LIT> ) ; if ( AM . Scale == <NUM_LIT> ) return true ; if ( AM . Scale == <NUM_LIT> && AM . HasBaseReg ) return true ;


<s> bool <ISA_LIT>TargetLowering :: isMemOpUniform ( const SDNode * N ) const { const MemSDNode * MemNode = cast < MemSDNode > ( N ) ;

return <STR_LIT> ( MemNode -> getMemOperand ( ) ) ;


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const {

return ( GA -> getAddressSpace ( ) == AMDGPUA<ISA_LIT> . GLOBAL_ADDRESS || GA -> getAddressSpace ( ) == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS ) && ! shouldEmitGOTReloc ( GA -> getGlobal ( ) ) ;


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return ( GA -> getAddressSpace ( ) == AMDGPUA<ISA_LIT> . GLOBAL_ADDRESS || GA -> getAddressSpace ( ) == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS ) && ! shouldEmitGOTReloc ( GA -> getGlobal ( ) ) ;


<s> return ToResultReg . getNode ( ) ; } } SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < Node -> getNumOperands ( ) ; ++ i ) { if ( ! isFrameIndexOp ( Node -> getOperand ( i ) ) ) { Ops . push_back ( Node -> getOperand ( i ) ) ; continue ; } SDLoc DL ( Node ) ; Ops . push_back ( SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Node -> getOperand ( i ) . getValueType ( ) , Node -> getOperand ( i ) ) , <NUM_LIT> ) ) ;


<s> Result = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; } else { assert ( CIdx -> getZExtValue ( ) == <NUM_LIT> ) ; } if ( ResultVT . bitsLT ( <STR_LIT> ) ) Result = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Result ) ; return DAG . getNode ( <STR_LIT> , SL , ResultVT , Result ) ; } SDValue Sixteen = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue ScaledIdx = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Idx , Sixteen ) ; SDValue BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Vec ) ;

SDValue Elt = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BC , ScaledIdx ) ;


<s> if ( ! Unsafe && VT == <STR_LIT> && Subtarget -> hasFP32Denormals ( ) ) return SDValue ( ) ; if ( const ConstantFPSDNode * CLHS = dyn_cast < ConstantFPSDNode > ( LHS ) ) { if ( Unsafe || VT == <STR_LIT> || VT == <STR_LIT> ) { if ( CLHS -> isExactlyValue ( <NUM_LIT> ) ) { if ( RHS . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SL , VT , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; } if ( CLHS -> isExactlyValue ( - <NUM_LIT> ) ) { SDValue FNegRHS = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; return DAG . getNode ( <STR_LIT> , SL , VT , FNegRHS ) ; } } } const SDNodeFlags * Flags = Op -> getFlags ( ) ; if ( Unsafe || Flags -> hasAllowReciprocal ( ) ) {


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; bool Unsafe = DAG . getTarget ( ) . Options . UnsafeFPMath ; if ( ! Unsafe && VT == <STR_LIT> && Subtarget -> hasFP32Denormals ( ) ) return SDValue ( ) ; if ( const ConstantFPSDNode * CLHS = dyn_cast < ConstantFPSDNode > ( LHS ) ) { if ( Unsafe || VT == <STR_LIT> || VT == <STR_LIT> ) { if ( CLHS -> isExactlyValue ( <NUM_LIT> ) ) { if ( RHS . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SL , VT , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; } if ( CLHS -> isExactlyValue ( - <NUM_LIT> ) ) { SDValue FNegRHS = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; return DAG . getNode ( <STR_LIT> , SL , VT , FNegRHS ) ; } } }

const SDNodeFlags * Flags = Op -> getFlags ( ) ;


<s> assert ( ! IsKernel || ( Info -> hasWorkGroupIDX ( ) && Info -> hasWorkItemIDX ( ) ) ) ; } if ( IsEntryFunc ) { allocateSpecialInputVGPRs ( CCInfo , MF , * TRI , * Info ) ; allocateHSAUserSGPRs ( CCInfo , MF , * TRI , * Info ) ; } if ( IsKernel ) { analyzeFormalArgumentsCompute ( CCInfo , Ins ) ; } else { CCAssignFn * AssignFn = CCAssignFnForCall ( CallConv , isVarArg ) ; CCInfo . AnalyzeFormalArguments ( Splits , AssignFn ) ; } SmallVector < SDValue , <NUM_LIT> > Chains ; for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) , ArgIdx = <NUM_LIT> ; i != e ; ++ i ) { const <STR_LIT> & Arg = Ins [ i ] ; if ( Skipped [ i ] ) { InVals . push_back ( DAG . getUNDEF ( Arg . VT ) ) ; continue ; } CCValAssign & VA = ArgLocs [ ArgIdx ++ ] ; MVT VT = VA . getLocVT ( ) ; if ( IsEntryFunc && VA . isMemLoc ( ) ) { VT = Ins [ i ] . VT ; EVT MemVT = VA . getLocVT ( ) ; const uint64_t Offset = Subtarget -> getExplicitKernelArgOffset ( MF ) + VA . getLocMemOffset ( ) ; Info -> setABIArgOffset ( Offset + MemVT . getStoreSize ( ) ) ; SDValue Arg = lowerKernargMemParameter ( DAG , VT , MemVT , DL , Chain , Offset , Ins [ i ] . Flags . isSExt ( ) , & Ins [ i ] ) ; Chains . push_back ( Arg . getValue ( <NUM_LIT> ) ) ; auto * ParamTy = dyn_cast < PointerType > ( FType -> getParamType ( Ins [ i ] . getOrigArgIndex ( ) ) ) ; if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS && ParamTy && ParamTy -> getAddressSpace ( ) == <ISA_LIT>AS :: LOCAL_ADDRESS ) { Arg = DAG . getNode ( <STR_LIT> , DL , Arg . getValueType ( ) , Arg , DAG . getValueType ( <STR_LIT> ) ) ; } InVals . push_back ( Arg ) ; continue ; } if ( VA . isMemLoc ( ) ) report_fatal_error ( <STR_LIT> ) ;

assert ( VA . isRegLoc ( ) && <STR_LIT> ) ;


<s> SDLoc DL ( GSD ) ; const GlobalValue * GV = GSD -> getGlobal ( ) ; EVT PtrVT = Op . getValueType ( ) ; if ( shouldEmitFixup ( GV ) ) return buildPCRelGlobalAddress ( DAG , GV , DL , GSD -> getOffset ( ) , PtrVT ) ;

else if ( shouldEmitPCReloc ( GV ) ) return buildPCRelGlobalAddress ( DAG , GV , DL , GSD -> getOffset ( ) , PtrVT , <ISA_LIT>InstrInfo :: MO_REL32 ) ;


<s> SDLoc SL ( Op ) ; SDValue Param = lowerKernargMemParameter ( DAG , <STR_LIT> , <STR_LIT> , SL , DAG . getEntryNode ( ) , Offset , false ) ;

return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Param , DAG . getValueType ( VT ) ) ;


<s> SDValue Ops [ ] = { M -> getOperand ( <NUM_LIT> ) , M -> getOperand ( <NUM_LIT> ) , M -> getOperand ( <NUM_LIT> ) } ; return DAG . getMemIntrinsicNode ( Opc , SDLoc ( Op ) , M -> getVTList ( ) , Ops , M -> getMemoryVT ( ) , M -> getMemOperand ( ) ) ; } case <STR_LIT> : case <STR_LIT> : { SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Opc = ( IntrID == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; EVT VT = Op . getValueType ( ) ; EVT IntVT = VT . changeTypeToInteger ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( MFI -> getBufferPSV ( ) ) , MachineMemOperand :: MOLoad , VT . getStoreSize ( ) , VT . getStoreSize ( ) ) ; return DAG . getMemIntrinsicNode ( Opc , DL , Op -> getVTList ( ) , Ops , IntVT , MMO ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : {

const ConstantSDNode * DMask = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ;