<s> SDLoc DL ( N ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; if ( DCI . isAfterLegalizeVectorOps ( ) && SrcVT == <STR_LIT> ) { if ( DAG . MaskedValueIsZero ( Src , APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ) { SDValue Cvt = DAG . getNode ( <STR_LIT> , DL , VT , Src ) ; DCI . AddToWorklist ( Cvt . getNode ( ) ) ; return Cvt ; } } if ( ! DCI . isBeforeLegalize ( ) || ! SrcVT . isVector ( ) || SrcVT . getVectorElementType ( ) != <STR_LIT> ) { return SDValue ( ) ; } assert ( DCI . isBeforeLegalize ( ) && <STR_LIT> ) ; unsigned NElts = SrcVT . getVectorNumElements ( ) ; if ( ! SrcVT . isSimple ( ) && NElts != <NUM_LIT> ) return SDValue ( ) ; if ( <STR_LIT> ( Src . getNode ( ) ) && Src . hasOneUse ( ) ) { EVT LoadVT = getEquivalentMemType ( * DAG . getContext ( ) , SrcVT ) ; EVT RegVT = getEquivalentLoadRegType ( * DAG . getContext ( ) , SrcVT ) ; EVT FloatVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NElts ) ; LoadSDNode * Load = cast < LoadSDNode > ( Src ) ; unsigned AS = Load -> getAddressSpace ( ) ; unsigned Align = Load -> getAlignment ( ) ; Type * Ty = LoadVT . getTypeForEVT ( * DAG . getContext ( ) ) ; unsigned ABIAlignment = DAG . getDataLayout ( ) . getABITypeAlignment ( Ty ) ; if ( Align < ABIAlignment && ! allowsMisalignedMemoryAccesses ( LoadVT , AS , Align , nullptr ) ) { return SDValue ( ) ; } SDValue NewLoad = DAG . getExtLoad ( <STR_LIT> , DL , RegVT , Load -> getChain ( ) , Load -> getBasePtr ( ) , LoadVT , Load -> getMemOperand ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Load , <NUM_LIT> ) , NewLoad . getValue ( <NUM_LIT> ) ) ; SmallVector < SDValue , <NUM_LIT> > Elts ; if ( RegVT . isVector ( ) ) DAG . ExtractVectorElements ( NewLoad , Elts ) ; else Elts . push_back ( NewLoad ) ;

SmallVector < SDValue , <NUM_LIT> > Ops ;


<s> if ( TII -> isMIMG ( Node -> getMachineOpcode ( ) ) ) adjustWritemask ( Node , DAG ) ; if ( Node -> getMachineOpcode ( ) == <STR_LIT> || Node -> getMachineOpcode ( ) == <STR_LIT> ) { legalizeTargetIndependentNode ( Node , DAG ) ; return Node ; }


<s> const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ;

return TII -> isInlineConstant ( Imm ) ;


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; }


<s> static unsigned SubIdx2Lane ( unsigned Idx ) { switch ( Idx ) { default : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ;


<s> MachineSDNode * <ISA_LIT>TargetLowering :: wrapAddr64Rsrc ( SelectionDAG & DAG , SDLoc DL , SDValue Ptr ) const { const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; const SDValue Ops0 [ ] = { DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , buildSMovImm32 ( DAG , DL , <NUM_LIT> ) , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , buildSMovImm32 ( DAG , DL , TII -> getDefaultRsrcDataFormat ( ) >> <NUM_LIT> ) , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) } ; SDValue SubRegHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops0 ) , <NUM_LIT> ) ;


<s> const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; const SDValue Ops0 [ ] = { DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , buildSMovImm32 ( DAG , DL , <NUM_LIT> ) , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , buildSMovImm32 ( DAG , DL , TII -> getDefaultRsrcDataFormat ( ) >> <NUM_LIT> ) , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) } ; SDValue SubRegHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops0 ) , <NUM_LIT> ) ; const SDValue Ops1 [ ] = { DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , Ptr , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , SubRegHi , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) } ;

return DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops1 ) ;


<s> if ( AddrSpace == <ISA_LIT>AS :: LOCAL_ADDRESS ) { return Align % <NUM_LIT> == <NUM_LIT> ; } if ( VT . bitsLT ( <STR_LIT> ) ) return false ; if ( IsFast ) * IsFast = true ;

return VT . bitsGT ( <STR_LIT> ) && Align % <NUM_LIT> == <NUM_LIT> ;


<s> static bool isFlatGlobalAddrSpace ( unsigned AS ) {

return AS == <ISA_LIT>AS :: GLOBAL_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS || AS == <ISA_LIT>AS :: CONSTANT_ADDRESS || AS > <ISA_LIT>AS :: MAX_<ISA_LIT>_ADDRESS ;


<s> default : return false ; } } case <ISA_LIT>AS :: LOCAL_ADDRESS : case <ISA_LIT>AS :: REGION_ADDRESS : { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ; if ( AM . Scale == <NUM_LIT> ) return true ; if ( AM . Scale == <NUM_LIT> && AM . HasBaseReg ) return true ; return false ; } case <ISA_LIT>AS :: FLAT_ADDRESS : return isLegalFlatAddressingMode ( AM ) ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> if ( RHS . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SL , VT , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; } } if ( Unsafe ) { SDValue Recip = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ;

return DAG . getNode ( <STR_LIT> , SL , VT , LHS , Recip ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFastFDIV ( SDValue Op , SelectionDAG & DAG ) const { SDLoc SL ( Op ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; bool Unsafe = DAG . getTarget ( ) . Options . UnsafeFPMath ; if ( const ConstantFPSDNode * CLHS = dyn_cast < ConstantFPSDNode > ( LHS ) ) { if ( ( Unsafe || ( VT == <STR_LIT> && ! Subtarget -> hasFP32Denormals ( ) ) ) && CLHS -> isExactlyValue ( <NUM_LIT> ) ) { if ( RHS . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SL , VT , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; } } if ( Unsafe ) {

SDValue Recip = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ;


<s> unsigned InputPtrRegLo = TRI -> getPhysRegSubReg ( InputPtrReg , & <STR_LIT> , <NUM_LIT> ) ; unsigned InputPtrRegHi = TRI -> getPhysRegSubReg ( InputPtrReg , & <STR_LIT> , <NUM_LIT> ) ; unsigned ScratchPtrReg = TRI -> getPreloadedValue ( MF , <ISA_LIT>RegisterInfo :: SCRATCH_PTR ) ; unsigned ScratchPtrRegLo = TRI -> getPhysRegSubReg ( ScratchPtrReg , & <STR_LIT> , <NUM_LIT> ) ; unsigned ScratchPtrRegHi = TRI -> getPhysRegSubReg ( ScratchPtrReg , & <STR_LIT> , <NUM_LIT> ) ; CCInfo . AllocateReg ( InputPtrRegLo ) ; CCInfo . AllocateReg ( InputPtrRegHi ) ; CCInfo . AllocateReg ( ScratchPtrRegLo ) ; CCInfo . AllocateReg ( ScratchPtrRegHi ) ; MF . addLiveIn ( InputPtrReg , & <STR_LIT> ) ; MF . addLiveIn ( ScratchPtrReg , & <STR_LIT> ) ; } if ( Info -> getShaderType ( ) == ShaderType :: COMPUTE ) { getOriginalFunctionArgs ( DAG , DAG . getMachineFunction ( ) . getFunction ( ) , Ins , Splits ) ; } AnalyzeFormalArguments ( CCInfo , Splits ) ; SmallVector < SDValue , <NUM_LIT> > Chains ; for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) , ArgIdx = <NUM_LIT> ; i != e ; ++ i ) { const <STR_LIT> & Arg = Ins [ i ] ; if ( Skipped [ i ] ) { InVals . push_back ( DAG . getUNDEF ( Arg . VT ) ) ; continue ; } CCValAssign & VA = ArgLocs [ ArgIdx ++ ] ; MVT VT = VA . getLocVT ( ) ; if ( VA . isMemLoc ( ) ) { VT = Ins [ i ] . VT ; EVT MemVT = Splits [ i ] . VT ; const unsigned Offset = Subtarget -> getExplicitKernelArgOffset ( ) + VA . getLocMemOffset ( ) ; SDValue Arg = LowerParameter ( DAG , VT , MemVT , DL , Chain , Offset , Ins [ i ] . Flags . isSExt ( ) ) ; Chains . push_back ( Arg . getValue ( <NUM_LIT> ) ) ; const PointerType * ParamTy = dyn_cast < PointerType > ( FType -> getParamType ( Ins [ i ] . getOrigArgIndex ( ) ) ) ; if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS && ParamTy && ParamTy -> getAddressSpace ( ) == <ISA_LIT>AS :: LOCAL_ADDRESS ) {

Arg = DAG . getNode ( <STR_LIT> , DL , Arg . getValueType ( ) , Arg , DAG . getValueType ( <STR_LIT> ) ) ;


<s> MVT PtrVT = getPointerTy ( DL , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; PointerType * PtrTy = PointerType :: get ( Ty , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; SDValue BasePtr = DAG . getCopyFromReg ( Chain , SL , MRI . getLiveInVirtReg ( InputPtrReg ) , PtrVT ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( Offset , SL , PtrVT ) ) ; SDValue PtrOffset = DAG . getUNDEF ( PtrVT ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ) ; unsigned Align = DL . getABITypeAlignment ( Ty ) ; if ( VT != MemVT && VT . isFloatingPoint ( ) ) { assert ( VT . getScalarType ( ) == <STR_LIT> && MemVT . getScalarType ( ) == <STR_LIT> ) ; EVT IVT = toIntegerVT ( VT ) ; EVT MemIVT = toIntegerVT ( MemVT ) ; SDValue Load = DAG . getLoad ( <STR_LIT> , <STR_LIT> , IVT , SL , Chain , Ptr , PtrOffset , PtrInfo , MemIVT , false , true , true , Align ) ;


<s> const DataLayout & DL = DAG . getDataLayout ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( Subtarget -> getRegisterInfo ( ) ) ; unsigned InputPtrReg = TRI -> getPreloadedValue ( MF , <ISA_LIT>RegisterInfo :: INPUT_PTR ) ; Type * Ty = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; MVT PtrVT = getPointerTy ( DL , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; PointerType * PtrTy = PointerType :: get ( Ty , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; SDValue BasePtr = DAG . getCopyFromReg ( Chain , SL , MRI . getLiveInVirtReg ( InputPtrReg ) , PtrVT ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( Offset , SL , PtrVT ) ) ; SDValue PtrOffset = DAG . getUNDEF ( PtrVT ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ) ; unsigned Align = DL . getABITypeAlignment ( Ty ) ; if ( VT != MemVT && VT . isFloatingPoint ( ) ) { assert ( VT . getScalarType ( ) == <STR_LIT> && MemVT . getScalarType ( ) == <STR_LIT> ) ; EVT IVT = toIntegerVT ( VT ) ; EVT MemIVT = toIntegerVT ( MemVT ) ; SDValue Load = DAG . getLoad ( <STR_LIT> , <STR_LIT> , IVT , SL , Chain , Ptr , PtrOffset , PtrInfo , MemIVT , false , true , true , Align ) ; SDValue Ops [ ] = { DAG . getNode ( <STR_LIT> , SL , VT , Load ) , Load . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( Ops , SL ) ; } <STR_LIT> ExtTy = Signed ? <STR_LIT> : <STR_LIT> ;

return DAG . getLoad ( <STR_LIT> , ExtTy , VT , SL , Chain , Ptr , PtrOffset , PtrInfo , MemVT , false , true , true , Align ) ;


<s> return <STR_LIT> ( VT . getSizeInBits ( ) ) ;


<s> static EVT toIntegerVT ( EVT VT ) { if ( VT . isVector ( ) ) return VT . changeVectorElementTypeToInteger ( ) ; return <STR_LIT> ( VT . getSizeInBits ( ) ) ;


<s> case <NUM_LIT> : RC = & <STR_LIT> ; break ; case <NUM_LIT> : RC = & <STR_LIT> ; break ; case <NUM_LIT> : RC = & <STR_LIT> ; break ; } unsigned NewOpcode = TII -> getMaskedMIMGOp ( MI . getOpcode ( ) , BitsSet ) ; MI . setDesc ( TII -> get ( NewOpcode ) ) ; MRI . setRegClass ( VReg , RC ) ; return ; } int NoRetAtomicOp = <STR_LIT> ( MI . getOpcode ( ) ) ; if ( NoRetAtomicOp != - <NUM_LIT> ) { if ( ! Node -> hasAnyUseOfValue ( <NUM_LIT> ) ) { MI . setDesc ( TII -> get ( NoRetAtomicOp ) ) ; MI . RemoveOperand ( <NUM_LIT> ) ; return ; } if ( ( Node -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) && Node -> use_begin ( ) -> isMachineOpcode ( ) && Node -> use_begin ( ) -> getMachineOpcode ( ) == <STR_LIT> && ! Node -> use_begin ( ) -> hasAnyUseOfValue ( <NUM_LIT> ) ) ) {

unsigned Def = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> std :: vector < SDValue > Ops ; Ops . insert ( Ops . end ( ) , Node -> op_begin ( ) , Node -> op_begin ( ) + DmaskIdx ) ; Ops . push_back ( DAG . getTargetConstant ( NewDmask , SDLoc ( Node ) , <STR_LIT> ) ) ; Ops . insert ( Ops . end ( ) , Node -> op_begin ( ) + DmaskIdx + <NUM_LIT> , Node -> op_end ( ) ) ; Node = ( MachineSDNode * ) DAG . UpdateNodeOperands ( Node , Ops ) ; if ( NewDmask && ( NewDmask & ( NewDmask - <NUM_LIT> ) ) == <NUM_LIT> ) { SDValue RC = DAG . getTargetConstant ( <STR_LIT> , SDLoc ( ) , <STR_LIT> ) ; SDNode * Copy = DAG . getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , SDLoc ( ) , Users [ Lane ] -> getValueType ( <NUM_LIT> ) , SDValue ( Node , <NUM_LIT> ) , RC ) ; DAG . ReplaceAllUsesWith ( Users [ Lane ] , Copy ) ; return ; } for ( unsigned i = <NUM_LIT> , Idx = <STR_LIT> ; i < <NUM_LIT> ; ++ i ) { SDNode * User = Users [ i ] ; if ( ! User ) continue ; SDValue Op = DAG . getTargetConstant ( Idx , SDLoc ( User ) , <STR_LIT> ) ; DAG . UpdateNodeOperands ( User , User -> getOperand ( <NUM_LIT> ) , Op ) ; switch ( Idx ) {


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , bool * IsFast ) const { if ( IsFast ) * IsFast = false ; if ( ! VT . isSimple ( ) || VT == <STR_LIT> ) return false ; if ( AddrSpace == <ISA_LIT>AS :: LOCAL_ADDRESS || AddrSpace == <ISA_LIT>AS :: REGION_ADDRESS ) { bool AlignedBy4 = ( Align % <NUM_LIT> == <NUM_LIT> ) ; if ( IsFast ) * IsFast = AlignedBy4 ; return AlignedBy4 ; } if ( Subtarget -> hasUnalignedBufferAccess ( ) ) {


<s> if ( const ConstantFPSDNode * Node = dyn_cast < ConstantFPSDNode > ( N ) ) { if ( TII -> isInlineConstant ( Node -> getValueAPF ( ) . bitcastToAPInt ( ) ) ) return <NUM_LIT> ;

if ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) return FloatToBits ( Node -> getValueAPF ( ) . convertToFloat ( ) ) ;


<s> return isUInt < <NUM_LIT> > ( OffsetSize ) ; } case <ISA_LIT>AS :: CONSTANT_ADDRESS : { if ( STI . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) return isUInt < <NUM_LIT> > ( OffsetSize ) ; else return ( OffsetSize % <NUM_LIT> == <NUM_LIT> ) && isUInt < <NUM_LIT> > ( OffsetSize / <NUM_LIT> ) ; } case <ISA_LIT>AS :: LOCAL_ADDRESS : case <ISA_LIT>AS :: REGION_ADDRESS : { return isUInt < <NUM_LIT> > ( OffsetSize ) ; } case <ISA_LIT>AS :: PRIVATE_ADDRESS : default : return <NUM_LIT> ;


<s> static std :: pair < unsigned , int > computeIndirectRegAndOffset ( const <ISA_LIT>RegisterInfo & TRI , const TargetRegisterClass * SuperRC , unsigned VecReg , int Offset ) { int NumElts = SuperRC -> getSize ( ) / <NUM_LIT> ;

if ( Offset >= NumElts || Offset < <NUM_LIT> ) return std :: make_pair ( <STR_LIT> , Offset ) ;


<s> if ( Offset >= NumElts || Offset < <NUM_LIT> ) return std :: make_pair ( <STR_LIT> , Offset ) ;

return std :: make_pair ( <STR_LIT> + Offset , <NUM_LIT> ) ;


<s> void <ISA_LIT>TargetLowering :: createDebuggerPrologueStackObjects ( MachineFunction & MF ) const { <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int ObjectIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { ObjectIdx = MF . getFrameInfo ( ) -> CreateFixedObject ( <NUM_LIT> , i * <NUM_LIT> , true ) ; Info -> setDebuggerWorkGroupIDStackObjectIndex ( i , ObjectIdx ) ;

ObjectIdx = MF . getFrameInfo ( ) -> CreateFixedObject ( <NUM_LIT> , i * <NUM_LIT> + <NUM_LIT> , true ) ;


<s> Info -> setDebuggerWorkGroupIDStackObjectIndex ( i , ObjectIdx ) ; ObjectIdx = MF . getFrameInfo ( ) -> CreateFixedObject ( <NUM_LIT> , i * <NUM_LIT> + <NUM_LIT> , true ) ; Info -> setDebuggerWorkItemIDStackObjectIndex ( i , ObjectIdx ) ;


<s> } const MCInstrDesc & MovRelDesc = TII -> get ( <STR_LIT> ) ; if ( setM0ToIndexFromSGPR ( TII , MRI , MI , Offset ) ) { MachineBasicBlock :: iterator I ( & MI ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineInstr * MovRel = BuildMI ( MBB , I , DL , MovRelDesc ) . addReg ( SrcVec -> getReg ( ) , RegState :: Undef , SubReg ) . addOperand ( * Val ) . addReg ( Dst , RegState :: ImplicitDefine ) . addReg ( SrcVec -> getReg ( ) , RegState :: Implicit ) ; const int ImpDefIdx = MovRelDesc . getNumOperands ( ) + MovRelDesc . getNumImplicitUses ( ) ; const int ImpUseIdx = ImpDefIdx + <NUM_LIT> ; MovRel -> tieOperands ( ImpDefIdx , ImpUseIdx ) ; MI . eraseFromParent ( ) ; return & MBB ; } if ( Val -> isReg ( ) ) MRI . clearKillFlags ( Val -> getReg ( ) ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned PhiReg = MRI . createVirtualRegister ( VecRC ) ; MachineInstr * MovRel = BuildMI ( * MF , DL , MovRelDesc ) . addReg ( PhiReg , RegState :: Undef , SubReg ) . addOperand ( * Val ) . addReg ( Dst , RegState :: ImplicitDefine ) . addReg ( PhiReg , RegState :: Implicit ) ;


<s> const MachineOperand * SrcVec = TII -> getNamedOperand ( MI , <STR_LIT> :: src ) ; int Offset = TII -> getNamedOperand ( MI , <STR_LIT> :: offset ) -> getImm ( ) ; const TargetRegisterClass * VecRC = MRI . getRegClass ( SrcVec -> getReg ( ) ) ; unsigned SubReg ; std :: tie ( SubReg , Offset ) = computeIndirectRegAndOffset ( TRI , VecRC , SrcVec -> getReg ( ) , Offset ) ; if ( setM0ToIndexFromSGPR ( TII , MRI , MI , Offset ) ) { MachineBasicBlock :: iterator I ( & MI ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( SrcVec -> getReg ( ) , RegState :: Undef , SubReg ) . addReg ( SrcVec -> getReg ( ) , RegState :: Implicit ) ; MI . eraseFromParent ( ) ; return & MBB ; } const DebugLoc & DL = MI . getDebugLoc ( ) ;


<s> case <STR_LIT> : { const <ISA_LIT>InstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; MachineFunction * MF = BB -> getParent ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( MFI -> LDSSize ) ; MI . eraseFromParent ( ) ; return BB ; } case <STR_LIT> :


<s> DAG . getContext ( ) -> diagnose ( BadIntrin ) ; return DAG . getUNDEF ( VT ) ;


<s> DiagnosticInfoUnsupported BadIntrin ( * DAG . getMachineFunction ( ) . getFunction ( ) , <STR_LIT> , DL . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( BadIntrin ) ; return DAG . getUNDEF ( VT ) ;


<s> DAG . getContext ( ) -> diagnose ( BadIntrin ) ;


<s> report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ) ; } if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS && Subtarget -> getRegisterInfo ( ) -> regsOverlap ( Reg , <STR_LIT> ) ) { report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ) ; } switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return Reg ; break ;


<s> unsigned <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , EVT VT , SelectionDAG & DAG ) const { unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( Reg == <STR_LIT> ) { report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ) ; } if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS && Subtarget -> getRegisterInfo ( ) -> regsOverlap ( Reg , <STR_LIT> ) ) { report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ) ; } switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return Reg ; break ; case <STR_LIT> : case <STR_LIT> : if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return Reg ;


<s> return static_cast < const <ISA_LIT>Subtarget * > ( Subtarget ) ;


<s> const <ISA_LIT>Subtarget * <ISA_LIT>TargetLowering :: getSubtarget ( ) const { return static_cast < const <ISA_LIT>Subtarget * > ( Subtarget ) ;


<s> bool <ISA_LIT>TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & CI , unsigned IntrID ) const { switch ( IntrID ) { case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>TargetLowering :: isCFIntrinsic ( const SDNode * Intr ) const { if ( Intr -> getOpcode ( ) != <STR_LIT> ) return false ; switch ( cast < ConstantSDNode > ( Intr -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) {


<s> static bool isKnownNeverSNan ( SelectionDAG & DAG , SDValue Op ) {

if ( ! DAG . getTargetLoweringInfo ( ) . hasFloatingPointExceptions ( ) ) return true ;


<s> switch ( AS ) { case <ISA_LIT>AS :: GLOBAL_ADDRESS : { if ( Subtarget -> getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { return isLegalFlatAddressingMode ( AM ) ; } return isLegalMUBUFAddressingMode ( AM ) ; } case <ISA_LIT>AS :: CONSTANT_ADDRESS : { if ( AM . BaseOffs % <NUM_LIT> != <NUM_LIT> ) return isLegalMUBUFAddressingMode ( AM ) ; if ( DL . getTypeStoreSize ( Ty ) < <NUM_LIT> ) return isLegalMUBUFAddressingMode ( AM ) ; if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs / <NUM_LIT> ) ) return false ; } else if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs / <NUM_LIT> ) ) return false ; } else if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ; } else llvm_unreachable ( <STR_LIT> ) ; if ( AM . Scale == <NUM_LIT> ) return true ; if ( AM . Scale == <NUM_LIT> && AM . HasBaseReg ) return true ; return false ; } case <ISA_LIT>AS :: PRIVATE_ADDRESS : return isLegalMUBUFAddressingMode ( AM ) ; case <ISA_LIT>AS :: LOCAL_ADDRESS : case <ISA_LIT>AS :: REGION_ADDRESS : { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ; if ( AM . Scale == <NUM_LIT> ) return true ; if ( AM . Scale == <NUM_LIT> && AM . HasBaseReg ) return true ; return false ; }


<s> const Value * Ptr = MemNode -> getMemOperand ( ) -> getValue ( ) ;

if ( ! Ptr || isa < UndefValue > ( Ptr ) || isa < Argument > ( Ptr ) || isa < Constant > ( Ptr ) || isa < GlobalValue > ( Ptr ) ) return true ;


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return GA -> getAddressSpace ( ) == <ISA_LIT>AS :: GLOBAL_ADDRESS && ! shouldEmitGOTReloc ( GA -> getGlobal ( ) , getTargetMachine ( ) ) ;


<s> if ( VT == <STR_LIT> && Op == <STR_LIT> ) return false ; return TargetLowering :: isTypeDesirableForOp ( Op , VT ) ;


<s> unsigned TmpExec = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , TmpExec ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , SaveExec ) . addReg ( <STR_LIT> ) ; MachineBasicBlock * LoopBB = MF -> CreateMachineBasicBlock ( ) ; MachineBasicBlock * RemainderBB = MF -> CreateMachineBasicBlock ( ) ; MachineFunction :: iterator MBBI ( MBB ) ; ++ MBBI ; MF -> insert ( MBBI , LoopBB ) ; MF -> insert ( MBBI , RemainderBB ) ; replaceSuccessorPhisWith ( MBB , * RemainderBB ) ; LoopBB -> addSuccessor ( LoopBB ) ; LoopBB -> addSuccessor ( RemainderBB ) ; RemainderBB -> transferSuccessors ( & MBB ) ; RemainderBB -> splice ( RemainderBB -> begin ( ) , & MBB , I , MBB . end ( ) ) ; MBB . addSuccessor ( LoopBB ) ; const MachineOperand * Idx = TII -> getNamedOperand ( MI , <STR_LIT> :: idx ) ; emitLoadM0FromVGPRLoop ( TII , MRI , MBB , * LoopBB , DL , MovRel , * Idx , InitResultReg , DstReg , PhiReg , TmpExec , Offset ) ; MachineBasicBlock :: iterator First = RemainderBB -> begin ( ) ; BuildMI ( * RemainderBB , First , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SaveExec ) ; MI . eraseFromParent ( ) ; return RemainderBB ;


<s> if ( ASC -> getDestAddressSpace ( ) == <ISA_LIT>AS :: LOCAL_ADDRESS || ASC -> getDestAddressSpace ( ) == <ISA_LIT>AS :: PRIVATE_ADDRESS ) { SDValue NonNull = DAG . getSetCC ( SL , <STR_LIT> , Src , FlatNullPtr , <STR_LIT> ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NonNull , Ptr , SegmentNullPtr ) ; } } if ( ASC -> getDestAddressSpace ( ) == <ISA_LIT>AS :: FLAT_ADDRESS ) { if ( ASC -> getSrcAddressSpace ( ) == <ISA_LIT>AS :: LOCAL_ADDRESS || ASC -> getSrcAddressSpace ( ) == <ISA_LIT>AS :: PRIVATE_ADDRESS ) { SDValue NonNull = DAG . getSetCC ( SL , <STR_LIT> , Src , SegmentNullPtr , <STR_LIT> ) ; SDValue Aperture = getSegmentAperture ( ASC -> getSrcAddressSpace ( ) , DAG ) ; SDValue CvtPtr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src , Aperture ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NonNull , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , CvtPtr ) , FlatNullPtr ) ; } } const MachineFunction & MF = DAG . getMachineFunction ( ) ;

DiagnosticInfoUnsupported InvalidAddrSpaceCast ( * MF . getFunction ( ) , <STR_LIT> , SL . getDebugLoc ( ) ) ;


<s> if ( ASC -> getDestAddressSpace ( ) == <ISA_LIT>AS :: FLAT_ADDRESS ) { if ( ASC -> getSrcAddressSpace ( ) == <ISA_LIT>AS :: LOCAL_ADDRESS || ASC -> getSrcAddressSpace ( ) == <ISA_LIT>AS :: PRIVATE_ADDRESS ) { SDValue NonNull = DAG . getSetCC ( SL , <STR_LIT> , Src , SegmentNullPtr , <STR_LIT> ) ; SDValue Aperture = getSegmentAperture ( ASC -> getSrcAddressSpace ( ) , DAG ) ; SDValue CvtPtr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src , Aperture ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NonNull , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , CvtPtr ) , FlatNullPtr ) ;


<s> if ( Intr -> getOpcode ( ) == <STR_LIT> ) { SetCC = Intr ; Intr = SetCC -> getOperand ( <NUM_LIT> ) . getNode ( ) ; } else { BR = findUser ( BRCOND , <STR_LIT> ) ; Target = BR -> getOperand ( <NUM_LIT> ) ; } if ( ! isCFIntrinsic ( Intr ) ) { return BRCOND ; } assert ( ! SetCC || ( SetCC -> getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> && cast < CondCodeSDNode > ( SetCC -> getOperand ( <NUM_LIT> ) . getNode ( ) ) -> get ( ) == <STR_LIT> ) ) ; ArrayRef < EVT > Res ( Intr -> value_begin ( ) + <NUM_LIT> , Intr -> value_end ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( BRCOND . getOperand ( <NUM_LIT> ) ) ; Ops . append ( Intr -> op_begin ( ) + <NUM_LIT> , Intr -> op_end ( ) ) ; Ops . push_back ( Target ) ; SDNode * Result = DAG . getNode ( Res . size ( ) > <NUM_LIT> ? <STR_LIT> : <STR_LIT> , DL , DAG . getVTList ( Res ) , Ops ) . getNode ( ) ; if ( BR ) { SDValue Ops [ ] = { BR -> getOperand ( <NUM_LIT> ) , BRCOND . getOperand ( <NUM_LIT> ) } ; SDValue NewBR = DAG . getNode ( <STR_LIT> , DL , BR -> getVTList ( ) , Ops ) ; DAG . ReplaceAllUsesWith ( BR , NewBR . getNode ( ) ) ; BR = NewBR . getNode ( ) ; } SDValue Chain = SDValue ( Result , Result -> getNumValues ( ) - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Intr -> getNumValues ( ) - <NUM_LIT> ; i != e ; ++ i ) { SDNode * CopyToReg = findUser ( SDValue ( Intr , i ) , <STR_LIT> ) ; if ( ! CopyToReg ) continue ; Chain = DAG . getCopyToReg ( Chain , DL , CopyToReg -> getOperand ( <NUM_LIT> ) , SDValue ( Result , i - <NUM_LIT> ) , SDValue ( ) ) ; DAG . ReplaceAllUsesWith ( SDValue ( CopyToReg , <NUM_LIT> ) , CopyToReg -> getOperand ( <NUM_LIT> ) ) ; }

DAG . ReplaceAllUsesOfValueWith ( SDValue ( Intr , Intr -> getNumValues ( ) - <NUM_LIT> ) , Intr -> getOperand ( <NUM_LIT> ) ) ;


<s> SDValue Ops [ ] = { BR -> getOperand ( <NUM_LIT> ) , BRCOND . getOperand ( <NUM_LIT> ) } ; SDValue NewBR = DAG . getNode ( <STR_LIT> , DL , BR -> getVTList ( ) , Ops ) ; DAG . ReplaceAllUsesWith ( BR , NewBR . getNode ( ) ) ; BR = NewBR . getNode ( ) ; } SDValue Chain = SDValue ( Result , Result -> getNumValues ( ) - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Intr -> getNumValues ( ) - <NUM_LIT> ; i != e ; ++ i ) { SDNode * CopyToReg = findUser ( SDValue ( Intr , i ) , <STR_LIT> ) ; if ( ! CopyToReg ) continue ; Chain = DAG . getCopyToReg ( Chain , DL , CopyToReg -> getOperand ( <NUM_LIT> ) , SDValue ( Result , i - <NUM_LIT> ) , SDValue ( ) ) ; DAG . ReplaceAllUsesWith ( SDValue ( CopyToReg , <NUM_LIT> ) , CopyToReg -> getOperand ( <NUM_LIT> ) ) ;


<s> const SDNodeFlags * Flags = Op -> getFlags ( ) ; if ( Unsafe || Flags -> hasAllowReciprocal ( ) ) { SDNodeFlags Flags ; Flags . setUnsafeAlgebra ( true ) ; SDValue Recip = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; return DAG . getNode ( <STR_LIT> , SL , VT , LHS , Recip , & Flags ) ; }


<s> if ( SDValue FastLowered = lowerFastUnsafeFDIV ( Op , DAG ) ) return FastLowered ; SDLoc SL ( Op ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; const SDValue One = DAG . getConstantFP ( <NUM_LIT> , SL , <STR_LIT> ) ; SDVTList ScaleVT = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue DenominatorScaled = DAG . getNode ( <STR_LIT> , SL , ScaleVT , RHS , RHS , LHS ) ; SDValue NumeratorScaled = DAG . getNode ( <STR_LIT> , SL , ScaleVT , LHS , RHS , LHS ) ; SDValue ApproxRcp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DenominatorScaled ) ; SDValue NegDivScale0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DenominatorScaled ) ;

SDValue Fma0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , ApproxRcp , One ) ;


<s> SDValue Fma2 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Fma1 , One ) ; SDValue DivScale1 = DAG . getNode ( <STR_LIT> , SL , ScaleVT , X , Y , X ) ; SDValue Fma3 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Fma1 , Fma2 , Fma1 ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale1 , Fma3 ) ; SDValue Fma4 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Mul , DivScale1 ) ; SDValue Scale ; if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) { const SDValue Hi = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue NumBC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , X ) ; SDValue DenBC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Y ) ; SDValue Scale0BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ; SDValue Scale1BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale1 ) ; SDValue NumHi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NumBC , Hi ) ; SDValue DenHi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DenBC , Hi ) ; SDValue Scale0Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Scale0BC , Hi ) ; SDValue Scale1Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Scale1BC , Hi ) ; SDValue CmpDen = DAG . getSetCC ( SL , <STR_LIT> , DenHi , Scale0Hi , <STR_LIT> ) ; SDValue CmpNum = DAG . getSetCC ( SL , <STR_LIT> , NumHi , Scale1Hi , <STR_LIT> ) ; Scale = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , CmpNum , CmpDen ) ; } else {

Scale = DivScale1 . getValue ( <NUM_LIT> ) ;


<s> unsigned KnownBits = Log2_64 ( MaxGPUAlloc / MinGranularity ) ; EVT ExtVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , KnownBits ) ; SDValue TFI = DAG . getTargetFrameIndex ( FrameIndex , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , TFI , DAG . getValueType ( ExtVT ) ) ;


<s> FrameIndexSDNode * FINode = cast < FrameIndexSDNode > ( Op ) ; unsigned FrameIndex = FINode -> getIndex ( ) ; uint64_t MaxGPUAlloc = UINT64_C ( <NUM_LIT> ) * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> ;


<s> const GlobalValue * GV = GSD -> getGlobal ( ) ; EVT PtrVT = Op . getValueType ( ) ; if ( ! shouldEmitGOTReloc ( GV , getTargetMachine ( ) ) ) return buildPCRelGlobalAddress ( DAG , GV , DL , GSD -> getOffset ( ) , PtrVT ) ; SDValue GOTAddr = buildPCRelGlobalAddress ( DAG , GV , DL , <NUM_LIT> , PtrVT , <ISA_LIT>InstrInfo :: MO_GOTPCREL ) ; Type * Ty = PtrVT . getTypeForEVT ( * DAG . getContext ( ) ) ;

PointerType * PtrTy = PointerType :: get ( Ty , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ;


<s> return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , Op . getOperand ( <NUM_LIT> ) , Glue ) ; } case <STR_LIT> : { SDValue Ops [ ] = { Chain , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ; EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore , VT . getStoreSize ( ) , <NUM_LIT> ) ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Ops , VT , MMO ) ; } case <STR_LIT> : { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( const ConstantFPSDNode * K = dyn_cast < ConstantFPSDNode > ( Src ) ) { if ( ! K -> isNegative ( ) ) return Chain ; SDValue NegOne = DAG . getTargetConstant ( FloatToBits ( - <NUM_LIT> ) , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , NegOne ) ; } SDValue Cast = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , Cast ) ;


<s> case <STR_LIT> : case <STR_LIT> : { MemSDNode * M = cast < MemSDNode > ( Op ) ; unsigned Opc = ( IntrID == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { M -> getOperand ( <NUM_LIT> ) , M -> getOperand ( <NUM_LIT> ) , M -> getOperand ( <NUM_LIT> ) } ; return DAG . getMemIntrinsicNode ( Opc , SDLoc ( Op ) , M -> getVTList ( ) , Ops , M -> getMemoryVT ( ) , M -> getMemOperand ( ) ) ; } default :


<s> unsigned AS = Load -> getAddressSpace ( ) ; if ( ! allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , MemVT , AS , Load -> getAlignment ( ) ) ) { SDValue Ops [ <NUM_LIT> ] ; std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = expandUnalignedLoad ( Load , DAG ) ; return DAG . getMergeValues ( Ops , DL ) ; } unsigned NumElements = MemVT . getVectorNumElements ( ) ; switch ( AS ) { case <ISA_LIT>AS :: CONSTANT_ADDRESS : if ( isMemOpUniform ( Load ) ) return SDValue ( ) ; case <ISA_LIT>AS :: GLOBAL_ADDRESS : case <ISA_LIT>AS :: FLAT_ADDRESS : if ( NumElements > <NUM_LIT> ) return SplitVectorLoad ( Op , DAG ) ; return SDValue ( ) ;


<s> SDValue Ops [ ] = { DAG . getNode ( <STR_LIT> , DL , MemVT , NewLD ) , NewLD . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( Ops , DL ) ; } if ( ! MemVT . isVector ( ) ) return SDValue ( ) ; assert ( Op . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned AS = Load -> getAddressSpace ( ) ; if ( ! allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , MemVT , AS , Load -> getAlignment ( ) ) ) { SDValue Ops [ <NUM_LIT> ] ; std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = expandUnalignedLoad ( Load , DAG ) ; return DAG . getMergeValues ( Ops , DL ) ; } unsigned NumElements = MemVT . getVectorNumElements ( ) ; switch ( AS ) { case <ISA_LIT>AS :: CONSTANT_ADDRESS : if ( isMemOpUniform ( Load ) ) return SDValue ( ) ; case <ISA_LIT>AS :: GLOBAL_ADDRESS : case <ISA_LIT>AS :: FLAT_ADDRESS : if ( NumElements > <NUM_LIT> ) return SplitVectorLoad ( Op , DAG ) ; return SDValue ( ) ; case <ISA_LIT>AS :: PRIVATE_ADDRESS : { switch ( Subtarget -> getMaxPrivateElementSize ( ) ) { case <NUM_LIT> : return scalarizeVectorLoad ( Load , DAG ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> ) return SplitVectorLoad ( Op , DAG ) ; return SDValue ( ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> ) return SplitVectorLoad ( Op , DAG ) ; return SDValue ( ) ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> SDValue PtrOffset = DAG . getUNDEF ( PtrVT ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ) ; unsigned Align = DL . getABITypeAlignment ( Ty ) ; <STR_LIT> ExtTy = Signed ? <STR_LIT> : <STR_LIT> ; if ( MemVT . isFloatingPoint ( ) ) ExtTy = <STR_LIT> ; SDValue Ptr = LowerParameterPtr ( DAG , SL , Chain , Offset ) ; return DAG . getLoad ( <STR_LIT> , ExtTy , VT , SL , Chain , Ptr , PtrOffset , PtrInfo , MemVT , Align , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MOInvariant ) ;


<s> MVT PtrVT = getPointerTy ( DL , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; PointerType * PtrTy = PointerType :: get ( Ty , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; SDValue PtrOffset = DAG . getUNDEF ( PtrVT ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ) ; unsigned Align = DL . getABITypeAlignment ( Ty ) ;


<s> unsigned InputPtrReg = TRI -> getPreloadedValue ( MF , <ISA_LIT>RegisterInfo :: KERNARG_SEGMENT_PTR ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; MVT PtrVT = getPointerTy ( DL , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; SDValue BasePtr = DAG . getCopyFromReg ( Chain , SL , MRI . getLiveInVirtReg ( InputPtrReg ) , PtrVT ) ; return DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( Offset , SL , PtrVT ) ) ;


<s> if ( Out . VT . isVector ( ) ) { MVT VT = Out . VT . getVectorElementType ( ) ; <STR_LIT> NewOut = Out ; NewOut . Flags . setSplit ( ) ; NewOut . VT = VT ; unsigned NumElements = Out . ArgVT . getVectorNumElements ( ) ; for ( unsigned j = <NUM_LIT> ; j != NumElements ; ++ j ) { SDValue Elem = DAG . getNode ( <STR_LIT> , DL , VT , OutVals [ i ] , DAG . getConstant ( j , DL , <STR_LIT> ) ) ; SplitVals . push_back ( Elem ) ; Splits . push_back ( NewOut ) ; NewOut . PartOffset += NewOut . VT . getStoreSize ( ) ; } } else { SplitVals . push_back ( OutVals [ i ] ) ; Splits . push_back ( Out ) ; } } SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; AnalyzeReturn ( CCInfo , Splits ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ; for ( unsigned i = <NUM_LIT> , realRVLocIdx = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i , ++ realRVLocIdx ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = SplitVals [ realRVLocIdx ] ; switch ( VA . getLocInfo ( ) ) {

default : llvm_unreachable ( <STR_LIT> ) ;


<s> SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue LHS = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Lo0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , Zero ) ; SDValue Lo1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RHS , Zero ) ; SDValue Lo = DAG . getSelect ( DL , <STR_LIT> , Cond , Lo0 , Lo1 ) ; SDValue Hi0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , One ) ; SDValue Hi1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RHS , One ) ; SDValue Hi = DAG . getSelect ( DL , <STR_LIT> , Cond , Hi0 , Hi1 ) ; SDValue Res = DAG . getBuildVector ( <STR_LIT> , DL , { Lo , Hi } ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res ) ;


<s> EVT VT = Store -> getMemoryVT ( ) ; if ( VT == <STR_LIT> ) { return DAG . getTruncStore ( Store -> getChain ( ) , DL , DAG . getSExtOrTrunc ( Store -> getValue ( ) , DL , <STR_LIT> ) , Store -> getBasePtr ( ) , <STR_LIT> , Store -> getMemOperand ( ) ) ; } assert ( VT . isVector ( ) && Store -> getValue ( ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> ) ; unsigned AS = Store -> getAddressSpace ( ) ; if ( ! allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , VT , AS , Store -> getAlignment ( ) ) ) { return expandUnalignedStore ( Store , DAG ) ; } unsigned NumElements = VT . getVectorNumElements ( ) ; switch ( AS ) { case <ISA_LIT>AS :: GLOBAL_ADDRESS : case <ISA_LIT>AS :: FLAT_ADDRESS : if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; return SDValue ( ) ; case <ISA_LIT>AS :: PRIVATE_ADDRESS : { switch ( Subtarget -> getMaxPrivateElementSize ( ) ) { case <NUM_LIT> : return scalarizeVectorStore ( Store , DAG ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; return SDValue ( ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; return SDValue ( ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } case <ISA_LIT>AS :: LOCAL_ADDRESS : { if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; if ( NumElements == <NUM_LIT> ) return Op ; return SplitVectorStore ( Op , DAG ) ;


<s> return DAG . getTruncStore ( Store -> getChain ( ) , DL , DAG . getSExtOrTrunc ( Store -> getValue ( ) , DL , <STR_LIT> ) , Store -> getBasePtr ( ) , <STR_LIT> , Store -> getMemOperand ( ) ) ; } assert ( VT . isVector ( ) && Store -> getValue ( ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> ) ; unsigned AS = Store -> getAddressSpace ( ) ; if ( ! allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , VT , AS , Store -> getAlignment ( ) ) ) { return expandUnalignedStore ( Store , DAG ) ; } unsigned NumElements = VT . getVectorNumElements ( ) ; switch ( AS ) { case <ISA_LIT>AS :: GLOBAL_ADDRESS : case <ISA_LIT>AS :: FLAT_ADDRESS : if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; return SDValue ( ) ; case <ISA_LIT>AS :: PRIVATE_ADDRESS : { switch ( Subtarget -> getMaxPrivateElementSize ( ) ) { case <NUM_LIT> : return scalarizeVectorStore ( Store , DAG ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; return SDValue ( ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; return SDValue ( ) ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> DiagnosticInfoUnsupported NoTrap ( * MF . getFunction ( ) , <STR_LIT> , Op . getDebugLoc ( ) , DS_Warning ) ; DAG . getContext ( ) -> diagnose ( NoTrap ) ;

return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ;


<s> const MachineFunction & MF = DAG . getMachineFunction ( ) ; DiagnosticInfoUnsupported NoTrap ( * MF . getFunction ( ) , <STR_LIT> , Op . getDebugLoc ( ) , DS_Warning ) ; DAG . getContext ( ) -> diagnose ( NoTrap ) ;


<s> if ( LHS . getOpcode ( ) == <STR_LIT> && RHS . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> LCC = cast < CondCodeSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) -> get ( ) ; <STR_LIT> RCC = cast < CondCodeSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue X = LHS . getOperand ( <NUM_LIT> ) ; SDValue Y = RHS . getOperand ( <NUM_LIT> ) ; if ( Y . getOpcode ( ) != <STR_LIT> || Y . getOperand ( <NUM_LIT> ) != X ) return SDValue ( ) ; if ( LCC == <STR_LIT> ) { if ( X != LHS . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; if ( RCC == <STR_LIT> ) { const ConstantFPSDNode * C1 = dyn_cast < ConstantFPSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) ; if ( ! C1 || ! C1 -> isInfinity ( ) || C1 -> isNegative ( ) ) return SDValue ( ) ; const uint32_t Mask = <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> ;

static_assert ( ( ( ~ ( <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> ) ) & <NUM_LIT> ) == Mask , <STR_LIT> ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> ) break ; if ( Subtarget -> hasFP32Denormals ( ) ) break ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> ) { SDValue A = LHS . getOperand ( <NUM_LIT> ) ; if ( A == LHS . getOperand ( <NUM_LIT> ) ) { const SDValue Two = DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Two , A , RHS ) ; } } if ( RHS . getOpcode ( ) == <STR_LIT> ) { SDValue A = RHS . getOperand ( <NUM_LIT> ) ; if ( A == RHS . getOperand ( <NUM_LIT> ) ) { const SDValue Two = DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Two , A , LHS ) ; } } return SDValue ( ) ; } case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) break ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && ! Subtarget -> hasFP32Denormals ( ) ) { SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> ) { SDValue A = LHS . getOperand ( <NUM_LIT> ) ; if ( A == LHS . getOperand ( <NUM_LIT> ) ) { const SDValue Two = DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue NegRHS = DAG . getNode ( <STR_LIT> , DL , VT , RHS ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Two , A , NegRHS ) ; } } if ( RHS . getOpcode ( ) == <STR_LIT> ) { SDValue A = RHS . getOperand ( <NUM_LIT> ) ; if ( A == RHS . getOperand ( <NUM_LIT> ) ) { const SDValue NegTwo = DAG . getConstantFP ( - <NUM_LIT> , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , NegTwo , A , LHS ) ; } } return SDValue ( ) ; } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( VT == <STR_LIT> && ! Subtarget -> hasFP32Denormals ( ) ) return DAG . getConstantFP ( <NUM_LIT> , SDLoc ( N ) , VT ) ; if ( VT == <STR_LIT> && ! Subtarget -> hasFP64Denormals ( ) ) return DAG . getConstantFP ( <NUM_LIT> , SDLoc ( N ) , VT ) ; } if ( C . isNaN ( ) ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; APFloat CanonicalQNaN = APFloat :: getQNaN ( C . getSemantics ( ) ) ; if ( C . isSignaling ( ) ) {

return DAG . getConstantFP ( CanonicalQNaN , SDLoc ( N ) , VT ) ;


<s> if ( ! K0 ) return SDValue ( ) ; APFloat :: cmpResult Cmp = K0 -> getValueAPF ( ) . compare ( K1 -> getValueAPF ( ) ) ; if ( Cmp == APFloat :: cmpGreaterThan ) return SDValue ( ) ;

SDValue Var = Op0 . getOperand ( <NUM_LIT> ) ;


<s> static SDValue performFPMed3ImmCombine ( SelectionDAG & DAG , const SDLoc & SL , SDValue Op0 , SDValue Op1 ) { ConstantFPSDNode * K1 = dyn_cast < ConstantFPSDNode > ( Op1 ) ; if ( ! K1 ) return SDValue ( ) ; ConstantFPSDNode * K0 = dyn_cast < ConstantFPSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) ; if ( ! K0 ) return SDValue ( ) ; APFloat :: cmpResult Cmp = K0 -> getValueAPF ( ) . compare ( K1 -> getValueAPF ( ) ) ; if ( Cmp == APFloat :: cmpGreaterThan ) return SDValue ( ) ; SDValue Var = Op0 . getOperand ( <NUM_LIT> ) ;

if ( ! isKnownNeverSNan ( DAG , Var ) ) return SDValue ( ) ;


<s> ConstantSDNode * K0 = dyn_cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) ; if ( ! K0 ) return SDValue ( ) ; if ( Signed ) { if ( K0 -> getAPIntValue ( ) . sge ( K1 -> getAPIntValue ( ) ) ) return SDValue ( ) ; } else { if ( K0 -> getAPIntValue ( ) . uge ( K1 -> getAPIntValue ( ) ) ) return SDValue ( ) ; } EVT VT = K0 -> getValueType ( <NUM_LIT> ) ;

return DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT> , SL , VT , Op0 . getOperand ( <NUM_LIT> ) , SDValue ( K0 , <NUM_LIT> ) , SDValue ( K1 , <NUM_LIT> ) ) ;


<s> if ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) ) { if ( SDValue Med3 = performIntMed3ImmCombine ( DAG , SDLoc ( N ) , Op0 , Op1 , false ) ) return Med3 ; } if ( ( ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> ) || ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> ) ) && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Op0 . hasOneUse ( ) ) { if ( SDValue Res = performFPMed3ImmCombine ( DAG , SDLoc ( N ) , Op0 , Op1 ) ) return Res ; }


<s> SDValue ExtSrc = RHS . getOperand ( <NUM_LIT> ) ; EVT SrcVT = ExtSrc . getValueType ( ) ; if ( SrcVT == <STR_LIT> ) { SDLoc SL ( N ) ; SDValue LowLHS , HiBits ; std :: tie ( LowLHS , HiBits ) = split64BitValue ( LHS , DAG ) ; SDValue LowOr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LowLHS , ExtSrc ) ; DCI . AddToWorklist ( LowOr . getNode ( ) ) ; DCI . AddToWorklist ( HiBits . getNode ( ) ) ; SDValue Vec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LowOr , HiBits ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Vec ) ; } } } if ( LHS . getOpcode ( ) == <STR_LIT> && RHS . getOpcode ( ) == <STR_LIT> ) { SDValue Src = LHS . getOperand ( <NUM_LIT> ) ; if ( Src != RHS . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; const ConstantSDNode * CLHS = dyn_cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) ; const ConstantSDNode * CRHS = dyn_cast < ConstantSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) ; if ( ! CLHS || ! CRHS ) return SDValue ( ) ; static const uint32_t MaxMask = <NUM_LIT> ; uint32_t NewMask = ( CLHS -> getZExtValue ( ) | CRHS -> getZExtValue ( ) ) & MaxMask ; SDLoc DL ( N ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src , DAG . getConstant ( NewMask , DL , <STR_LIT> ) ) ;


<s> if ( ! CN1 ) return SDValue ( ) ; const ConstantSDNode * CAdd = dyn_cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; if ( ! CAdd ) return SDValue ( ) ; APInt Offset = CAdd -> getAPIntValue ( ) << CN1 -> getAPIntValue ( ) ; if ( ! canFoldOffset ( Offset . getZExtValue ( ) , AddrSpace , * getSubtarget ( ) ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc SL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue ShlX = DAG . getNode ( <STR_LIT> , SL , VT , N0 . getOperand ( <NUM_LIT> ) , N1 ) ; SDValue COffset = DAG . getConstant ( Offset , SL , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , SL , VT , ShlX , COffset ) ;


<s> EVT SrcVT = Src . getValueType ( ) ; if ( DCI . isAfterLegalizeVectorOps ( ) && SrcVT == <STR_LIT> ) { if ( DAG . MaskedValueIsZero ( Src , APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ) { SDValue Cvt = DAG . getNode ( <STR_LIT> , DL , VT , Src ) ; DCI . AddToWorklist ( Cvt . getNode ( ) ) ; return Cvt ; } }


<s> if ( DAG . MaskedValueIsZero ( Src , APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ) { SDValue Cvt = DAG . getNode ( <STR_LIT> , DL , VT , Src ) ; DCI . AddToWorklist ( Cvt . getNode ( ) ) ; return Cvt ;


<s> for ( MachineInstr & MI : * Succ ) { if ( ! MI . isPHI ( ) ) break ;

for ( unsigned I = <NUM_LIT> , E = MI . getNumOperands ( ) ; I != E ; I += <NUM_LIT> ) {


<s> assert ( Idx -> getReg ( ) != <STR_LIT> ) ; if ( ! TII -> getRegisterInfo ( ) . isSGPRClass ( IdxRC ) ) return false ; if ( Offset == <NUM_LIT> ) { BuildMI ( * MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addOperand ( * Idx ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addOperand ( * Idx ) . addImm ( Offset ) ; } return true ;


<s> const MachineOperand * Idx = TII -> getNamedOperand ( MI , <STR_LIT> :: idx ) ; const TargetRegisterClass * IdxRC = MRI . getRegClass ( Idx -> getReg ( ) ) ; assert ( Idx -> getReg ( ) != <STR_LIT> ) ; if ( ! TII -> getRegisterInfo ( ) . isSGPRClass ( IdxRC ) ) return false ; if ( Offset == <NUM_LIT> ) { BuildMI ( * MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addOperand ( * Idx ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addOperand ( * Idx ) . addImm ( Offset ) ; }


<s> bool <ISA_LIT>TargetLowering :: shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const { const <ISA_LIT>InstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; return TII -> isInlineConstant ( Imm ) ;


<s> const <ISA_LIT>InstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; return TII -> isInlineConstant ( Imm ) ;


<s> static bool shouldEmitGOTReloc ( const GlobalValue * GV , const TargetMachine & TM ) {

return GV -> getType ( ) -> getAddressSpace ( ) == <ISA_LIT>AS :: GLOBAL_ADDRESS && ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ;


<s> static bool shouldEmitGOTReloc ( const GlobalValue * GV , const TargetMachine & TM ) { return GV -> getType ( ) -> getAddressSpace ( ) == <ISA_LIT>AS :: GLOBAL_ADDRESS && ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) { for ( unsigned Op = <NUM_LIT> ; Op < <STR_LIT> ; ++ Op ) { switch ( Op ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : setOperationAction ( Op , VT , Custom ) ; break ; default : setOperationAction ( Op , VT , Expand ) ; break ; } } } for ( MVT Vec64 : { <STR_LIT> , <STR_LIT> } ) { setOperationAction ( <STR_LIT> , Vec64 , Promote ) ; AddPromotedToType ( <STR_LIT> , Vec64 , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , Vec64 , Promote ) ; AddPromotedToType ( <STR_LIT> , Vec64 , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , Vec64 , Promote ) ; AddPromotedToType ( <STR_LIT> , Vec64 , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , Vec64 , Promote ) ; AddPromotedToType ( <STR_LIT> , Vec64 , <STR_LIT> ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; if ( getSubtarget ( ) -> hasFlatAddressSpace ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ;


<s> } MachineFunction * MF = BB -> getParent ( ) ; MachineBasicBlock * SplitBB = MF -> CreateMachineBasicBlock ( BB -> getBasicBlock ( ) ) ; replaceSuccessorPhisWith ( * BB , * SplitBB ) ; MF -> insert ( ++ MachineFunction :: iterator ( BB ) , SplitBB ) ; SplitBB -> splice ( SplitBB -> begin ( ) , BB , SplitPoint , BB -> end ( ) ) ; SplitBB -> transferSuccessors ( BB ) ;


<s> void <ISA_LIT>TargetLowering :: computeKnownBitsForFrameIndex ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { TargetLowering :: computeKnownBitsForFrameIndex ( Op , Known , DemandedElts , DAG , Depth ) ;

Known . Zero . setHighBits ( getSubtarget ( ) -> getKnownHighZeroBitsForFrameIndex ( ) ) ;


<s> void <ISA_LIT>TargetLowering :: computeKnownBitsForFrameIndex ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { TargetLowering :: computeKnownBitsForFrameIndex ( Op , Known , DemandedElts , DAG , Depth ) ; Known . Zero . setHighBits ( getSubtarget ( ) -> getKnownHighZeroBitsForFrameIndex ( ) ) ;


<s> EVT ReqRetVT = ResultTypes [ <NUM_LIT> ] ; EVT ReqRetEltVT = ReqRetVT . isVector ( ) ? ReqRetVT . getVectorElementType ( ) : ReqRetVT ; int ReqRetNumElts = ReqRetVT . isVector ( ) ? ReqRetVT . getVectorNumElements ( ) : <NUM_LIT> ; EVT AdjEltVT = Unpacked && IsD16 ? <STR_LIT> : ReqRetEltVT ; EVT AdjVT = Unpacked ? ReqRetNumElts > <NUM_LIT> ? EVT :: getVectorVT ( Context , AdjEltVT , ReqRetNumElts ) : AdjEltVT : ReqRetVT ; int NumElts ; if ( IsD16 && ! Unpacked ) NumElts = NumVDataDwords << <NUM_LIT> ; else NumElts = NumVDataDwords ; EVT CastVT = NumElts > <NUM_LIT> ? EVT :: getVectorVT ( Context , AdjEltVT , NumElts ) : AdjEltVT ; bool V6F16Special = false ; if ( NumElts == <NUM_LIT> ) { CastVT = EVT :: getVectorVT ( Context , <STR_LIT> , NumElts / <NUM_LIT> ) ; DMaskPop >>= <NUM_LIT> ; ReqRetNumElts >>= <NUM_LIT> ; V6F16Special = true ; AdjVT = <STR_LIT> ; } SDValue N = SDValue ( Result , <NUM_LIT> ) ; SDValue CastRes = DAG . getNode ( <STR_LIT> , DL , CastVT , N ) ; SmallVector < SDValue , <NUM_LIT> > BVElts ; if ( CastVT . isVector ( ) ) { DAG . ExtractVectorElements ( CastRes , BVElts , <NUM_LIT> , DMaskPop ) ; } else { BVElts . push_back ( CastRes ) ; } int ExtraElts = ReqRetNumElts - DMaskPop ; while ( ExtraElts -- ) BVElts . push_back ( DAG . getUNDEF ( AdjEltVT ) ) ; SDValue PreTFCRes ; if ( ReqRetNumElts > <NUM_LIT> ) { SDValue NewVec = DAG . getBuildVector ( AdjVT , DL , BVElts ) ; if ( IsD16 && Unpacked ) PreTFCRes = adjustLoadValueTypeImpl ( NewVec , ReqRetVT , DL , DAG , Unpacked ) ; else PreTFCRes = NewVec ; } else { PreTFCRes = BVElts [ <NUM_LIT> ] ; } if ( V6F16Special ) PreTFCRes = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , PreTFCRes ) ; if ( ! IsTexFail ) { if ( Result -> getNumValues ( ) > <NUM_LIT> ) return DAG . getMergeValues ( { PreTFCRes , SDValue ( Result , <NUM_LIT> ) } , DL ) ; else return PreTFCRes ; } SmallVector < SDValue , <NUM_LIT> > TFCElt ; DAG . ExtractVectorElements ( N , TFCElt , DMaskPop , <NUM_LIT> ) ;

SDValue TFCRes = DAG . getNode ( <STR_LIT> , DL , ResultTypes [ <NUM_LIT> ] , TFCElt [ <NUM_LIT> ] ) ;


<s> BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , CurrentIdxReg ) . addReg ( IdxReg . getReg ( ) , getUndefRegState ( IdxReg . isUndef ( ) ) ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , CondReg ) . addReg ( CurrentIdxReg ) . addReg ( IdxReg . getReg ( ) , <NUM_LIT> , IdxReg . getSubReg ( ) ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , NewExec ) . addReg ( CondReg , RegState :: Kill ) ; MRI . setSimpleHint ( NewExec , CondReg ) ; if ( UseGPRIdxMode ) { unsigned IdxReg ; if ( Offset == <NUM_LIT> ) { IdxReg = CurrentIdxReg ; } else { IdxReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , IdxReg ) . addReg ( CurrentIdxReg , RegState :: Kill ) . addImm ( Offset ) ; } unsigned IdxMode = IsIndirectSrc ? <STR_LIT> :: SRC0_ENABLE : <STR_LIT> :: DST_ENABLE ; MachineInstr * SetOn = BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) ) . addReg ( IdxReg , RegState :: Kill ) . addImm ( IdxMode ) ; SetOn -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; } else { if ( Offset == <NUM_LIT> ) { BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( CurrentIdxReg , RegState :: Kill ) ; } else {

BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( CurrentIdxReg , RegState :: Kill ) . addImm ( Offset ) ;


<s> unsigned CurrentIdxReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned CondReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII -> get ( TargetOpcode :: PHI ) , PhiReg ) . addReg ( InitReg ) . addMBB ( & OrigBB ) . addReg ( ResultReg ) . addMBB ( & LoopBB ) ; BuildMI ( LoopBB , I , DL , TII -> get ( TargetOpcode :: PHI ) , PhiExec ) . addReg ( InitSaveExecReg ) . addMBB ( & OrigBB ) . addReg ( NewExec ) . addMBB ( & LoopBB ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , CurrentIdxReg ) . addReg ( IdxReg . getReg ( ) , getUndefRegState ( IdxReg . isUndef ( ) ) ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , CondReg ) . addReg ( CurrentIdxReg ) . addReg ( IdxReg . getReg ( ) , <NUM_LIT> , IdxReg . getSubReg ( ) ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , NewExec ) . addReg ( CondReg , RegState :: Kill ) ; MRI . setSimpleHint ( NewExec , CondReg ) ; if ( UseGPRIdxMode ) { unsigned IdxReg ; if ( Offset == <NUM_LIT> ) { IdxReg = CurrentIdxReg ; } else { IdxReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , IdxReg ) . addReg ( CurrentIdxReg , RegState :: Kill ) . addImm ( Offset ) ;


<s> } bool NeedSP = ! Info -> isEntryFunction ( ) || MFI . hasVarSizedObjects ( ) || MFI . hasCalls ( ) ; if ( NeedSP ) { unsigned ReservedStackPtrOffsetReg = TRI -> reservedStackPtrOffsetReg ( MF ) ; Info -> setStackPtrOffsetReg ( ReservedStackPtrOffsetReg ) ; assert ( Info -> getStackPtrOffsetReg ( ) != Info -> getFrameOffsetReg ( ) ) ; assert ( ! TRI -> isSubRegister ( Info -> getScratchRSrcReg ( ) , Info -> getStackPtrOffsetReg ( ) ) ) ;

if ( Info -> getStackPtrOffsetReg ( ) != <STR_LIT> ) MRI . replaceRegWith ( <STR_LIT> , Info -> getStackPtrOffsetReg ( ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : { Value * Ptr = II -> getArgOperand ( <NUM_LIT> ) ; AccessTy = II -> getType ( ) ; Ops . push_back ( Ptr ) ; return true ; }


<s> if ( ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath || ( N0 -> getFlags ( ) . hasAllowContract ( ) && N1 -> getFlags ( ) . hasAllowContract ( ) ) ) && isFMAFasterThanFMulAndFAdd ( VT ) ) { return <STR_LIT> ;


<s> EVT VT = N0 -> getValueType ( <NUM_LIT> ) ; if ( ( ( VT == <STR_LIT> && ! Subtarget -> hasFP32Denormals ( ) ) || ( VT == <STR_LIT> && ! Subtarget -> hasFP16Denormals ( ) && getSubtarget ( ) -> hasMadF16 ( ) ) ) && isOperationLegal ( <STR_LIT> , VT ) ) return <STR_LIT> ;

const TargetOptions & Options = DAG . getTarget ( ) . Options ;


<s> MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MMO , <NUM_LIT> , <NUM_LIT> ) ; } assert ( VTList . NumVTs == <NUM_LIT> ) ; SDVTList WidenedVTList = DAG . getVTList ( WidenedVT , VTList . VTs [ <NUM_LIT> ] ) ; auto NewOp = DAG . getMemIntrinsicNode ( Opcode , DL , WidenedVTList , Ops , WidenedMemVT , MMO ) ; if ( WidenedVT != VT ) { auto Extract = DAG . getNode ( <STR_LIT> , DL , VT , NewOp , DAG . getConstant ( <NUM_LIT> , DL , getVectorIdxTy ( DAG . getDataLayout ( ) ) ) ) ; NewOp = DAG . getMergeValues ( { Extract , SDValue ( NewOp . getNode ( ) , <NUM_LIT> ) } , DL ) ;


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , const AttributeList & FuncAttributes ) const {

if ( Size >= <NUM_LIT> && DstAlign >= <NUM_LIT> ) return <STR_LIT> ;


<s> if ( Size >= <NUM_LIT> && DstAlign >= <NUM_LIT> ) return <STR_LIT> ; if ( Size >= <NUM_LIT> && DstAlign >= <NUM_LIT> ) return <STR_LIT> ; return <STR_LIT> ;


<s> unsigned LoopSize = <NUM_LIT> ; for ( const MachineBasicBlock * MBB : ML -> blocks ( ) ) { if ( MBB != Header ) LoopSize += ( <NUM_LIT> << MBB -> getAlignment ( ) ) / <NUM_LIT> ; for ( const MachineInstr & MI : * MBB ) { LoopSize += TII -> getInstSizeInBytes ( MI ) ; if ( LoopSize > <NUM_LIT> ) return PrefAlign ; } } if ( LoopSize <= <NUM_LIT> ) return PrefAlign ; if ( LoopSize <= <NUM_LIT> ) return CacheLineAlign ; for ( MachineLoop * P = ML -> getParentLoop ( ) ; P ; P = P -> getParentLoop ( ) ) { if ( MachineBasicBlock * Exit = P -> getExitBlock ( ) ) { auto I = Exit -> getFirstNonDebugInstr ( ) ; if ( I != Exit -> end ( ) && I -> getOpcode ( ) == <STR_LIT> ) return CacheLineAlign ; } } MachineBasicBlock * Pre = ML -> getLoopPreheader ( ) ; MachineBasicBlock * Exit = ML -> getExitBlock ( ) ; if ( Pre && Exit ) { BuildMI ( * Pre , Pre -> getFirstTerminator ( ) , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( * Exit , Exit -> getFirstNonDebugInstr ( ) , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ;


<s> const TargetRegisterClass * RC = TargetLoweringBase :: getRegClassFor ( VT , false ) ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; if ( RC == & <STR_LIT> && ! isDivergent ) return & <STR_LIT> ; if ( ! TRI -> isSGPRClass ( RC ) && ! isDivergent ) return TRI -> getEquivalentSGPRClass ( RC ) ; else if ( TRI -> isSGPRClass ( RC ) && isDivergent ) return TRI -> getEquivalentVGPRClass ( RC ) ;


<s> if ( ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS || Subtarget -> getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) && Subtarget -> getRegisterInfo ( ) -> regsOverlap ( Reg , <STR_LIT> ) ) { report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ) ; } switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return Reg ; break ; case <STR_LIT> :


<s> unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( Reg == <STR_LIT> ) { report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ) ; } if ( ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS || Subtarget -> getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) && Subtarget -> getRegisterInfo ( ) -> regsOverlap ( Reg , <STR_LIT> ) ) { report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ) ; } switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( Attr . hasFnAttribute ( Attribute :: ReadNone ) ) return false ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( RsrcIntr -> IsImage ) { Info . ptrVal = MFI -> getImagePSV ( * MF . getSubtarget < GCNSubtarget > ( ) . getInstrInfo ( ) , CI . getArgOperand ( RsrcIntr -> RsrcArg ) ) ; Info . align = <NUM_LIT> ; } else { Info . ptrVal = MFI -> getBufferPSV ( * MF . getSubtarget < GCNSubtarget > ( ) . getInstrInfo ( ) , CI . getArgOperand ( RsrcIntr -> RsrcArg ) ) ; } Info . flags = MachineMemOperand :: MODereferenceable ; if ( Attr . hasFnAttribute ( Attribute :: ReadOnly ) ) { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getType ( ) , true ) ; if ( Info . memVT == <STR_LIT> ) { Info . memVT = memVTFromAggregate ( CI . getType ( ) ) ; } Info . flags |= MachineMemOperand :: MOLoad ; } else if ( Attr . hasFnAttribute ( Attribute :: WriteOnly ) ) { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . flags |= MachineMemOperand :: MOStore ; } else { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getType ( ) ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MODereferenceable ; Info . flags |= MachineMemOperand :: MOVolatile ; } return true ; }


<s> SDValue <ISA_LIT>TargetLowering :: handleByteShortBufferLoads ( SelectionDAG & DAG , EVT LoadVT , SDLoc DL , ArrayRef < SDValue > Ops , MemSDNode * M ) const { EVT IntVT = LoadVT . changeTypeToInteger ( ) ; unsigned Opc = ( LoadVT . getScalarType ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDVTList ResList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue BufferLoad = DAG . getMemIntrinsicNode ( Opc , DL , ResList , Ops , IntVT , M -> getMemOperand ( ) ) ; SDValue BufferLoadTrunc = DAG . getNode ( <STR_LIT> , DL , LoadVT . getScalarType ( ) , BufferLoad ) ;

return DAG . getMergeValues ( { BufferLoadTrunc , BufferLoad . getValue ( <NUM_LIT> ) } , DL ) ;


<s> SDVTList ResList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue BufferLoad = DAG . getMemIntrinsicNode ( Opc , DL , ResList , Ops , IntVT , M -> getMemOperand ( ) ) ;

SDValue BufferLoadTrunc = DAG . getNode ( <STR_LIT> , DL , LoadVT . getScalarType ( ) , BufferLoad ) ;


<s> SDValue <ISA_LIT>TargetLowering :: handleByteShortBufferStores ( SelectionDAG & DAG , EVT VDataType , SDLoc DL , SDValue Ops [ ] , MemSDNode * M ) const { SDValue BufferStoreExt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ops [ <NUM_LIT> ] ) ; Ops [ <NUM_LIT> ] = BufferStoreExt ;

unsigned Opc = ( VDataType == <STR_LIT> ) ? <STR_LIT> :


<s> ArrayRef < SDValue > OpsRef = makeArrayRef ( & Ops [ <NUM_LIT> ] , <NUM_LIT> ) ; return DAG . getMemIntrinsicNode ( Opc , DL , M -> getVTList ( ) , OpsRef , VDataType , M -> getMemOperand ( ) ) ;


<s> if ( ( Intrinsic -> getIntrinsicID ( ) == <STR_LIT> ) && ( V == U -> getOperand ( <NUM_LIT> ) ) ) Result = true ; } else { Result = hasIfBreakUser ( U , Visited ) ; } if ( Result ) break ; }


<s> if ( AM . Scale == <NUM_LIT> ) return true ; if ( AM . Scale == <NUM_LIT> && AM . HasBaseReg ) return true ; return false ; } else if ( AS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) { return isLegalMUBUFAddressingMode ( AM ) ; } else if ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS || AS == <ISA_LIT>AS :: REGION_ADDRESS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ; if ( AM . Scale == <NUM_LIT> ) return true ; if ( AM . Scale == <NUM_LIT> && AM . HasBaseReg ) return true ; return false ; } else if ( AS == <ISA_LIT>AS :: FLAT_ADDRESS || AS == <ISA_LIT>AS :: UNKNOWN_ADDRESS_SPACE ) { return isLegalFlatAddressingMode ( AM ) ; } else { llvm_unreachable ( <STR_LIT> ) ; }


<s> if ( AS == <ISA_LIT>AS :: CONSTANT_ADDRESS || AS == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT || AS == <ISA_LIT>AS :: BUFFER_FAT_POINTER ) { if ( AM . BaseOffs % <NUM_LIT> != <NUM_LIT> ) return isLegalMUBUFAddressingMode ( AM ) ; if ( Ty -> isSized ( ) && DL . getTypeStoreSize ( Ty ) < <NUM_LIT> ) return isLegalGlobalAddressingMode ( AM ) ; if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs / <NUM_LIT> ) ) return false ; } else if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs / <NUM_LIT> ) ) return false ; } else if ( Subtarget -> getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ; } else llvm_unreachable ( <STR_LIT> ) ; if ( AM . Scale == <NUM_LIT> ) return true ; if ( AM . Scale == <NUM_LIT> && AM . HasBaseReg ) return true ; return false ; } else if ( AS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) { return isLegalMUBUFAddressingMode ( AM ) ; } else if ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS || AS == <ISA_LIT>AS :: REGION_ADDRESS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ; if ( AM . Scale == <NUM_LIT> ) return true ; if ( AM . Scale == <NUM_LIT> && AM . HasBaseReg ) return true ; return false ; } else if ( AS == <ISA_LIT>AS :: FLAT_ADDRESS || AS == <ISA_LIT>AS :: UNKNOWN_ADDRESS_SPACE ) { return isLegalFlatAddressingMode ( AM ) ; } else {


<s> if ( Subtarget -> getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) return isUInt < <NUM_LIT> > ( AM . BaseOffs ) && AM . Scale == <NUM_LIT> ;


<s> static SDValue lowerFCMPIntrinsic ( const <ISA_LIT>TargetLowering & TLI , SDNode * N , SelectionDAG & DAG ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; const auto * CD = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; int CondCode = CD -> getSExtValue ( ) ; if ( CondCode < FCmpInst :: Predicate :: FIRST_FCMP_PREDICATE || CondCode > FCmpInst :: Predicate :: LAST_FCMP_PREDICATE ) { return DAG . getUNDEF ( VT ) ; } SDValue Src0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Src1 = N -> getOperand ( <NUM_LIT> ) ; EVT CmpVT = Src0 . getValueType ( ) ; SDLoc SL ( N ) ; if ( CmpVT == <STR_LIT> && ! TLI . isTypeLegal ( CmpVT ) ) {

Src0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src0 ) ;


<s> bool IsIEEEMode = Info -> getMode ( ) . IEEE ; if ( IsIEEEMode ) return expandFMINNUM_FMAXNUM ( Op . getNode ( ) , DAG ) ; if ( VT == <STR_LIT> ) return splitBinaryVectorOp ( Op , DAG ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerFMINNUM_FMAXNUM ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; const MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool IsIEEEMode = Info -> getMode ( ) . IEEE ; if ( IsIEEEMode ) return expandFMINNUM_FMAXNUM ( Op . getNode ( ) , DAG ) ;

if ( VT == <STR_LIT> ) return splitBinaryVectorOp ( Op , DAG ) ;


<s> const auto * CD = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; int CondCode = CD -> getSExtValue ( ) ; if ( CondCode < ICmpInst :: Predicate :: FIRST_ICMP_PREDICATE || CondCode > ICmpInst :: Predicate :: LAST_ICMP_PREDICATE ) return DAG . getUNDEF ( VT ) ; ICmpInst :: Predicate IcInput = static_cast < ICmpInst :: Predicate > ( CondCode ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; EVT CmpVT = LHS . getValueType ( ) ; if ( CmpVT == <STR_LIT> && ! TLI . isTypeLegal ( <STR_LIT> ) ) { unsigned PromoteOp = ICmpInst :: isSigned ( IcInput ) ? <STR_LIT> : <STR_LIT> ; LHS = DAG . getNode ( PromoteOp , DL , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( PromoteOp , DL , <STR_LIT> , RHS ) ;


<s> if ( ! allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , MemVT , AS , Alignment ) ) { SDValue Ops [ <NUM_LIT> ] ; std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = expandUnalignedLoad ( Load , DAG ) ; return DAG . getMergeValues ( Ops , DL ) ; } if ( Subtarget -> hasLDSMisalignedBug ( ) && AS == <ISA_LIT>AS :: FLAT_ADDRESS && Alignment < MemVT . getStoreSize ( ) && MemVT . getSizeInBits ( ) > <NUM_LIT> ) { return SplitVectorLoad ( Op , DAG ) ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( AS == <ISA_LIT>AS :: FLAT_ADDRESS ) AS = MFI -> hasFlatScratchInit ( ) ? <ISA_LIT>AS :: PRIVATE_ADDRESS : <ISA_LIT>AS :: GLOBAL_ADDRESS ; unsigned NumElements = MemVT . getVectorNumElements ( ) ; if ( AS == <ISA_LIT>AS :: CONSTANT_ADDRESS || AS == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) { if ( ! Op -> isDivergent ( ) && Alignment >= <NUM_LIT> && NumElements < <NUM_LIT> ) { if ( MemVT . isPow2VectorType ( ) ) return SDValue ( ) ; if ( NumElements == <NUM_LIT> ) return WidenVectorLoad ( Op , DAG ) ; return SplitVectorLoad ( Op , DAG ) ; } } if ( AS == <ISA_LIT>AS :: CONSTANT_ADDRESS || AS == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT || AS == <ISA_LIT>AS :: GLOBAL_ADDRESS ) { if ( Subtarget -> getScalarizeGlobalBehavior ( ) && ! Op -> isDivergent ( ) && ! Load -> isVolatile ( ) && isMemOpHasNoClobberedMemOperand ( Load ) && Alignment >= <NUM_LIT> && NumElements < <NUM_LIT> ) { if ( MemVT . isPow2VectorType ( ) ) return SDValue ( ) ; if ( NumElements == <NUM_LIT> ) return WidenVectorLoad ( Op , DAG ) ; return SplitVectorLoad ( Op , DAG ) ; } } if ( AS == <ISA_LIT>AS :: CONSTANT_ADDRESS || AS == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT || AS == <ISA_LIT>AS :: GLOBAL_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS ) { if ( NumElements > <NUM_LIT> ) return SplitVectorLoad ( Op , DAG ) ; if ( NumElements == <NUM_LIT> && ! Subtarget -> hasDwordx3LoadStores ( ) ) return WidenVectorLoad ( Op , DAG ) ; return SDValue ( ) ; } if ( AS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) { switch ( Subtarget -> getMaxPrivateElementSize ( ) ) {


<s> case <STR_LIT> : { SDValue Result = LowerLOAD ( Op , DAG ) ; assert ( ( ! Result . getNode ( ) || Result . getNode ( ) -> getNumValues ( ) == <NUM_LIT> ) && <STR_LIT> ) ; return Result ; } case <STR_LIT> : case <STR_LIT> : return LowerTrig ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerFDIV ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_CMP_SWAP ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; return LowerGlobalAddress ( MFI , Op , DAG ) ; } case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_W_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_VOID ( Op , DAG ) ; case <STR_LIT> : return lowerADDRSPACECAST ( Op , DAG ) ; case <STR_LIT> : return lowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return lowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return lowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return lowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return lowerTRAP ( Op , DAG ) ; case <STR_LIT> : return lowerDEBUGTRAP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return splitUnaryVectorOp ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return lowerFMINNUM_FMAXNUM ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> SDValue <ISA_LIT>TargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { default : return <ISA_LIT>TargetLowering :: LowerOperation ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : { SDValue Result = LowerLOAD ( Op , DAG ) ; assert ( ( ! Result . getNode ( ) || Result . getNode ( ) -> getNumValues ( ) == <NUM_LIT> ) && <STR_LIT> ) ; return Result ; } case <STR_LIT> : case <STR_LIT> : return LowerTrig ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerFDIV ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_CMP_SWAP ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; return LowerGlobalAddress ( MFI , Op , DAG ) ; } case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_W_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_VOID ( Op , DAG ) ; case <STR_LIT> : return lowerADDRSPACECAST ( Op , DAG ) ; case <STR_LIT> : return lowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return lowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return lowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return lowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return lowerTRAP ( Op , DAG ) ; case <STR_LIT> : return lowerDEBUGTRAP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return splitUnaryVectorOp ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return lowerFMINNUM_FMAXNUM ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( Info -> isEntryFunction ( ) ) return DAG . getConstant ( <NUM_LIT> , DL , VT ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; const <ISA_LIT>RegisterInfo * TRI = getSubtarget ( ) -> getRegisterInfo ( ) ; unsigned Reg = MF . addLiveIn ( TRI -> getReturnAddressReg ( MF ) , getRegClassFor ( VT , Op . getNode ( ) -> isDivergent ( ) ) ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , Reg , VT ) ;


<s> } if ( Subtarget -> hasLDSMisalignedBug ( ) && AS == <ISA_LIT>AS :: FLAT_ADDRESS && Store -> getAlignment ( ) < VT . getStoreSize ( ) && VT . getSizeInBits ( ) > <NUM_LIT> ) { return SplitVectorStore ( Op , DAG ) ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( AS == <ISA_LIT>AS :: FLAT_ADDRESS ) AS = MFI -> hasFlatScratchInit ( ) ? <ISA_LIT>AS :: PRIVATE_ADDRESS : <ISA_LIT>AS :: GLOBAL_ADDRESS ; unsigned NumElements = VT . getVectorNumElements ( ) ; if ( AS == <ISA_LIT>AS :: GLOBAL_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS ) { if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; if ( NumElements == <NUM_LIT> && ! Subtarget -> hasDwordx3LoadStores ( ) ) return SplitVectorStore ( Op , DAG ) ; return SDValue ( ) ; } else if ( AS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) { switch ( Subtarget -> getMaxPrivateElementSize ( ) ) { case <NUM_LIT> : return scalarizeVectorStore ( Store , DAG ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; return SDValue ( ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> || NumElements == <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; return SDValue ( ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS ) { if ( Subtarget -> useDS128 ( ) && Store -> getAlignment ( ) >= <NUM_LIT> && VT . getStoreSize ( ) == <NUM_LIT> && NumElements != <NUM_LIT> ) return SDValue ( ) ; if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS && NumElements == <NUM_LIT> && VT . getStoreSize ( ) == <NUM_LIT> && Store -> getAlignment ( ) < <NUM_LIT> ) { return SplitVectorStore ( Op , DAG ) ; } return SDValue ( ) ; } else {


<s> default : llvm_unreachable ( <STR_LIT> ) ; case Type :: IntegerTyID : ElementSize = cast < IntegerType > ( ElementType ) -> getBitWidth ( ) ; break ; case Type :: HalfTyID : ElementSize = <NUM_LIT> ; break ; case Type :: FloatTyID : ElementSize = <NUM_LIT> ; break ; } unsigned AdditionalElts = ElementSize == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; Pow2Elts = <NUM_LIT> << Log2_32_Ceil ( NumElts + AdditionalElts ) ; return <STR_LIT> ( <STR_LIT> ( ElementType , false ) , Pow2Elts ) ;


<s> static bool parseCachePolicy ( SDValue CachePolicy , SelectionDAG & DAG , SDValue * GLC , SDValue * SLC , SDValue * DLC ) { auto CachePolicyConst = cast < ConstantSDNode > ( CachePolicy . getNode ( ) ) ; uint64_t Value = CachePolicyConst -> getZExtValue ( ) ; SDLoc DL ( CachePolicy ) ; if ( GLC ) { * GLC = DAG . getTargetConstant ( ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> , DL , <STR_LIT> ) ; Value &= ~ ( uint64_t ) <NUM_LIT> ; } if ( SLC ) {

* SLC = DAG . getTargetConstant ( ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> , DL , <STR_LIT> ) ;


<s> return getMad64_32 ( DAG , SL , VT , MulLHS , MulRHS , AddRHS , false ) ; } if ( numBitsSigned ( MulLHS , DAG ) < <NUM_LIT> && numBitsSigned ( MulRHS , DAG ) < <NUM_LIT> ) { MulLHS = DAG . getSExtOrTrunc ( MulLHS , SL , <STR_LIT> ) ; MulRHS = DAG . getSExtOrTrunc ( MulRHS , SL , <STR_LIT> ) ; AddRHS = DAG . getSExtOrTrunc ( AddRHS , SL , <STR_LIT> ) ; return getMad64_32 ( DAG , SL , VT , MulLHS , MulRHS , AddRHS , true ) ; } return SDValue ( ) ; } if ( SDValue V = reassociateScalarOps ( N , DAG ) ) { return V ; } if ( VT != <STR_LIT> || ! DCI . isAfterLegalizeDAG ( ) ) return SDValue ( ) ; unsigned Opc = LHS . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) std :: swap ( RHS , LHS ) ; Opc = RHS . getOpcode ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { auto Cond = RHS . getOperand ( <NUM_LIT> ) ; if ( ! isBoolSGPR ( Cond ) ) break ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Args [ ] = { LHS , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) , Cond } ; Opc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , SL , VTList , Args ) ; } case <STR_LIT> : { auto C = dyn_cast < ConstantSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) ; if ( ! C || C -> getZExtValue ( ) != <NUM_LIT> ) break ; SDValue Args [ ] = { LHS , RHS . getOperand ( <NUM_LIT> ) , RHS . getOperand ( <NUM_LIT> ) } ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , RHS -> getVTList ( ) , Args ) ; } }


<s> MulRHS = DAG . getZExtOrTrunc ( MulRHS , SL , <STR_LIT> ) ; AddRHS = DAG . getZExtOrTrunc ( AddRHS , SL , <STR_LIT> ) ; return getMad64_32 ( DAG , SL , VT , MulLHS , MulRHS , AddRHS , false ) ; } if ( numBitsSigned ( MulLHS , DAG ) < <NUM_LIT> && numBitsSigned ( MulRHS , DAG ) < <NUM_LIT> ) { MulLHS = DAG . getSExtOrTrunc ( MulLHS , SL , <STR_LIT> ) ; MulRHS = DAG . getSExtOrTrunc ( MulRHS , SL , <STR_LIT> ) ; AddRHS = DAG . getSExtOrTrunc ( AddRHS , SL , <STR_LIT> ) ; return getMad64_32 ( DAG , SL , VT , MulLHS , MulRHS , AddRHS , true ) ; } return SDValue ( ) ; } if ( SDValue V = reassociateScalarOps ( N , DAG ) ) { return V ; } if ( VT != <STR_LIT> || ! DCI . isAfterLegalizeDAG ( ) ) return SDValue ( ) ; unsigned Opc = LHS . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) std :: swap ( RHS , LHS ) ; Opc = RHS . getOpcode ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { auto Cond = RHS . getOperand ( <NUM_LIT> ) ; if ( ! isBoolSGPR ( Cond ) ) break ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Args [ ] = { LHS , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) , Cond } ; Opc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , SL , VTList , Args ) ; } case <STR_LIT> : { auto C = dyn_cast < ConstantSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) ; if ( ! C || C -> getZExtValue ( ) != <NUM_LIT> ) break ; SDValue Args [ ] = { LHS , RHS . getOperand ( <NUM_LIT> ) , RHS . getOperand ( <NUM_LIT> ) } ;

return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , RHS -> getVTList ( ) , Args ) ;


<s> const APFloat & F = CSrc -> getValueAPF ( ) ; APFloat Zero = APFloat :: getZero ( F . getSemantics ( ) ) ; APFloat :: cmpResult Cmp0 = F . compare ( Zero ) ; if ( Cmp0 == APFloat :: cmpLessThan || ( Cmp0 == APFloat :: cmpUnordered && MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMode ( ) . DX10Clamp ) ) { return DCI . DAG . getConstantFP ( Zero , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; } APFloat One ( F . getSemantics ( ) , <STR_LIT> ) ; APFloat :: cmpResult Cmp1 = F . compare ( One ) ;

if ( Cmp1 == APFloat :: cmpGreaterThan ) return DCI . DAG . getConstantFP ( One , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ;


<s> const APFloat & F = CSrc -> getValueAPF ( ) ; APFloat Zero = APFloat :: getZero ( F . getSemantics ( ) ) ; APFloat :: cmpResult Cmp0 = F . compare ( Zero ) ; if ( Cmp0 == APFloat :: cmpLessThan || ( Cmp0 == APFloat :: cmpUnordered && MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMode ( ) . DX10Clamp ) ) {

return DCI . DAG . getConstantFP ( Zero , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: performCvtF32UByteNCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; SDLoc SL ( N ) ; unsigned Offset = N -> getOpcode ( ) - <STR_LIT> ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; SDValue Srl = N -> getOperand ( <NUM_LIT> ) ; if ( Srl . getOpcode ( ) == <STR_LIT> ) Srl = Srl . getOperand ( <NUM_LIT> ) ;

if ( Srl . getOpcode ( ) == <STR_LIT> ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( DCI . isBeforeLegalize ( ) ) break ; return performMemSDNodeCombine ( cast < MemSDNode > ( N ) , DCI ) ; case <STR_LIT> : return performAndCombine ( N , DCI ) ; case <STR_LIT> : return performOrCombine ( N , DCI ) ; case <STR_LIT> : return performXorCombine ( N , DCI ) ; case <STR_LIT> : return performZeroExtendCombine ( N , DCI ) ; case <STR_LIT> : return performSignExtendInRegCombine ( N , DCI ) ; case <STR_LIT> : return performClassCombine ( N , DCI ) ; case <STR_LIT> : return performFCanonicalizeCombine ( N , DCI ) ; case <STR_LIT> : return performRcpCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . isUndef ( ) ) return Src ; break ; } case <STR_LIT> : case <STR_LIT> : return performUCharToFloatCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performCvtF32UByteNCombine ( N , DCI ) ; case <STR_LIT> : return performFMed3Combine ( N , DCI ) ; case <STR_LIT> : return performCvtPkRTZCombine ( N , DCI ) ; case <STR_LIT> : return performClampCombine ( N , DCI ) ; case <STR_LIT> : { SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { SDLoc SL ( N ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; EVT EltVT = Src . getValueType ( ) ; if ( EltVT == <STR_LIT> ) Src = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; return DAG . getNode ( <STR_LIT> , SL , VT , Ext ) ; } break ; } case <STR_LIT> : return performExtractVectorEltCombine ( N , DCI ) ; case <STR_LIT> : return performInsertVectorEltCombine ( N , DCI ) ; }

return <ISA_LIT>TargetLowering :: PerformDAGCombine ( N , DCI ) ;


<s> SDValue Vec2 = Op2 . getOperand ( <NUM_LIT> ) ; SDValue FMAOp1 = FMA . getOperand ( <NUM_LIT> ) ; SDValue FMAOp2 = FMA . getOperand ( <NUM_LIT> ) ; SDValue FMAAcc = FMA . getOperand ( <NUM_LIT> ) ; if ( FMAOp1 . getOpcode ( ) != <STR_LIT> || FMAOp2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; FMAOp1 = FMAOp1 . getOperand ( <NUM_LIT> ) ; FMAOp2 = FMAOp2 . getOperand ( <NUM_LIT> ) ; if ( FMAOp1 . getOpcode ( ) != <STR_LIT> || FMAOp2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Vec3 = FMAOp1 . getOperand ( <NUM_LIT> ) ; SDValue Vec4 = FMAOp2 . getOperand ( <NUM_LIT> ) ; SDValue Idx2 = FMAOp1 . getOperand ( <NUM_LIT> ) ; if ( Idx1 != Op2 . getOperand ( <NUM_LIT> ) || Idx2 != FMAOp2 . getOperand ( <NUM_LIT> ) || Idx1 == Idx2 ) return SDValue ( ) ; if ( Vec1 == Vec2 || Vec3 == Vec4 ) return SDValue ( ) ; if ( Vec1 . getValueType ( ) != <STR_LIT> || Vec2 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ( Vec1 == Vec3 && Vec2 == Vec4 ) || ( Vec1 == Vec4 && Vec2 == Vec3 ) ) { return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Vec1 , Vec2 , FMAAcc , DAG . getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; }


<s> SDValue Var = Op0 . getOperand ( <NUM_LIT> ) ; if ( ! DAG . isKnownNeverSNaN ( Var ) ) return SDValue ( ) ; const <ISA_LIT>InstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; if ( ( ! K0 -> hasOneUse ( ) || TII -> isInlineConstant ( K0 -> getValueAPF ( ) . bitcastToAPInt ( ) ) ) && ( ! K1 -> hasOneUse ( ) || TII -> isInlineConstant ( K1 -> getValueAPF ( ) . bitcastToAPInt ( ) ) ) ) { return DAG . getNode ( <STR_LIT> , SL , K0 -> getValueType ( <NUM_LIT> ) , Var , SDValue ( K0 , <NUM_LIT> ) , SDValue ( K1 , <NUM_LIT> ) ) ; } } return SDValue ( ) ;


<s> if ( LHS . getOpcode ( ) == <STR_LIT> ) { auto C = dyn_cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) ; if ( ! C || ! C -> isNullValue ( ) ) return SDValue ( ) ; SDValue Args [ ] = { LHS . getOperand ( <NUM_LIT> ) , RHS , LHS . getOperand ( <NUM_LIT> ) } ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , LHS -> getVTList ( ) , Args ) ; } return SDValue ( ) ;


<s> if ( VT != <STR_LIT> ) return SDValue ( ) ; SDLoc SL ( N ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> ) { auto C = dyn_cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) ; if ( ! C || ! C -> isNullValue ( ) ) return SDValue ( ) ;

SDValue Args [ ] = { LHS . getOperand ( <NUM_LIT> ) , RHS , LHS . getOperand ( <NUM_LIT> ) } ;


<s> SDValue Src0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Src1 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Src2 = Node -> getOperand ( <NUM_LIT> ) ; if ( ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) != <STR_LIT> ) && ( Src0 == Src1 || Src0 == Src2 ) ) break ; MVT VT = Src0 . getValueType ( ) . getSimpleVT ( ) ; const TargetRegisterClass * RC = getRegClassFor ( VT , Src0 . getNode ( ) -> isDivergent ( ) ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue UndefReg = DAG . getRegister ( MRI . createVirtualRegister ( RC ) , VT ) ; SDValue ImpDef = DAG . getCopyToReg ( DAG . getEntryNode ( ) , SDLoc ( Node ) , UndefReg , Src0 , SDValue ( ) ) ; if ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) == <STR_LIT> ) { if ( Src1 . isMachineOpcode ( ) && Src1 . getMachineOpcode ( ) != <STR_LIT> ) Src0 = Src1 ; else if ( Src2 . isMachineOpcode ( ) && Src2 . getMachineOpcode ( ) != <STR_LIT> ) Src0 = Src2 ; else { assert ( Src1 . getMachineOpcode ( ) == <STR_LIT> ) ; Src0 = UndefReg ; Src1 = UndefReg ; } } else break ;

SmallVector < SDValue , <NUM_LIT> > Ops = { Src0 , Src1 , Src2 } ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; unsigned Opc = N -> getOpcode ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ! ( Op0 -> isDivergent ( ) ^ Op1 -> isDivergent ( ) ) ) return SDValue ( ) ; if ( Op0 -> isDivergent ( ) ) std :: swap ( Op0 , Op1 ) ; if ( Op1 . getOpcode ( ) != Opc || ! Op1 . hasOneUse ( ) ) return SDValue ( ) ; SDValue Op2 = Op1 . getOperand ( <NUM_LIT> ) ; Op1 = Op1 . getOperand ( <NUM_LIT> ) ; if ( ! ( Op1 -> isDivergent ( ) ^ Op2 -> isDivergent ( ) ) ) return SDValue ( ) ;

if ( Op1 -> isDivergent ( ) ) std :: swap ( Op1 , Op2 ) ;


<s> if ( Op1 -> isDivergent ( ) ) std :: swap ( Op1 , Op2 ) ; if ( DAG . isConstantIntBuildVectorOrConstantInt ( Op0 ) || DAG . isConstantIntBuildVectorOrConstantInt ( Op1 ) ) return SDValue ( ) ; SDLoc SL ( N ) ; SDValue Add1 = DAG . getNode ( Opc , SL , VT , Op0 , Op1 ) ;

return DAG . getNode ( Opc , SL , VT , Add1 , Op2 ) ;


<s> case <STR_LIT> : return true ; } } if ( const ExtractValueInst * ExtValue = dyn_cast < ExtractValueInst > ( V ) ) { if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( ExtValue -> getOperand ( <NUM_LIT> ) ) ) { switch ( Intrinsic -> getIntrinsicID ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : { ArrayRef < unsigned > Indices = ExtValue -> getIndices ( ) ; if ( Indices . size ( ) == <NUM_LIT> && Indices [ <NUM_LIT> ] == <NUM_LIT> ) { return true ; } } } } } if ( const CallInst * CI = dyn_cast < CallInst > ( V ) ) { if ( isa < InlineAsm > ( CI -> getCalledValue ( ) ) ) { const <ISA_LIT>RegisterInfo * <ISA_LIT>RI = Subtarget -> getRegisterInfo ( ) ; ImmutableCallSite CS ( CI ) ; TargetLowering :: AsmOperandInfoVector TargetConstraints = ParseConstraints ( MF . getDataLayout ( ) , Subtarget -> getRegisterInfo ( ) , CS ) ; for ( auto & TC : TargetConstraints ) { if ( TC . Type == InlineAsm :: isOutput ) { ComputeConstraintToUse ( TC , SDValue ( ) ) ;


<s> MachineBasicBlock :: iterator I ( & MI ) ; const MachineOperand * Idx = TII -> getNamedOperand ( MI , <STR_LIT> :: idx ) ; const TargetRegisterClass * IdxRC = MRI . getRegClass ( Idx -> getReg ( ) ) ; assert ( Idx -> getReg ( ) != <STR_LIT> ) ; if ( ! TII -> getRegisterInfo ( ) . isSGPRClass ( IdxRC ) ) return false ; if ( UseGPRIdxMode ) { unsigned IdxMode = IsIndirectSrc ? <STR_LIT> :: SRC0_ENABLE : <STR_LIT> :: DST_ENABLE ; if ( Offset == <NUM_LIT> ) { MachineInstr * SetOn = BuildMI ( * MBB , I , DL , TII -> get ( <STR_LIT> ) ) . add ( * Idx ) . addImm ( IdxMode ) ; SetOn -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; } else {

unsigned Tmp = MRI . createVirtualRegister ( & <STR_LIT> ) ;


<s> return ( GV -> getValueType ( ) -> isFunctionTy ( ) || GV -> getType ( ) -> getAddressSpace ( ) == <ISA_LIT>AS :: GLOBAL_ADDRESS || GV -> getType ( ) -> getAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS || GV -> getType ( ) -> getAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) && ! shouldEmitFixup ( GV ) && ! getTargetMachine ( ) . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ;


<s> bool <ISA_LIT>TargetLowering :: shouldEmitGOTReloc ( const GlobalValue * GV ) const { return ( GV -> getValueType ( ) -> isFunctionTy ( ) || GV -> getType ( ) -> getAddressSpace ( ) == <ISA_LIT>AS :: GLOBAL_ADDRESS || GV -> getType ( ) -> getAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS || GV -> getType ( ) -> getAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) && ! shouldEmitFixup ( GV ) && ! getTargetMachine ( ) . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ;


<s> return ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS && Subtarget -> hasLDSFPAtomics ( ) ) ? AtomicExpansionKind :: None : AtomicExpansionKind :: CmpXChg ; } default : break ; } return <ISA_LIT>TargetLowering :: shouldExpandAtomicRMWInIR ( RMW ) ;


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ;


<s> if ( Unpacked && LoadVT . isVector ( ) ) { EquivLoadVT = LoadVT . isVector ( ) ? EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , LoadVT . getVectorNumElements ( ) ) : LoadVT ; } SDVTList VTList = DAG . getVTList ( EquivLoadVT , <STR_LIT> ) ; SDValue Load = DAG . getMemIntrinsicNode ( IsIntrinsic ? ( unsigned ) <STR_LIT> : Opcode , DL , VTList , Ops , M -> getMemoryVT ( ) , M -> getMemOperand ( ) ) ;


<s> if ( ST -> supportsMinMaxDenormModes ( ) && DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) ) && DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) ) ) return true ; return ( MaxDepth > <NUM_LIT> ) && isCanonicalized ( DAG , Op . getOperand ( <NUM_LIT> ) , ST , MaxDepth - <NUM_LIT> ) && isCanonicalized ( DAG , Op . getOperand ( <NUM_LIT> ) , ST , MaxDepth - <NUM_LIT> ) ; case <STR_LIT> : { auto F = cast < ConstantFPSDNode > ( Op ) -> getValueAPF ( ) ; return ! F . isDenormal ( ) && ! ( F . isNaN ( ) && F . isSignaling ( ) ) ; } } return false ;


<s> return Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) != <STR_LIT> || ST -> hasFP16Denormals ( ) ; case <STR_LIT> : case <STR_LIT> : return ST -> hasFP16Denormals ( ) ; case <STR_LIT> : case <STR_LIT> : return ( MaxDepth > <NUM_LIT> ) && isCanonicalized ( DAG , Op . getOperand ( <NUM_LIT> ) , ST , MaxDepth - <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Op . getValueType ( ) . getScalarType ( ) != <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ST -> supportsMinMaxDenormModes ( ) && DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) ) && DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) ) ) return true ; return ( MaxDepth > <NUM_LIT> ) && isCanonicalized ( DAG , Op . getOperand ( <NUM_LIT> ) , ST , MaxDepth - <NUM_LIT> ) && isCanonicalized ( DAG , Op . getOperand ( <NUM_LIT> ) , ST , MaxDepth - <NUM_LIT> ) ; case <STR_LIT> : {

auto F = cast < ConstantFPSDNode > ( Op ) -> getValueAPF ( ) ;


<s> EVT LoadVT = Op . getValueType ( ) ; bool IsD16 = LoadVT . getScalarType ( ) == <STR_LIT> ; if ( IsD16 ) return adjustLoadValueType ( <STR_LIT> , M , DAG ) ; return DAG . getMemIntrinsicNode ( Opc , DL , Op -> getVTList ( ) , Ops , IntVT , M -> getMemOperand ( ) ) ; } case <STR_LIT> : { MemSDNode * M = cast < MemSDNode > ( Op ) ; EVT LoadVT = Op . getValueType ( ) ; bool IsD16 = LoadVT . getScalarType ( ) == <STR_LIT> ; if ( IsD16 ) { return adjustLoadValueType ( <STR_LIT> , M , DAG ) ; } SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Ops , LoadVT , M -> getMemOperand ( ) ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ; EVT VT = Op . getValueType ( ) ;