<s> bool Mask = ( Chan != TRI . getHWRegChan ( DstReg ) ) ; unsigned SubDstReg = <STR_LIT> . getRegister ( ( DstBase * <NUM_LIT> ) + Chan ) ; MachineInstr * BMI = TII -> buildSlotOfVectorInstruction ( MBB , & MI , Chan , SubDstReg ) ; if ( Chan > <NUM_LIT> ) { BMI -> bundleWithPred ( ) ; } if ( Mask ) { TII -> addFlag ( * BMI , <NUM_LIT> , MO_FLAG_MASK ) ; } if ( Chan != <NUM_LIT> ) TII -> addFlag ( * BMI , <NUM_LIT> , MO_FLAG_NOT_LAST ) ; unsigned Opcode = BMI -> getOpcode ( ) ; unsigned Src0 = BMI -> getOperand ( TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0 ) ) . getReg ( ) ; unsigned Src1 = BMI -> getOperand ( TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1 ) ) . getReg ( ) ; ( void ) Src0 ; ( void ) Src1 ; if ( ( TRI . getEncodingValue ( Src0 ) & <NUM_LIT> ) < <NUM_LIT> && ( TRI . getEncodingValue ( Src1 ) & <NUM_LIT> ) < <NUM_LIT> ) assert ( TRI . getHWRegChan ( Src0 ) == TRI . getHWRegChan ( Src1 ) ) ; } MI . eraseFromParent ( ) ; continue ; } } bool IsReduction = TII -> isReductionOp ( MI . getOpcode ( ) ) ; bool IsVector = TII -> isVector ( MI ) ; bool IsCube = TII -> isCubeOp ( MI . getOpcode ( ) ) ; if ( ! IsReduction && ! IsVector && ! IsCube ) { continue ; } for ( unsigned Chan = <NUM_LIT> ; Chan < <NUM_LIT> ; Chan ++ ) { unsigned DstReg = MI . getOperand ( TII -> getOperandIdx ( MI , <STR_LIT> :: dst ) ) . getReg ( ) ; unsigned Src0 = MI . getOperand ( TII -> getOperandIdx ( MI , <STR_LIT> :: src0 ) ) . getReg ( ) ; unsigned Src1 = <NUM_LIT> ; if ( ! IsCube ) { int Src1Idx = TII -> getOperandIdx ( MI , <STR_LIT> :: src1 ) ; if ( Src1Idx != - <NUM_LIT> ) { Src1 = MI . getOperand ( Src1Idx ) . getReg ( ) ; } } if ( IsReduction ) { unsigned SubRegIndex = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( Chan ) ; Src0 = TRI . getSubReg ( Src0 , SubRegIndex ) ; Src1 = TRI . getSubReg ( Src1 , SubRegIndex ) ; } else if ( IsCube ) { static const int CubeSrcSwz [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; unsigned SubRegIndex0 = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( CubeSrcSwz [ Chan ] ) ; unsigned SubRegIndex1 = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( CubeSrcSwz [ <NUM_LIT> - Chan ] ) ; Src1 = TRI . getSubReg ( Src0 , SubRegIndex1 ) ; Src0 = TRI . getSubReg ( Src0 , SubRegIndex0 ) ; } bool Mask = false ; bool NotLast = true ;


<s> uint64_t Val = OldMI -> getOperand ( OpIdx ) . getImm ( ) ; TII -> setImmOperand ( * NewMI , Op , Val ) ; }


<s> void <ISA_LIT>ExpandSpecialInstrsPass :: SetFlagInNewMI ( MachineInstr * NewMI , const MachineInstr * OldMI , unsigned Op ) { int OpIdx = TII -> getOperandIdx ( * OldMI , Op ) ; if ( OpIdx > - <NUM_LIT> ) { uint64_t Val = OldMI -> getOperand ( OpIdx ) . getImm ( ) ;

TII -> setImmOperand ( NewMI , Op , Val ) ;


<s> if ( OpIdx > - <NUM_LIT> ) { uint64_t Val = OldMI -> getOperand ( OpIdx ) . getImm ( ) ; TII -> setImmOperand ( NewMI , Op , Val ) ; }


<s> for ( unsigned Chan = <NUM_LIT> ; Chan < <NUM_LIT> ; Chan ++ ) { Register DstReg = MI . getOperand ( TII -> getOperandIdx ( MI , <STR_LIT> :: dst ) ) . getReg ( ) ; Register Src0 = MI . getOperand ( TII -> getOperandIdx ( MI , <STR_LIT> :: src0 ) ) . getReg ( ) ; unsigned Src1 = <NUM_LIT> ; if ( ! IsCube ) { int Src1Idx = TII -> getOperandIdx ( MI , <STR_LIT> :: src1 ) ; if ( Src1Idx != - <NUM_LIT> ) { Src1 = MI . getOperand ( Src1Idx ) . getReg ( ) ; } } if ( IsReduction ) { unsigned SubRegIndex = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( Chan ) ; Src0 = TRI . getSubReg ( Src0 , SubRegIndex ) ; Src1 = TRI . getSubReg ( Src1 , SubRegIndex ) ; } else if ( IsCube ) { static const int CubeSrcSwz [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; unsigned SubRegIndex0 = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( CubeSrcSwz [ Chan ] ) ; unsigned SubRegIndex1 = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( CubeSrcSwz [ <NUM_LIT> - Chan ] ) ; Src1 = TRI . getSubReg ( Src0 , SubRegIndex1 ) ; Src0 = TRI . getSubReg ( Src0 , SubRegIndex0 ) ; } bool Mask = false ; bool NotLast = true ; if ( IsCube ) { unsigned SubRegIndex = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( Chan ) ; DstReg = TRI . getSubReg ( DstReg , SubRegIndex ) ; } else { Mask = ( Chan != TRI . getHWRegChan ( DstReg ) ) ; unsigned DstBase = TRI . getEncodingValue ( DstReg ) & HW_REG_MASK ; DstReg = <STR_LIT> . getRegister ( ( DstBase * <NUM_LIT> ) + Chan ) ; } NotLast = ( Chan != <NUM_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : break ; } MachineInstr * NewMI = TII -> buildDefaultInstruction ( MBB , I , Opcode , DstReg , Src0 , Src1 ) ; if ( Chan != <NUM_LIT> ) NewMI -> bundleWithPred ( ) ; if ( Mask ) {

TII -> addFlag ( * NewMI , <NUM_LIT> , MO_FLAG_MASK ) ;


<s> <ISA_LIT>ExpandSpecialInstrsPass ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TII ( nullptr ) {


<s> <ISA_LIT>ExpandSpecialInstrsPass ( ) : MachineFunctionPass ( ID ) , TII ( nullptr ) {


<s> StackOffset <ISA_LIT>FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>RegisterInfo * RI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; FrameReg = RI -> getFrameRegister ( MF ) ; unsigned OffsetBytes = <NUM_LIT> * ( getStackWidth ( MF ) * <NUM_LIT> ) ; int UpperBound = FI == - <NUM_LIT> ? MFI . getNumObjects ( ) : FI ;

for ( int i = MFI . getObjectIndexBegin ( ) ; i < UpperBound ; ++ i ) {


<s> StackOffset <ISA_LIT>FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>RegisterInfo * RI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ;

FrameReg = RI -> getFrameRegister ( MF ) ;


<s> void emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


<s> void emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


<s> for ( int i = MFI . getObjectIndexBegin ( ) ; i < UpperBound ; ++ i ) { OffsetBytes = alignTo ( OffsetBytes , MFI . getObjectAlign ( i ) ) ; OffsetBytes += MFI . getObjectSize ( i ) ; OffsetBytes = alignTo ( OffsetBytes , Align ( <NUM_LIT> ) ) ;


<s> <ISA_LIT>FrameLowering ( StackDirection D , Align StackAl , int LAO , Align TransAl = Align :: None ( ) ) : <ISA_LIT>FrameLowering ( D , StackAl , LAO , TransAl ) {


<s> <ISA_LIT>FrameLowering ( StackDirection D , Align StackAl , int LAO , unsigned TransAl = <NUM_LIT> ) : <ISA_LIT>FrameLowering ( D , StackAl , LAO , TransAl ) {


<s> <ISA_LIT>FrameLowering :: ~ <ISA_LIT>FrameLowering ( ) {


<s> void emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const override {


<s> void emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const override {


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>RegisterInfo * RI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; FrameReg = RI -> getFrameRegister ( MF ) ; unsigned OffsetBytes = <NUM_LIT> * ( getStackWidth ( MF ) * <NUM_LIT> ) ; int UpperBound = FI == - <NUM_LIT> ? MFI . getNumObjects ( ) : FI ; for ( int i = MFI . getObjectIndexBegin ( ) ; i < UpperBound ; ++ i ) { OffsetBytes = alignTo ( OffsetBytes , MFI . getObjectAlignment ( i ) ) ; OffsetBytes += MFI . getObjectSize ( i ) ;

OffsetBytes = alignTo ( OffsetBytes , <NUM_LIT> ) ;


<s> <ISA_LIT>FrameLowering ( StackDirection D , Align StackAl , int LAO , Align TransAl = Align ( <NUM_LIT> ) ) : <ISA_LIT>FrameLowering ( D , StackAl , LAO , TransAl ) {


<s> O << <STR_LIT> ; printOperand ( MI , OpNo + <NUM_LIT> , O ) ;


<s> O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; }


<s> while ( I != MBB . begin ( ) && std :: prev ( I ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PriorI = std :: prev ( I ) ; if ( AllowModify ) I -> removeFromParent ( ) ; I = PriorI ; } MachineInstr & LastInst = * I ; unsigned LastOpc = LastInst . getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isJump ( ( -- I ) -> getOpcode ( ) ) ) { if ( LastOpc == <STR_LIT> ) { TBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( LastOpc == <STR_LIT> ) { auto predSet = I ; while ( ! isPredicateSetter ( predSet -> getOpcode ( ) ) ) { predSet = -- I ; } TBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( <STR_LIT> , false ) ) ; return false ; } return true ; } MachineInstr & SecondLastInst = * I ;

unsigned SecondLastOpc = SecondLastInst . getOpcode ( ) ;


<s> if ( isBranch ( I -> getOpcode ( ) ) ) return true ; if ( ! isJump ( I -> getOpcode ( ) ) ) { return false ; } while ( I != MBB . begin ( ) && std :: prev ( I ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PriorI = std :: prev ( I ) ; if ( AllowModify ) I -> removeFromParent ( ) ; I = PriorI ; } MachineInstr & LastInst = * I ; unsigned LastOpc = LastInst . getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isJump ( ( -- I ) -> getOpcode ( ) ) ) { if ( LastOpc == <STR_LIT> ) { TBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( LastOpc == <STR_LIT> ) { auto predSet = I ; while ( ! isPredicateSetter ( predSet -> getOpcode ( ) ) ) { predSet = -- I ; } TBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( <STR_LIT> , false ) ) ; return false ; } return true ; } MachineInstr & SecondLastInst = * I ; unsigned SecondLastOpc = SecondLastInst . getOpcode ( ) ; if ( SecondLastOpc == <STR_LIT> && LastOpc == <STR_LIT> ) { auto predSet = -- I ; while ( ! isPredicateSetter ( predSet -> getOpcode ( ) ) ) { predSet = -- I ; }

TBB = SecondLastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ;


<s> if ( Src1Reg ) { MIB . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } MIB . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( Src0Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( - <NUM_LIT> ) ; if ( Src1Reg ) { MIB . addReg ( Src1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( - <NUM_LIT> ) ; }

MIB . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> } MachineInstr * MOVA = buildDefaultInstruction ( * MBB , I , <STR_LIT> , <STR_LIT> , OffsetReg ) ; setImmOperand ( * MOVA , <STR_LIT> :: write , <NUM_LIT> ) ; MachineInstrBuilder Mov = buildDefaultInstruction ( * MBB , I , <STR_LIT> , ValueReg , AddrReg ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) ; setImmOperand ( * Mov , <STR_LIT> :: src0_rel , <NUM_LIT> ) ;


<s> case <NUM_LIT> : AddrReg = <STR_LIT> . getRegister ( Address ) ; break ; case <NUM_LIT> : AddrReg = <STR_LIT> . getRegister ( Address ) ; break ; case <NUM_LIT> : AddrReg = <STR_LIT> . getRegister ( Address ) ; break ; case <NUM_LIT> : AddrReg = <STR_LIT> . getRegister ( Address ) ; break ; } MachineInstr * MOVA = buildDefaultInstruction ( * MBB , I , <STR_LIT> , <STR_LIT> , OffsetReg ) ; setImmOperand ( * MOVA , <STR_LIT> :: write , <NUM_LIT> ) ; MachineInstrBuilder Mov = buildDefaultInstruction ( * MBB , I , <STR_LIT> , AddrReg , ValueReg ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) ; setImmOperand ( * Mov , <STR_LIT> :: dst_rel , <NUM_LIT> ) ;


<s> if ( isVector ( MI ) || isCubeOp ( MI . getOpcode ( ) ) ) return true ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ;


<s> VectorComponents = <NUM_LIT> ; } else if ( ( <STR_LIT> . contains ( DestReg ) || <STR_LIT> . contains ( DestReg ) ) && ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ) { VectorComponents = <NUM_LIT> ; } if ( VectorComponents > <NUM_LIT> ) { for ( unsigned I = <NUM_LIT> ; I < VectorComponents ; I ++ ) { unsigned SubRegIndex = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( I ) ; buildDefaultInstruction ( MBB , MI , <STR_LIT> , RI . getSubReg ( DestReg , SubRegIndex ) , RI . getSubReg ( SrcReg , SubRegIndex ) ) . addReg ( DestReg , RegState :: Define | RegState :: Implicit ) ; } } else { MachineInstr * NewMI = buildDefaultInstruction ( MBB , MI , <STR_LIT> , DestReg , SrcReg ) ;

NewMI -> getOperand ( getOperandIdx ( * NewMI , <STR_LIT> :: src0 ) ) . setIsKill ( KillSrc ) ;


<s> const InstrItineraryData * II = STI . getInstrItineraryData ( ) ; return static_cast < const <ISA_LIT>Subtarget & > ( STI ) . createDFAPacketizer ( II ) ;


<s> return static_cast < const <ISA_LIT>Subtarget & > ( STI ) . createDFAPacketizer ( II ) ;


<s> return MI . findRegisterDefOperandIdx ( <STR_LIT> , false , false , & RI ) != - <NUM_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: DefinesPredicate ( MachineInstr & MI , std :: vector < MachineOperand > & Pred ) const {

return isPredicateSetter ( MI . getOpcode ( ) ) ;


<s> bool <ISA_LIT>InstrInfo :: DefinesPredicate ( MachineInstr & MI , std :: vector < MachineOperand > & Pred ) const { return isPredicateSetter ( MI . getOpcode ( ) ) ;


<s> int Index = RI . getEncodingValue ( Reg ) & <NUM_LIT> ; if ( Reg == <STR_LIT> ) { Result . push_back ( std :: make_pair ( Index , <NUM_LIT> ) ) ; } if ( PV . find ( Reg ) != PV . end ( ) ) { Result . push_back ( std :: make_pair ( <NUM_LIT> , <NUM_LIT> ) ) ; continue ; } if ( Index > <NUM_LIT> ) { ConstCount ++ ; Result . push_back ( DummyPair ) ; continue ; } unsigned Chan = RI . getHWRegChan ( Reg ) ; Result . push_back ( std :: make_pair ( Index , Chan ) ) ; } for ( ; i < <NUM_LIT> ; ++ i ) Result . push_back ( DummyPair ) ;


<s> if ( isPredicateSetter ( MI . getOpcode ( ) ) ) return & MI ; } return nullptr ;


<s> -- I ; MachineInstr & MI = * I ; if ( isPredicateSetter ( MI . getOpcode ( ) ) ) return & MI ; } return nullptr ;


<s> static MachineBasicBlock :: iterator FindLastAluClause ( MachineBasicBlock & MBB ) { for ( MachineBasicBlock :: reverse_iterator It = MBB . rbegin ( ) , E = MBB . rend ( ) ; It != E ; ++ It ) { if ( It -> getOpcode ( ) == <STR_LIT> || It -> getOpcode ( ) == <STR_LIT> ) return It . getReverse ( ) ; } return MBB . end ( ) ;


<s> ValidUpTo = isLegalUpTo ( IGSrcs , SwzCandidate , TransSrcs , TransSwz ) ; if ( ValidUpTo == IGSrcs . size ( ) ) return true ; } while ( NextPossibleSolution ( SwzCandidate , ValidUpTo ) ) ; return false ;


<s> bool <ISA_LIT>InstrInfo :: FindSwizzleForVectorSlot ( const std :: vector < std :: vector < std :: pair < int , unsigned >> > & IGSrcs , std :: vector < <ISA_LIT>InstrInfo :: BankSwizzle > & SwzCandidate , const std :: vector < std :: pair < int , unsigned >> & TransSrcs , <ISA_LIT>InstrInfo :: BankSwizzle TransSwz ) const { unsigned ValidUpTo = <NUM_LIT> ; do { ValidUpTo = isLegalUpTo ( IGSrcs , SwzCandidate , TransSrcs , TransSwz ) ; if ( ValidUpTo == IGSrcs . size ( ) ) return true ;

} while ( NextPossibleSolution ( SwzCandidate , ValidUpTo ) ) ;


<s> if ( Literals . size ( ) > <NUM_LIT> ) return false ; if ( Src . first -> getReg ( ) == <STR_LIT> ) Consts . push_back ( Src . second ) ; if ( <STR_LIT> . contains ( Src . first -> getReg ( ) ) || <STR_LIT> . contains ( Src . first -> getReg ( ) ) ) {

unsigned Index = RI . getEncodingValue ( Src . first -> getReg ( ) ) & <NUM_LIT> ;


<s> const TargetRegisterClass * <ISA_LIT>InstrInfo :: getIndirectAddrRegClass ( ) const { return & <STR_LIT> ;


<s> const TargetRegisterClass * IndirectRC = getIndirectAddrRegClass ( ) ; for ( std :: pair < unsigned , unsigned > LI : MRI . liveins ( ) ) { unsigned Reg = LI . first ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) || ! IndirectRC -> contains ( Reg ) ) continue ; unsigned RegIndex ; unsigned RegEnd ; for ( RegIndex = <NUM_LIT> , RegEnd = IndirectRC -> getNumRegs ( ) ; RegIndex != RegEnd ; ++ RegIndex ) { if ( IndirectRC -> getRegister ( RegIndex ) == Reg ) break ; } Offset = std :: max ( Offset , ( int ) RegIndex ) ; }


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MFI . hasVarSizedObjects ( ) ) { return - <NUM_LIT> ; } if ( MFI . getNumObjects ( ) == <NUM_LIT> ) { return - <NUM_LIT> ; } const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

const <ISA_LIT>FrameLowering * TFL = ST . getFrameLowering ( ) ;


<s> const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFL = ST . getFrameLowering ( ) ; unsigned IgnoredFrameReg ; Offset = TFL -> getFrameIndexReference ( MF , - <NUM_LIT> , IgnoredFrameReg ) ;

return getIndirectIndexBegin ( MF ) + Offset ;


<s> unsigned int <ISA_LIT>InstrInfo :: getPredicationCost ( const MachineInstr & ) const {


<s> case <ISA_LIT>InstrInfo :: ALU_VEC_012_SCL_210 : { unsigned Cycles [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return Cycles [ Op ] ; } case <ISA_LIT>InstrInfo :: ALU_VEC_021_SCL_122 : { unsigned Cycles [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return Cycles [ Op ] ; } case <ISA_LIT>InstrInfo :: ALU_VEC_120_SCL_212 : { unsigned Cycles [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return Cycles [ Op ] ; } case <ISA_LIT>InstrInfo :: ALU_VEC_102_SCL_221 : { unsigned Cycles [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return Cycles [ Op ] ; } default : llvm_unreachable ( <STR_LIT> ) ;


<s> } case <ISA_LIT>InstrInfo :: ALU_VEC_021_SCL_122 : { unsigned Cycles [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return Cycles [ Op ] ; } case <ISA_LIT>InstrInfo :: ALU_VEC_120_SCL_212 : { unsigned Cycles [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return Cycles [ Op ] ; } case <ISA_LIT>InstrInfo :: ALU_VEC_102_SCL_221 : {


<s> if ( Cond . empty ( ) ) { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } else { MachineInstr * PredSet = findFirstPredicateSetterFrom ( MBB , MBB . end ( ) ) ; assert ( PredSet && <STR_LIT> ) ; addFlag ( * PredSet , <NUM_LIT> , MO_FLAG_PUSH ) ; PredSet -> getOperand ( <NUM_LIT> ) . setImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( <STR_LIT> , RegState :: Kill ) ; MachineBasicBlock :: iterator CfAlu = FindLastAluClause ( MBB ) ; if ( CfAlu == MBB . end ( ) ) return <NUM_LIT> ; assert ( CfAlu -> getOpcode ( ) == <STR_LIT> ) ;

CfAlu -> setDesc ( get ( <STR_LIT> ) ) ;


<s> static bool isBranch ( unsigned Opcode ) { return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> const std :: pair < int , unsigned > & Src = TransOps [ i ] ; unsigned Cycle = getTransSwizzle ( TransSwz , i ) ; if ( Src . first < <NUM_LIT> ) continue ; if ( ConstCount > <NUM_LIT> && Cycle == <NUM_LIT> ) return false ; if ( ConstCount > <NUM_LIT> && Cycle == <NUM_LIT> ) return false ; } return true ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> static bool isJump ( unsigned Opcode ) { return Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> return isLD<ISA_LIT>nstr ( Opcode ) && getOperandIdx ( Opcode , <STR_LIT> :: dst ) != - <NUM_LIT> ;


<s> const std :: vector < std :: pair < int , unsigned >> & Srcs = Swizzle ( IGSrcs [ i ] , Swz [ i ] ) ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) { const std :: pair < int , unsigned > & Src = Srcs [ j ] ; if ( Src . first < <NUM_LIT> || Src . first == <NUM_LIT> ) continue ; if ( Src . first == GET_REG_INDEX ( RI . getEncodingValue ( <STR_LIT> ) ) ) { if ( Swz [ i ] != <ISA_LIT>InstrInfo :: ALU_VEC_012_SCL_210 && Swz [ i ] != <ISA_LIT>InstrInfo :: ALU_VEC_021_SCL_122 ) { return false ; } continue ; } if ( Vector [ Src . second ] [ j ] < <NUM_LIT> ) Vector [ Src . second ] [ j ] = Src . first ; if ( Vector [ Src . second ] [ j ] != Src . first ) return i ; } } for ( unsigned i = <NUM_LIT> , e = TransSrcs . size ( ) ; i < e ; ++ i ) {

const std :: pair < int , unsigned > & Src = TransSrcs [ i ] ;


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; }


<s> if ( MI . getParent ( ) -> begin ( ) != MachineBasicBlock :: const_iterator ( MI ) ) return false ; return MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ; } else if ( isVector ( MI ) ) { return false ; } else {

return TargetInstrInfo :: isPredicable ( MI ) ;


<s> } else if ( MI . getOpcode ( ) == <STR_LIT> ) { if ( MI . getParent ( ) -> begin ( ) != MachineBasicBlock :: const_iterator ( MI ) ) return false ; return MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ; } else if ( isVector ( MI ) ) { return false ;


<s> if ( idx < <NUM_LIT> ) return false ; unsigned Reg = MI . getOperand ( idx ) . getReg ( ) ; switch ( Reg ) {


<s> static bool isPredicateSetter ( unsigned Opcode ) { switch ( Opcode ) { case <STR_LIT> : return true ; default : return false ;


<s> static bool isPredicateSetter ( unsigned Opcode ) { switch ( Opcode ) { case <STR_LIT> : return true ; default : return false ; }


<s> bool <ISA_LIT>InstrInfo :: isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , BranchProbability Probability ) const {


<s> bool <ISA_LIT>InstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , unsigned ExtraPredCycles , BranchProbability Probability ) const {


<s> bool <ISA_LIT>InstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , unsigned ExtraPredCycles , BranchProbability Probability ) const { return true ;


<s> return isTransOnly ( MI . getOpcode ( ) ) ;


<s> bool <ISA_LIT>InstrInfo :: isVectorOnly ( const MachineInstr & MI ) const {

return isVectorOnly ( MI . getOpcode ( ) ) ;


<s> return true ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { MI . getOperand ( getOperandIdx ( MI , <STR_LIT> :: pred_sel_X ) ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; MI . getOperand ( getOperandIdx ( MI , <STR_LIT> :: pred_sel_Y ) ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; MI . getOperand ( getOperandIdx ( MI , <STR_LIT> :: pred_sel_Z ) ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; MI . getOperand ( getOperandIdx ( MI , <STR_LIT> :: pred_sel_W ) ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; MachineInstrBuilder MIB ( * MI . getParent ( ) -> getParent ( ) , MI ) ; MIB . addReg ( <STR_LIT> , RegState :: Implicit ) ; return true ; } if ( PIdx != - <NUM_LIT> ) {

MachineOperand & PMO = MI . getOperand ( PIdx ) ;


<s> MI . getOperand ( <NUM_LIT> ) . setImm ( <NUM_LIT> ) ; return true ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { MI . getOperand ( getOperandIdx ( MI , <STR_LIT> :: pred_sel_X ) ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; MI . getOperand ( getOperandIdx ( MI , <STR_LIT> :: pred_sel_Y ) ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; MI . getOperand ( getOperandIdx ( MI , <STR_LIT> :: pred_sel_Z ) ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; MI . getOperand ( getOperandIdx ( MI , <STR_LIT> :: pred_sel_W ) ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; MachineInstrBuilder MIB ( * MI . getParent ( ) -> getParent ( ) , MI ) ; MIB . addReg ( <STR_LIT> , RegState :: Implicit ) ; return true ; } if ( PIdx != - <NUM_LIT> ) { MachineOperand & PMO = MI . getOperand ( PIdx ) ; PMO . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; MachineInstrBuilder MIB ( * MI . getParent ( ) -> getParent ( ) , MI ) ; MIB . addReg ( <STR_LIT> , RegState :: Implicit ) ; return true ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & ST ) : <ISA_LIT>GenInstrInfo ( - <NUM_LIT> , - <NUM_LIT> ) , RI ( ) , ST ( ST ) {


<s> if ( ! I -> isReg ( ) || ! I -> isUse ( ) || TargetRegisterInfo :: isVirtualRegister ( I -> getReg ( ) ) ) continue ;

if ( <STR_LIT> . contains ( I -> getReg ( ) ) ) return true ;


if ( ! I -> isReg ( ) || ! I -> isUse ( ) || TargetRegisterInfo :: isVirtualRegister ( I -> getReg ( ) ) ) continue ;


<s> MachineBasicBlock :: iterator I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) { return <NUM_LIT> ; } -- I ; switch ( I -> getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : { MachineInstr * predSet = findFirstPredicateSetterFrom ( MBB , I ) ; clearFlag ( * predSet , <NUM_LIT> , MO_FLAG_PUSH ) ; I -> eraseFromParent ( ) ; MachineBasicBlock :: iterator CfAlu = FindLastAluClause ( MBB ) ; if ( CfAlu == MBB . end ( ) ) break ; assert ( CfAlu -> getOpcode ( ) == <STR_LIT> ) ; CfAlu -> setDesc ( get ( <STR_LIT> ) ) ; break ; } case <STR_LIT> : I -> eraseFromParent ( ) ; break ; } I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) { return <NUM_LIT> ; } -- I ; switch ( I -> getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : { MachineInstr * predSet = findFirstPredicateSetterFrom ( MBB , I ) ; clearFlag ( * predSet , <NUM_LIT> , MO_FLAG_PUSH ) ; I -> eraseFromParent ( ) ; MachineBasicBlock :: iterator CfAlu = FindLastAluClause ( MBB ) ; if ( CfAlu == MBB . end ( ) ) break ; assert ( CfAlu -> getOpcode ( ) == <STR_LIT> ) ; CfAlu -> setDesc ( get ( <STR_LIT> ) ) ; break ; } case <STR_LIT> : I -> eraseFromParent ( ) ; break ;


<s> for ( int Index = getIndirectIndexBegin ( MF ) ; Index <= End ; ++ Index ) { for ( unsigned Chan = <NUM_LIT> ; Chan < StackWidth ; ++ Chan ) { unsigned Reg = <STR_LIT> . getRegister ( ( <NUM_LIT> * Index ) + Chan ) ; TRI . reserveRegisterTuples ( Reserved , Reg ) ;


<s> case <ISA_LIT>InstrInfo :: ALU_VEC_021_SCL_122 : std :: swap ( Src [ <NUM_LIT> ] , Src [ <NUM_LIT> ] ) ; break ; case <ISA_LIT>InstrInfo :: ALU_VEC_102_SCL_221 : std :: swap ( Src [ <NUM_LIT> ] , Src [ <NUM_LIT> ] ) ; break ; case <ISA_LIT>InstrInfo :: ALU_VEC_120_SCL_212 : std :: swap ( Src [ <NUM_LIT> ] , Src [ <NUM_LIT> ] ) ; std :: swap ( Src [ <NUM_LIT> ] , Src [ <NUM_LIT> ] ) ; break ; case <ISA_LIT>InstrInfo :: ALU_VEC_201 : std :: swap ( Src [ <NUM_LIT> ] , Src [ <NUM_LIT> ] ) ;


<s> bool <ISA_LIT>InstrInfo :: usesAddressRegister ( MachineInstr & MI ) const {

return MI . findRegisterUseOperandIdx ( <STR_LIT> , false , & RI ) != - <NUM_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: usesAddressRegister ( MachineInstr & MI ) const { return MI . findRegisterUseOperandIdx ( <STR_LIT> , false , & RI ) != - <NUM_LIT> ;


<s> return ( <STR_LIT> ( MF -> getFunction ( ) . getCallingConv ( ) ) && usesVertexCache ( MI . getOpcode ( ) ) ) || usesTextureCache ( MI . getOpcode ( ) ) ;


<s> const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; return ! <STR_LIT> ( MF -> getFunction ( ) . getCallingConv ( ) ) && usesVertexCache ( MI . getOpcode ( ) ) ;


<s> MachineBasicBlock :: iterator PriorI = std :: prev ( I ) ; if ( AllowModify ) I -> removeFromParent ( ) ; I = PriorI ; } MachineInstr * LastInst = I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isJump ( static_cast < MachineInstr * > ( -- I ) -> getOpcode ( ) ) ) { if ( LastOpc == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( LastOpc == <STR_LIT> ) { MachineInstr * predSet = I ; while ( ! isPredicateSetter ( predSet -> getOpcode ( ) ) ) { predSet = -- I ; } TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( <STR_LIT> , false ) ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( SecondLastOpc == <STR_LIT> && LastOpc == <STR_LIT> ) { MachineInstr * predSet = -- I ; while ( ! isPredicateSetter ( predSet -> getOpcode ( ) ) ) { predSet = -- I ; } TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ;

FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ;


<s> if ( ! isJump ( static_cast < MachineInstr * > ( I ) -> getOpcode ( ) ) ) { return false ; } while ( I != MBB . begin ( ) && std :: prev ( I ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PriorI = std :: prev ( I ) ; if ( AllowModify ) I -> removeFromParent ( ) ; I = PriorI ; } MachineInstr * LastInst = I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isJump ( static_cast < MachineInstr * > ( -- I ) -> getOpcode ( ) ) ) { if ( LastOpc == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( LastOpc == <STR_LIT> ) { MachineInstr * predSet = I ; while ( ! isPredicateSetter ( predSet -> getOpcode ( ) ) ) { predSet = -- I ; } TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( <STR_LIT> , false ) ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( SecondLastOpc == <STR_LIT> && LastOpc == <STR_LIT> ) { MachineInstr * predSet = -- I ; while ( ! isPredicateSetter ( predSet -> getOpcode ( ) ) ) { predSet = -- I ; } TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( <STR_LIT> , false ) ) ; return false ;


<s> MachineInstrBuilder MIB = BuildMI ( MBB , I , MBB . findDebugLoc ( I ) , get ( Opcode ) , DstReg ) ; if ( Src1Reg ) { MIB . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } MIB . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( Src0Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( - <NUM_LIT> ) ;


<s> switch ( AddrChan ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : AddrReg = <STR_LIT> . getRegister ( Address ) ; break ; case <NUM_LIT> : AddrReg = <STR_LIT> . getRegister ( Address ) ; break ; case <NUM_LIT> : AddrReg = <STR_LIT> . getRegister ( Address ) ; break ; case <NUM_LIT> : AddrReg = <STR_LIT> . getRegister ( Address ) ; break ; } MachineInstr * MOVA = buildDefaultInstruction ( * MBB , I , <STR_LIT> , <STR_LIT> , OffsetReg ) ; setImmOperand ( MOVA , <STR_LIT> :: write , <NUM_LIT> ) ; MachineInstrBuilder Mov = buildDefaultInstruction ( * MBB , I , <STR_LIT> , ValueReg , AddrReg ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) ; setImmOperand ( Mov , <STR_LIT> :: src0_rel , <NUM_LIT> ) ; return Mov ;


<s> MachineInstr * MOVA = buildDefaultInstruction ( * MBB , I , <STR_LIT> , <STR_LIT> , OffsetReg ) ; setImmOperand ( MOVA , <STR_LIT> :: write , <NUM_LIT> ) ;

MachineInstrBuilder Mov = buildDefaultInstruction ( * MBB , I , <STR_LIT> , AddrReg , ValueReg ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) ;


<s> MachineInstrBuilder <ISA_LIT>InstrInfo :: buildIndirectWrite ( MachineBasicBlock * MBB , MachineBasicBlock :: iterator I , unsigned ValueReg , unsigned Address , unsigned OffsetReg , unsigned AddrChan ) const { unsigned AddrReg ; switch ( AddrChan ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : AddrReg = <STR_LIT> . getRegister ( Address ) ; break ; case <NUM_LIT> : AddrReg = <STR_LIT> . getRegister ( Address ) ; break ; case <NUM_LIT> : AddrReg = <STR_LIT> . getRegister ( Address ) ; break ;


<s> unsigned <ISA_LIT>InstrInfo :: calculateIndirectAddress ( unsigned RegIndex , unsigned Channel ) const { assert ( Channel == <NUM_LIT> ) ;


<s> assert ( Channel == <NUM_LIT> ) ; return RegIndex ;


<s> bool <ISA_LIT>InstrInfo :: canBeConsideredALU ( const MachineInstr * MI ) const { if ( isALUInstr ( MI -> getOpcode ( ) ) ) return true ; if ( isVector ( * MI ) || isCubeOp ( MI -> getOpcode ( ) ) ) return true ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> :


<s> } if ( VectorComponents > <NUM_LIT> ) { for ( unsigned I = <NUM_LIT> ; I < VectorComponents ; I ++ ) { unsigned SubRegIndex = RI . getSubRegFromChannel ( I ) ; buildDefaultInstruction ( MBB , MI , <STR_LIT> , RI . getSubReg ( DestReg , SubRegIndex ) , RI . getSubReg ( SrcReg , SubRegIndex ) ) . addReg ( DestReg , RegState :: Define | RegState :: Implicit ) ; } } else {

MachineInstr * NewMI = buildDefaultInstruction ( MBB , MI , <STR_LIT> , DestReg , SrcReg ) ;


<s> VectorComponents = <NUM_LIT> ; } else if ( ( <STR_LIT> . contains ( DestReg ) || <STR_LIT> . contains ( DestReg ) ) && ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ) { VectorComponents = <NUM_LIT> ; } if ( VectorComponents > <NUM_LIT> ) { for ( unsigned I = <NUM_LIT> ; I < VectorComponents ; I ++ ) { unsigned SubRegIndex = RI . getSubRegFromChannel ( I ) ; buildDefaultInstruction ( MBB , MI , <STR_LIT> , RI . getSubReg ( DestReg , SubRegIndex ) , RI . getSubReg ( SrcReg , SubRegIndex ) ) . addReg ( DestReg , RegState :: Define | RegState :: Implicit ) ; } } else { MachineInstr * NewMI = buildDefaultInstruction ( MBB , MI , <STR_LIT> , DestReg , SrcReg ) ; NewMI -> getOperand ( getOperandIdx ( * NewMI , <STR_LIT> :: src0 ) ) . setIsKill ( KillSrc ) ;


<s> const InstrItineraryData * II = STI . getInstrItineraryData ( ) ; return static_cast < const <ISA_LIT>Subtarget & > ( STI ) . createDFAPacketizer ( II ) ;


<s> return MI -> findRegisterDefOperandIdx ( <STR_LIT> ) != - <NUM_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: definesAddressRegister ( MachineInstr * MI ) const { return MI -> findRegisterDefOperandIdx ( <STR_LIT> ) != - <NUM_LIT> ;


<s> return isPredicateSetter ( MI -> getOpcode ( ) ) ;


<s> bool <ISA_LIT>InstrInfo :: DefinesPredicate ( MachineInstr * MI , std :: vector < MachineOperand > & Pred ) const { return isPredicateSetter ( MI -> getOpcode ( ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : buildIndirectRead ( MI -> getParent ( ) , MI , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , RI . getHWRegIndex ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , RI . getHWRegChan ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; break ; case <STR_LIT> : case <STR_LIT> : buildIndirectWrite ( MI -> getParent ( ) , MI , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , RI . getHWRegIndex ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , RI . getHWRegChan ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ;


<s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { switch ( MI -> getOpcode ( ) ) { default : return <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MI ) ; case <STR_LIT> : case <STR_LIT> : buildIndirectRead ( MI -> getParent ( ) , MI , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , RI . getHWRegIndex ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , RI . getHWRegChan ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; break ; case <STR_LIT> :


<s> static MachineInstr * findFirstPredicateSetterFrom ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) { while ( I != MBB . begin ( ) ) { -- I ;


<s> static MachineInstr * findFirstPredicateSetterFrom ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) { while ( I != MBB . begin ( ) ) { -- I ; MachineInstr * MI = I ; if ( isPredicateSetter ( MI -> getOpcode ( ) ) ) return MI ;


<s> for ( MachineBasicBlock :: reverse_iterator It = MBB . rbegin ( ) , E = MBB . rend ( ) ; It != E ; ++ It ) { if ( It -> getOpcode ( ) == <STR_LIT> || It -> getOpcode ( ) == <STR_LIT> ) return std :: prev ( It . base ( ) ) ;


if ( It -> getOpcode ( ) == <STR_LIT> || It -> getOpcode ( ) == <STR_LIT> ) return std :: prev ( It . base ( ) ) ;


<s> bool <ISA_LIT>InstrInfo :: FindSwizzleForVectorSlot ( const std :: vector < std :: vector < std :: pair < int , unsigned > > > & IGSrcs , std :: vector < <ISA_LIT>InstrInfo :: BankSwizzle > & SwzCandidate , const std :: vector < std :: pair < int , unsigned > > & TransSrcs , <ISA_LIT>InstrInfo :: BankSwizzle TransSwz ) const { unsigned ValidUpTo = <NUM_LIT> ; do { ValidUpTo = isLegalUpTo ( IGSrcs , SwzCandidate , TransSrcs , TransSwz ) ; if ( ValidUpTo == IGSrcs . size ( ) ) return true ; } while ( NextPossibleSolution ( SwzCandidate , ValidUpTo ) ) ;


<s> std :: pair < MachineOperand * , unsigned > Src = Srcs [ j ] ; if ( Src . first -> getReg ( ) == <STR_LIT> ) Literals . insert ( Src . second ) ; if ( Literals . size ( ) > <NUM_LIT> ) return false ; if ( Src . first -> getReg ( ) == <STR_LIT> ) Consts . push_back ( Src . second ) ; if ( <STR_LIT> . contains ( Src . first -> getReg ( ) ) || <STR_LIT> . contains ( Src . first -> getReg ( ) ) ) { unsigned Index = RI . getEncodingValue ( Src . first -> getReg ( ) ) & <NUM_LIT> ; unsigned Chan = RI . getHWRegChan ( Src . first -> getReg ( ) ) ; Consts . push_back ( ( Index << <NUM_LIT> ) | Chan ) ; } }


<s> ValidSwizzle . push_back ( ( <ISA_LIT>InstrInfo :: BankSwizzle ) IG [ i ] -> getOperand ( Op ) . getImm ( ) ) ; } std :: vector < std :: pair < int , unsigned > > TransOps ; if ( ! isLastAluTrans ) return FindSwizzleForVectorSlot ( IGSrcs , ValidSwizzle , TransOps , TransBS ) ; TransOps = std :: move ( IGSrcs . back ( ) ) ; IGSrcs . pop_back ( ) ; ValidSwizzle . pop_back ( ) ; static const <ISA_LIT>InstrInfo :: BankSwizzle TransSwz [ ] = { ALU_VEC_012_SCL_210 , ALU_VEC_021_SCL_122 , ALU_VEC_120_SCL_212 , ALU_VEC_102_SCL_221 } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { TransBS = TransSwz [ i ] ; if ( ! isConstCompatible ( TransBS , TransOps , ConstCount ) ) continue ; bool Result = FindSwizzleForVectorSlot ( IGSrcs , ValidSwizzle , TransOps , TransBS ) ; if ( Result ) { ValidSwizzle . push_back ( TransBS ) ; return true ;


<s> const TargetRegisterClass * <ISA_LIT>InstrInfo :: getIndirectAddrRegClass ( ) const {


<s> unsigned int <ISA_LIT>InstrInfo :: getInstrLatency ( const InstrItineraryData * ItinData , const MachineInstr * MI , unsigned * PredCost ) const { if ( PredCost ) * PredCost = <NUM_LIT> ; return <NUM_LIT> ;


<s> unsigned <ISA_LIT>InstrInfo :: getMaxAlusPerClause ( ) const { return <NUM_LIT> ;


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return RI ;


<s> int <ISA_LIT>InstrInfo :: getSrcIdx ( unsigned Opcode , unsigned SrcNum ) const { static const unsigned OpTable [ ] = { <STR_LIT> :: src0 , <STR_LIT> :: src1 , <STR_LIT> :: src2 } ; assert ( SrcNum < <NUM_LIT> ) ; return getOperandIdx ( Opcode , OpTable [ SrcNum ] ) ;


<s> case <ISA_LIT>InstrInfo :: ALU_VEC_120_SCL_212 : { unsigned Cycles [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return Cycles [ Op ] ; } case <ISA_LIT>InstrInfo :: ALU_VEC_102_SCL_221 : { unsigned Cycles [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return Cycles [ Op ] ; } default :


<s> static unsigned getTransSwizzle ( <ISA_LIT>InstrInfo :: BankSwizzle Swz , unsigned Op ) { switch ( Swz ) { case <ISA_LIT>InstrInfo :: ALU_VEC_012_SCL_210 : { unsigned Cycles [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return Cycles [ Op ] ; }

case <ISA_LIT>InstrInfo :: ALU_VEC_021_SCL_122 : {


<s> return ( ( TargetFlags & <STR_LIT> ) | ( TargetFlags & <STR_LIT> ) | ( TargetFlags & <STR_LIT> ) ) ;


<s> bool <ISA_LIT>InstrInfo :: hasInstrModifiers ( unsigned Opcode ) const {

unsigned TargetFlags = get ( Opcode ) . TSFlags ;


<s> assert ( PredSet && <STR_LIT> ) ; addFlag ( PredSet , <NUM_LIT> , MO_FLAG_PUSH ) ; PredSet -> getOperand ( <NUM_LIT> ) . setImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( <STR_LIT> , RegState :: Kill ) ; MachineBasicBlock :: iterator CfAlu = FindLastAluClause ( MBB ) ; if ( CfAlu == MBB . end ( ) ) return <NUM_LIT> ; assert ( CfAlu -> getOpcode ( ) == <STR_LIT> ) ; CfAlu -> setDesc ( get ( <STR_LIT> ) ) ; return <NUM_LIT> ; } } else {

MachineInstr * PredSet = findFirstPredicateSetterFrom ( MBB , MBB . end ( ) ) ;


<s> return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> for ( unsigned i = <NUM_LIT> , e = TransOps . size ( ) ; i < e ; ++ i ) { const std :: pair < int , unsigned > & Src = TransOps [ i ] ; unsigned Cycle = getTransSwizzle ( TransSwz , i ) ; if ( Src . first < <NUM_LIT> ) continue ;

if ( ConstCount > <NUM_LIT> && Cycle == <NUM_LIT> ) return false ;


<s> bool <ISA_LIT>InstrInfo :: isCubeOp ( unsigned Opcode ) const { switch ( Opcode ) { default : return false ; case <STR_LIT> :


<s> static bool isJump ( unsigned Opcode ) {

return Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> unsigned TargetFlags = get ( Opcode ) . TSFlags ; return ( ( TargetFlags & <STR_LIT> ) | ( TargetFlags & <STR_LIT> ) | ( TargetFlags & <STR_LIT> ) ) ;


<s> bool <ISA_LIT>InstrInfo :: isLDSNoRetInstr ( unsigned Opcode ) const { return isLD<ISA_LIT>nstr ( Opcode ) && getOperandIdx ( Opcode , <STR_LIT> :: dst ) == - <NUM_LIT> ;


<s> return isLD<ISA_LIT>nstr ( Opcode ) && getOperandIdx ( Opcode , <STR_LIT> :: dst ) != - <NUM_LIT> ;


<s> if ( I -> isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( I -> getReg ( ) ) && I -> isUse ( ) && RI . isPhysRegLiveAcrossClauses ( I -> getReg ( ) ) ) return false ;


<s> continue ; } if ( Vector [ Src . second ] [ j ] < <NUM_LIT> ) Vector [ Src . second ] [ j ] = Src . first ; if ( Vector [ Src . second ] [ j ] != Src . first ) return i ; } } for ( unsigned i = <NUM_LIT> , e = TransSrcs . size ( ) ; i < e ; ++ i ) { const std :: pair < int , unsigned > & Src = TransSrcs [ i ] ; unsigned Cycle = getTransSwizzle ( TransSwz , i ) ; if ( Src . first < <NUM_LIT> ) continue ; if ( Src . first == <NUM_LIT> ) continue ;

if ( Vector [ Src . second ] [ Cycle ] < <NUM_LIT> ) Vector [ Src . second ] [ Cycle ] = Src . first ;


<s> for ( unsigned i = <NUM_LIT> , e = TransSrcs . size ( ) ; i < e ; ++ i ) { const std :: pair < int , unsigned > & Src = TransSrcs [ i ] ; unsigned Cycle = getTransSwizzle ( TransSwz , i ) ; if ( Src . first < <NUM_LIT> ) continue ; if ( Src . first == <NUM_LIT> ) continue ; if ( Vector [ Src . second ] [ Cycle ] < <NUM_LIT> ) Vector [ Src . second ] [ Cycle ] = Src . first ; if ( Vector [ Src . second ] [ Cycle ] != Src . first ) return IGSrcs . size ( ) - <NUM_LIT> ; }


<s> bool <ISA_LIT>InstrInfo :: isMov ( unsigned Opcode ) const { switch ( Opcode ) {


<s> default : return false ; case <STR_LIT> : return true ; }


<s> return false ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( MI -> getParent ( ) -> begin ( ) != MachineBasicBlock :: iterator ( MI ) ) return false ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> || MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ;


<s> unsigned Reg = MI -> getOperand ( idx ) . getReg ( ) ; switch ( Reg ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; }


<s> bool <ISA_LIT>InstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumTCycles , unsigned ExtraTCycles , MachineBasicBlock & FMBB , unsigned NumFCycles , unsigned ExtraFCycles , BranchProbability Probability ) const { return true ;


<s> bool <ISA_LIT>InstrInfo :: isReductionOp ( unsigned Opcode ) const { return false ;


<s> return get ( MI . getOpcode ( ) ) . TSFlags & <STR_LIT> ;


<s> bool isRegisterStore ( const MachineInstr & MI ) const {

return get ( MI . getOpcode ( ) ) . TSFlags & <STR_LIT> ;


<s> return isTransOnly ( MI -> getOpcode ( ) ) ;


<s> bool <ISA_LIT>InstrInfo :: isTrig ( const MachineInstr & MI ) const {


<s> return isVectorOnly ( MI -> getOpcode ( ) ) ;


<s> bool <ISA_LIT>InstrInfo :: mustBeLastInClause ( unsigned Opcode ) const { switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> :


<s> switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return true ; default : return false ;


<s> for ( unsigned i = ResetIdx + <NUM_LIT> , e = SwzCandidate . size ( ) ; i < e ; i ++ ) { SwzCandidate [ i ] = <ISA_LIT>InstrInfo :: ALU_VEC_012_SCL_210 ; } if ( ResetIdx == - <NUM_LIT> ) return false ; int NextSwizzle = SwzCandidate [ ResetIdx ] + <NUM_LIT> ;

SwzCandidate [ ResetIdx ] = ( <ISA_LIT>InstrInfo :: BankSwizzle ) NextSwizzle ;


<s> MI -> getOperand ( getOperandIdx ( * MI , <STR_LIT> :: pred_sel_W ) ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; MachineInstrBuilder MIB ( * MI -> getParent ( ) -> getParent ( ) , MI ) ; MIB . addReg ( <STR_LIT> , RegState :: Implicit ) ; return true ; } if ( PIdx != - <NUM_LIT> ) { MachineOperand & PMO = MI -> getOperand ( PIdx ) ; PMO . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ;


<s> return true ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { MI -> getOperand ( getOperandIdx ( * MI , <STR_LIT> :: pred_sel_X ) ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; MI -> getOperand ( getOperandIdx ( * MI , <STR_LIT> :: pred_sel_Y ) ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; MI -> getOperand ( getOperandIdx ( * MI , <STR_LIT> :: pred_sel_Z ) ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; MI -> getOperand ( getOperandIdx ( * MI , <STR_LIT> :: pred_sel_W ) ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; MachineInstrBuilder MIB ( * MI -> getParent ( ) -> getParent ( ) , MI ) ; MIB . addReg ( <STR_LIT> , RegState :: Implicit ) ; return true ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & st ) : <ISA_LIT>InstrInfo ( st ) , RI ( ) {


<s> if ( ! I -> isReg ( ) || ! I -> isUse ( ) || TargetRegisterInfo :: isVirtualRegister ( I -> getReg ( ) ) ) continue ; if ( <STR_LIT> . contains ( I -> getReg ( ) ) ) return true ;


<s> bool <ISA_LIT>InstrInfo :: readsLDSSrcReg ( const MachineInstr * MI ) const { if ( ! isALUInstr ( MI -> getOpcode ( ) ) ) { return false ; }

for ( MachineInstr :: const_mop_iterator I = MI -> operands_begin ( ) , E = MI -> operands_end ( ) ; I != E ; ++ I ) {


<s> clearFlag ( predSet , <NUM_LIT> , MO_FLAG_PUSH ) ; I -> eraseFromParent ( ) ; MachineBasicBlock :: iterator CfAlu = FindLastAluClause ( MBB ) ; if ( CfAlu == MBB . end ( ) ) break ; assert ( CfAlu -> getOpcode ( ) == <STR_LIT> ) ; CfAlu -> setDesc ( get ( <STR_LIT> ) ) ; break ; } case <STR_LIT> : I -> eraseFromParent ( ) ; break ; } I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) { return <NUM_LIT> ; } -- I ; switch ( I -> getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : { MachineInstr * predSet = findFirstPredicateSetterFrom ( MBB , I ) ; clearFlag ( predSet , <NUM_LIT> , MO_FLAG_PUSH ) ; I -> eraseFromParent ( ) ; MachineBasicBlock :: iterator CfAlu = FindLastAluClause ( MBB ) ; if ( CfAlu == MBB . end ( ) ) break ; assert ( CfAlu -> getOpcode ( ) == <STR_LIT> ) ; CfAlu -> setDesc ( get ( <STR_LIT> ) ) ; break ;


<s> unsigned StackWidth = TFL -> getStackWidth ( MF ) ; int End = getIndirectIndexEnd ( MF ) ; if ( End == - <NUM_LIT> ) return ; for ( int Index = getIndirectIndexBegin ( MF ) ; Index <= End ; ++ Index ) { unsigned SuperReg = <STR_LIT> . getRegister ( Index ) ; Reserved . set ( SuperReg ) ; for ( unsigned Chan = <NUM_LIT> ; Chan < StackWidth ; ++ Chan ) { unsigned Reg = <STR_LIT> . getRegister ( ( <NUM_LIT> * Index ) + Chan ) ;


<s> int End = getIndirectIndexEnd ( MF ) ; if ( End == - <NUM_LIT> ) return ; for ( int Index = getIndirectIndexBegin ( MF ) ; Index <= End ; ++ Index ) { unsigned SuperReg = <STR_LIT> . getRegister ( Index ) ; Reserved . set ( SuperReg ) ; for ( unsigned Chan = <NUM_LIT> ; Chan < StackWidth ; ++ Chan ) { unsigned Reg = <STR_LIT> . getRegister ( ( <NUM_LIT> * Index ) + Chan ) ;


<s> MO . setImm ( OPCODE_IS_NOT_ZERO_INT ) ; break ; case OPCODE_IS_NOT_ZERO_INT : MO . setImm ( OPCODE_IS_ZERO_INT ) ; break ; case OPCODE_IS_ZERO : MO . setImm ( OPCODE_IS_NOT_ZERO ) ; break ; case OPCODE_IS_NOT_ZERO : MO . setImm ( OPCODE_IS_ZERO ) ; break ; default : return true ; } MachineOperand & MO2 = Cond [ <NUM_LIT> ] ; switch ( MO2 . getReg ( ) ) { case <STR_LIT> : MO2 . setReg ( <STR_LIT> ) ; break ; case <STR_LIT> : MO2 . setReg ( <STR_LIT> ) ; break ; default :


<s> bool <ISA_LIT>InstrInfo :: SubsumesPredicate ( ArrayRef < MachineOperand > Pred1 , ArrayRef < MachineOperand > Pred2 ) const {


<s> bool <ISA_LIT>InstrInfo :: SubsumesPredicate ( ArrayRef < MachineOperand > Pred1 , ArrayRef < MachineOperand > Pred2 ) const { return false ;


<s> static std :: vector < std :: pair < int , unsigned > > Swizzle ( std :: vector < std :: pair < int , unsigned > > Src , <ISA_LIT>InstrInfo :: BankSwizzle Swz ) { if ( Src [ <NUM_LIT> ] == Src [ <NUM_LIT> ] ) Src [ <NUM_LIT> ] . first = - <NUM_LIT> ; switch ( Swz ) { case <ISA_LIT>InstrInfo :: ALU_VEC_012_SCL_210 : break ; case <ISA_LIT>InstrInfo :: ALU_VEC_021_SCL_122 : std :: swap ( Src [ <NUM_LIT> ] , Src [ <NUM_LIT> ] ) ; break ; case <ISA_LIT>InstrInfo :: ALU_VEC_102_SCL_221 : std :: swap ( Src [ <NUM_LIT> ] , Src [ <NUM_LIT> ] ) ; break ; case <ISA_LIT>InstrInfo :: ALU_VEC_120_SCL_212 : std :: swap ( Src [ <NUM_LIT> ] , Src [ <NUM_LIT> ] ) ; std :: swap ( Src [ <NUM_LIT> ] , Src [ <NUM_LIT> ] ) ; break ; case <ISA_LIT>InstrInfo :: ALU_VEC_201 : std :: swap ( Src [ <NUM_LIT> ] , Src [ <NUM_LIT> ] ) ; std :: swap ( Src [ <NUM_LIT> ] , Src [ <NUM_LIT> ] ) ; break ; case <ISA_LIT>InstrInfo :: ALU_VEC_210 : std :: swap ( Src [ <NUM_LIT> ] , Src [ <NUM_LIT> ] ) ; break ;


<s> bool <ISA_LIT>InstrInfo :: usesAddressRegister ( MachineInstr * MI ) const {

return MI -> findRegisterUseOperandIdx ( <STR_LIT> ) != - <NUM_LIT> ;


<s> return ( MFI -> getShaderType ( ) == ShaderType :: COMPUTE && usesVertexCache ( MI -> getOpcode ( ) ) ) || usesTextureCache ( MI -> getOpcode ( ) ) ;


<s> bool <ISA_LIT>InstrInfo :: usesVertexCache ( const MachineInstr * MI ) const { const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ;

const <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;


<s> const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;

return MFI -> getShaderType ( ) != ShaderType :: COMPUTE && usesVertexCache ( MI -> getOpcode ( ) ) ;


<s> if ( I == MBB . end ( ) ) return false ; if ( isBranch ( I -> getOpcode ( ) ) ) return true ; if ( ! isJump ( static_cast < MachineInstr * > ( I ) -> getOpcode ( ) ) ) { return false ; } while ( I != MBB . begin ( ) && std :: prev ( I ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PriorI = std :: prev ( I ) ; if ( AllowModify ) I -> removeFromParent ( ) ; I = PriorI ; } MachineInstr & LastInst = * I ; unsigned LastOpc = LastInst . getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isJump ( static_cast < MachineInstr * > ( -- I ) -> getOpcode ( ) ) ) { if ( LastOpc == <STR_LIT> ) { TBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( LastOpc == <STR_LIT> ) { auto predSet = I ; while ( ! isPredicateSetter ( predSet -> getOpcode ( ) ) ) { predSet = -- I ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : AddrReg = <STR_LIT> . getRegister ( Address ) ; break ; case <NUM_LIT> : AddrReg = <STR_LIT> . getRegister ( Address ) ; break ; case <NUM_LIT> : AddrReg = <STR_LIT> . getRegister ( Address ) ; break ; case <NUM_LIT> : AddrReg = <STR_LIT> . getRegister ( Address ) ; break ; } MachineInstr * MOVA = buildDefaultInstruction ( * MBB , I , <STR_LIT> , <STR_LIT> , OffsetReg ) ; setImmOperand ( * MOVA , <STR_LIT> :: write , <NUM_LIT> ) ; MachineInstrBuilder Mov = buildDefaultInstruction ( * MBB , I , <STR_LIT> , ValueReg , AddrReg ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) ; setImmOperand ( * Mov , <STR_LIT> :: src0_rel , <NUM_LIT> ) ;


<s> case <NUM_LIT> : AddrReg = <STR_LIT> . getRegister ( Address ) ; break ; } MachineInstr * MOVA = buildDefaultInstruction ( * MBB , I , <STR_LIT> , <STR_LIT> , OffsetReg ) ; setImmOperand ( * MOVA , <STR_LIT> :: write , <NUM_LIT> ) ;

MachineInstrBuilder Mov = buildDefaultInstruction ( * MBB , I , <STR_LIT> , AddrReg , ValueReg ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) ;


<s> } MachineInstr * MOVA = buildDefaultInstruction ( * MBB , I , <STR_LIT> , <STR_LIT> , OffsetReg ) ; setImmOperand ( * MOVA , <STR_LIT> :: write , <NUM_LIT> ) ; MachineInstrBuilder Mov = buildDefaultInstruction ( * MBB , I , <STR_LIT> , AddrReg , ValueReg ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) ;

setImmOperand ( * Mov , <STR_LIT> :: dst_rel , <NUM_LIT> ) ;


<s> if ( isALUInstr ( MI . getOpcode ( ) ) ) return true ; if ( isVector ( MI ) || isCubeOp ( MI . getOpcode ( ) ) ) return true ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return false ; }


<s> VectorComponents = <NUM_LIT> ; } else if ( ( <STR_LIT> . contains ( DestReg ) || <STR_LIT> . contains ( DestReg ) ) && ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ) { VectorComponents = <NUM_LIT> ; } if ( VectorComponents > <NUM_LIT> ) { for ( unsigned I = <NUM_LIT> ; I < VectorComponents ; I ++ ) { unsigned SubRegIndex = RI . getSubRegFromChannel ( I ) ; buildDefaultInstruction ( MBB , MI , <STR_LIT> , RI . getSubReg ( DestReg , SubRegIndex ) , RI . getSubReg ( SrcReg , SubRegIndex ) ) . addReg ( DestReg , RegState :: Define | RegState :: Implicit ) ; }


<s> buildMovInstr ( MBB , MI , getIndirectAddrRegClass ( ) -> getRegister ( Address ) , MI . getOperand ( ValOpIdx ) . getReg ( ) ) ; } else { buildIndirectWrite ( MBB , MI , MI . getOperand ( ValOpIdx ) . getReg ( ) , calculateIndirectAddress ( RegIndex , Channel ) , OffsetReg ) ; } } else { return false ; } MBB -> erase ( MI ) ; return true ; } case <STR_LIT> : case <STR_LIT> : buildIndirectRead ( MI . getParent ( ) , MI , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , RI . getHWRegIndex ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , RI . getHWRegChan ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; break ; case <STR_LIT> : case <STR_LIT> :

buildIndirectWrite ( MI . getParent ( ) , MI , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , RI . getHWRegIndex ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , RI . getHWRegChan ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ;


<s> } else { buildIndirectRead ( MBB , MI , MI . getOperand ( DstOpIdx ) . getReg ( ) , Address , OffsetReg ) ; } } else if ( isRegisterStore ( MI ) ) { int ValOpIdx = <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> :: val ) ; unsigned RegIndex = MI . getOperand ( RegOpIdx ) . getImm ( ) ; unsigned Channel = MI . getOperand ( ChanOpIdx ) . getImm ( ) ; unsigned Address = calculateIndirectAddress ( RegIndex , Channel ) ; unsigned OffsetReg = MI . getOperand ( OffsetOpIdx ) . getReg ( ) ; if ( OffsetReg == <STR_LIT> ) { buildMovInstr ( MBB , MI , getIndirectAddrRegClass ( ) -> getRegister ( Address ) , MI . getOperand ( ValOpIdx ) . getReg ( ) ) ; } else { buildIndirectWrite ( MBB , MI , MI . getOperand ( ValOpIdx ) . getReg ( ) , calculateIndirectAddress ( RegIndex , Channel ) , OffsetReg ) ; } } else { return false ; } MBB -> erase ( MI ) ; return true ; } case <STR_LIT> : case <STR_LIT> : buildIndirectRead ( MI . getParent ( ) , MI , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , RI . getHWRegIndex ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , RI . getHWRegChan ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; break ; case <STR_LIT> : case <STR_LIT> : buildIndirectWrite ( MI . getParent ( ) , MI , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , RI . getHWRegIndex ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , RI . getHWRegChan ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ;


<s> if ( Literals . size ( ) > <NUM_LIT> ) return false ; if ( Src . first -> getReg ( ) == <STR_LIT> ) Consts . push_back ( Src . second ) ; if ( <STR_LIT> . contains ( Src . first -> getReg ( ) ) || <STR_LIT> . contains ( Src . first -> getReg ( ) ) ) { unsigned Index = RI . getEncodingValue ( Src . first -> getReg ( ) ) & <NUM_LIT> ; unsigned Chan = RI . getHWRegChan ( Src . first -> getReg ( ) ) ; Consts . push_back ( ( Index << <NUM_LIT> ) | Chan ) ; } }


<s> MachineInstr & MI = * MIs [ i ] ; if ( ! isALUInstr ( MI . getOpcode ( ) ) ) continue ; ArrayRef < std :: pair < MachineOperand * , int64_t >> Srcs = getSrcs ( MI ) ; for ( const auto & Src : Srcs ) { if ( Src . first -> getReg ( ) == <STR_LIT> ) Literals . insert ( Src . second ) ; if ( Literals . size ( ) > <NUM_LIT> ) return false ; if ( Src . first -> getReg ( ) == <STR_LIT> ) Consts . push_back ( Src . second ) ; if ( <STR_LIT> . contains ( Src . first -> getReg ( ) ) || <STR_LIT> . contains ( Src . first -> getReg ( ) ) ) { unsigned Index = RI . getEncodingValue ( Src . first -> getReg ( ) ) & <NUM_LIT> ; unsigned Chan = RI . getHWRegChan ( Src . first -> getReg ( ) ) ; Consts . push_back ( ( Index << <NUM_LIT> ) | Chan ) ; } } }

return fitsConstReadLimitations ( Consts ) ;


<s> ValidSwizzle . clear ( ) ; unsigned ConstCount ; BankSwizzle TransBS = ALU_VEC_012_SCL_210 ; for ( unsigned i = <NUM_LIT> , e = IG . size ( ) ; i < e ; ++ i ) { IGSrcs . push_back ( ExtractSrcs ( * IG [ i ] , PV , ConstCount ) ) ; unsigned Op = getOperandIdx ( IG [ i ] -> getOpcode ( ) , <STR_LIT> :: bank_swizzle ) ; ValidSwizzle . push_back ( ( <ISA_LIT>InstrInfo :: BankSwizzle ) IG [ i ] -> getOperand ( Op ) . getImm ( ) ) ; } std :: vector < std :: pair < int , unsigned > > TransOps ; if ( ! isLastAluTrans ) return FindSwizzleForVectorSlot ( IGSrcs , ValidSwizzle , TransOps , TransBS ) ; TransOps = std :: move ( IGSrcs . back ( ) ) ; IGSrcs . pop_back ( ) ;


<s> if ( MFI -> getNumObjects ( ) == <NUM_LIT> ) { return - <NUM_LIT> ; } const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFL = ST . getFrameLowering ( ) ; unsigned IgnoredFrameReg ; Offset = TFL -> getFrameIndexReference ( MF , - <NUM_LIT> , IgnoredFrameReg ) ; return getIndirectIndexBegin ( MF ) + Offset ;


<s> { <STR_LIT> :: src0_X , <STR_LIT> :: src0_sel_X } , { <STR_LIT> :: src0_Y , <STR_LIT> :: src0_sel_Y } , { <STR_LIT> :: src0_Z , <STR_LIT> :: src0_sel_Z } , { <STR_LIT> :: src0_W , <STR_LIT> :: src0_sel_W } , { <STR_LIT> :: src1_X , <STR_LIT> :: src1_sel_X } , { <STR_LIT> :: src1_Y , <STR_LIT> :: src1_sel_Y } , { <STR_LIT> :: src1_Z , <STR_LIT> :: src1_sel_Z } , { <STR_LIT> :: src1_W , <STR_LIT> :: src1_sel_W } , } ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) { MachineOperand & MO = MI . getOperand ( getOperandIdx ( MI . getOpcode ( ) , OpTable [ j ] [ <NUM_LIT> ] ) ) ; unsigned Reg = MO . getReg ( ) ; if ( Reg == <STR_LIT> ) { MachineOperand & Sel = MI . getOperand ( getOperandIdx ( MI . getOpcode ( ) , OpTable [ j ] [ <NUM_LIT> ] ) ) ; Result . push_back ( std :: make_pair ( & MO , Sel . getImm ( ) ) ) ; continue ; }


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) { static const unsigned OpTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> :: src0_X , <STR_LIT> :: src0_sel_X } , { <STR_LIT> :: src0_Y , <STR_LIT> :: src0_sel_Y } , { <STR_LIT> :: src0_Z , <STR_LIT> :: src0_sel_Z } , { <STR_LIT> :: src0_W , <STR_LIT> :: src0_sel_W } , { <STR_LIT> :: src1_X , <STR_LIT> :: src1_sel_X } , { <STR_LIT> :: src1_Y , <STR_LIT> :: src1_sel_Y } , { <STR_LIT> :: src1_Z , <STR_LIT> :: src1_sel_Z } , { <STR_LIT> :: src1_W , <STR_LIT> :: src1_sel_W } , } ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) { MachineOperand & MO = MI . getOperand ( getOperandIdx ( MI . getOpcode ( ) , OpTable [ j ] [ <NUM_LIT> ] ) ) ; unsigned Reg = MO . getReg ( ) ; if ( Reg == <STR_LIT> ) { MachineOperand & Sel = MI . getOperand ( getOperandIdx ( MI . getOpcode ( ) , OpTable [ j ] [ <NUM_LIT> ] ) ) ; Result . push_back ( std :: make_pair ( & MO , Sel . getImm ( ) ) ) ; continue ; } } return Result ; } static const unsigned OpTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> :: src0 , <STR_LIT> :: src0_sel } , { <STR_LIT> :: src1 , <STR_LIT> :: src1_sel } , { <STR_LIT> :: src2 , <STR_LIT> :: src2_sel } , } ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) { int SrcIdx = getOperandIdx ( MI . getOpcode ( ) , OpTable [ j ] [ <NUM_LIT> ] ) ; if ( SrcIdx < <NUM_LIT> ) break ; MachineOperand & MO = MI . getOperand ( SrcIdx ) ; unsigned Reg = MO . getReg ( ) ;


<s> MachineBasicBlock :: iterator CfAlu = FindLastAluClause ( MBB ) ; if ( CfAlu == MBB . end ( ) ) return <NUM_LIT> ; assert ( CfAlu -> getOpcode ( ) == <STR_LIT> ) ; CfAlu -> setDesc ( get ( <STR_LIT> ) ) ; return <NUM_LIT> ; } } else { MachineInstr * PredSet = findFirstPredicateSetterFrom ( MBB , MBB . end ( ) ) ; assert ( PredSet && <STR_LIT> ) ; addFlag ( * PredSet , <NUM_LIT> , MO_FLAG_PUSH ) ; PredSet -> getOperand ( <NUM_LIT> ) . setImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( <STR_LIT> , RegState :: Kill ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; MachineBasicBlock :: iterator CfAlu = FindLastAluClause ( MBB ) ; if ( CfAlu == MBB . end ( ) ) return <NUM_LIT> ; assert ( CfAlu -> getOpcode ( ) == <STR_LIT> ) ; CfAlu -> setDesc ( get ( <STR_LIT> ) ) ; return <NUM_LIT> ; }


<s> MachineInstr * PredSet = findFirstPredicateSetterFrom ( MBB , MBB . end ( ) ) ; assert ( PredSet && <STR_LIT> ) ; addFlag ( * PredSet , <NUM_LIT> , MO_FLAG_PUSH ) ; PredSet -> getOperand ( <NUM_LIT> ) . setImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( <STR_LIT> , RegState :: Kill ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; MachineBasicBlock :: iterator CfAlu = FindLastAluClause ( MBB ) ;

if ( CfAlu == MBB . end ( ) ) return <NUM_LIT> ;


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; }


<s> bool <ISA_LIT>InstrInfo :: isPredicable ( MachineInstr & MI ) const { if ( MI . getOpcode ( ) == <STR_LIT> ) { return false ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { if ( MI . getParent ( ) -> begin ( ) != MachineBasicBlock :: iterator ( MI ) ) return false ; return MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ;


<s> if ( idx < <NUM_LIT> ) return false ;

unsigned Reg = MI . getOperand ( idx ) . getReg ( ) ;


<s> bool <ISA_LIT>InstrInfo :: isPredicated ( const MachineInstr & MI ) const { int idx = MI . findFirstPredOperandIdx ( ) ; if ( idx < <NUM_LIT> ) return false ; unsigned Reg = MI . getOperand ( idx ) . getReg ( ) ; switch ( Reg ) { default : return false ; case <STR_LIT> : case <STR_LIT> :


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) { MI . getOperand ( <NUM_LIT> ) . setImm ( <NUM_LIT> ) ; return true ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { MI . getOperand ( getOperandIdx ( MI , <STR_LIT> :: pred_sel_X ) ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; MI . getOperand ( getOperandIdx ( MI , <STR_LIT> :: pred_sel_Y ) ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; MI . getOperand ( getOperandIdx ( MI , <STR_LIT> :: pred_sel_Z ) ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; MI . getOperand ( getOperandIdx ( MI , <STR_LIT> :: pred_sel_W ) ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; MachineInstrBuilder MIB ( * MI . getParent ( ) -> getParent ( ) , MI ) ; MIB . addReg ( <STR_LIT> , RegState :: Implicit ) ; return true ; } if ( PIdx != - <NUM_LIT> ) { MachineOperand & PMO = MI . getOperand ( PIdx ) ; PMO . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; MachineInstrBuilder MIB ( * MI . getParent ( ) -> getParent ( ) , MI ) ; MIB . addReg ( <STR_LIT> , RegState :: Implicit ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & ST ) : <ISA_LIT>InstrInfo ( ST ) , RI ( ) , ST ( ST ) {


<s> bool <ISA_LIT>InstrInfo :: readsLDSSrcReg ( const MachineInstr & MI ) const { if ( ! isALUInstr ( MI . getOpcode ( ) ) ) { return false ; } for ( MachineInstr :: const_mop_iterator I = MI . operands_begin ( ) , E = MI . operands_end ( ) ; I != E ; ++ I ) { if ( ! I -> isReg ( ) || ! I -> isUse ( ) || TargetRegisterInfo :: isVirtualRegister ( I -> getReg ( ) ) ) continue ; if ( <STR_LIT> . contains ( I -> getReg ( ) ) ) return true ; } return false ;


<s> if ( ! isALUInstr ( MI . getOpcode ( ) ) ) { return false ; } for ( MachineInstr :: const_mop_iterator I = MI . operands_begin ( ) , E = MI . operands_end ( ) ; I != E ; ++ I ) { if ( ! I -> isReg ( ) || ! I -> isUse ( ) || TargetRegisterInfo :: isVirtualRegister ( I -> getReg ( ) ) ) continue ; if ( <STR_LIT> . contains ( I -> getReg ( ) ) ) return true ; } return false ;


<s> } case <STR_LIT> : I -> eraseFromParent ( ) ; break ; } I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) { return <NUM_LIT> ; } -- I ; switch ( I -> getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : { MachineInstr * predSet = findFirstPredicateSetterFrom ( MBB , I ) ; clearFlag ( * predSet , <NUM_LIT> , MO_FLAG_PUSH ) ; I -> eraseFromParent ( ) ; MachineBasicBlock :: iterator CfAlu = FindLastAluClause ( MBB ) ; if ( CfAlu == MBB . end ( ) ) break ; assert ( CfAlu -> getOpcode ( ) == <STR_LIT> ) ; CfAlu -> setDesc ( get ( <STR_LIT> ) ) ; break ; } case <STR_LIT> : I -> eraseFromParent ( ) ; break ; } return <NUM_LIT> ;


<s> void <ISA_LIT>InstrInfo :: reserveIndirectRegisters ( BitVector & Reserved , const MachineFunction & MF ) const { const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFL = ST . getFrameLowering ( ) ; unsigned StackWidth = TFL -> getStackWidth ( MF ) ; int End = getIndirectIndexEnd ( MF ) ; if ( End == - <NUM_LIT> ) return ; for ( int Index = getIndirectIndexBegin ( MF ) ; Index <= End ; ++ Index ) { unsigned SuperReg = <STR_LIT> . getRegister ( Index ) ; Reserved . set ( SuperReg ) ; for ( unsigned Chan = <NUM_LIT> ; Chan < StackWidth ; ++ Chan ) { unsigned Reg = <STR_LIT> . getRegister ( ( <NUM_LIT> * Index ) + Chan ) ; Reserved . set ( Reg ) ; }


<s> return MI . findRegisterUseOperandIdx ( <STR_LIT> ) != - <NUM_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: usesAddressRegister ( MachineInstr & MI ) const {

return MI . findRegisterUseOperandIdx ( <STR_LIT> ) != - <NUM_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: usesTextureCache ( const MachineInstr & MI ) const { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ;

return ( <STR_LIT> ( MF -> getFunction ( ) -> getCallingConv ( ) ) && usesVertexCache ( MI . getOpcode ( ) ) ) || usesTextureCache ( MI . getOpcode ( ) ) ;


<s> const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; return ( <STR_LIT> ( MF -> getFunction ( ) -> getCallingConv ( ) ) && usesVertexCache ( MI . getOpcode ( ) ) ) || usesTextureCache ( MI . getOpcode ( ) ) ;


<s> return ! <STR_LIT> ( MF -> getFunction ( ) -> getCallingConv ( ) ) && usesVertexCache ( MI . getOpcode ( ) ) ;


<s> if ( VectorComponents > <NUM_LIT> ) { for ( unsigned I = <NUM_LIT> ; I < VectorComponents ; I ++ ) { unsigned SubRegIndex = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( I ) ; buildDefaultInstruction ( MBB , MI , <STR_LIT> , RI . getSubReg ( DestReg , SubRegIndex ) , RI . getSubReg ( SrcReg , SubRegIndex ) ) . addReg ( DestReg , RegState :: Define | RegState :: Implicit ) ; } } else { MachineInstr * NewMI = buildDefaultInstruction ( MBB , MI , <STR_LIT> , DestReg , SrcReg ) ;

NewMI -> getOperand ( getOperandIdx ( * NewMI , <STR_LIT> :: src0 ) ) . setIsKill ( KillSrc ) ;


<s> std :: vector < std :: pair < int , unsigned >> <ISA_LIT>InstrInfo :: ExtractSrcs ( MachineInstr & MI , const DenseMap < unsigned , unsigned > & PV , unsigned & ConstCount ) const { ConstCount = <NUM_LIT> ; const std :: pair < int , unsigned > DummyPair ( - <NUM_LIT> , <NUM_LIT> ) ; std :: vector < std :: pair < int , unsigned >> Result ; unsigned i = <NUM_LIT> ; for ( const auto & Src : getSrcs ( MI ) ) { ++ i ; Register Reg = Src . first -> getReg ( ) ; int Index = RI . getEncodingValue ( Reg ) & <NUM_LIT> ; if ( Reg == <STR_LIT> ) { Result . push_back ( std :: make_pair ( Index , <NUM_LIT> ) ) ; } if ( PV . find ( Reg ) != PV . end ( ) ) { Result . push_back ( std :: make_pair ( <NUM_LIT> , <NUM_LIT> ) ) ; continue ; } if ( Index > <NUM_LIT> ) { ConstCount ++ ; Result . push_back ( DummyPair ) ; continue ;


<s> BankSwizzle TransBS = ALU_VEC_012_SCL_210 ; for ( unsigned i = <NUM_LIT> , e = IG . size ( ) ; i < e ; ++ i ) { IGSrcs . push_back ( ExtractSrcs ( * IG [ i ] , PV , ConstCount ) ) ; unsigned Op = getOperandIdx ( IG [ i ] -> getOpcode ( ) , <STR_LIT> :: bank_swizzle ) ; ValidSwizzle . push_back ( ( <ISA_LIT>InstrInfo :: BankSwizzle ) IG [ i ] -> getOperand ( Op ) . getImm ( ) ) ; } std :: vector < std :: pair < int , unsigned >> TransOps ; if ( ! isLastAluTrans ) return FindSwizzleForVectorSlot ( IGSrcs , ValidSwizzle , TransOps , TransBS ) ; TransOps = std :: move ( IGSrcs . back ( ) ) ; IGSrcs . pop_back ( ) ; ValidSwizzle . pop_back ( ) ; static const <ISA_LIT>InstrInfo :: BankSwizzle TransSwz [ ] = { ALU_VEC_012_SCL_210 , ALU_VEC_021_SCL_122 , ALU_VEC_120_SCL_212 , ALU_VEC_102_SCL_221 } ;

for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) {


<s> IGSrcs . pop_back ( ) ; ValidSwizzle . pop_back ( ) ; static const <ISA_LIT>InstrInfo :: BankSwizzle TransSwz [ ] = { ALU_VEC_012_SCL_210 , ALU_VEC_021_SCL_122 , ALU_VEC_120_SCL_212 , ALU_VEC_102_SCL_221 } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { TransBS = TransSwz [ i ] ; if ( ! isConstCompatible ( TransBS , TransOps , ConstCount ) ) continue ; bool Result = FindSwizzleForVectorSlot ( IGSrcs , ValidSwizzle , TransOps , TransBS ) ; if ( Result ) { ValidSwizzle . push_back ( TransBS ) ; return true ;


<s> if ( Register :: isVirtualRegister ( Reg ) || ! IndirectRC -> contains ( Reg ) ) continue ; unsigned RegIndex ; unsigned RegEnd ; for ( RegIndex = <NUM_LIT> , RegEnd = IndirectRC -> getNumRegs ( ) ; RegIndex != RegEnd ; ++ RegIndex ) { if ( IndirectRC -> getRegister ( RegIndex ) == Reg ) break ; }

Offset = std :: max ( Offset , ( int ) RegIndex ) ;


<s> int <ISA_LIT>InstrInfo :: getIndirectIndexBegin ( const MachineFunction & MF ) const { const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int Offset = - <NUM_LIT> ; if ( MFI . getNumObjects ( ) == <NUM_LIT> ) { return - <NUM_LIT> ; } if ( MRI . livein_empty ( ) ) { return <NUM_LIT> ; } const TargetRegisterClass * IndirectRC = getIndirectAddrRegClass ( ) ; for ( std :: pair < unsigned , unsigned > LI : MRI . liveins ( ) ) { unsigned Reg = LI . first ; if ( Register :: isVirtualRegister ( Reg ) || ! IndirectRC -> contains ( Reg ) ) continue ; unsigned RegIndex ; unsigned RegEnd ; for ( RegIndex = <NUM_LIT> , RegEnd = IndirectRC -> getNumRegs ( ) ; RegIndex != RegEnd ; ++ RegIndex ) { if ( IndirectRC -> getRegister ( RegIndex ) == Reg ) break ; } Offset = std :: max ( Offset , ( int ) RegIndex ) ; }


<s> Result . push_back ( std :: make_pair ( & MO , Sel . getImm ( ) ) ) ; continue ; } } return Result ; } static const unsigned OpTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> :: src0 , <STR_LIT> :: src0_sel } , { <STR_LIT> :: src1 , <STR_LIT> :: src1_sel } , { <STR_LIT> :: src2 , <STR_LIT> :: src2_sel } , } ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) { int SrcIdx = getOperandIdx ( MI . getOpcode ( ) , OpTable [ j ] [ <NUM_LIT> ] ) ; if ( SrcIdx < <NUM_LIT> ) break ; MachineOperand & MO = MI . getOperand ( SrcIdx ) ; Register Reg = MO . getReg ( ) ; if ( Reg == <STR_LIT> ) { MachineOperand & Sel = MI . getOperand ( getOperandIdx ( MI . getOpcode ( ) , OpTable [ j ] [ <NUM_LIT> ] ) ) ; Result . push_back ( std :: make_pair ( & MO , Sel . getImm ( ) ) ) ;


<s> } case <ISA_LIT>InstrInfo :: ALU_VEC_021_SCL_122 : { unsigned Cycles [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return Cycles [ Op ] ; } case <ISA_LIT>InstrInfo :: ALU_VEC_120_SCL_212 : { unsigned Cycles [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return Cycles [ Op ] ; }

case <ISA_LIT>InstrInfo :: ALU_VEC_102_SCL_221 : {


<s> bool <ISA_LIT>InstrInfo :: isLegalToSplitMBBAt ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) const { for ( MachineInstr :: const_mop_iterator I = MBBI -> operands_begin ( ) , E = MBBI -> operands_end ( ) ; I != E ; ++ I ) { if ( I -> isReg ( ) && ! Register :: isVirtualRegister ( I -> getReg ( ) ) && I -> isUse ( ) && RI . isPhysRegLiveAcrossClauses ( I -> getReg ( ) ) ) return false ;


<s> if ( ! isALUInstr ( MI . getOpcode ( ) ) ) { return false ; } for ( MachineInstr :: const_mop_iterator I = MI . operands_begin ( ) , E = MI . operands_end ( ) ; I != E ; ++ I ) { if ( ! I -> isReg ( ) || ! I -> isUse ( ) || Register :: isVirtualRegister ( I -> getReg ( ) ) ) continue ; if ( <STR_LIT> . contains ( I -> getReg ( ) ) ) return true ;


<s> bool <ISA_LIT>InstrInfo :: ClobbersPredicate ( MachineInstr & MI , std :: vector < MachineOperand > & Pred , bool SkipDead ) const {

return isPredicateSetter ( MI . getOpcode ( ) ) ;


<s> unsigned VectorComponents = <NUM_LIT> ; if ( ( <STR_LIT> . contains ( DestReg ) || <STR_LIT> . contains ( DestReg ) ) && ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ) { VectorComponents = <NUM_LIT> ; } else if ( ( <STR_LIT> . contains ( DestReg ) || <STR_LIT> . contains ( DestReg ) ) && ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ) { VectorComponents = <NUM_LIT> ; } if ( VectorComponents > <NUM_LIT> ) { for ( unsigned I = <NUM_LIT> ; I < VectorComponents ; I ++ ) { unsigned SubRegIndex = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( I ) ; buildDefaultInstruction ( MBB , MI , <STR_LIT> , RI . getSubReg ( DestReg , SubRegIndex ) , RI . getSubReg ( SrcReg , SubRegIndex ) ) . addReg ( DestReg , RegState :: Define | RegState :: Implicit ) ; } } else {

MachineInstr * NewMI = buildDefaultInstruction ( MBB , MI , <STR_LIT> , DestReg , SrcReg ) ;


<s> unsigned SubRegIndex = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( I ) ; buildDefaultInstruction ( MBB , MI , <STR_LIT> , RI . getSubReg ( DestReg , SubRegIndex ) , RI . getSubReg ( SrcReg , SubRegIndex ) ) . addReg ( DestReg , RegState :: Define | RegState :: Implicit ) ; } } else { MachineInstr * NewMI = buildDefaultInstruction ( MBB , MI , <STR_LIT> , DestReg , SrcReg ) ;


<s> unsigned RegEnd ; for ( RegIndex = <NUM_LIT> , RegEnd = IndirectRC -> getNumRegs ( ) ; RegIndex != RegEnd ; ++ RegIndex ) { if ( IndirectRC -> getRegister ( RegIndex ) == ( unsigned ) Reg ) break ; } Offset = std :: max ( Offset , ( int ) RegIndex ) ; }


<s> if ( MFI . hasVarSizedObjects ( ) ) { return - <NUM_LIT> ; } if ( MFI . getNumObjects ( ) == <NUM_LIT> ) { return - <NUM_LIT> ; } const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

const <ISA_LIT>FrameLowering * TFL = ST . getFrameLowering ( ) ;


<s> } const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFL = ST . getFrameLowering ( ) ; Register IgnoredFrameReg ; Offset = TFL -> getFrameIndexReference ( MF , - <NUM_LIT> , IgnoredFrameReg ) . getFixed ( ) ; return getIndirectIndexBegin ( MF ) + Offset ;


<s> if ( I -> isReg ( ) && ! I -> getReg ( ) . isVirtual ( ) && I -> isUse ( ) && RI . isPhysRegLiveAcrossClauses ( I -> getReg ( ) ) ) return false ;


<s> if ( ! isALUInstr ( MI . getOpcode ( ) ) ) { return false ; } for ( MachineInstr :: const_mop_iterator I = MI . operands_begin ( ) , E = MI . operands_end ( ) ; I != E ; ++ I ) { if ( ! I -> isReg ( ) || ! I -> isUse ( ) || I -> getReg ( ) . isVirtual ( ) ) continue ; if ( <STR_LIT> . contains ( I -> getReg ( ) ) ) return true ; } return false ;


<s> bool <ISA_LIT>InstrInfo :: fitsConstReadLimitations ( const std :: vector < MachineInstr * > & MIs ) const { std :: vector < unsigned > Consts ; SmallSet < int64_t , <NUM_LIT> > Literals ; for ( MachineInstr * MI : MIs ) { if ( ! isALUInstr ( MI -> getOpcode ( ) ) ) continue ; for ( const auto & Src : getSrcs ( * MI ) ) { if ( Src . first -> getReg ( ) == <STR_LIT> ) Literals . insert ( Src . second ) ; if ( Literals . size ( ) > <NUM_LIT> ) return false ; if ( Src . first -> getReg ( ) == <STR_LIT> ) Consts . push_back ( Src . second ) ; if ( <STR_LIT> . contains ( Src . first -> getReg ( ) ) || <STR_LIT> . contains ( Src . first -> getReg ( ) ) ) { unsigned Index = RI . getEncodingValue ( Src . first -> getReg ( ) ) & <NUM_LIT> ; unsigned Chan = RI . getHWRegChan ( Src . first -> getReg ( ) ) ; Consts . push_back ( ( Index << <NUM_LIT> ) | Chan ) ; } }


<s> for ( MachineInstr * MI : IG ) { IGSrcs . push_back ( ExtractSrcs ( * MI , PV , ConstCount ) ) ; unsigned Op = getOperandIdx ( MI -> getOpcode ( ) , <STR_LIT> :: bank_swizzle ) ; ValidSwizzle . push_back ( ( <ISA_LIT>InstrInfo :: BankSwizzle ) MI -> getOperand ( Op ) . getImm ( ) ) ; } std :: vector < std :: pair < int , unsigned >> TransOps ; if ( ! isLastAluTrans ) return FindSwizzleForVectorSlot ( IGSrcs , ValidSwizzle , TransOps , TransBS ) ; TransOps = std :: move ( IGSrcs . back ( ) ) ; IGSrcs . pop_back ( ) ; ValidSwizzle . pop_back ( ) ; static const <ISA_LIT>InstrInfo :: BankSwizzle TransSwz [ ] = { ALU_VEC_012_SCL_210 , ALU_VEC_021_SCL_122 , ALU_VEC_120_SCL_212 , ALU_VEC_102_SCL_221 } ; for ( <ISA_LIT>InstrInfo :: BankSwizzle TransBS : TransSwz ) { if ( ! isConstCompatible ( TransBS , TransOps , ConstCount ) ) continue ; bool Result = FindSwizzleForVectorSlot ( IGSrcs , ValidSwizzle , TransOps , TransBS ) ; if ( Result ) { ValidSwizzle . push_back ( TransBS ) ; return true ;


<s> SmallVector < std :: pair < MachineOperand * , int64_t > , <NUM_LIT> > Result ; if ( MI . getOpcode ( ) == <STR_LIT> ) { static const unsigned OpTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> :: src0_X , <STR_LIT> :: src0_sel_X } , { <STR_LIT> :: src0_Y , <STR_LIT> :: src0_sel_Y } , { <STR_LIT> :: src0_Z , <STR_LIT> :: src0_sel_Z } , { <STR_LIT> :: src0_W , <STR_LIT> :: src0_sel_W } , { <STR_LIT> :: src1_X , <STR_LIT> :: src1_sel_X } , { <STR_LIT> :: src1_Y , <STR_LIT> :: src1_sel_Y } , { <STR_LIT> :: src1_Z , <STR_LIT> :: src1_sel_Z } , { <STR_LIT> :: src1_W , <STR_LIT> :: src1_sel_W } , } ; for ( const auto & Op : OpTable ) { MachineOperand & MO = MI . getOperand ( getOperandIdx ( MI . getOpcode ( ) , Op [ <NUM_LIT> ] ) ) ; Register Reg = MO . getReg ( ) ; if ( Reg == <STR_LIT> ) { MachineOperand & Sel = MI . getOperand ( getOperandIdx ( MI . getOpcode ( ) , Op [ <NUM_LIT> ] ) ) ; Result . push_back ( std :: make_pair ( & MO , Sel . getImm ( ) ) ) ; continue ; } } return Result ; } static const unsigned OpTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> :: src0 , <STR_LIT> :: src0_sel } , { <STR_LIT> :: src1 , <STR_LIT> :: src1_sel } , { <STR_LIT> :: src2 , <STR_LIT> :: src2_sel } , } ; for ( const auto & Op : OpTable ) { int SrcIdx = getOperandIdx ( MI . getOpcode ( ) , Op [ <NUM_LIT> ] ) ; if ( SrcIdx < <NUM_LIT> ) break ; MachineOperand & MO = MI . getOperand ( SrcIdx ) ; Register Reg = MO . getReg ( ) ; if ( Reg == <STR_LIT> ) { MachineOperand & Sel = MI . getOperand ( getOperandIdx ( MI . getOpcode ( ) , Op [ <NUM_LIT> ] ) ) ; Result . push_back ( std :: make_pair ( & MO , Sel . getImm ( ) ) ) ; continue ; } if ( Reg == <STR_LIT> ) { MachineOperand & Operand = MI . getOperand ( getOperandIdx ( MI . getOpcode ( ) , <STR_LIT> :: literal ) ) ; if ( Operand . isImm ( ) ) { Result . push_back ( std :: make_pair ( & MO , Operand . getImm ( ) ) ) ; continue ; } assert ( Operand . isGlobal ( ) ) ; } Result . push_back ( std :: make_pair ( & MO , <NUM_LIT> ) ) ; }


<s> int getInstrLatency ( const InstrItineraryData * ItinData , SDNode * Node ) const override {


<s> bool <ISA_LIT>InstrInfo :: isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCyles , const BranchProbability & Probability ) const {


<s> } while ( I != MBB . begin ( ) && std :: prev ( I ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PriorI = std :: prev ( I ) ; if ( AllowModify ) I -> removeFromParent ( ) ; I = PriorI ; } MachineInstr & LastInst = * I ; unsigned LastOpc = LastInst . getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isJump ( ( -- I ) -> getOpcode ( ) ) ) { if ( LastOpc == <STR_LIT> ) { TBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( LastOpc == <STR_LIT> ) { auto predSet = I ; while ( ! isPredicateSetter ( predSet -> getOpcode ( ) ) ) { predSet = -- I ; } TBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ;

Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ;


<s> while ( I != MBB . begin ( ) && std :: prev ( I ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PriorI = std :: prev ( I ) ; if ( AllowModify ) I -> removeFromParent ( ) ; I = PriorI ; } MachineInstr & LastInst = * I ; unsigned LastOpc = LastInst . getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isJump ( ( -- I ) -> getOpcode ( ) ) ) { if ( LastOpc == <STR_LIT> ) { TBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( LastOpc == <STR_LIT> ) { auto predSet = I ; while ( ! isPredicateSetter ( predSet -> getOpcode ( ) ) ) { predSet = -- I ; } TBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( <STR_LIT> , false ) ) ; return false ; } return true ; } MachineInstr & SecondLastInst = * I ; unsigned SecondLastOpc = SecondLastInst . getOpcode ( ) ; if ( SecondLastOpc == <STR_LIT> && LastOpc == <STR_LIT> ) { auto predSet = -- I ; while ( ! isPredicateSetter ( predSet -> getOpcode ( ) ) ) { predSet = -- I ; } TBB = SecondLastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; FBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( <STR_LIT> , false ) ) ; return false ;


<s> if ( ( <STR_LIT> . contains ( DestReg ) || <STR_LIT> . contains ( DestReg ) ) && ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ) { VectorComponents = <NUM_LIT> ; } else if ( ( <STR_LIT> . contains ( DestReg ) || <STR_LIT> . contains ( DestReg ) ) && ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ) {


<s> if ( Reg == <STR_LIT> ) { Result . push_back ( std :: make_pair ( Index , <NUM_LIT> ) ) ; } if ( PV . find ( Reg ) != PV . end ( ) ) { Result . push_back ( std :: make_pair ( <NUM_LIT> , <NUM_LIT> ) ) ; continue ; } if ( Index > <NUM_LIT> ) { ConstCount ++ ; Result . push_back ( DummyPair ) ; continue ; } unsigned Chan = RI . getHWRegChan ( Reg ) ; Result . push_back ( std :: make_pair ( Index , Chan ) ) ; }

for ( ; i < <NUM_LIT> ; ++ i ) Result . push_back ( DummyPair ) ;


<s> unsigned Reg = Src . first -> getReg ( ) ; int Index = RI . getEncodingValue ( Reg ) & <NUM_LIT> ; if ( Reg == <STR_LIT> ) { Result . push_back ( std :: make_pair ( Index , <NUM_LIT> ) ) ; } if ( PV . find ( Reg ) != PV . end ( ) ) { Result . push_back ( std :: make_pair ( <NUM_LIT> , <NUM_LIT> ) ) ; continue ; } if ( Index > <NUM_LIT> ) { ConstCount ++ ;


<s> It != E ; ++ It ) { if ( It -> getOpcode ( ) == <STR_LIT> || It -> getOpcode ( ) == <STR_LIT> ) return It . getReverse ( ) ; } return MBB . end ( ) ;


<s> SmallSet < int64_t , <NUM_LIT> > Literals ; for ( unsigned i = <NUM_LIT> , n = MIs . size ( ) ; i < n ; i ++ ) { MachineInstr & MI = * MIs [ i ] ; if ( ! isALUInstr ( MI . getOpcode ( ) ) ) continue ; for ( const auto & Src : getSrcs ( MI ) ) { if ( Src . first -> getReg ( ) == <STR_LIT> ) Literals . insert ( Src . second ) ; if ( Literals . size ( ) > <NUM_LIT> ) return false ; if ( Src . first -> getReg ( ) == <STR_LIT> ) Consts . push_back ( Src . second ) ;

if ( <STR_LIT> . contains ( Src . first -> getReg ( ) ) || <STR_LIT> . contains ( Src . first -> getReg ( ) ) ) {


<s> unsigned ConstCount ; BankSwizzle TransBS = ALU_VEC_012_SCL_210 ; for ( unsigned i = <NUM_LIT> , e = IG . size ( ) ; i < e ; ++ i ) { IGSrcs . push_back ( ExtractSrcs ( * IG [ i ] , PV , ConstCount ) ) ; unsigned Op = getOperandIdx ( IG [ i ] -> getOpcode ( ) , <STR_LIT> :: bank_swizzle ) ; ValidSwizzle . push_back ( ( <ISA_LIT>InstrInfo :: BankSwizzle ) IG [ i ] -> getOperand ( Op ) . getImm ( ) ) ; } std :: vector < std :: pair < int , unsigned >> TransOps ; if ( ! isLastAluTrans ) return FindSwizzleForVectorSlot ( IGSrcs , ValidSwizzle , TransOps , TransBS ) ; TransOps = std :: move ( IGSrcs . back ( ) ) ; IGSrcs . pop_back ( ) ; ValidSwizzle . pop_back ( ) ; static const <ISA_LIT>InstrInfo :: BankSwizzle TransSwz [ ] = { ALU_VEC_012_SCL_210 , ALU_VEC_021_SCL_122 , ALU_VEC_120_SCL_212 , ALU_VEC_102_SCL_221 } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) {


<s> if ( ! FBB ) { if ( Cond . empty ( ) ) { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } else { MachineInstr * PredSet = findFirstPredicateSetterFrom ( MBB , MBB . end ( ) ) ; assert ( PredSet && <STR_LIT> ) ; addFlag ( * PredSet , <NUM_LIT> , MO_FLAG_PUSH ) ; PredSet -> getOperand ( <NUM_LIT> ) . setImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( <STR_LIT> , RegState :: Kill ) ; MachineBasicBlock :: iterator CfAlu = FindLastAluClause ( MBB ) ; if ( CfAlu == MBB . end ( ) ) return <NUM_LIT> ; assert ( CfAlu -> getOpcode ( ) == <STR_LIT> ) ; CfAlu -> setDesc ( get ( <STR_LIT> ) ) ; return <NUM_LIT> ; } } else { MachineInstr * PredSet = findFirstPredicateSetterFrom ( MBB , MBB . end ( ) ) ; assert ( PredSet && <STR_LIT> ) ; addFlag ( * PredSet , <NUM_LIT> , MO_FLAG_PUSH ) ;


<s> const std :: pair < int , unsigned > & Src = Srcs [ j ] ; if ( Src . first < <NUM_LIT> || Src . first == <NUM_LIT> ) continue ; if ( Src . first == GET_REG_INDEX ( RI . getEncodingValue ( <STR_LIT> ) ) ) { if ( Swz [ i ] != <ISA_LIT>InstrInfo :: ALU_VEC_012_SCL_210 && Swz [ i ] != <ISA_LIT>InstrInfo :: ALU_VEC_021_SCL_122 ) { return false ; } continue ; } if ( Vector [ Src . second ] [ j ] < <NUM_LIT> ) Vector [ Src . second ] [ j ] = Src . first ; if ( Vector [ Src . second ] [ j ] != Src . first ) return i ; } } for ( unsigned i = <NUM_LIT> , e = TransSrcs . size ( ) ; i < e ; ++ i ) { const std :: pair < int , unsigned > & Src = TransSrcs [ i ] ; unsigned Cycle = getTransSwizzle ( TransSwz , i ) ;

if ( Src . first < <NUM_LIT> ) continue ;


<s> return MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ; } else if ( isVector ( MI ) ) {


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) { return false ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { if ( MI . getParent ( ) -> begin ( ) != MachineBasicBlock :: const_iterator ( MI ) ) return false ; return MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ; } else if ( isVector ( MI ) ) { return false ; } else { return <ISA_LIT>InstrInfo :: isPredicable ( MI ) ;


<s> const <ISA_LIT>FrameLowering * TFL = ST . getFrameLowering ( ) ; unsigned StackWidth = TFL -> getStackWidth ( MF ) ; int End = getIndirectIndexEnd ( MF ) ; if ( End == - <NUM_LIT> ) return ; for ( int Index = getIndirectIndexBegin ( MF ) ; Index <= End ; ++ Index ) {

for ( unsigned Chan = <NUM_LIT> ; Chan < StackWidth ; ++ Chan ) {


<s> break ; case <STR_LIT> : MO . setImm ( <STR_LIT> ) ; break ; case <STR_LIT> : MO . setImm ( <STR_LIT> ) ; break ; case <STR_LIT> : MO . setImm ( <STR_LIT> ) ; break ; default : return true ; }

MachineOperand & MO2 = Cond [ <NUM_LIT> ] ;


<s> if ( MFI . getNumObjects ( ) == <NUM_LIT> ) { return - <NUM_LIT> ; } if ( MRI . livein_empty ( ) ) { return <NUM_LIT> ; } const TargetRegisterClass * IndirectRC = getIndirectAddrRegClass ( ) ; for ( MachineRegisterInfo :: livein_iterator LI = MRI . livein_begin ( ) , LE = MRI . livein_end ( ) ; LI != LE ; ++ LI ) { unsigned Reg = LI -> first ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) || ! IndirectRC -> contains ( Reg ) ) continue ; unsigned RegIndex ; unsigned RegEnd ; for ( RegIndex = <NUM_LIT> , RegEnd = IndirectRC -> getNumRegs ( ) ; RegIndex != RegEnd ; ++ RegIndex ) { if ( IndirectRC -> getRegister ( RegIndex ) == Reg ) break ; } Offset = std :: max ( Offset , ( int ) RegIndex ) ;


<s> return <NUM_LIT> ; } const TargetRegisterClass * IndirectRC = getIndirectAddrRegClass ( ) ; for ( MachineRegisterInfo :: livein_iterator LI = MRI . livein_begin ( ) , LE = MRI . livein_end ( ) ; LI != LE ; ++ LI ) { unsigned Reg = LI -> first ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) || ! IndirectRC -> contains ( Reg ) ) continue ; unsigned RegIndex ; unsigned RegEnd ; for ( RegIndex = <NUM_LIT> , RegEnd = IndirectRC -> getNumRegs ( ) ; RegIndex != RegEnd ; ++ RegIndex ) {

if ( IndirectRC -> getRegister ( RegIndex ) == Reg ) break ;


<s> const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFL = ST . getFrameLowering ( ) ; unsigned StackWidth = TFL -> getStackWidth ( MF ) ; int End = getIndirectIndexEnd ( MF ) ; if ( End == - <NUM_LIT> ) return ; for ( int Index = getIndirectIndexBegin ( MF ) ; Index <= End ; ++ Index ) {

unsigned SuperReg = <STR_LIT> . getRegister ( Index ) ;


<s> unsigned Reg = Src . first -> getReg ( ) ; int Index = RI . getEncodingValue ( Reg ) & <NUM_LIT> ; if ( Reg == <STR_LIT> ) { Result . push_back ( std :: make_pair ( Index , <NUM_LIT> ) ) ; } if ( PV . find ( Reg ) != PV . end ( ) ) { Result . push_back ( std :: make_pair ( <NUM_LIT> , <NUM_LIT> ) ) ; continue ; } if ( Index > <NUM_LIT> ) { ConstCount ++ ; Result . push_back ( DummyPair ) ; continue ; } unsigned Chan = RI . getHWRegChan ( Reg ) ; Result . push_back ( std :: make_pair ( Index , Chan ) ) ; }


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MFI . hasVarSizedObjects ( ) ) { return - <NUM_LIT> ; } if ( MFI . getNumObjects ( ) == <NUM_LIT> ) { return - <NUM_LIT> ; } const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFL = ST . getFrameLowering ( ) ; Register IgnoredFrameReg ;

Offset = TFL -> getFrameIndexReference ( MF , - <NUM_LIT> , IgnoredFrameReg ) ;


<s> if ( MFI . hasVarSizedObjects ( ) ) { return - <NUM_LIT> ; } if ( MFI . getNumObjects ( ) == <NUM_LIT> ) { return - <NUM_LIT> ; } const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> buildMovInstr ( MBB , MI , MI -> getOperand ( DstOpIdx ) . getReg ( ) , getIndirectAddrRegClass ( ) -> getRegister ( Address ) ) ; } else { buildIndirectRead ( MBB , MI , MI -> getOperand ( DstOpIdx ) . getReg ( ) , Address , OffsetReg ) ; } } else if ( isRegisterStore ( * MI ) ) { int ValOpIdx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: val ) ; unsigned RegIndex = MI -> getOperand ( RegOpIdx ) . getImm ( ) ; unsigned Channel = MI -> getOperand ( ChanOpIdx ) . getImm ( ) ; unsigned Address = calculateIndirectAddress ( RegIndex , Channel ) ; unsigned OffsetReg = MI -> getOperand ( OffsetOpIdx ) . getReg ( ) ; if ( OffsetReg == <STR_LIT> ) { buildMovInstr ( MBB , MI , getIndirectAddrRegClass ( ) -> getRegister ( Address ) , MI -> getOperand ( ValOpIdx ) . getReg ( ) ) ; } else { buildIndirectWrite ( MBB , MI , MI -> getOperand ( ValOpIdx ) . getReg ( ) , calculateIndirectAddress ( RegIndex , Channel ) , OffsetReg ) ; }


<s> const std :: pair < int , unsigned > DummyPair ( - <NUM_LIT> , <NUM_LIT> ) ; std :: vector < std :: pair < int , unsigned > > Result ; unsigned i = <NUM_LIT> ; for ( unsigned n = Srcs . size ( ) ; i < n ; ++ i ) { unsigned Reg = Srcs [ i ] . first -> getReg ( ) ; int Index = RI . getEncodingValue ( Reg ) & <NUM_LIT> ; if ( Reg == <STR_LIT> ) { Result . push_back ( std :: make_pair ( Index , <NUM_LIT> ) ) ; } if ( PV . find ( Reg ) != PV . end ( ) ) { Result . push_back ( std :: make_pair ( <NUM_LIT> , <NUM_LIT> ) ) ; continue ; } if ( Index > <NUM_LIT> ) { ConstCount ++ ; Result . push_back ( DummyPair ) ; continue ; } unsigned Chan = RI . getHWRegChan ( Reg ) ; Result . push_back ( std :: make_pair ( Index , Chan ) ) ; } for ( ; i < <NUM_LIT> ; ++ i ) Result . push_back ( DummyPair ) ;


<s> SmallSet < int64_t , <NUM_LIT> > Literals ; for ( unsigned i = <NUM_LIT> , n = MIs . size ( ) ; i < n ; i ++ ) { MachineInstr * MI = MIs [ i ] ; if ( ! isALUInstr ( MI -> getOpcode ( ) ) ) continue ; ArrayRef < std :: pair < MachineOperand * , int64_t >> Srcs = getSrcs ( MI ) ; for ( const auto & Src : Srcs ) { if ( Src . first -> getReg ( ) == <STR_LIT> ) Literals . insert ( Src . second ) ; if ( Literals . size ( ) > <NUM_LIT> ) return false ; if ( Src . first -> getReg ( ) == <STR_LIT> ) Consts . push_back ( Src . second ) ; if ( <STR_LIT> . contains ( Src . first -> getReg ( ) ) || <STR_LIT> . contains ( Src . first -> getReg ( ) ) ) { unsigned Index = RI . getEncodingValue ( Src . first -> getReg ( ) ) & <NUM_LIT> ;

unsigned Chan = RI . getHWRegChan ( Src . first -> getReg ( ) ) ;


<s> for ( const auto & Src : Srcs ) { if ( Src . first -> getReg ( ) == <STR_LIT> ) Literals . insert ( Src . second ) ; if ( Literals . size ( ) > <NUM_LIT> ) return false ; if ( Src . first -> getReg ( ) == <STR_LIT> ) Consts . push_back ( Src . second ) ; if ( <STR_LIT> . contains ( Src . first -> getReg ( ) ) || <STR_LIT> . contains ( Src . first -> getReg ( ) ) ) {

unsigned Index = RI . getEncodingValue ( Src . first -> getReg ( ) ) & <NUM_LIT> ;


<s> SmallVector < std :: pair < MachineOperand * , int64_t > , <NUM_LIT> > <ISA_LIT>InstrInfo :: getSrcs ( MachineInstr * MI ) const { SmallVector < std :: pair < MachineOperand * , int64_t > , <NUM_LIT> > Result ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { static const unsigned OpTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> :: src0_X , <STR_LIT> :: src0_sel_X } , { <STR_LIT> :: src0_Y , <STR_LIT> :: src0_sel_Y } , { <STR_LIT> :: src0_Z , <STR_LIT> :: src0_sel_Z } , { <STR_LIT> :: src0_W , <STR_LIT> :: src0_sel_W } , { <STR_LIT> :: src1_X , <STR_LIT> :: src1_sel_X } , { <STR_LIT> :: src1_Y , <STR_LIT> :: src1_sel_Y } , { <STR_LIT> :: src1_Z , <STR_LIT> :: src1_sel_Z } , { <STR_LIT> :: src1_W , <STR_LIT> :: src1_sel_W } , } ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) { MachineOperand & MO = MI -> getOperand ( getOperandIdx ( MI -> getOpcode ( ) , OpTable [ j ] [ <NUM_LIT> ] ) ) ; unsigned Reg = MO . getReg ( ) ;


<s> bool <ISA_LIT>InstrInfo :: usesVertexCache ( const MachineInstr * MI ) const {

const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ;


<s> return ! <STR_LIT> ( MF -> getFunction ( ) -> getCallingConv ( ) ) && usesVertexCache ( MI -> getOpcode ( ) ) ;


<s> break ; case <STR_LIT> : MO . setImm ( <STR_LIT> ) ; break ; case <STR_LIT> : MO . setImm ( <STR_LIT> ) ; break ; case <STR_LIT> : MO . setImm ( <STR_LIT> ) ; break ; default : return true ; } MachineOperand & MO2 = Cond [ <NUM_LIT> ] ; switch ( MO2 . getReg ( ) ) { case <STR_LIT> : MO2 . setReg ( <STR_LIT> ) ; break ; case <STR_LIT> : MO2 . setReg ( <STR_LIT> ) ;


<s> assert ( PredSet && <STR_LIT> ) ; addFlag ( PredSet , <NUM_LIT> , MO_FLAG_PUSH ) ; PredSet -> getOperand ( <NUM_LIT> ) . setImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( <STR_LIT> , RegState :: Kill ) ; MachineBasicBlock :: iterator CfAlu = FindLastAluClause ( MBB ) ; if ( CfAlu == MBB . end ( ) ) return <NUM_LIT> ; assert ( CfAlu -> getOpcode ( ) == <STR_LIT> ) ; CfAlu -> setDesc ( get ( <STR_LIT> ) ) ; return <NUM_LIT> ; } } else { MachineInstr * PredSet = findFirstPredicateSetterFrom ( MBB , MBB . end ( ) ) ; assert ( PredSet && <STR_LIT> ) ; addFlag ( PredSet , <NUM_LIT> , MO_FLAG_PUSH ) ; PredSet -> getOperand ( <NUM_LIT> ) . setImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( <STR_LIT> , RegState :: Kill ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; MachineBasicBlock :: iterator CfAlu = FindLastAluClause ( MBB ) ; if ( CfAlu == MBB . end ( ) ) return <NUM_LIT> ; assert ( CfAlu -> getOpcode ( ) == <STR_LIT> ) ; CfAlu -> setDesc ( get ( <STR_LIT> ) ) ;


<s> MachineInstr & LastInst = * I ; unsigned LastOpc = LastInst . getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isJump ( static_cast < MachineInstr * > ( -- I ) -> getOpcode ( ) ) ) { if ( LastOpc == <STR_LIT> ) { TBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( LastOpc == <STR_LIT> ) { auto predSet = I ; while ( ! isPredicateSetter ( predSet -> getOpcode ( ) ) ) { predSet = -- I ; } TBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( <STR_LIT> , false ) ) ; return false ; } return true ; } MachineInstr & SecondLastInst = * I ; unsigned SecondLastOpc = SecondLastInst . getOpcode ( ) ; if ( SecondLastOpc == <STR_LIT> && LastOpc == <STR_LIT> ) { auto predSet = -- I ; while ( ! isPredicateSetter ( predSet -> getOpcode ( ) ) ) { predSet = -- I ; } TBB = SecondLastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; FBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( <STR_LIT> , false ) ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( TargetMachine * TM , CodeGenOpt :: Level OptLevel ) : <ISA_LIT>DAGToDAGISel ( TM , OptLevel ) {


<s> bool <ISA_LIT>DAGToDAGISel :: SelectGlobalValueConstantOffset ( SDValue Addr , SDValue & IntPtr ) {

if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Addr ) ) {


<s> bool <ISA_LIT>DAGToDAGISel :: SelectGlobalValueConstantOffset ( SDValue Addr , SDValue & IntPtr ) { if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Addr ) ) { IntPtr = CurDAG -> getIntPtrConstant ( Cst -> getZExtValue ( ) / <NUM_LIT> , SDLoc ( Addr ) , true ) ; return true ; }


<s> BaseReg = Addr ; Offset = CurDAG -> getIntPtrConstant ( <NUM_LIT> , SDLoc ( Addr ) , true ) ; return true ; }


<s> if ( VT . bitsLT ( <STR_LIT> ) ) return false ; if ( IsFast ) * IsFast = true ; return VT . bitsGT ( <STR_LIT> ) && Align % <NUM_LIT> == <NUM_LIT> ;


<s> if ( IsFast ) * IsFast = false ; if ( ! VT . isSimple ( ) || VT == <STR_LIT> ) return false ; if ( VT . bitsLT ( <STR_LIT> ) ) return false ;


<s> if ( ( AS == AMDGPUA<ISA_LIT> . LOCAL_ADDRESS || AS == AMDGPUA<ISA_LIT> . PRIVATE_ADDRESS ) ) {

return ( MemVT . getSizeInBits ( ) <= <NUM_LIT> ) ;


<s> if ( NewBldVec [ i ] . isUndef ( ) ) continue ; for ( unsigned j = <NUM_LIT> ; j < i ; j ++ ) { if ( NewBldVec [ i ] == NewBldVec [ j ] ) { NewBldVec [ i ] = DAG . getUNDEF ( NewBldVec [ i ] . getValueType ( ) ) ; RemapSwizzle [ i ] = j ; break ; } } } return DAG . getBuildVector ( VectorEntry . getValueType ( ) , SDLoc ( VectorEntry ) , NewBldVec ) ;


<s> static int ConstantAddressBlock ( unsigned AddressSpace , <ISA_LIT>AS AMDGPUA<ISA_LIT> ) { switch ( AddressSpace ) { case AMDGPUA<ISA_LIT> . CONSTANT_BUFFER_0 : return <NUM_LIT> ; case AMDGPUA<ISA_LIT> . CONSTANT_BUFFER_1 : return <NUM_LIT> + <NUM_LIT> ; case AMDGPUA<ISA_LIT> . CONSTANT_BUFFER_2 : return <NUM_LIT> + <NUM_LIT> * <NUM_LIT> ; case AMDGPUA<ISA_LIT> . CONSTANT_BUFFER_3 : return <NUM_LIT> + <NUM_LIT> * <NUM_LIT> ; case AMDGPUA<ISA_LIT> . CONSTANT_BUFFER_4 :