<s> case <STR_LIT> : { unsigned ImmReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , Inst , DL , get ( <STR_LIT> ) , ImmReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , Inst , DL , get ( <STR_LIT> ) , ResultReg ) . addReg ( ImmReg , RegState :: Kill ) . add ( Src0 ) . add ( Src1 ) ; break ; } case <STR_LIT> : { unsigned ImmReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned TmpReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , Inst , DL , get ( <STR_LIT> ) , TmpReg ) . addImm ( <NUM_LIT> ) . add ( Src0 ) ; BuildMI ( * MBB , Inst , DL , get ( <STR_LIT> ) , ImmReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , Inst , DL , get ( <STR_LIT> ) , ResultReg ) . add ( Src1 ) . addReg ( ImmReg , RegState :: Kill ) . addReg ( TmpReg , RegState :: Kill ) ;


<s> static void reportIllegalCopy ( const <ISA_LIT>InstrInfo * TII , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) {

MachineFunction * MF = MBB . getParent ( ) ;


<s> DiagnosticInfoUnsupported IllegalCopy ( * MF -> getFunction ( ) , <STR_LIT> , DL , DS_Error ) ; LLVMContext & C = MF -> getFunction ( ) -> getContext ( ) ; C . diagnose ( IllegalCopy ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> bool <ISA_LIT>InstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { assert ( Cond . size ( ) == <NUM_LIT> ) ; Cond [ <NUM_LIT> ] . setImm ( - Cond [ <NUM_LIT> ] . getImm ( ) ) ; return false ;


<s> assert ( Cond . size ( ) == <NUM_LIT> ) ; Cond [ <NUM_LIT> ] . setImm ( - Cond [ <NUM_LIT> ] . getImm ( ) ) ; return false ;


<s> const MachineOperand * FirstDst = nullptr ; const MachineOperand * SecondDst = nullptr ; if ( ( isMUBUF ( FirstLdSt ) && isMUBUF ( SecondLdSt ) ) || ( isMTBUF ( FirstLdSt ) && isMTBUF ( SecondLdSt ) ) || ( isFLAT ( FirstLdSt ) && isFLAT ( SecondLdSt ) ) ) { FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdata ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdata ) ; } else if ( isSMRD ( FirstLdSt ) && isSMRD ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: sdst ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: sdst ) ; } else if ( isDS ( FirstLdSt ) && isDS ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdst ) ;

SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdst ) ;


<s> & <STR_LIT> ; unsigned MidReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; const TargetRegisterClass * SrcSubRC = RI . getSubRegClass ( SrcRC , <STR_LIT> ) ; MachineOperand SrcRegSub0 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , <STR_LIT> , SrcSubRC ) ; MachineOperand SrcRegSub1 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , <STR_LIT> , SrcSubRC ) ; BuildMI ( MBB , MII , DL , InstDesc , MidReg ) . add ( SrcRegSub0 ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MII , DL , InstDesc , ResultReg ) . add ( SrcRegSub1 ) . addReg ( MidReg ) ;

MRI . replaceRegWith ( Dest . getReg ( ) , ResultReg ) ;


<s> const TargetRegisterClass * NewDestSubRC = RI . getSubRegClass ( NewDestRC , <STR_LIT> ) ; unsigned DestSub0 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & LoHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . add ( SrcReg0Sub0 ) . add ( SrcReg1Sub0 ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; unsigned DestSub1 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & HiHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . add ( SrcReg0Sub1 ) . add ( SrcReg1Sub1 ) ; unsigned FullDestReg = MRI . createVirtualRegister ( NewDestRC ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ;

MRI . replaceRegWith ( Dest . getReg ( ) , FullDestReg ) ;


<s> MachineBasicBlock & MBB = * Inst . getParent ( ) ; MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; MachineOperand & Dest = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src0 = Inst . getOperand ( <NUM_LIT> ) ; DebugLoc DL = Inst . getDebugLoc ( ) ; MachineBasicBlock :: iterator MII = Inst ; const MCInstrDesc & InstDesc = get ( Opcode ) ; const TargetRegisterClass * Src0RC = Src0 . isReg ( ) ? MRI . getRegClass ( Src0 . getReg ( ) ) : & <STR_LIT> ; const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ;

const TargetRegisterClass * DestRC = MRI . getRegClass ( Dest . getReg ( ) ) ;


<s> if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; const MCInstrDesc & OpDesc = get ( getSGPRSpillSaveOpcode ( RC -> getSize ( ) ) ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) && RC -> getSize ( ) == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; } MachineInstrBuilder Spill = BuildMI ( MBB , MI , DL , OpDesc ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getScratchWaveOffsetReg ( ) , RegState :: Implicit ) ; if ( ST . hasScalarStores ( ) ) { Spill . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; }


<s> } else { assert ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; ImmOffset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( MBB -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getGeneration ( ) <= <ISA_LIT>Subtarget :: SEA_ISLANDS ) ImmOffset <<= <NUM_LIT> ; RegOffset = MRI . createVirtualRegister ( & <STR_LIT> ) ; if ( isUInt < <NUM_LIT> > ( ImmOffset ) ) { BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , RegOffset ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , RegOffset ) . addImm ( ImmOffset ) ; ImmOffset = <NUM_LIT> ; } } unsigned SRsrc = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord0 = RegOffset ; unsigned DWord1 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord2 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord3 = MRI . createVirtualRegister ( & <STR_LIT> ) ; uint64_t RsrcDataFormat = getDefaultRsrcDataFormat ( ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord1 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord2 ) . addImm ( RsrcDataFormat & <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord3 ) . addImm ( RsrcDataFormat >> <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , SRsrc ) . addReg ( DWord0 ) . addImm ( <STR_LIT> ) . addReg ( DWord1 ) . addImm ( <STR_LIT> ) . addReg ( DWord2 ) . addImm ( <STR_LIT> ) . addReg ( DWord3 ) . addImm ( <STR_LIT> ) ; MI -> setDesc ( get ( NewOpcode ) ) ; if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { MI -> getOperand ( <NUM_LIT> ) . setReg ( SRsrc ) ; } else { MI -> getOperand ( <NUM_LIT> ) . ChangeToRegister ( SRsrc , false ) ; } MI -> addOperand ( * MBB -> getParent ( ) , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MI -> addOperand ( * MBB -> getParent ( ) , MachineOperand :: CreateImm ( ImmOffset ) ) ; MI -> addOperand ( * MBB -> getParent ( ) , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ;


<s> const MIRFormatter * getMIRFormatter ( ) const override {

if ( ! Formatter . get ( ) ) Formatter = std :: make_unique < <ISA_LIT>MIRFormatter > ( ) ;


<s> if ( ! Formatter . get ( ) ) Formatter = std :: make_unique < <ISA_LIT>MIRFormatter > ( ) ;


<s> unsigned getOpSize ( const MachineInstr & MI , unsigned OpNo ) const { const MachineOperand & MO = MI . getOperand ( OpNo ) ;


<s> inline TargetInstrInfo :: RegSubRegPair getRegSubRegPair ( const MachineOperand & O ) { assert ( O . isReg ( ) ) ;

return TargetInstrInfo :: RegSubRegPair ( O . getReg ( ) , O . getSubReg ( ) ) ;


<s> const TargetSchedModel & getSchedModel ( ) const { return SchedModel ;


<s> const GCNSubtarget & getSubtarget ( ) const { return ST ;


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ;

if ( MI . isInlineAsm ( ) ) return true ;


<s> return llvm :: any_of ( MI . explicit_uses ( ) , [ & MRI , this ] ( const MachineOperand & MO ) {

return MO . isReg ( ) && RI . isVGPR ( MRI , MO . getReg ( ) ) ; } ) ;


<s> const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;

return llvm :: any_of ( MI . explicit_uses ( ) , [ & MRI , this ] ( const MachineOperand & MO ) {


<s> bool isAtomic ( uint16_t Opcode ) const {

return get ( Opcode ) . TSFlags & ( <STR_LIT> | <STR_LIT> ) ;


<s> bool isAtomicNoRet ( uint16_t Opcode ) const { return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> bool isDOT ( uint16_t Opcode ) const {

return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> bool isDOT ( uint16_t Opcode ) const { return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> bool isFPAtomic ( uint16_t Opcode ) const {


<s> return isInlineConstant ( Imm . bitcastToAPInt ( ) ) ;


<s> bool isInlineConstant ( const APFloat & Imm ) const {

return isInlineConstant ( Imm . bitcastToAPInt ( ) ) ;


<s> bool isMAI ( uint16_t Opcode ) const { return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> if ( ! P . SubReg ) return RC == & TRC ; auto * TRI = MRI . getTargetRegisterInfo ( ) ; return RC == TRI -> getMatchingSuperRegClass ( RC , & TRC , P . SubReg ) ;


<s> if ( ! P . SubReg ) return RC == & TRC ;

auto * TRI = MRI . getTargetRegisterInfo ( ) ;


<s> bool isPacked ( uint16_t Opcode ) const { return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> return Flags & ( <STR_LIT> | <STR_LIT> ) ;


<s> bool isSegmentSpecificFLAT ( uint16_t Opcode ) const { auto Flags = get ( Opcode ) . TSFlags ; return Flags & ( <STR_LIT> | <STR_LIT> ) ;


Register Dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


<s> bool usesFPDPRounding ( uint16_t Opcode ) const {


<s> void <ISA_LIT>InstrInfo :: addSCCDefUsersToVALUWorklist ( MachineOperand & Op , MachineInstr & SCCDefInst , SetVectorType & Worklist ) const { assert ( Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> && Op . isDef ( ) && ! Op . isDead ( ) && Op . getParent ( ) == & SCCDefInst ) ; for ( MachineInstr & MI :

make_range ( std :: next ( MachineBasicBlock :: iterator ( SCCDefInst ) ) , SCCDefInst . getParent ( ) -> end ( ) ) ) {


<s> assert ( Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> && Op . isDef ( ) && ! Op . isDead ( ) && Op . getParent ( ) == & SCCDefInst ) ; for ( MachineInstr & MI : make_range ( std :: next ( MachineBasicBlock :: iterator ( SCCDefInst ) ) , SCCDefInst . getParent ( ) -> end ( ) ) ) {

if ( MI . findRegisterUseOperandIdx ( <STR_LIT> , false , & RI ) != - <NUM_LIT> ) Worklist . insert ( & MI ) ;


<s> case <STR_LIT> : break ; default : OpNo = I . getOperandNo ( ) ; break ; } if ( ! RI . hasVGPRs ( getOpRegClass ( UseMI , OpNo ) ) ) { Worklist . insert ( & UseMI ) ; do { ++ I ; } while ( I != E && I -> getParent ( ) == & UseMI ) ; } else {


<s> if ( MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( isDS ( MIa ) ) { if ( isDS ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) || isSegmentSpecificFLAT ( MIb ) ; } if ( isMUBUF ( MIa ) || isMTBUF ( MIa ) ) { if ( isMUBUF ( MIb ) || isMTBUF ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) && ! isSMRD ( MIb ) ; } if ( isSMRD ( MIa ) ) { if ( isSMRD ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) && ! isMUBUF ( MIa ) && ! isMTBUF ( MIa ) ; }


<s> assert ( ( MIb . mayLoad ( ) || MIb . mayStore ( ) ) && <STR_LIT> ) ; if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) ) return false ; if ( MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( isDS ( MIa ) ) { if ( isDS ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) || isSegmentSpecificFLAT ( MIb ) ; } if ( isMUBUF ( MIa ) || isMTBUF ( MIa ) ) { if ( isMUBUF ( MIb ) || isMTBUF ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) && ! isSMRD ( MIb ) ; } if ( isSMRD ( MIa ) ) { if ( isSMRD ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) && ! isMUBUF ( MIa ) && ! isMTBUF ( MIa ) ; }


<s> } RS -> enterBasicBlock ( Entry ) ; unsigned STmp0 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; unsigned STmp1 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp0 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Z ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Y ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( STmp1 ) . addReg ( STmp0 ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp1 ) . addReg ( TIDIGXReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp0 ) . addReg ( TIDIGYReg ) . addReg ( TIDReg ) ; getAddNoCarry ( Entry , Insert , DL , TIDReg ) . addReg ( TIDReg ) . addReg ( TIDIGZReg ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addReg ( TIDReg ) ; }

BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( <NUM_LIT> ) . addReg ( TIDReg ) ;


<s> unsigned WavefrontSize = ST . getWavefrontSize ( ) ; unsigned TIDReg = MFI -> getTIDReg ( ) ; if ( ! MFI -> hasCalculatedTID ( ) ) { MachineBasicBlock & Entry = MBB . getParent ( ) -> front ( ) ; MachineBasicBlock :: iterator Insert = Entry . front ( ) ; const DebugLoc & DL = Insert -> getDebugLoc ( ) ; TIDReg = RI . findUnusedRegister ( MF -> getRegInfo ( ) , & <STR_LIT> , * MF ) ; if ( TIDReg == <STR_LIT> ) return TIDReg ; if ( ! <STR_LIT> ( MF -> getFunction ( ) . getCallingConv ( ) ) && WorkGroupSize > WavefrontSize ) { unsigned TIDIGXReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; unsigned TIDIGYReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; unsigned TIDIGZReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; unsigned InputPtrReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; for ( unsigned Reg : { TIDIGXReg , TIDIGYReg , TIDIGZReg } ) { if ( ! Entry . isLiveIn ( Reg ) ) Entry . addLiveIn ( Reg ) ; } RS -> enterBasicBlock ( Entry ) ; unsigned STmp0 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; unsigned STmp1 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp0 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Z ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Y ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( STmp1 ) . addReg ( STmp0 ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp1 ) . addReg ( TIDIGXReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp0 ) . addReg ( TIDIGYReg ) . addReg ( TIDReg ) ; getAddNoCarry ( Entry , Insert , DL , TIDReg ) . addReg ( TIDReg ) . addReg ( TIDIGZReg ) . addImm ( <NUM_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: canShrink ( const MachineInstr & MI , const MachineRegisterInfo & MRI ) const { const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ; if ( Src2 ) { switch ( MI . getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; if ( ! Src1 -> isReg ( ) || ! RI . isVGPR ( MRI , Src1 -> getReg ( ) ) ) return false ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Src2 -> isReg ( ) || ! RI . isVGPR ( MRI , Src2 -> getReg ( ) ) || hasModifiersSet ( MI , <STR_LIT> :: src2_modifiers ) ) return false ; break ; case <STR_LIT> : break ; } }


<s> const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; if ( ! Src1 -> isReg ( ) || ! RI . isVGPR ( MRI , Src1 -> getReg ( ) ) ) return false ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Src2 -> isReg ( ) || ! RI . isVGPR ( MRI , Src2 -> getReg ( ) ) || hasModifiersSet ( MI , <STR_LIT> :: src2_modifiers ) ) return false ;


<s> return false ; } unsigned Width0 = ( * MIa . memoperands_begin ( ) ) -> getSize ( ) ; unsigned Width1 = ( * MIb . memoperands_begin ( ) ) -> getSize ( ) ; if ( offsetsDoNotOverlap ( Width0 , Offset0 , Width1 , Offset1 ) ) { return true ; }


<s> if ( pseudoToMCOpcode ( NewOpc ) != - <NUM_LIT> ) return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( * Dst ) . add ( * Src0 ) . addImm ( Imm ) . add ( * Src2 ) ; } if ( auto Imm = getFoldableImm ( Src0 ) ) { if ( pseudoToMCOpcode ( NewOpc ) != - <NUM_LIT> && isOperandLegal ( MI , <STR_LIT> ( NewOpc , <STR_LIT> :: src0 ) , Src1 ) ) return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( * Dst ) . add ( * Src1 ) . addImm ( Imm ) . add ( * Src2 ) ; } } unsigned NewOpc = IsFMA ? ( IsF16 ? <STR_LIT> : <STR_LIT> ) : ( IsF16 ? <STR_LIT> : <STR_LIT> ) ; if ( pseudoToMCOpcode ( NewOpc ) == - <NUM_LIT> ) return nullptr ;

return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( * Dst ) . addImm ( Src0Mods ? Src0Mods -> getImm ( ) : <NUM_LIT> ) . add ( * Src0 ) . addImm ( Src1Mods ? Src1Mods -> getImm ( ) : <NUM_LIT> ) . add ( * Src1 ) . addImm ( <NUM_LIT> ) . add ( * Src2 ) . addImm ( Clamp ? Clamp -> getImm ( ) : <NUM_LIT> ) . addImm ( Omod ? Omod -> getImm ( ) : <NUM_LIT> ) ;


<s> const MachineOperand * Omod = getNamedOperand ( MI , <STR_LIT> :: omod ) ; if ( ! Src0Mods && ! Src1Mods && ! Clamp && ! Omod && ( ST . getConstantBusLimit ( Opc ) > <NUM_LIT> || ! Src0 -> isReg ( ) || ! RI . isSGPRReg ( MBB -> getParent ( ) -> getRegInfo ( ) , Src0 -> getReg ( ) ) ) ) { if ( auto Imm = getFoldableImm ( Src2 ) ) { unsigned NewOpc = IsFMA ? ( IsF16 ? <STR_LIT> : <STR_LIT> ) : ( IsF16 ? <STR_LIT> : <STR_LIT> ) ; if ( pseudoToMCOpcode ( NewOpc ) != - <NUM_LIT> ) return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( * Dst ) . add ( * Src0 ) . add ( * Src1 ) . addImm ( Imm ) ; } unsigned NewOpc = IsFMA ? ( IsF16 ? <STR_LIT> : <STR_LIT> ) : ( IsF16 ? <STR_LIT> : <STR_LIT> ) ; if ( auto Imm = getFoldableImm ( Src1 ) ) { if ( pseudoToMCOpcode ( NewOpc ) != - <NUM_LIT> ) return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( * Dst ) . add ( * Src0 ) . addImm ( Imm ) . add ( * Src2 ) ; }

if ( auto Imm = getFoldableImm ( Src0 ) ) {


<s> if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) { if ( SrcReg == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( - <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; return ; } if ( ! <STR_LIT> . contains ( SrcReg ) ) { reportIllegalCopy ( this , MBB , MI , DL , DestReg , SrcReg , KillSrc ) ; return ; } BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( RC == & <STR_LIT> ) { if ( DestReg == <STR_LIT> ) { if ( <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } return ; } if ( ! <STR_LIT> . contains ( SrcReg ) ) { reportIllegalCopy ( this , MBB , MI , DL , DestReg , SrcReg , KillSrc ) ; return ; } BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( DestReg == <STR_LIT> ) { assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) ; return ; } unsigned EltSize = <NUM_LIT> ; unsigned Opcode = <STR_LIT> ; if ( RI . isSGPRClass ( RC ) ) { if ( ! ( RI . getRegSizeInBits ( * RC ) % <NUM_LIT> ) ) { Opcode = <STR_LIT> ; EltSize = <NUM_LIT> ; } else { Opcode = <STR_LIT> ; EltSize = <NUM_LIT> ; } if ( ! RI . isSGPRClass ( RI . getPhysRegClass ( SrcReg ) ) ) { reportIllegalCopy ( this , MBB , MI , DL , DestReg , SrcReg , KillSrc ) ; return ;


<s> BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MI . eraseFromParent ( ) ; break ; } case <STR_LIT> : { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MachineInstr * Copy = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; expandPostRAPseudo ( * Copy ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MI . eraseFromParent ( ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MCInstrDesc & MovRelDesc = get ( <STR_LIT> ) ; unsigned VecReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsUndef = MI . getOperand ( <NUM_LIT> ) . isUndef ( ) ; unsigned SubReg = <STR_LIT> + MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( VecReg == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineInstr * MovRel = BuildMI ( MBB , MI , DL , MovRelDesc ) . addReg ( RI . getSubReg ( VecReg , SubReg ) , RegState :: Undef ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( VecReg , RegState :: ImplicitDefine ) . addReg ( VecReg , RegState :: Implicit | ( IsUndef ? RegState :: Undef : <NUM_LIT> ) ) ; const int ImpDefIdx = MovRelDesc . getNumOperands ( ) + MovRelDesc . getNumImplicitUses ( ) ; const int ImpUseIdx = ImpDefIdx + <NUM_LIT> ; MovRel -> tieOperands ( ImpDefIdx , ImpUseIdx ) ; MI . eraseFromParent ( ) ; break ;


<s> } if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) { if ( hasAnyModifiersSet ( UseMI ) ) return false ; MachineOperand * Src0 = getNamedOperand ( UseMI , <STR_LIT> :: src0 ) ; if ( isInlineConstant ( UseMI , * Src0 , * ImmOp ) ) return false ; bool IsF32 = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; bool IsFMA = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; MachineOperand * Src1 = getNamedOperand ( UseMI , <STR_LIT> :: src1 ) ; MachineOperand * Src2 = getNamedOperand ( UseMI , <STR_LIT> :: src2 ) ; if ( Src0 -> isReg ( ) && Src0 -> getReg ( ) == Reg ) { if ( ! Src1 -> isReg ( ) || RI . isSGPRClass ( MRI -> getRegClass ( Src1 -> getReg ( ) ) ) ) return false ; if ( ! Src2 -> isReg ( ) || RI . isSGPRClass ( MRI -> getRegClass ( Src2 -> getReg ( ) ) ) ) return false ; unsigned NewOpc = IsFMA ? ( IsF32 ? <STR_LIT> : <STR_LIT> ) : ( IsF32 ? <STR_LIT> : <STR_LIT> ) ; if ( pseudoToMCOpcode ( NewOpc ) == - <NUM_LIT> ) return false ; const int64_t Imm = ImmOp -> getImm ( ) ; UseMI . RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: omod ) ) ; UseMI . RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: clamp ) ) ; unsigned Src1Reg = Src1 -> getReg ( ) ; unsigned Src1SubReg = Src1 -> getSubReg ( ) ; Src0 -> setReg ( Src1Reg ) ; Src0 -> setSubReg ( Src1SubReg ) ; Src0 -> setIsKill ( Src1 -> isKill ( ) ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) UseMI . untieRegOperand ( <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ) ; Src1 -> ChangeToImmediate ( Imm ) ; removeModOperands ( UseMI ) ; UseMI . setDesc ( get ( NewOpc ) ) ;

bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ;


<s> if ( ST . isAmdHsaOS ( ) ) { if ( ST . getGeneration ( ) <= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) RsrcDataFormat |= ( <NUM_LIT> << <NUM_LIT> ) ; if ( ST . getGeneration ( ) == <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) RsrcDataFormat |= ( <NUM_LIT> << <NUM_LIT> ) ; }


<s> uint64_t <ISA_LIT>InstrInfo :: getDefaultRsrcDataFormat ( ) const { if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) { return ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ; } uint64_t RsrcDataFormat = <STR_LIT> ;


<s> int Src0Idx = <STR_LIT> ( Opc , <STR_LIT> :: src0 ) ; if ( Src0Idx == - <NUM_LIT> ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src0Idx ) , Desc . OpInfo [ Src0Idx ] ) ) return isVOP3 ( MI ) ? <NUM_LIT> : ( DescSize + <NUM_LIT> ) ; int Src1Idx = <STR_LIT> ( Opc , <STR_LIT> :: src1 ) ; if ( Src1Idx == - <NUM_LIT> ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src1Idx ) , Desc . OpInfo [ Src1Idx ] ) ) return isVOP3 ( MI ) ? <NUM_LIT> : ( DescSize + <NUM_LIT> ) ; int Src2Idx = <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ; if ( Src2Idx == - <NUM_LIT> ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src2Idx ) , Desc . OpInfo [ Src2Idx ] ) ) return isVOP3 ( MI ) ? <NUM_LIT> : ( DescSize + <NUM_LIT> ) ; return DescSize ; } if ( isMIMG ( MI ) ) { int VAddr0Idx = <STR_LIT> ( Opc , <STR_LIT> :: vaddr0 ) ; if ( VAddr0Idx < <NUM_LIT> ) return <NUM_LIT> ; int RSrcIdx = <STR_LIT> ( Opc , <STR_LIT> :: srsrc ) ; return <NUM_LIT> + <NUM_LIT> * ( ( RSrcIdx - VAddr0Idx + <NUM_LIT> ) / <NUM_LIT> ) ; } switch ( Opc ) { case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : case TargetOpcode :: EH_LABEL : return <NUM_LIT> ; case TargetOpcode :: BUNDLE : return getInstBundleSize ( MI ) ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) , & MF -> getSubtarget ( ) ) ; } default : return DescSize ; }


<s> if ( VAddr0Idx < <NUM_LIT> ) return <NUM_LIT> ; int RSrcIdx = <STR_LIT> ( Opc , <STR_LIT> :: srsrc ) ; return <NUM_LIT> + <NUM_LIT> * ( ( RSrcIdx - VAddr0Idx + <NUM_LIT> ) / <NUM_LIT> ) ; } switch ( Opc ) { case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : case TargetOpcode :: EH_LABEL : return <NUM_LIT> ; case TargetOpcode :: BUNDLE : return getInstBundleSize ( MI ) ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) , & MF -> getSubtarget ( ) ) ;


<s> return false ; } if ( isMUBUF ( LdSt ) || isMTBUF ( LdSt ) ) { const MachineOperand * SOffset = getNamedOperand ( LdSt , <STR_LIT> :: soffset ) ; if ( SOffset && SOffset -> isReg ( ) ) return false ; const MachineOperand * AddrReg = getNamedOperand ( LdSt , <STR_LIT> :: vaddr ) ; if ( ! AddrReg ) return false ; const MachineOperand * OffsetImm = getNamedOperand ( LdSt , <STR_LIT> :: offset ) ; BaseOp = AddrReg ; Offset = OffsetImm -> getImm ( ) ; if ( SOffset ) Offset += SOffset -> getImm ( ) ; assert ( BaseOp -> isReg ( ) && <STR_LIT> <STR_LIT> ) ; return true ; } if ( isSMRD ( LdSt ) ) { const MachineOperand * OffsetImm = getNamedOperand ( LdSt , <STR_LIT> :: offset ) ; if ( ! OffsetImm ) return false ; const MachineOperand * SBaseReg = getNamedOperand ( LdSt , <STR_LIT> :: sbase ) ; BaseOp = SBaseReg ; Offset = OffsetImm -> getImm ( ) ; assert ( BaseOp -> isReg ( ) && <STR_LIT> <STR_LIT> ) ; return true ;


<s> uint64_t <ISA_LIT>InstrInfo :: getScratchRsrcWords23 ( ) const { uint64_t Rsrc23 = getDefaultRsrcDataFormat ( ) | <STR_LIT> | <NUM_LIT> ; if ( ST . getGeneration ( ) <= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { uint64_t EltSizeValue = Log2_32 ( ST . getMaxPrivateElementSize ( ) ) - <NUM_LIT> ; Rsrc23 |= EltSizeValue << <STR_LIT> ;


<s> uint64_t EltSizeValue = Log2_32 ( ST . getMaxPrivateElementSize ( ) ) - <NUM_LIT> ; Rsrc23 |= EltSizeValue << <STR_LIT> ; } uint64_t IndexStride = ST . getGeneration ( ) <= <ISA_LIT>Subtarget :: GFX9 ? <NUM_LIT> : <NUM_LIT> ; Rsrc23 |= IndexStride << <STR_LIT> ; if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS && ST . getGeneration ( ) <= <ISA_LIT>Subtarget :: GFX9 ) Rsrc23 &= ~ <STR_LIT> ;


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> :


<s> unsigned Opcode = MI . getOpcode ( ) ; if ( MI . mayStore ( ) && isSMRD ( MI ) ) return true ; if ( MI . isReturn ( ) ) return true ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ;

if ( MI . isCall ( ) || MI . isInlineAsm ( ) ) return true ;


<s> unsigned Opcode = MI . getOpcode ( ) ; if ( MI . mayStore ( ) && isSMRD ( MI ) ) return true ; if ( MI . isReturn ( ) ) return true ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; if ( MI . isCall ( ) || MI . isInlineAsm ( ) ) return true ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ;


<s> if ( BrOffset >= <NUM_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( PCReg , RegState :: Define , <STR_LIT> ) . addReg ( PCReg , <NUM_LIT> , <STR_LIT> ) . addMBB ( & DestBB , MO_LONG_BRANCH_FORWARD ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( PCReg , RegState :: Define , <STR_LIT> ) . addReg ( PCReg , <NUM_LIT> , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( PCReg , RegState :: Define , <STR_LIT> ) . addReg ( PCReg , <NUM_LIT> , <STR_LIT> ) . addMBB ( & DestBB , MO_LONG_BRANCH_BACKWARD ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( PCReg , RegState :: Define , <STR_LIT> ) . addReg ( PCReg , <NUM_LIT> , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addReg ( PCReg ) ; RS -> enterBasicBlockEnd ( MBB ) ; unsigned Scav = RS -> scavengeRegisterBackwards ( <STR_LIT> , MachineBasicBlock :: iterator ( GetPC ) , false , <NUM_LIT> ) ; MRI . replaceRegWith ( PCReg , Scav ) ; MRI . clearVirtRegs ( ) ; RS -> setRegUsed ( Scav ) ;


<s> static const int16_t Sub0_15 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; static const int16_t Sub0_15_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; unsigned SelOp = <STR_LIT> ; const TargetRegisterClass * EltRC = & <STR_LIT> ; const int16_t * SubIndices = Sub0_15 ; int NElts = DstSize / <NUM_LIT> ; if ( Pred == SCC_TRUE ) { if ( NElts % <NUM_LIT> ) { SelOp = <STR_LIT> ; EltRC = & <STR_LIT> ; } else { SelOp = <STR_LIT> ; EltRC = & <STR_LIT> ; SubIndices = Sub0_15_64 ; NElts /= <NUM_LIT> ; } } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) ; I = MIB -> getIterator ( ) ; SmallVector < unsigned , <NUM_LIT> > Regs ; for ( int Idx = <NUM_LIT> ; Idx != NElts ; ++ Idx ) {

unsigned DstElt = MRI . createVirtualRegister ( EltRC ) ;


<s> break ; } case <ISA_LIT>InstrInfo :: VCCNZ : { MachineOperand RegOp = Cond [ <NUM_LIT> ] ; RegOp . setImplicit ( false ) ; unsigned SReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , SReg ) . add ( RegOp ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( FalseReg ) . addImm ( <NUM_LIT> ) . addReg ( TrueReg ) . addReg ( SReg ) ; break ; } case <ISA_LIT>InstrInfo :: VCCZ : { MachineOperand RegOp = Cond [ <NUM_LIT> ] ; RegOp . setImplicit ( false ) ; unsigned SReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , SReg ) . add ( RegOp ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( TrueReg ) . addImm ( <NUM_LIT> ) . addReg ( FalseReg ) . addReg ( SReg ) ; break ; } case <ISA_LIT>InstrInfo :: EXECNZ : { unsigned SReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned SReg2 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , SReg2 ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , SReg ) . addImm ( - <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( FalseReg ) . addImm ( <NUM_LIT> ) . addReg ( TrueReg ) . addReg ( SReg ) ;


<s> auto * BB = DefI -> getParent ( ) ; DenseSet < MachineInstr * > Uses ; for ( auto & Use : MRI . use_nodbg_operands ( VReg ) ) { auto * I = Use . getParent ( ) ; if ( I -> getParent ( ) != BB ) return false ; Uses . insert ( I ) ; } auto E = BB -> end ( ) ; for ( auto I = std :: next ( DefI -> getIterator ( ) ) ; I != E ; ++ I ) { Uses . erase ( & * I ) ; if ( Uses . empty ( ) || I -> modifiesRegister ( <STR_LIT> , TRI ) ) break ; } return Uses . empty ( ) ;


<s> } auto E = BB -> end ( ) ; for ( auto I = std :: next ( DefI -> getIterator ( ) ) ; I != E ; ++ I ) { Uses . erase ( & * I ) ; if ( Uses . empty ( ) || I -> modifiesRegister ( <STR_LIT> , TRI ) ) break ; } return Uses . empty ( ) ;


<s> if ( MO . isImm ( ) && isInlineConstant ( MO , OpInfo ) ) return RI . opCanUseInlineConstant ( OpInfo . OperandType ) ; if ( ! RI . opCanUseLiteralConstant ( OpInfo . OperandType ) ) return false ; if ( ! isVOP3 ( MI ) || ! <STR_LIT> ( InstDesc , OpNo ) ) return true ;

const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( MO . getImm ( ) , ST . hasInv2PiInlineImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( isInt < <NUM_LIT> > ( Imm ) || isUInt < <NUM_LIT> > ( Imm ) ) { int16_t Trunc = static_cast < int16_t > ( Imm ) ; return ST . has16BitInsts ( ) && <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : { if ( isInt < <NUM_LIT> > ( Imm ) || isUInt < <NUM_LIT> > ( Imm ) ) { int16_t Trunc = static_cast < int16_t > ( Imm ) ; return ST . has16BitInsts ( ) && <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ; } return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { uint32_t Trunc = static_cast < uint32_t > ( Imm ) ; return <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ; }


<s> if ( isVOP3 ( MI ) && isLiteralConstantLike ( * MO , OpInfo ) && ! VOP3LiteralLimit -- ) return false ; SmallDenseSet < RegSubRegPair > SGPRsUsed ; if ( MO -> isReg ( ) ) SGPRsUsed . insert ( RegSubRegPair ( MO -> getReg ( ) , MO -> getSubReg ( ) ) ) ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { if ( i == OpIdx ) continue ; const MachineOperand & Op = MI . getOperand ( i ) ; if ( Op . isReg ( ) ) { RegSubRegPair SGPR ( Op . getReg ( ) , Op . getSubReg ( ) ) ; if ( ! SGPRsUsed . count ( SGPR ) && usesConstantBus ( MRI , Op , InstDesc . OpInfo [ i ] ) ) { if ( -- ConstantBusLimit <= <NUM_LIT> ) return false ; SGPRsUsed . insert ( SGPR ) ; } } else if ( InstDesc . OpInfo [ i ] . OperandType == <STR_LIT> ) { if ( -- ConstantBusLimit <= <NUM_LIT> ) return false ; } else if ( isVOP3 ( MI ) && <STR_LIT> ( InstDesc , i ) && isLiteralConstantLike ( Op , InstDesc . OpInfo [ i ] ) ) { if ( ! VOP3LiteralLimit -- ) return false ; if ( -- ConstantBusLimit <= <NUM_LIT> ) return false ;


<s> case <STR_LIT> : return MI . getNumOperands ( ) == MI . getDesc ( ) . getNumOperands ( ) ; default : return false ;


<s> const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( * MI . getParent ( ) , MI , DL , get ( <STR_LIT> ) , Reg ) . add ( Src1 ) ; Src1 . ChangeToRegister ( Reg , false ) ; } return ; } if ( isLegalRegOperand ( MRI , InstrDesc . OpInfo [ Src1Idx ] , Src1 ) ) return ; if ( Opc == <STR_LIT> && Src1 . isReg ( ) && RI . isVGPR ( MRI , Src1 . getReg ( ) ) ) { unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( * MI . getParent ( ) , MI , DL , get ( <STR_LIT> ) , Reg ) . add ( Src1 ) ; Src1 . ChangeToRegister ( Reg , false ) ; return ; } if ( HasImplicitSGPR || ! MI . isCommutable ( ) ) { legalizeOpWithMove ( MI , Src1Idx ) ; return ; } int Src0Idx = <STR_LIT> ( Opc , <STR_LIT> :: src0 ) ; MachineOperand & Src0 = MI . getOperand ( Src0Idx ) ; if ( ( ! Src1 . isImm ( ) && ! Src1 . isReg ( ) ) || ! isLegalRegOperand ( MRI , InstrDesc . OpInfo [ Src1Idx ] , Src0 ) ) { legalizeOpWithMove ( MI , Src1Idx ) ; return ; } int CommutedOpc = commuteOpcode ( MI ) ; if ( CommutedOpc == - <NUM_LIT> ) { legalizeOpWithMove ( MI , Src1Idx ) ; return ;


<s> MachineOperand & Src0 = MI . getOperand ( Src0Idx ) ; if ( Src0 . isReg ( ) && ( RI . isSGPRReg ( MRI , Src0 . getReg ( ) ) || isLiteralConstantLike ( Src0 , InstrDesc . OpInfo [ Src0Idx ] ) ) ) legalizeOpWithMove ( MI , Src0Idx ) ; } if ( Opc == <STR_LIT> ) { int Src0Idx = <STR_LIT> ( Opc , <STR_LIT> :: src0 ) ; MachineOperand & Src0 = MI . getOperand ( Src0Idx ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; if ( Src0 . isReg ( ) && RI . isVGPR ( MRI , Src0 . getReg ( ) ) ) { unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , DL , get ( <STR_LIT> ) , Reg ) . add ( Src0 ) ; Src0 . ChangeToRegister ( Reg , false ) ; } if ( Src1 . isReg ( ) && RI . isVGPR ( MRI , Src1 . getReg ( ) ) ) { unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( * MI . getParent ( ) , MI , DL , get ( <STR_LIT> ) , Reg ) . add ( Src1 ) ; Src1 . ChangeToRegister ( Reg , false ) ; } return ;


<s> const TargetRegisterClass * RC = RI . getRegClass ( RCID ) ; unsigned Size = TRI -> getRegSizeInBits ( * RC ) ; unsigned Opcode = ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( MO . isReg ( ) ) Opcode = <STR_LIT> ; else if ( RI . isSGPRClass ( RC ) ) Opcode = ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * VRC = RI . getEquivalentVGPRClass ( RC ) ;

if ( RI . getCommonSubClass ( & <STR_LIT> , VRC ) ) VRC = & <STR_LIT> ;


<s> if ( ( isMUBUF ( FirstLdSt ) && isMUBUF ( SecondLdSt ) ) || ( isMTBUF ( FirstLdSt ) && isMTBUF ( SecondLdSt ) ) || ( isFLAT ( FirstLdSt ) && isFLAT ( SecondLdSt ) ) ) { const unsigned MaxGlobalLoadCluster = <NUM_LIT> ; if ( NumLoads > MaxGlobalLoadCluster ) return false ; FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdata ) ; if ( ! FirstDst ) FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdata ) ; if ( ! SecondDst ) SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdst ) ; } else if ( isSMRD ( FirstLdSt ) && isSMRD ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: sdst ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: sdst ) ; } else if ( isDS ( FirstLdSt ) && isDS ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdst ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } return true ; } if ( <ISA_LIT>InstrInfo :: isGenericOpcode ( MI . getOpcode ( ) ) || <ISA_LIT>InstrInfo :: isSALU ( MI ) || <ISA_LIT>InstrInfo :: isSMRD ( MI ) ) return false ;


<s> const TargetRegisterClass * Src1RC = MRI . getRegClass ( Src1 . getReg ( ) ) ; const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; const TargetRegisterClass * Src1SubRC = RI . getSubRegClass ( Src1RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; unsigned LoOpc = IsAdd ? <STR_LIT> : <STR_LIT> ;

MachineInstr * LoHalf = BuildMI ( MBB , MII , DL , get ( LoOpc ) , DestSub0 ) . addReg ( CarryReg , RegState :: Define ) . add ( SrcReg0Sub0 ) . add ( SrcReg1Sub0 ) . addImm ( <NUM_LIT> ) ;


<s> MachineOperand & Src0 = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = Inst . getOperand ( <NUM_LIT> ) ; const DebugLoc & DL = Inst . getDebugLoc ( ) ; MachineBasicBlock :: iterator MII = Inst ; const TargetRegisterClass * Src0RC = MRI . getRegClass ( Src0 . getReg ( ) ) ; const TargetRegisterClass * Src1RC = MRI . getRegClass ( Src1 . getReg ( ) ) ; const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; const TargetRegisterClass * Src1SubRC = RI . getSubRegClass ( Src1RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; unsigned LoOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; MachineInstr * LoHalf = BuildMI ( MBB , MII , DL , get ( LoOpc ) , DestSub0 ) . addReg ( CarryReg , RegState :: Define ) . add ( SrcReg0Sub0 ) . add ( SrcReg1Sub0 ) . addImm ( <NUM_LIT> ) ; unsigned HiOpc = IsAdd ? <STR_LIT> : <STR_LIT> ;

MachineInstr * HiHalf = BuildMI ( MBB , MII , DL , get ( HiOpc ) , DestSub1 ) . addReg ( DeadCarryReg , RegState :: Define | RegState :: Dead ) . add ( SrcReg0Sub1 ) . add ( SrcReg1Sub1 ) . addReg ( CarryReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ;


<s> FrameInfo . setStackID ( FrameIndex , <STR_LIT> ) ; if ( ST . hasScalarStores ( ) ) { Spill . addReg ( <STR_LIT> , RegState :: ImplicitDefine | RegState :: Dead ) ; } return ; } assert ( RI . hasVGPRs ( RC ) && <STR_LIT> ) ; unsigned Opcode = getVGPRSpillSaveOpcode ( SpillSize ) ; MFI -> setHasSpilledVGPRs ( ) ; BuildMI ( MBB , MI , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI -> getStackPtrOffsetReg ( ) ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> if ( MO . isImplicit ( ) ) { return MO . getReg ( ) == <STR_LIT> || MO . getReg ( ) == <STR_LIT> || MO . getReg ( ) == <STR_LIT> ; } else { return <STR_LIT> . contains ( MO . getReg ( ) ) || <STR_LIT> . contains ( MO . getReg ( ) ) ;


<s> if ( MO . isImm ( ) ) return ! isInlineConstant ( MO , OpInfo ) ; if ( ! MO . isReg ( ) ) return true ; if ( ! MO . isUse ( ) ) return false ; if ( TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) return RI . isSGPRClass ( MRI . getRegClass ( MO . getReg ( ) ) ) ; if ( MO . getReg ( ) == <STR_LIT> ) return false ; if ( MO . isImplicit ( ) ) { return MO . getReg ( ) == <STR_LIT> || MO . getReg ( ) == <STR_LIT> || MO . getReg ( ) == <STR_LIT> ; } else {

return <STR_LIT> . contains ( MO . getReg ( ) ) || <STR_LIT> . contains ( MO . getReg ( ) ) ;


<s> void <ISA_LIT>InstrInfo :: addUsersToMoveToVALUWorklist ( Register DstReg , MachineRegisterInfo & MRI , SetVectorType & Worklist ) const { for ( MachineRegisterInfo :: use_iterator I = MRI . use_begin ( DstReg ) , E = MRI . use_end ( ) ; I != E ; ) { MachineInstr & UseMI = * I -> getParent ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : llvm_unreachable ( <STR_LIT> ) ; } ++ I ; } if ( I == E ) return false ; if ( I -> getOpcode ( ) != <STR_LIT> ) return analyzeBranchImpl ( MBB , I , TBB , FBB , Cond , AllowModify ) ; ++ I ;


<s> if ( Op32DstIdx != - <NUM_LIT> ) { Inst32 . add ( MI . getOperand ( <NUM_LIT> ) ) ; } else { assert ( ( ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; } Inst32 . add ( * getNamedOperand ( MI , <STR_LIT> :: src0 ) ) ; const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; if ( Src1 ) Inst32 . add ( * Src1 ) ; const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ; if ( Src2 ) { int Op32Src2Idx = <STR_LIT> ( Op32 , <STR_LIT> :: src2 ) ; if ( Op32Src2Idx != - <NUM_LIT> ) { Inst32 . add ( * Src2 ) ; } else {


<s> <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const DebugLoc & DL = MBB . findDebugLoc ( MI ) ; unsigned WorkGroupSize = MFI -> getMaxFlatWorkGroupSize ( ) ; unsigned WavefrontSize = ST . getWavefrontSize ( ) ; Register TIDReg = MFI -> getTIDReg ( ) ; if ( ! MFI -> hasCalculatedTID ( ) ) { MachineBasicBlock & Entry = MBB . getParent ( ) -> front ( ) ; MachineBasicBlock :: iterator Insert = Entry . front ( ) ; const DebugLoc & DL = Insert -> getDebugLoc ( ) ; TIDReg = RI . findUnusedRegister ( MF -> getRegInfo ( ) , & <STR_LIT> , * MF ) ; if ( TIDReg == <STR_LIT> ) return TIDReg ; if ( ! <STR_LIT> ( MF -> getFunction ( ) . getCallingConv ( ) ) && WorkGroupSize > WavefrontSize ) { Register TIDIGXReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; Register TIDIGYReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; Register TIDIGZReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; Register InputPtrReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; for ( unsigned Reg : { TIDIGXReg , TIDIGYReg , TIDIGZReg } ) {

if ( ! Entry . isLiveIn ( Reg ) ) Entry . addLiveIn ( Reg ) ;


<s> MachineBasicBlock :: iterator TI = LoopEnd -> getFirstTerminator ( ) ; assert ( TI != LoopEnd -> end ( ) ) ; MachineInstr * Branch = & ( * TI ) ; MachineFunction * MF = LoopEnd -> getParent ( ) ; MachineRegisterInfo & MRI = LoopEnd -> getParent ( ) -> getRegInfo ( ) ; if ( Branch -> getOpcode ( ) == <STR_LIT> ) { Register DstReg = MRI . createVirtualRegister ( RI . getBoolRC ( ) ) ; Register BackEdgeReg = MRI . createVirtualRegister ( RI . getBoolRC ( ) ) ; MachineInstrBuilder HeaderPHIBuilder = BuildMI ( * ( MF ) , Branch -> getDebugLoc ( ) , get ( TargetOpcode :: PHI ) , DstReg ) ; for ( MachineBasicBlock :: pred_iterator PI = LoopEntry -> pred_begin ( ) , E = LoopEntry -> pred_end ( ) ; PI != E ; ++ PI ) { if ( * PI == LoopEnd ) { HeaderPHIBuilder . addReg ( BackEdgeReg ) ; } else { MachineBasicBlock * PMBB = * PI ; Register ZeroReg = MRI . createVirtualRegister ( RI . getBoolRC ( ) ) ; materializeImmediate ( * PMBB , PMBB -> getFirstTerminator ( ) , DebugLoc ( ) , ZeroReg , <NUM_LIT> ) ; HeaderPHIBuilder . addReg ( ZeroReg ) ; } HeaderPHIBuilder . addMBB ( * PI ) ; } MachineInstr * HeaderPhi = HeaderPHIBuilder ; MachineInstr * <ISA_LIT>IFBREAK = BuildMI ( * ( MF ) , Branch -> getDebugLoc ( ) , get ( <STR_LIT> ) , BackEdgeReg ) . addReg ( DstReg ) . add ( Branch -> getOperand ( <NUM_LIT> ) ) ; MachineInstr * <ISA_LIT>LOOP = BuildMI ( * ( MF ) , Branch -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( BackEdgeReg ) . addMBB ( LoopEntry ) ; LoopEntry -> insert ( LoopEntry -> begin ( ) , HeaderPhi ) ; LoopEnd -> erase ( TI ) ; LoopEnd -> insert ( LoopEnd -> end ( ) , <ISA_LIT>IFBREAK ) ; LoopEnd -> insert ( LoopEnd -> end ( ) , <ISA_LIT>LOOP ) ;


<s> Register VRsrc = Rsrc . getReg ( ) ; unsigned VRsrcUndef = getUndefRegState ( Rsrc . isUndef ( ) ) ; unsigned RegSize = TRI -> getRegSizeInBits ( Rsrc . getReg ( ) , MRI ) ; unsigned NumSubRegs = RegSize / <NUM_LIT> ; assert ( NumSubRegs % <NUM_LIT> == <NUM_LIT> && NumSubRegs <= <NUM_LIT> && <STR_LIT> ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < NumSubRegs ; Idx += <NUM_LIT> ) { Register CurRegLo = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register CurRegHi = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , CurRegLo ) . addReg ( VRsrc , VRsrcUndef , TRI -> getSubRegFromChannel ( Idx ) ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , CurRegHi ) . addReg ( VRsrc , VRsrcUndef , TRI -> getSubRegFromChannel ( Idx + <NUM_LIT> ) ) ; ReadlanePieces . push_back ( CurRegLo ) ; ReadlanePieces . push_back ( CurRegHi ) ; Register CurReg = MRI . createVirtualRegister ( & <STR_LIT> ) ;

BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , CurReg ) . addReg ( CurRegLo ) . addImm ( <STR_LIT> ) . addReg ( CurRegHi ) . addImm ( <STR_LIT> ) ;


<s> BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , CurReg ) . addReg ( CurRegLo ) . addImm ( <STR_LIT> ) . addReg ( CurRegHi ) . addImm ( <STR_LIT> ) ; Register NewCondReg = MRI . createVirtualRegister ( BoolXExecRC ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , NewCondReg ) . addReg ( CurReg ) . addReg ( VRsrc , VRsrcUndef , TRI -> getSubRegFromChannel ( Idx , <NUM_LIT> ) ) ; if ( CondReg == <STR_LIT> ) CondReg = NewCondReg ; else { Register AndReg = MRI . createVirtualRegister ( BoolXExecRC ) ; BuildMI ( LoopBB , I , DL , TII . get ( AndOpc ) , AndReg ) . addReg ( CondReg ) . addReg ( NewCondReg ) ; CondReg = AndReg ; } } auto SRsrcRC = TRI -> getEquivalentSGPRClass ( MRI . getRegClass ( VRsrc ) ) ; Register SRsrc = MRI . createVirtualRegister ( SRsrcRC ) ; auto Merge = BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrc ) ; unsigned Channel = <NUM_LIT> ; for ( Register Piece : ReadlanePieces ) { Merge . addReg ( Piece ) . addImm ( TRI -> getSubRegFromChannel ( Channel ++ ) ) ; } Rsrc . setReg ( SRsrc ) ; Rsrc . setIsKill ( true ) ; Register SaveExec = MRI . createVirtualRegister ( BoolXExecRC ) ; MRI . setSimpleHint ( SaveExec , CondReg ) ; BuildMI ( LoopBB , I , DL , TII . get ( SaveExecOpc ) , SaveExec ) . addReg ( CondReg , RegState :: Kill ) ; I = LoopBB . end ( ) ;

BuildMI ( LoopBB , I , DL , TII . get ( XorTermOpc ) , Exec ) . addReg ( Exec ) . addReg ( SaveExec ) ;


<s> bool llvm :: execMayBeModifiedBeforeAnyUse ( const MachineRegisterInfo & MRI , Register VReg , const MachineInstr & DefMI ) { assert ( MRI . isSSA ( ) && <STR_LIT> ) ; auto * TRI = MRI . getTargetRegisterInfo ( ) ; auto * DefBB = DefMI . getParent ( ) ; const int MaxUseInstScan = <NUM_LIT> ; int NumUseInst = <NUM_LIT> ; for ( auto & UseInst : MRI . use_nodbg_instructions ( VReg ) ) {

if ( UseInst . getParent ( ) != DefBB ) return true ;


<s> for ( auto & UseInst : MRI . use_nodbg_instructions ( VReg ) ) { if ( UseInst . getParent ( ) != DefBB ) return true ; if ( ++ NumUseInst > MaxUseInstScan ) return true ; } const int MaxInstScan = <NUM_LIT> ; int NumInst = <NUM_LIT> ;

for ( auto I = std :: next ( DefMI . getIterator ( ) ) ; ; ++ I ) {


<s> if ( Opc == <STR_LIT> ) { Register DstReg = UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Is16Bit = getOpSize ( UseMI , <NUM_LIT> ) == <NUM_LIT> ; bool isVGPRCopy = RI . isVGPR ( * MRI , DstReg ) ; unsigned NewOpc = isVGPRCopy ? <STR_LIT> : <STR_LIT> ; APInt Imm ( <NUM_LIT> , ImmOp -> getImm ( ) ) ; if ( UseMI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <STR_LIT> ) Imm = Imm . ashr ( <NUM_LIT> ) ; if ( RI . isAGPR ( * MRI , DstReg ) ) { if ( ! isInlineConstant ( Imm ) ) return false ; NewOpc = <STR_LIT> ; } if ( Is16Bit ) { if ( isVGPRCopy ) return false ; if ( DstReg . isVirtual ( ) && UseMI . getOperand ( <NUM_LIT> ) . getSubReg ( ) != <STR_LIT> ) return false ; UseMI . getOperand ( <NUM_LIT> ) . setSubReg ( <NUM_LIT> ) ; if ( DstReg . isPhysical ( ) ) { DstReg = RI . get32BitRegister ( DstReg ) ; UseMI . getOperand ( <NUM_LIT> ) . setReg ( DstReg ) ; } assert ( UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) . isVirtual ( ) ) ; } UseMI . setDesc ( get ( NewOpc ) ) ; UseMI . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( Imm . getSExtValue ( ) ) ; UseMI . addImplicitDefUseOperands ( * UseMI . getParent ( ) -> getParent ( ) ) ; return true ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) { if ( hasAnyModifiersSet ( UseMI ) ) return false ; MachineOperand * Src0 = getNamedOperand ( UseMI , <STR_LIT> :: src0 ) ; if ( isInlineConstant ( UseMI , * Src0 , * ImmOp ) ) return false ; bool IsF32 = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; bool IsFMA = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; MachineOperand * Src1 = getNamedOperand ( UseMI , <STR_LIT> :: src1 ) ; MachineOperand * Src2 = getNamedOperand ( UseMI , <STR_LIT> :: src2 ) ; if ( Src0 -> isReg ( ) && Src0 -> getReg ( ) == Reg ) { if ( ! Src1 -> isReg ( ) || RI . isSGPRClass ( MRI -> getRegClass ( Src1 -> getReg ( ) ) ) ) return false ; if ( ! Src2 -> isReg ( ) || RI . isSGPRClass ( MRI -> getRegClass ( Src2 -> getReg ( ) ) ) ) return false ; unsigned NewOpc = IsFMA ? ( IsF32 ? <STR_LIT> : <STR_LIT> ) : ( IsF32 ? <STR_LIT> : <STR_LIT> ) ;

if ( pseudoToMCOpcode ( NewOpc ) == - <NUM_LIT> ) return false ;


<s> switch ( Size ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> :


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> :


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ;


<s> if ( ST . isAmdHsaOS ( ) ) { if ( ST . getGeneration ( ) <= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) RsrcDataFormat |= ( <NUM_LIT> << <NUM_LIT> ) ; if ( ST . getGeneration ( ) == <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) RsrcDataFormat |= ( <NUM_LIT> << <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const TargetRegisterClass * SrcRC = getOpRegClass ( Inst , <NUM_LIT> ) ; if ( RI . hasAGPRs ( SrcRC ) ) { if ( RI . hasAGPRs ( NewDstRC ) ) return nullptr ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NewDstRC = RI . getEquivalentAGPRClass ( NewDstRC ) ; break ; default : NewDstRC = RI . getEquivalentVGPRClass ( NewDstRC ) ;


<s> const TargetRegisterClass * <ISA_LIT>InstrInfo :: getDestEquivalentVGPRClass ( const MachineInstr & Inst ) const { const TargetRegisterClass * NewDstRC = getOpRegClass ( Inst , <NUM_LIT> ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const TargetRegisterClass * SrcRC = getOpRegClass ( Inst , <NUM_LIT> ) ; if ( RI . hasAGPRs ( SrcRC ) ) { if ( RI . hasAGPRs ( NewDstRC ) ) return nullptr ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NewDstRC = RI . getEquivalentAGPRClass ( NewDstRC ) ; break ; default : NewDstRC = RI . getEquivalentVGPRClass ( NewDstRC ) ; } if ( ! NewDstRC ) return nullptr ; } else { if ( RI . hasVGPRs ( NewDstRC ) || NewDstRC == & <STR_LIT> ) return nullptr ; NewDstRC = RI . getEquivalentVGPRClass ( NewDstRC ) ; if ( ! NewDstRC ) return nullptr ; } return NewDstRC ; }


<s> return get ( getIndirectSGPRWritePseudo32 ( VecSize ) ) ; case <NUM_LIT> : return get ( getIndirectSGPRWritePseudo64 ( VecSize ) ) ; default :


<s> if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ;


if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ;


<s> if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ;


<s> if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ;


<s> if ( isFixedSize ( MI ) ) return DescSize ; if ( isVALU ( MI ) || isSALU ( MI ) ) { int Src0Idx = <STR_LIT> ( Opc , <STR_LIT> :: src0 ) ; if ( Src0Idx == - <NUM_LIT> ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src0Idx ) , Desc . OpInfo [ Src0Idx ] ) ) return isVOP3 ( MI ) ? <NUM_LIT> : ( DescSize + <NUM_LIT> ) ; int Src1Idx = <STR_LIT> ( Opc , <STR_LIT> :: src1 ) ; if ( Src1Idx == - <NUM_LIT> ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src1Idx ) , Desc . OpInfo [ Src1Idx ] ) ) return isVOP3 ( MI ) ? <NUM_LIT> : ( DescSize + <NUM_LIT> ) ; int Src2Idx = <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ; if ( Src2Idx == - <NUM_LIT> ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src2Idx ) , Desc . OpInfo [ Src2Idx ] ) ) return isVOP3 ( MI ) ? <NUM_LIT> : ( DescSize + <NUM_LIT> ) ; return DescSize ; } if ( isMIMG ( MI ) ) { int VAddr0Idx = <STR_LIT> ( Opc , <STR_LIT> :: vaddr0 ) ; if ( VAddr0Idx < <NUM_LIT> ) return <NUM_LIT> ; int RSrcIdx = <STR_LIT> ( Opc , <STR_LIT> :: srsrc ) ; return <NUM_LIT> + <NUM_LIT> * ( ( RSrcIdx - VAddr0Idx + <NUM_LIT> ) / <NUM_LIT> ) ; } switch ( Opc ) { case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL :


<s> if ( isFixedSize ( MI ) ) return DescSize ; if ( isVALU ( MI ) || isSALU ( MI ) ) { int Src0Idx = <STR_LIT> ( Opc , <STR_LIT> :: src0 ) ; if ( Src0Idx == - <NUM_LIT> ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src0Idx ) , Desc . OpInfo [ Src0Idx ] ) ) return isVOP3 ( MI ) ? <NUM_LIT> : ( DescSize + <NUM_LIT> ) ; int Src1Idx = <STR_LIT> ( Opc , <STR_LIT> :: src1 ) ; if ( Src1Idx == - <NUM_LIT> ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src1Idx ) , Desc . OpInfo [ Src1Idx ] ) ) return isVOP3 ( MI ) ? <NUM_LIT> : ( DescSize + <NUM_LIT> ) ; int Src2Idx = <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ; if ( Src2Idx == - <NUM_LIT> ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src2Idx ) , Desc . OpInfo [ Src2Idx ] ) ) return isVOP3 ( MI ) ? <NUM_LIT> : ( DescSize + <NUM_LIT> ) ; return DescSize ; } if ( isMIMG ( MI ) ) { int VAddr0Idx = <STR_LIT> ( Opc , <STR_LIT> :: vaddr0 ) ; if ( VAddr0Idx < <NUM_LIT> ) return <NUM_LIT> ; int RSrcIdx = <STR_LIT> ( Opc , <STR_LIT> :: srsrc ) ; return <NUM_LIT> + <NUM_LIT> * ( ( RSrcIdx - VAddr0Idx + <NUM_LIT> ) / <NUM_LIT> ) ; } switch ( Opc ) { case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : case TargetOpcode :: EH_LABEL : return <NUM_LIT> ; case TargetOpcode :: BUNDLE : return getInstBundleSize ( MI ) ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) , & ST ) ; }


<s> unsigned <ISA_LIT>InstrInfo :: getNumFlatOffsetBits ( bool Signed ) const { if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) return Signed ? <NUM_LIT> : <NUM_LIT> ; return Signed ? <NUM_LIT> : <NUM_LIT> ;


<s> const TargetRegisterClass * <ISA_LIT>InstrInfo :: getOpRegClass ( const MachineInstr & MI , unsigned OpNo ) const { const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const MCInstrDesc & Desc = get ( MI . getOpcode ( ) ) ; if ( MI . isVariadic ( ) || OpNo >= Desc . getNumOperands ( ) || Desc . OpInfo [ OpNo ] . RegClass == - <NUM_LIT> ) { Register Reg = MI . getOperand ( OpNo ) . getReg ( ) ; if ( Reg . isVirtual ( ) ) return MRI . getRegClass ( Reg ) ;


<s> if ( ST . getGeneration ( ) <= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { uint64_t EltSizeValue = Log2_32 ( ST . getMaxPrivateElementSize ( ) ) - <NUM_LIT> ; Rsrc23 |= EltSizeValue << <STR_LIT> ;


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ;


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ;


<s> const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; return MI . getOperand ( <NUM_LIT> ) . isReg ( ) || RI . isAGPR ( MRI , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ? <STR_LIT> : <STR_LIT> ; } case <STR_LIT> : return ST . hasAddNoCarry ( ) ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return ST . hasAddNoCarry ( ) ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return ST . hasDLInsts ( ) ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> :


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ;


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: hasUnwantedEffectsWhenEXECEmpty ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( MI . mayStore ( ) && isSMRD ( MI ) ) return true ;


<s> if ( MI . isReturn ( ) ) return true ;

if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ;


<s> RS . setRegUsed ( Tmp ) ; while ( RegNo -- && RS . FindUnusedReg ( & <STR_LIT> ) ) { Register Tmp2 = RS . scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; if ( ! Tmp2 || RI . getHWRegIndex ( Tmp2 ) >= MaxVGPRs ) break ; Tmp = Tmp2 ; RS . setRegUsed ( Tmp ) ; } unsigned TmpCopyOp = <STR_LIT> ; if ( <STR_LIT> . contains ( SrcReg ) ) { TmpCopyOp = <STR_LIT> ; } else { assert ( <STR_LIT> . contains ( SrcReg ) ) ; } MachineInstrBuilder UseBuilder = BuildMI ( MBB , MI , DL , TII . get ( TmpCopyOp ) , Tmp ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; if ( ImpUseSuperReg ) { UseBuilder . addReg ( ImpUseSuperReg , getKillRegState ( KillSrc ) | RegState :: Implicit ) ; } MachineInstrBuilder DefBuilder = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( Tmp , RegState :: Kill ) ; if ( ImpDefSuperReg ) DefBuilder . addReg ( ImpDefSuperReg , RegState :: Define | RegState :: Implicit ) ;


<s> if ( BytesAdded ) * BytesAdded = <NUM_LIT> ; return <NUM_LIT> ; } assert ( TBB && FBB ) ; MachineInstr * CondBr = BuildMI ( & MBB , DL , get ( Opcode ) ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; MachineOperand & CondReg = CondBr -> getOperand ( <NUM_LIT> ) ; CondReg . setIsUndef ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; CondReg . setIsKill ( Cond [ <NUM_LIT> ] . isKill ( ) ) ; if ( BytesAdded ) * BytesAdded = <NUM_LIT> ;


<s> } else { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( PCReg , RegState :: Define , <STR_LIT> ) . addReg ( PCReg , <NUM_LIT> , <STR_LIT> ) . addMBB ( & DestBB , MO_LONG_BRANCH_BACKWARD ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( PCReg , RegState :: Define , <STR_LIT> ) . addReg ( PCReg , <NUM_LIT> , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addReg ( PCReg ) ; RS -> enterBasicBlockEnd ( MBB ) ;

Register Scav = RS -> scavengeRegisterBackwards ( <STR_LIT> , MachineBasicBlock :: iterator ( GetPC ) , false , <NUM_LIT> ) ;


<s> auto I = MBB . end ( ) ; MachineInstr * GetPC = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , PCReg ) ; if ( BrOffset >= <NUM_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( PCReg , RegState :: Define , <STR_LIT> ) . addReg ( PCReg , <NUM_LIT> , <STR_LIT> ) . addMBB ( & DestBB , MO_LONG_BRANCH_FORWARD ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( PCReg , RegState :: Define , <STR_LIT> ) . addReg ( PCReg , <NUM_LIT> , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } else {

BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( PCReg , RegState :: Define , <STR_LIT> ) . addReg ( PCReg , <NUM_LIT> , <STR_LIT> ) . addMBB ( & DestBB , MO_LONG_BRANCH_BACKWARD ) ;


<s> unsigned NumOps = MI . getDesc ( ) . getNumOperands ( ) + MI . getDesc ( ) . getNumImplicitUses ( ) ; return MI . getNumOperands ( ) == NumOps ;


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumOps = MI . getDesc ( ) . getNumOperands ( ) + MI . getDesc ( ) . getNumImplicitUses ( ) ; return MI . getNumOperands ( ) == NumOps ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>InstrInfo :: isInlineConstant ( const MachineOperand & MO , uint8_t OperandType ) const { if ( ! MO . isImm ( ) || OperandType < <STR_LIT> || OperandType > <STR_LIT> ) return false ; int64_t Imm = MO . getImm ( ) ; switch ( OperandType ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { int32_t Trunc = static_cast < int32_t > ( Imm ) ; return <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( MO . getImm ( ) , ST . hasInv2PiInlineImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( Imm ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( Imm ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( isInt < <NUM_LIT> > ( Imm ) || isUInt < <NUM_LIT> > ( Imm ) ) { int16_t Trunc = static_cast < int16_t > ( Imm ) ; return ST . has16BitInsts ( ) && <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ; } return false ; } case <STR_LIT> : case <STR_LIT> :


<s> if ( ! ST . hasFlatInstOffsets ( ) ) return false ; if ( ST . hasFlatSegmentOffsetBug ( ) && AddrSpace == <ISA_LIT>AS :: FLAT_ADDRESS ) return false ; if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) return Signed ? isInt < <NUM_LIT> > ( Offset ) : isUInt < <NUM_LIT> > ( Offset ) ;


<s> if ( ST . hasFlatSegmentOffsetBug ( ) && AddrSpace == <ISA_LIT>AS :: FLAT_ADDRESS ) return false ; if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) return Signed ? isInt < <NUM_LIT> > ( Offset ) : isUInt < <NUM_LIT> > ( Offset ) ; return Signed ? isInt < <NUM_LIT> > ( Offset ) : isUInt < <NUM_LIT> > ( Offset ) ;


<s> Register Reg = MO . getReg ( ) ; const TargetRegisterClass * RC = Reg . isVirtual ( ) ? MRI . getRegClass ( Reg ) : RI . getPhysRegClass ( Reg ) ; const TargetRegisterClass * DRC = RI . getRegClass ( OpInfo . RegClass ) ; if ( MO . getSubReg ( ) ) { const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const TargetRegisterClass * SuperRC = RI . getLargestLegalSuperClass ( RC , * MF ) ; if ( ! SuperRC ) return false ; DRC = RI . getMatchingSuperRegClass ( SuperRC , DRC , MO . getSubReg ( ) ) ; if ( ! DRC ) return false ; } return RC -> hasSuperClassEq ( DRC ) ;


<s> bool <ISA_LIT>InstrInfo :: isLegalRegOperand ( const MachineRegisterInfo & MRI , const MCOperandInfo & OpInfo , const MachineOperand & MO ) const { if ( ! MO . isReg ( ) ) return false ; Register Reg = MO . getReg ( ) ; const TargetRegisterClass * RC = Reg . isVirtual ( ) ? MRI . getRegClass ( Reg ) : RI . getPhysRegClass ( Reg ) ; const TargetRegisterClass * DRC = RI . getRegClass ( OpInfo . RegClass ) ; if ( MO . getSubReg ( ) ) { const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const TargetRegisterClass * SuperRC = RI . getLargestLegalSuperClass ( RC , * MF ) ;


<s> const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const MCInstrDesc & InstDesc = MI . getDesc ( ) ; const MCOperandInfo & OpInfo = InstDesc . OpInfo [ OpIdx ] ; const TargetRegisterClass * DefinedRC = OpInfo . RegClass != - <NUM_LIT> ? RI . getRegClass ( OpInfo . RegClass ) : nullptr ; if ( ! MO ) MO = & MI . getOperand ( OpIdx ) ; int ConstantBusLimit = ST . getConstantBusLimit ( MI . getOpcode ( ) ) ; int VOP3LiteralLimit = ST . hasVOP3Literal ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( isVALU ( MI ) && usesConstantBus ( MRI , * MO , OpInfo ) ) { if ( isVOP3 ( MI ) && isLiteralConstantLike ( * MO , OpInfo ) && ! VOP3LiteralLimit -- ) return false ; SmallDenseSet < RegSubRegPair > SGPRsUsed ; if ( MO -> isReg ( ) ) SGPRsUsed . insert ( RegSubRegPair ( MO -> getReg ( ) , MO -> getSubReg ( ) ) ) ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { if ( i == OpIdx ) continue ; const MachineOperand & Op = MI . getOperand ( i ) ; if ( Op . isReg ( ) ) { RegSubRegPair SGPR ( Op . getReg ( ) , Op . getSubReg ( ) ) ; if ( ! SGPRsUsed . count ( SGPR ) && usesConstantBus ( MRI , Op , InstDesc . OpInfo [ i ] ) ) { if ( -- ConstantBusLimit <= <NUM_LIT> ) return false ; SGPRsUsed . insert ( SGPR ) ; }

} else if ( InstDesc . OpInfo [ i ] . OperandType == <STR_LIT> ) {


<s> int VOP3LiteralLimit = ST . hasVOP3Literal ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( isVALU ( MI ) && usesConstantBus ( MRI , * MO , OpInfo ) ) { if ( isVOP3 ( MI ) && isLiteralConstantLike ( * MO , OpInfo ) && ! VOP3LiteralLimit -- ) return false ; SmallDenseSet < RegSubRegPair > SGPRsUsed ; if ( MO -> isReg ( ) ) SGPRsUsed . insert ( RegSubRegPair ( MO -> getReg ( ) , MO -> getSubReg ( ) ) ) ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { if ( i == OpIdx ) continue ; const MachineOperand & Op = MI . getOperand ( i ) ; if ( Op . isReg ( ) ) { RegSubRegPair SGPR ( Op . getReg ( ) , Op . getSubReg ( ) ) ; if ( ! SGPRsUsed . count ( SGPR ) && usesConstantBus ( MRI , Op , InstDesc . OpInfo [ i ] ) ) { if ( -- ConstantBusLimit <= <NUM_LIT> ) return false ; SGPRsUsed . insert ( SGPR ) ; } } else if ( InstDesc . OpInfo [ i ] . OperandType == <STR_LIT> ) { if ( -- ConstantBusLimit <= <NUM_LIT> ) return false ; } else if ( isVOP3 ( MI ) && <STR_LIT> ( InstDesc , i ) && isLiteralConstantLike ( Op , InstDesc . OpInfo [ i ] ) ) { if ( ! VOP3LiteralLimit -- ) return false ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MI . getNumOperands ( ) == MI . getDesc ( ) . getNumOperands ( ) ; default : return false ;


<s> Op . setReg ( DstReg ) ; Op . setSubReg ( <NUM_LIT> ) ; MachineInstr * Def = MRI . getVRegDef ( OpReg ) ; if ( ! Def ) return ; if ( Def -> isMoveImmediate ( ) && DstRC != & <STR_LIT> ) FoldImmediate ( * Copy , * Def , OpReg , & MRI ) ; bool ImpDef = Def -> isImplicitDef ( ) ; while ( ! ImpDef && Def && Def -> isCopy ( ) ) { if ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) . isPhysical ( ) ) break ;

Def = MRI . getUniqueVRegDef ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> MachineOperand * SAddr = getNamedOperand ( MI , <STR_LIT> :: saddr ) ;

if ( ! SAddr || RI . isSGPRClass ( MRI . getRegClass ( SAddr -> getReg ( ) ) ) ) return ;


<s> BuildMI ( * MI . getParent ( ) , MI , DL , get ( <STR_LIT> ) , Reg ) . add ( Src2 ) ; Src2 . ChangeToRegister ( Reg , false ) ; } } int ConstantBusLimit = ST . getConstantBusLimit ( Opc ) ; int LiteralLimit = ST . hasVOP3Literal ( ) ? <NUM_LIT> : <NUM_LIT> ; SmallDenseSet < unsigned > SGPRsUsed ; Register SGPRReg = findUsedSGPR ( MI , VOP3Idx ) ; if ( SGPRReg != <STR_LIT> ) { SGPRsUsed . insert ( SGPRReg ) ; -- ConstantBusLimit ; } for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { int Idx = VOP3Idx [ i ] ; if ( Idx == - <NUM_LIT> ) break ; MachineOperand & MO = MI . getOperand ( Idx ) ; if ( ! MO . isReg ( ) ) { if ( ! isLiteralConstantLike ( MO , get ( Opc ) . OpInfo [ Idx ] ) ) continue ; if ( LiteralLimit > <NUM_LIT> && ConstantBusLimit > <NUM_LIT> ) { -- LiteralLimit ; -- ConstantBusLimit ; continue ; } -- LiteralLimit ; -- ConstantBusLimit ; legalizeOpWithMove ( MI , Idx ) ; continue ;


<s> Register Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , DL , get ( <STR_LIT> ) , Reg ) . add ( Src2 ) ; Src2 . ChangeToRegister ( Reg , false ) ; } } int ConstantBusLimit = ST . getConstantBusLimit ( Opc ) ; int LiteralLimit = ST . hasVOP3Literal ( ) ? <NUM_LIT> : <NUM_LIT> ; SmallDenseSet < unsigned > SGPRsUsed ; Register SGPRReg = findUsedSGPR ( MI , VOP3Idx ) ; if ( SGPRReg != <STR_LIT> ) { SGPRsUsed . insert ( SGPRReg ) ; -- ConstantBusLimit ; } for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { int Idx = VOP3Idx [ i ] ; if ( Idx == - <NUM_LIT> ) break ; MachineOperand & MO = MI . getOperand ( Idx ) ; if ( ! MO . isReg ( ) ) { if ( ! isLiteralConstantLike ( MO , get ( Opc ) . OpInfo [ Idx ] ) ) continue ; if ( LiteralLimit > <NUM_LIT> && ConstantBusLimit > <NUM_LIT> ) { -- LiteralLimit ; -- ConstantBusLimit ; continue ; } -- LiteralLimit ; -- ConstantBusLimit ; legalizeOpWithMove ( MI , Idx ) ; continue ; } if ( RI . hasAGPRs ( MRI . getRegClass ( MO . getReg ( ) ) ) && ! isOperandLegal ( MI , Idx , & MO ) ) { legalizeOpWithMove ( MI , Idx ) ; continue ;


<s> if ( MO . isReg ( ) ) Opcode = <STR_LIT> ; else if ( RI . isSGPRClass ( RC ) ) Opcode = ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * VRC = RI . getEquivalentVGPRClass ( RC ) ; if ( RI . getCommonSubClass ( & <STR_LIT> , VRC ) ) VRC = & <STR_LIT> ; else VRC = & <STR_LIT> ; Register Reg = MRI . createVirtualRegister ( VRC ) ; DebugLoc DL = MBB -> findDebugLoc ( I ) ;

BuildMI ( * MI . getParent ( ) , I , DL , get ( Opcode ) , Reg ) . add ( MO ) ;


<s> if ( RI . spillSGPRToVGPR ( ) ) FrameInfo . setStackID ( FrameIndex , TargetStackID :: SGPRSpill ) ; BuildMI ( MBB , MI , DL , OpDesc , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getStackPtrOffsetReg ( ) , RegState :: Implicit ) ; return ; } unsigned Opcode = RI . hasAGPRs ( RC ) ? getAGPRSpillRestoreOpcode ( SpillSize ) : getVGPRSpillRestoreOpcode ( SpillSize ) ; BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) . addFrameIndex ( FrameIndex ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI -> getStackPtrOffsetReg ( ) ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> MachineBasicBlock :: iterator I ( & MI ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned Exec = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned MovExecOpc = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; const auto * BoolXExecRC = TRI -> getRegClass ( <STR_LIT> ) ; Register SaveExec = MRI . createVirtualRegister ( BoolXExecRC ) ; BuildMI ( MBB , I , DL , TII . get ( MovExecOpc ) , SaveExec ) . addReg ( Exec ) ; for ( auto & MO : MI . uses ( ) ) { if ( MO . isReg ( ) && MO . isUse ( ) ) { MRI . clearKillFlags ( MO . getReg ( ) ) ; } } MachineBasicBlock * LoopBB = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * RemainderBB = MF . CreateMachineBasicBlock ( ) ; MachineFunction :: iterator MBBI ( MBB ) ; ++ MBBI ; MF . insert ( MBBI , LoopBB ) ; MF . insert ( MBBI , RemainderBB ) ; LoopBB -> addSuccessor ( LoopBB ) ; LoopBB -> addSuccessor ( RemainderBB ) ; MachineBasicBlock :: iterator J = I ++ ; RemainderBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; RemainderBB -> splice ( RemainderBB -> begin ( ) , & MBB , I , MBB . end ( ) ) ;

LoopBB -> splice ( LoopBB -> begin ( ) , & MBB , J ) ;


<s> for ( MachineInstr & CandI : make_range ( std :: next ( MachineBasicBlock :: reverse_iterator ( Inst ) ) , Inst . getParent ( ) -> rend ( ) ) ) { if ( CandI . findRegisterDefOperandIdx ( <STR_LIT> , false , false , & RI ) != - <NUM_LIT> ) { if ( CandI . isCopy ( ) && CandI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { SCCSource = CandI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; } } } if ( ( SCCSource != <STR_LIT> ) && Src0 . isImm ( ) && ( Src0 . getImm ( ) == - <NUM_LIT> ) && Src1 . isImm ( ) && ( Src1 . getImm ( ) == <NUM_LIT> ) ) { MRI . replaceRegWith ( Dest . getReg ( ) , SCCSource ) ; return ; } const TargetRegisterClass * TC = ST . getWavefrontSize ( ) == <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ; Register CopySCC = MRI . createVirtualRegister ( TC ) ; if ( SCCSource == <STR_LIT> ) { unsigned Opcode = ( ST . getWavefrontSize ( ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; auto NewSelect = BuildMI ( MBB , MII , DL , get ( Opcode ) , CopySCC ) . addImm ( - <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; NewSelect -> getOperand ( <NUM_LIT> ) . setIsUndef ( Cond . isUndef ( ) ) ;


<s> if ( RegClass == & <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( Value ) ; return ; } if ( RegClass == & <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( Value ) ; return ; } unsigned EltSize = <NUM_LIT> ; unsigned Opcode = <STR_LIT> ; if ( RI . isSGPRClass ( RegClass ) ) { if ( RI . getRegSizeInBits ( * RegClass ) > <NUM_LIT> ) { Opcode = <STR_LIT> ; EltSize = <NUM_LIT> ; } else { Opcode = <STR_LIT> ; EltSize = <NUM_LIT> ; } } ArrayRef < int16_t > SubIndices = RI . getRegSplitParts ( RegClass , EltSize ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < SubIndices . size ( ) ; ++ Idx ) { int64_t IdxValue = Idx == <NUM_LIT> ? Value : <NUM_LIT> ; MachineInstrBuilder Builder = BuildMI ( MBB , MI , DL , get ( Opcode ) , RI . getSubReg ( DestReg , SubIndices [ Idx ] ) ) ;


<s> const DebugLoc & DL = Inst . getDebugLoc ( ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : { Register ImmReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register TmpReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , Inst , DL , get ( <STR_LIT> ) , ImmReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , Inst , DL , get ( <STR_LIT> ) , TmpReg ) . addReg ( ImmReg , RegState :: Kill ) . add ( Src0 ) ; BuildMI ( * MBB , Inst , DL , get ( <STR_LIT> ) , ResultReg ) . add ( Src1 ) . addImm ( <NUM_LIT> ) . addReg ( TmpReg , RegState :: Kill ) ; break ; } case <STR_LIT> : { Register ImmReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , Inst , DL , get ( <STR_LIT> ) , ImmReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , Inst , DL , get ( <STR_LIT> ) , ResultReg ) . addReg ( ImmReg , RegState :: Kill ) . add ( Src0 ) . add ( Src1 ) ; break ; } case <STR_LIT> : { Register ImmReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register TmpReg = MRI . createVirtualRegister ( & <STR_LIT> ) ;

BuildMI ( * MBB , Inst , DL , get ( <STR_LIT> ) , TmpReg ) . addImm ( <NUM_LIT> ) . add ( Src0 ) ;


<s> MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; Register OldDstReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned Opc = Inst . getOpcode ( ) ; assert ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; unsigned NewOpc = Opc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; Inst . RemoveOperand ( <NUM_LIT> ) ; Inst . setDesc ( get ( NewOpc ) ) ;

Inst . addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ;


<s> Inst . RemoveOperand ( <NUM_LIT> ) ; Inst . setDesc ( get ( NewOpc ) ) ; Inst . addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst . addImplicitDefUseOperands ( * MBB . getParent ( ) ) ; MRI . replaceRegWith ( OldDstReg , ResultReg ) ; legalizeOperands ( Inst , MDT ) ; addUsersToMoveToVALUWorklist ( ResultReg , MRI , Worklist ) ;


<s> Gen = <STR_LIT> ; break ; case <ISA_LIT>Subtarget :: GFX10 : Gen = <STR_LIT> ; break ; } } int MCOp = <STR_LIT> ( Opcode , Gen ) ; if ( MCOp == - <NUM_LIT> ) return Opcode ; if ( MCOp == ( uint16_t ) - <NUM_LIT> ) return - <NUM_LIT> ;

if ( isAsmOnlyOpcode ( MCOp ) ) return - <NUM_LIT> ;


<s> const MachineInstr & SecondLdSt = * BaseOps2 . front ( ) -> getParent ( ) ; if ( ! memOpsHaveSameBasePtr ( FirstLdSt , BaseOps1 , SecondLdSt , BaseOps2 ) ) return false ; const unsigned LoadSize = NumBytes / NumLoads ; const unsigned NumDWORDs = ( ( LoadSize + <NUM_LIT> ) / <NUM_LIT> ) * NumLoads ;


<s> return false ; } return true ; } if ( MI . isPreISelOpcode ( ) || <ISA_LIT>InstrInfo :: isGenericOpcode ( MI . getOpcode ( ) ) || <ISA_LIT>InstrInfo :: isSALU ( MI ) || <ISA_LIT>InstrInfo :: isSMRD ( MI ) ) return false ;


<s> } if ( MI . isPreISelOpcode ( ) || <ISA_LIT>InstrInfo :: isGenericOpcode ( MI . getOpcode ( ) ) || <ISA_LIT>InstrInfo :: isSALU ( MI ) || <ISA_LIT>InstrInfo :: isSMRD ( MI ) ) return false ;


<s> addUsersToMoveToVALUWorklist ( ResultReg , MRI , Worklist ) ; return ; } MachineOperand & Src = Inst . getOperand ( <NUM_LIT> ) ; Register TmpReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , TmpReg ) . addImm ( <NUM_LIT> ) . addReg ( Src . getReg ( ) , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , ResultReg ) . addReg ( Src . getReg ( ) , <NUM_LIT> , <STR_LIT> ) . addImm ( <STR_LIT> ) . addReg ( TmpReg ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , ResultReg ) ; addUsersToMoveToVALUWorklist ( ResultReg , MRI , Worklist ) ;


<s> MachineOperand & Dest = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src0 = Inst . getOperand ( <NUM_LIT> ) ; DebugLoc DL = Inst . getDebugLoc ( ) ; MachineBasicBlock :: iterator MII = Inst ; const MCInstrDesc & InstDesc = get ( Opcode ) ; const TargetRegisterClass * Src0RC = Src0 . isReg ( ) ? MRI . getRegClass ( Src0 . getReg ( ) ) : & <STR_LIT> ; const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ;

const TargetRegisterClass * DestRC = MRI . getRegClass ( Dest . getReg ( ) ) ;


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , Register SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineFrameInfo & FrameInfo = MF -> getFrameInfo ( ) ; const DebugLoc & DL = MBB . findDebugLoc ( MI ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , FrameInfo . getObjectSize ( FrameIndex ) , FrameInfo . getObjectAlign ( FrameIndex ) ) ; unsigned SpillSize = TRI -> getSpillSize ( * RC ) ; if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ;

assert ( SrcReg != <STR_LIT> && <STR_LIT> ) ;


<s> if ( I == MBB . end ( ) ) return false ; if ( I -> getOpcode ( ) == <STR_LIT> ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } BranchPredicate Pred = getBranchPredicate ( I -> getOpcode ( ) ) ;


<s> unsigned STmp0 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; unsigned STmp1 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp0 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Z ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Y ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( STmp1 ) . addReg ( STmp0 ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp1 ) . addReg ( TIDIGXReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp0 ) . addReg ( TIDIGYReg ) . addReg ( TIDReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( TIDReg ) . addReg ( TIDIGZReg ) ; } else { BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addReg ( TIDReg ) ; } BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( <NUM_LIT> ) . addReg ( TIDReg ) ; MFI -> setTIDReg ( TIDReg ) ; } unsigned LDSOffset = MFI -> getLDSSize ( ) + ( FrameOffset * WorkGroupSize ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , TmpReg ) . addImm ( LDSOffset ) . addReg ( TIDReg ) ; return TmpReg ;


<s> assert ( ! SrcOp . isFPImm ( ) ) ; if ( SrcOp . isImm ( ) ) { APInt Imm ( <NUM_LIT> , SrcOp . getImm ( ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstLo ) . addImm ( Imm . getLoBits ( <NUM_LIT> ) . getZExtValue ( ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstHi ) . addImm ( Imm . getHiBits ( <NUM_LIT> ) . getZExtValue ( ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; } else { assert ( SrcOp . isReg ( ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstLo ) . addReg ( RI . getSubReg ( SrcOp . getReg ( ) , <STR_LIT> ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstHi ) . addReg ( RI . getSubReg ( SrcOp . getReg ( ) , <STR_LIT> ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; } MI . eraseFromParent ( ) ; break ; } case <STR_LIT> : { unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstLo = RI . getSubReg ( Dst , <STR_LIT> ) ; unsigned DstHi = RI . getSubReg ( Dst , <STR_LIT> ) ; unsigned Src0 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const MachineOperand & SrcCond = MI . getOperand ( <NUM_LIT> ) ;

BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstLo ) . addReg ( RI . getSubReg ( Src0 , <STR_LIT> ) ) . addReg ( RI . getSubReg ( Src1 , <STR_LIT> ) ) . addReg ( SrcCond . getReg ( ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ;


<s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; switch ( MI . getOpcode ( ) ) { default : return <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MI ) ; case <STR_LIT> : { unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstLo = RI . getSubReg ( Dst , <STR_LIT> ) ; unsigned DstHi = RI . getSubReg ( Dst , <STR_LIT> ) ; const MachineOperand & SrcOp = MI . getOperand ( <NUM_LIT> ) ; assert ( ! SrcOp . isFPImm ( ) ) ; if ( SrcOp . isImm ( ) ) { APInt Imm ( <NUM_LIT> , SrcOp . getImm ( ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstLo ) . addImm ( Imm . getLoBits ( <NUM_LIT> ) . getZExtValue ( ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstHi ) . addImm ( Imm . getHiBits ( <NUM_LIT> ) . getZExtValue ( ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; } else { assert ( SrcOp . isReg ( ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstLo ) . addReg ( RI . getSubReg ( SrcOp . getReg ( ) , <STR_LIT> ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstHi ) . addReg ( RI . getSubReg ( SrcOp . getReg ( ) , <STR_LIT> ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ;


<s> } switch ( Opc ) { case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : case TargetOpcode :: BUNDLE : case TargetOpcode :: EH_LABEL : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; }


<s> if ( DescSize == <NUM_LIT> || DescSize == <NUM_LIT> ) return DescSize ; assert ( DescSize == <NUM_LIT> ) ; if ( isVALU ( MI ) || isSALU ( MI ) ) { int Src0Idx = <STR_LIT> ( Opc , <STR_LIT> :: src0 ) ; if ( Src0Idx == - <NUM_LIT> ) return <NUM_LIT> ; if ( isLiteralConstantLike ( MI . getOperand ( Src0Idx ) , getOpSize ( MI , Src0Idx ) ) ) return <NUM_LIT> ; int Src1Idx = <STR_LIT> ( Opc , <STR_LIT> :: src1 ) ; if ( Src1Idx == - <NUM_LIT> ) return <NUM_LIT> ; if ( isLiteralConstantLike ( MI . getOperand ( Src1Idx ) , getOpSize ( MI , Src1Idx ) ) ) return <NUM_LIT> ; return <NUM_LIT> ; } switch ( Opc ) {


<s> bool isFLATGlobal ( uint16_t Opcode ) const {

return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> return false ; case MachineOperand :: MO_Immediate : return ! isInlineConstant ( MO , OpSize ) ; case MachineOperand :: MO_FrameIndex : case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_GlobalAddress :


<s> bool isSegmentSpecificFLAT ( uint16_t Opcode ) const { auto Flags = get ( Opcode ) . TSFlags ;

return Flags & ( <STR_LIT> | <STR_LIT> ) ;


<s> MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad , Size , Align ) ; if ( RI . isSGPRClass ( RC ) ) { unsigned Opcode = getSGPRSpillRestoreOpcode ( RC -> getSize ( ) ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) && RC -> getSize ( ) == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( DestReg , & <STR_LIT> ) ; } BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) ; return ; }

if ( ! ST . isVGPRSpillingEnabled ( * MF -> getFunction ( ) ) ) {


<s> } if ( ! ST . isVGPRSpillingEnabled ( * MF -> getFunction ( ) ) ) { LLVMContext & Ctx = MF -> getFunction ( ) -> getContext ( ) ; Ctx . emitError ( <STR_LIT> <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg ) ; return ; } assert ( RI . hasVGPRs ( RC ) && <STR_LIT> ) ; unsigned Opcode = getVGPRSpillSaveOpcode ( RC -> getSize ( ) ) ; MFI -> setHasSpilledVGPRs ( ) ; BuildMI ( MBB , MI , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI -> getScratchWaveOffsetReg ( ) ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> unsigned Size = FrameInfo . getObjectSize ( FrameIndex ) ; unsigned Align = FrameInfo . getObjectAlignment ( FrameIndex ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , Size , Align ) ; if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) && RC -> getSize ( ) == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; } unsigned Opcode = getSGPRSpillSaveOpcode ( RC -> getSize ( ) ) ;

BuildMI ( MBB , MI , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) ;


<s> switch ( Desc . OpInfo [ i ] . OperandType ) { case MCOI :: OPERAND_REGISTER : if ( MI . getOperand ( i ) . isImm ( ) ) { ErrInfo = <STR_LIT> ; return false ; } break ; case <STR_LIT> : break ; case <STR_LIT> : if ( isLiteralConstant ( MI . getOperand ( i ) , RI . getRegClass ( RegClass ) -> getSize ( ) ) ) { ErrInfo = <STR_LIT> ; return false ; } break ; case MCOI :: OPERAND_IMMEDIATE : case <STR_LIT> : if ( ! MI . getOperand ( i ) . isImm ( ) && ! MI . getOperand ( i ) . isFI ( ) ) { ErrInfo = <STR_LIT> ; return false ; } LLVM_FALLTHROUGH ; default : continue ; } if ( ! MI . getOperand ( i ) . isReg ( ) ) continue ; if ( RegClass != - <NUM_LIT> ) { unsigned Reg = MI . getOperand ( i ) . getReg ( ) ; if ( Reg == <STR_LIT> || TargetRegisterInfo :: isVirtualRegister ( Reg ) ) continue ; const TargetRegisterClass * RC = RI . getRegClass ( RegClass ) ; if ( ! RC -> contains ( Reg ) ) { ErrInfo = <STR_LIT> ; return false ; } } } if ( isVOP1 ( MI ) || isVOP2 ( MI ) || isVOP3 ( MI ) || isVOPC ( MI ) ) { const int OpIndices [ ] = { Src0Idx , Src1Idx , Src2Idx } ; unsigned ConstantBusCount = <NUM_LIT> ; if ( <STR_LIT> ( Opcode , <STR_LIT> :: imm ) != - <NUM_LIT> ) ++ ConstantBusCount ; unsigned SGPRUsed = findImplicitSGPRRead ( MI ) ; if ( SGPRUsed != <STR_LIT> ) ++ ConstantBusCount ; for ( int OpIdx : OpIndices ) {


<s> return false ; } } } if ( isVOP1 ( MI ) || isVOP2 ( MI ) || isVOP3 ( MI ) || isVOPC ( MI ) ) { const int OpIndices [ ] = { Src0Idx , Src1Idx , Src2Idx } ; unsigned ConstantBusCount = <NUM_LIT> ; if ( <STR_LIT> ( Opcode , <STR_LIT> :: imm ) != - <NUM_LIT> ) ++ ConstantBusCount ; unsigned SGPRUsed = findImplicitSGPRRead ( MI ) ; if ( SGPRUsed != <STR_LIT> ) ++ ConstantBusCount ; for ( int OpIdx : OpIndices ) { if ( OpIdx == - <NUM_LIT> ) break ; const MachineOperand & MO = MI . getOperand ( OpIdx ) ; if ( usesConstantBus ( MRI , MO , getOpSize ( Opcode , OpIdx ) ) ) { if ( MO . isReg ( ) ) { if ( MO . getReg ( ) != SGPRUsed ) ++ ConstantBusCount ; SGPRUsed = MO . getReg ( ) ; } else { ++ ConstantBusCount ; } } } if ( ConstantBusCount > <NUM_LIT> ) { ErrInfo = <STR_LIT> ; return false ; } } if ( Desc . getOpcode ( ) == <STR_LIT> || Desc . getOpcode ( ) == <STR_LIT> ) { const MachineOperand & Src0 = MI . getOperand ( Src0Idx ) ; const MachineOperand & Src1 = MI . getOperand ( Src1Idx ) ; const MachineOperand & Src2 = MI . getOperand ( Src2Idx ) ; if ( Src0 . isReg ( ) && Src1 . isReg ( ) && Src2 . isReg ( ) ) { if ( ! compareMachineOp ( Src0 , Src1 ) && ! compareMachineOp ( Src0 , Src2 ) ) { ErrInfo = <STR_LIT> ; return false ; } } } if ( Desc . getOpcode ( ) == <STR_LIT> || Desc . getOpcode ( ) == <STR_LIT> || Desc . getOpcode ( ) == <STR_LIT> || Desc . getOpcode ( ) == <STR_LIT> ) {

const bool IsDst = Desc . getOpcode ( ) == <STR_LIT> || Desc . getOpcode ( ) == <STR_LIT> ;


<s> const MachineOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) ) { if ( unsigned SubReg = MO . getSubReg ( ) ) { assert ( RI . getRegSizeInBits ( * RI . getSubClassWithSubReg ( MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) . getRegClass ( MO . getReg ( ) ) , SubReg ) ) >= <NUM_LIT> && <STR_LIT> ) ; return RI . getNumChannelsFromSubReg ( SubReg ) * <NUM_LIT> ; } }

return RI . getRegSizeInBits ( * getOpRegClass ( MI , OpNo ) ) / <NUM_LIT> ;


<s> assert ( RI . getRegSizeInBits ( * RI . getSubClassWithSubReg ( MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) . getRegClass ( MO . getReg ( ) ) , SubReg ) ) >= <NUM_LIT> && <STR_LIT> ) ; return RI . getNumChannelsFromSubReg ( SubReg ) * <NUM_LIT> ; } }


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : llvm_unreachable ( <STR_LIT> ) ; } ++ I ; } if ( I == E ) return false ; if ( I -> getOpcode ( ) != <STR_LIT> ) return analyzeBranchImpl ( MBB , I , TBB , FBB , Cond , AllowModify ) ; ++ I ;


<s> } Inst32 . add ( * getNamedOperand ( MI , <STR_LIT> :: src0 ) ) ; const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; if ( Src1 ) Inst32 . add ( * Src1 ) ; const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ; if ( Src2 ) { int Op32Src2Idx = <STR_LIT> ( Op32 , <STR_LIT> :: src2 ) ; if ( Op32Src2Idx != - <NUM_LIT> ) {


<s> } RS -> enterBasicBlock ( Entry ) ; Register STmp0 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; Register STmp1 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp0 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Z ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Y ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( STmp1 ) . addReg ( STmp0 ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp1 ) . addReg ( TIDIGXReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp0 ) . addReg ( TIDIGYReg ) . addReg ( TIDReg ) ; getAddNoCarry ( Entry , Insert , DL , TIDReg ) . addReg ( TIDReg ) . addReg ( TIDIGZReg ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addReg ( TIDReg ) ; } BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( <NUM_LIT> ) . addReg ( TIDReg ) ; MFI -> setTIDReg ( TIDReg ) ;