<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; static const int16_t Sub0_7 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; static const int16_t Sub0_3 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; static const int16_t Sub0_2 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; static const int16_t Sub0_1 [ ] = { <STR_LIT> , <STR_LIT> , } ; switch ( <STR_LIT> ( * RC -> MC ) ) { case <NUM_LIT> : return { } ; case <NUM_LIT> : return makeArrayRef ( Sub0_1 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_2 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_3 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_7 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_15 ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } if ( EltSize == <NUM_LIT> ) { static const int16_t Sub0_15_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const int16_t Sub0_7_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const int16_t Sub0_3_64 [ ] = { <STR_LIT> , <STR_LIT> } ; switch ( <STR_LIT> ( * RC -> MC ) ) {


<s> case <NUM_LIT> : return makeArrayRef ( Sub0_3 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_7 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_15 ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } if ( EltSize == <NUM_LIT> ) { static const int16_t Sub0_15_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const int16_t Sub0_7_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const int16_t Sub0_3_64 [ ] = { <STR_LIT> , <STR_LIT> } ; switch ( <STR_LIT> ( * RC -> MC ) ) { case <NUM_LIT> : return { } ; case <NUM_LIT> : return makeArrayRef ( Sub0_3_64 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_7_64 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_15_64 ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } assert ( EltSize == <NUM_LIT> && <STR_LIT> ) ; static const int16_t Sub0_15_128 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const int16_t Sub0_7_128 [ ] = { <STR_LIT> , <STR_LIT> } ; switch ( <STR_LIT> ( * RC -> MC ) ) {


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg ) ) ; } unsigned StackPtrReg = MFI -> getStackPtrOffsetReg ( ) ; if ( StackPtrReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , StackPtrReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , StackPtrReg ) ) ; } unsigned FrameReg = MFI -> getFrameOffsetReg ( ) ; if ( FrameReg != <STR_LIT> ) {

reserveRegisterTuples ( Reserved , FrameReg ) ;


<s> unsigned Count = getSubRegIndexLaneMask ( SubIdx ) . getNumLanes ( ) ; if ( isSGPRClass ( RC ) ) { switch ( Count ) { case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : default : llvm_unreachable ( <STR_LIT> ) ; } } else { switch ( Count ) { case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ;


<s> unsigned Size = getRegSizeInBits ( * RC ) ; if ( Size < <NUM_LIT> ) return false ; switch ( Size ) { case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ;


<s> case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const GCNSubtarget & Subtarget = MF -> getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; if ( Offset == <NUM_LIT> ) { BuildMI ( * MBB , Ins , DL , TII -> get ( <STR_LIT> ) , BaseReg ) . addFrameIndex ( FrameIdx ) ; return ;


<s> bool <ISA_LIT>RegisterInfo :: requiresFrameIndexReplacementScavenging ( const MachineFunction & MF ) const {

return MF . getFrameInfo ( ) . hasStackObjects ( ) && MF . getSubtarget < GCNSubtarget > ( ) . hasScalarStores ( ) && MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> hasSpilledSGPRs ( ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: reservedStackPtrOffsetReg ( const MachineFunction & MF ) const {


<s> unsigned NumRegPressureSets = getNumRegPressureSets ( ) ; SGPRSetID = NumRegPressureSets ; VGPRSetID = NumRegPressureSets ; for ( unsigned i = <NUM_LIT> ; i < NumRegPressureSets ; ++ i ) { classifyPressureSet ( i , <STR_LIT> , SGPRPressureSets ) ; classifyPressureSet ( i , <STR_LIT> , VGPRPressureSets ) ; } std :: vector < unsigned > PressureSetRegUnits ( NumRegPressureSets , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = getNumRegUnits ( ) ; i != e ; ++ i ) { const int * PSets = getRegUnitPressureSets ( i ) ; for ( unsigned j = <NUM_LIT> ; PSets [ j ] != - <NUM_LIT> ; ++ j ) { ++ PressureSetRegUnits [ PSets [ j ] ] ; } } unsigned VGPRMax = <NUM_LIT> , SGPRMax = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumRegPressureSets ; ++ i ) { if ( isVGPRPressureSet ( i ) && PressureSetRegUnits [ i ] > VGPRMax ) { VGPRSetID = i ; VGPRMax = PressureSetRegUnits [ i ] ; continue ; } if ( isSGPRPressureSet ( i ) && PressureSetRegUnits [ i ] > SGPRMax ) { SGPRSetID = i ; SGPRMax = PressureSetRegUnits [ i ] ; } }

assert ( SGPRSetID < NumRegPressureSets && VGPRSetID < NumRegPressureSets ) ;


<s> if ( SpillToVGPR ) { <ISA_LIT>MachineFunctionInfo :: SpilledReg Spill = VGPRSpills [ i ] ; bool VGPRDefined = true ; if ( MBB == & MF -> front ( ) ) VGPRDefined = ! SGPRSpillVGPRDefinedSet . insert ( Spill . VGPR ) . second ; BuildMI ( * MBB , MI , DL , TII -> getMCOpcodeFromPseudo ( <STR_LIT> ) , Spill . VGPR ) . addReg ( SubReg , getKillRegState ( IsKill ) ) . addImm ( Spill . Lane ) . addReg ( Spill . VGPR , VGPRDefined ? <NUM_LIT> : RegState :: Undef ) ; } else { if ( OnlyToVGPR ) return false ; unsigned TmpReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstrBuilder Mov = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , TmpReg ) . addReg ( SubReg , SubKillState ) ; if ( NumSubRegs > <NUM_LIT> ) { unsigned SuperKillState = <NUM_LIT> ; if ( i + <NUM_LIT> == e ) SuperKillState |= getKillRegState ( IsKill ) ; Mov . addReg ( SuperReg , RegState :: Implicit | SuperKillState ) ; } unsigned Align = FrameInfo . getObjectAlignment ( Index ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , Index , EltSize * i ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , EltSize , MinAlign ( Align , EltSize * i ) ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( TmpReg , RegState :: Kill ) . addFrameIndex ( Index ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI -> getFrameOffsetReg ( ) ) . addImm ( i * <NUM_LIT> ) . addMemOperand ( MMO ) ; } } if ( M0CopyReg != <STR_LIT> ) { BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( M0CopyReg , RegState :: Kill ) ; } MI -> eraseFromParent ( ) ; MFI -> addToSpilledSGPRs ( NumSubRegs ) ;


<s> & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , } ; for ( const TargetRegisterClass * BaseClass : BaseClasses ) { if ( BaseClass -> contains ( Reg ) ) { return BaseClass ; } }


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPhysRegClass ( unsigned Reg ) const { assert ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) ; static const TargetRegisterClass * const BaseClasses [ ] = {

& <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , } ;


<s> const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Occupancy = ST . getOccupancyWithLocalMemSize ( MFI -> getLDSSize ( ) , MF . getFunction ( ) ) ; switch ( RC -> getID ( ) ) { default : return <ISA_LIT>RegisterInfo :: getRegPressureLimit ( RC , MF ) ; case <STR_LIT> : return std :: min ( ST . getMaxNumVGPRs ( Occupancy ) , ST . getMaxNumVGPRs ( MF ) ) ; case <STR_LIT> : return std :: min ( ST . getMaxNumSGPRs ( Occupancy , true ) , ST . getMaxNumSGPRs ( MF ) ) ; }


<s> reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg ) ) ; } unsigned StackPtrReg = MFI -> getStackPtrOffsetReg ( ) ; if ( StackPtrReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , StackPtrReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , StackPtrReg ) ) ; } unsigned FrameReg = MFI -> getFrameOffsetReg ( ) ; if ( FrameReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , FrameReg ) ;

assert ( ! isSubRegister ( ScratchRSrcReg , FrameReg ) ) ;


<s> reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) {


<s> const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; if ( Offset == <NUM_LIT> ) { BuildMI ( * MBB , Ins , DL , TII -> get ( <STR_LIT> ) , BaseReg ) . addFrameIndex ( FrameIdx ) ; return ; } MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned OffsetReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned FIReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , Ins , DL , TII -> get ( <STR_LIT> ) , OffsetReg ) . addImm ( Offset ) ;

BuildMI ( * MBB , Ins , DL , TII -> get ( <STR_LIT> ) , FIReg ) . addFrameIndex ( FrameIdx ) ;


<s> const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned BaseIdx = alignDown ( ST . getMaxNumSGPRs ( MF ) , <NUM_LIT> ) - <NUM_LIT> ;

unsigned BaseReg ( <STR_LIT> . getRegister ( BaseIdx ) ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: reservedPrivateSegmentBufferReg ( const MachineFunction & MF ) const { const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned BaseIdx = alignDown ( ST . getMaxNumSGPRs ( MF ) , <NUM_LIT> ) - <NUM_LIT> ;


<s> const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


return <STR_LIT> . getRegister ( Reg ) ;


<s> void <ISA_LIT>RegisterInfo :: resolveFrameIndex ( MachineInstr & MI , unsigned BaseReg , int64_t Offset ) const { MachineBasicBlock * MBB = MI . getParent ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; bool SeenFI = false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( MO . isFI ( ) ) { if ( SeenFI ) llvm_unreachable ( <STR_LIT> ) ; SeenFI = true ; } } MachineOperand * FIOp = TII -> getNamedOperand ( MI , <STR_LIT> :: vaddr ) ; assert ( FIOp && FIOp -> isFI ( ) && <STR_LIT> ) ; assert ( TII -> isMUBUF ( MI ) ) ; assert ( TII -> getNamedOperand ( MI , <STR_LIT> :: soffset ) -> getReg ( ) == MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getFrameOffsetReg ( ) && <STR_LIT> ) ; MachineOperand * OffsetOp = TII -> getNamedOperand ( MI , <STR_LIT> :: offset ) ; int64_t NewOffset = OffsetOp -> getImm ( ) + Offset ;

assert ( isUInt < <NUM_LIT> > ( NewOffset ) && <STR_LIT> ) ;


<s> MachineFunction * MF = MBB -> getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; bool SeenFI = false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( MO . isFI ( ) ) { if ( SeenFI ) llvm_unreachable ( <STR_LIT> ) ; SeenFI = true ; } } MachineOperand * FIOp = TII -> getNamedOperand ( MI , <STR_LIT> :: vaddr ) ; assert ( FIOp && FIOp -> isFI ( ) && <STR_LIT> ) ;


<s> for ( unsigned i = <NUM_LIT> , e = getNumRegUnits ( ) ; i != e ; ++ i ) { const int * PSets = getRegUnitPressureSets ( i ) ; for ( unsigned j = <NUM_LIT> ; PSets [ j ] != - <NUM_LIT> ; ++ j ) { ++ PressureSetRegUnits [ PSets [ j ] ] ; } } unsigned VGPRMax = <NUM_LIT> , SGPRMax = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumRegPressureSets ; ++ i ) { if ( isVGPRPressureSet ( i ) && PressureSetRegUnits [ i ] > VGPRMax ) { VGPRSetID = i ; VGPRMax = PressureSetRegUnits [ i ] ;


<s> if ( MBB == & MF -> front ( ) ) VGPRDefined = ! SGPRSpillVGPRDefinedSet . insert ( Spill . VGPR ) . second ; BuildMI ( * MBB , MI , DL , TII -> getMCOpcodeFromPseudo ( <STR_LIT> ) , Spill . VGPR ) . addReg ( SubReg , getKillRegState ( IsKill ) ) . addImm ( Spill . Lane ) . addReg ( Spill . VGPR , VGPRDefined ? <NUM_LIT> : RegState :: Undef ) ; } else { if ( OnlyToVGPR ) return false ; unsigned TmpReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstrBuilder Mov = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , TmpReg ) . addReg ( SubReg , SubKillState ) ; if ( NumSubRegs > <NUM_LIT> ) { unsigned SuperKillState = <NUM_LIT> ; if ( i + <NUM_LIT> == e ) SuperKillState |= getKillRegState ( IsKill ) ; Mov . addReg ( SuperReg , RegState :: Implicit | SuperKillState ) ; } unsigned Align = FrameInfo . getObjectAlignment ( Index ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , Index , EltSize * i ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , EltSize , MinAlign ( Align , EltSize * i ) ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( TmpReg , RegState :: Kill ) . addFrameIndex ( Index ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI -> getFrameOffsetReg ( ) ) . addImm ( i * <NUM_LIT> ) . addMemOperand ( MMO ) ; } } if ( M0CopyReg != <STR_LIT> ) {

BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( M0CopyReg , RegState :: Kill ) ;


<s> unsigned Align = MFI . getObjectAlignment ( Index ) ; const MachinePointerInfo & BasePtrInfo = MMO -> getPointerInfo ( ) ; Register TmpReg = hasAGPRs ( RC ) ? TII -> getNamedOperand ( * MI , <STR_LIT> :: tmp ) -> getReg ( ) : Register ( ) ; assert ( ( Offset % EltSize ) == <NUM_LIT> && <STR_LIT> ) ; if ( ! isUInt < <NUM_LIT> > ( Offset + Size - EltSize ) ) { SOffset = <STR_LIT> ; Offset *= ST . getWavefrontSize ( ) ; if ( RS ) SOffset = RS -> scavengeRegister ( & <STR_LIT> , MI , <NUM_LIT> , false ) ; if ( SOffset == <STR_LIT> ) { SOffset = ScratchOffsetReg ; ScratchOffsetRegDelta = Offset ; } else { Scavenged = true ; } BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SOffset ) . addReg ( ScratchOffsetReg ) . addImm ( Offset ) ; Offset = <NUM_LIT> ; } for ( unsigned i = <NUM_LIT> , e = NumSubRegs ; i != e ; ++ i , Offset += EltSize ) { Register SubReg = NumSubRegs == <NUM_LIT> ? Register ( ValueReg ) : getSubReg ( ValueReg , getSubRegFromChannel ( i ) ) ; unsigned SOffsetRegState = <NUM_LIT> ; unsigned SrcDstRegState = getDefRegState ( ! IsStore ) ; if ( i + <NUM_LIT> == e ) { SOffsetRegState |= getKillRegState ( Scavenged ) ; SrcDstRegState |= getKillRegState ( IsKill ) ; } auto MIB = spillVGPRtoAGPR ( MI , Index , i , SubReg , IsKill ) ; if ( ! MIB . getInstr ( ) ) { unsigned FinalReg = SubReg ; if ( TmpReg != <STR_LIT> ) { if ( IsStore ) BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , TmpReg ) . addReg ( SubReg , getKillRegState ( IsKill ) ) ; SubReg = TmpReg ; } MachinePointerInfo PInfo = BasePtrInfo . getWithOffset ( EltSize * i ) ; MachineMemOperand * NewMMO = MF -> getMachineMemOperand ( PInfo , MMO -> getFlags ( ) , EltSize , MinAlign ( Align , EltSize * i ) ) ; MIB = BuildMI ( * MBB , MI , DL , Desc ) . addReg ( SubReg , getDefRegState ( ! IsStore ) | getKillRegState ( IsKill ) ) . addReg ( ScratchRsrcReg ) . addReg ( SOffset , SOffsetRegState ) . addImm ( Offset ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( NewMMO ) ; if ( ! IsStore && TmpReg != <STR_LIT> ) MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , FinalReg ) . addReg ( TmpReg , RegState :: Kill ) ; } if ( NumSubRegs > <NUM_LIT> ) MIB . addReg ( ValueReg , RegState :: Implicit | SrcDstRegState ) ;


<s> const DebugLoc & DL = MI -> getDebugLoc ( ) ; bool IsStore = Desc . mayStore ( ) ; bool Scavenged = false ; unsigned SOffset = ScratchOffsetReg ; const unsigned EltSize = <NUM_LIT> ; const TargetRegisterClass * RC = getRegClassForReg ( MF -> getRegInfo ( ) , ValueReg ) ; unsigned NumSubRegs = <STR_LIT> ( RC -> getID ( ) ) / ( EltSize * CHAR_BIT ) ; unsigned Size = NumSubRegs * EltSize ; int64_t Offset = InstOffset + MFI . getObjectOffset ( Index ) ; int64_t ScratchOffsetRegDelta = <NUM_LIT> ; unsigned Align = MFI . getObjectAlignment ( Index ) ; const MachinePointerInfo & BasePtrInfo = MMO -> getPointerInfo ( ) ; Register TmpReg = hasAGPRs ( RC ) ? TII -> getNamedOperand ( * MI , <STR_LIT> :: tmp ) -> getReg ( ) : Register ( ) ; assert ( ( Offset % EltSize ) == <NUM_LIT> && <STR_LIT> ) ; if ( ! isUInt < <NUM_LIT> > ( Offset + Size - EltSize ) ) { SOffset = <STR_LIT> ; Offset *= ST . getWavefrontSize ( ) ; if ( RS ) SOffset = RS -> scavengeRegister ( & <STR_LIT> , MI , <NUM_LIT> , false ) ; if ( SOffset == <STR_LIT> ) { SOffset = ScratchOffsetReg ; ScratchOffsetRegDelta = Offset ; } else { Scavenged = true ; } BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SOffset ) . addReg ( ScratchOffsetReg ) . addImm ( Offset ) ; Offset = <NUM_LIT> ; } for ( unsigned i = <NUM_LIT> , e = NumSubRegs ; i != e ; ++ i , Offset += EltSize ) { Register SubReg = NumSubRegs == <NUM_LIT> ? Register ( ValueReg ) : getSubReg ( ValueReg , getSubRegFromChannel ( i ) ) ; unsigned SOffsetRegState = <NUM_LIT> ;

unsigned SrcDstRegState = getDefRegState ( ! IsStore ) ;


<s> for ( auto & S : LI . subranges ( ) ) { if ( ( S . LaneMask & SubLanes ) == SubLanes ) { V = S . getVNInfoAt ( UseIdx ) ; break ; } } } else { V = LI . getVNInfoAt ( UseIdx ) ; } if ( ! V ) return nullptr ; DefIdx = V -> def ; } else { for ( MCRegUnitIterator Units ( Reg , this ) ; Units . isValid ( ) ; ++ Units ) { LiveRange & LR = LIS -> getRegUnit ( * Units ) ; if ( VNInfo * V = LR . getVNInfoAt ( UseIdx ) ) { if ( ! DefIdx . isValid ( ) || MDT . dominates ( LIS -> getInstructionFromIndex ( DefIdx ) , LIS -> getInstructionFromIndex ( V -> def ) ) ) DefIdx = V -> def ; } else { return nullptr ; } }


<s> static const TargetRegisterClass * const BaseClasses [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , } ;

for ( const TargetRegisterClass * BaseClass : BaseClasses ) {


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPhysRegClass ( unsigned Reg ) const { assert ( ! Register :: isVirtualRegister ( Reg ) ) ; static const TargetRegisterClass * const BaseClasses [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , } ;


<s> if ( Register :: isVirtualRegister ( Reg ) ) return MRI . getRegClass ( Reg ) ; return getPhysRegClass ( Reg ) ;


<s> const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; if ( Offset == <NUM_LIT> ) { BuildMI ( * MBB , Ins , DL , TII -> get ( <STR_LIT> ) , BaseReg ) . addFrameIndex ( FrameIdx ) ; return ; } MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; Register OffsetReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register FIReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , Ins , DL , TII -> get ( <STR_LIT> ) , OffsetReg ) . addImm ( Offset ) ; BuildMI ( * MBB , Ins , DL , TII -> get ( <STR_LIT> ) , FIReg ) . addFrameIndex ( FrameIdx ) ; TII -> getAddNoCarry ( * MBB , Ins , DL , BaseReg ) . addReg ( OffsetReg , RegState :: Kill ) . addReg ( FIReg ) . addImm ( <NUM_LIT> ) ;


<s> } auto MIB = BuildMI ( * MBB , MI , DL , TII -> get ( ScalarLoadOp ) , SubReg ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( OffsetReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; if ( NumSubRegs > <NUM_LIT> && i == <NUM_LIT> ) MIB . addReg ( SuperReg , RegState :: ImplicitDefine ) ; continue ; } if ( SpillToVGPR ) { <ISA_LIT>MachineFunctionInfo :: SpilledReg Spill = VGPRSpills [ i ] ; auto MIB = BuildMI ( * MBB , MI , DL , TII -> getMCOpcodeFromPseudo ( <STR_LIT> ) , SubReg ) . addReg ( Spill . VGPR ) . addImm ( Spill . Lane ) ; if ( NumSubRegs > <NUM_LIT> && i == <NUM_LIT> ) MIB . addReg ( SuperReg , RegState :: ImplicitDefine ) ; } else { if ( OnlyToVGPR ) return false ; if ( ! TmpVGPR . isValid ( ) ) TmpVGPR = RS -> scavengeRegister ( & <STR_LIT> , MI , <NUM_LIT> ) ; unsigned Align = FrameInfo . getObjectAlignment ( Index ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , Index , EltSize * i ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad , EltSize , MinAlign ( Align , EltSize * i ) ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , TmpVGPR ) . addFrameIndex ( Index ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI -> getStackPtrOffsetReg ( ) ) . addImm ( i * <NUM_LIT> ) . addMemOperand ( MMO ) ; auto MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SubReg ) . addReg ( TmpVGPR , RegState :: Kill ) ; if ( NumSubRegs > <NUM_LIT> ) MIB . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , RegState :: ImplicitDefine ) ; } } if ( M0CopyReg != <STR_LIT> ) { BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( M0CopyReg , RegState :: Kill ) ; } MI -> eraseFromParent ( ) ;


<s> for ( unsigned i = <NUM_LIT> , e = getNumRegUnits ( ) ; i != e ; ++ i ) { const int * PSets = getRegUnitPressureSets ( i ) ; for ( unsigned j = <NUM_LIT> ; PSets [ j ] != - <NUM_LIT> ; ++ j ) { ++ PressureSetRegUnits [ PSets [ j ] ] ; } } unsigned VGPRMax = <NUM_LIT> , SGPRMax = <NUM_LIT> , AGPRMax = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumRegPressureSets ; ++ i ) { if ( isVGPRPressureSet ( i ) && PressureSetRegUnits [ i ] > VGPRMax ) {


<s> bool SpillToSMEM = spillSGPRToSMEM ( ) ; if ( SpillToSMEM && OnlyToVGPR ) return false ; Register FrameReg = getFrameRegister ( * MF ) ; assert ( SpillToVGPR || ( SuperReg != MFI -> getStackPtrOffsetReg ( ) && SuperReg != MFI -> getFrameOffsetReg ( ) && SuperReg != MFI -> getScratchWaveOffsetReg ( ) ) ) ; assert ( SuperReg != <STR_LIT> && <STR_LIT> ) ; unsigned OffsetReg = <STR_LIT> ; unsigned M0CopyReg = <STR_LIT> ; if ( SpillToSMEM ) { if ( RS -> isRegUsed ( <STR_LIT> ) ) { M0CopyReg = RS -> scavengeRegister ( & <STR_LIT> , MI , <NUM_LIT> , false ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , M0CopyReg ) . addReg ( <STR_LIT> ) ; } } unsigned ScalarStoreOp ; unsigned EltSize = <NUM_LIT> ; const TargetRegisterClass * RC = getPhysRegClass ( SuperReg ) ; if ( SpillToSMEM && isSGPRClass ( RC ) ) { std :: tie ( EltSize , ScalarStoreOp ) = getSpillEltSize ( getRegSizeInBits ( * RC ) / <NUM_LIT> , true ) ; } ArrayRef < int16_t > SplitParts = getRegSplitParts ( RC , EltSize ) ; unsigned NumSubRegs = SplitParts . empty ( ) ? <NUM_LIT> : SplitParts . size ( ) ; Register TmpVGPR ; unsigned SubKillState = getKillRegState ( ( NumSubRegs == <NUM_LIT> ) && IsKill ) ; for ( unsigned i = <NUM_LIT> , e = NumSubRegs ; i < e ; ++ i ) { Register SubReg = NumSubRegs == <NUM_LIT> ? SuperReg : getSubReg ( SuperReg , SplitParts [ i ] ) ; if ( SpillToSMEM ) { int64_t FrOffset = FrameInfo . getObjectOffset ( Index ) ; unsigned Align = FrameInfo . getObjectAlignment ( Index ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , Index , EltSize * i ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , EltSize , MinAlign ( Align , EltSize * i ) ) ; int64_t Offset = ( ST . getWavefrontSize ( ) * FrOffset ) + ( EltSize * i ) ; if ( Offset != <NUM_LIT> ) {

BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , OffsetReg ) . addReg ( FrameReg ) . addImm ( Offset ) ;


<s> MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget & ST = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; bool IsStore = MI -> mayStore ( ) ; bool RanOutOfSGPRs = false ; bool Scavenged = false ; unsigned SOffset = ScratchOffset ; unsigned OriginalImmOffset = Offset ; unsigned NumSubRegs = getNumSubRegsForSpillOp ( MI -> getOpcode ( ) ) ; unsigned Size = NumSubRegs * <NUM_LIT> ; if ( ! isUInt < <NUM_LIT> > ( Offset + Size ) ) { SOffset = <STR_LIT> ; if ( RS ) SOffset = RS -> FindUnusedReg ( & <STR_LIT> ) ; if ( SOffset == <STR_LIT> ) { RanOutOfSGPRs = true ; SOffset = ScratchOffset ;


<s> return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; default :


<s> if ( ! <ISA_LIT>InstrInfo :: isMUBUF ( * MI ) ) return <NUM_LIT> ;

assert ( Idx == <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: vaddr ) && <STR_LIT> ) ;


<s> if ( ! <ISA_LIT>InstrInfo :: isMUBUF ( * MI ) ) return <NUM_LIT> ; assert ( Idx == <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: vaddr ) && <STR_LIT> ) ; int OffIdx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: offset ) ;

return MI -> getOperand ( OffIdx ) . getImm ( ) ;


<s> unsigned MaxInvocationsPerWave = <ISA_LIT>MDPerCU * ST . getWavefrontSize ( ) ; return alignTo ( MFI . getMaximumWorkGroupSize ( MF ) , MaxInvocationsPerWave ) / MaxInvocationsPerWave ;


<s> static unsigned getMaxWaveCountPer<ISA_LIT>MD ( const MachineFunction & MF ) { const <ISA_LIT>MachineFunctionInfo & MFI = * MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;

const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> TotalSGPRCountPer<ISA_LIT>MD = <NUM_LIT> ; AddressableSGPRCount = <NUM_LIT> ; SGPRUsageAlignment = <NUM_LIT> ; ReservedSGPRCount = <NUM_LIT> ; } else { TotalSGPRCountPer<ISA_LIT>MD = <NUM_LIT> ; AddressableSGPRCount = <NUM_LIT> ; SGPRUsageAlignment = <NUM_LIT> ; ReservedSGPRCount = <NUM_LIT> ; }

unsigned MaxSGPRCount = ( TotalSGPRCountPer<ISA_LIT>MD / MaxWaveCountPer<ISA_LIT>MD ) ;


<s> const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned MaxWaveCountPer<ISA_LIT>MD = getMaxWaveCountPer<ISA_LIT>MD ( MF ) ; unsigned TotalSGPRCountPer<ISA_LIT>MD , AddressableSGPRCount , SGPRUsageAlignment ; unsigned ReservedSGPRCount ; if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { TotalSGPRCountPer<ISA_LIT>MD = <NUM_LIT> ; AddressableSGPRCount = <NUM_LIT> ; SGPRUsageAlignment = <NUM_LIT> ; ReservedSGPRCount = <NUM_LIT> ; } else { TotalSGPRCountPer<ISA_LIT>MD = <NUM_LIT> ; AddressableSGPRCount = <NUM_LIT> ; SGPRUsageAlignment = <NUM_LIT> ;


<s> unsigned MaxWaveCountPer<ISA_LIT>MD = getMaxWaveCountPer<ISA_LIT>MD ( MF ) ; unsigned TotalVGPRCountPer<ISA_LIT>MD = <NUM_LIT> ; unsigned VGPRUsageAlignment = <NUM_LIT> ;

return alignDown ( TotalVGPRCountPer<ISA_LIT>MD / MaxWaveCountPer<ISA_LIT>MD , VGPRUsageAlignment ) ;


<s> static unsigned getMaxWorkGroupVGPRCount ( const MachineFunction & MF ) { unsigned MaxWaveCountPer<ISA_LIT>MD = getMaxWaveCountPer<ISA_LIT>MD ( MF ) ; unsigned TotalVGPRCountPer<ISA_LIT>MD = <NUM_LIT> ; unsigned VGPRUsageAlignment = <NUM_LIT> ;


<s> unsigned <ISA_LIT>RegisterInfo :: getNumSGPRsAllowed ( const <ISA_LIT>Subtarget & ST , unsigned WaveCount ) const { if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { switch ( WaveCount ) { case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ;


<s> assert ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) ; static const TargetRegisterClass * const BaseClasses [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , } ;


<s> case <STR_LIT> : switch ( Channel ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } case <STR_LIT> : switch ( Channel ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; } break ; case <STR_LIT> : switch ( Channel ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; } break ; } const TargetRegisterClass * RC = getPhysRegClass ( Reg ) ; if ( RC -> getSize ( ) == <NUM_LIT> ) {


<s> case <ISA_LIT>RegisterInfo :: PRIVATE_SEGMENT_BUFFER : assert ( ST . isAmdHsaOS ( ) && <STR_LIT> ) ; assert ( MFI -> hasPrivateSegmentBuffer ( ) ) ; return MFI -> PrivateSegmentBufferUserSGPR ; case <ISA_LIT>RegisterInfo :: KERNARG_SEGMENT_PTR : assert ( MFI -> hasKernargSegmentPtr ( ) ) ; return MFI -> KernargSegmentPtrUserSGPR ; case <ISA_LIT>RegisterInfo :: DISPATCH_ID : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>RegisterInfo :: FLAT_SCRATCH_INIT : assert ( MFI -> hasFlatScratchInit ( ) ) ; return MFI -> FlatScratchInitUserSGPR ; case <ISA_LIT>RegisterInfo :: DISPATCH_PTR : assert ( MFI -> hasDispatchPtr ( ) ) ; return MFI -> DispatchPtrUserSGPR ; case <ISA_LIT>RegisterInfo :: QUEUE_PTR : assert ( MFI -> hasQueuePtr ( ) ) ; return MFI -> QueuePtrUserSGPR ;


<s> assert ( MFI -> hasWorkGroupIDY ( ) ) ; return MFI -> WorkGroupIDYSystemSGPR ; case <ISA_LIT>RegisterInfo :: WORKGROUP_ID_Z : assert ( MFI -> hasWorkGroupIDZ ( ) ) ; return MFI -> WorkGroupIDZSystemSGPR ; case <ISA_LIT>RegisterInfo :: PRIVATE_SEGMENT_WAVE_BYTE_OFFSET : return MFI -> PrivateSegmentWaveByteOffsetSystemSGPR ; case <ISA_LIT>RegisterInfo :: PRIVATE_SEGMENT_BUFFER : assert ( ST . isAmdHsaOS ( ) && <STR_LIT> ) ; assert ( MFI -> hasPrivateSegmentBuffer ( ) ) ; return MFI -> PrivateSegmentBufferUserSGPR ; case <ISA_LIT>RegisterInfo :: KERNARG_SEGMENT_PTR : assert ( MFI -> hasKernargSegmentPtr ( ) ) ; return MFI -> KernargSegmentPtrUserSGPR ; case <ISA_LIT>RegisterInfo :: DISPATCH_ID : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>RegisterInfo :: FLAT_SCRATCH_INIT : assert ( MFI -> hasFlatScratchInit ( ) ) ; return MFI -> FlatScratchInitUserSGPR ; case <ISA_LIT>RegisterInfo :: DISPATCH_PTR : assert ( MFI -> hasDispatchPtr ( ) ) ; return MFI -> DispatchPtrUserSGPR ;


<s> unsigned <ISA_LIT>RegisterInfo :: getRegPressureSetLimit ( const MachineFunction & MF , unsigned Idx ) const { const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

unsigned SGPRLimit = getNumSGPRsAllowed ( STI , STI . getMaxWavesPerCU ( ) ) ;


<s> unsigned MaxWorkGroupSGPRCount = getMaxWorkGroupSGPRCount ( MF ) ; unsigned MaxWorkGroupVGPRCount = getMaxWorkGroupVGPRCount ( MF ) ; unsigned NumSGPRs = <STR_LIT> . getNumRegs ( ) ; unsigned NumVGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxWorkGroupSGPRCount ; i < NumSGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } for ( unsigned i = MaxWorkGroupVGPRCount ; i < NumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg ) ) ; } const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ST . debuggerReserveRegs ( ) ) { unsigned ReservedVGPRFirst = MaxWorkGroupVGPRCount - MFI -> getDebuggerReservedVGPRCount ( ) ; for ( unsigned i = ReservedVGPRFirst ; i < MaxWorkGroupVGPRCount ; ++ i ) {


<s> Reserved . set ( <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; unsigned MaxWorkGroupSGPRCount = getMaxWorkGroupSGPRCount ( MF ) ; unsigned MaxWorkGroupVGPRCount = getMaxWorkGroupVGPRCount ( MF ) ; unsigned NumSGPRs = <STR_LIT> . getNumRegs ( ) ; unsigned NumVGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxWorkGroupSGPRCount ; i < NumSGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } for ( unsigned i = MaxWorkGroupVGPRCount ; i < NumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg ) ) ; }


<s> if ( SubIdx == <STR_LIT> ) return RC ; unsigned Count = countPopulation ( getSubRegIndexLaneMask ( SubIdx ) ) ; if ( isSGPRClass ( RC ) ) { switch ( Count ) { case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ;


<s> case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ;


<s> switch ( RC -> getSize ( ) ) { case <NUM_LIT> : return false ; case <NUM_LIT> : return false ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ;


<s> const TargetRegisterClass * RC ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) RC = MRI . getRegClass ( Reg ) ; else RC = getPhysRegClass ( Reg ) ;


<s> MachineFunction * MF = MBB -> getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; if ( Offset == <NUM_LIT> ) {

BuildMI ( * MBB , Ins , DL , TII -> get ( <STR_LIT> ) , BaseReg ) . addFrameIndex ( FrameIdx ) ;


<s> bool <ISA_LIT>RegisterInfo :: needsFrameBaseReg ( MachineInstr * MI , int64_t Offset ) const {


<s> return MF . getFrameInfo ( ) -> hasStackObjects ( ) ;


<s> unsigned BaseIdx = alignDown ( getMaxWorkGroupSGPRCount ( MF ) , <NUM_LIT> ) - <NUM_LIT> ; unsigned BaseReg ( <STR_LIT> . getRegister ( BaseIdx ) ) ; return getMatchingSuperReg ( BaseReg , <STR_LIT> , & <STR_LIT> ) ;


<s> if ( RegCount & <NUM_LIT> ) { Reg = RegCount - <NUM_LIT> ; } else { Reg = RegCount - <NUM_LIT> ;


<s> const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; bool SeenFI = false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( MO . isFI ( ) ) { if ( SeenFI ) llvm_unreachable ( <STR_LIT> ) ; SeenFI = true ; } } MachineOperand * FIOp = TII -> getNamedOperand ( MI , <STR_LIT> :: vaddr ) ; assert ( FIOp && FIOp -> isFI ( ) && <STR_LIT> ) ; assert ( TII -> isMUBUF ( MI ) ) ; MachineOperand * OffsetOp = TII -> getNamedOperand ( MI , <STR_LIT> :: offset ) ; int64_t NewOffset = OffsetOp -> getImm ( ) + Offset ; if ( isUInt < <NUM_LIT> > ( NewOffset ) ) {

FIOp -> ChangeToRegister ( BaseReg , false ) ;


<s> unsigned NumRegPressureSets = getNumRegPressureSets ( ) ; SGPR32SetID = NumRegPressureSets ; VGPR32SetID = NumRegPressureSets ; for ( unsigned i = <NUM_LIT> ; i < NumRegPressureSets ; ++ i ) {

if ( strncmp ( <STR_LIT> , getRegPressureSetName ( i ) , <NUM_LIT> ) == <NUM_LIT> ) SGPR32SetID = i ;


<s> const DebugLoc & DL = MI -> getDebugLoc ( ) ; bool IsStore = Desc . mayStore ( ) ; bool Scavenged = false ; unsigned SOffset = ScratchOffsetReg ; const unsigned EltSize = <NUM_LIT> ; const TargetRegisterClass * RC = getRegClassForReg ( MF -> getRegInfo ( ) , ValueReg ) ; unsigned NumSubRegs = <STR_LIT> ( RC -> getID ( ) ) / ( EltSize * CHAR_BIT ) ; unsigned Size = NumSubRegs * EltSize ; int64_t Offset = InstOffset + MFI . getObjectOffset ( Index ) ; int64_t ScratchOffsetRegDelta = <NUM_LIT> ; unsigned Align = MFI . getObjectAlignment ( Index ) ; const MachinePointerInfo & BasePtrInfo = MMO -> getPointerInfo ( ) ; Register TmpReg = hasAGPRs ( RC ) ? TII -> getNamedOperand ( * MI , <STR_LIT> :: tmp ) -> getReg ( ) : Register ( ) ; assert ( ( Offset % EltSize ) == <NUM_LIT> && <STR_LIT> ) ; if ( ! isUInt < <NUM_LIT> > ( Offset + Size - EltSize ) ) { SOffset = <STR_LIT> ; Offset *= ST . getWavefrontSize ( ) ; if ( RS ) SOffset = RS -> scavengeRegister ( & <STR_LIT> , MI , <NUM_LIT> , false ) ; if ( SOffset == <STR_LIT> ) { SOffset = ScratchOffsetReg ; ScratchOffsetRegDelta = Offset ; } else { Scavenged = true ; }

BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SOffset ) . addReg ( ScratchOffsetReg ) . addImm ( Offset ) ;


<s> case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ;


<s> case <NUM_LIT> : return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; default :

if ( Size < <NUM_LIT> ) return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> :


<s> case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> :


<s> case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; default : assert ( Size < <NUM_LIT> && <STR_LIT> ) ; return false ; }


<s> void <ISA_LIT>RegisterInfo :: resolveFrameIndex ( MachineInstr & MI , unsigned BaseReg , int64_t Offset ) const { MachineBasicBlock * MBB = MI . getParent ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const GCNSubtarget & Subtarget = MF -> getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; bool SeenFI = false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( MO . isFI ( ) ) { if ( SeenFI ) llvm_unreachable ( <STR_LIT> ) ; SeenFI = true ; } }

MachineOperand * FIOp = TII -> getNamedOperand ( MI , <STR_LIT> :: vaddr ) ;


<s> assert ( TII -> isMUBUF ( MI ) ) ; assert ( TII -> getNamedOperand ( MI , <STR_LIT> :: soffset ) -> getReg ( ) == MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getStackPtrOffsetReg ( ) && <STR_LIT> ) ; MachineOperand * OffsetOp = TII -> getNamedOperand ( MI , <STR_LIT> :: offset ) ; int64_t NewOffset = OffsetOp -> getImm ( ) + Offset ;

assert ( isUInt < <NUM_LIT> > ( NewOffset ) && <STR_LIT> ) ;


<s> if ( spillVGPRtoAGPR ( MI , Index , <NUM_LIT> , Reg -> getReg ( ) , false ) . getInstr ( ) ) return true ; MachineInstrBuilder NewMI = BuildMI ( * MBB , MI , DL , TII -> get ( LoadStoreOp ) ) . add ( * Reg ) . add ( * TII -> getNamedOperand ( * MI , <STR_LIT> :: srsrc ) ) . add ( * TII -> getNamedOperand ( * MI , <STR_LIT> :: soffset ) ) . addImm ( Offset ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . cloneMemRefs ( * MI ) ;

const MachineOperand * VDataIn = TII -> getNamedOperand ( * MI , <STR_LIT> :: vdata_in ) ;


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; const DebugLoc & DL = MI -> getDebugLoc ( ) ; bool IsStore = MI -> mayStore ( ) ; unsigned Opc = MI -> getOpcode ( ) ; int LoadStoreOp = IsStore ? getOffsetMUBUFStore ( Opc ) : getOffsetMUBUFLoad ( Opc ) ; if ( LoadStoreOp == - <NUM_LIT> ) return false ; const MachineOperand * Reg = TII -> getNamedOperand ( * MI , <STR_LIT> :: vdata ) ; if ( spillVGPRtoAGPR ( MI , Index , <NUM_LIT> , Reg -> getReg ( ) , false ) . getInstr ( ) ) return true ; MachineInstrBuilder NewMI = BuildMI ( * MBB , MI , DL , TII -> get ( LoadStoreOp ) ) . add ( * Reg ) . add ( * TII -> getNamedOperand ( * MI , <STR_LIT> :: srsrc ) ) . add ( * TII -> getNamedOperand ( * MI , <STR_LIT> :: soffset ) ) . addImm ( Offset ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . cloneMemRefs ( * MI ) ; const MachineOperand * VDataIn = TII -> getNamedOperand ( * MI , <STR_LIT> :: vdata_in ) ;

if ( VDataIn ) NewMI . add ( * VDataIn ) ;


<s> unsigned Align = MFI . getObjectAlignment ( Index ) ; const MachinePointerInfo & BasePtrInfo = MMO -> getPointerInfo ( ) ; Register TmpReg = hasAGPRs ( RC ) ? TII -> getNamedOperand ( * MI , <STR_LIT> :: tmp ) -> getReg ( ) : Register ( ) ; assert ( ( Offset % EltSize ) == <NUM_LIT> && <STR_LIT> ) ; if ( ! isUInt < <NUM_LIT> > ( Offset + Size - EltSize ) ) { SOffset = <STR_LIT> ; Offset *= ST . getWavefrontSize ( ) ; if ( RS ) SOffset = RS -> scavengeRegister ( & <STR_LIT> , MI , <NUM_LIT> , false ) ; if ( SOffset == <STR_LIT> ) { SOffset = ScratchOffsetReg ; ScratchOffsetRegDelta = Offset ; } else { Scavenged = true ; } BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SOffset ) . addReg ( ScratchOffsetReg ) . addImm ( Offset ) ; Offset = <NUM_LIT> ; } for ( unsigned i = <NUM_LIT> , e = NumSubRegs ; i != e ; ++ i , Offset += EltSize ) { unsigned SubReg = NumSubRegs == <NUM_LIT> ? ValueReg : getSubReg ( ValueReg , getSubRegFromChannel ( i ) ) ; unsigned SOffsetRegState = <NUM_LIT> ; unsigned SrcDstRegState = getDefRegState ( ! IsStore ) ; if ( i + <NUM_LIT> == e ) { SOffsetRegState |= getKillRegState ( Scavenged ) ; SrcDstRegState |= getKillRegState ( IsKill ) ; } auto MIB = spillVGPRtoAGPR ( MI , Index , i , SubReg , IsKill ) ; if ( ! MIB . getInstr ( ) ) { unsigned FinalReg = SubReg ; if ( TmpReg != <STR_LIT> ) { if ( IsStore ) BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , TmpReg ) . addReg ( SubReg , getKillRegState ( IsKill ) ) ; SubReg = TmpReg ; } MachinePointerInfo PInfo = BasePtrInfo . getWithOffset ( EltSize * i ) ; MachineMemOperand * NewMMO = MF -> getMachineMemOperand ( PInfo , MMO -> getFlags ( ) , EltSize , MinAlign ( Align , EltSize * i ) ) ;

MIB = BuildMI ( * MBB , MI , DL , Desc ) . addReg ( SubReg , getDefRegState ( ! IsStore ) | getKillRegState ( IsKill ) ) . addReg ( ScratchRsrcReg ) . addReg ( SOffset , SOffsetRegState ) . addImm ( Offset ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( NewMMO ) ;


<s> if ( Info -> isEntryFunction ( ) ) return false ; return TargetRegisterInfo :: canRealignStack ( MF ) ;


<s> if ( Info -> isEntryFunction ( ) ) return false ;

return TargetRegisterInfo :: canRealignStack ( MF ) ;


<s> const int * PSets = getRegUnitPressureSets ( * U ) ; if ( hasPressureSet ( PSets , PSetID ) ) { PressureSets . set ( PSetID ) ; break ; }


<s> unsigned Reg ; if ( RegCount & <NUM_LIT> ) { Reg = RegCount - <NUM_LIT> ; } else { Reg = RegCount - <NUM_LIT> ; } return Reg ;


<s> if ( RegCount & <NUM_LIT> ) { Reg = RegCount - <NUM_LIT> ; } else { Reg = RegCount - <NUM_LIT> ;


<s> if ( ! LIS -> hasInterval ( Reg ) ) return nullptr ; LiveInterval & LI = LIS -> getInterval ( Reg ) ; LaneBitmask SubLanes = SubReg ? getSubRegIndexLaneMask ( SubReg ) : MRI . getMaxLaneMaskForVReg ( Reg ) ; VNInfo * V = nullptr ; if ( LI . hasSubRanges ( ) ) { for ( auto & S : LI . subranges ( ) ) { if ( ( S . LaneMask & SubLanes ) == SubLanes ) { V = S . getVNInfoAt ( UseIdx ) ; break ; } } } else { V = LI . getVNInfoAt ( UseIdx ) ; } if ( ! V ) return nullptr ; DefIdx = V -> def ; } else { for ( MCRegUnitIterator Units ( Reg , this ) ; Units . isValid ( ) ; ++ Units ) { LiveRange & LR = LIS -> getRegUnit ( * Units ) ; if ( VNInfo * V = LR . getVNInfoAt ( UseIdx ) ) {

if ( ! DefIdx . isValid ( ) || MDT . dominates ( LIS -> getInstructionFromIndex ( DefIdx ) , LIS -> getInstructionFromIndex ( V -> def ) ) ) DefIdx = V -> def ;


<s> if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { if ( ! LIS -> hasInterval ( Reg ) ) return nullptr ; LiveInterval & LI = LIS -> getInterval ( Reg ) ; LaneBitmask SubLanes = SubReg ? getSubRegIndexLaneMask ( SubReg ) : MRI . getMaxLaneMaskForVReg ( Reg ) ; VNInfo * V = nullptr ; if ( LI . hasSubRanges ( ) ) { for ( auto & S : LI . subranges ( ) ) { if ( ( S . LaneMask & SubLanes ) == SubLanes ) { V = S . getVNInfoAt ( UseIdx ) ; break ; } } } else { V = LI . getVNInfoAt ( UseIdx ) ; } if ( ! V ) return nullptr ; DefIdx = V -> def ; } else { for ( MCRegUnitIterator Units ( Reg , this ) ; Units . isValid ( ) ; ++ Units ) { LiveRange & LR = LIS -> getRegUnit ( * Units ) ; if ( VNInfo * V = LR . getVNInfoAt ( UseIdx ) ) { if ( ! DefIdx . isValid ( ) || MDT . dominates ( LIS -> getInstructionFromIndex ( DefIdx ) , LIS -> getInstructionFromIndex ( V -> def ) ) ) DefIdx = V -> def ;


<s> unsigned <ISA_LIT>RegisterInfo :: findUnusedRegister ( const MachineRegisterInfo & MRI , const TargetRegisterClass * RC , const MachineFunction & MF ) const { for ( unsigned Reg : * RC ) if ( MRI . isAllocatable ( Reg ) && ! MRI . isPhysRegUsed ( Reg ) ) return Reg ;


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getConstrainedRegClassForOperand ( const MachineOperand & MO , const MachineRegisterInfo & MRI ) const {

if ( const RegisterBank * RB = MRI . getRegBankOrNull ( MO . getReg ( ) ) ) return getRegClassForTypeOnBank ( MRI . getType ( MO . getReg ( ) ) , * RB , MRI ) ;


<s> case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; default :


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getEquivalentAGPRClass ( const TargetRegisterClass * SRC ) const { switch ( getRegSizeInBits ( * SRC ) ) { case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> :


<s> assert ( Idx == <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: vaddr ) && <STR_LIT> ) ;


<s> unsigned getHWRegIndex ( unsigned Reg ) const { return getEncodingValue ( Reg ) & <NUM_LIT> ;


<s> unsigned getHWRegIndex ( unsigned Reg ) const {

return getEncodingValue ( Reg ) & <NUM_LIT> ;


<s> int64_t <ISA_LIT>RegisterInfo :: getMUBUFInstrOffset ( const MachineInstr * MI ) const { assert ( <ISA_LIT>InstrInfo :: isMUBUF ( * MI ) ) ; int OffIdx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: offset ) ; return MI -> getOperand ( OffIdx ) . getImm ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> :


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPhysRegClass ( unsigned Reg ) const { assert ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) ; static const TargetRegisterClass * const BaseClasses [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , } ; for ( const TargetRegisterClass * BaseClass : BaseClasses ) {


<s> static const TargetRegisterClass * const BaseClasses [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , } ; for ( const TargetRegisterClass * BaseClass : BaseClasses ) { if ( BaseClass -> contains ( Reg ) ) {


<s> return isWave32 ? & <STR_LIT> : & <STR_LIT> ; case - <NUM_LIT> : return nullptr ; default :

return <ISA_LIT>RegisterInfo :: getRegClass ( RCID ) ;


<s> if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) return MRI . getRegClass ( Reg ) ; return getPhysRegClass ( Reg ) ;


<s> return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> :


<s> return <ISA_LIT>RegisterInfo :: getRegPressureLimit ( RC , MF ) ; case <STR_LIT> : return std :: min ( ST . getMaxNumVGPRs ( Occupancy ) , ST . getMaxNumVGPRs ( MF ) ) ; case <STR_LIT> : return std :: min ( ST . getMaxNumSGPRs ( Occupancy , true ) , ST . getMaxNumSGPRs ( MF ) ) ; }


<s> unsigned Occupancy = ST . getOccupancyWithLocalMemSize ( MFI -> getLDSSize ( ) , MF . getFunction ( ) ) ; switch ( RC -> getID ( ) ) { default : return <ISA_LIT>RegisterInfo :: getRegPressureLimit ( RC , MF ) ;


<s> if ( Idx == getSGPRPressureSet ( ) ) return getRegPressureLimit ( & <STR_LIT> , const_cast < MachineFunction & > ( MF ) ) ; return <ISA_LIT>RegisterInfo :: getRegPressureSetLimit ( MF , Idx ) ;


<s> static const int16_t Sub0_2 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; static const int16_t Sub0_1 [ ] = { <STR_LIT> , <STR_LIT> , } ; switch ( <STR_LIT> ( * RC -> MC ) ) { case <NUM_LIT> : return { } ; case <NUM_LIT> : return makeArrayRef ( Sub0_1 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_2 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_3 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_4 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_7 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_15 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_31 ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } if ( EltSize == <NUM_LIT> ) { static const int16_t Sub0_31_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const int16_t Sub0_15_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const int16_t Sub0_7_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const int16_t Sub0_3_64 [ ] = { <STR_LIT> , <STR_LIT> } ; switch ( <STR_LIT> ( * RC -> MC ) ) { case <NUM_LIT> : return { } ; case <NUM_LIT> : return makeArrayRef ( Sub0_3_64 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_7_64 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_15_64 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_31_64 ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } if ( EltSize == <NUM_LIT> ) { static const int16_t Sub0_31_128 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const int16_t Sub0_15_128 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const int16_t Sub0_7_128 [ ] = { <STR_LIT> , <STR_LIT> } ; switch ( <STR_LIT> ( * RC -> MC ) ) { case <NUM_LIT> : return { } ; case <NUM_LIT> : return makeArrayRef ( Sub0_7_128 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_15_128 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_31_128 ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } assert ( EltSize == <NUM_LIT> && <STR_LIT> ) ; static const int16_t Sub0_31_256 [ ] = {


<s> if ( hasRegUnit ( <STR_LIT> , RegUnit ) ) return Empty ;

return <ISA_LIT>RegisterInfo :: getRegUnitPressureSets ( RegUnit ) ;


<s> reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; if ( isWave32 ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ;

assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg ) ) ;


<s> if ( SuperRegSize % <NUM_LIT> == <NUM_LIT> ) { return { <NUM_LIT> , Store ? <STR_LIT> : <STR_LIT> } ; } return { <NUM_LIT> , Store ? <STR_LIT> :


<s> return & <STR_LIT> ; case <NUM_LIT> : default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( hasAGPRs ( RC ) ) { switch ( Count ) { case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : default : llvm_unreachable ( <STR_LIT> ) ; } } else { switch ( Count ) { case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ;


<s> if ( PSets [ i ] == ( int ) PSetID ) return true ; } return false ;


<s> assert ( RC && <STR_LIT> ) ; return hasAGPRs ( RC ) ;


<s> int64_t NewOffset = Offset + getMUBUFInstrOffset ( MI ) ; return isUInt < <NUM_LIT> > ( NewOffset ) ;


<s> bool <ISA_LIT>RegisterInfo :: isFrameOffsetLegal ( const MachineInstr * MI , unsigned BaseReg , int64_t Offset ) const { if ( ! <ISA_LIT>InstrInfo :: isMUBUF ( * MI ) ) return false ; int64_t NewOffset = Offset + getMUBUFInstrOffset ( MI ) ; return isUInt < <NUM_LIT> > ( NewOffset ) ;


<s> bool isSGPRPressureSet ( unsigned SetID ) const {

return SGPRPressureSets . test ( SetID ) && ! VGPRPressureSets . test ( SetID ) ;


<s> bool isSGPRPressureSet ( unsigned SetID ) const { return SGPRPressureSets . test ( SetID ) && ! VGPRPressureSets . test ( SetID ) ;


<s> if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) RC = MRI . getRegClass ( Reg ) ; else RC = getPhysRegClass ( Reg ) ;


<s> const TargetRegisterClass * RC ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) RC = MRI . getRegClass ( Reg ) ; else RC = getPhysRegClass ( Reg ) ; return isSGPRClass ( RC ) ;


<s> assert ( RC && <STR_LIT> ) ; return hasVGPRs ( RC ) ;


<s> return VGPRPressureSets . test ( SetID ) && ! SGPRPressureSets . test ( SetID ) ;


<s> bool isVGPRPressureSet ( unsigned SetID ) const {

return VGPRPressureSets . test ( SetID ) && ! SGPRPressureSets . test ( SetID ) ;


<s> const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; if ( Offset == <NUM_LIT> ) { BuildMI ( * MBB , Ins , DL , TII -> get ( <STR_LIT> ) , BaseReg ) . addFrameIndex ( FrameIdx ) ; return ; } MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned OffsetReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned FIReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , Ins , DL , TII -> get ( <STR_LIT> ) , OffsetReg ) . addImm ( Offset ) ;

BuildMI ( * MBB , Ins , DL , TII -> get ( <STR_LIT> ) , FIReg ) . addFrameIndex ( FrameIdx ) ;


<s> if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const GCNSubtarget & Subtarget = MF -> getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; if ( Offset == <NUM_LIT> ) { BuildMI ( * MBB , Ins , DL , TII -> get ( <STR_LIT> ) , BaseReg ) . addFrameIndex ( FrameIdx ) ;


<s> int64_t FullOffset = Offset + getMUBUFInstrOffset ( MI ) ; return ! isUInt < <NUM_LIT> > ( FullOffset ) ;


<s> return OpType >= <STR_LIT> && OpType <= <STR_LIT> ;


<s> bool opCanUseLiteralConstant ( unsigned OpType ) const {

return OpType >= <STR_LIT> && OpType <= <STR_LIT> ;


<s> if ( ! MFI . hasStackObjects ( ) ) return false ; if ( ! isUInt < <NUM_LIT> > ( MFI . getStackSize ( ) ) ) return true ;

return MF . getSubtarget < GCNSubtarget > ( ) . hasScalarStores ( ) && MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> hasSpilledSGPRs ( ) ;


<s> if ( ! isUInt < <NUM_LIT> > ( MFI . getStackSize ( ) ) ) return true ;


<s> bool <ISA_LIT>RegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;

if ( MFI . hasStackObjects ( ) ) return true ;


<s> const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: reservedPrivateSegmentBufferReg ( const MachineFunction & MF ) const {

const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ;


<s> unsigned BaseIdx = alignDown ( ST . getMaxNumSGPRs ( MF ) , <NUM_LIT> ) - <NUM_LIT> ; unsigned BaseReg ( <STR_LIT> . getRegister ( BaseIdx ) ) ; return getMatchingSuperReg ( BaseReg , <STR_LIT> , & <STR_LIT> ) ;


<s> const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ;


<s> const GCNSubtarget & Subtarget = MF -> getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; bool SeenFI = false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( MO . isFI ( ) ) { if ( SeenFI ) llvm_unreachable ( <STR_LIT> ) ; SeenFI = true ; } } MachineOperand * FIOp = TII -> getNamedOperand ( MI , <STR_LIT> :: vaddr ) ; assert ( FIOp && FIOp -> isFI ( ) && <STR_LIT> ) ; assert ( TII -> isMUBUF ( MI ) ) ; assert ( TII -> getNamedOperand ( MI , <STR_LIT> :: soffset ) -> getReg ( ) == MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getFrameOffsetReg ( ) && <STR_LIT> ) ; MachineOperand * OffsetOp = TII -> getNamedOperand ( MI , <STR_LIT> :: offset ) ; int64_t NewOffset = OffsetOp -> getImm ( ) + Offset ;

assert ( isUInt < <NUM_LIT> > ( NewOffset ) && <STR_LIT> ) ;


<s> if ( SpillToVGPR ) { <ISA_LIT>MachineFunctionInfo :: SpilledReg Spill = VGPRSpills [ i ] ; auto MIB = BuildMI ( * MBB , MI , DL , TII -> getMCOpcodeFromPseudo ( <STR_LIT> ) , SubReg ) . addReg ( Spill . VGPR ) . addImm ( Spill . Lane ) ; if ( NumSubRegs > <NUM_LIT> && i == <NUM_LIT> ) MIB . addReg ( SuperReg , RegState :: ImplicitDefine ) ; } else { if ( OnlyToVGPR ) return false ; unsigned TmpReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned Align = FrameInfo . getObjectAlignment ( Index ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , Index , EltSize * i ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad , EltSize , MinAlign ( Align , EltSize * i ) ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , TmpReg ) . addFrameIndex ( Index ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI -> getStackPtrOffsetReg ( ) ) . addImm ( i * <NUM_LIT> ) . addMemOperand ( MMO ) ; auto MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SubReg ) . addReg ( TmpReg , RegState :: Kill ) ; if ( NumSubRegs > <NUM_LIT> ) MIB . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , RegState :: ImplicitDefine ) ; } } if ( M0CopyReg != <STR_LIT> ) { BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( M0CopyReg , RegState :: Kill ) ;


<s> } } unsigned VGPRMax = <NUM_LIT> , SGPRMax = <NUM_LIT> , AGPRMax = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumRegPressureSets ; ++ i ) { if ( isVGPRPressureSet ( i ) && PressureSetRegUnits [ i ] > VGPRMax ) { VGPRSetID = i ; VGPRMax = PressureSetRegUnits [ i ] ; continue ; } if ( isSGPRPressureSet ( i ) && PressureSetRegUnits [ i ] > SGPRMax ) { SGPRSetID = i ; SGPRMax = PressureSetRegUnits [ i ] ; } if ( isAGPRPressureSet ( i ) && PressureSetRegUnits [ i ] > AGPRMax ) { AGPRSetID = i ; AGPRMax = PressureSetRegUnits [ i ] ; continue ; } }

assert ( SGPRSetID < NumRegPressureSets && VGPRSetID < NumRegPressureSets && AGPRSetID < NumRegPressureSets ) ;


<s> bool VGPRDefined = true ; if ( MBB == & MF -> front ( ) ) VGPRDefined = ! SGPRSpillVGPRDefinedSet . insert ( Spill . VGPR ) . second ; BuildMI ( * MBB , MI , DL , TII -> getMCOpcodeFromPseudo ( <STR_LIT> ) , Spill . VGPR ) . addReg ( SubReg , getKillRegState ( IsKill ) ) . addImm ( Spill . Lane ) . addReg ( Spill . VGPR , VGPRDefined ? <NUM_LIT> : RegState :: Undef ) ; } else { if ( OnlyToVGPR ) return false ; unsigned TmpReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstrBuilder Mov = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , TmpReg ) . addReg ( SubReg , SubKillState ) ; if ( NumSubRegs > <NUM_LIT> ) { unsigned SuperKillState = <NUM_LIT> ; if ( i + <NUM_LIT> == e ) SuperKillState |= getKillRegState ( IsKill ) ; Mov . addReg ( SuperReg , RegState :: Implicit | SuperKillState ) ; } unsigned Align = FrameInfo . getObjectAlignment ( Index ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , Index , EltSize * i ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , EltSize , MinAlign ( Align , EltSize * i ) ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( TmpReg , RegState :: Kill ) . addFrameIndex ( Index ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI -> getStackPtrOffsetReg ( ) ) . addImm ( i * <NUM_LIT> ) . addMemOperand ( MMO ) ; } } if ( M0CopyReg != <STR_LIT> ) { BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( M0CopyReg , RegState :: Kill ) ; } MI -> eraseFromParent ( ) ; MFI -> addToSpilledSGPRs ( NumSubRegs ) ; return true ;


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const {


<s> int LoadStoreOp = IsStore ? getOffsetMUBUFStore ( Opc ) : getOffsetMUBUFLoad ( Opc ) ; if ( LoadStoreOp == - <NUM_LIT> ) return false ; const MachineOperand * Reg = TII -> getNamedOperand ( * MI , <STR_LIT> :: vdata ) ; MachineInstrBuilder NewMI = BuildMI ( * MBB , MI , DL , TII -> get ( LoadStoreOp ) ) . add ( * Reg ) . add ( * TII -> getNamedOperand ( * MI , <STR_LIT> :: srsrc ) ) . add ( * TII -> getNamedOperand ( * MI , <STR_LIT> :: soffset ) ) . addImm ( Offset ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . cloneMemRefs ( * MI ) ; const MachineOperand * VDataIn = TII -> getNamedOperand ( * MI , <STR_LIT> :: vdata_in ) ; if ( VDataIn ) NewMI . add ( * VDataIn ) ;


<s> & <STR_LIT> ; case <NUM_LIT> : return RB -> getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB -> getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB -> getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB -> getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB -> getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; default :


<s> switch ( getRegSizeInBits ( * VRC ) ) { case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> :


<s> case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPhysRegClass ( unsigned Reg ) const { assert ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) ; static const TargetRegisterClass * const BaseClasses [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , } ; for ( const TargetRegisterClass * BaseClass : BaseClasses ) { if ( BaseClass -> contains ( Reg ) ) { return BaseClass ;


<s> StringRef <ISA_LIT>RegisterInfo :: getRegAsmName ( unsigned Reg ) const { if ( Reg >= BeginReg && Reg <= EndReg ) { \ unsigned Index = Reg - BeginReg ; \ assert ( Index < array_lengthof ( RegTable ) ) ; \ return RegTable [ Index ] ; \ } REG_RANGE ( <STR_LIT> , <STR_LIT> , VGPR32RegNames ) ; REG_RANGE ( <STR_LIT> , <STR_LIT> , SGPR32RegNames ) ; REG_RANGE ( <STR_LIT> , <STR_LIT> , VGPR64RegNames ) ; REG_RANGE ( <STR_LIT> , <STR_LIT> , SGPR64RegNames ) ; REG_RANGE ( <STR_LIT> , <STR_LIT> , VGPR96RegNames ) ; REG_RANGE ( <STR_LIT> , <STR_LIT> , VGPR128RegNames ) ; REG_RANGE ( <STR_LIT> , <STR_LIT> , SGPR128RegNames ) ;


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; static const int16_t Sub0_1 [ ] = { <STR_LIT> , <STR_LIT> , } ; switch ( <STR_LIT> ( * RC -> MC ) ) { case <NUM_LIT> : return { } ; case <NUM_LIT> : return makeArrayRef ( Sub0_1 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_2 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_3 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_4 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_7 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_15 ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } if ( EltSize == <NUM_LIT> ) { static const int16_t Sub0_15_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const int16_t Sub0_7_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const int16_t Sub0_3_64 [ ] = { <STR_LIT> , <STR_LIT> } ; switch ( <STR_LIT> ( * RC -> MC ) ) { case <NUM_LIT> : return { } ; case <NUM_LIT> : return makeArrayRef ( Sub0_3_64 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_7_64 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_15_64 ) ; default : llvm_unreachable ( <STR_LIT> ) ; } }

assert ( EltSize == <NUM_LIT> && <STR_LIT> ) ;


<s> reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; if ( isWave32 ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg ) ) ; } unsigned StackPtrReg = MFI -> getStackPtrOffsetReg ( ) ; if ( StackPtrReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , StackPtrReg ) ;

assert ( ! isSubRegister ( ScratchRSrcReg , StackPtrReg ) ) ;


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; if ( isWave32 ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ;

unsigned TotalNumVGPRs = <STR_LIT> . getNumRegs ( ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; } } else { switch ( Count ) { case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : default : llvm_unreachable ( <STR_LIT> ) ; } }


<s> case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> :


<s> return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ;


<s> classifyPressureSet ( i , <STR_LIT> , SGPRPressureSets ) ; classifyPressureSet ( i , <STR_LIT> , VGPRPressureSets ) ; } std :: vector < unsigned > PressureSetRegUnits ( NumRegPressureSets , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = getNumRegUnits ( ) ; i != e ; ++ i ) { const int * PSets = getRegUnitPressureSets ( i ) ; for ( unsigned j = <NUM_LIT> ; PSets [ j ] != - <NUM_LIT> ; ++ j ) { ++ PressureSetRegUnits [ PSets [ j ] ] ; } } unsigned VGPRMax = <NUM_LIT> , SGPRMax = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumRegPressureSets ; ++ i ) { if ( isVGPRPressureSet ( i ) && PressureSetRegUnits [ i ] > VGPRMax ) { VGPRSetID = i ; VGPRMax = PressureSetRegUnits [ i ] ; continue ; } if ( isSGPRPressureSet ( i ) && PressureSetRegUnits [ i ] > SGPRMax ) { SGPRSetID = i ;


<s> const int * PSets = getRegUnitPressureSets ( i ) ; for ( unsigned j = <NUM_LIT> ; PSets [ j ] != - <NUM_LIT> ; ++ j ) { ++ PressureSetRegUnits [ PSets [ j ] ] ; } } unsigned VGPRMax = <NUM_LIT> , SGPRMax = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumRegPressureSets ; ++ i ) { if ( isVGPRPressureSet ( i ) && PressureSetRegUnits [ i ] > VGPRMax ) { VGPRSetID = i ; VGPRMax = PressureSetRegUnits [ i ] ; continue ; } if ( isSGPRPressureSet ( i ) && PressureSetRegUnits [ i ] > SGPRMax ) { SGPRSetID = i ; SGPRMax = PressureSetRegUnits [ i ] ; }


<s> BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , OffsetReg ) . addReg ( FrameReg ) ; } BuildMI ( * MBB , MI , DL , TII -> get ( ScalarStoreOp ) ) . addReg ( SubReg , getKillRegState ( IsKill ) ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( OffsetReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; continue ; } if ( SpillToVGPR ) { <ISA_LIT>MachineFunctionInfo :: SpilledReg Spill = VGPRSpills [ i ] ; bool VGPRDefined = true ; if ( MBB == & MF -> front ( ) ) VGPRDefined = ! SGPRSpillVGPRDefinedSet . insert ( Spill . VGPR ) . second ; BuildMI ( * MBB , MI , DL , TII -> getMCOpcodeFromPseudo ( <STR_LIT> ) , Spill . VGPR ) . addReg ( SubReg , getKillRegState ( IsKill ) ) . addImm ( Spill . Lane ) . addReg ( Spill . VGPR , VGPRDefined ? <NUM_LIT> : RegState :: Undef ) ; } else { if ( OnlyToVGPR ) return false ; unsigned TmpReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstrBuilder Mov = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , TmpReg ) . addReg ( SubReg , SubKillState ) ; if ( NumSubRegs > <NUM_LIT> ) { unsigned SuperKillState = <NUM_LIT> ; if ( i + <NUM_LIT> == e ) SuperKillState |= getKillRegState ( IsKill ) ; Mov . addReg ( SuperReg , RegState :: Implicit | SuperKillState ) ; } unsigned Align = FrameInfo . getObjectAlignment ( Index ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , Index , EltSize * i ) ;

MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , EltSize , MinAlign ( Align , EltSize * i ) ) ;


<s> M0CopyReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , M0CopyReg ) . addReg ( <STR_LIT> ) ; } } unsigned ScalarStoreOp ; unsigned EltSize = <NUM_LIT> ; const TargetRegisterClass * RC = getPhysRegClass ( SuperReg ) ; if ( SpillToSMEM && isSGPRClass ( RC ) ) { std :: tie ( EltSize , ScalarStoreOp ) = getSpillEltSize ( getRegSizeInBits ( * RC ) / <NUM_LIT> , true ) ; } ArrayRef < int16_t > SplitParts = getRegSplitParts ( RC , EltSize ) ; unsigned NumSubRegs = SplitParts . empty ( ) ? <NUM_LIT> : SplitParts . size ( ) ; unsigned SubKillState = getKillRegState ( ( NumSubRegs == <NUM_LIT> ) && IsKill ) ; for ( unsigned i = <NUM_LIT> , e = NumSubRegs ; i < e ; ++ i ) { unsigned SubReg = NumSubRegs == <NUM_LIT> ? SuperReg : getSubReg ( SuperReg , SplitParts [ i ] ) ; if ( SpillToSMEM ) { int64_t FrOffset = FrameInfo . getObjectOffset ( Index ) ; unsigned Align = FrameInfo . getObjectAlignment ( Index ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , Index , EltSize * i ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , EltSize , MinAlign ( Align , EltSize * i ) ) ; int64_t Offset = ( ST . getWavefrontSize ( ) * FrOffset ) + ( EltSize * i ) ; if ( Offset != <NUM_LIT> ) { BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , OffsetReg ) . addReg ( FrameReg ) . addImm ( Offset ) ; } else { BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , OffsetReg ) . addReg ( FrameReg ) ;


<s> const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; const DebugLoc & DL = MI -> getDebugLoc ( ) ; bool IsStore = MI -> mayStore ( ) ; unsigned Opc = MI -> getOpcode ( ) ; int LoadStoreOp = IsStore ? getOffsetMUBUFStore ( Opc ) : getOffsetMUBUFLoad ( Opc ) ; if ( LoadStoreOp == - <NUM_LIT> ) return false ; const MachineOperand * Reg = TII -> getNamedOperand ( * MI , <STR_LIT> :: vdata ) ;

if ( spillVGPRtoAGPR ( ST , MI , Index , <NUM_LIT> , Reg -> getReg ( ) , false ) . getInstr ( ) ) return true ;


<s> unsigned NumSubRegs = <STR_LIT> ( RC -> getID ( ) ) / ( EltSize * CHAR_BIT ) ; unsigned Size = NumSubRegs * EltSize ; int64_t Offset = InstOffset + MFI . getObjectOffset ( Index ) ; int64_t ScratchOffsetRegDelta = <NUM_LIT> ; unsigned Align = MFI . getObjectAlignment ( Index ) ; const MachinePointerInfo & BasePtrInfo = MMO -> getPointerInfo ( ) ; Register TmpReg = hasAGPRs ( RC ) ? TII -> getNamedOperand ( * MI , <STR_LIT> :: tmp ) -> getReg ( ) : Register ( ) ; assert ( ( Offset % EltSize ) == <NUM_LIT> && <STR_LIT> ) ; if ( ! isUInt < <NUM_LIT> > ( Offset + Size - EltSize ) ) { SOffset = <STR_LIT> ; Offset *= ST . getWavefrontSize ( ) ; if ( RS ) SOffset = RS -> scavengeRegister ( & <STR_LIT> , MI , <NUM_LIT> , false ) ; if ( SOffset == <STR_LIT> ) { SOffset = ScratchOffsetReg ; ScratchOffsetRegDelta = Offset ; } else { Scavenged = true ; } BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SOffset ) . addReg ( ScratchOffsetReg ) . addImm ( Offset ) ; Offset = <NUM_LIT> ; } for ( unsigned i = <NUM_LIT> , e = NumSubRegs ; i != e ; ++ i , Offset += EltSize ) { Register SubReg = NumSubRegs == <NUM_LIT> ? Register ( ValueReg ) : getSubReg ( ValueReg , getSubRegFromChannel ( i ) ) ; unsigned SOffsetRegState = <NUM_LIT> ; unsigned SrcDstRegState = getDefRegState ( ! IsStore ) ; if ( i + <NUM_LIT> == e ) { SOffsetRegState |= getKillRegState ( Scavenged ) ; SrcDstRegState |= getKillRegState ( IsKill ) ; } auto MIB = spillVGPRtoAGPR ( ST , MI , Index , i , SubReg , IsKill ) ; if ( ! MIB . getInstr ( ) ) {


<s> return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> :


<s> reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; if ( isWave32 ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } if ( ! ST . hasMAIInsts ( ) ) { for ( unsigned i = <NUM_LIT> ; i < MaxNumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } } const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg ) ) ; } unsigned StackPtrReg = MFI -> getStackPtrOffsetReg ( ) ; if ( StackPtrReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , StackPtrReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , StackPtrReg ) ) ; } unsigned FrameReg = MFI -> getFrameOffsetReg ( ) ; if ( FrameReg != <STR_LIT> ) {

reserveRegisterTuples ( Reserved , FrameReg ) ;


<s> reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; if ( isWave32 ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } if ( ! ST . hasMAIInsts ( ) ) { for ( unsigned i = <NUM_LIT> ; i < MaxNumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } } const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != <STR_LIT> ) {

reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ;


<s> MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; if ( Offset == <NUM_LIT> ) { BuildMI ( * MBB , Ins , DL , TII -> get ( <STR_LIT> ) , BaseReg ) . addFrameIndex ( FrameIdx ) ; return ; }

MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ;


<s> unsigned BaseIdx = alignDown ( ST . getMaxNumSGPRs ( MF ) , <NUM_LIT> ) - <NUM_LIT> ;

unsigned BaseReg ( <STR_LIT> . getRegister ( BaseIdx ) ) ;


return <STR_LIT> . getRegister ( Reg ) ;


<s> assert ( TII -> getNamedOperand ( MI , <STR_LIT> :: soffset ) -> getReg ( ) == MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getStackPtrOffsetReg ( ) && <STR_LIT> ) ; MachineOperand * OffsetOp = TII -> getNamedOperand ( MI , <STR_LIT> :: offset ) ; int64_t NewOffset = OffsetOp -> getImm ( ) + Offset ; assert ( isUInt < <NUM_LIT> > ( NewOffset ) && <STR_LIT> ) ;

FIOp -> ChangeToRegister ( BaseReg , false ) ;


<s> SeenFI = true ; } } MachineOperand * FIOp = TII -> getNamedOperand ( MI , <STR_LIT> :: vaddr ) ; MachineBasicBlock * MBB = MI . getParent ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; assert ( FIOp && FIOp -> isFI ( ) && <STR_LIT> ) ; assert ( TII -> isMUBUF ( MI ) ) ; assert ( TII -> getNamedOperand ( MI , <STR_LIT> :: soffset ) -> getReg ( ) == MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getStackPtrOffsetReg ( ) && <STR_LIT> ) ;

MachineOperand * OffsetOp = TII -> getNamedOperand ( MI , <STR_LIT> :: offset ) ;


<s> if ( OnlyToVGPR && ! SpillToVGPR ) return false ; MachineFrameInfo & FrameInfo = MF -> getFrameInfo ( ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; const DebugLoc & DL = MI -> getDebugLoc ( ) ; Register SuperReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( SuperReg != <STR_LIT> && <STR_LIT> ) ; unsigned EltSize = <NUM_LIT> ; const TargetRegisterClass * RC = getPhysRegClass ( SuperReg ) ; ArrayRef < int16_t > SplitParts = getRegSplitParts ( RC , EltSize ) ; unsigned NumSubRegs = SplitParts . empty ( ) ? <NUM_LIT> : SplitParts . size ( ) ; Register TmpVGPR ; for ( unsigned i = <NUM_LIT> , e = NumSubRegs ; i < e ; ++ i ) { Register SubReg = NumSubRegs == <NUM_LIT> ? SuperReg : getSubReg ( SuperReg , SplitParts [ i ] ) ; if ( SpillToVGPR ) { <ISA_LIT>MachineFunctionInfo :: SpilledReg Spill = VGPRSpills [ i ] ; auto MIB = BuildMI ( * MBB , MI , DL , TII -> getMCOpcodeFromPseudo ( <STR_LIT> ) , SubReg ) . addReg ( Spill . VGPR ) . addImm ( Spill . Lane ) ; if ( NumSubRegs > <NUM_LIT> && i == <NUM_LIT> ) MIB . addReg ( SuperReg , RegState :: ImplicitDefine ) ; } else { if ( OnlyToVGPR ) return false ; if ( ! TmpVGPR . isValid ( ) ) TmpVGPR = RS -> scavengeRegister ( & <STR_LIT> , MI , <NUM_LIT> ) ; unsigned Align = FrameInfo . getObjectAlignment ( Index ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , Index , EltSize * i ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad , EltSize , MinAlign ( Align , EltSize * i ) ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , TmpVGPR ) . addFrameIndex ( Index ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI -> getStackPtrOffsetReg ( ) ) . addImm ( i * <NUM_LIT> ) . addMemOperand ( MMO ) ; auto MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SubReg ) . addReg ( TmpVGPR , RegState :: Kill ) ; if ( NumSubRegs > <NUM_LIT> ) MIB . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , RegState :: ImplicitDefine ) ;


<s> classifyPressureSet ( i , <STR_LIT> , SGPRPressureSets ) ; classifyPressureSet ( i , <STR_LIT> , VGPRPressureSets ) ; classifyPressureSet ( i , <STR_LIT> , AGPRPressureSets ) ; } std :: vector < unsigned > PressureSetRegUnits ( NumRegPressureSets , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = getNumRegUnits ( ) ; i != e ; ++ i ) { const int * PSets = getRegUnitPressureSets ( i ) ; for ( unsigned j = <NUM_LIT> ; PSets [ j ] != - <NUM_LIT> ; ++ j ) { ++ PressureSetRegUnits [ PSets [ j ] ] ; } } unsigned VGPRMax = <NUM_LIT> , SGPRMax = <NUM_LIT> , AGPRMax = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumRegPressureSets ; ++ i ) { if ( isVGPRPressureSet ( i ) && PressureSetRegUnits [ i ] > VGPRMax ) { VGPRSetID = i ; VGPRMax = PressureSetRegUnits [ i ] ; continue ; }

if ( isSGPRPressureSet ( i ) && PressureSetRegUnits [ i ] > SGPRMax ) {


<s> <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; DenseSet < unsigned > SGPRSpillVGPRDefinedSet ; ArrayRef < <ISA_LIT>MachineFunctionInfo :: SpilledReg > VGPRSpills = MFI -> getSGPRToVGPRSpills ( Index ) ; bool SpillToVGPR = ! VGPRSpills . empty ( ) ; if ( OnlyToVGPR && ! SpillToVGPR ) return false ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; Register SuperReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; const DebugLoc & DL = MI -> getDebugLoc ( ) ; MachineFrameInfo & FrameInfo = MF -> getFrameInfo ( ) ; assert ( SpillToVGPR || ( SuperReg != MFI -> getStackPtrOffsetReg ( ) && SuperReg != MFI -> getFrameOffsetReg ( ) && SuperReg != MFI -> getScratchWaveOffsetReg ( ) ) ) ; assert ( SuperReg != <STR_LIT> && <STR_LIT> ) ; unsigned EltSize = <NUM_LIT> ; const TargetRegisterClass * RC = getPhysRegClass ( SuperReg ) ; ArrayRef < int16_t > SplitParts = getRegSplitParts ( RC , EltSize ) ; unsigned NumSubRegs = SplitParts . empty ( ) ? <NUM_LIT> : SplitParts . size ( ) ; Register TmpVGPR ; unsigned SubKillState = getKillRegState ( ( NumSubRegs == <NUM_LIT> ) && IsKill ) ; for ( unsigned i = <NUM_LIT> , e = NumSubRegs ; i < e ; ++ i ) {

Register SubReg = NumSubRegs == <NUM_LIT> ? SuperReg : getSubReg ( SuperReg , SplitParts [ i ] ) ;


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; MCPhysReg Reg = MFI -> getVGPRToAGPRSpill ( Index , Lane ) ; if ( Reg == <STR_LIT> ) return MachineInstrBuilder ( ) ; bool IsStore = MI -> mayStore ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; auto * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( MRI . getTargetRegisterInfo ( ) ) ; unsigned Dst = IsStore ? Reg : ValueReg ; unsigned Src = IsStore ? ValueReg : Reg ; unsigned Opc = ( IsStore ^ TRI -> isVGPR ( MRI , Reg ) ) ? <STR_LIT> : <STR_LIT> ;

return BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( Opc ) , Dst ) . addReg ( Src , getKillRegState ( IsKill ) ) ;


<s> MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; MCPhysReg Reg = MFI -> getVGPRToAGPRSpill ( Index , Lane ) ; if ( Reg == <STR_LIT> ) return MachineInstrBuilder ( ) ; bool IsStore = MI -> mayStore ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; auto * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( MRI . getTargetRegisterInfo ( ) ) ; unsigned Dst = IsStore ? Reg : ValueReg ; unsigned Src = IsStore ? ValueReg : Reg ;

unsigned Opc = ( IsStore ^ TRI -> isVGPR ( MRI , Reg ) ) ? <STR_LIT> : <STR_LIT> ;


<s> for ( ; ExecLane < ( NumSubRegs - <NUM_LIT> ) ; ++ ExecLane ) { SavedExecReg = getMatchingSuperReg ( getSubReg ( SuperReg , SplitParts [ FirstPart + ExecLane ] ) , <STR_LIT> , & <STR_LIT> ) ; if ( SavedExecReg ) break ; } } assert ( SavedExecReg ) ; BuildMI ( * MBB , MI , DL , TII -> get ( ExecMovOpc ) , SavedExecReg ) . addReg ( ExecReg ) ; BuildMI ( * MBB , MI , DL , TII -> get ( ExecMovOpc ) , ExecReg ) . addImm ( VGPRLanes ) ; MachineFrameInfo & FrameInfo = MF -> getFrameInfo ( ) ; assert ( FrameInfo . getStackID ( Index ) != TargetStackID :: SGPRSpill ) ; Register FrameReg = FrameInfo . isFixedObjectIndex ( Index ) && hasBasePointer ( * MF ) ? getBaseRegister ( ) : getFrameRegister ( * MF ) ; Align Alignment = FrameInfo . getObjectAlign ( Index ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , Index ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , IsLoad ? MachineMemOperand :: MOLoad : MachineMemOperand :: MOStore , EltSize , Alignment ) ; if ( IsLoad ) { buildSpillLoadStore ( MI , <STR_LIT> , Index , VGPR , false , MFI -> getScratchRSrcReg ( ) , FrameReg , Offset * EltSize , MMO , RS ) ; } else { buildSpillLoadStore ( MI , <STR_LIT> , Index , VGPR , IsKill , MFI -> getScratchRSrcReg ( ) , FrameReg , Offset * EltSize , MMO , RS ) ; MFI -> addToSpilledVGPRs ( <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return restoreSGPR ( MI , FI , RS , true ) ; default : llvm_unreachable ( <STR_LIT> ) ;