<s> if ( findChainOperand ( Load0 ) != findChainOperand ( Load1 ) ) return false ; Offset0 = Load0Offset -> getZExtValue ( ) ; Offset1 = Load1Offset -> getZExtValue ( ) ; return true ; } if ( ( isMUBUF ( Opc0 ) || isMTBUF ( Opc0 ) ) && ( isMUBUF ( Opc1 ) || isMTBUF ( Opc1 ) ) ) { if ( ! nodesHaveSameOperandValue ( Load0 , Load1 , <STR_LIT> :: soffset ) || findChainOperand ( Load0 ) != findChainOperand ( Load1 ) || ! nodesHaveSameOperandValue ( Load0 , Load1 , <STR_LIT> :: vaddr ) || ! nodesHaveSameOperandValue ( Load0 , Load1 , <STR_LIT> :: srsrc ) ) return false ; int OffIdx0 = <STR_LIT> ( Opc0 , <STR_LIT> :: offset ) ; int OffIdx1 = <STR_LIT> ( Opc1 , <STR_LIT> :: offset ) ; if ( OffIdx0 == - <NUM_LIT> || OffIdx1 == - <NUM_LIT> ) return false ; -- OffIdx0 ; -- OffIdx1 ; SDValue Off0 = Load0 -> getOperand ( OffIdx0 ) ; SDValue Off1 = Load1 -> getOperand ( OffIdx1 ) ;

if ( ! isa < ConstantSDNode > ( Off0 ) || ! isa < ConstantSDNode > ( Off1 ) ) return false ;


<s> bool <ISA_LIT>InstrInfo :: areMemAccessesTriviallyDisjoint ( MachineInstr * MIa , MachineInstr * MIb , AliasAnalysis * AA ) const { assert ( MIa && ( MIa -> mayLoad ( ) || MIa -> mayStore ( ) ) && <STR_LIT> ) ; assert ( MIb && ( MIb -> mayLoad ( ) || MIb -> mayStore ( ) ) && <STR_LIT> ) ; if ( MIa -> hasUnmodeledSideEffects ( ) || MIb -> hasUnmodeledSideEffects ( ) ) return false ; if ( MIa -> hasOrderedMemoryRef ( ) || MIb -> hasOrderedMemoryRef ( ) ) return false ; if ( isDS ( * MIa ) ) { if ( isDS ( * MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( * MIb ) ; } if ( isMUBUF ( * MIa ) || isMTBUF ( * MIa ) ) { if ( isMUBUF ( * MIb ) || isMTBUF ( * MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( * MIb ) && ! isSMRD ( * MIb ) ; } if ( isSMRD ( * MIa ) ) {

if ( isSMRD ( * MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ;


<s> if ( MIa -> hasUnmodeledSideEffects ( ) || MIb -> hasUnmodeledSideEffects ( ) ) return false ; if ( MIa -> hasOrderedMemoryRef ( ) || MIb -> hasOrderedMemoryRef ( ) ) return false ; if ( isDS ( * MIa ) ) { if ( isDS ( * MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( * MIb ) ; } if ( isMUBUF ( * MIa ) || isMTBUF ( * MIa ) ) { if ( isMUBUF ( * MIb ) || isMTBUF ( * MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( * MIb ) && ! isSMRD ( * MIb ) ; } if ( isSMRD ( * MIa ) ) { if ( isSMRD ( * MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( * MIb ) && ! isMUBUF ( * MIa ) && ! isMTBUF ( * MIa ) ; } if ( isFLAT ( * MIa ) ) { if ( isFLAT ( * MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ;


<s> if ( Op . isImm ( ) ) { if ( SubIdx == <STR_LIT> ) return MachineOperand :: CreateImm ( Op . getImm ( ) & <NUM_LIT> ) ; if ( SubIdx == <STR_LIT> ) return MachineOperand :: CreateImm ( Op . getImm ( ) >> <NUM_LIT> ) ;


<s> MachineOperand <ISA_LIT>InstrInfo :: buildExtractSubRegOrImm ( MachineBasicBlock :: iterator MII , MachineRegisterInfo & MRI , MachineOperand & Op , const TargetRegisterClass * SuperRC , unsigned SubIdx , const TargetRegisterClass * SubRC ) const { if ( Op . isImm ( ) ) {

if ( SubIdx == <STR_LIT> ) return MachineOperand :: CreateImm ( Op . getImm ( ) & <NUM_LIT> ) ;


<s> MachineInstrBuilder <ISA_LIT>InstrInfo :: buildIndirectRead ( MachineBasicBlock * MBB , MachineBasicBlock :: iterator I , unsigned ValueReg , unsigned Address , unsigned OffsetReg ) const { const DebugLoc & DL = MBB -> findDebugLoc ( I ) ;

unsigned IndirectBaseReg = <STR_LIT> . getRegister ( getIndirectIndexBegin ( * MBB -> getParent ( ) ) ) ;


<s> unsigned IndirectBaseReg = <STR_LIT> . getRegister ( getIndirectIndexBegin ( * MBB -> getParent ( ) ) ) ;

return BuildMI ( * MBB , I , DL , get ( <STR_LIT> ) ) . addOperand ( I -> getOperand ( <NUM_LIT> ) ) . addOperand ( I -> getOperand ( <NUM_LIT> ) ) . addReg ( IndirectBaseReg ) . addReg ( OffsetReg ) . addImm ( <NUM_LIT> ) ;


return BuildMI ( * MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( IndirectBaseReg , RegState :: Define ) . addOperand ( I -> getOperand ( <NUM_LIT> ) ) . addReg ( IndirectBaseReg ) . addReg ( OffsetReg ) . addImm ( <NUM_LIT> ) . addReg ( ValueReg ) ;


<s> MachineInstr * <ISA_LIT>InstrInfo :: buildMovInstr ( MachineBasicBlock * MBB , MachineBasicBlock :: iterator I , unsigned DstReg , unsigned SrcReg ) const { return BuildMI ( * MBB , I , MBB -> findDebugLoc ( I ) , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) ;


<s> assert ( Channel == <NUM_LIT> ) ; return RegIndex ;


<s> unsigned WavefrontSize = ST . getWavefrontSize ( ) ; unsigned TIDReg = MFI -> getTIDReg ( ) ; if ( ! MFI -> hasCalculatedTID ( ) ) { MachineBasicBlock & Entry = MBB . getParent ( ) -> front ( ) ; MachineBasicBlock :: iterator Insert = Entry . front ( ) ; DebugLoc DL = Insert -> getDebugLoc ( ) ; TIDReg = RI . findUnusedRegister ( MF -> getRegInfo ( ) , & <STR_LIT> ) ; if ( TIDReg == <STR_LIT> ) return TIDReg ; if ( MFI -> getShaderType ( ) == ShaderType :: COMPUTE && WorkGroupSize > WavefrontSize ) { unsigned TIDIGXReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: WORKGROUP_ID_X ) ; unsigned TIDIGYReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: WORKGROUP_ID_Y ) ; unsigned TIDIGZReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: WORKGROUP_ID_Z ) ; unsigned InputPtrReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: KERNARG_SEGMENT_PTR ) ; for ( unsigned Reg : { TIDIGXReg , TIDIGYReg , TIDIGZReg } ) { if ( ! Entry . isLiveIn ( Reg ) ) Entry . addLiveIn ( Reg ) ; } RS -> enterBasicBlock ( & Entry ) ; unsigned STmp0 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; unsigned STmp1 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp0 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Z ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Y ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( STmp1 ) . addReg ( STmp0 ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp1 ) . addReg ( TIDIGXReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp0 ) . addReg ( TIDIGYReg ) . addReg ( TIDReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( TIDReg ) . addReg ( TIDIGZReg ) ; } else { BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addReg ( TIDReg ) ; }

BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( <NUM_LIT> ) . addReg ( TIDReg ) ;


<s> unsigned BaseReg1 , Offset1 ; if ( getMemOpBaseRegImmOfs ( MIa , BaseReg0 , Offset0 , & RI ) && getMemOpBaseRegImmOfs ( MIb , BaseReg1 , Offset1 , & RI ) ) { assert ( MIa -> hasOneMemOperand ( ) && MIb -> hasOneMemOperand ( ) && <STR_LIT> ) ;

unsigned Width0 = ( * MIa -> memoperands_begin ( ) ) -> getSize ( ) ;


<s> MachineOperand & Src1 = MI -> getOperand ( Src1Idx ) ; if ( isVOP2 ( * MI ) ) { const MCInstrDesc & InstrDesc = MI -> getDesc ( ) ; const MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; if ( ! isLegalRegOperand ( MRI , InstrDesc . OpInfo [ Src1Idx ] , Src0 ) ) return nullptr ; } if ( ! Src1 . isReg ( ) ) { if ( NewMI || ! Src1 . isImm ( ) || ( ! isVOP2 ( * MI ) && ! isVOP3 ( * MI ) ) ) { return nullptr ; } if ( MachineOperand * Src0Mods = getNamedOperand ( * MI , <STR_LIT> :: src0_modifiers ) ) { MachineOperand * Src1Mods = getNamedOperand ( * MI , <STR_LIT> :: src1_modifiers ) ; int Src0ModsVal = Src0Mods -> getImm ( ) ; if ( ! Src1Mods && Src0ModsVal != <NUM_LIT> ) return nullptr ; int Src1ModsVal = Src1Mods -> getImm ( ) ; assert ( ( Src1ModsVal == <NUM_LIT> ) && <STR_LIT> ) ; Src1Mods -> setImm ( Src0ModsVal ) ; Src0Mods -> setImm ( Src1ModsVal ) ; } unsigned Reg = Src0 . getReg ( ) ; unsigned SubReg = Src0 . getSubReg ( ) ; if ( Src1 . isImm ( ) ) Src0 . ChangeToImmediate ( Src1 . getImm ( ) ) ; else llvm_unreachable ( <STR_LIT> ) ; Src1 . ChangeToRegister ( Reg , false ) ; Src1 . setSubReg ( SubReg ) ; } else { MI = TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx0 , OpIdx1 ) ; } if ( MI ) MI -> setDesc ( get ( CommutedOpcode ) ) ;


<s> int NewOpc ; NewOpc = <STR_LIT> ( Opcode ) ; if ( NewOpc != - <NUM_LIT> ) return pseudoToMCOpcode ( NewOpc ) != - <NUM_LIT> ? NewOpc : - <NUM_LIT> ; NewOpc = <STR_LIT> ( Opcode ) ;


<s> case <STR_LIT> : { const MachineOperand * Src0 = getNamedOperand ( * MI , <STR_LIT> :: src0 ) ; if ( Src0 -> isImm ( ) && ! isInlineConstant ( * Src0 , <NUM_LIT> ) ) return nullptr ; break ; } } const MachineOperand * Dst = getNamedOperand ( * MI , <STR_LIT> :: dst ) ; const MachineOperand * Src0 = getNamedOperand ( * MI , <STR_LIT> :: src0 ) ;

const MachineOperand * Src1 = getNamedOperand ( * MI , <STR_LIT> :: src1 ) ;


<s> default : return nullptr ; case <STR_LIT> : break ; case <STR_LIT> : { const MachineOperand * Src0 = getNamedOperand ( * MI , <STR_LIT> :: src0 ) ; if ( Src0 -> isImm ( ) && ! isInlineConstant ( * Src0 , <NUM_LIT> ) ) return nullptr ; break ; } } const MachineOperand * Dst = getNamedOperand ( * MI , <STR_LIT> :: dst ) ; const MachineOperand * Src0 = getNamedOperand ( * MI , <STR_LIT> :: src0 ) ;


<s> unsigned Src1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const MachineOperand & SrcCond = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstLo ) . addReg ( RI . getSubReg ( Src0 , <STR_LIT> ) ) . addReg ( RI . getSubReg ( Src1 , <STR_LIT> ) ) . addOperand ( SrcCond ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstHi ) . addReg ( RI . getSubReg ( Src0 , <STR_LIT> ) ) . addReg ( RI . getSubReg ( Src1 , <STR_LIT> ) ) . addOperand ( SrcCond ) ; MI -> eraseFromParent ( ) ; break ; } case <STR_LIT> : { const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( ST . getRegisterInfo ( ) ) ; MachineFunction & MF = * MBB . getParent ( ) ; unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned RegLo = TRI -> getSubReg ( Reg , <STR_LIT> ) ; unsigned RegHi = TRI -> getSubReg ( Reg , <STR_LIT> ) ; MIBundleBuilder Bundler ( MBB , MI ) ; Bundler . append ( BuildMI ( MF , DL , get ( <STR_LIT> ) , Reg ) ) ; Bundler . append ( BuildMI ( MF , DL , get ( <STR_LIT> ) , RegLo ) . addReg ( RegLo ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ) ; Bundler . append ( BuildMI ( MF , DL , get ( <STR_LIT> ) , RegHi ) . addReg ( RegHi ) . addImm ( <NUM_LIT> ) ) ; llvm :: finalizeBundle ( MBB , Bundler . begin ( ) ) ; MI -> eraseFromParent ( ) ; break ;


<s> if ( Src1Idx == - <NUM_LIT> ) return false ; MachineOperand & Src1 = MI -> getOperand ( Src1Idx ) ; if ( Src1 . isImm ( ) ) { if ( ! isVOP2 ( MI -> getOpcode ( ) ) && ! isVOP3 ( MI -> getOpcode ( ) ) ) return false ; } else if ( Src1 . isReg ( ) ) { if ( hasModifiersSet ( * MI , <STR_LIT> :: src0_modifiers ) || hasModifiersSet ( * MI , <STR_LIT> :: src1_modifiers ) ) return false ; } else return false ;

return fixCommutedOpIndices ( SrcOpIdx0 , SrcOpIdx1 , Src0Idx , Src1Idx ) ;


<s> Src1 -> setIsKill ( Src2 -> isKill ( ) ) ; if ( Opc == <STR_LIT> ) { UseMI -> untieRegOperand ( <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ) ; } Src2 -> ChangeToImmediate ( Imm ) ; removeModOperands ( * UseMI ) ; UseMI -> setDesc ( get ( <STR_LIT> ) ) ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; if ( DeleteDef ) DefMI -> eraseFromParent ( ) ; return true ; } if ( Src2 -> isReg ( ) && Src2 -> getReg ( ) == Reg ) { if ( ! Src0 -> isImm ( ) && ( Src0 -> isReg ( ) && RI . isSGPRClass ( MRI -> getRegClass ( Src0 -> getReg ( ) ) ) ) ) return false ; if ( ! Src1 -> isReg ( ) || ( Src1 -> isReg ( ) && RI . isSGPRClass ( MRI -> getRegClass ( Src1 -> getReg ( ) ) ) ) ) return false ; const int64_t Imm = DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; UseMI -> RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: omod ) ) ; UseMI -> RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: clamp ) ) ; if ( Opc == <STR_LIT> ) { UseMI -> untieRegOperand ( <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ) ; } Src2 -> ChangeToImmediate ( Imm ) ;


<s> RsrcDataFormat |= ( <NUM_LIT> << <NUM_LIT> ) ; if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) RsrcDataFormat |= ( <NUM_LIT> << <NUM_LIT> ) ; } return RsrcDataFormat ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( RI . hasVGPRs ( NewDstRC ) ) return nullptr ; NewDstRC = RI . getEquivalentVGPRClass ( NewDstRC ) ; if ( ! NewDstRC ) return nullptr ; return NewDstRC ; default :


<s> const TargetRegisterClass * <ISA_LIT>InstrInfo :: getIndirectAddrRegClass ( ) const { return & <STR_LIT> ;


<s> if ( isDS ( * LdSt ) ) { const MachineOperand * OffsetImm = getNamedOperand ( * LdSt , <STR_LIT> :: offset ) ; if ( OffsetImm ) { const MachineOperand * AddrReg = getNamedOperand ( * LdSt , <STR_LIT> :: addr ) ; BaseReg = AddrReg -> getReg ( ) ; Offset = OffsetImm -> getImm ( ) ; return true ; } const MachineOperand * Offset0Imm = getNamedOperand ( * LdSt , <STR_LIT> :: offset0 ) ; const MachineOperand * Offset1Imm = getNamedOperand ( * LdSt , <STR_LIT> :: offset1 ) ; uint8_t Offset0 = Offset0Imm -> getImm ( ) ; uint8_t Offset1 = Offset1Imm -> getImm ( ) ; if ( Offset1 > Offset0 && Offset1 - Offset0 == <NUM_LIT> ) { unsigned EltSize ; if ( LdSt -> mayLoad ( ) ) EltSize = getOpRegClass ( * LdSt , <NUM_LIT> ) -> getSize ( ) / <NUM_LIT> ; else { assert ( LdSt -> mayStore ( ) ) ; int Data0Idx = <STR_LIT> ( Opc , <STR_LIT> :: data0 ) ; EltSize = getOpRegClass ( * LdSt , Data0Idx ) -> getSize ( ) ; } if ( isStride64 ( Opc ) ) EltSize *= <NUM_LIT> ; const MachineOperand * AddrReg = getNamedOperand ( * LdSt , <STR_LIT> :: addr ) ; BaseReg = AddrReg -> getReg ( ) ; Offset = EltSize * Offset0 ; return true ; } return false ; } if ( isMUBUF ( * LdSt ) || isMTBUF ( * LdSt ) ) { if ( <STR_LIT> ( Opc , <STR_LIT> :: soffset ) != - <NUM_LIT> ) return false ; const MachineOperand * AddrReg = getNamedOperand ( * LdSt , <STR_LIT> :: vaddr ) ; if ( ! AddrReg ) return false ;


<s> } else if ( DstRC -> getSize ( ) == <NUM_LIT> && RI . isSGPRClass ( DstRC ) ) { return <STR_LIT> ; } else if ( DstRC -> getSize ( ) == <NUM_LIT> && ! RI . isSGPRClass ( DstRC ) ) { return <STR_LIT> ;


<s> return RI . isSGPRClass ( DstRC ) ? <STR_LIT> : <STR_LIT> ; } else if ( DstRC -> getSize ( ) == <NUM_LIT> && RI . isSGPRClass ( DstRC ) ) { return <STR_LIT> ; } else if ( DstRC -> getSize ( ) == <NUM_LIT> && ! RI . isSGPRClass ( DstRC ) ) { return <STR_LIT> ;


<s> uint64_t <ISA_LIT>InstrInfo :: getScratchRsrcWords23 ( ) const { uint64_t Rsrc23 = getDefaultRsrcDataFormat ( ) | <STR_LIT> | <NUM_LIT> ; if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) Rsrc23 &= ~ <STR_LIT> ; return Rsrc23 ;


<s> switch ( MI . getOpcode ( ) ) { default : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . isReg ( ) ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default :


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ;


<s> unsigned OpSize = RI . getRegClass ( OpInfo . RegClass ) -> getSize ( ) ; if ( isLiteralConstant ( MO , OpSize ) ) return RI . opCanUseLiteralConstant ( OpInfo . OperandType ) ; return RI . opCanUseInlineConstant ( OpInfo . OperandType ) ;


<s> bool <ISA_LIT>InstrInfo :: isInlineConstant ( const MachineOperand & MO , unsigned OpSize ) const {


<s> bool <ISA_LIT>InstrInfo :: isLegalRegOperand ( const MachineRegisterInfo & MRI , const MCOperandInfo & OpInfo , const MachineOperand & MO ) const { if ( ! MO . isReg ( ) ) return false ; unsigned Reg = MO . getReg ( ) ;

const TargetRegisterClass * RC = TargetRegisterInfo :: isVirtualRegister ( Reg ) ? MRI . getRegClass ( Reg ) :


<s> if ( ! MO . isReg ( ) ) return false ; unsigned Reg = MO . getReg ( ) ; const TargetRegisterClass * RC = TargetRegisterInfo :: isVirtualRegister ( Reg ) ? MRI . getRegClass ( Reg ) :


<s> bool <ISA_LIT>InstrInfo :: isLiteralConstant ( const MachineOperand & MO , unsigned OpSize ) const { return MO . isImm ( ) && ! isInlineConstant ( MO , OpSize ) ;


<s> bool <ISA_LIT>InstrInfo :: isMov ( unsigned Opcode ) const { switch ( Opcode ) {


<s> return getVALUOp ( MI ) != <STR_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: isSALUOpSupportedOnVALU ( const MachineInstr & MI ) const { return getVALUOp ( MI ) != <STR_LIT> ;


<s> const MCInstrDesc & InstrDesc = get ( Opc ) ; int Src1Idx = <STR_LIT> ( Opc , <STR_LIT> :: src1 ) ; MachineOperand & Src1 = MI -> getOperand ( Src1Idx ) ; bool HasImplicitSGPR = findImplicitSGPRRead ( * MI ) != <STR_LIT> ; if ( HasImplicitSGPR ) { int Src0Idx = <STR_LIT> ( Opc , <STR_LIT> :: src0 ) ; MachineOperand & Src0 = MI -> getOperand ( Src0Idx ) ; if ( Src0 . isReg ( ) && RI . isSGPRReg ( MRI , Src0 . getReg ( ) ) ) legalizeOpWithMove ( MI , Src0Idx ) ; } if ( isLegalRegOperand ( MRI , InstrDesc . OpInfo [ Src1Idx ] , Src1 ) ) return ; if ( HasImplicitSGPR || ! MI -> isCommutable ( ) ) { legalizeOpWithMove ( MI , Src1Idx ) ; return ; } int Src0Idx = <STR_LIT> ( Opc , <STR_LIT> :: src0 ) ; MachineOperand & Src0 = MI -> getOperand ( Src0Idx ) ; if ( ( ! Src1 . isImm ( ) && ! Src1 . isReg ( ) ) || ! isLegalRegOperand ( MRI , InstrDesc . OpInfo [ Src1Idx ] , Src0 ) ) { legalizeOpWithMove ( MI , Src1Idx ) ; return ; } int CommutedOpc = commuteOpcode ( * MI ) ; if ( CommutedOpc == - <NUM_LIT> ) { legalizeOpWithMove ( MI , Src1Idx ) ; return ; } MI -> setDesc ( get ( CommutedOpc ) ) ; unsigned Src0Reg = Src0 . getReg ( ) ; unsigned Src0SubReg = Src0 . getSubReg ( ) ; bool Src0Kill = Src0 . isKill ( ) ; if ( Src1 . isImm ( ) ) Src0 . ChangeToImmediate ( Src1 . getImm ( ) ) ; else if ( Src1 . isReg ( ) ) { Src0 . ChangeToRegister ( Src1 . getReg ( ) , false , false , Src1 . isKill ( ) ) ; Src0 . setSubReg ( Src1 . getSubReg ( ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; Src1 . ChangeToRegister ( Src0Reg , false , false , Src0Kill ) ; Src1 . setSubReg ( Src0SubReg ) ;


<s> <STR_LIT> ( Opc , <STR_LIT> :: src0 ) , <STR_LIT> ( Opc , <STR_LIT> :: src1 ) , <STR_LIT> ( Opc , <STR_LIT> :: src2 ) } ; unsigned SGPRReg = findUsedSGPR ( MI , VOP3Idx ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { int Idx = VOP3Idx [ i ] ;


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineOperand & MO = MI -> getOperand ( OpIdx ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned RCID = get ( MI -> getOpcode ( ) ) . OpInfo [ OpIdx ] . RegClass ; const TargetRegisterClass * RC = RI . getRegClass ( RCID ) ; unsigned Opcode = <STR_LIT> ; if ( MO . isReg ( ) ) Opcode = <STR_LIT> ; else if ( RI . isSGPRClass ( RC ) ) Opcode = <STR_LIT> ; const TargetRegisterClass * VRC = RI . getEquivalentVGPRClass ( RC ) ; if ( RI . getCommonSubClass ( & <STR_LIT> , VRC ) ) VRC = & <STR_LIT> ; else VRC = & <STR_LIT> ;

unsigned Reg = MRI . createVirtualRegister ( VRC ) ;


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineOperand & MO = MI -> getOperand ( OpIdx ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned RCID = get ( MI -> getOpcode ( ) ) . OpInfo [ OpIdx ] . RegClass ; const TargetRegisterClass * RC = RI . getRegClass ( RCID ) ; unsigned Opcode = <STR_LIT> ;

if ( MO . isReg ( ) ) Opcode = <STR_LIT> ;


<s> } if ( ! ST . isVGPRSpillingEnabled ( MFI ) ) { LLVMContext & Ctx = MF -> getFunction ( ) -> getContext ( ) ; Ctx . emitError ( <STR_LIT> <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) ; return ; } assert ( RI . hasVGPRs ( RC ) && <STR_LIT> ) ; unsigned Opcode = getVGPRSpillRestoreOpcode ( RC -> getSize ( ) ) ;

BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) . addFrameIndex ( FrameIndex ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI -> getScratchWaveOffsetReg ( ) ) . addMemOperand ( MMO ) ;


<s> MachineOperand & Dest = Inst -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = Inst -> getOperand ( <NUM_LIT> ) ; unsigned TmpReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , TmpReg ) . addImm ( <NUM_LIT> ) . addReg ( Src . getReg ( ) ) ;

BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , ResultReg ) . addReg ( Src . getReg ( ) ) . addReg ( TmpReg ) ;


<s> unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , TmpReg ) . addImm ( <NUM_LIT> ) . addReg ( Src . getReg ( ) ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , ResultReg ) . addReg ( Src . getReg ( ) ) . addReg ( TmpReg ) ;

MRI . replaceRegWith ( Dest . getReg ( ) , ResultReg ) ;


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; int DstIdx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: dst ) ; assert ( DstIdx != - <NUM_LIT> ) ; unsigned DstRCID = get ( MI -> getOpcode ( ) ) . OpInfo [ DstIdx ] . RegClass ; switch ( RI . getRegClass ( DstRCID ) -> getSize ( ) ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : { unsigned NewOpcode = getVALUOp ( * MI ) ; unsigned RegOffset ; unsigned ImmOffset ; if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { RegOffset = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ImmOffset = <NUM_LIT> ; } else { assert ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; ImmOffset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( MBB -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getGeneration ( ) <= <ISA_LIT>Subtarget :: SEA_ISLANDS ) ImmOffset <<= <NUM_LIT> ; RegOffset = MRI . createVirtualRegister ( & <STR_LIT> ) ; if ( isUInt < <NUM_LIT> > ( ImmOffset ) ) { BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , RegOffset ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , RegOffset ) . addImm ( ImmOffset ) ; ImmOffset = <NUM_LIT> ; } } unsigned SRsrc = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord0 = RegOffset ; unsigned DWord1 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord2 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord3 = MRI . createVirtualRegister ( & <STR_LIT> ) ; uint64_t RsrcDataFormat = getDefaultRsrcDataFormat ( ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord1 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord2 ) . addImm ( RsrcDataFormat & <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord3 ) . addImm ( RsrcDataFormat >> <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , SRsrc ) . addReg ( DWord0 ) . addImm ( <STR_LIT> ) . addReg ( DWord1 ) . addImm ( <STR_LIT> ) . addReg ( DWord2 ) . addImm ( <STR_LIT> ) . addReg ( DWord3 ) . addImm ( <STR_LIT> ) ;

const MCInstrDesc & NewInstDesc = get ( NewOpcode ) ;


<s> BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , RegOffset ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , RegOffset ) . addImm ( ImmOffset ) ; ImmOffset = <NUM_LIT> ; } } unsigned SRsrc = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord0 = RegOffset ; unsigned DWord1 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord2 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord3 = MRI . createVirtualRegister ( & <STR_LIT> ) ; uint64_t RsrcDataFormat = getDefaultRsrcDataFormat ( ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord1 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord2 ) . addImm ( RsrcDataFormat & <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord3 ) . addImm ( RsrcDataFormat >> <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , SRsrc ) . addReg ( DWord0 ) . addImm ( <STR_LIT> ) . addReg ( DWord1 ) . addImm ( <STR_LIT> ) . addReg ( DWord2 ) . addImm ( <STR_LIT> ) . addReg ( DWord3 ) . addImm ( <STR_LIT> ) ; const MCInstrDesc & NewInstDesc = get ( NewOpcode ) ; const TargetRegisterClass * NewDstRC = RI . getRegClass ( NewInstDesc . OpInfo [ <NUM_LIT> ] . RegClass ) ; unsigned NewDstReg = MRI . createVirtualRegister ( NewDstRC ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MRI . replaceRegWith ( DstReg , NewDstReg ) ; MachineInstr * NewInst = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , NewInstDesc , NewDstReg ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addReg ( SRsrc ) . addImm ( <NUM_LIT> ) . addImm ( ImmOffset ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; MI -> eraseFromParent ( ) ; legalizeOperands ( NewInst ) ; addUsersToMoveToVALUWorklist ( NewDstReg , MRI , Worklist ) ;


<s> for ( int Index = Begin ; Index <= End ; ++ Index ) Reserved . set ( <STR_LIT> . getRegister ( Index ) ) ; for ( int Index = std :: max ( <NUM_LIT> , Begin - <NUM_LIT> ) ; Index <= End ; ++ Index ) Reserved . set ( <STR_LIT> . getRegister ( Index ) ) ; for ( int Index = std :: max ( <NUM_LIT> , Begin - <NUM_LIT> ) ; Index <= End ; ++ Index ) Reserved . set ( <STR_LIT> . getRegister ( Index ) ) ; for ( int Index = std :: max ( <NUM_LIT> , Begin - <NUM_LIT> ) ; Index <= End ; ++ Index ) Reserved . set ( <STR_LIT> . getRegister ( Index ) ) ; for ( int Index = std :: max ( <NUM_LIT> , Begin - <NUM_LIT> ) ; Index <= End ; ++ Index ) Reserved . set ( <STR_LIT> . getRegister ( Index ) ) ; for ( int Index = std :: max ( <NUM_LIT> , Begin - <NUM_LIT> ) ; Index <= End ; ++ Index ) Reserved . set ( <STR_LIT> . getRegister ( Index ) ) ;


<s> if ( isDS ( * FirstLdSt ) && isDS ( * SecondLdSt ) ) return true ; if ( isSMRD ( * FirstLdSt ) && isSMRD ( * SecondLdSt ) ) return true ;

if ( ( isMUBUF ( * FirstLdSt ) || isMTBUF ( * FirstLdSt ) ) && ( isMUBUF ( * SecondLdSt ) || isMTBUF ( * SecondLdSt ) ) ) return true ;


<s> bool <ISA_LIT>InstrInfo :: shouldClusterLoads ( MachineInstr * FirstLdSt , MachineInstr * SecondLdSt , unsigned NumLoads ) const { if ( NumLoads > <NUM_LIT> ) return false ; if ( isDS ( * FirstLdSt ) && isDS ( * SecondLdSt ) ) return true ; if ( isSMRD ( * FirstLdSt ) && isSMRD ( * SecondLdSt ) ) return true ; if ( ( isMUBUF ( * FirstLdSt ) || isMTBUF ( * FirstLdSt ) ) && ( isMUBUF ( * SecondLdSt ) || isMTBUF ( * SecondLdSt ) ) ) return true ; return false ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & st ) : <ISA_LIT>InstrInfo ( st ) , RI ( ) {


<s> MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; MachineBasicBlock :: iterator MII = Inst ; DebugLoc DL = Inst -> getDebugLoc ( ) ; MachineOperand & Dest = Inst -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = Inst -> getOperand ( <NUM_LIT> ) ; const MCInstrDesc & InstDesc = get ( <STR_LIT> ) ; const TargetRegisterClass * SrcRC = Src . isReg ( ) ? MRI . getRegClass ( Src . getReg ( ) ) : & <STR_LIT> ; unsigned MidReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; const TargetRegisterClass * SrcSubRC = RI . getSubRegClass ( SrcRC , <STR_LIT> ) ; MachineOperand SrcRegSub0 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , <STR_LIT> , SrcSubRC ) ; MachineOperand SrcRegSub1 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , <STR_LIT> , SrcSubRC ) ; BuildMI ( MBB , MII , DL , InstDesc , MidReg ) . addOperand ( SrcRegSub0 ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MII , DL , InstDesc , ResultReg ) . addOperand ( SrcRegSub1 ) . addReg ( MidReg ) ; MRI . replaceRegWith ( Dest . getReg ( ) , ResultReg ) ;

addUsersToMoveToVALUWorklist ( ResultReg , MRI , Worklist ) ;


<s> uint32_t Offset = Imm & <NUM_LIT> ; uint32_t BitWidth = ( Imm & <NUM_LIT> ) >> <NUM_LIT> ; ( void ) Offset ; assert ( Inst -> getOpcode ( ) == <STR_LIT> && BitWidth <= <NUM_LIT> && Offset == <NUM_LIT> && <STR_LIT> ) ; if ( BitWidth < <NUM_LIT> ) { unsigned MidRegLo = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned MidRegHi = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , MidRegLo ) . addReg ( Inst -> getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( BitWidth ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , MidRegHi ) . addImm ( <NUM_LIT> ) . addReg ( MidRegLo ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , ResultReg ) . addReg ( MidRegLo ) . addImm ( <STR_LIT> ) . addReg ( MidRegHi ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , ResultReg ) ; addUsersToMoveToVALUWorklist ( ResultReg , MRI , Worklist ) ; return ; }

MachineOperand & Src = Inst -> getOperand ( <NUM_LIT> ) ;


<s> const TargetRegisterClass * NewDestRC = RI . getEquivalentVGPRClass ( DestRC ) ; const TargetRegisterClass * NewDestSubRC = RI . getSubRegClass ( NewDestRC , <STR_LIT> ) ; unsigned DestSub0 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr * LoHalf = BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . addOperand ( SrcReg0Sub0 ) . addOperand ( SrcReg1Sub0 ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; unsigned DestSub1 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr * HiHalf = BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . addOperand ( SrcReg0Sub1 ) . addOperand ( SrcReg1Sub1 ) ; unsigned FullDestReg = MRI . createVirtualRegister ( NewDestRC ) ;

BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ;


<s> const TargetRegisterClass * NewDestSubRC = RI . getSubRegClass ( NewDestRC , <STR_LIT> ) ; unsigned DestSub0 = MRI . createVirtualRegister ( NewDestSubRC ) ; BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . addOperand ( SrcReg0Sub0 ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; unsigned DestSub1 = MRI . createVirtualRegister ( NewDestSubRC ) ; BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . addOperand ( SrcReg0Sub1 ) ; unsigned FullDestReg = MRI . createVirtualRegister ( NewDestRC ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ;

MRI . replaceRegWith ( Dest . getReg ( ) , FullDestReg ) ;


<s> MachineFunction * MF = MBB . getParent ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineFrameInfo * FrameInfo = MF -> getFrameInfo ( ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; unsigned Size = FrameInfo -> getObjectSize ( FrameIndex ) ; unsigned Align = FrameInfo -> getObjectAlignment ( FrameIndex ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , Size , Align ) ; if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; unsigned Opcode = getSGPRSpillSaveOpcode ( RC -> getSize ( ) ) ; BuildMI ( MBB , MI , DL , get ( Opcode ) ) . addReg ( SrcReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) ; return ; } if ( ! ST . isVGPRSpillingEnabled ( MFI ) ) { LLVMContext & Ctx = MF -> getFunction ( ) -> getContext ( ) ; Ctx . emitError ( <STR_LIT> <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg ) ; return ;


<s> assert ( Inst -> getNumExplicitOperands ( ) == <NUM_LIT> ) ; MachineOperand Op1 = Inst -> getOperand ( <NUM_LIT> ) ;


<s> if ( isLiteralConstant ( MO , OpSize ) ) return true ; if ( ! MO . isReg ( ) || ! MO . isUse ( ) ) return false ; if ( TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) return RI . isSGPRClass ( MRI . getRegClass ( MO . getReg ( ) ) ) ; if ( ! MO . isImplicit ( ) && ( MO . getReg ( ) == <STR_LIT> ) ) return true ; if ( ! MO . isImplicit ( ) && MO . getReg ( ) == <STR_LIT> ) return true ; if ( MO . getReg ( ) == <STR_LIT> || MO . getReg ( ) == <STR_LIT> || ( ! MO . isImplicit ( ) && ( <STR_LIT> . contains ( MO . getReg ( ) ) || <STR_LIT> . contains ( MO . getReg ( ) ) ) ) ) { return true ;


<s> ErrInfo = <STR_LIT> ; return false ; } break ; case <STR_LIT> : break ; case <STR_LIT> : if ( isLiteralConstant ( MI -> getOperand ( i ) , RI . getRegClass ( RegClass ) -> getSize ( ) ) ) { ErrInfo = <STR_LIT> ; return false ; } break ; case MCOI :: OPERAND_IMMEDIATE : if ( ! MI -> getOperand ( i ) . isImm ( ) && ! MI -> getOperand ( i ) . isFI ( ) ) { ErrInfo = <STR_LIT> ; return false ; } default : continue ; } if ( ! MI -> getOperand ( i ) . isReg ( ) ) continue ; if ( RegClass != - <NUM_LIT> ) { unsigned Reg = MI -> getOperand ( i ) . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) continue ; const TargetRegisterClass * RC = RI . getRegClass ( RegClass ) ; if ( ! RC -> contains ( Reg ) ) { ErrInfo = <STR_LIT> ; return false ; } } } if ( isVOP1 ( * MI ) || isVOP2 ( * MI ) || isVOP3 ( * MI ) || isVOPC ( * MI ) ) { const int OpIndices [ ] = { Src0Idx , Src1Idx , Src2Idx } ; unsigned ConstantBusCount = <NUM_LIT> ; unsigned SGPRUsed = findImplicitSGPRRead ( * MI ) ; if ( SGPRUsed != <STR_LIT> ) ++ ConstantBusCount ; for ( int OpIdx : OpIndices ) { if ( OpIdx == - <NUM_LIT> ) break ; const MachineOperand & MO = MI -> getOperand ( OpIdx ) ; if ( usesConstantBus ( MRI , MO , getOpSize ( Opcode , OpIdx ) ) ) { if ( MO . isReg ( ) ) { if ( MO . getReg ( ) != SGPRUsed ) ++ ConstantBusCount ; SGPRUsed = MO . getReg ( ) ; } else { ++ ConstantBusCount ; } } } if ( ConstantBusCount > <NUM_LIT> ) { ErrInfo = <STR_LIT> ; return false ; } } if ( Desc . getOpcode ( ) == <STR_LIT> || Desc . getOpcode ( ) == <STR_LIT> ) { const MachineOperand & Src0 = MI -> getOperand ( Src0Idx ) ; const MachineOperand & Src1 = MI -> getOperand ( Src1Idx ) ; const MachineOperand & Src2 = MI -> getOperand ( Src2Idx ) ; if ( Src0 . isReg ( ) && Src1 . isReg ( ) && Src2 . isReg ( ) ) { if ( ! compareMachineOp ( Src0 , Src1 ) && ! compareMachineOp ( Src0 , Src2 ) ) { ErrInfo = <STR_LIT> ; return false ; } } } if ( ! isGenericOpcode ( Opcode ) && ! isSALU ( Opcode ) && ! isSMRD ( Opcode ) ) { const MachineOperand * Exec = MI -> findRegisterUseOperand ( <STR_LIT> ) ; if ( ! Exec || ! Exec -> isImplicit ( ) ) { ErrInfo = <STR_LIT> ; return false ; }


<s> if ( MI . findRegisterDefOperandIdx ( <STR_LIT> ) != - <NUM_LIT> ) return ;

if ( MI . findRegisterUseOperandIdx ( <STR_LIT> ) != - <NUM_LIT> ) Worklist . push_back ( & MI ) ;


<s> assert ( ( MIa . mayLoad ( ) || MIa . mayStore ( ) ) && <STR_LIT> ) ; assert ( ( MIb . mayLoad ( ) || MIb . mayStore ( ) ) && <STR_LIT> ) ; if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) ) return false ; if ( MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ;


<s> } if ( isMUBUF ( MIa ) || isMTBUF ( MIa ) ) { if ( isMUBUF ( MIb ) || isMTBUF ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) && ! isSMRD ( MIb ) ; } if ( isSMRD ( MIa ) ) { if ( isSMRD ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ;

return ! isFLAT ( MIb ) && ! isMUBUF ( MIa ) && ! isMTBUF ( MIa ) ;


<s> unsigned STmp1 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp0 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Z ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Y ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( STmp1 ) . addReg ( STmp0 ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp1 ) . addReg ( TIDIGXReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp0 ) . addReg ( TIDIGYReg ) . addReg ( TIDReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( TIDReg ) . addReg ( TIDIGZReg ) ; } else {

BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> if ( MachineOperand * Src0Mods = getNamedOperand ( MI , <STR_LIT> :: src0_modifiers ) ) { MachineOperand * Src1Mods = getNamedOperand ( MI , <STR_LIT> :: src1_modifiers ) ; int Src0ModsVal = Src0Mods -> getImm ( ) ; if ( ! Src1Mods && Src0ModsVal != <NUM_LIT> ) return nullptr ; int Src1ModsVal = Src1Mods -> getImm ( ) ; assert ( ( Src1ModsVal == <NUM_LIT> ) && <STR_LIT> ) ; Src1Mods -> setImm ( Src0ModsVal ) ; Src0Mods -> setImm ( Src1ModsVal ) ; } unsigned Reg = Src0 . getReg ( ) ; unsigned SubReg = Src0 . getSubReg ( ) ; if ( Src1 . isImm ( ) ) Src0 . ChangeToImmediate ( Src1 . getImm ( ) ) ; else llvm_unreachable ( <STR_LIT> ) ; Src1 . ChangeToRegister ( Reg , false ) ; Src1 . setSubReg ( SubReg ) ; } else { CommutedMI = TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx0 , OpIdx1 ) ;


<s> return nullptr ; case <STR_LIT> : break ; case <STR_LIT> : { const MachineOperand * Src0 = getNamedOperand ( MI , <STR_LIT> :: src0 ) ; if ( Src0 -> isImm ( ) && ! isInlineConstant ( * Src0 , <NUM_LIT> ) ) return nullptr ; break ; } } const MachineOperand * Dst = getNamedOperand ( MI , <STR_LIT> :: vdst ) ; const MachineOperand * Src0 = getNamedOperand ( MI , <STR_LIT> :: src0 ) ; const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ;

const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ;


<s> const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ;

return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) ) . addOperand ( * Dst ) . addImm ( <NUM_LIT> ) . addOperand ( * Src0 ) . addImm ( <NUM_LIT> ) . addOperand ( * Src1 ) . addImm ( <NUM_LIT> ) . addOperand ( * Src2 ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> return ; } else if ( <STR_LIT> . contains ( DestReg ) ) { assert ( <STR_LIT> . contains ( SrcReg ) ) ; Opcode = <STR_LIT> ; SubIndices = Sub0_3_64 ; } else if ( <STR_LIT> . contains ( DestReg ) ) { assert ( <STR_LIT> . contains ( SrcReg ) ) ; Opcode = <STR_LIT> ; SubIndices = Sub0_7_64 ; } else if ( <STR_LIT> . contains ( DestReg ) ) { assert ( <STR_LIT> . contains ( SrcReg ) ) ; Opcode = <STR_LIT> ; SubIndices = Sub0_15_64 ; } else if ( <STR_LIT> . contains ( DestReg ) ) { assert ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( <STR_LIT> . contains ( DestReg ) ) { assert ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ; Opcode = <STR_LIT> ; SubIndices = Sub0_1 ; } else if ( <STR_LIT> . contains ( DestReg ) ) { assert ( <STR_LIT> . contains ( SrcReg ) ) ; Opcode = <STR_LIT> ; SubIndices = Sub0_2 ; } else if ( <STR_LIT> . contains ( DestReg ) ) { assert ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ; Opcode = <STR_LIT> ; SubIndices = Sub0_3 ; } else if ( <STR_LIT> . contains ( DestReg ) ) { assert ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ; Opcode = <STR_LIT> ; SubIndices = Sub0_7 ; } else if ( <STR_LIT> . contains ( DestReg ) ) { assert ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ; Opcode = <STR_LIT> ; SubIndices = Sub0_15 ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( RI . getHWRegIndex ( DestReg ) <= RI . getHWRegIndex ( SrcReg ) ) Forward = true ; else Forward = false ; for ( unsigned Idx = <NUM_LIT> ; Idx < SubIndices . size ( ) ; ++ Idx ) {


<s> BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstHi ) . addImm ( Imm . getHiBits ( <NUM_LIT> ) . getZExtValue ( ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; } else { assert ( SrcOp . isReg ( ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstLo ) . addReg ( RI . getSubReg ( SrcOp . getReg ( ) , <STR_LIT> ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstHi ) . addReg ( RI . getSubReg ( SrcOp . getReg ( ) , <STR_LIT> ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; } MI . eraseFromParent ( ) ; break ; } case <STR_LIT> : { unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstLo = RI . getSubReg ( Dst , <STR_LIT> ) ; unsigned DstHi = RI . getSubReg ( Dst , <STR_LIT> ) ; unsigned Src0 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const MachineOperand & SrcCond = MI . getOperand ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstLo ) . addReg ( RI . getSubReg ( Src0 , <STR_LIT> ) ) . addReg ( RI . getSubReg ( Src1 , <STR_LIT> ) ) . addReg ( SrcCond . getReg ( ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstHi ) . addReg ( RI . getSubReg ( Src0 , <STR_LIT> ) ) . addReg ( RI . getSubReg ( Src1 , <STR_LIT> ) ) . addReg ( SrcCond . getReg ( ) , getKillRegState ( SrcCond . isKill ( ) ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; MI . eraseFromParent ( ) ; break ; } case <STR_LIT> : { const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( ST . getRegisterInfo ( ) ) ;

MachineFunction & MF = * MBB . getParent ( ) ;


<s> bool <ISA_LIT>InstrInfo :: findCommutedOpIndices ( MachineInstr & MI , unsigned & SrcOpIdx0 , unsigned & SrcOpIdx1 ) const { const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( ! MCID . isCommutable ( ) ) return false ; unsigned Opc = MI . getOpcode ( ) ; int Src0Idx = <STR_LIT> ( Opc , <STR_LIT> :: src0 ) ; if ( Src0Idx == - <NUM_LIT> ) return false ; if ( ! MI . getOperand ( Src0Idx ) . isReg ( ) ) return false ; int Src1Idx = <STR_LIT> ( Opc , <STR_LIT> :: src1 ) ; if ( Src1Idx == - <NUM_LIT> ) return false ; MachineOperand & Src1 = MI . getOperand ( Src1Idx ) ; if ( Src1 . isImm ( ) ) { if ( ! isVOP2 ( MI . getOpcode ( ) ) && ! isVOP3 ( MI . getOpcode ( ) ) ) return false ; } else if ( Src1 . isReg ( ) ) { if ( hasModifiersSet ( MI , <STR_LIT> :: src0_modifiers ) || hasModifiersSet ( MI , <STR_LIT> :: src1_modifiers ) ) return false ; } else return false ; return fixCommutedOpIndices ( SrcOpIdx0 , SrcOpIdx1 , Src0Idx , Src1Idx ) ;


<s> if ( ! isVOP2 ( MI . getOpcode ( ) ) && ! isVOP3 ( MI . getOpcode ( ) ) ) return false ; } else if ( Src1 . isReg ( ) ) { if ( hasModifiersSet ( MI , <STR_LIT> :: src0_modifiers ) || hasModifiersSet ( MI , <STR_LIT> :: src1_modifiers ) ) return false ; } else return false ; return fixCommutedOpIndices ( SrcOpIdx0 , SrcOpIdx1 , Src0Idx , Src1Idx ) ;


<s> Src1 -> ChangeToImmediate ( Imm ) ; removeModOperands ( UseMI ) ; UseMI . setDesc ( get ( <STR_LIT> ) ) ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; if ( DeleteDef ) DefMI . eraseFromParent ( ) ; return true ; } if ( Src2 -> isReg ( ) && Src2 -> getReg ( ) == Reg ) { if ( ! Src0 -> isImm ( ) && ( Src0 -> isReg ( ) && RI . isSGPRClass ( MRI -> getRegClass ( Src0 -> getReg ( ) ) ) ) ) return false ; if ( ! Src1 -> isReg ( ) || RI . isSGPRClass ( MRI -> getRegClass ( Src1 -> getReg ( ) ) ) ) return false ; const int64_t Imm = DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; UseMI . RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: omod ) ) ; UseMI . RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: clamp ) ) ; if ( Opc == <STR_LIT> ) { UseMI . untieRegOperand ( <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ) ; } Src2 -> ChangeToImmediate ( Imm ) ; removeModOperands ( UseMI ) ; UseMI . setDesc ( get ( <STR_LIT> ) ) ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ;


<s> uint64_t RsrcDataFormat = <STR_LIT> ; if ( ST . isAmdHsaOS ( ) ) { RsrcDataFormat |= ( <NUM_LIT> << <NUM_LIT> ) ; if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) RsrcDataFormat |= ( <NUM_LIT> << <NUM_LIT> ) ; }


<s> bool <ISA_LIT>InstrInfo :: getMemOpBaseRegImmOfs ( MachineInstr & LdSt , unsigned & BaseReg , int64_t & Offset , const TargetRegisterInfo * TRI ) const { unsigned Opc = LdSt . getOpcode ( ) ; if ( isDS ( LdSt ) ) { const MachineOperand * OffsetImm = getNamedOperand ( LdSt , <STR_LIT> :: offset ) ; if ( OffsetImm ) { const MachineOperand * AddrReg = getNamedOperand ( LdSt , <STR_LIT> :: addr ) ; BaseReg = AddrReg -> getReg ( ) ; Offset = OffsetImm -> getImm ( ) ; return true ; } const MachineOperand * Offset0Imm = getNamedOperand ( LdSt , <STR_LIT> :: offset0 ) ; const MachineOperand * Offset1Imm = getNamedOperand ( LdSt , <STR_LIT> :: offset1 ) ; uint8_t Offset0 = Offset0Imm -> getImm ( ) ; uint8_t Offset1 = Offset1Imm -> getImm ( ) ; if ( Offset1 > Offset0 && Offset1 - Offset0 == <NUM_LIT> ) { unsigned EltSize ; if ( LdSt . mayLoad ( ) ) EltSize = getOpRegClass ( LdSt , <NUM_LIT> ) -> getSize ( ) / <NUM_LIT> ; else { assert ( LdSt . mayStore ( ) ) ; int Data0Idx = <STR_LIT> ( Opc , <STR_LIT> :: data0 ) ; EltSize = getOpRegClass ( LdSt , Data0Idx ) -> getSize ( ) ; } if ( isStride64 ( Opc ) ) EltSize *= <NUM_LIT> ; const MachineOperand * AddrReg = getNamedOperand ( LdSt , <STR_LIT> :: addr ) ; BaseReg = AddrReg -> getReg ( ) ; Offset = EltSize * Offset0 ; return true ; } return false ; } if ( isMUBUF ( LdSt ) || isMTBUF ( LdSt ) ) { if ( <STR_LIT> ( Opc , <STR_LIT> :: soffset ) != - <NUM_LIT> ) return false ; const MachineOperand * AddrReg = getNamedOperand ( LdSt , <STR_LIT> :: vaddr ) ; if ( ! AddrReg ) return false ; const MachineOperand * OffsetImm = getNamedOperand ( LdSt , <STR_LIT> :: offset ) ; BaseReg = AddrReg -> getReg ( ) ; Offset = OffsetImm -> getImm ( ) ; return true ; }


<s> if ( OpNum >= TID . getNumOperands ( ) ) return nullptr ; return RI . getRegClass ( TID . OpInfo [ OpNum ] . RegClass ) ;


<s> const TargetRegisterClass * getRegClass ( const MCInstrDesc & TID , unsigned OpNum , const TargetRegisterInfo * TRI , const MachineFunction & MF ) const override { if ( OpNum >= TID . getNumOperands ( ) ) return nullptr ; return RI . getRegClass ( TID . OpInfo [ OpNum ] . RegClass ) ;


<s> uint64_t EltSizeValue = Log2_32 ( ST . getMaxPrivateElementSize ( ) ) - <NUM_LIT> ; Rsrc23 |= ( EltSizeValue << <STR_LIT> ) | ( UINT64_C ( <NUM_LIT> ) << <STR_LIT> ) ; if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) Rsrc23 &= ~ <STR_LIT> ; return Rsrc23 ;


<s> } assert ( TBB && Cond [ <NUM_LIT> ] . isImm ( ) ) ; unsigned Opcode = getBranchOpcode ( static_cast < BranchPredicate > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; if ( ! FBB ) { BuildMI ( & MBB , DL , get ( Opcode ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } assert ( TBB && FBB ) ; BuildMI ( & MBB , DL , get ( Opcode ) ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ;


<s> return isSegmentSpecificFLAT ( MI ) ;


<s> unsigned OpSize = RI . getRegClass ( OpInfo . RegClass ) -> getSize ( ) ; if ( isLiteralConstant ( MO , OpSize ) ) return RI . opCanUseLiteralConstant ( OpInfo . OperandType ) ;

return RI . opCanUseInlineConstant ( OpInfo . OperandType ) ;


<s> int Src0Idx = <STR_LIT> ( Opc , <STR_LIT> :: src0 ) ; MachineOperand & Src0 = MI . getOperand ( Src0Idx ) ; if ( Src0 . isReg ( ) && RI . isSGPRReg ( MRI , Src0 . getReg ( ) ) ) legalizeOpWithMove ( MI , Src0Idx ) ; } if ( isLegalRegOperand ( MRI , InstrDesc . OpInfo [ Src1Idx ] , Src1 ) ) return ; if ( HasImplicitSGPR || ! MI . isCommutable ( ) ) { legalizeOpWithMove ( MI , Src1Idx ) ; return ; } int Src0Idx = <STR_LIT> ( Opc , <STR_LIT> :: src0 ) ; MachineOperand & Src0 = MI . getOperand ( Src0Idx ) ; if ( ( ! Src1 . isImm ( ) && ! Src1 . isReg ( ) ) || ! isLegalRegOperand ( MRI , InstrDesc . OpInfo [ Src1Idx ] , Src0 ) ) { legalizeOpWithMove ( MI , Src1Idx ) ; return ; } int CommutedOpc = commuteOpcode ( MI ) ; if ( CommutedOpc == - <NUM_LIT> ) { legalizeOpWithMove ( MI , Src1Idx ) ; return ;


<s> MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; MachineBasicBlock :: iterator MII = Inst ; DebugLoc DL = Inst . getDebugLoc ( ) ; MachineOperand & Dest = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = Inst . getOperand ( <NUM_LIT> ) ; unsigned TmpReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , TmpReg ) . addImm ( <NUM_LIT> ) . addReg ( Src . getReg ( ) ) ;


<s> case <STR_LIT> : splitScalar64BitBCNT ( Worklist , Inst ) ; Inst . eraseFromParent ( ) ; continue ; case <STR_LIT> : { splitScalar64BitBFE ( Worklist , Inst ) ; Inst . eraseFromParent ( ) ; continue ; } case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : lowerScalarAbs ( Worklist , Inst ) ; Inst . eraseFromParent ( ) ; continue ; case <STR_LIT> : case <STR_LIT> : BuildMI ( * MBB , Inst , Inst . getDebugLoc ( ) , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ;


<s> const TargetRegisterClass * VRC = MRI . getRegClass ( SrcReg ) ; const TargetRegisterClass * SRC = RI . getEquivalentSGPRClass ( VRC ) ; unsigned DstReg = MRI . createVirtualRegister ( SRC ) ; unsigned SubRegs = VRC -> getSize ( ) / <NUM_LIT> ; SmallVector < unsigned , <NUM_LIT> > SRegs ; for ( unsigned i = <NUM_LIT> ; i < SubRegs ; ++ i ) {

unsigned SGPR = MRI . createVirtualRegister ( & <STR_LIT> ) ;


<s> unsigned SubRegs = VRC -> getSize ( ) / <NUM_LIT> ; SmallVector < unsigned , <NUM_LIT> > SRegs ; for ( unsigned i = <NUM_LIT> ; i < SubRegs ; ++ i ) { unsigned SGPR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( <STR_LIT> ) , SGPR ) . addReg ( SrcReg , <NUM_LIT> , RI . getSubRegFromChannel ( i ) ) ; SRegs . push_back ( SGPR ) ; } MachineInstrBuilder MIB = BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( <STR_LIT> ) , DstReg ) ;


<s> MachineBasicBlock :: iterator Next = std :: next ( I ) ; I -> eraseFromParent ( ) ; ++ Count ; I = Next ; } return Count ;


<s> MachineBasicBlock :: iterator Next = std :: next ( I ) ; I -> eraseFromParent ( ) ; ++ Count ; I = Next ; }


<s> bool <ISA_LIT>InstrInfo :: ReverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { assert ( Cond . size ( ) == <NUM_LIT> ) ; Cond [ <NUM_LIT> ] . setImm ( - Cond [ <NUM_LIT> ] . getImm ( ) ) ;


<s> SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: sdst ) ; } if ( ( isMUBUF ( FirstLdSt ) && isMUBUF ( SecondLdSt ) ) || ( isMTBUF ( FirstLdSt ) && isMTBUF ( SecondLdSt ) ) ) { FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdata ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdata ) ; } if ( ! FirstDst || ! SecondDst ) return false ; unsigned LoadClusterThreshold = <NUM_LIT> ; const MachineRegisterInfo & MRI = FirstLdSt . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ;

const TargetRegisterClass * DstRC = MRI . getRegClass ( FirstDst -> getReg ( ) ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & ST ) : <ISA_LIT>InstrInfo ( ST ) , RI ( ) , ST ( ST ) {


<s> MachineOperand & Dest = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = Inst . getOperand ( <NUM_LIT> ) ; const MCInstrDesc & InstDesc = get ( <STR_LIT> ) ; const TargetRegisterClass * SrcRC = Src . isReg ( ) ? MRI . getRegClass ( Src . getReg ( ) ) : & <STR_LIT> ; unsigned MidReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; const TargetRegisterClass * SrcSubRC = RI . getSubRegClass ( SrcRC , <STR_LIT> ) ;

MachineOperand SrcRegSub0 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , <STR_LIT> , SrcSubRC ) ;


<s> BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , MidRegLo ) . addReg ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( BitWidth ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , MidRegHi ) . addImm ( <NUM_LIT> ) . addReg ( MidRegLo ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , ResultReg ) . addReg ( MidRegLo ) . addImm ( <STR_LIT> ) . addReg ( MidRegHi ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , ResultReg ) ; addUsersToMoveToVALUWorklist ( ResultReg , MRI , Worklist ) ; return ; } MachineOperand & Src = Inst . getOperand ( <NUM_LIT> ) ; unsigned TmpReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ;

BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , TmpReg ) . addImm ( <NUM_LIT> ) . addReg ( Src . getReg ( ) , <NUM_LIT> , <STR_LIT> ) ;


<s> & <STR_LIT> ; const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; const TargetRegisterClass * Src1RC = Src1 . isReg ( ) ? MRI . getRegClass ( Src1 . getReg ( ) ) : & <STR_LIT> ; const TargetRegisterClass * Src1SubRC = RI . getSubRegClass ( Src1RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; const TargetRegisterClass * DestRC = MRI . getRegClass ( Dest . getReg ( ) ) ; const TargetRegisterClass * NewDestRC = RI . getEquivalentVGPRClass ( DestRC ) ; const TargetRegisterClass * NewDestSubRC = RI . getSubRegClass ( NewDestRC , <STR_LIT> ) ; unsigned DestSub0 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & LoHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . addOperand ( SrcReg0Sub0 ) . addOperand ( SrcReg1Sub0 ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; unsigned DestSub1 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & HiHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . addOperand ( SrcReg0Sub1 ) . addOperand ( SrcReg1Sub1 ) ; unsigned FullDestReg = MRI . createVirtualRegister ( NewDestRC ) ;


<s> const TargetRegisterClass * NewDestSubRC = RI . getSubRegClass ( NewDestRC , <STR_LIT> ) ; unsigned DestSub0 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & LoHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . addOperand ( SrcReg0Sub0 ) . addOperand ( SrcReg1Sub0 ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; unsigned DestSub1 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & HiHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . addOperand ( SrcReg0Sub1 ) . addOperand ( SrcReg1Sub1 ) ; unsigned FullDestReg = MRI . createVirtualRegister ( NewDestRC ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , FullDestReg ) ; legalizeOperands ( LoHalf ) ; legalizeOperands ( HiHalf ) ; addUsersToMoveToVALUWorklist ( FullDestReg , MRI , Worklist ) ;


<s> const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; const TargetRegisterClass * DestRC = MRI . getRegClass ( Dest . getReg ( ) ) ; const TargetRegisterClass * NewDestRC = RI . getEquivalentVGPRClass ( DestRC ) ; const TargetRegisterClass * NewDestSubRC = RI . getSubRegClass ( NewDestRC , <STR_LIT> ) ; unsigned DestSub0 = MRI . createVirtualRegister ( NewDestSubRC ) ; BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . addOperand ( SrcReg0Sub0 ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ;

unsigned DestSub1 = MRI . createVirtualRegister ( NewDestSubRC ) ;


<s> const TargetRegisterClass * NewDestRC = RI . getEquivalentVGPRClass ( DestRC ) ; const TargetRegisterClass * NewDestSubRC = RI . getSubRegClass ( NewDestRC , <STR_LIT> ) ; unsigned DestSub0 = MRI . createVirtualRegister ( NewDestSubRC ) ; BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . addOperand ( SrcReg0Sub0 ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; unsigned DestSub1 = MRI . createVirtualRegister ( NewDestSubRC ) ; BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . addOperand ( SrcReg0Sub1 ) ; unsigned FullDestReg = MRI . createVirtualRegister ( NewDestRC ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , FullDestReg ) ; addUsersToMoveToVALUWorklist ( FullDestReg , MRI , Worklist ) ;


<s> if ( ! MO . isReg ( ) || ! MO . isUse ( ) ) return false ; if ( TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) return RI . isSGPRClass ( MRI . getRegClass ( MO . getReg ( ) ) ) ;

if ( ! MO . isImplicit ( ) && ( MO . getReg ( ) == <STR_LIT> ) ) return true ;


<s> if ( ! MO . isImplicit ( ) && ( MO . getReg ( ) == <STR_LIT> ) ) return true ; if ( ! MO . isImplicit ( ) && MO . getReg ( ) == <STR_LIT> ) return true ;

return ( MO . getReg ( ) == <STR_LIT> || MO . getReg ( ) == <STR_LIT> || ( ! MO . isImplicit ( ) && ( <STR_LIT> . contains ( MO . getReg ( ) ) || <STR_LIT> . contains ( MO . getReg ( ) ) ) ) ) ;


<s> const TargetRegisterClass * RC = RI . getRegClass ( RegClass ) ; if ( ! RC -> contains ( Reg ) ) { ErrInfo = <STR_LIT> ; return false ; } } } if ( isVOP1 ( MI ) || isVOP2 ( MI ) || isVOP3 ( MI ) || isVOPC ( MI ) ) { const int OpIndices [ ] = { Src0Idx , Src1Idx , Src2Idx } ; unsigned ConstantBusCount = <NUM_LIT> ; if ( <STR_LIT> ( Opcode , <STR_LIT> :: imm ) != - <NUM_LIT> ) ++ ConstantBusCount ; unsigned SGPRUsed = findImplicitSGPRRead ( MI ) ; if ( SGPRUsed != <STR_LIT> ) ++ ConstantBusCount ; for ( int OpIdx : OpIndices ) { if ( OpIdx == - <NUM_LIT> ) break ; const MachineOperand & MO = MI . getOperand ( OpIdx ) ; if ( usesConstantBus ( MRI , MO , getOpSize ( Opcode , OpIdx ) ) ) { if ( MO . isReg ( ) ) { if ( MO . getReg ( ) != SGPRUsed ) ++ ConstantBusCount ; SGPRUsed = MO . getReg ( ) ; } else { ++ ConstantBusCount ; } } } if ( ConstantBusCount > <NUM_LIT> ) { ErrInfo = <STR_LIT> ; return false ; } } if ( Desc . getOpcode ( ) == <STR_LIT> || Desc . getOpcode ( ) == <STR_LIT> ) { const MachineOperand & Src0 = MI . getOperand ( Src0Idx ) ;

const MachineOperand & Src1 = MI . getOperand ( Src1Idx ) ;


<s> if ( unsigned SubReg = MO . getSubReg ( ) ) {

assert ( RI . getRegSizeInBits ( * RI . getSubClassWithSubReg ( MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) . getRegClass ( MO . getReg ( ) ) , SubReg ) ) >= <NUM_LIT> && <STR_LIT> ) ;


<s> unsigned Reg = NewDesc . ImplicitUses [ i ] ; Inst -> addOperand ( MachineOperand :: CreateReg ( Reg , false , true ) ) ; } } if ( NewDesc . ImplicitDefs ) { for ( unsigned i = <NUM_LIT> ; NewDesc . ImplicitDefs [ i ] ; ++ i ) {

unsigned Reg = NewDesc . ImplicitDefs [ i ] ;


<s> unsigned <ISA_LIT>InstrInfo :: buildExtractSubReg ( MachineBasicBlock :: iterator MI , MachineRegisterInfo & MRI , MachineOperand & SuperReg , const TargetRegisterClass * SuperRC , unsigned SubIdx , const TargetRegisterClass * SubRC ) const { assert ( SuperReg . isReg ( ) ) ; unsigned NewSuperReg = MRI . createVirtualRegister ( SuperRC ) ; unsigned SubReg = MRI . createVirtualRegister ( SubRC ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; BuildMI ( * MBB , MI , DL , get ( TargetOpcode :: COPY ) , NewSuperReg ) . addReg ( SuperReg . getReg ( ) , <NUM_LIT> , SuperReg . getSubReg ( ) ) ; BuildMI ( * MBB , MI , DL , get ( TargetOpcode :: COPY ) , SubReg ) . addReg ( NewSuperReg , <NUM_LIT> , SubIdx ) ;


<s> assert ( Src0Idx != - <NUM_LIT> && <STR_LIT> ) ; MachineOperand & Src0 = MI -> getOperand ( Src0Idx ) ; if ( ! Src0 . isReg ( ) ) return nullptr ; int Src1Idx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: src1 ) ; if ( Src1Idx == - <NUM_LIT> ) return nullptr ; MachineOperand & Src1 = MI -> getOperand ( Src1Idx ) ; if ( isVOP2 ( MI -> getOpcode ( ) ) && ( ! isOperandLegal ( MI , Src0Idx , & Src1 ) || ! isOperandLegal ( MI , Src1Idx , & Src0 ) ) ) { return nullptr ; } if ( ! Src1 . isReg ( ) ) { if ( NewMI || ! Src1 . isImm ( ) || ( ! isVOP2 ( MI -> getOpcode ( ) ) && ! isVOP3 ( MI -> getOpcode ( ) ) ) ) { return nullptr ; } if ( MachineOperand * Src0Mods = getNamedOperand ( * MI , <STR_LIT> :: src0_modifiers ) ) { MachineOperand * Src1Mods = getNamedOperand ( * MI , <STR_LIT> :: src1_modifiers ) ; int Src0ModsVal = Src0Mods -> getImm ( ) ; if ( ! Src1Mods && Src0ModsVal != <NUM_LIT> ) return nullptr ; int Src1ModsVal = Src1Mods -> getImm ( ) ; assert ( ( Src1ModsVal == <NUM_LIT> ) && <STR_LIT> ) ; Src1Mods -> setImm ( Src0ModsVal ) ; Src0Mods -> setImm ( Src1ModsVal ) ; } unsigned Reg = Src0 . getReg ( ) ; unsigned SubReg = Src0 . getSubReg ( ) ; if ( Src1 . isImm ( ) ) Src0 . ChangeToImmediate ( Src1 . getImm ( ) ) ; else llvm_unreachable ( <STR_LIT> ) ; Src1 . ChangeToRegister ( Reg , false ) ; Src1 . setSubReg ( SubReg ) ;


<s> if ( isVOP2 ( MI -> getOpcode ( ) ) && ( ! isOperandLegal ( MI , Src0Idx , & Src1 ) || ! isOperandLegal ( MI , Src1Idx , & Src0 ) ) ) { return nullptr ; } if ( ! Src1 . isReg ( ) ) { if ( NewMI || ! Src1 . isImm ( ) || ( ! isVOP2 ( MI -> getOpcode ( ) ) && ! isVOP3 ( MI -> getOpcode ( ) ) ) ) { return nullptr ; } if ( MachineOperand * Src0Mods = getNamedOperand ( * MI , <STR_LIT> :: src0_modifiers ) ) { MachineOperand * Src1Mods = getNamedOperand ( * MI , <STR_LIT> :: src1_modifiers ) ;

int Src0ModsVal = Src0Mods -> getImm ( ) ;


<s> if ( Src0Idx == - <NUM_LIT> ) return false ; if ( ! MI -> getOperand ( Src0Idx ) . isReg ( ) ) return false ; int Src1Idx = <STR_LIT> ( Opc , <STR_LIT> :: src1 ) ; if ( Src1Idx == - <NUM_LIT> ) return false ; if ( ! MI -> getOperand ( Src1Idx ) . isReg ( ) ) return false ; if ( hasModifiersSet ( * MI , <STR_LIT> :: src0_modifiers ) || hasModifiersSet ( * MI , <STR_LIT> :: src1_modifiers ) ) return false ; SrcOpIdx1 = Src0Idx ; SrcOpIdx2 = Src1Idx ; return true ;


<s> Src0 -> setReg ( Src1Reg ) ; Src0 -> setSubReg ( Src1SubReg ) ; Src0 -> setIsKill ( Src1 -> isKill ( ) ) ; Src1 -> setReg ( Src2Reg ) ; Src1 -> setSubReg ( Src2SubReg ) ; Src1 -> setIsKill ( Src2 -> isKill ( ) ) ; if ( Opc == <STR_LIT> ) { UseMI -> untieRegOperand ( <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ) ; } UseMI -> RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ) ; Src2 -> ChangeToImmediate ( Imm ) ; removeModOperands ( * UseMI ) ; UseMI -> setDesc ( get ( <STR_LIT> ) ) ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; if ( DeleteDef ) DefMI -> eraseFromParent ( ) ; return true ; } if ( Src2 -> isReg ( ) && Src2 -> getReg ( ) == Reg ) { if ( ! Src0 -> isImm ( ) && ( Src0 -> isReg ( ) && RI . isSGPRClass ( MRI -> getRegClass ( Src0 -> getReg ( ) ) ) ) ) return false ; if ( ! Src1 -> isReg ( ) || ( Src1 -> isReg ( ) && RI . isSGPRClass ( MRI -> getRegClass ( Src1 -> getReg ( ) ) ) ) ) return false ; const int64_t Imm = DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; UseMI -> RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: omod ) ) ; UseMI -> RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: clamp ) ) ; if ( Opc == <STR_LIT> ) { UseMI -> untieRegOperand ( <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ) ; } Src2 -> ChangeToImmediate ( Imm ) ; removeModOperands ( * UseMI ) ; UseMI -> setDesc ( get ( <STR_LIT> ) ) ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; if ( DeleteDef ) DefMI -> eraseFromParent ( ) ; return true ;


<s> case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: isSafeToMoveRegClassDefs ( const TargetRegisterClass * RC ) const { return RC != & <STR_LIT> ;


<s> switch ( MI -> getOpcode ( ) ) { default : return <ISA_LIT>InstrInfo :: isTriviallyReMaterializable ( MI , AA ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :

return MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ;


<s> MachineFunction * MF = MBB . getParent ( ) ; const <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineFrameInfo * FrameInfo = MF -> getFrameInfo ( ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; int Opcode = - <NUM_LIT> ; if ( RI . isSGPRClass ( RC ) ) { switch ( RC -> getSize ( ) * <NUM_LIT> ) { case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; } } else if ( RI . hasVGPRs ( RC ) && ST . isVGPRSpillingEnabled ( MFI ) ) { switch ( RC -> getSize ( ) * <NUM_LIT> ) { case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ;


<s> } else { BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , RegOffset ) . addImm ( ImmOffset ) ; ImmOffset = <NUM_LIT> ; } } unsigned SRsrc = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord0 = RegOffset ; unsigned DWord1 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord2 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord3 = MRI . createVirtualRegister ( & <STR_LIT> ) ; uint64_t RsrcDataFormat = getDefaultRsrcDataFormat ( ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord1 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord2 ) . addImm ( RsrcDataFormat & <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord3 ) . addImm ( RsrcDataFormat >> <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , SRsrc ) . addReg ( DWord0 ) . addImm ( <STR_LIT> ) . addReg ( DWord1 ) . addImm ( <STR_LIT> ) . addReg ( DWord2 ) . addImm ( <STR_LIT> ) . addReg ( DWord3 ) . addImm ( <STR_LIT> ) ; MI -> setDesc ( get ( NewOpcode ) ) ; if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { MI -> getOperand ( <NUM_LIT> ) . setReg ( SRsrc ) ; } else { MI -> getOperand ( <NUM_LIT> ) . ChangeToRegister ( SRsrc , false ) ; } MI -> addOperand ( * MBB -> getParent ( ) , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MI -> addOperand ( * MBB -> getParent ( ) , MachineOperand :: CreateImm ( ImmOffset ) ) ; MI -> addOperand ( * MBB -> getParent ( ) , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MI -> addOperand ( * MBB -> getParent ( ) , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MI -> addOperand ( * MBB -> getParent ( ) , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; const TargetRegisterClass * NewDstRC = RI . getRegClass ( get ( NewOpcode ) . OpInfo [ <NUM_LIT> ] . RegClass ) ;

unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> legalizeOperands ( Inst ) ; continue ; } const MCInstrDesc & NewDesc = get ( NewOpcode ) ; Inst -> setDesc ( NewDesc ) ; for ( unsigned i = Inst -> getNumOperands ( ) - <NUM_LIT> ; i > <NUM_LIT> ; -- i ) { MachineOperand & Op = Inst -> getOperand ( i ) ; if ( Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> ) Inst -> RemoveOperand ( i ) ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Size = ( Opcode == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( Size ) ) ; } else if ( Opcode == <STR_LIT> ) { Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } addDescImplicitUseDef ( NewDesc , Inst ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { const MachineOperand & OffsetWidthOp = Inst -> getOperand ( <NUM_LIT> ) ; assert ( OffsetWidthOp . isImm ( ) && <STR_LIT> ) ; uint32_t Imm = OffsetWidthOp . getImm ( ) ; uint32_t Offset = Imm & <NUM_LIT> ; uint32_t BitWidth = ( Imm & <NUM_LIT> ) >> <NUM_LIT> ; Inst -> RemoveOperand ( <NUM_LIT> ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( Offset ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( BitWidth ) ) ; } const TargetRegisterClass * NewDstRC = getOpRegClass ( * Inst , <NUM_LIT> ) ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( RI . hasVGPRs ( NewDstRC ) ) continue ; NewDstRC = RI . getEquivalentVGPRClass ( NewDstRC ) ; if ( ! NewDstRC ) continue ; break ; default : break ; } unsigned DstReg = Inst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewDstReg = MRI . createVirtualRegister ( NewDstRC ) ; MRI . replaceRegWith ( DstReg , NewDstReg ) ; legalizeOperands ( Inst ) ; for ( MachineRegisterInfo :: use_iterator I = MRI . use_begin ( NewDstReg ) , E = MRI . use_end ( ) ; I != E ; ++ I ) {

MachineInstr & UseMI = * I -> getParent ( ) ;


<s> MachineInstr * Lo = BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) , LoDst ) . addImm ( Op . getImm ( ) & <NUM_LIT> ) ; MachineInstr * Hi = BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) , HiDst ) . addImm ( Op . getImm ( ) >> <NUM_LIT> ) ; BuildMI ( * MBB , MI , DL , get ( TargetOpcode :: REG_SEQUENCE ) , Dst ) . addReg ( LoDst ) . addImm ( <STR_LIT> ) . addReg ( HiDst ) . addImm ( <STR_LIT> ) ; Worklist . push_back ( Lo ) ;


<s> unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; const TargetRegisterClass * SrcSubRC = RI . getSubRegClass ( SrcRC , <STR_LIT> ) ; MachineOperand SrcRegSub0 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , <STR_LIT> , SrcSubRC ) ; MachineOperand SrcRegSub1 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , <STR_LIT> , SrcSubRC ) ; MachineInstr * First = BuildMI ( MBB , MII , DL , InstDesc , MidReg ) . addOperand ( SrcRegSub0 ) . addImm ( <NUM_LIT> ) ;

MachineInstr * Second = BuildMI ( MBB , MII , DL , InstDesc , ResultReg ) . addOperand ( SrcRegSub1 ) . addReg ( MidReg ) ;


<s> & <STR_LIT> ; const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; const TargetRegisterClass * Src1RC = Src1 . isReg ( ) ? MRI . getRegClass ( Src1 . getReg ( ) ) : & <STR_LIT> ; const TargetRegisterClass * Src1SubRC = RI . getSubRegClass ( Src1RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; const TargetRegisterClass * DestRC = MRI . getRegClass ( Dest . getReg ( ) ) ; const TargetRegisterClass * DestSubRC = RI . getSubRegClass ( DestRC , <STR_LIT> ) ; unsigned DestSub0 = MRI . createVirtualRegister ( DestRC ) ; MachineInstr * LoHalf = BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . addOperand ( SrcReg0Sub0 ) . addOperand ( SrcReg1Sub0 ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; unsigned DestSub1 = MRI . createVirtualRegister ( DestSubRC ) ; MachineInstr * HiHalf = BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . addOperand ( SrcReg0Sub1 ) . addOperand ( SrcReg1Sub1 ) ; unsigned FullDestReg = MRI . createVirtualRegister ( DestRC ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , FullDestReg ) ;


<s> MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; unsigned DestSub1 = MRI . createVirtualRegister ( DestSubRC ) ; MachineInstr * HiHalf = BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . addOperand ( SrcReg0Sub1 ) ; unsigned FullDestReg = MRI . createVirtualRegister ( DestRC ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , FullDestReg ) ; Worklist . push_back ( LoHalf ) ;


<s> MachineInstr * LoHalf = BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . addOperand ( SrcReg0Sub0 ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; unsigned DestSub1 = MRI . createVirtualRegister ( DestSubRC ) ; MachineInstr * HiHalf = BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . addOperand ( SrcReg0Sub1 ) ; unsigned FullDestReg = MRI . createVirtualRegister ( DestRC ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , FullDestReg ) ; Worklist . push_back ( LoHalf ) ; Worklist . push_back ( HiHalf ) ;


<s> const MachineOperand * SBase = getNamedOperand ( * MI , <STR_LIT> :: sbase ) ; bool IsKill = SBase -> isKill ( ) ; if ( OffOp ) { bool isVI = MBB -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ; unsigned OffScale = isVI ? <NUM_LIT> : <NUM_LIT> ; unsigned LoOffset = OffOp -> getImm ( ) * OffScale ; unsigned HiOffset = LoOffset + HalfSize ; Lo = BuildMI ( * MBB , MI , DL , get ( HalfImmOp ) , RegLo ) . addReg ( SBase -> getReg ( ) , <NUM_LIT> , SBase -> getSubReg ( ) ) . addImm ( LoOffset / OffScale ) ; if ( ! isUInt < <NUM_LIT> > ( HiOffset ) || ( ! isVI && ! isUInt < <NUM_LIT> > ( HiOffset / OffScale ) ) ) { unsigned OffsetSGPR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) , OffsetSGPR ) . addImm ( HiOffset ) ; Hi = BuildMI ( * MBB , MI , DL , get ( HalfSGPROp ) , RegHi ) . addReg ( SBase -> getReg ( ) , getKillRegState ( IsKill ) , SBase -> getSubReg ( ) ) . addReg ( OffsetSGPR ) ; } else {

Hi = BuildMI ( * MBB , MI , DL , get ( HalfImmOp ) , RegHi ) . addReg ( SBase -> getReg ( ) , getKillRegState ( IsKill ) , SBase -> getSubReg ( ) ) . addImm ( HiOffset / OffScale ) ;


<s> switch ( RC -> getSize ( ) * <NUM_LIT> ) { case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; } } if ( Opcode != - <NUM_LIT> ) { FrameInfo -> setObjectAlignment ( FrameIndex , <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( Opcode ) ) . addReg ( SrcReg ) . addFrameIndex ( FrameIndex ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) ;


<s> for ( int i = <NUM_LIT> , e = Desc . getNumOperands ( ) ; i != e ; ++ i ) { if ( MI -> getOperand ( i ) . isFPImm ( ) ) { ErrInfo = <STR_LIT> <STR_LIT> ; return false ; } int RegClass = Desc . OpInfo [ i ] . RegClass ; switch ( Desc . OpInfo [ i ] . OperandType ) { case MCOI :: OPERAND_REGISTER : if ( MI -> getOperand ( i ) . isImm ( ) ) { ErrInfo = <STR_LIT> ; return false ; } break ; case <STR_LIT> : break ; case <STR_LIT> : if ( isLiteralConstant ( MI -> getOperand ( i ) , RI . getRegClass ( RegClass ) -> getSize ( ) ) ) { ErrInfo = <STR_LIT> ; return false ; } break ; case MCOI :: OPERAND_IMMEDIATE : if ( ! MI -> getOperand ( i ) . isImm ( ) && ! MI -> getOperand ( i ) . isFI ( ) ) { ErrInfo = <STR_LIT> ; return false ; } default : continue ; } if ( ! MI -> getOperand ( i ) . isReg ( ) ) continue ; if ( RegClass != - <NUM_LIT> ) { unsigned Reg = MI -> getOperand ( i ) . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) continue ; const TargetRegisterClass * RC = RI . getRegClass ( RegClass ) ; if ( ! RC -> contains ( Reg ) ) { ErrInfo = <STR_LIT> ; return false ; } } } if ( isVOP1 ( Opcode ) || isVOP2 ( Opcode ) || isVOP3 ( Opcode ) || isVOPC ( Opcode ) ) { const int OpIndices [ ] = { Src0Idx , Src1Idx , Src2Idx } ; unsigned ConstantBusCount = <NUM_LIT> ; unsigned SGPRUsed = <STR_LIT> ; for ( int OpIdx : OpIndices ) { if ( OpIdx == - <NUM_LIT> ) break ; const MachineOperand & MO = MI -> getOperand ( OpIdx ) ; if ( usesConstantBus ( MRI , MO , getOpSize ( Opcode , OpIdx ) ) ) { if ( MO . isReg ( ) ) {

if ( MO . getReg ( ) != SGPRUsed ) ++ ConstantBusCount ;


<s> MachineInstr & UseMI = * I -> getParent ( ) ; if ( ! canReadVGPR ( UseMI , I . getOperandNo ( ) ) ) { Worklist . push_back ( & UseMI ) ; do {


<s> } BranchPredicate Pred = getBranchPredicate ( I -> getOpcode ( ) ) ; if ( Pred == INVALID_BR ) return true ; MachineBasicBlock * CondBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( Pred ) ) ; Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; ++ I ; if ( I == MBB . end ( ) ) { TBB = CondBB ; return false ;


<s> if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) ) return false ; if ( MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( AA && MIa . hasOneMemOperand ( ) && MIb . hasOneMemOperand ( ) ) { const MachineMemOperand * MMOa = * MIa . memoperands_begin ( ) ; const MachineMemOperand * MMOb = * MIb . memoperands_begin ( ) ; if ( MMOa -> getValue ( ) && MMOb -> getValue ( ) ) { MemoryLocation LocA ( MMOa -> getValue ( ) , MMOa -> getSize ( ) , MMOa -> getAAInfo ( ) ) ; MemoryLocation LocB ( MMOb -> getValue ( ) , MMOb -> getSize ( ) , MMOb -> getAAInfo ( ) ) ; if ( ! AA -> alias ( LocA , LocB ) ) return true ; } } if ( isDS ( MIa ) ) { if ( isDS ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) ; } if ( isMUBUF ( MIa ) || isMTBUF ( MIa ) ) {

if ( isMUBUF ( MIb ) || isMTBUF ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ;


<s> assert ( ( MIa . mayLoad ( ) || MIa . mayStore ( ) ) && <STR_LIT> ) ; assert ( ( MIb . mayLoad ( ) || MIb . mayStore ( ) ) && <STR_LIT> ) ; if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) ) return false ; if ( MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( AA && MIa . hasOneMemOperand ( ) && MIb . hasOneMemOperand ( ) ) { const MachineMemOperand * MMOa = * MIa . memoperands_begin ( ) ;

const MachineMemOperand * MMOb = * MIb . memoperands_begin ( ) ;


<s> MachineFunction * MF = MBB . getParent ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const <ISA_LIT>Subtarget & ST = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; unsigned WorkGroupSize = MFI -> getMaxFlatWorkGroupSize ( ) ; unsigned WavefrontSize = ST . getWavefrontSize ( ) ; unsigned TIDReg = MFI -> getTIDReg ( ) ; if ( ! MFI -> hasCalculatedTID ( ) ) { MachineBasicBlock & Entry = MBB . getParent ( ) -> front ( ) ; MachineBasicBlock :: iterator Insert = Entry . front ( ) ; DebugLoc DL = Insert -> getDebugLoc ( ) ; TIDReg = RI . findUnusedRegister ( MF -> getRegInfo ( ) , & <STR_LIT> , * MF ) ; if ( TIDReg == <STR_LIT> ) return TIDReg ; if ( ! <STR_LIT> ( MF -> getFunction ( ) -> getCallingConv ( ) ) && WorkGroupSize > WavefrontSize ) { unsigned TIDIGXReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: WORKGROUP_ID_X ) ; unsigned TIDIGYReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: WORKGROUP_ID_Y ) ; unsigned TIDIGZReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: WORKGROUP_ID_Z ) ; unsigned InputPtrReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: KERNARG_SEGMENT_PTR ) ; for ( unsigned Reg : { TIDIGXReg , TIDIGYReg , TIDIGZReg } ) { if ( ! Entry . isLiveIn ( Reg ) ) Entry . addLiveIn ( Reg ) ; } RS -> enterBasicBlock ( Entry ) ;

unsigned STmp0 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ;


<s> } } const MachineOperand * Dst = getNamedOperand ( MI , <STR_LIT> :: vdst ) ; const MachineOperand * Src0 = getNamedOperand ( MI , <STR_LIT> :: src0 ) ; const MachineOperand * Src0Mods = getNamedOperand ( MI , <STR_LIT> :: src0_modifiers ) ; const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; const MachineOperand * Src1Mods = getNamedOperand ( MI , <STR_LIT> :: src1_modifiers ) ; const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ; const MachineOperand * Clamp = getNamedOperand ( MI , <STR_LIT> :: clamp ) ; const MachineOperand * Omod = getNamedOperand ( MI , <STR_LIT> :: omod ) ; return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( IsF16 ? <STR_LIT> : <STR_LIT> ) ) . add ( * Dst ) . addImm ( Src0Mods ? Src0Mods -> getImm ( ) : <NUM_LIT> ) . add ( * Src0 ) . addImm ( Src1Mods ? Src1Mods -> getImm ( ) : <NUM_LIT> ) . add ( * Src1 ) . addImm ( <NUM_LIT> ) . add ( * Src2 ) . addImm ( Clamp ? Clamp -> getImm ( ) : <NUM_LIT> ) . addImm ( Omod ? Omod -> getImm ( ) : <NUM_LIT> ) ;


<s> } const MachineOperand * Dst = getNamedOperand ( MI , <STR_LIT> :: vdst ) ; const MachineOperand * Src0 = getNamedOperand ( MI , <STR_LIT> :: src0 ) ; const MachineOperand * Src0Mods = getNamedOperand ( MI , <STR_LIT> :: src0_modifiers ) ; const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; const MachineOperand * Src1Mods = getNamedOperand ( MI , <STR_LIT> :: src1_modifiers ) ; const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ; const MachineOperand * Clamp = getNamedOperand ( MI , <STR_LIT> :: clamp ) ; const MachineOperand * Omod = getNamedOperand ( MI , <STR_LIT> :: omod ) ; return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( IsF16 ? <STR_LIT> : <STR_LIT> ) ) . add ( * Dst ) . addImm ( Src0Mods ? Src0Mods -> getImm ( ) : <NUM_LIT> ) . add ( * Src0 ) . addImm ( Src1Mods ? Src1Mods -> getImm ( ) : <NUM_LIT> ) . add ( * Src1 ) . addImm ( <NUM_LIT> ) . add ( * Src2 ) . addImm ( Clamp ? Clamp -> getImm ( ) : <NUM_LIT> ) . addImm ( Omod ? Omod -> getImm ( ) : <NUM_LIT> ) ;


<s> BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( - <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; return ; } if ( ! <STR_LIT> . contains ( SrcReg ) ) { reportIllegalCopy ( this , MBB , MI , DL , DestReg , SrcReg , KillSrc ) ; return ; } BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( RC == & <STR_LIT> ) { if ( DestReg == <STR_LIT> ) { if ( <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } return ; } if ( ! <STR_LIT> . contains ( SrcReg ) ) { reportIllegalCopy ( this , MBB , MI , DL , DestReg , SrcReg , KillSrc ) ; return ; } BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( DestReg == <STR_LIT> ) { assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) ; return ; } unsigned EltSize = <NUM_LIT> ; unsigned Opcode = <STR_LIT> ; if ( RI . isSGPRClass ( RC ) ) { if ( RC -> getSize ( ) > <NUM_LIT> ) { Opcode = <STR_LIT> ; EltSize = <NUM_LIT> ; } else { Opcode = <STR_LIT> ;


<s> break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MCInstrDesc & MovRelDesc = get ( <STR_LIT> ) ; unsigned VecReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsUndef = MI . getOperand ( <NUM_LIT> ) . isUndef ( ) ; unsigned SubReg = <STR_LIT> + MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( VecReg == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineInstr * MovRel = BuildMI ( MBB , MI , DL , MovRelDesc ) . addReg ( RI . getSubReg ( VecReg , SubReg ) , RegState :: Undef ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( VecReg , RegState :: ImplicitDefine ) . addReg ( VecReg , RegState :: Implicit | ( IsUndef ? RegState :: Undef : <NUM_LIT> ) ) ; const int ImpDefIdx = MovRelDesc . getNumOperands ( ) + MovRelDesc . getNumImplicitUses ( ) ; const int ImpUseIdx = ImpDefIdx + <NUM_LIT> ; MovRel -> tieOperands ( ImpDefIdx , ImpUseIdx ) ; MI . eraseFromParent ( ) ; break ; } case <STR_LIT> : { MachineFunction & MF = * MBB . getParent ( ) ; unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned RegLo = RI . getSubReg ( Reg , <STR_LIT> ) ; unsigned RegHi = RI . getSubReg ( Reg , <STR_LIT> ) ; MIBundleBuilder Bundler ( MBB , MI ) ; Bundler . append ( BuildMI ( MF , DL , get ( <STR_LIT> ) , Reg ) ) ; Bundler . append ( BuildMI ( MF , DL , get ( <STR_LIT> ) , RegLo ) . addReg ( RegLo ) . add ( MI . getOperand ( <NUM_LIT> ) ) ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) , RegHi ) . addReg ( RegHi ) ; if ( MI . getOperand ( <NUM_LIT> ) . getTargetFlags ( ) == <ISA_LIT>InstrInfo :: MO_NONE ) MIB . addImm ( <NUM_LIT> ) ;

else MIB . add ( MI . getOperand ( <NUM_LIT> ) ) ;


<s> const MachineOperand * ImmOp = getNamedOperand ( DefMI , <STR_LIT> :: src0 ) ; assert ( ImmOp ) ; if ( ! ImmOp -> isImm ( ) ) { return false ; } UseMI . setDesc ( get ( NewOpc ) ) ; UseMI . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( ImmOp -> getImm ( ) ) ; UseMI . addImplicitDefUseOperands ( * UseMI . getParent ( ) -> getParent ( ) ) ; return true ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) { if ( hasAnyModifiersSet ( UseMI ) ) return false ; const MachineOperand & ImmOp = DefMI . getOperand ( <NUM_LIT> ) ; MachineOperand * Src0 = getNamedOperand ( UseMI , <STR_LIT> :: src0 ) ; if ( isInlineConstant ( UseMI , * Src0 , ImmOp ) ) return false ; bool IsF32 = Opc == <STR_LIT> || Opc == <STR_LIT> ; MachineOperand * Src1 = getNamedOperand ( UseMI , <STR_LIT> :: src1 ) ; MachineOperand * Src2 = getNamedOperand ( UseMI , <STR_LIT> :: src2 ) ; if ( Src0 -> isReg ( ) && Src0 -> getReg ( ) == Reg ) { if ( ! Src1 -> isReg ( ) || RI . isSGPRClass ( MRI -> getRegClass ( Src1 -> getReg ( ) ) ) ) return false ; if ( ! Src2 -> isReg ( ) || RI . isSGPRClass ( MRI -> getRegClass ( Src2 -> getReg ( ) ) ) ) return false ; const int64_t Imm = DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; UseMI . RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: omod ) ) ; UseMI . RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: clamp ) ) ; unsigned Src1Reg = Src1 -> getReg ( ) ; unsigned Src1SubReg = Src1 -> getSubReg ( ) ; Src0 -> setReg ( Src1Reg ) ; Src0 -> setSubReg ( Src1SubReg ) ; Src0 -> setIsKill ( Src1 -> isKill ( ) ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) UseMI . untieRegOperand ( <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ) ; Src1 -> ChangeToImmediate ( Imm ) ;


<s> unsigned UnusedCarry = MRI . createVirtualRegister ( & <STR_LIT> ) ; return BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( UnusedCarry , RegState :: Define | RegState :: Dead ) ;


<s> if ( isVALU ( MI ) || isSALU ( MI ) ) { if ( isFixedSize ( MI ) ) return DescSize ; int Src0Idx = <STR_LIT> ( Opc , <STR_LIT> :: src0 ) ; if ( Src0Idx == - <NUM_LIT> ) return <NUM_LIT> ; if ( isLiteralConstantLike ( MI . getOperand ( Src0Idx ) , Desc . OpInfo [ Src0Idx ] ) ) return <NUM_LIT> ; int Src1Idx = <STR_LIT> ( Opc , <STR_LIT> :: src1 ) ; if ( Src1Idx == - <NUM_LIT> ) return <NUM_LIT> ; if ( isLiteralConstantLike ( MI . getOperand ( Src1Idx ) , Desc . OpInfo [ Src1Idx ] ) ) return <NUM_LIT> ; return <NUM_LIT> ; } if ( DescSize == <NUM_LIT> ) return <NUM_LIT> ;


<s> if ( SOffset && SOffset -> isReg ( ) ) return false ; const MachineOperand * AddrReg = getNamedOperand ( LdSt , <STR_LIT> :: vaddr ) ; if ( ! AddrReg ) return false ; const MachineOperand * OffsetImm = getNamedOperand ( LdSt , <STR_LIT> :: offset ) ; BaseReg = AddrReg -> getReg ( ) ; Offset = OffsetImm -> getImm ( ) ; if ( SOffset ) Offset += SOffset -> getImm ( ) ; return true ; } if ( isSMRD ( LdSt ) ) { const MachineOperand * OffsetImm = getNamedOperand ( LdSt , <STR_LIT> :: offset ) ; if ( ! OffsetImm ) return false ; const MachineOperand * SBaseReg = getNamedOperand ( LdSt , <STR_LIT> :: sbase ) ; BaseReg = SBaseReg -> getReg ( ) ; Offset = OffsetImm -> getImm ( ) ; return true ; } if ( isFLAT ( LdSt ) ) { const MachineOperand * AddrReg = getNamedOperand ( LdSt , <STR_LIT> :: vaddr ) ; BaseReg = AddrReg -> getReg ( ) ; Offset = <NUM_LIT> ; return true ;


<s> default : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . isReg ( ) ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> preserveCondRegFlags ( CondBr -> getOperand ( <NUM_LIT> ) , Cond [ <NUM_LIT> ] ) ; if ( BytesAdded ) * BytesAdded = <NUM_LIT> ; return <NUM_LIT> ; } assert ( TBB && FBB ) ; MachineInstr * CondBr = BuildMI ( & MBB , DL , get ( Opcode ) ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; MachineOperand & CondReg = CondBr -> getOperand ( <NUM_LIT> ) ;

CondReg . setIsUndef ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ;


<s> preserveCondRegFlags ( CondBr -> getOperand ( <NUM_LIT> ) , Cond [ <NUM_LIT> ] ) ; if ( BytesAdded ) * BytesAdded = <NUM_LIT> ; return <NUM_LIT> ; } assert ( TBB && FBB ) ; MachineInstr * CondBr = BuildMI ( & MBB , DL , get ( Opcode ) ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; MachineOperand & CondReg = CondBr -> getOperand ( <NUM_LIT> ) ; CondReg . setIsUndef ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; CondReg . setIsKill ( Cond [ <NUM_LIT> ] . isKill ( ) ) ; if ( BytesAdded ) * BytesAdded = <NUM_LIT> ;


<s> unsigned SelOp = Pred == SCC_TRUE ? <STR_LIT> : <STR_LIT> ; MachineInstr * Select = BuildMI ( MBB , I , DL , get ( SelOp ) , DstReg ) . addReg ( FalseReg ) . addReg ( TrueReg ) ; preserveCondRegFlags ( Select -> getOperand ( <NUM_LIT> ) , Cond [ <NUM_LIT> ] ) ; return ; } if ( DstSize == <NUM_LIT> && Pred == SCC_TRUE ) { MachineInstr * Select = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( FalseReg ) . addReg ( TrueReg ) ; preserveCondRegFlags ( Select -> getOperand ( <NUM_LIT> ) , Cond [ <NUM_LIT> ] ) ; return ; } static const int16_t Sub0_15 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; static const int16_t Sub0_15_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; unsigned SelOp = <STR_LIT> ; const TargetRegisterClass * EltRC = & <STR_LIT> ; const int16_t * SubIndices = Sub0_15 ; int NElts = DstSize / <NUM_LIT> ; if ( Pred == SCC_TRUE ) { SelOp = <STR_LIT> ; EltRC = & <STR_LIT> ; SubIndices = Sub0_15_64 ; assert ( NElts % <NUM_LIT> == <NUM_LIT> ) ; NElts /= <NUM_LIT> ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) ; I = MIB -> getIterator ( ) ; SmallVector < unsigned , <NUM_LIT> > Regs ; for ( int Idx = <NUM_LIT> ; Idx != NElts ; ++ Idx ) {

unsigned DstElt = MRI . createVirtualRegister ( EltRC ) ;


<s> } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { return <STR_LIT> ( MO . getImm ( ) , ST . hasInv2PiInlineImm ( ) ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( isInt < <NUM_LIT> > ( Imm ) || isUInt < <NUM_LIT> > ( Imm ) ) { int16_t Trunc = static_cast < int16_t > ( Imm ) ; return ST . has16BitInsts ( ) && <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ; } return false ; }


<s> MRI . constrainRegClass ( DestReg , & <STR_LIT> ) ; } MachineInstrBuilder Spill = BuildMI ( MBB , MI , DL , OpDesc , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getScratchWaveOffsetReg ( ) , RegState :: Implicit ) ; if ( ST . hasScalarStores ( ) ) { Spill . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; } return ; } if ( ! ST . isVGPRSpillingEnabled ( * MF -> getFunction ( ) ) ) { LLVMContext & Ctx = MF -> getFunction ( ) -> getContext ( ) ; Ctx . emitError ( <STR_LIT> <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) ; return ; } assert ( RI . hasVGPRs ( RC ) && <STR_LIT> ) ; unsigned Opcode = getVGPRSpillRestoreOpcode ( RC -> getSize ( ) ) ; BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) . addFrameIndex ( FrameIndex ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI -> getScratchWaveOffsetReg ( ) ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> if ( ! ST . isVGPRSpillingEnabled ( * MF -> getFunction ( ) ) ) { LLVMContext & Ctx = MF -> getFunction ( ) -> getContext ( ) ; Ctx . emitError ( <STR_LIT> <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) ; return ; } assert ( RI . hasVGPRs ( RC ) && <STR_LIT> ) ; unsigned Opcode = getVGPRSpillRestoreOpcode ( RC -> getSize ( ) ) ; BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) . addFrameIndex ( FrameIndex ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI -> getScratchWaveOffsetReg ( ) ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> case <STR_LIT> : { unsigned ImmReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , Inst , DL , get ( <STR_LIT> ) , ImmReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , Inst , DL , get ( <STR_LIT> ) , ResultReg ) . addReg ( ImmReg , RegState :: Kill ) . add ( Src0 ) . add ( Src1 ) ; break ; } case <STR_LIT> : { unsigned ImmReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned TmpReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , Inst , DL , get ( <STR_LIT> ) , TmpReg ) . addImm ( <NUM_LIT> ) . add ( Src0 ) ; BuildMI ( * MBB , Inst , DL , get ( <STR_LIT> ) , ImmReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , Inst , DL , get ( <STR_LIT> ) , ResultReg ) . add ( Src1 ) . addReg ( ImmReg , RegState :: Kill ) . addReg ( TmpReg , RegState :: Kill ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ;