<s> SDValue OneSubAC = DAG . getNode ( <STR_LIT> , DL , VT , OneSubA , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) , OneSubAC ) ;


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BC , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BC , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue CvtHi = DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT> , SL , <STR_LIT> , Hi ) ; SDValue CvtLo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo ) ; SDValue LdExp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , CvtHi , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LdExp , CvtLo ) ;


<s> EVT VT = Op . getValueType ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; if ( ExtType == <STR_LIT> && VT . getSizeInBits ( ) < <NUM_LIT> ) { assert ( VT == <STR_LIT> && <STR_LIT> ) ; SDValue Chain = Load -> getChain ( ) ; SDValue BasePtr = Load -> getBasePtr ( ) ; MachineMemOperand * MMO = Load -> getMemOperand ( ) ; SDValue NewLD = DAG . getExtLoad ( <STR_LIT> , DL , <STR_LIT> , Chain , BasePtr , <STR_LIT> , MMO ) ; SDValue Ops [ ] = { DAG . getNode ( <STR_LIT> , DL , VT , NewLD ) , NewLD . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( Ops , DL ) ; } if ( Subtarget -> getGeneration ( ) >= <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS || Load -> getAddressSpace ( ) != <ISA_LIT>AS :: PRIVATE_ADDRESS || ExtType == <STR_LIT> || Load -> getMemoryVT ( ) . bitsGE ( <STR_LIT> ) ) return SDValue ( ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Load -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Ret = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Load -> getChain ( ) , Ptr , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Load -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Ret = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ret , ShiftAmt ) ; EVT MemEltVT = MemVT . getScalarType ( ) ;


<s> SDValue Ops [ ] = { DAG . getNode ( <STR_LIT> , DL , VT , NewLD ) , NewLD . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( Ops , DL ) ; } if ( Subtarget -> getGeneration ( ) >= <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS || Load -> getAddressSpace ( ) != <ISA_LIT>AS :: PRIVATE_ADDRESS || ExtType == <STR_LIT> || Load -> getMemoryVT ( ) . bitsGE ( <STR_LIT> ) ) return SDValue ( ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Load -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Ret = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Load -> getChain ( ) , Ptr , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Load -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Ret = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ret , ShiftAmt ) ; EVT MemEltVT = MemVT . getScalarType ( ) ;


<s> Op . getNode ( ) -> dump ( ) ; llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; break ; case <STR_LIT> : return Lower<ISA_LIT>GN_EXTEND_INREG ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerFrameIndex ( Op , DAG ) ; case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerFREM ( Op , DAG ) ; case <STR_LIT> : return LowerFCEIL ( Op , DAG ) ; case <STR_LIT> : return LowerFTRUNC ( Op , DAG ) ;

case <STR_LIT> : return LowerFRINT ( Op , DAG ) ;


<s> case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerFREM ( Op , DAG ) ; case <STR_LIT> : return LowerFCEIL ( Op , DAG ) ; case <STR_LIT> : return LowerFTRUNC ( Op , DAG ) ; case <STR_LIT> : return LowerFRINT ( Op , DAG ) ; case <STR_LIT> : return LowerFNEARBYINT ( Op , DAG ) ; case <STR_LIT> : return LowerFROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFFLOOR ( Op , DAG ) ; case <STR_LIT> : return Lower<ISA_LIT>NT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_<ISA_LIT>NT ( Op , DAG ) ;

case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , SDLoc DL , SelectionDAG & DAG ) const { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain ) ;


<s> SDValue DIVREM = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( HalfVT , HalfVT ) , LHS_Lo , RHS_Lo ) ; SDValue Res [ <NUM_LIT> ] = { DAG . getNode ( <STR_LIT> , DL , VT , DIVREM . getValue ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , VT , DIVREM . getValue ( <NUM_LIT> ) ) } ; return DAG . getMergeValues ( Res , DL ) ; } SDValue LHSign = DAG . getSelectCC ( DL , LHS , Zero , NegOne , Zero , <STR_LIT> ) ; SDValue RHSign = DAG . getSelectCC ( DL , RHS , Zero , NegOne , Zero , <STR_LIT> ) ; SDValue DSign = DAG . getNode ( <STR_LIT> , DL , VT , LHSign , RHSign ) ; SDValue RSign = LHSign ; LHS = DAG . getNode ( <STR_LIT> , DL , VT , LHS , LHSign ) ; RHS = DAG . getNode ( <STR_LIT> , DL , VT , RHS , RHSign ) ; LHS = DAG . getNode ( <STR_LIT> , DL , VT , LHS , LHSign ) ; RHS = DAG . getNode ( <STR_LIT> , DL , VT , RHS , RHSign ) ; SDValue Div = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , VT ) , LHS , RHS ) ; SDValue Rem = Div . getValue ( <NUM_LIT> ) ; Div = DAG . getNode ( <STR_LIT> , DL , VT , Div , DSign ) ; Rem = DAG . getNode ( <STR_LIT> , DL , VT , Rem , RSign ) ; Div = DAG . getNode ( <STR_LIT> , DL , VT , Div , DSign ) ; Rem = DAG . getNode ( <STR_LIT> , DL , VT , Rem , RSign ) ;


<s> } EVT MemVT = Store -> getMemoryVT ( ) ; if ( Store -> getAddressSpace ( ) == <ISA_LIT>AS :: PRIVATE_ADDRESS && MemVT . bitsLT ( <STR_LIT> ) ) { unsigned Mask = <NUM_LIT> ; if ( Store -> getMemoryVT ( ) == <STR_LIT> ) { Mask = <NUM_LIT> ; } else if ( Store -> getMemoryVT ( ) == <STR_LIT> ) { Mask = <NUM_LIT> ; } SDValue BasePtr = Store -> getBasePtr ( ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Dst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , Ptr , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SExtValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Store -> getValue ( ) ) ; SDValue MaskedValue = DAG . getZeroExtendInReg ( SExtValue , DL , MemVT ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MaskedValue , ShiftAmt ) ; SDValue DstMask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( Mask , DL , <STR_LIT> ) , ShiftAmt ) ; DstMask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DstMask , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Dst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Dst , DstMask ) ; SDValue Value = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Dst , ShiftedValue ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , Value , Ptr , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> if ( ( Store -> getAddressSpace ( ) == <ISA_LIT>AS :: LOCAL_ADDRESS || Store -> getAddressSpace ( ) == <ISA_LIT>AS :: PRIVATE_ADDRESS ) && Store -> getValue ( ) . getValueType ( ) . isVector ( ) ) { return SplitVectorStore ( Op , DAG ) ; } EVT MemVT = Store -> getMemoryVT ( ) ; if ( Store -> getAddressSpace ( ) == <ISA_LIT>AS :: PRIVATE_ADDRESS && MemVT . bitsLT ( <STR_LIT> ) ) { unsigned Mask = <NUM_LIT> ; if ( Store -> getMemoryVT ( ) == <STR_LIT> ) { Mask = <NUM_LIT> ; } else if ( Store -> getMemoryVT ( ) == <STR_LIT> ) { Mask = <NUM_LIT> ; } SDValue BasePtr = Store -> getBasePtr ( ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Dst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , Ptr , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;

SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> SDValue Num = Op . getOperand ( <NUM_LIT> ) ; SDValue Den = Op . getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { if ( DAG . MaskedValueIsZero ( Num , APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) && DAG . MaskedValueIsZero ( Den , APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ) { return LowerDIVREM24 ( Op , DAG , false ) ; } } SDValue RCP = DAG . getNode ( <STR_LIT> , DL , VT , Den ) ; SDValue RCP_LO = DAG . getNode ( <STR_LIT> , DL , VT , RCP , Den ) ; SDValue RCP_HI = DAG . getNode ( <STR_LIT> , DL , VT , RCP , Den ) ; SDValue NEG_RCP_LO = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , RCP_LO ) ; SDValue ABS_RCP_LO = DAG . getSelectCC ( DL , RCP_HI , DAG . getConstant ( <NUM_LIT> , DL , VT ) , NEG_RCP_LO , RCP_LO , <STR_LIT> ) ; SDValue E = DAG . getNode ( <STR_LIT> , DL , VT , ABS_RCP_LO , RCP ) ; SDValue RCP_A_E = DAG . getNode ( <STR_LIT> , DL , VT , RCP , E ) ; SDValue RCP_S_E = DAG . getNode ( <STR_LIT> , DL , VT , RCP , E ) ; SDValue Tmp0 = DAG . getSelectCC ( DL , RCP_HI , DAG . getConstant ( <NUM_LIT> , DL , VT ) , RCP_A_E , RCP_S_E , <STR_LIT> ) ; SDValue Quotient = DAG . getNode ( <STR_LIT> , DL , VT , Tmp0 , Num ) ; SDValue Num_S_Remainder = DAG . getNode ( <STR_LIT> , DL , VT , Quotient , Den ) ; SDValue Remainder = DAG . getNode ( <STR_LIT> , DL , VT , Num , Num_S_Remainder ) ; SDValue Remainder_GE_Den = DAG . getSelectCC ( DL , Remainder , Den , DAG . getConstant ( - <NUM_LIT> , DL , VT ) , DAG . getConstant ( <NUM_LIT> , DL , VT ) , <STR_LIT> ) ; SDValue Remainder_GE_Zero = DAG . getSelectCC ( DL , Num , Num_S_Remainder , DAG . getConstant ( - <NUM_LIT> , DL , VT ) , DAG . getConstant ( <NUM_LIT> , DL , VT ) , <STR_LIT> ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , DL , VT , Remainder_GE_Den , Remainder_GE_Zero ) ; SDValue Quotient_A_One = DAG . getNode ( <STR_LIT> , DL , VT , Quotient , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Quotient_S_One = DAG . getNode ( <STR_LIT> , DL , VT , Quotient , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Div = DAG . getSelectCC ( DL , Tmp1 , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Quotient , Quotient_A_One , <STR_LIT> ) ;

Div = DAG . getSelectCC ( DL , Remainder_GE_Zero , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Quotient_S_One , Div , <STR_LIT> ) ;


<s> EVT VT = Op . getValueType ( ) ; EVT HalfVT = VT . getHalfSizedIntegerVT ( * DAG . getContext ( ) ) ; SDValue one = DAG . getConstant ( <NUM_LIT> , DL , HalfVT ) ; SDValue zero = DAG . getConstant ( <NUM_LIT> , DL , HalfVT ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS_Lo = DAG . getNode ( <STR_LIT> , DL , HalfVT , LHS , zero ) ; SDValue LHS_Hi = DAG . getNode ( <STR_LIT> , DL , HalfVT , LHS , one ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS_Lo = DAG . getNode ( <STR_LIT> , DL , HalfVT , RHS , zero ) ; SDValue RHS_Hi = DAG . getNode ( <STR_LIT> , DL , HalfVT , RHS , one ) ; if ( VT == <STR_LIT> && DAG . MaskedValueIsZero ( RHS , APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) && DAG . MaskedValueIsZero ( LHS , APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ) { SDValue Res = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( HalfVT , HalfVT ) , LHS_Lo , RHS_Lo ) ; SDValue DIV = DAG . getNode ( <STR_LIT> , DL , VT , Res . getValue ( <NUM_LIT> ) , zero ) ; SDValue REM = DAG . getNode ( <STR_LIT> , DL , VT , Res . getValue ( <NUM_LIT> ) , zero ) ; Results . push_back ( DIV ) ; Results . push_back ( REM ) ; return ;


<s> Results . push_back ( REM ) ; return ; } SDValue DIV_Part = DAG . getNode ( <STR_LIT> , DL , HalfVT , LHS_Hi , RHS_Lo ) ; SDValue REM_Part = DAG . getNode ( <STR_LIT> , DL , HalfVT , LHS_Hi , RHS_Lo ) ; SDValue REM_Lo = DAG . getSelectCC ( DL , RHS_Hi , zero , REM_Part , LHS_Hi , <STR_LIT> ) ; SDValue REM = DAG . getNode ( <STR_LIT> , DL , VT , REM_Lo , zero ) ; SDValue DIV_Hi = DAG . getSelectCC ( DL , RHS_Hi , zero , DIV_Part , zero , <STR_LIT> ) ; SDValue DIV_Lo = zero ; const unsigned halfBitWidth = HalfVT . getSizeInBits ( ) ; for ( unsigned i = <NUM_LIT> ; i < halfBitWidth ; ++ i ) { const unsigned bitPos = halfBitWidth - i - <NUM_LIT> ; SDValue POS = DAG . getConstant ( bitPos , DL , HalfVT ) ; SDValue HBit = DAG . getNode ( <STR_LIT> , DL , HalfVT , LHS_Lo , POS ) ; HBit = DAG . getNode ( <STR_LIT> , DL , HalfVT , HBit , one ) ; HBit = DAG . getNode ( <STR_LIT> , DL , VT , HBit ) ; REM = DAG . getNode ( <STR_LIT> , DL , VT , REM , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; REM = DAG . getNode ( <STR_LIT> , DL , VT , REM , HBit ) ; SDValue BIT = DAG . getConstant ( <NUM_LIT> << bitPos , DL , HalfVT ) ; SDValue realBIT = DAG . getSelectCC ( DL , REM , RHS , BIT , zero , <STR_LIT> ) ; DIV_Lo = DAG . getNode ( <STR_LIT> , DL , HalfVT , DIV_Lo , realBIT ) ; SDValue REM_sub = DAG . getNode ( <STR_LIT> , DL , VT , REM , RHS ) ; REM = DAG . getSelectCC ( DL , REM , RHS , REM_sub , REM , <STR_LIT> ) ; }

SDValue DIV = DAG . getNode ( <STR_LIT> , DL , VT , DIV_Lo , DIV_Hi ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerUINT_TO_FP ( SDValue Op , SelectionDAG & DAG ) const { SDValue S0 = Op . getOperand ( <NUM_LIT> ) ; if ( S0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; EVT DestVT = Op . getValueType ( ) ; if ( DestVT == <STR_LIT> ) return LowerINT_TO_FP64 ( Op , DAG , false ) ; assert ( DestVT == <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , S0 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue FloatLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , S0 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue FloatHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ;

FloatHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FloatHi , DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> unsigned MemEltBits = MemEltVT . getSizeInBits ( ) ; unsigned MemNumElements = MemVT . getVectorNumElements ( ) ; unsigned PackedSize = MemVT . getStoreSizeInBits ( ) ; SDValue Mask = DAG . getConstant ( ( <NUM_LIT> << MemEltBits ) - <NUM_LIT> , DL , <STR_LIT> ) ; assert ( Value . getValueType ( ) . getScalarSizeInBits ( ) >= <NUM_LIT> ) ; SDValue PackedValue ; for ( unsigned i = <NUM_LIT> ; i < MemNumElements ; ++ i ) { SDValue Elt = DAG . getNode ( <STR_LIT> , DL , ElemVT , Value , DAG . getConstant ( i , DL , <STR_LIT> ) ) ; Elt = DAG . getZExtOrTrunc ( Elt , DL , <STR_LIT> ) ; Elt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Elt , Mask ) ; SDValue Shift = DAG . getConstant ( MemEltBits * i , DL , <STR_LIT> ) ; Elt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Elt , Shift ) ; if ( i == <NUM_LIT> ) {


<s> unsigned SignBits = Signed ? ( <NUM_LIT> - WidthVal + <NUM_LIT> ) : ( <NUM_LIT> - WidthVal ) ; unsigned OpSignBits = DAG . ComputeNumSignBits ( BitsFrom ) ; if ( OpSignBits >= SignBits ) return BitsFrom ; EVT SmallVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , WidthVal ) ; if ( Signed ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BitsFrom , DAG . getValueType ( SmallVT ) ) ; } return DAG . getZeroExtendInReg ( BitsFrom , DL , SmallVT ) ; } if ( ConstantSDNode * CVal = dyn_cast < ConstantSDNode > ( BitsFrom ) ) { if ( Signed ) { return constantFoldBFE < int32_t > ( DAG , CVal -> getSExtValue ( ) , OffsetVal , WidthVal , DL ) ; } return constantFoldBFE < uint32_t > ( DAG , CVal -> getZExtValue ( ) , OffsetVal , WidthVal , DL ) ; } if ( ( OffsetVal + WidthVal ) >= <NUM_LIT> ) { SDValue ShiftVal = DAG . getConstant ( OffsetVal , DL , <STR_LIT> ) ; return DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , BitsFrom , ShiftVal ) ; } if ( BitsFrom . hasOneUse ( ) ) { APInt Demanded = APInt :: getBitsSet ( <NUM_LIT> , OffsetVal , OffsetVal + WidthVal ) ; APInt KnownZero , KnownOne ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLO . ShrinkDemandedConstant ( BitsFrom , Demanded ) || TLI . SimplifyDemandedBits ( BitsFrom , Demanded , KnownZero , KnownOne , TLO ) ) { DCI . CommitTargetLoweringOpt ( TLO ) ; } } break ; } case <STR_LIT> : return performStoreCombine ( N , DCI ) ;


<s> SDValue <ISA_LIT>TargetLowering :: performMulCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > <NUM_LIT> ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Mul ; if ( Subtarget -> hasMulU24 ( ) && isU24 ( N0 , DAG ) && isU24 ( N1 , DAG ) ) { N0 = DAG . getZExtOrTrunc ( N0 , DL , <STR_LIT> ) ; N1 = DAG . getZExtOrTrunc ( N1 , DL , <STR_LIT> ) ; Mul = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 , N1 ) ; } else if ( Subtarget -> hasMulI24 ( ) && isI24 ( N0 , DAG ) && isI24 ( N1 , DAG ) ) { N0 = DAG . getSExtOrTrunc ( N0 , DL , <STR_LIT> ) ; N1 = DAG . getSExtOrTrunc ( N1 , DL , <STR_LIT> ) ; Mul = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 , N1 ) ;


<s> SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDLoc SL ( N ) ; SelectionDAG & DAG = DCI . DAG ; SDValue Lo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LHS ) ;

const SDValue Zero = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: performShlCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHS || RHS -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDLoc SL ( N ) ; SelectionDAG & DAG = DCI . DAG ; SDValue Lo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LHS ) ;


<s> EVT LoadVT = getEquivalentMemType ( * DAG . getContext ( ) , MemVT ) ; SDValue NewLoad = DAG . getLoad ( <STR_LIT> , <STR_LIT> , LoadVT , SL , LoadVal -> getChain ( ) , LoadVal -> getBasePtr ( ) , LoadVal -> getOffset ( ) , LoadVT , LoadVal -> getMemOperand ( ) ) ; SDValue CastLoad = DAG . getNode ( <STR_LIT> , SL , VT , NewLoad . getValue ( <NUM_LIT> ) ) ; DCI . CombineTo ( LoadVal , CastLoad , NewLoad . getValue ( <NUM_LIT> ) , false ) ;

return DAG . getStore ( SN -> getChain ( ) , SL , NewLoad , SN -> getBasePtr ( ) , SN -> getMemOperand ( ) ) ;


<s> virtual SDNode * PostISelFolding ( MachineSDNode * N , SelectionDAG & DAG ) const {


<s> switch ( N -> getOpcode ( ) ) { case <STR_LIT> : return ; case <STR_LIT> : { SDNode * Node = LowerLOAD ( SDValue ( N , <NUM_LIT> ) , DAG ) . getNode ( ) ; if ( ! Node ) return ; Results . push_back ( SDValue ( Node , <NUM_LIT> ) ) ; Results . push_back ( SDValue ( Node , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , SDValue ( Node , <NUM_LIT> ) ) ; return ;


<s> SDValue NewLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , EltVT , Load -> getChain ( ) , Ptr , SrcValue . getWithOffset ( i * MemEltSize ) , MemEltVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> isInvariant ( ) , Load -> getAlignment ( ) ) ; Loads . push_back ( NewLoad . getValue ( <NUM_LIT> ) ) ; Chains . push_back ( NewLoad . getValue ( <NUM_LIT> ) ) ; } SDValue Ops [ ] = { DAG . getNode ( <STR_LIT> , SL , LoadVT , Loads ) , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Chains ) } ;

return DAG . getMergeValues ( Ops , SL ) ;


<s> SDLoc SL ( Op ) ; SmallVector < SDValue , <NUM_LIT> > Chains ; unsigned EltSize = MemEltVT . getStoreSize ( ) ; MachinePointerInfo SrcValue ( Store -> getMemOperand ( ) -> getValue ( ) ) ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) { SDValue Val = DAG . getNode ( <STR_LIT> , SL , EltVT , Store -> getValue ( ) , DAG . getConstant ( i , SL , <STR_LIT> ) ) ; SDValue Offset = DAG . getConstant ( i * MemEltVT . getStoreSize ( ) , SL , PtrVT ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , PtrVT , Store -> getBasePtr ( ) , Offset ) ; SDValue NewStore = DAG . getTruncStore ( Store -> getChain ( ) , SL , Val , Ptr , SrcValue . getWithOffset ( i * EltSize ) , MemEltVT , Store -> isNonTemporal ( ) , Store -> isVolatile ( ) , Store -> getAlignment ( ) ) ; Chains . push_back ( NewStore ) ; }

return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Chains ) ;


<s> for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) { SDValue Val = DAG . getNode ( <STR_LIT> , SL , EltVT , Store -> getValue ( ) , DAG . getConstant ( i , SL , <STR_LIT> ) ) ; SDValue Offset = DAG . getConstant ( i * MemEltVT . getStoreSize ( ) , SL , PtrVT ) ;

SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , PtrVT , Store -> getBasePtr ( ) , Offset ) ;


<s> bool <ISA_LIT>TargetLowering :: shouldReduceLoadWidth ( SDNode * N , <STR_LIT> , EVT NewVT ) const {

unsigned NewSize = NewVT . getStoreSizeInBits ( ) ;


<s> APInt Demanded = APInt :: getLowBitsSet ( VT . getSizeInBits ( ) , <NUM_LIT> ) ; APInt KnownZero , KnownOne ; TargetLowering :: TargetLoweringOpt TLO ( DAG , true , true ) ; if ( TLI . SimplifyDemandedBits ( Op , Demanded , KnownZero , KnownOne , TLO ) ) DCI . CommitTargetLoweringOpt ( TLO ) ;


<s> if ( VT . getVectorNumElements ( ) == <NUM_LIT> ) return ScalarizeVectorLoad ( Op , DAG ) ; LoadSDNode * Load = cast < LoadSDNode > ( Op ) ; SDValue BasePtr = Load -> getBasePtr ( ) ; EVT PtrVT = BasePtr . getValueType ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; SDLoc SL ( Op ) ; const MachinePointerInfo & SrcValue = Load -> getMemOperand ( ) -> getPointerInfo ( ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Op , SL , LoVT , HiVT ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned BaseAlign = Load -> getAlignment ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , LoVT , Load -> getChain ( ) , BasePtr , SrcValue , LoMemVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> isInvariant ( ) , BaseAlign ) ; SDValue HiPtr = DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( Size , SL , PtrVT ) ) ; SDValue HiLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , HiVT , Load -> getChain ( ) , HiPtr , SrcValue . getWithOffset ( LoMemVT . getStoreSize ( ) ) , HiMemVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> isInvariant ( ) , HiAlign ) ; SDValue Ops [ ] = { DAG . getNode ( <STR_LIT> , SL , VT , LoLoad , HiLoad ) , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LoLoad . getValue ( <NUM_LIT> ) , HiLoad . getValue ( <NUM_LIT> ) ) } ;


<s> EVT MemVT = Store -> getMemoryVT ( ) ; SDValue Chain = Store -> getChain ( ) ; SDValue BasePtr = Store -> getBasePtr ( ) ; SDLoc SL ( Op ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Val , SL , LoVT , HiVT ) ; EVT PtrVT = BasePtr . getValueType ( ) ; SDValue HiPtr = DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( LoMemVT . getStoreSize ( ) , SL , PtrVT ) ) ;

const MachinePointerInfo & SrcValue = Store -> getMemOperand ( ) -> getPointerInfo ( ) ;


<s> if ( VT . getVectorNumElements ( ) == <NUM_LIT> ) return ScalarizeVectorStore ( Op , DAG ) ; EVT MemVT = Store -> getMemoryVT ( ) ; SDValue Chain = Store -> getChain ( ) ; SDValue BasePtr = Store -> getBasePtr ( ) ; SDLoc SL ( Op ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Val , SL , LoVT , HiVT ) ; EVT PtrVT = BasePtr . getValueType ( ) ; SDValue HiPtr = DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( LoMemVT . getStoreSize ( ) , SL , PtrVT ) ) ;


<s> bool <ISA_LIT>TargetLowering :: storeOfVectorConstantIsCheap ( EVT MemVT , unsigned NumElem , unsigned AS ) const { return true ;


<s> for ( SDNode :: use_iterator I = LoadVal -> use_begin ( ) ; ! I . atEnd ( ) ; ++ I ) {

if ( ! <STR_LIT> ( * I ) ) return false ;


<s> bool mayIgnoreSignedZero ( SDValue Op ) const { if ( getTargetMachine ( ) . Options . NoSignedZerosFPMath ) return true ;

if ( const auto * BO = dyn_cast < BinaryWithFlagsSDNode > ( Op ) ) return BO -> Flags . hasNoSignedZeros ( ) ;


<s> if ( const auto * BO = dyn_cast < BinaryWithFlagsSDNode > ( Op ) ) return BO -> Flags . hasNoSignedZeros ( ) ;


<s> case <STR_LIT> : { return allocateCCRegs ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State , & <STR_LIT> , <NUM_LIT> ) ; } default :


<s> } break ; } case <STR_LIT> : { ConstantSDNode * CMask = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! CMask ) return ; KnownBits LHSKnown = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; KnownBits RHSKnown = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned Sel = CMask -> getZExtValue ( ) ; for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; I += <NUM_LIT> ) { unsigned SelBits = Sel & <NUM_LIT> ; if ( SelBits < <NUM_LIT> ) { SelBits *= <NUM_LIT> ; Known . One |= ( ( RHSKnown . One . getZExtValue ( ) >> SelBits ) & <NUM_LIT> ) << I ; Known . Zero |= ( ( RHSKnown . Zero . getZExtValue ( ) >> SelBits ) & <NUM_LIT> ) << I ; } else if ( SelBits < <NUM_LIT> ) { SelBits = ( SelBits & <NUM_LIT> ) * <NUM_LIT> ; Known . One |= ( ( LHSKnown . One . getZExtValue ( ) >> SelBits ) & <NUM_LIT> ) << I ; Known . Zero |= ( ( LHSKnown . Zero . getZExtValue ( ) >> SelBits ) & <NUM_LIT> ) << I ; } else if ( SelBits == <NUM_LIT> ) { Known . Zero |= <NUM_LIT> << I ; } else if ( SelBits > <NUM_LIT> ) { Known . One |= <NUM_LIT> << I ; } Sel >>= <NUM_LIT> ; } break ; } case <STR_LIT> : { Known . Zero . setHighBits ( <NUM_LIT> ) ; break ; } case <STR_LIT> : { Known . Zero . setHighBits ( <NUM_LIT> ) ; break ; } case <STR_LIT> : { unsigned IID = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IID ) { case <STR_LIT> : case <STR_LIT> : { const GCNSubtarget & ST = DAG . getMachineFunction ( ) . getSubtarget < GCNSubtarget > ( ) ; unsigned Size = Op . getValueType ( ) . getSizeInBits ( ) ; Known . Zero . setHighBits ( Size - ST . getWavefrontSizeLog2 ( ) ) ; break ; } default : break ; }


<s> const GCNSubtarget & ST = DAG . getMachineFunction ( ) . getSubtarget < GCNSubtarget > ( ) ; int64_t OffsetVal = <NUM_LIT> ; if ( ST . hasFlatInstOffsets ( ) && ( ! ST . hasFlatSegmentOffsetBug ( ) || findMemSDNode ( N ) -> getAddressSpace ( ) != <ISA_LIT>AS :: FLAT_ADDRESS ) && DAG . isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; int64_t COffsetVal = cast < ConstantSDNode > ( N1 ) -> getSExtValue ( ) ; if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) { if ( ( IsSigned && isInt < <NUM_LIT> > ( COffsetVal ) ) || ( ! IsSigned && isUInt < <NUM_LIT> > ( COffsetVal ) ) ) { Addr = N0 ; OffsetVal = COffsetVal ; } } else { if ( ( IsSigned && isInt < <NUM_LIT> > ( COffsetVal ) ) || ( ! IsSigned && isUInt < <NUM_LIT> > ( COffsetVal ) ) ) { Addr = N0 ; OffsetVal = COffsetVal ; } } } VAddr = Addr ; Offset = DAG . getTargetConstant ( OffsetVal , SDLoc ( ) , <STR_LIT> ) ;

SLC = DAG . getTargetConstant ( <NUM_LIT> , SDLoc ( ) , <STR_LIT> ) ;


<s> <ISA_LIT>MachineFunction * MFI = MF . getInfo < <ISA_LIT>MachineFunction > ( ) ; uint64_t Offset = MFI -> allocateKernArg ( ValVT . getStoreSize ( ) , ArgFlags . getOrigAlign ( ) ) ; State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return true ;


<s> uint64_t Offset = MFI -> allocateKernArg ( ValVT . getStoreSize ( ) , ArgFlags . getOrigAlign ( ) ) ; State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ;


<s> } case <STR_LIT> : case <STR_LIT> : { ConstantSDNode * CWidth = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! CWidth ) return ; unsigned BitWidth = <NUM_LIT> ; uint32_t Width = CWidth -> getZExtValue ( ) & <NUM_LIT> ;

if ( Opc == <STR_LIT> ) KnownZero = APInt :: getHighBitsSet ( BitWidth , BitWidth - Width ) ;


<s> if ( VT != <STR_LIT> ) Op = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Op ) ; SDValue FFBH = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Op ) ; if ( VT != <STR_LIT> ) FFBH = DAG . getNode ( <STR_LIT> , SL , VT , FFBH ) ; return FFBH ;


<s> static SDValue getFFBH_U32 ( const TargetLowering & TLI , SelectionDAG & DAG , const SDLoc & SL , SDValue Op ) { EVT VT = Op . getValueType ( ) ; EVT LegalVT = TLI . getTypeToTransformTo ( * DAG . getContext ( ) , VT ) ;

if ( LegalVT != <STR_LIT> ) return SDValue ( ) ;


<s> uint64_t ArgOffset = MFI -> getABIArgOffset ( ) ; switch ( Param ) { case GRID_DIM : return ArgOffset ; case GRID_OFFSET : return ArgOffset + <NUM_LIT> ; } llvm_unreachable ( <STR_LIT> ) ;


<s> return ArgOffset ; case GRID_OFFSET : return ArgOffset + <NUM_LIT> ; } llvm_unreachable ( <STR_LIT> ) ;


<s> else if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) FuncName = G -> getGlobal ( ) -> getName ( ) ; DiagnosticInfoUnsupported NoCalls ( Fn , <STR_LIT> + FuncName , CLI . DL . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( NoCalls ) ;

for ( unsigned I = <NUM_LIT> , E = CLI . Ins . size ( ) ; I != E ; ++ I ) InVals . push_back ( DAG . getUNDEF ( CLI . Ins [ I ] . VT ) ) ;


<s> SelectionDAG & DAG = CLI . DAG ; const Function & Fn = * DAG . getMachineFunction ( ) . getFunction ( ) ; StringRef FuncName ( <STR_LIT> ) ; if ( const ExternalSymbolSDNode * G = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) FuncName = G -> getSymbol ( ) ; else if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) FuncName = G -> getGlobal ( ) -> getName ( ) ; DiagnosticInfoUnsupported NoCalls ( Fn , <STR_LIT> + FuncName , CLI . DL . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( NoCalls ) ;


<s> SmallVector < SDValue , <NUM_LIT> > Args ;

for ( const SDUse & U : Op -> ops ( ) ) DAG . ExtractVectorElements ( U . get ( ) , Args ) ;


<s> for ( const SDUse & U : Op -> ops ( ) ) DAG . ExtractVectorElements ( U . get ( ) , Args ) ;

return DAG . getBuildVector ( Op . getValueType ( ) , SDLoc ( Op ) , Args ) ;


<s> EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) ; SDValue Hi0 = DAG . getSetCC ( SL , SetCCVT , Hi , Zero , <STR_LIT> ) ; SDValue CtlzLo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo ) ; SDValue CtlzHi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi ) ; const SDValue Bits32 = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , CtlzLo , Bits32 ) ; SDValue NewCtlz = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi0 , Add , CtlzHi ) ; if ( ! ZeroUndef ) { SDValue Lo0 = DAG . getSetCC ( SL , SetCCVT , Lo , Zero , <STR_LIT> ) ;

SDValue SrcIsZero = DAG . getNode ( <STR_LIT> , SL , SetCCVT , Lo0 , Hi0 ) ;


<s> SDValue jq = DAG . getConstant ( <NUM_LIT> , DL , IntVT ) ; if ( Sign ) { jq = DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS ) ; jq = DAG . getNode ( <STR_LIT> , DL , VT , jq , DAG . getConstant ( BitSize - <NUM_LIT> , DL , VT ) ) ; jq = DAG . getNode ( <STR_LIT> , DL , VT , jq , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; } SDValue ia = LHS ; SDValue ib = RHS ; SDValue fa = DAG . getNode ( ToFp , DL , FltVT , ia ) ; SDValue fb = DAG . getNode ( ToFp , DL , FltVT , ib ) ; SDValue fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fa , DAG . getNode ( <STR_LIT> , DL , FltVT , fb ) ) ; fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ; SDValue fqneg = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ; SDValue fr = DAG . getNode ( <STR_LIT> , DL , FltVT , fqneg , fb , fa ) ; SDValue iq = DAG . getNode ( ToInt , DL , IntVT , fq ) ; fr = DAG . getNode ( <STR_LIT> , DL , FltVT , fr ) ;

fb = DAG . getNode ( <STR_LIT> , DL , FltVT , fb ) ;


<s> fb = DAG . getNode ( <STR_LIT> , DL , FltVT , fb ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue cv = DAG . getSetCC ( DL , SetCCVT , fr , fb , <STR_LIT> ) ; jq = DAG . getNode ( <STR_LIT> , DL , VT , cv , jq , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Div = DAG . getNode ( <STR_LIT> , DL , VT , iq , jq ) ; SDValue Rem = DAG . getNode ( <STR_LIT> , DL , VT , Div , RHS ) ; Rem = DAG . getNode ( <STR_LIT> , DL , VT , LHS , Rem ) ; if ( Sign ) { SDValue InRegSize = DAG . getValueType ( EVT :: getIntegerVT ( * DAG . getContext ( ) , DivBits ) ) ; Div = DAG . getNode ( <STR_LIT> , DL , VT , Div , InRegSize ) ; Rem = DAG . getNode ( <STR_LIT> , DL , VT , Rem , InRegSize ) ; } else { SDValue TruncMask = DAG . getConstant ( ( UINT64_C ( <NUM_LIT> ) << DivBits ) - <NUM_LIT> , DL , VT ) ; Div = DAG . getNode ( <STR_LIT> , DL , VT , Div , TruncMask ) ;

Rem = DAG . getNode ( <STR_LIT> , DL , VT , Rem , TruncMask ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerDYNAMIC_STACKALLOC ( SDValue Op , SelectionDAG & DAG ) const { const Function & Fn = * DAG . getMachineFunction ( ) . getFunction ( ) ; DiagnosticInfoUnsupported NoDynamicAlloca ( Fn , <STR_LIT> , SDLoc ( Op ) . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( NoDynamicAlloca ) ; auto Ops = { DAG . getConstant ( <NUM_LIT> , SDLoc ( ) , Op . getValueType ( ) ) , Op . getOperand ( <NUM_LIT> ) } ; return DAG . getMergeValues ( Ops , SDLoc ( ) ) ;


<s> return DAG . getConstant ( Offset , SDLoc ( Op ) , Op . getValueType ( ) ) ; } } const Function & Fn = * DAG . getMachineFunction ( ) . getFunction ( ) ; DiagnosticInfoUnsupported BadInit ( Fn , <STR_LIT> , SDLoc ( Op ) . getDebugLoc ( ) ) ;

DAG . getContext ( ) -> diagnose ( BadInit ) ;


<s> switch ( IntrinsicID ) { default : return Op ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { default : Op -> dump ( & DAG ) ; llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; break ; case <STR_LIT> : return Lower<ISA_LIT>GN_EXTEND_INREG ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerFREM ( Op , DAG ) ; case <STR_LIT> : return LowerFCEIL ( Op , DAG ) ; case <STR_LIT> : return LowerFTRUNC ( Op , DAG ) ; case <STR_LIT> : return LowerFRINT ( Op , DAG ) ; case <STR_LIT> : return LowerFNEARBYINT ( Op , DAG ) ; case <STR_LIT> : return LowerFROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFFLOOR ( Op , DAG ) ; case <STR_LIT> : return Lower<ISA_LIT>NT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_<ISA_LIT>NT ( Op , DAG ) ;

case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ;


<s> assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; EVT DestVT = Op . getValueType ( ) ; if ( DestVT == <STR_LIT> ) return LowerINT_TO_FP32 ( Op , DAG , true ) ; assert ( DestVT == <STR_LIT> ) ; return LowerINT_TO_FP64 ( Op , DAG , true ) ;


<s> assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; EVT DestVT = Op . getValueType ( ) ; if ( DestVT == <STR_LIT> ) return LowerINT_TO_FP32 ( Op , DAG , true ) ;


<s> for ( unsigned i = <NUM_LIT> ; i < halfBitWidth ; ++ i ) { const unsigned bitPos = halfBitWidth - i - <NUM_LIT> ; SDValue POS = DAG . getConstant ( bitPos , DL , HalfVT ) ; SDValue HBit = DAG . getNode ( <STR_LIT> , DL , HalfVT , LHS_Lo , POS ) ; HBit = DAG . getNode ( <STR_LIT> , DL , HalfVT , HBit , one ) ; HBit = DAG . getNode ( <STR_LIT> , DL , VT , HBit ) ; REM = DAG . getNode ( <STR_LIT> , DL , VT , REM , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; REM = DAG . getNode ( <STR_LIT> , DL , VT , REM , HBit ) ; SDValue BIT = DAG . getConstant ( <NUM_LIT> << bitPos , DL , HalfVT ) ; SDValue realBIT = DAG . getSelectCC ( DL , REM , RHS , BIT , zero , <STR_LIT> ) ; DIV_Lo = DAG . getNode ( <STR_LIT> , DL , HalfVT , DIV_Lo , realBIT ) ; SDValue REM_sub = DAG . getNode ( <STR_LIT> , DL , VT , REM , RHS ) ; REM = DAG . getSelectCC ( DL , REM , RHS , REM_sub , REM , <STR_LIT> ) ; } SDValue DIV = DAG . getBuildVector ( <STR_LIT> , DL , { DIV_Lo , DIV_Hi } ) ;

DIV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DIV ) ;


<s> assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerUINT_TO_FP ( SDValue Op , SelectionDAG & DAG ) const {

assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ;


<s> SDLoc DL ( Op ) ; SDValue Value = Store -> getValue ( ) ; EVT VT = Value . getValueType ( ) ; EVT ElemVT = VT . getVectorElementType ( ) ; SDValue Ptr = Store -> getBasePtr ( ) ; EVT MemEltVT = MemVT . getVectorElementType ( ) ; unsigned MemEltBits = MemEltVT . getSizeInBits ( ) ; unsigned MemNumElements = MemVT . getVectorNumElements ( ) ; unsigned PackedSize = MemVT . getStoreSizeInBits ( ) ; SDValue Mask = DAG . getConstant ( ( <NUM_LIT> << MemEltBits ) - <NUM_LIT> , DL , <STR_LIT> ) ; assert ( Value . getValueType ( ) . getScalarSizeInBits ( ) >= <NUM_LIT> ) ; SDValue PackedValue ; for ( unsigned i = <NUM_LIT> ; i < MemNumElements ; ++ i ) { SDValue Elt = DAG . getNode ( <STR_LIT> , DL , ElemVT , Value , DAG . getConstant ( i , DL , <STR_LIT> ) ) ; Elt = DAG . getZExtOrTrunc ( Elt , DL , <STR_LIT> ) ; Elt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Elt , Mask ) ; SDValue Shift = DAG . getConstant ( MemEltBits * i , DL , <STR_LIT> ) ; Elt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Elt , Shift ) ; if ( i == <NUM_LIT> ) { PackedValue = Elt ; } else { PackedValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , PackedValue , Elt ) ; } } if ( PackedSize < <NUM_LIT> ) { EVT PackedVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , PackedSize ) ; return DAG . getTruncStore ( Store -> getChain ( ) , DL , PackedValue , Ptr , Store -> getMemOperand ( ) -> getPointerInfo ( ) , PackedVT , Store -> getAlignment ( ) , Store -> getMemOperand ( ) -> getFlags ( ) ) ; } return DAG . getStore ( Store -> getChain ( ) , DL , PackedValue , Ptr , Store -> getMemOperand ( ) -> getPointerInfo ( ) , Store -> getAlignment ( ) , Store -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> SDLoc SL ( N ) ; SelectionDAG & DAG = DCI . DAG ; SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = split64BitValue ( N -> getOperand ( <NUM_LIT> ) , DAG ) ; SDValue LoRHS = DAG . getConstant ( Lo_32 ( Val ) , SL , <STR_LIT> ) ; SDValue HiRHS = DAG . getConstant ( Hi_32 ( Val ) , SL , <STR_LIT> ) ;

SDValue LoAnd = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo , LoRHS ) ;


<s> SDValue <ISA_LIT>TargetLowering :: performCtlzCombine ( const SDLoc & SL , SDValue Cond , SDValue LHS , SDValue RHS , DAGCombinerInfo & DCI ) const { ConstantSDNode * CmpRhs = dyn_cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ; if ( ! CmpRhs || ! CmpRhs -> isNullValue ( ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue CmpLHS = Cond . getOperand ( <NUM_LIT> ) ; if ( CCOpcode == <STR_LIT> && isCtlzOpc ( RHS . getOpcode ( ) ) && RHS . getOperand ( <NUM_LIT> ) == CmpLHS && isNegativeOne ( LHS ) ) { return getFFBH_U32 ( * this , DAG , SL , CmpLHS ) ; }

if ( CCOpcode == <STR_LIT> && isCtlzOpc ( LHS . getOpcode ( ) ) && LHS . getOperand ( <NUM_LIT> ) == CmpLHS && isNegativeOne ( RHS ) ) {


<s> unsigned Size = VT . getStoreSize ( ) ; unsigned Align = LN -> getAlignment ( ) ; if ( Align < Size && isTypeLegal ( VT ) ) { bool IsFast ; unsigned AS = LN -> getAddressSpace ( ) ; if ( ! allowsMisalignedMemoryAccesses ( VT , AS , Align , & IsFast ) ) { SDValue Ops [ <NUM_LIT> ] ; std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = expandUnalignedLoad ( LN , DAG ) ; return DAG . getMergeValues ( Ops , SDLoc ( N ) ) ; } if ( ! IsFast ) return SDValue ( ) ; } if ( ! shouldCombineMemoryType ( VT ) ) return SDValue ( ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue NewLoad = DAG . getLoad ( NewVT , SL , LN -> getChain ( ) , LN -> getBasePtr ( ) , LN -> getMemOperand ( ) ) ; SDValue BC = DAG . getNode ( <STR_LIT> , SL , VT , NewLoad ) ;

DCI . CombineTo ( N , BC , NewLoad . getValue ( <NUM_LIT> ) ) ;


<s> if ( ! DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; LoadSDNode * LN = cast < LoadSDNode > ( N ) ; if ( LN -> isVolatile ( ) || ! <STR_LIT> ( LN ) || hasVolatileUser ( LN ) ) return SDValue ( ) ; SDLoc SL ( N ) ; SelectionDAG & DAG = DCI . DAG ; EVT VT = LN -> getMemoryVT ( ) ; unsigned Size = VT . getStoreSize ( ) ; unsigned Align = LN -> getAlignment ( ) ;

if ( Align < Size && isTypeLegal ( VT ) ) {


<s> SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; if ( Cond . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue LHS = Cond . getOperand ( <NUM_LIT> ) ; SDValue RHS = Cond . getOperand ( <NUM_LIT> ) ; SDValue CC = Cond . getOperand ( <NUM_LIT> ) ; SDValue True = N -> getOperand ( <NUM_LIT> ) ; SDValue False = N -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && Cond . hasOneUse ( ) ) { SDValue MinMax = CombineFMinMaxLegacy ( SDLoc ( N ) , VT , LHS , RHS , True , False , CC , DCI ) ; return MinMax ;


<s> SDValue RHS = Cond . getOperand ( <NUM_LIT> ) ; SDValue CC = Cond . getOperand ( <NUM_LIT> ) ; SDValue True = N -> getOperand ( <NUM_LIT> ) ; SDValue False = N -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && Cond . hasOneUse ( ) ) { SDValue MinMax = CombineFMinMaxLegacy ( SDLoc ( N ) , VT , LHS , RHS , True , False , CC , DCI ) ; return MinMax ; }

return performCtlzCombine ( SDLoc ( N ) , Cond , True , False , DCI ) ;


<s> SelectionDAG & DAG = DCI . DAG ; SDValue ShiftAmt = DAG . getConstant ( RHSVal - <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LHS ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo , ShiftAmt ) ; const SDValue Zero = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Vec = DAG . getBuildVector ( <STR_LIT> , SL , { Zero , NewShift } ) ;

return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Vec ) ;


<s> if ( ! allowsMisalignedMemoryAccesses ( VT , AS , Align , & IsFast ) ) return expandUnalignedStore ( SN , DAG ) ; if ( ! IsFast ) return SDValue ( ) ; } if ( ! shouldCombineMemoryType ( VT ) ) return SDValue ( ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue Val = SN -> getValue ( ) ; bool OtherUses = ! Val . hasOneUse ( ) ; SDValue CastVal = DAG . getNode ( <STR_LIT> , SL , NewVT , Val ) ; if ( OtherUses ) { SDValue CastBack = DAG . getNode ( <STR_LIT> , SL , VT , CastVal ) ;

DAG . ReplaceAllUsesOfValueWith ( Val , CastBack ) ;


<s> std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Op , SL , LoVT , HiVT ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned BaseAlign = Load -> getAlignment ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , LoVT , Load -> getChain ( ) , BasePtr , SrcValue , LoMemVT , BaseAlign , Load -> getMemOperand ( ) -> getFlags ( ) ) ;

SDValue HiPtr = DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( Size , SL , PtrVT ) ) ;


<s> EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Val , SL , LoVT , HiVT ) ; EVT PtrVT = BasePtr . getValueType ( ) ; SDValue HiPtr = DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( LoMemVT . getStoreSize ( ) , SL , PtrVT ) ) ; const MachinePointerInfo & SrcValue = Store -> getMemOperand ( ) -> getPointerInfo ( ) ; unsigned BaseAlign = Store -> getAlignment ( ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoStore = DAG . getTruncStore ( Chain , SL , Lo , BasePtr , SrcValue , LoMemVT , BaseAlign , Store -> getMemOperand ( ) -> getFlags ( ) ) ;

SDValue HiStore = DAG . getTruncStore ( Chain , SL , Hi , HiPtr , SrcValue . getWithOffset ( Size ) , HiMemVT , HiAlign , Store -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> uint64_t Offset = MFI -> allocateKernArg ( LocVT . getStoreSize ( ) , ArgFlags . getOrigAlign ( ) ) ; State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ;


<s> <ISA_LIT>MachineFunction * MFI = MF . getInfo < <ISA_LIT>MachineFunction > ( ) ; uint64_t Offset = MFI -> allocateKernArg ( LocVT . getStoreSize ( ) , ArgFlags . getOrigAlign ( ) ) ; State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { return allocateCCRegs ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State , & <STR_LIT> , <NUM_LIT> ) ;


<s> unsigned NumMayIncreaseSize = <NUM_LIT> ; MVT VT = N -> getValueType ( <NUM_LIT> ) . getScalarType ( ) . getSimpleVT ( ) ;

for ( const SDNode * U : N -> uses ( ) ) {


<s> } else { unsigned MemoryBits = In . ArgVT . getStoreSizeInBits ( ) / NumRegs ; assert ( In . ArgVT . getStoreSizeInBits ( ) % NumRegs == <NUM_LIT> ) ; if ( In . VT . isInteger ( ) ) { MemVT = EVT :: getIntegerVT ( State . getContext ( ) , MemoryBits ) ; } else if ( In . VT . isVector ( ) ) { assert ( ! In . VT . getScalarType ( ) . isFloatingPoint ( ) ) ; unsigned NumElements = In . VT . getVectorNumElements ( ) ; assert ( MemoryBits % NumElements == <NUM_LIT> ) ; EVT ScalarVT = EVT :: getIntegerVT ( State . getContext ( ) , MemoryBits / NumElements ) ; MemVT = EVT :: getVectorVT ( State . getContext ( ) , ScalarVT , NumElements ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } } if ( MemVT . isVector ( ) && MemVT . getVectorNumElements ( ) == <NUM_LIT> ) MemVT = MemVT . getScalarType ( ) ; if ( MemVT . isExtended ( ) ) {

assert ( MemVT . isVector ( ) && MemVT . getVectorNumElements ( ) == <NUM_LIT> ) ;


<s> CCAssignFn * <ISA_LIT>CallLowering :: CCAssignFnForCall ( CallingConv :: ID CC , bool IsVarArg ) const {


<s> unsigned BitWidth = KnownZero . getBitWidth ( ) ; KnownZero = KnownOne = APInt ( BitWidth , <NUM_LIT> ) ; APInt KnownZero2 ; APInt KnownOne2 ; unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : { KnownZero = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : { ConstantSDNode * CWidth = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! CWidth ) return ; uint32_t Width = CWidth -> getZExtValue ( ) & <NUM_LIT> ; if ( Opc == <STR_LIT> ) KnownZero = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> - Width ) ; break ;


<s> EVT VT = Op . getValueType ( ) ; EVT LegalVT = getTypeToTransformTo ( * DAG . getContext ( ) , VT ) ; if ( LegalVT != <STR_LIT> && ( Subtarget -> has16BitInsts ( ) && LegalVT != <STR_LIT> ) ) return SDValue ( ) ; if ( VT != <STR_LIT> ) Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ; SDValue FFBH = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ; if ( VT != <STR_LIT> ) FFBH = DAG . getNode ( <STR_LIT> , DL , VT , FFBH ) ; return FFBH ;


<s> if ( LegalVT != <STR_LIT> && ( Subtarget -> has16BitInsts ( ) && LegalVT != <STR_LIT> ) ) return SDValue ( ) ; if ( VT != <STR_LIT> ) Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ; SDValue FFBH = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ; if ( VT != <STR_LIT> ) FFBH = DAG . getNode ( <STR_LIT> , DL , VT , FFBH ) ;


<s> unsigned Alignment = Subtarget -> getAlignmentForImplicitArgPtr ( ) ; uint64_t ArgOffset = alignTo ( MFI -> getABIArgOffset ( ) , Alignment ) ; switch ( Param ) { case GRID_DIM : return ArgOffset ;


<s> if ( isa < MemSDNode > ( N ) ) return false ; switch ( N -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> return DAG . getConstant ( Offset , SDLoc ( Op ) , Op . getValueType ( ) ) ; } } const Function & Fn = * DAG . getMachineFunction ( ) . getFunction ( ) ;

DiagnosticInfoUnsupported BadInit ( Fn , <STR_LIT> , SDLoc ( Op ) . getDebugLoc ( ) ) ;


<s> assert ( G -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ! hasDefinedInitializer ( GV ) ) { unsigned Offset = MFI -> allocateLDSGlobal ( DL , * GV ) ; return DAG . getConstant ( Offset , SDLoc ( Op ) , Op . getValueType ( ) ) ; } } const Function & Fn = * DAG . getMachineFunction ( ) . getFunction ( ) ; DiagnosticInfoUnsupported BadInit ( Fn , <STR_LIT> , SDLoc ( Op ) . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( BadInit ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { default : Op -> print ( errs ( ) , & DAG ) ; llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; break ; case <STR_LIT> : return Lower<ISA_LIT>GN_EXTEND_INREG ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerFREM ( Op , DAG ) ; case <STR_LIT> : return LowerFCEIL ( Op , DAG ) ; case <STR_LIT> : return LowerFTRUNC ( Op , DAG ) ; case <STR_LIT> : return LowerFRINT ( Op , DAG ) ; case <STR_LIT> : return LowerFNEARBYINT ( Op , DAG ) ; case <STR_LIT> : return LowerFROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFFLOOR ( Op , DAG ) ; case <STR_LIT> : return Lower<ISA_LIT>NT_TO_FP ( Op , DAG ) ;

case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ;


<s> ConstantFPSDNode * CSrc = dyn_cast < ConstantFPSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! CSrc ) return SDValue ( ) ; const APFloat & F = CSrc -> getValueAPF ( ) ; APFloat Zero = APFloat :: getZero ( F . getSemantics ( ) ) ; APFloat :: cmpResult Cmp0 = F . compare ( Zero ) ; if ( Cmp0 == APFloat :: cmpLessThan || ( Cmp0 == APFloat :: cmpUnordered && Subtarget -> enableDX10Clamp ( ) ) ) { return DCI . DAG . getConstantFP ( Zero , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ;


<s> SDValue CmpLHS = Cond . getOperand ( <NUM_LIT> ) ; if ( CCOpcode == <STR_LIT> && isCtlzOpc ( RHS . getOpcode ( ) ) && RHS . getOperand ( <NUM_LIT> ) == CmpLHS && isNegativeOne ( LHS ) ) { return getFFBH_U32 ( DAG , CmpLHS , SL ) ; }


<s> Mul = getMul24 ( DAG , DL , N0 , N1 , Size , false ) ; } else if ( Subtarget -> hasMulI24 ( ) && isI24 ( N0 , DAG ) && isI24 ( N1 , DAG ) ) { N0 = DAG . getSExtOrTrunc ( N0 , DL , <STR_LIT> ) ; N1 = DAG . getSExtOrTrunc ( N1 , DL , <STR_LIT> ) ; Mul = getMul24 ( DAG , DL , N0 , N1 , Size , true ) ; } else { return SDValue ( ) ;


<s> SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Mul ; if ( Subtarget -> hasMulU24 ( ) && isU24 ( N0 , DAG ) && isU24 ( N1 , DAG ) ) { N0 = DAG . getZExtOrTrunc ( N0 , DL , <STR_LIT> ) ; N1 = DAG . getZExtOrTrunc ( N1 , DL , <STR_LIT> ) ; Mul = getMul24 ( DAG , DL , N0 , N1 , Size , false ) ; } else if ( Subtarget -> hasMulI24 ( ) && isI24 ( N0 , DAG ) && isI24 ( N1 , DAG ) ) { N0 = DAG . getSExtOrTrunc ( N0 , DL , <STR_LIT> ) ; N1 = DAG . getSExtOrTrunc ( N1 , DL , <STR_LIT> ) ; Mul = getMul24 ( DAG , DL , N0 , N1 , Size , true ) ; } else { return SDValue ( ) ;


<s> SDLoc SL ( N ) ; <STR_LIT> NewCC = getSetCCInverse ( cast < CondCodeSDNode > ( CC ) -> get ( ) , LHS . getValueType ( ) . isInteger ( ) ) ; SDValue NewCond = DAG . getSetCC ( SL , Cond . getValueType ( ) , LHS , RHS , NewCC ) ; return DAG . getNode ( <STR_LIT> , SL , VT , NewCond , False , True ) ; } if ( VT == <STR_LIT> && Subtarget -> hasFminFmaxLegacy ( ) ) { SDValue MinMax = combineFMinMaxLegacy ( SDLoc ( N ) , VT , LHS , RHS , True , False , CC , DCI ) ; return MinMax ; } } return performCtlzCombine ( SDLoc ( N ) , Cond , True , False , DCI ) ;


<s> static bool simplifyI24 ( SDNode * Node24 , unsigned OpIdx , TargetLowering :: DAGCombinerInfo & DCI ) { SelectionDAG & DAG = DCI . DAG ; SDValue Op = Node24 -> getOperand ( OpIdx ) ;


<s> uint64_t ArgOffset = alignTo ( MFI -> getExplicitKernArgSize ( ) , Alignment ) + ExplicitArgOffset ; switch ( Param ) { case GRID_DIM : return ArgOffset ; case GRID_OFFSET :


<s> case <STR_LIT> : case <STR_LIT> : { KnownBits LHSKnown = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; KnownBits RHSKnown = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned TrailZ = LHSKnown . countMinTrailingZeros ( ) + RHSKnown . countMinTrailingZeros ( ) ; Known . Zero . setLowBits ( std :: min ( TrailZ , <NUM_LIT> ) ) ; unsigned LHSValBits = <NUM_LIT> - std :: max ( LHSKnown . countMinSignBits ( ) , <NUM_LIT> ) ; unsigned RHSValBits = <NUM_LIT> - std :: max ( RHSKnown . countMinSignBits ( ) , <NUM_LIT> ) ; unsigned MaxValBits = std :: min ( LHSValBits + RHSValBits , <NUM_LIT> ) ; if ( MaxValBits >= <NUM_LIT> ) break ; bool Negative = false ; if ( Opc == <STR_LIT> ) { bool LHSNegative = ! ! ( LHSKnown . One & ( <NUM_LIT> << <NUM_LIT> ) ) ; bool LHSPositive = ! ! ( LHSKnown . Zero & ( <NUM_LIT> << <NUM_LIT> ) ) ; bool RHSNegative = ! ! ( RHSKnown . One & ( <NUM_LIT> << <NUM_LIT> ) ) ; bool RHSPositive = ! ! ( RHSKnown . Zero & ( <NUM_LIT> << <NUM_LIT> ) ) ; if ( ( ! LHSNegative && ! LHSPositive ) || ( ! RHSNegative && ! RHSPositive ) ) break ; Negative = ( LHSNegative && RHSPositive ) || ( LHSPositive && RHSNegative ) ; } if ( Negative ) Known . One . setHighBits ( <NUM_LIT> - MaxValBits ) ; else Known . Zero . setHighBits ( <NUM_LIT> - MaxValBits ) ; break ; } case <STR_LIT> : { ConstantSDNode * CMask = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! CMask ) return ; KnownBits LHSKnown = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; KnownBits RHSKnown = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned Sel = CMask -> getZExtValue ( ) ; for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; I += <NUM_LIT> ) { unsigned SelBits = Sel & <NUM_LIT> ; if ( SelBits < <NUM_LIT> ) {


<s> SDValue LHS = N0 . getOperand ( <NUM_LIT> ) ; SDValue RHS = N0 . getOperand ( <NUM_LIT> ) ; if ( isConstantCostlierToNegate ( RHS ) ) return SDValue ( ) ; SDValue NegLHS = DAG . getNode ( <STR_LIT> , SL , VT , LHS ) ; SDValue NegRHS = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; unsigned Opposite = inverseMinMax ( Opc ) ; SDValue Res = DAG . getNode ( Opposite , SL , VT , NegLHS , NegRHS , N0 -> getFlags ( ) ) ; if ( ! N0 . hasOneUse ( ) ) DAG . ReplaceAllUsesWith ( N0 , DAG . getNode ( <STR_LIT> , SL , VT , Res ) ) ; return Res ; } case <STR_LIT> : { SDValue Ops [ <NUM_LIT> ] ; for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) Ops [ I ] = DAG . getNode ( <STR_LIT> , SL , VT , N0 -> getOperand ( I ) , N0 -> getFlags ( ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , SL , VT , Ops , N0 -> getFlags ( ) ) ; if ( ! N0 . hasOneUse ( ) ) DAG . ReplaceAllUsesWith ( N0 , DAG . getNode ( <STR_LIT> , SL , VT , Res ) ) ; return Res ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue CvtSrc = N0 . getOperand ( <NUM_LIT> ) ; if ( CvtSrc . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( Opc , SL , VT , CvtSrc . getOperand ( <NUM_LIT> ) ) ; } if ( ! N0 . hasOneUse ( ) ) return SDValue ( ) ; SDValue Neg = DAG . getNode ( <STR_LIT> , SL , CvtSrc . getValueType ( ) , CvtSrc ) ; return DAG . getNode ( Opc , SL , VT , Neg , N0 -> getFlags ( ) ) ; } case <STR_LIT> : { SDValue CvtSrc = N0 . getOperand ( <NUM_LIT> ) ; if ( CvtSrc . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , SL , VT , CvtSrc . getOperand ( <NUM_LIT> ) , N0 . getOperand ( <NUM_LIT> ) ) ; } if ( ! N0 . hasOneUse ( ) ) return SDValue ( ) ; SDValue Neg = DAG . getNode ( <STR_LIT> , SL , CvtSrc . getValueType ( ) , CvtSrc ) ; return DAG . getNode ( <STR_LIT> , SL , VT , Neg , N0 . getOperand ( <NUM_LIT> ) ) ; }


<s> unsigned Size = VT . getScalarSizeInBits ( ) ; if ( ( Known . isConstant ( ) && Known . getConstant ( ) . ule ( Size ) ) || ( Known . getBitWidth ( ) - Known . countMinLeadingZeros ( ) <= Log2_32 ( Size ) ) ) { EVT MidVT = VT . isVector ( ) ? EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) : <STR_LIT> ; EVT NewShiftVT = getShiftAmountTy ( MidVT , DAG . getDataLayout ( ) ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , SL , MidVT , Src . getOperand ( <NUM_LIT> ) ) ; DCI . AddToWorklist ( Trunc . getNode ( ) ) ; if ( Amt . getValueType ( ) != NewShiftVT ) { Amt = DAG . getZExtOrTrunc ( Amt , SL , NewShiftVT ) ; DCI . AddToWorklist ( Amt . getNode ( ) ) ; } SDValue ShrunkShift = DAG . getNode ( Src . getOpcode ( ) , SL , MidVT , Trunc , Amt ) ; return DAG . getNode ( <STR_LIT> , SL , VT , ShrunkShift ) ; } } }


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * RMW ) const { if ( RMW -> getOperation ( ) == AtomicRMWInst :: Nand ) return AtomicExpansionKind :: CmpXChg ;


<s> return DAG . getConstantFP ( <NUM_LIT> , SL , VT ) ; case <STR_LIT> : return DAG . getConstantFP ( APFloat ( APFloat :: IEEEhalf ( ) , <STR_LIT> ) , SL , VT ) ; case <STR_LIT> : return DAG . getConstantFP ( APFloat ( APFloat :: IEEEdouble ( ) , <STR_LIT> ) , SL , VT ) ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> case <STR_LIT> : return DAG . getConstantFP ( <NUM_LIT> , SL , VT ) ; case <STR_LIT> : return DAG . getConstantFP ( APFloat ( APFloat :: IEEEhalf ( ) , <STR_LIT> ) , SL , VT ) ; case <STR_LIT> : return DAG . getConstantFP ( APFloat ( APFloat :: IEEEdouble ( ) , <STR_LIT> ) , SL , VT ) ;


<s> unsigned IntrID = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntrID ) { default : return false ; case <STR_LIT> : case <STR_LIT> : return true ; } } break ; case <STR_LIT> : {

const LoadSDNode * L = dyn_cast < LoadSDNode > ( N ) ;


<s> SDValue Mul = DAG . getNode ( <STR_LIT> , SL , VT , Src , K , Op -> getFlags ( ) ) ;

return DAG . getNode ( <STR_LIT> , SL , VT , Mul , Op -> getFlags ( ) ) ;


<s> case <STR_LIT> : return Lower<ISA_LIT>GN_EXTEND_INREG ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerFREM ( Op , DAG ) ; case <STR_LIT> : return LowerFCEIL ( Op , DAG ) ; case <STR_LIT> : return LowerFTRUNC ( Op , DAG ) ; case <STR_LIT> : return LowerFRINT ( Op , DAG ) ; case <STR_LIT> : return LowerFNEARBYINT ( Op , DAG ) ; case <STR_LIT> : return LowerFROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFFLOOR ( Op , DAG ) ; case <STR_LIT> : return LowerFLOG ( Op , DAG , <NUM_LIT> / <ISA_LIT>_LOG2E_F ) ; case <STR_LIT> : return LowerFLOG ( Op , DAG , <ISA_LIT>_LN2_F / <ISA_LIT>_LN10_F ) ; case <STR_LIT> : return lowerFEXP ( Op , DAG ) ; case <STR_LIT> : return Lower<ISA_LIT>NT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_FP16 ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_<ISA_LIT>NT ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ; case <STR_LIT> :


<s> bool mergeStoresAfterLegalization ( EVT ) const override {


<s> uint64_t CVal = Val . getZExtValue ( ) ; SDValue Vec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DAG . getConstant ( Lo_32 ( CVal ) , SL , <STR_LIT> ) , DAG . getConstant ( Hi_32 ( CVal ) , SL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SL , DestVT , Vec ) ; } break ; } case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) break ; return performShlCombine ( N , DCI ) ; } case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) break ; return performSrlCombine ( N , DCI ) ; } case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) break ; return performSraCombine ( N , DCI ) ; } case <STR_LIT> : return performTruncateCombine ( N , DCI ) ; case <STR_LIT> : return performMulCombine ( N , DCI ) ; case <STR_LIT> : return performMulhsCombine ( N , DCI ) ; case <STR_LIT> : return performMulhuCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( SDValue V = simplifyI24 ( N , DCI ) ) return V ; return SDValue ( ) ; } case <STR_LIT> : case <STR_LIT> : return performMulLoHi24Combine ( N , DCI ) ; case <STR_LIT> : return performSelectCombine ( N , DCI ) ; case <STR_LIT> : return performFNegCombine ( N , DCI ) ; case <STR_LIT> : return performFAbsCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : { assert ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) && <STR_LIT> ) ; ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) break ; uint32_t WidthVal = Width -> getZExtValue ( ) & <NUM_LIT> ; if ( WidthVal == <NUM_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; SDValue BitsFrom = N -> getOperand ( <NUM_LIT> ) ; uint32_t OffsetVal = Offset -> getZExtValue ( ) & <NUM_LIT> ; bool Signed = N -> getOpcode ( ) == <STR_LIT> ; if ( OffsetVal == <NUM_LIT> ) {

unsigned SignBits = Signed ? ( <NUM_LIT> - WidthVal + <NUM_LIT> ) : ( <NUM_LIT> - WidthVal ) ;


<s> static SDValue simplifyI24 ( SDNode * Node24 , TargetLowering :: DAGCombinerInfo & DCI ) { SelectionDAG & DAG = DCI . DAG ; SDValue LHS = Node24 -> getOperand ( <NUM_LIT> ) ; SDValue RHS = Node24 -> getOperand ( <NUM_LIT> ) ;

APInt Demanded = APInt :: getLowBitsSet ( LHS . getValueSizeInBits ( ) , <NUM_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: isConstantUnsignedBitfieldExtactLegal ( unsigned Opc , LLT Ty1 , LLT Ty2 ) const { return Ty1 == Ty2 && ( Ty1 == LLT :: scalar ( <NUM_LIT> ) || Ty1 == LLT :: scalar ( <NUM_LIT> ) ) ;


<s> EVT VT = Op . getValueType ( ) ; EVT SrcVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ;

if ( ( ( SrcVT == <STR_LIT> && VT == <STR_LIT> ) || ( SrcVT == <STR_LIT> && VT == <STR_LIT> ) ) && Start != <NUM_LIT> ) return Op ;


<s> SmallVector < SDValue , <NUM_LIT> > CastedElts ; SDLoc SL ( N ) ; for ( unsigned I = <NUM_LIT> , E = SrcVT . getVectorNumElements ( ) ; I != E ; ++ I ) { SDValue Elt = Src . getOperand ( I ) ; CastedElts . push_back ( DAG . getNode ( <STR_LIT> , DL , DestEltVT , Elt ) ) ; } return DAG . getBuildVector ( DestVT , SL , CastedElts ) ; } } } if ( DestVT . getSizeInBits ( ) != <NUM_LIT> || ! DestVT . isVector ( ) ) break ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Src ) ) { SDLoc SL ( N ) ; uint64_t CVal = C -> getZExtValue ( ) ; SDValue BV = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DAG . getConstant ( Lo_32 ( CVal ) , SL , <STR_LIT> ) , DAG . getConstant ( Hi_32 ( CVal ) , SL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SL , DestVT , BV ) ; } if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( Src ) ) { const APInt & Val = C -> getValueAPF ( ) . bitcastToAPInt ( ) ; SDLoc SL ( N ) ; uint64_t CVal = Val . getZExtValue ( ) ; SDValue Vec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DAG . getConstant ( Lo_32 ( CVal ) , SL , <STR_LIT> ) , DAG . getConstant ( Hi_32 ( CVal ) , SL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SL , DestVT , Vec ) ; } break ; } case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) break ; return performShlCombine ( N , DCI ) ; } case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) break ; return performSrlCombine ( N , DCI ) ; } case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) break ; return performSraCombine ( N , DCI ) ; } case <STR_LIT> : return performTruncateCombine ( N , DCI ) ; case <STR_LIT> : return performMulCombine ( N , DCI ) ; case <STR_LIT> : return performMulhsCombine ( N , DCI ) ; case <STR_LIT> : return performMulhuCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> unsigned AS = LN -> getAddressSpace ( ) ; if ( ! allowsMisalignedMemoryAccesses ( VT , AS , Alignment , LN -> getMemOperand ( ) -> getFlags ( ) , & IsFast ) ) { SDValue Ops [ <NUM_LIT> ] ; if ( VT . isVector ( ) ) std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = scalarizeVectorLoad ( LN , DAG ) ; else std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = expandUnalignedLoad ( LN , DAG ) ; return DAG . getMergeValues ( Ops , SDLoc ( N ) ) ; }


<s> unsigned ShiftAmt = RHS -> getZExtValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc SL ( N ) ; if ( LHS . getOpcode ( ) == <STR_LIT> ) { if ( auto * Mask = dyn_cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) ) { if ( Mask -> getAPIntValue ( ) . isShiftedMask ( ) && Mask -> getAPIntValue ( ) . countTrailingZeros ( ) == ShiftAmt ) { return DAG . getNode ( <STR_LIT> , SL , VT , DAG . getNode ( <STR_LIT> , SL , VT , LHS . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , SL , VT , LHS . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ) ; } } } if ( VT != <STR_LIT> ) return SDValue ( ) ; if ( ShiftAmt < <NUM_LIT> ) return SDValue ( ) ;

SDValue Zero = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ;


<s> StoreSDNode * SN = cast < StoreSDNode > ( N ) ; if ( ! SN -> isSimple ( ) || ! <STR_LIT> ( SN ) ) return SDValue ( ) ; EVT VT = SN -> getMemoryVT ( ) ; unsigned Size = VT . getStoreSize ( ) ; SDLoc SL ( N ) ; SelectionDAG & DAG = DCI . DAG ; Align Alignment = SN -> getAlign ( ) ; if ( Alignment < Size && isTypeLegal ( VT ) ) { bool IsFast ; unsigned AS = SN -> getAddressSpace ( ) ;

if ( ! allowsMisalignedMemoryAccesses ( VT , AS , Alignment , SN -> getMemOperand ( ) -> getFlags ( ) , & IsFast ) ) {


<s> } if ( ! IsFast ) return SDValue ( ) ; } if ( ! shouldCombineMemoryType ( VT ) ) return SDValue ( ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue Val = SN -> getValue ( ) ; bool OtherUses = ! Val . hasOneUse ( ) ; SDValue CastVal = DAG . getNode ( <STR_LIT> , SL , NewVT , Val ) ; if ( OtherUses ) { SDValue CastBack = DAG . getNode ( <STR_LIT> , SL , VT , CastVal ) ; DAG . ReplaceAllUsesOfValueWith ( Val , CastBack ) ; }

return DAG . getStore ( SN -> getChain ( ) , SL , CastVal , SN -> getBasePtr ( ) , SN -> getMemOperand ( ) ) ;


<s> CCAssignFn * <ISA_LIT>CallLowering :: CCAssignFnForCall ( CallingConv :: ID CC , bool IsVarArg ) { switch ( CC ) { case CallingConv :: <ISA_LIT>_KERNEL :


<s> switch ( CC ) { case CallingConv :: <ISA_LIT>_KERNEL : case CallingConv :: SPIR_KERNEL : return CC_<ISA_LIT>_Kernel ; case CallingConv :: <ISA_LIT>_VS : case CallingConv :: <ISA_LIT>_GS : case CallingConv :: <ISA_LIT>_PS : case CallingConv :: <ISA_LIT>_CS : case CallingConv :: <ISA_LIT>_HS : return RetCC_<ISA_LIT>_Shader ; case CallingConv :: C : case CallingConv :: Fast : return RetCC_<ISA_LIT>_Func ; default :


<s> Known . Zero = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : { ConstantSDNode * CWidth = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! CWidth ) return ; uint32_t Width = CWidth -> getZExtValue ( ) & <NUM_LIT> ; if ( Opc == <STR_LIT> ) Known . Zero = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> - Width ) ; break ; } case <STR_LIT> : case <STR_LIT> : { unsigned BitWidth = Known . getBitWidth ( ) ; Known . Zero = APInt :: getHighBitsSet ( BitWidth , BitWidth - <NUM_LIT> ) ; break ; }


<s> case <STR_LIT> : case <STR_LIT> : { Known . Zero = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : { ConstantSDNode * CWidth = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! CWidth ) return ; uint32_t Width = CWidth -> getZExtValue ( ) & <NUM_LIT> ; if ( Opc == <STR_LIT> ) Known . Zero = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> - Width ) ; break ; } case <STR_LIT> : case <STR_LIT> : { unsigned BitWidth = Known . getBitWidth ( ) ; Known . Zero = APInt :: getHighBitsSet ( BitWidth , BitWidth - <NUM_LIT> ) ; break ; } }


<s> SDValue N0 = Op -> getOperand ( <NUM_LIT> ) ; SDValue N1 = Op -> getOperand ( <NUM_LIT> ) ; EVT VT = N0 . getValueType ( ) ; if ( VT . isInteger ( ) && ! VT . isVector ( ) ) { KnownBits LHSKnown , RHSKnown ; DAG . computeKnownBits ( N0 , LHSKnown ) ; if ( LHSKnown . Zero . getBoolValue ( ) ) { DAG . computeKnownBits ( N1 , RHSKnown ) ; if ( ! ( ~ RHSKnown . Zero & ~ LHSKnown . Zero ) ) return true ; } }


<s> EVT VT = Op . getValueType ( ) ; DAG . computeKnownBits ( Op , Known ) ; return ( VT . getSizeInBits ( ) - Known . countMinLeadingZeros ( ) ) <= <NUM_LIT> ;


<s> static bool isU24 ( SDValue Op , SelectionDAG & DAG ) { KnownBits Known ;


<s> SDLoc SL ( N ) ; uint64_t CVal = C -> getZExtValue ( ) ; return DAG . getNode ( <STR_LIT> , SL , DestVT , DAG . getConstant ( Lo_32 ( CVal ) , SL , <STR_LIT> ) , DAG . getConstant ( Hi_32 ( CVal ) , SL , <STR_LIT> ) ) ; } if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( Src ) ) { const APInt & Val = C -> getValueAPF ( ) . bitcastToAPInt ( ) ; SDLoc SL ( N ) ; uint64_t CVal = Val . getZExtValue ( ) ; SDValue Vec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DAG . getConstant ( Lo_32 ( CVal ) , SL , <STR_LIT> ) , DAG . getConstant ( Hi_32 ( CVal ) , SL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SL , DestVT , Vec ) ; } break ; } case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) break ; return performShlCombine ( N , DCI ) ; } case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) break ; return performSrlCombine ( N , DCI ) ; } case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) break ; return performSraCombine ( N , DCI ) ; } case <STR_LIT> : return performMulCombine ( N , DCI ) ; case <STR_LIT> : return performMulhsCombine ( N , DCI ) ; case <STR_LIT> : return performMulhuCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { simplifyI24 ( N , <NUM_LIT> , DCI ) || simplifyI24 ( N , <NUM_LIT> , DCI ) ; return SDValue ( ) ; } case <STR_LIT> : case <STR_LIT> : return performMulLoHi24Combine ( N , DCI ) ; case <STR_LIT> : return performSelectCombine ( N , DCI ) ; case <STR_LIT> : return performFNegCombine ( N , DCI ) ; case <STR_LIT> : return performFAbsCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : { assert ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) && <STR_LIT> ) ; ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) break ; uint32_t WidthVal = Width -> getZExtValue ( ) & <NUM_LIT> ; if ( WidthVal == <NUM_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ;


<s> DAG . computeKnownBits ( X , Known ) ; unsigned LZ = Known . countMinLeadingZeros ( ) ; if ( LZ < RHSVal ) break ; EVT XVT = X . getValueType ( ) ; SDValue Shl = DAG . getNode ( <STR_LIT> , SL , XVT , X , SDValue ( RHS , <NUM_LIT> ) ) ; return DAG . getZExtOrTrunc ( Shl , SL , VT ) ; } case <STR_LIT> : if ( ! isOrEquivalentToAdd ( DAG , LHS ) ) break ; LLVM_FALLTHROUGH ; case <STR_LIT> : { if ( ConstantSDNode * C2 = dyn_cast < ConstantSDNode > ( LHS -> getOperand ( <NUM_LIT> ) ) ) { SDValue Shl = DAG . getNode ( <STR_LIT> , SL , VT , LHS -> getOperand ( <NUM_LIT> ) , SDValue ( RHS , <NUM_LIT> ) ) ; SDValue C2V = DAG . getConstant ( C2 -> getAPIntValue ( ) << RHSVal , SDLoc ( C2 ) , VT ) ; return DAG . getNode ( LHS -> getOpcode ( ) , SL , VT , Shl , C2V ) ; } break ; } } if ( VT != <STR_LIT> ) return SDValue ( ) ; if ( RHSVal < <NUM_LIT> ) return SDValue ( ) ; SDValue ShiftAmt = DAG . getConstant ( RHSVal - <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LHS ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo , ShiftAmt ) ; const SDValue Zero = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ;

SDValue Vec = DAG . getBuildVector ( <STR_LIT> , SL , { Zero , NewShift } ) ;


<s> EVT XVT = X . getValueType ( ) ; SDValue Shl = DAG . getNode ( <STR_LIT> , SL , XVT , X , SDValue ( RHS , <NUM_LIT> ) ) ; return DAG . getZExtOrTrunc ( Shl , SL , VT ) ; } case <STR_LIT> : if ( ! isOrEquivalentToAdd ( DAG , LHS ) ) break ; LLVM_FALLTHROUGH ; case <STR_LIT> : { if ( ConstantSDNode * C2 = dyn_cast < ConstantSDNode > ( LHS -> getOperand ( <NUM_LIT> ) ) ) { SDValue Shl = DAG . getNode ( <STR_LIT> , SL , VT , LHS -> getOperand ( <NUM_LIT> ) , SDValue ( RHS , <NUM_LIT> ) ) ; SDValue C2V = DAG . getConstant ( C2 -> getAPIntValue ( ) << RHSVal , SDLoc ( C2 ) , VT ) ; return DAG . getNode ( LHS -> getOpcode ( ) , SL , VT , Shl , C2V ) ; } break ; } } if ( VT != <STR_LIT> ) return SDValue ( ) ; if ( RHSVal < <NUM_LIT> ) return SDValue ( ) ; SDValue ShiftAmt = DAG . getConstant ( RHSVal - <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LHS ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo , ShiftAmt ) ; const SDValue Zero = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return false ; } case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SNaN ; case <STR_LIT> : case <STR_LIT> : { return SNaN ; } case <STR_LIT> : { unsigned IntrinsicID = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntrinsicID ) { case <STR_LIT> : return true ; case <STR_LIT> : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ; } case <STR_LIT> : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) && DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return false ; } case <STR_LIT> : case <STR_LIT> : return SNaN ; default : return false ; } } default : return false ;


<s> EVT VT = Op . getValueType ( ) ; assert ( VT . getVectorNumElements ( ) == <NUM_LIT> ) ; SDValue BasePtr = Load -> getBasePtr ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; SDLoc SL ( Op ) ; const MachinePointerInfo & SrcValue = Load -> getMemOperand ( ) -> getPointerInfo ( ) ; unsigned BaseAlign = Load -> getAlignment ( ) ; EVT WideVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , <NUM_LIT> ) ;

EVT WideMemVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MemVT . getVectorElementType ( ) , <NUM_LIT> ) ;


<s> assert ( VT . getVectorNumElements ( ) == <NUM_LIT> ) ; SDValue BasePtr = Load -> getBasePtr ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; SDLoc SL ( Op ) ; const MachinePointerInfo & SrcValue = Load -> getMemOperand ( ) -> getPointerInfo ( ) ; unsigned BaseAlign = Load -> getAlignment ( ) ; EVT WideVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , <NUM_LIT> ) ;


<s> if ( ! CMask ) return ; KnownBits LHSKnown = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; KnownBits RHSKnown = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned Sel = CMask -> getZExtValue ( ) ; for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; I += <NUM_LIT> ) { unsigned SelBits = Sel & <NUM_LIT> ; if ( SelBits < <NUM_LIT> ) { SelBits *= <NUM_LIT> ; Known . One |= ( ( RHSKnown . One . getZExtValue ( ) >> SelBits ) & <NUM_LIT> ) << I ; Known . Zero |= ( ( RHSKnown . Zero . getZExtValue ( ) >> SelBits ) & <NUM_LIT> ) << I ; } else if ( SelBits < <NUM_LIT> ) { SelBits = ( SelBits & <NUM_LIT> ) * <NUM_LIT> ; Known . One |= ( ( LHSKnown . One . getZExtValue ( ) >> SelBits ) & <NUM_LIT> ) << I ; Known . Zero |= ( ( LHSKnown . Zero . getZExtValue ( ) >> SelBits ) & <NUM_LIT> ) << I ; } else if ( SelBits == <NUM_LIT> ) { Known . Zero |= <NUM_LIT> << I ; } else if ( SelBits > <NUM_LIT> ) { Known . One |= <NUM_LIT> << I ; } Sel >>= <NUM_LIT> ; } break ; } case <STR_LIT> : { Known . Zero . setHighBits ( <NUM_LIT> ) ; break ; } case <STR_LIT> : { Known . Zero . setHighBits ( <NUM_LIT> ) ; break ; } case <STR_LIT> : { auto GA = cast < GlobalAddressSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; unsigned Align = GA -> getGlobal ( ) -> getAlignment ( ) ; Known . Zero . setHighBits ( <NUM_LIT> ) ; if ( Align ) Known . Zero . setLowBits ( Log2_32 ( Align ) ) ; break ; } case <STR_LIT> : { unsigned IID = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IID ) { case <STR_LIT> :


<s> const Function & Fn = * DAG . getMachineFunction ( ) . getFunction ( ) ; DiagnosticInfoUnsupported NoDynamicAlloca ( Fn , <STR_LIT> , SDLoc ( Op ) . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( NoDynamicAlloca ) ; return SDValue ( ) ;


<s> const Function & Fn = * DAG . getMachineFunction ( ) . getFunction ( ) ; DiagnosticInfoUnsupported NoDynamicAlloca ( Fn , <STR_LIT> , SDLoc ( Op ) . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( NoDynamicAlloca ) ;


<s> switch ( IntrinsicID ) { default : return Op ; case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) ) ;


<s> default : return Op ; case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> :


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & DL , SelectionDAG & DAG ) const {

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain ) ;


<s> assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; EVT DestVT = Op . getValueType ( ) ; if ( DestVT == <STR_LIT> ) return LowerINT_TO_FP32 ( Op , DAG , true ) ;

if ( DestVT == <STR_LIT> ) return LowerINT_TO_FP64 ( Op , DAG , true ) ;


<s> SDValue <ISA_LIT>TargetLowering :: Lower<ISA_LIT>NT_TO_FP ( SDValue Op , SelectionDAG & DAG ) const {

assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ;


<s> if ( DestVT == <STR_LIT> ) return LowerINT_TO_FP64 ( Op , DAG , false ) ; if ( DestVT == <STR_LIT> ) return LowerINT_TO_FP32 ( Op , DAG , false ) ; return SDValue ( ) ;


<s> assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; EVT DestVT = Op . getValueType ( ) ; if ( DestVT == <STR_LIT> ) return LowerINT_TO_FP64 ( Op , DAG , false ) ;

if ( DestVT == <STR_LIT> ) return LowerINT_TO_FP32 ( Op , DAG , false ) ;


<s> EVT VT = Value . getValueType ( ) ; if ( isTypeLegal ( VT ) || SN -> isVolatile ( ) || ! <STR_LIT> ( Value . getNode ( ) ) || VT . getSizeInBits ( ) < <NUM_LIT> ) return SDValue ( ) ; LoadSDNode * LoadVal = cast < LoadSDNode > ( Value ) ; if ( LoadVal -> isVolatile ( ) || ! usesAllNormalStores ( LoadVal ) ) return SDValue ( ) ; EVT MemVT = LoadVal -> getMemoryVT ( ) ; if ( ! MemVT . isRound ( ) ) return SDValue ( ) ; SDLoc SL ( N ) ; SelectionDAG & DAG = DCI . DAG ; EVT LoadVT = getEquivalentMemType ( * DAG . getContext ( ) , MemVT ) ; SDValue NewLoad = DAG . getLoad ( <STR_LIT> , <STR_LIT> , LoadVT , SL , LoadVal -> getChain ( ) , LoadVal -> getBasePtr ( ) , LoadVal -> getOffset ( ) , LoadVT , LoadVal -> getMemOperand ( ) ) ;

SDValue CastLoad = DAG . getNode ( <STR_LIT> , SL , VT , NewLoad . getValue ( <NUM_LIT> ) ) ;


<s> EVT VT = Value . getValueType ( ) ; if ( isTypeLegal ( VT ) || SN -> isVolatile ( ) || ! <STR_LIT> ( Value . getNode ( ) ) || VT . getSizeInBits ( ) < <NUM_LIT> ) return SDValue ( ) ; LoadSDNode * LoadVal = cast < LoadSDNode > ( Value ) ; if ( LoadVal -> isVolatile ( ) || ! usesAllNormalStores ( LoadVal ) ) return SDValue ( ) ; EVT MemVT = LoadVal -> getMemoryVT ( ) ; if ( ! MemVT . isRound ( ) ) return SDValue ( ) ;


<s> unsigned BaseAlign = Load -> getAlignment ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , LoVT , Load -> getChain ( ) , BasePtr , SrcValue , LoMemVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> isInvariant ( ) , BaseAlign ) ; SDValue HiPtr = DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( Size , SL , PtrVT ) ) ; SDValue HiLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , HiVT , Load -> getChain ( ) , HiPtr , SrcValue . getWithOffset ( LoMemVT . getStoreSize ( ) ) , HiMemVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> isInvariant ( ) , HiAlign ) ; SDValue Ops [ ] = { DAG . getNode ( <STR_LIT> , SL , VT , LoLoad , HiLoad ) , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LoLoad . getValue ( <NUM_LIT> ) , HiLoad . getValue ( <NUM_LIT> ) ) } ;

return DAG . getMergeValues ( Ops , SL ) ;


<s> EVT PtrVT = BasePtr . getValueType ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; SDLoc SL ( Op ) ; const MachinePointerInfo & SrcValue = Load -> getMemOperand ( ) -> getPointerInfo ( ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Op , SL , LoVT , HiVT ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned BaseAlign = Load -> getAlignment ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , LoVT , Load -> getChain ( ) , BasePtr , SrcValue , LoMemVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> isInvariant ( ) , BaseAlign ) ; SDValue HiPtr = DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( Size , SL , PtrVT ) ) ; SDValue HiLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , HiVT , Load -> getChain ( ) , HiPtr , SrcValue . getWithOffset ( LoMemVT . getStoreSize ( ) ) , HiMemVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> isInvariant ( ) , HiAlign ) ; SDValue Ops [ ] = {

DAG . getNode ( <STR_LIT> , SL , VT , LoLoad , HiLoad ) , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LoLoad . getValue ( <NUM_LIT> ) , HiLoad . getValue ( <NUM_LIT> ) ) } ;


<s> const MachinePointerInfo & SrcValue = Store -> getMemOperand ( ) -> getPointerInfo ( ) ; unsigned BaseAlign = Store -> getAlignment ( ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoStore = DAG . getTruncStore ( Chain , SL , Lo , BasePtr , SrcValue , LoMemVT , Store -> isNonTemporal ( ) , Store -> isVolatile ( ) , BaseAlign ) ; SDValue HiStore = DAG . getTruncStore ( Chain , SL , Hi , HiPtr , SrcValue . getWithOffset ( Size ) , HiMemVT , Store -> isNonTemporal ( ) , Store -> isVolatile ( ) , HiAlign ) ;

return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LoStore , HiStore ) ;


<s> EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Val , SL , LoVT , HiVT ) ; EVT PtrVT = BasePtr . getValueType ( ) ; SDValue HiPtr = DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( LoMemVT . getStoreSize ( ) , SL , PtrVT ) ) ; const MachinePointerInfo & SrcValue = Store -> getMemOperand ( ) -> getPointerInfo ( ) ; unsigned BaseAlign = Store -> getAlignment ( ) ; unsigned Size = LoMemVT . getStoreSize ( ) ;

unsigned HiAlign = MinAlign ( BaseAlign , Size ) ;


<s> case <STR_LIT> : { unsigned IntrID = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntrID ) { case <STR_LIT> : case <STR_LIT> : return true ; } return false ;


<s> case <STR_LIT> : case <STR_LIT> : return true ; } return false ; } case <STR_LIT> : if ( cast < LoadSDNode > ( N ) -> getMemOperand ( ) -> getAddrSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) return true ; return false ; } return false ;


<s> if ( SrcVT == <STR_LIT> || ( SrcVT == <STR_LIT> && Src . getOpcode ( ) == <STR_LIT> ) ) { SDLoc DL ( Op ) ;

SDValue FpToInt32 = DAG . getNode ( Op . getOpcode ( ) , DL , <STR_LIT> , Src ) ;


<s> SDLoc DL ( Op ) ; SDValue FpToUInt32 = DAG . getNode ( Op . getOpcode ( ) , DL , <STR_LIT> , Src ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FpToUInt32 ) ; }

if ( Op . getValueType ( ) == <STR_LIT> && Src . getValueType ( ) == <STR_LIT> ) return LowerFP64_TO_INT ( Op , DAG , false ) ;


<s> return DAG . getUNDEF ( Op . getValueType ( ) ) ; } assert ( G -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ! hasDefinedInitializer ( GV ) ) { unsigned Offset = MFI -> allocateLDSGlobal ( DL , * cast < GlobalVariable > ( GV ) ) ; return DAG . getConstant ( Offset , SDLoc ( Op ) , Op . getValueType ( ) ) ; } } const Function & Fn = DAG . getMachineFunction ( ) . getFunction ( ) ; DiagnosticInfoUnsupported BadInit ( Fn , <STR_LIT> , SDLoc ( Op ) . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( BadInit ) ;


<s> if ( CCOpcode == <STR_LIT> && ( isCtlzOpc ( RHS . getOpcode ( ) ) || isCttzOpc ( RHS . getOpcode ( ) ) ) && RHS . getOperand ( <NUM_LIT> ) == CmpLHS && isNegativeOne ( LHS ) ) { unsigned Opc = isCttzOpc ( RHS . getOpcode ( ) ) ? <STR_LIT> : <STR_LIT> ; return getFFBX_U32 ( DAG , CmpLHS , SL , Opc ) ; } if ( CCOpcode == <STR_LIT> && ( isCtlzOpc ( LHS . getOpcode ( ) ) || isCttzOpc ( LHS . getOpcode ( ) ) ) && LHS . getOperand ( <NUM_LIT> ) == CmpLHS && isNegativeOne ( RHS ) ) { unsigned Opc = isCttzOpc ( LHS . getOpcode ( ) ) ? <STR_LIT> : <STR_LIT> ; return getFFBX_U32 ( DAG , CmpLHS , SL , Opc ) ; } return SDValue ( ) ;


<s> SelectionDAG & DAG = DCI . DAG ; <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue CmpLHS = Cond . getOperand ( <NUM_LIT> ) ; if ( CCOpcode == <STR_LIT> && ( isCtlzOpc ( RHS . getOpcode ( ) ) || isCttzOpc ( RHS . getOpcode ( ) ) ) && RHS . getOperand ( <NUM_LIT> ) == CmpLHS && isNegativeOne ( LHS ) ) {

unsigned Opc = isCttzOpc ( RHS . getOpcode ( ) ) ? <STR_LIT> : <STR_LIT> ;


<s> SDLoc SL ( N ) ; uint64_t CVal = Val . getZExtValue ( ) ; SDValue Vec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DAG . getConstant ( Lo_32 ( CVal ) , SL , <STR_LIT> ) , DAG . getConstant ( Hi_32 ( CVal ) , SL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SL , DestVT , Vec ) ; } break ; } case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) break ; return performShlCombine ( N , DCI ) ; } case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) break ; return performSrlCombine ( N , DCI ) ; } case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) break ; return performSraCombine ( N , DCI ) ; } case <STR_LIT> : return performTruncateCombine ( N , DCI ) ; case <STR_LIT> : return performMulCombine ( N , DCI ) ; case <STR_LIT> : return performMulhsCombine ( N , DCI ) ; case <STR_LIT> : return performMulhuCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( SDValue V = simplifyI24 ( N , DCI ) ) return V ; return SDValue ( ) ; } case <STR_LIT> : return performSelectCombine ( N , DCI ) ; case <STR_LIT> : return performFNegCombine ( N , DCI ) ; case <STR_LIT> : return performFAbsCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : { assert ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) && <STR_LIT> ) ; ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) break ; uint32_t WidthVal = Width -> getZExtValue ( ) & <NUM_LIT> ; if ( WidthVal == <NUM_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; SDValue BitsFrom = N -> getOperand ( <NUM_LIT> ) ; uint32_t OffsetVal = Offset -> getZExtValue ( ) & <NUM_LIT> ; bool Signed = N -> getOpcode ( ) == <STR_LIT> ; if ( OffsetVal == <NUM_LIT> ) { unsigned SignBits = Signed ? ( <NUM_LIT> - WidthVal + <NUM_LIT> ) : ( <NUM_LIT> - WidthVal ) ; unsigned OpSignBits = DAG . ComputeNumSignBits ( BitsFrom ) ; if ( OpSignBits >= SignBits ) return BitsFrom ; EVT SmallVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , WidthVal ) ; if ( Signed ) {

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BitsFrom , DAG . getValueType ( SmallVT ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: performIntrinsicWOChainCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { unsigned IID = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IID ) {


<s> SelectionDAG & DAG = DCI . DAG ; EVT VT = LN -> getMemoryVT ( ) ; unsigned Size = VT . getStoreSize ( ) ; Align Alignment = LN -> getAlign ( ) ; if ( Alignment < Size && isTypeLegal ( VT ) ) { bool IsFast ; unsigned AS = LN -> getAddressSpace ( ) ; if ( ! allowsMisalignedMemoryAccesses ( VT , AS , Alignment . value ( ) , LN -> getMemOperand ( ) -> getFlags ( ) , & IsFast ) ) { SDValue Ops [ <NUM_LIT> ] ; if ( VT . isVector ( ) ) std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = scalarizeVectorLoad ( LN , DAG ) ; else std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = expandUnalignedLoad ( LN , DAG ) ;

return DAG . getMergeValues ( Ops , SDLoc ( N ) ) ;


<s> if ( Alignment < Size && isTypeLegal ( VT ) ) { bool IsFast ; unsigned AS = SN -> getAddressSpace ( ) ; if ( ! allowsMisalignedMemoryAccesses ( VT , AS , Alignment . value ( ) , SN -> getMemOperand ( ) -> getFlags ( ) , & IsFast ) ) { if ( VT . isVector ( ) ) return scalarizeVectorStore ( SN , DAG ) ; return expandUnalignedStore ( SN , DAG ) ; } if ( ! IsFast ) return SDValue ( ) ; } if ( ! shouldCombineMemoryType ( VT ) ) return SDValue ( ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue Val = SN -> getValue ( ) ; bool OtherUses = ! Val . hasOneUse ( ) ; SDValue CastVal = DAG . getNode ( <STR_LIT> , SL , NewVT , Val ) ; if ( OtherUses ) { SDValue CastBack = DAG . getNode ( <STR_LIT> , SL , VT , CastVal ) ; DAG . ReplaceAllUsesOfValueWith ( Val , CastBack ) ;


<s> SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . getOpcode ( ) == <STR_LIT> && ! VT . isVector ( ) ) { SDValue Vec = Src . getOperand ( <NUM_LIT> ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) { SDValue Elt0 = Vec . getOperand ( <NUM_LIT> ) ; EVT EltVT = Elt0 . getValueType ( ) ; if ( VT . getFixedSizeInBits ( ) <= EltVT . getFixedSizeInBits ( ) ) { if ( EltVT . isFloatingPoint ( ) ) { Elt0 = DAG . getNode ( <STR_LIT> , SL , EltVT . changeTypeToInteger ( ) , Elt0 ) ; } return DAG . getNode ( <STR_LIT> , SL , VT , Elt0 ) ; } } } if ( Src . getOpcode ( ) == <STR_LIT> && ! VT . isVector ( ) ) { if ( auto K = isConstOrConstSplat ( Src . getOperand ( <NUM_LIT> ) ) ) { if ( <NUM_LIT> * K -> getZExtValue ( ) == Src . getValueType ( ) . getScalarSizeInBits ( ) ) { SDValue BV = stripBitcast ( Src . getOperand ( <NUM_LIT> ) ) ; if ( BV . getOpcode ( ) == <STR_LIT> && BV . getValueType ( ) . getVectorNumElements ( ) == <NUM_LIT> ) { SDValue SrcElt = BV . getOperand ( <NUM_LIT> ) ; EVT SrcEltVT = SrcElt . getValueType ( ) ; if ( SrcEltVT . isFloatingPoint ( ) ) { SrcElt = DAG . getNode ( <STR_LIT> , SL , SrcEltVT . changeTypeToInteger ( ) , SrcElt ) ; } return DAG . getNode ( <STR_LIT> , SL , VT , SrcElt ) ; } } } } if ( VT . getScalarSizeInBits ( ) < <NUM_LIT> ) { EVT SrcVT = Src . getValueType ( ) ; if ( SrcVT . getScalarSizeInBits ( ) > <NUM_LIT> && ( Src . getOpcode ( ) == <STR_LIT> || Src . getOpcode ( ) == <STR_LIT> || Src . getOpcode ( ) == <STR_LIT> ) ) {

SDValue Amt = Src . getOperand ( <NUM_LIT> ) ;


<s> } APInt Demanded = APInt :: getLowBitsSet ( LHS . getValueSizeInBits ( ) , <NUM_LIT> ) ; SDValue DemandedLHS = TLI . SimplifyMultipleUseDemandedBits ( LHS , Demanded , DAG ) ; SDValue DemandedRHS = TLI . SimplifyMultipleUseDemandedBits ( RHS , Demanded , DAG ) ;

if ( DemandedLHS || DemandedRHS ) return DAG . getNode ( NewOpcode , SDLoc ( Node24 ) , Node24 -> getVTList ( ) , DemandedLHS ? DemandedLHS : LHS , DemandedRHS ? DemandedRHS : RHS ) ;


<s> SDValue Ptr = DAG . getConstant ( Offset , SL , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Chain , SL , ArgVal , Ptr , DstInfo , Align ( <NUM_LIT> ) , MachineMemOperand :: MODereferenceable ) ; return Store ;


<s> SDValue Store = DAG . getStore ( Chain , SL , ArgVal , Ptr , DstInfo , Align ( <NUM_LIT> ) , MachineMemOperand :: MODereferenceable ) ;


<s> const DataLayout & DL = Fn . getParent ( ) -> getDataLayout ( ) ; unsigned InIndex = <NUM_LIT> ; for ( const Argument & Arg : Fn . args ( ) ) { Type * BaseArgTy = Arg . getType ( ) ; unsigned Align = DL . getABITypeAlignment ( BaseArgTy ) ; MaxAlign = std :: max ( Align , MaxAlign ) ; unsigned AllocSize = DL . getTypeAllocSize ( BaseArgTy ) ; uint64_t ArgOffset = alignTo ( ExplicitArgOffset , Align ) + ExplicitOffset ; ExplicitArgOffset = alignTo ( ExplicitArgOffset , Align ) + AllocSize ; SmallVector < EVT , <NUM_LIT> > ValueVTs ; SmallVector < uint64_t , <NUM_LIT> > Offsets ; ComputeValueVTs ( * this , DL , BaseArgTy , ValueVTs , & Offsets , ArgOffset ) ; for ( unsigned Value = <NUM_LIT> , NumValues = ValueVTs . size ( ) ; Value != NumValues ; ++ Value ) { uint64_t BasePartOffset = Offsets [ Value ] ; EVT ArgVT = ValueVTs [ Value ] ; EVT MemVT = ArgVT ; MVT RegisterVT = getRegisterTypeForCallingConv ( Ctx , CC , ArgVT ) ; unsigned NumRegs = getNumRegistersForCallingConv ( Ctx , CC , ArgVT ) ; if ( NumRegs == <NUM_LIT> ) { if ( ArgVT . isExtended ( ) ) { MemVT = RegisterVT ; } else { MemVT = ArgVT ; } } else if ( ArgVT . isVector ( ) && RegisterVT . isVector ( ) && ArgVT . getScalarType ( ) == RegisterVT . getScalarType ( ) ) { assert ( ArgVT . getVectorNumElements ( ) > RegisterVT . getVectorNumElements ( ) ) ; MemVT = RegisterVT ;

} else if ( ArgVT . isVector ( ) && ArgVT . getVectorNumElements ( ) == NumRegs ) {


<s> KnownBits RHSKnown = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned Sel = CMask -> getZExtValue ( ) ; for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; I += <NUM_LIT> ) { unsigned SelBits = Sel & <NUM_LIT> ; if ( SelBits < <NUM_LIT> ) { SelBits *= <NUM_LIT> ; Known . One |= ( ( RHSKnown . One . getZExtValue ( ) >> SelBits ) & <NUM_LIT> ) << I ; Known . Zero |= ( ( RHSKnown . Zero . getZExtValue ( ) >> SelBits ) & <NUM_LIT> ) << I ; } else if ( SelBits < <NUM_LIT> ) { SelBits = ( SelBits & <NUM_LIT> ) * <NUM_LIT> ; Known . One |= ( ( LHSKnown . One . getZExtValue ( ) >> SelBits ) & <NUM_LIT> ) << I ; Known . Zero |= ( ( LHSKnown . Zero . getZExtValue ( ) >> SelBits ) & <NUM_LIT> ) << I ; } else if ( SelBits == <NUM_LIT> ) { Known . Zero |= <NUM_LIT> << I ; } else if ( SelBits > <NUM_LIT> ) { Known . One |= <NUM_LIT> << I ; } Sel >>= <NUM_LIT> ; } break ; } case <STR_LIT> : { Known . Zero . setHighBits ( <NUM_LIT> ) ; break ; } case <STR_LIT> : { Known . Zero . setHighBits ( <NUM_LIT> ) ; break ; } case <STR_LIT> : { auto GA = cast < GlobalAddressSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; unsigned Align = GA -> getGlobal ( ) -> getAlignment ( ) ; Known . Zero . setHighBits ( <NUM_LIT> ) ; if ( Align ) Known . Zero . setLowBits ( Log2_32 ( Align ) ) ; break ; }