<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef GPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , TargetTriple ( TT ) , Gen ( TT . getArch ( ) == Triple :: amdgcn ? SOUTHERN_ISLANDS : <ISA_LIT> ) , IsaVersion ( ISAVersion0_0_0 ) , WavefrontSize ( <NUM_LIT> ) , LocalMemorySize ( <NUM_LIT> ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP32Denormals ( false ) , FP64FP16Denormals ( false ) , FPExceptions ( false ) , DX10Clamp ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , CodeObjectV3 ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , TrapHandler ( false ) , DebuggerInsertNops ( false ) , DebuggerReserveRegs ( false ) , DebuggerEmitPrologue ( false ) , EnableHugePrivateBuffer ( false ) , EnableVGPRSpilling ( false ) , EnablePromoteAlloca ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , DumpCode ( false ) , FP64 ( false ) , FMA ( false ) , IsGCN ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , Has16BitInsts ( false ) , HasIntClamp ( false ) , HasVOP3PInsts ( false ) , HasMadMixInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasInv2PiInlineImm ( false ) , HasSDWA ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , AddNoCarryInsts ( false ) , <ISA_LIT>ALUInst ( false ) , CaymanISA ( false ) , CFALUBug ( false ) , HasVertexCache ( false ) , TexVTXClauseSize ( <NUM_LIT> ) , ScalarizeGlobal ( false ) , FeatureDisable ( false ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) { AS = <STR_LIT> ( TT ) ;

initializeSubtargetDependencies ( TT , GPU , FS ) ;


<s> <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , <ISA_LIT>Subtarget ( TT ) , TargetTriple ( TT ) , Gen ( SOUTHERN_ISLANDS ) , IsaVersion ( ISAVersion0_0_0 ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP64FP16Denormals ( false ) , DX10Clamp ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , CodeObjectV3 ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , TrapHandler ( false ) , DebuggerInsertNops ( false ) , DebuggerEmitPrologue ( false ) , EnableHugePrivateBuffer ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , EnableDS128 ( false ) , EnablePRTStrictNull ( false ) , DumpCode ( false ) , FP64 ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , VIInsts ( false ) , GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , HasIntClamp ( false ) , HasFmaMixInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasScalarAtomics ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , HasR128A16 ( false ) , HasDLInsts ( false ) , HasDotInsts ( false ) , EnableSRAMECC ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , AddNoCarryInsts ( false ) , HasUnpackedD16VMem ( false ) , ScalarizeGlobal ( false ) , FeatureDisable ( false ) , InstrInfo ( initializeSubtargetDependencies ( TT , GPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) { CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ;

Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this , TM ) ) ;


<s> if ( LDSBankCount == <NUM_LIT> ) LDSBankCount = <NUM_LIT> ; if ( TT . getArch ( ) == Triple :: amdgcn ) { if ( LocalMemorySize == <NUM_LIT> ) LocalMemorySize = <NUM_LIT> ; if ( ! HasMovrel && ! HasVGPRIndexMode ) HasMovrel = true ; } HasFminFmaxLegacy = getGeneration ( ) < <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ; return * this ;


<s> bool needWaitcntBeforeBarrier ( ) const { return getGeneration ( ) < GFX9 ;


<s> MaxAlign = Align ( <NUM_LIT> ) ; for ( const Argument & Arg : F . args ( ) ) { Type * ArgTy = Arg . getType ( ) ; const Align Alignment = DL . getABITypeAlign ( ArgTy ) ;

uint64_t AllocSize = DL . getTypeAllocSize ( ArgTy ) ;


<s> for ( const Argument & Arg : F . args ( ) ) { Type * ArgTy = Arg . getType ( ) ; const Align Alignment = DL . getABITypeAlign ( ArgTy ) ; uint64_t AllocSize = DL . getTypeAllocSize ( ArgTy ) ; ExplicitArgBytes = alignTo ( ExplicitArgBytes , Alignment ) + AllocSize ;

MaxAlign = std :: max ( MaxAlign , Alignment ) ;


<s> assert ( ! hasFP64 ( ) || ( getGeneration ( ) >= <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) ) ; if ( ! hasAddr64 ( ) && ! FS . contains ( <STR_LIT> ) ) { FlatForGlobal = true ; } if ( MaxPrivateElementSize == <NUM_LIT> ) MaxPrivateElementSize = <NUM_LIT> ; if ( LDSBankCount == <NUM_LIT> ) LDSBankCount = <NUM_LIT> ; if ( TT . getArch ( ) == Triple :: amdgcn ) { if ( LocalMemorySize == <NUM_LIT> ) LocalMemorySize = <NUM_LIT> ; if ( ! HasMovrel && ! HasVGPRIndexMode ) HasMovrel = true ; } if ( WavefrontSizeLog2 == <NUM_LIT> ) WavefrontSizeLog2 = <NUM_LIT> ; HasFminFmaxLegacy = getGeneration ( ) < <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ; if ( ! FS . contains ( <STR_LIT> ) && DoesNotSupportXNACK && EnableXNACK ) { ToggleFeature ( <STR_LIT> ) ; EnableXNACK = false ; } if ( DoesNotSupportSRAMECC && EnableSRAMECC ) { ToggleFeature ( <STR_LIT> ) ; EnableSRAMECC = false ; } return * this ;


<s> if ( LDSBankCount == <NUM_LIT> ) LDSBankCount = <NUM_LIT> ; if ( TT . getArch ( ) == Triple :: amdgcn ) { if ( LocalMemorySize == <NUM_LIT> ) LocalMemorySize = <NUM_LIT> ; if ( ! HasMovrel && ! HasVGPRIndexMode ) HasMovrel = true ; } if ( WavefrontSizeLog2 == <NUM_LIT> ) WavefrontSizeLog2 = <NUM_LIT> ; HasFminFmaxLegacy = getGeneration ( ) < <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ; if ( ! FS . contains ( <STR_LIT> ) && DoesNotSupportXNACK && EnableXNACK ) { ToggleFeature ( <STR_LIT> ) ; EnableXNACK = false ; } if ( DoesNotSupportSRAMECC && EnableSRAMECC ) { ToggleFeature ( <STR_LIT> ) ; EnableSRAMECC = false ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef GPU , StringRef FS , TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , DumpCode ( false ) , <ISA_LIT>ALUInst ( false ) , HasVertexCache ( false ) , TexVTXClauseSize ( <NUM_LIT> ) , Gen ( <ISA_LIT>Subtarget :: <ISA_LIT> ) , FP64 ( false ) , FP64Denormals ( false ) , FP32Denormals ( false ) , FastFMAF32 ( false ) , CaymanISA ( false ) , FlatAddressSpace ( false ) , FlatForGlobal ( false ) , EnableIRStructurizer ( true ) , EnablePromoteAlloca ( false ) , EnableIfCvt ( true ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , EnableXNACK ( false ) , WavefrontSize ( <NUM_LIT> ) , CFALUBug ( false ) , LocalMemorySize ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , EnableVGPRSpilling ( false ) , SGPRInitBug ( false ) , IsGCN ( false ) , GCN1Encoding ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , LDSBankCount ( <NUM_LIT> ) , IsaVersion ( ISAVersion0_0_0 ) , EnableHugeScratchBuffer ( false ) , Enable<ISA_LIT>Scheduler ( false ) , FrameLowering ( nullptr ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) , TargetTriple ( TT ) { initializeSubtargetDependencies ( TT , GPU , FS ) ; const unsigned MaxStackAlign = <NUM_LIT> * <NUM_LIT> ; if ( getGeneration ( ) <= <ISA_LIT>Subtarget :: NORTHERN_ISLANDS ) { InstrInfo . reset ( new <ISA_LIT>InstrInfo ( * this ) ) ; TLInfo . reset ( new <ISA_LIT>TargetLowering ( TM , * this ) ) ; FrameLowering . reset ( new <ISA_LIT>FrameLowering ( TargetFrameLowering :: StackGrowsUp , MaxStackAlign , <NUM_LIT> ) ) ; } else { InstrInfo . reset ( new <ISA_LIT>InstrInfo ( * this ) ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef GPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , TargetTriple ( TT ) , Gen ( TT . getArch ( ) == Triple :: amdgcn ? SOUTHERN_ISLANDS : <ISA_LIT> ) , IsaVersion ( ISAVersion0_0_0 ) , WavefrontSize ( <NUM_LIT> ) , LocalMemorySize ( <NUM_LIT> ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP32Denormals ( false ) , FP64FP16Denormals ( false ) , FPExceptions ( false ) , DX10Clamp ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , TrapHandler ( false ) , DebuggerInsertNops ( false ) , DebuggerReserveRegs ( false ) , DebuggerEmitPrologue ( false ) , EnableVGPRSpilling ( false ) , EnablePromoteAlloca ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , DumpCode ( false ) , FP64 ( false ) , IsGCN ( false ) , GCN1Encoding ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , Has16BitInsts ( false ) , HasVOP3PInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasInv2PiInlineImm ( false ) , HasSDWA ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , <ISA_LIT>ALUInst ( false ) , CaymanISA ( false ) , CFALUBug ( false ) , HasVertexCache ( false ) , TexVTXClauseSize ( <NUM_LIT> ) , ScalarizeGlobal ( false ) , FeatureDisable ( false ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) { AS = <STR_LIT> ( TT ) ;


<s> const <ISA_LIT>CallLowering * getCallLowering ( ) const override {


<s> GISel -> RegBankInfo . reset ( new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ) ; GISel -> InstSelector . reset ( new <ISA_LIT>InstructionSelector ( * this , * static_cast < <ISA_LIT>RegisterBankInfo * > ( GISel -> RegBankInfo . get ( ) ) ) ) ;


<s> GISel -> Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( ) ) ; GISel -> RegBankInfo . reset ( new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ) ;

GISel -> InstSelector . reset ( new <ISA_LIT>InstructionSelector ( * this , * static_cast < <ISA_LIT>RegisterBankInfo * > ( GISel -> RegBankInfo . get ( ) ) ) ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef GPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , TargetTriple ( TT ) , Gen ( TT . getArch ( ) == Triple :: amdgcn ? SOUTHERN_ISLANDS : <ISA_LIT> ) , IsaVersion ( ISAVersion0_0_0 ) , WavefrontSize ( <NUM_LIT> ) , LocalMemorySize ( <NUM_LIT> ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP32Denormals ( false ) , FP64FP16Denormals ( false ) , FPExceptions ( false ) , DX10Clamp ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , TrapHandler ( false ) , DebuggerInsertNops ( false ) , DebuggerReserveRegs ( false ) , DebuggerEmitPrologue ( false ) , EnableVGPRSpilling ( false ) , EnablePromoteAlloca ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , DumpCode ( false ) , FP64 ( false ) , IsGCN ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , Has16BitInsts ( false ) , HasIntClamp ( false ) , HasVOP3PInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasInv2PiInlineImm ( false ) , HasSDWA ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , AddNoCarryInsts ( false ) , <ISA_LIT>ALUInst ( false ) , CaymanISA ( false ) , CFALUBug ( false ) , HasVertexCache ( false ) , TexVTXClauseSize ( <NUM_LIT> ) , ScalarizeGlobal ( false ) , FeatureDisable ( false ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) { AS = <STR_LIT> ( TT ) ;


<s> } if ( MaxPrivateElementSize == <NUM_LIT> ) MaxPrivateElementSize = <NUM_LIT> ; if ( LDSBankCount == <NUM_LIT> ) LDSBankCount = <NUM_LIT> ; if ( TT . getArch ( ) == Triple :: amdgcn ) { if ( LocalMemorySize == <NUM_LIT> ) LocalMemorySize = <NUM_LIT> ;

if ( ! HasMovrel && ! HasVGPRIndexMode ) HasMovrel = true ;


<s> FP32Denormals = false ; } if ( MaxPrivateElementSize == <NUM_LIT> ) MaxPrivateElementSize = <NUM_LIT> ; if ( LDSBankCount == <NUM_LIT> ) LDSBankCount = <NUM_LIT> ; if ( TT . getArch ( ) == Triple :: amdgcn ) { if ( LocalMemorySize == <NUM_LIT> ) LocalMemorySize = <NUM_LIT> ; if ( ! HasMovrel && ! HasVGPRIndexMode ) HasMovrel = true ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef GPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , TargetTriple ( TT ) , Gen ( TT . getArch ( ) == Triple :: amdgcn ? SOUTHERN_ISLANDS : <ISA_LIT> ) , IsaVersion ( ISAVersion0_0_0 ) , WavefrontSize ( <NUM_LIT> ) , LocalMemorySize ( <NUM_LIT> ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP32Denormals ( false ) , FP64FP16Denormals ( false ) , FPExceptions ( false ) , DX10Clamp ( false ) , FlatForGlobal ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , TrapHandler ( false ) , DebuggerInsertNops ( false ) , DebuggerReserveRegs ( false ) , DebuggerEmitPrologue ( false ) , EnableVGPRSpilling ( false ) , EnablePromoteAlloca ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , DumpCode ( false ) , FP64 ( false ) , IsGCN ( false ) , GCN1Encoding ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , Has16BitInsts ( false ) , HasVOP3PInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasInv2PiInlineImm ( false ) , HasSDWA ( false ) , HasDPP ( false ) , FlatAddressSpace ( false ) , <ISA_LIT>ALUInst ( false ) , CaymanISA ( false ) , CFALUBug ( false ) , HasVertexCache ( false ) , TexVTXClauseSize ( <NUM_LIT> ) , ScalarizeGlobal ( false ) , FeatureDisable ( false ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) { AS = <STR_LIT> ( TT ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef GPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , TargetTriple ( TT ) , Gen ( TT . getArch ( ) == Triple :: amdgcn ? SOUTHERN_ISLANDS : <ISA_LIT> ) , IsaVersion ( ISAVersion0_0_0 ) , WavefrontSize ( <NUM_LIT> ) , LocalMemorySize ( <NUM_LIT> ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP32Denormals ( false ) , FP64FP16Denormals ( false ) , FPExceptions ( false ) , DX10Clamp ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , CodeObjectV3 ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , TrapHandler ( false ) , DebuggerInsertNops ( false ) , DebuggerReserveRegs ( false ) , DebuggerEmitPrologue ( false ) , EnableHugePrivateBuffer ( false ) , EnableVGPRSpilling ( false ) , EnablePromoteAlloca ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , EnableDS128 ( false ) , DumpCode ( false ) , FP64 ( false ) , FMA ( false ) , MIMG_R128 ( false ) , IsGCN ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , Has16BitInsts ( false ) , HasIntClamp ( false ) , HasVOP3PInsts ( false ) , HasMadMixInsts ( false ) , HasFmaMixInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasScalarAtomics ( false ) , HasInv2PiInlineImm ( false ) , HasSDWA ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , HasDLInsts ( false ) , D16PreservesUnusedBits ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , AddNoCarryInsts ( false ) , HasUnpackedD16VMem ( false ) , <ISA_LIT>ALUInst ( false ) , CaymanISA ( false ) , CFALUBug ( false ) , HasVertexCache ( false ) , TexVTXClauseSize ( <NUM_LIT> ) , ScalarizeGlobal ( false ) , FeatureDisable ( false ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) { AS = <STR_LIT> ( TT ) ; initializeSubtargetDependencies ( TT , GPU , FS ) ;


<s> unsigned getMaxFlatWorkGroupSize ( ) const {


<s> unsigned getMaxWavesPerCU ( unsigned FlatWorkGroupSize ) const {

return getWavesPerWorkGroup ( FlatWorkGroupSize ) ;


<s> unsigned getMaxWorkGroupsPerCU ( unsigned FlatWorkGroupSize ) const { if ( getGeneration ( ) < <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) return <NUM_LIT> ;

return getWavesPerWorkGroup ( FlatWorkGroupSize ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ;


<s> unsigned getMinFlatWorkGroupSize ( ) const { return <NUM_LIT> ;


<s> unsigned getMinWavesPerEU ( ) const {


<s> unsigned getWavesPerWorkGroup ( unsigned FlatWorkGroupSize ) const {

return alignTo ( FlatWorkGroupSize , getWavefrontSize ( ) ) / getWavefrontSize ( ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef GPU , StringRef FS , const GCNTargetMachine & TM ) : <ISA_LIT>Subtarget ( TT , GPU , FS , TM ) , InstrInfo ( * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) , TLInfo ( TM , * this ) { CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef GPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , TargetTriple ( TT ) , Gen ( TT . getArch ( ) == Triple :: amdgcn ? SOUTHERN_ISLANDS : <ISA_LIT> ) , IsaVersion ( ISAVersion0_0_0 ) , WavefrontSize ( <NUM_LIT> ) , LocalMemorySize ( <NUM_LIT> ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP16Denormals ( false ) , FP32Denormals ( false ) , FP64Denormals ( false ) , FPExceptions ( false ) , FlatForGlobal ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , EnableXNACK ( false ) , DebuggerInsertNops ( false ) , DebuggerReserveRegs ( false ) , DebuggerEmitPrologue ( false ) , EnableVGPRSpilling ( false ) , EnablePromoteAlloca ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , DumpCode ( false ) , FP64 ( false ) , IsGCN ( false ) , GCN1Encoding ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , Has16BitInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasInv2PiInlineImm ( false ) , FlatAddressSpace ( false ) , <ISA_LIT>ALUInst ( false ) , CaymanISA ( false ) , CFALUBug ( false ) , HasVertexCache ( false ) , TexVTXClauseSize ( <NUM_LIT> ) , ScalarizeGlobal ( false ) , FeatureDisable ( false ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) {


<s> if ( hasSGPRInitBug ( ) ) return <ISA_LIT>Subtarget :: FIXED_SGPR_COUNT_FOR_INIT_BUG ; if ( getGeneration ( ) >= VOLCANIC_ISLANDS ) return <NUM_LIT> ;


<s> if ( hasSGPRInitBug ( ) ) return <ISA_LIT>Subtarget :: FIXED_SGPR_COUNT_FOR_INIT_BUG ; if ( getGeneration ( ) >= VOLCANIC_ISLANDS ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> RequestedFlatWorkGroupSize = true ; } std :: pair < unsigned , unsigned > Requested = <STR_LIT> ( F , <STR_LIT> , Default , true ) ; if ( Requested . second && Requested . first > Requested . second ) return Default ; if ( Requested . first < getMinWavesPerEU ( ) || Requested . first > getMaxWavesPerEU ( ) ) return Default ;

if ( Requested . second > getMaxWavesPerEU ( ) ) return Default ;


<s> FullFS += FS ; ParseSubtargetFeatures ( GPU , FullFS ) ; if ( ! hasAddr64 ( ) && ! FS . contains ( <STR_LIT> ) ) { FlatForGlobal = true ; } if ( getGeneration ( ) <= <ISA_LIT>Subtarget :: NORTHERN_ISLANDS ) { FP16Denormals = false ; FP32Denormals = false ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef GPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , TargetTriple ( TT ) , Gen ( TT . getArch ( ) == Triple :: amdgcn ? SOUTHERN_ISLANDS : <ISA_LIT> ) , IsaVersion ( ISAVersion0_0_0 ) , WavefrontSize ( <NUM_LIT> ) , LocalMemorySize ( <NUM_LIT> ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP32Denormals ( false ) , FP64FP16Denormals ( false ) , FPExceptions ( false ) , FlatForGlobal ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , EnableXNACK ( false ) , DebuggerInsertNops ( false ) , DebuggerReserveRegs ( false ) , DebuggerEmitPrologue ( false ) , EnableVGPRSpilling ( false ) , EnablePromoteAlloca ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , DumpCode ( false ) , FP64 ( false ) , IsGCN ( false ) , GCN1Encoding ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , Has16BitInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasInv2PiInlineImm ( false ) , HasSDWA ( false ) , HasDPP ( false ) , FlatAddressSpace ( false ) , <ISA_LIT>ALUInst ( false ) , CaymanISA ( false ) , CFALUBug ( false ) , HasVertexCache ( false ) , TexVTXClauseSize ( <NUM_LIT> ) , ScalarizeGlobal ( false ) , FeatureDisable ( false ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) { initializeSubtargetDependencies ( TT , GPU , FS ) ;


<s> if ( isAmdHsaOS ( ) ) FullFS += <STR_LIT> ; FullFS += FS ; ParseSubtargetFeatures ( GPU , FullFS ) ; if ( ! hasAddr64 ( ) && ! FS . contains ( <STR_LIT> ) ) { FlatForGlobal = true ; } if ( getGeneration ( ) <= <ISA_LIT>Subtarget :: NORTHERN_ISLANDS ) { FP64FP16Denormals = false ;


<s> TargetTriple ( TT ) , Has16BitInsts ( false ) , HasMadMixInsts ( false ) , HasSDWA ( false ) , HasVOP3PInsts ( false ) , HasMulI24 ( true ) , HasMulU24 ( true ) , HasInv2PiInlineImm ( false ) , HasFminFmaxLegacy ( true ) , EnablePromoteAlloca ( false ) , HasTrigReducedRange ( false ) , MaxWavesPerEU ( <NUM_LIT> ) , LocalMemorySize ( <NUM_LIT> ) , WavefrontSize ( <NUM_LIT> ) {


<s> bool useDS128 ( bool UserEnable ) const {


<s> ToggleFeature ( <STR_LIT> ) ; FlatForGlobal = true ; } if ( ! hasFlat ( ) && ! FS . contains ( <STR_LIT> ) && FlatForGlobal ) { ToggleFeature ( <STR_LIT> ) ; FlatForGlobal = false ; } if ( MaxPrivateElementSize == <NUM_LIT> ) MaxPrivateElementSize = <NUM_LIT> ; if ( LDSBankCount == <NUM_LIT> ) LDSBankCount = <NUM_LIT> ; if ( TT . getArch ( ) == Triple :: amdgcn ) { if ( LocalMemorySize == <NUM_LIT> ) LocalMemorySize = <NUM_LIT> ; if ( ! HasMovrel && ! HasVGPRIndexMode ) HasMovrel = true ; } if ( WavefrontSizeLog2 == <NUM_LIT> ) WavefrontSizeLog2 = <NUM_LIT> ; HasFminFmaxLegacy = getGeneration ( ) < <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ; TargetID . setTargetIDFromFeaturesString ( FS ) ;

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TargetID . getXnackSetting ( ) << '\n' ) ;


<s> FullFS += FS ; ParseSubtargetFeatures ( GPU , GPU , FullFS ) ; if ( Gen == <ISA_LIT>Subtarget :: INVALID ) { Gen = TT . getOS ( ) == Triple :: AMDHSA ? <ISA_LIT>Subtarget :: SEA_ISLANDS : <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ; } assert ( ! hasFP64 ( ) || ( getGeneration ( ) >= <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) ) ; assert ( hasAddr64 ( ) || hasFlat ( ) ) ; if ( ! hasAddr64 ( ) && ! FS . contains ( <STR_LIT> ) && ! FlatForGlobal ) { ToggleFeature ( <STR_LIT> ) ; FlatForGlobal = true ; }

if ( ! hasFlat ( ) && ! FS . contains ( <STR_LIT> ) && FlatForGlobal ) {


<s> SmallString < <NUM_LIT> > FullFS ( <STR_LIT> ) ; if ( isAmdHsaOS ( ) ) FullFS += <STR_LIT> ; FullFS += <STR_LIT> ; if ( FS . find_insensitive ( <STR_LIT> ) != StringRef :: npos ) { if ( FS . find_insensitive ( <STR_LIT> ) == StringRef :: npos ) FullFS += <STR_LIT> ; if ( FS . find_insensitive ( <STR_LIT> ) == StringRef :: npos ) FullFS += <STR_LIT> ; if ( FS . find_insensitive ( <STR_LIT> ) == StringRef :: npos ) FullFS += <STR_LIT> ; } FullFS += FS ; ParseSubtargetFeatures ( GPU , GPU , FullFS ) ; if ( Gen == <ISA_LIT>Subtarget :: INVALID ) { Gen = TT . getOS ( ) == Triple :: AMDHSA ? <ISA_LIT>Subtarget :: SEA_ISLANDS : <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ; } assert ( ! hasFP64 ( ) || ( getGeneration ( ) >= <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) ) ; assert ( hasAddr64 ( ) || hasFlat ( ) ) ; if ( ! hasAddr64 ( ) && ! FS . contains ( <STR_LIT> ) && ! FlatForGlobal ) { ToggleFeature ( <STR_LIT> ) ; FlatForGlobal = true ; } if ( ! hasFlat ( ) && ! FS . contains ( <STR_LIT> ) && FlatForGlobal ) { ToggleFeature ( <STR_LIT> ) ; FlatForGlobal = false ; } if ( MaxPrivateElementSize == <NUM_LIT> ) MaxPrivateElementSize = <NUM_LIT> ; if ( LDSBankCount == <NUM_LIT> ) LDSBankCount = <NUM_LIT> ; if ( TT . getArch ( ) == Triple :: amdgcn ) { if ( LocalMemorySize == <NUM_LIT> ) LocalMemorySize = <NUM_LIT> ; if ( ! HasMovrel && ! HasVGPRIndexMode ) HasMovrel = true ;


<s> GCNSubtarget :: GCNSubtarget ( const Triple & TT , StringRef GPU , StringRef FS , const GCNTargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , <ISA_LIT>Subtarget ( TT ) , TargetTriple ( TT ) , Gen ( SOUTHERN_ISLANDS ) , IsaVersion ( ISAVersion0_0_0 ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP64FP16Denormals ( false ) , DX10Clamp ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , CodeObjectV3 ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , TrapHandler ( false ) , DebuggerInsertNops ( false ) , DebuggerEmitPrologue ( false ) , EnableHugePrivateBuffer ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , EnableDS128 ( false ) , DumpCode ( false ) , FP64 ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , VIInsts ( false ) , GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , HasIntClamp ( false ) , HasFmaMixInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasScalarAtomics ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , HasR128A16 ( false ) , HasDLInsts ( false ) , EnableSRAMECC ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , AddNoCarryInsts ( false ) , HasUnpackedD16VMem ( false ) , ScalarizeGlobal ( false ) , FeatureDisable ( false ) , InstrInfo ( initializeSubtargetDependencies ( TT , GPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) { CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this , TM ) ) ; RegBankInfo . reset ( new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ) ; InstSelector . reset ( new <ISA_LIT>InstructionSelector ( * this , * static_cast < <ISA_LIT>RegisterBankInfo * > ( RegBankInfo . get ( ) ) , TM ) ) ;


<s> GCNSubtarget :: GCNSubtarget ( const Triple & TT , StringRef GPU , StringRef FS , const GCNTargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , <ISA_LIT>Subtarget ( TT ) , TargetTriple ( TT ) , Gen ( TT . getOS ( ) == Triple :: AMDHSA ? SEA_ISLANDS : SOUTHERN_ISLANDS ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP64FP16Denormals ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , CodeObjectV3 ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , DoesNotSupportXNACK ( false ) , EnableCuMode ( false ) , TrapHandler ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , EnableDS128 ( false ) , EnablePRTStrictNull ( false ) , DumpCode ( false ) , FP64 ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , GFX8Insts ( false ) , GFX9Insts ( false ) , GFX10Insts ( false ) , GFX7GFX8GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , HasIntClamp ( false ) , HasFmaMixInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasScalarAtomics ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , HasDPP8 ( false ) , HasR128A16 ( false ) , HasNSAEncoding ( false ) , HasDLInsts ( false ) , HasDot1Insts ( false ) , HasDot2Insts ( false ) , HasDot5Insts ( false ) , HasDot6Insts ( false ) , EnableSRAMECC ( false ) , DoesNotSupportSRAMECC ( false ) , HasNoSdstCMPX ( false ) , HasVscnt ( false ) , HasRegisterBanking ( false ) , HasVOP3Literal ( false ) , HasNoDataDepHazard ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , ScalarFlatScratchInsts ( false ) , AddNoCarryInsts ( false ) , HasUnpackedD16VMem ( false ) , LDSMisalignedBug ( false ) , ScalarizeGlobal ( false ) , HasVcmpxPermlaneHazard ( false ) , HasVMEMtoScalarWriteHazard ( false ) , HasSMEMtoVectorWriteHazard ( false ) , HasInstFwdPrefetchBug ( false ) , HasVcmpxExecWARHazard ( false ) , HasLdsBranchVmemWARHazard ( false ) , HasNSAtoVMEMBug ( false ) , HasOffset3fBug ( false ) , HasFlatSegmentOffsetBug ( false ) , FeatureDisable ( false ) , InstrInfo ( initializeSubtargetDependencies ( TT , GPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) { CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this , TM ) ) ;

RegBankInfo . reset ( new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ) ;


<s> GCNSubtarget :: GCNSubtarget ( const Triple & TT , StringRef GPU , StringRef FS , const GCNTargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , <ISA_LIT>Subtarget ( TT , getFeatureBits ( ) ) , TargetTriple ( TT ) , Gen ( SOUTHERN_ISLANDS ) , IsaVersion ( ISAVersion0_0_0 ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP64FP16Denormals ( false ) , DX10Clamp ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , CodeObjectV3 ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , TrapHandler ( false ) , DebuggerInsertNops ( false ) , DebuggerEmitPrologue ( false ) , EnableHugePrivateBuffer ( false ) , EnableVGPRSpilling ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , EnableDS128 ( false ) , DumpCode ( false ) , FP64 ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , HasIntClamp ( false ) , HasFmaMixInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasScalarAtomics ( false ) , HasInv2PiInlineImm ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , HasDLInsts ( false ) , D16PreservesUnusedBits ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , AddNoCarryInsts ( false ) , HasUnpackedD16VMem ( false ) , ScalarizeGlobal ( false ) , FeatureDisable ( false ) , InstrInfo ( initializeSubtargetDependencies ( TT , GPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) {


<s> GCNSubtarget & GCNSubtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef GPU , StringRef FS ) { SmallString < <NUM_LIT> > FullFS ( <STR_LIT> ) ; if ( isAmdHsaOS ( ) ) FullFS += <STR_LIT> ; FullFS += <STR_LIT> ; if ( FS . find_lower ( <STR_LIT> ) != StringRef :: npos ) { if ( FS . find_lower ( <STR_LIT> ) == StringRef :: npos ) FullFS += <STR_LIT> ; if ( FS . find_lower ( <STR_LIT> ) == StringRef :: npos ) FullFS += <STR_LIT> ; if ( FS . find_lower ( <STR_LIT> ) == StringRef :: npos ) FullFS += <STR_LIT> ; } FullFS += FS ; ParseSubtargetFeatures ( GPU , GPU , FullFS ) ; assert ( ! hasFP64 ( ) || ( getGeneration ( ) >= <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) ) ; if ( ! hasAddr64 ( ) && ! FS . contains ( <STR_LIT> ) ) {


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT ) : TargetTriple ( TT ) {


<s> <ISA_LIT>GenSubtargetInfo ( TT , GPU , GPU , FS ) , <ISA_LIT>Subtarget ( TT ) , TargetTriple ( TT ) , TargetID ( * this ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) , InstrInfo ( initializeSubtargetDependencies ( TT , GPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) { MaxWavesPerEU = <STR_LIT> :: getMaxWavesPerEU ( this ) ; CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ;

InlineAsmLoweringInfo . reset ( new InlineAsmLowering ( getTargetLowering ( ) ) ) ;


<s> unsigned GCNSubtarget :: getBaseReservedNumSGPRs ( const bool HasFlatScratch ) const { if ( getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) return <NUM_LIT> ; if ( HasFlatScratch || HasArchitectedFlatScratch ) {

if ( getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) return <NUM_LIT> ;


<s> unsigned <ISA_LIT>Subtarget :: getImplicitArgNumBytes ( const Function & F ) const { assert ( <STR_LIT> ( F . getCallingConv ( ) ) ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) return <NUM_LIT> ; if ( isMesaKernel ( F ) ) return <NUM_LIT> ; unsigned NBytes = ( <STR_LIT> ( ) >= <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ;

return <STR_LIT> ( F , <STR_LIT> , NBytes ) ;


<s> if ( F . hasFnAttribute ( <STR_LIT> ) ) return <NUM_LIT> ; if ( isMesaKernel ( F ) ) return <NUM_LIT> ;

unsigned NBytes = ( <STR_LIT> ( ) >= <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ;


<s> unsigned GCNSubtarget :: getReservedNumSGPRs ( const Function & F ) const { const bool KernelUsesFlatScratch = hasFlatAddressSpace ( ) ; return getBaseReservedNumSGPRs ( KernelUsesFlatScratch ) ;


<s> <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , <ISA_LIT>Subtarget ( TT ) , TargetTriple ( TT ) , Gen ( TT . getOS ( ) == Triple :: AMDHSA ? SEA_ISLANDS : SOUTHERN_ISLANDS ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP64FP16Denormals ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , CodeObjectV3 ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , DoesNotSupportXNACK ( false ) , EnableCuMode ( false ) , TrapHandler ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , EnableDS128 ( false ) , EnablePRTStrictNull ( false ) , DumpCode ( false ) , FP64 ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , GFX8Insts ( false ) , GFX9Insts ( false ) , GFX10Insts ( false ) , GFX7GFX8GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , HasIntClamp ( false ) , HasFmaMixInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasScalarAtomics ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , HasDPP8 ( false ) , HasR128A16 ( false ) , HasGFX10A16 ( false ) , HasNSAEncoding ( false ) , HasDLInsts ( false ) , HasDot1Insts ( false ) , HasDot2Insts ( false ) , HasDot3Insts ( false ) , HasDot4Insts ( false ) , HasDot5Insts ( false ) , HasDot6Insts ( false ) , HasMAIInsts ( false ) , HasPkFmacF16Inst ( false ) , HasAtomicFaddInsts ( false ) , EnableSRAMECC ( false ) , DoesNotSupportSRAMECC ( false ) , HasNoSdstCMPX ( false ) , HasVscnt ( false ) , HasRegisterBanking ( false ) , HasVOP3Literal ( false ) , HasNoDataDepHazard ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , ScalarFlatScratchInsts ( false ) , AddNoCarryInsts ( false ) , HasUnpackedD16VMem ( false ) , LDSMisalignedBug ( false ) , HasMFMAInlineLiteralBug ( false ) , ScalarizeGlobal ( false ) , HasVcmpxPermlaneHazard ( false ) , HasVMEMtoScalarWriteHazard ( false ) , HasSMEMtoVectorWriteHazard ( false ) , HasInstFwdPrefetchBug ( false ) , HasVcmpxExecWARHazard ( false ) , HasLdsBranchVmemWARHazard ( false ) , HasNSAtoVMEMBug ( false ) , HasOffset3fBug ( false ) , HasFlatSegmentOffsetBug ( false ) , FeatureDisable ( false ) , InstrInfo ( initializeSubtargetDependencies ( TT , GPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) { MaxWavesPerEU = <STR_LIT> :: getMaxWavesPerEU ( this ) ;

CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ;


<s> if ( getGeneration ( ) <= <ISA_LIT>Subtarget :: NORTHERN_ISLANDS ) { InstrInfo . reset ( new <ISA_LIT>InstrInfo ( * this ) ) ; TLInfo . reset ( new <ISA_LIT>TargetLowering ( TM , * this ) ) ; FrameLowering . reset ( new <ISA_LIT>FrameLowering ( TargetFrameLowering :: StackGrowsUp , MaxStackAlign , <NUM_LIT> ) ) ; } else { InstrInfo . reset ( new <ISA_LIT>InstrInfo ( * this ) ) ; TLInfo . reset ( new <ISA_LIT>TargetLowering ( TM , * this ) ) ; FrameLowering . reset ( new <ISA_LIT>FrameLowering ( TargetFrameLowering :: StackGrowsUp , MaxStackAlign , <NUM_LIT> ) ) ;


<s> const CallLowering * <ISA_LIT>Subtarget :: getCallLowering ( ) const {


<s> ParseSubtargetFeatures ( GPU , FullFS ) ; if ( getGeneration ( ) <= <ISA_LIT>Subtarget :: NORTHERN_ISLANDS ) { FP32Denormals = false ; FP64Denormals = false ; }

if ( MaxPrivateElementSize == <NUM_LIT> ) MaxPrivateElementSize = <NUM_LIT> ;


<s> return ! <STR_LIT> ( F . getCallingConv ( ) ) || EnableVGPRSpilling ;


<s> Policy . OnlyTopDown = false ; Policy . OnlyBottomUp = false ; if ( ! enable<ISA_LIT>Scheduler ( ) ) Policy . ShouldTrackLaneMasks = true ;


<s> FullFS += FS ; ParseSubtargetFeatures ( GPU , FullFS ) ; if ( getGeneration ( ) <= <ISA_LIT>Subtarget :: NORTHERN_ISLANDS ) { FP32Denormals = false ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef GPU , StringRef FS , TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , DevName ( GPU ) , Is64bit ( false ) , DumpCode ( false ) , <ISA_LIT>ALUInst ( false ) , HasVertexCache ( false ) , TexVTXClauseSize ( <NUM_LIT> ) , Gen ( <ISA_LIT>Subtarget :: <ISA_LIT> ) , FP64 ( false ) , FP64Denormals ( false ) , FP32Denormals ( false ) , FastFMAF32 ( false ) , CaymanISA ( false ) , FlatAddressSpace ( false ) , EnableIRStructurizer ( true ) , EnablePromoteAlloca ( false ) , EnableIfCvt ( true ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , WavefrontSize ( <NUM_LIT> ) , CFALUBug ( false ) , LocalMemorySize ( <NUM_LIT> ) , EnableVGPRSpilling ( false ) , SGPRInitBug ( false ) , IsGCN ( false ) , GCN1Encoding ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , LDSBankCount ( <NUM_LIT> ) , IsaVersion ( ISAVersion0_0_0 ) , EnableHugeScratchBuffer ( false ) , FrameLowering ( nullptr ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) , TargetTriple ( TT ) { initializeSubtargetDependencies ( TT , GPU , FS ) ; const unsigned MaxStackAlign = <NUM_LIT> * <NUM_LIT> ; if ( getGeneration ( ) <= <ISA_LIT>Subtarget :: NORTHERN_ISLANDS ) { InstrInfo . reset ( new <ISA_LIT>InstrInfo ( * this ) ) ; TLInfo . reset ( new <ISA_LIT>TargetLowering ( TM , * this ) ) ; FrameLowering . reset ( new <ISA_LIT>FrameLowering ( TargetFrameLowering :: StackGrowsUp , MaxStackAlign , <NUM_LIT> ) ) ; } else { InstrInfo . reset ( new <ISA_LIT>InstrInfo ( * this ) ) ; TLInfo . reset ( new <ISA_LIT>TargetLowering ( TM , * this ) ) ;


<s> ParseSubtargetFeatures ( GPU , FullFS ) ; if ( getGeneration ( ) <= <ISA_LIT>Subtarget :: NORTHERN_ISLANDS ) { FP32Denormals = false ; FP64Denormals = false ;


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef GPU , StringRef FS ) { SmallString < <NUM_LIT> > FullFS ( <STR_LIT> ) ; FullFS += FS ; if ( GPU == <STR_LIT> && TT . getArch ( ) == Triple :: amdgcn ) GPU = <STR_LIT> ;

ParseSubtargetFeatures ( GPU , FullFS ) ;


<s> GCNSubtarget :: GCNSubtarget ( const Triple & TT , StringRef GPU , StringRef FS , const GCNTargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , <ISA_LIT>Subtarget ( TT ) , TargetTriple ( TT ) , Gen ( TT . getOS ( ) == Triple :: AMDHSA ? SEA_ISLANDS : SOUTHERN_ISLANDS ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP64FP16Denormals ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , CodeObjectV3 ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , DoesNotSupportXNACK ( false ) , EnableCuMode ( false ) , TrapHandler ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , EnableDS128 ( false ) , EnablePRTStrictNull ( false ) , DumpCode ( false ) , FP64 ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , GFX8Insts ( false ) , GFX9Insts ( false ) , GFX10Insts ( false ) , GFX7GFX8GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , HasIntClamp ( false ) , HasFmaMixInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasScalarAtomics ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , HasR128A16 ( false ) , HasNSAEncoding ( false ) , HasDLInsts ( false ) , HasDot1Insts ( false ) , HasDot2Insts ( false ) , EnableSRAMECC ( false ) , DoesNotSupportSRAMECC ( false ) , HasNoSdstCMPX ( false ) , HasVscnt ( false ) , HasRegisterBanking ( false ) , HasVOP3Literal ( false ) , HasNoDataDepHazard ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , ScalarFlatScratchInsts ( false ) , AddNoCarryInsts ( false ) , HasUnpackedD16VMem ( false ) , LDSMisalignedBug ( false ) , ScalarizeGlobal ( false ) , HasVcmpxPermlaneHazard ( false ) , HasVMEMtoScalarWriteHazard ( false ) , HasSMEMtoVectorWriteHazard ( false ) , HasInstFwdPrefetchBug ( false ) , HasVcmpxExecWARHazard ( false ) , HasLdsBranchVmemWARHazard ( false ) , HasNSAtoVMEMBug ( false ) , HasFlatSegmentOffsetBug ( false ) , FeatureDisable ( false ) , InstrInfo ( initializeSubtargetDependencies ( TT , GPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) { CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ;

Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this , TM ) ) ;


<s> FullFS += <STR_LIT> ; FullFS += FS ; ParseSubtargetFeatures ( GPU , FullFS ) ; assert ( ! hasFP64 ( ) || ( getGeneration ( ) >= <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) ) ; if ( ! hasAddr64 ( ) && ! FS . contains ( <STR_LIT> ) ) { FlatForGlobal = true ; } if ( MaxPrivateElementSize == <NUM_LIT> ) MaxPrivateElementSize = <NUM_LIT> ; if ( LDSBankCount == <NUM_LIT> ) LDSBankCount = <NUM_LIT> ; if ( TT . getArch ( ) == Triple :: amdgcn ) { if ( LocalMemorySize == <NUM_LIT> ) LocalMemorySize = <NUM_LIT> ; if ( ! HasMovrel && ! HasVGPRIndexMode ) HasMovrel = true ; } if ( WavefrontSize == <NUM_LIT> ) WavefrontSize = <NUM_LIT> ; HasFminFmaxLegacy = getGeneration ( ) < <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ; if ( DoesNotSupportXNACK && EnableXNACK ) { ToggleFeature ( <STR_LIT> ) ; EnableXNACK = false ; } if ( DoesNotSupportSRAMECC && EnableSRAMECC ) { ToggleFeature ( <STR_LIT> ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT ) :

TargetTriple ( TT ) , GCN3Encoding ( false ) , Has16BitInsts ( false ) , HasMadMixInsts ( false ) , HasMadMacF32Insts ( false ) , HasDsSrc2Insts ( false ) , HasSDWA ( false ) , HasVOP3PInsts ( false ) , HasMulI24 ( true ) , HasMulU24 ( true ) , HasInv2PiInlineImm ( false ) , HasFminFmaxLegacy ( true ) , EnablePromoteAlloca ( false ) , HasTrigReducedRange ( false ) , MaxWavesPerEU ( <NUM_LIT> ) , LocalMemorySize ( <NUM_LIT> ) , WavefrontSizeLog2 ( <NUM_LIT> ) {


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT ) : TargetTriple ( TT ) , GCN3Encoding ( false ) , Has16BitInsts ( false ) , HasMadMixInsts ( false ) , HasMadMacF32Insts ( false ) , HasDsSrc2Insts ( false ) , HasSDWA ( false ) , HasVOP3PInsts ( false ) , HasMulI24 ( true ) , HasMulU24 ( true ) , HasInv2PiInlineImm ( false ) , HasFminFmaxLegacy ( true ) , EnablePromoteAlloca ( false ) , HasTrigReducedRange ( false ) , MaxWavesPerEU ( <NUM_LIT> ) , LocalMemorySize ( <NUM_LIT> ) , WavefrontSizeLog2 ( <NUM_LIT> ) {


<s> unsigned GCNSubtarget :: getMaxNumVGPRs ( const MachineFunction & MF ) const { const Function & F = MF . getFunction ( ) ; const <ISA_LIT>MachineFunctionInfo & MFI = * MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; std :: pair < unsigned , unsigned > WavesPerEU = MFI . getWavesPerEU ( ) ; unsigned MaxNumVGPRs = getMaxNumVGPRs ( WavesPerEU . first ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { unsigned Requested = <STR_LIT> ( F , <STR_LIT> , MaxNumVGPRs ) ; if ( hasGFX90AInsts ( ) ) Requested *= <NUM_LIT> ;

if ( Requested && Requested > getMaxNumVGPRs ( WavesPerEU . first ) ) Requested = <NUM_LIT> ;


<s> <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , <ISA_LIT>CommonSubtarget ( TT , getFeatureBits ( ) ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) , TargetTriple ( TT ) , Gen ( SOUTHERN_ISLANDS ) , IsaVersion ( ISAVersion0_0_0 ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP64FP16Denormals ( false ) , DX10Clamp ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , CodeObjectV3 ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , TrapHandler ( false ) , DebuggerInsertNops ( false ) , DebuggerEmitPrologue ( false ) , EnableHugePrivateBuffer ( false ) , EnableVGPRSpilling ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , EnableDS128 ( false ) , DumpCode ( false ) , FP64 ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , HasIntClamp ( false ) , HasFmaMixInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasScalarAtomics ( false ) , HasInv2PiInlineImm ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , HasDLInsts ( false ) , D16PreservesUnusedBits ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , AddNoCarryInsts ( false ) , HasUnpackedD16VMem ( false ) , ScalarizeGlobal ( false ) , FeatureDisable ( false ) { AS = <STR_LIT> ( TT ) ;

initializeSubtargetDependencies ( TT , GPU , FS ) ;


<s> const <ISA_LIT>CommonSubtarget & <ISA_LIT>CommonSubtarget :: get ( const TargetMachine & TM , const Function & F ) { if ( TM . getTargetTriple ( ) . getArch ( ) == Triple :: amdgcn ) return static_cast < const <ISA_LIT>CommonSubtarget & > ( TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ) ;

else return static_cast < const <ISA_LIT>CommonSubtarget & > ( TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ) ;


<s> return std :: make_pair ( getWavefrontSize ( ) * <NUM_LIT> , getWavefrontSize ( ) * <NUM_LIT> ) ; case CallingConv :: <ISA_LIT>_VS : case CallingConv :: <ISA_LIT>_LS : case CallingConv :: <ISA_LIT>_HS : case CallingConv :: <ISA_LIT>_ES :


<s> unsigned getExplicitKernelArgOffset ( const MachineFunction & MF ) const {


<s> unsigned getExplicitKernelArgOffset ( const MachineFunction & MF ) const { return <NUM_LIT> ;


<s> Default . second = <STR_LIT> ( F , <STR_LIT> , Default . second ) ; Default . first = std :: min ( Default . first , Default . second ) ; std :: pair < unsigned , unsigned > Requested = <STR_LIT> ( F , <STR_LIT> , Default ) ;

if ( Requested . first > Requested . second ) return Default ;


<s> if ( ExplicitArgBytes == - <NUM_LIT> ) ExplicitArgBytes = getExplicitKernArgSize ( F ) ; unsigned ExplicitOffset = getExplicitKernelArgOffset ( F ) ;

uint64_t TotalSize = ExplicitOffset + ExplicitArgBytes ;


<s> if ( NWaves == <NUM_LIT> ) return getLocalMemorySize ( ) ; unsigned WorkGroupSize = getFlatWorkGroupSizes ( F ) . second ;

unsigned WorkGroupsPerCu = getMaxWorkGroupsPerCU ( WorkGroupSize ) ;


<s> unsigned WorkGroupSize = getFlatWorkGroupSizes ( F ) . second ; unsigned WorkGroupsPerCu = getMaxWorkGroupsPerCU ( WorkGroupSize ) ; unsigned MaxWaves = getMaxWavesPerEU ( ) ;

return getLocalMemorySize ( ) * MaxWaves / WorkGroupsPerCu / NWaves ;


<s> unsigned MaxNumVGPRs = getMaxNumVGPRs ( WavesPerEU . first ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { unsigned Requested = <STR_LIT> ( F , <STR_LIT> , MaxNumVGPRs ) ; if ( Requested && Requested > getMaxNumVGPRs ( WavesPerEU . first ) ) Requested = <NUM_LIT> ; if ( WavesPerEU . second && Requested && Requested < getMinNumVGPRs ( WavesPerEU . second ) ) Requested = <NUM_LIT> ; if ( Requested ) MaxNumVGPRs = Requested ; } return MaxNumVGPRs ;


<s> unsigned <ISA_LIT>CommonSubtarget :: getOccupancyWithLocalMemSize ( const MachineFunction & MF ) const { const auto * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; return getOccupancyWithLocalMemSize ( MFI -> getLDSSize ( ) , MF . getFunction ( ) ) ;


<s> std :: pair < unsigned , unsigned > Requested = <STR_LIT> ( F , <STR_LIT> , Default , true ) ; if ( Requested . second && Requested . first > Requested . second ) return Default ; if ( Requested . first < getMinWavesPerEU ( ) || Requested . first > getMaxWavesPerEU ( ) ) return Default ; if ( Requested . second > getMaxWavesPerEU ( ) ) return Default ; if ( RequestedFlatWorkGroupSize && Requested . first < MinImpliedByFlatWorkGroupSize ) return Default ; return Requested ;


<s> ParseSubtargetFeatures ( GPU , FullFS ) ; assert ( ! hasFP64 ( ) || ( getGeneration ( ) >= <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) ) ; if ( ! hasAddr64 ( ) && ! FS . contains ( <STR_LIT> ) ) { FlatForGlobal = true ; } if ( MaxPrivateElementSize == <NUM_LIT> ) MaxPrivateElementSize = <NUM_LIT> ; if ( LDSBankCount == <NUM_LIT> ) LDSBankCount = <NUM_LIT> ;

if ( TT . getArch ( ) == Triple :: amdgcn ) {


<s> break ; default : break ; } if ( Dim <= <NUM_LIT> ) { if ( auto Node = Kernel -> getMetadata ( <STR_LIT> ) ) if ( Node -> getNumOperands ( ) == <NUM_LIT> ) MinSize = MaxSize = mdconst :: extract < ConstantInt > ( Node -> getOperand ( Dim ) ) -> getZExtValue ( ) ; } } } if ( ! MaxSize ) return false ; if ( IdQuery ) MinSize = <NUM_LIT> ; else ++ MaxSize ; MDBuilder MDB ( I -> getContext ( ) ) ; MDNode * MaxWorkGroupSizeRange = MDB . createRange ( APInt ( <NUM_LIT> , MinSize ) , APInt ( <NUM_LIT> , MaxSize ) ) ; I -> setMetadata ( LLVMContext :: MD_range , MaxWorkGroupSizeRange ) ;


<s> <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , <ISA_LIT>CommonSubtarget ( TT , getFeatureBits ( ) ) , InstrInfo ( * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) , FMA ( false ) , CaymanISA ( false ) , CFALUBug ( false ) , DX10Clamp ( false ) , HasVertexCache ( false ) , <ISA_LIT>ALUInst ( false ) , FP64 ( false ) , TexVTXClauseSize ( <NUM_LIT> ) , Gen ( <ISA_LIT> ) , TLInfo ( TM , initializeSubtargetDependencies ( TT , GPU , FS ) ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) , AS ( <STR_LIT> ( TT ) ) {


<s> virtual ~ <ISA_LIT>CommonSubtarget ( ) {


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const override {


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef GPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , TargetTriple ( TT ) , Gen ( TT . getArch ( ) == Triple :: amdgcn ? SOUTHERN_ISLANDS : <ISA_LIT> ) , IsaVersion ( ISAVersion0_0_0 ) , WavefrontSize ( <NUM_LIT> ) , LocalMemorySize ( <NUM_LIT> ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP32Denormals ( false ) , FP64FP16Denormals ( false ) , FPExceptions ( false ) , DX10Clamp ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , CodeObjectV3 ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , TrapHandler ( false ) , DebuggerInsertNops ( false ) , DebuggerReserveRegs ( false ) , DebuggerEmitPrologue ( false ) , EnableHugePrivateBuffer ( false ) , EnableVGPRSpilling ( false ) , EnablePromoteAlloca ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , DumpCode ( false ) , FP64 ( false ) , FMA ( false ) , MIMG_R128 ( false ) , IsGCN ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , Has16BitInsts ( false ) , HasIntClamp ( false ) , HasVOP3PInsts ( false ) , HasMadMixInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasScalarAtomics ( false ) , HasInv2PiInlineImm ( false ) , HasSDWA ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , AddNoCarryInsts ( false ) , HasUnpackedD16VMem ( false ) , <ISA_LIT>ALUInst ( false ) , CaymanISA ( false ) , CFALUBug ( false ) , HasVertexCache ( false ) , TexVTXClauseSize ( <NUM_LIT> ) , ScalarizeGlobal ( false ) , FeatureDisable ( false ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) { AS = <STR_LIT> ( TT ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef GPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , TargetTriple ( TT ) , Gen ( TT . getArch ( ) == Triple :: amdgcn ? SOUTHERN_ISLANDS : <ISA_LIT> ) , IsaVersion ( ISAVersion0_0_0 ) , WavefrontSize ( <NUM_LIT> ) , LocalMemorySize ( <NUM_LIT> ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP32Denormals ( false ) , FP64Denormals ( false ) , FPExceptions ( false ) , FlatForGlobal ( false ) , UnalignedBufferAccess ( false ) , EnableXNACK ( false ) , DebuggerInsertNops ( false ) , DebuggerReserveRegs ( false ) , DebuggerEmitPrologue ( false ) , EnableVGPRSpilling ( false ) , EnablePromoteAlloca ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , DumpCode ( false ) , FP64 ( false ) , IsGCN ( false ) , GCN1Encoding ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , Has16BitInsts ( false ) , FlatAddressSpace ( false ) , <ISA_LIT>ALUInst ( false ) , CaymanISA ( false ) , CFALUBug ( false ) , HasVertexCache ( false ) , TexVTXClauseSize ( <NUM_LIT> ) , FeatureDisable ( false ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) , T<ISA_LIT>nfo ( ) { initializeSubtargetDependencies ( TT , GPU , FS ) ;


<s> GCNSubtarget :: GCNSubtarget ( const Triple & TT , StringRef GPU , StringRef FS , const GCNTargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , <ISA_LIT>Subtarget ( TT ) , TargetTriple ( TT ) , Gen ( TT . getOS ( ) == Triple :: AMDHSA ? SEA_ISLANDS : SOUTHERN_ISLANDS ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP64FP16Denormals ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , CodeObjectV3 ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , DoesNotSupportXNACK ( false ) , EnableCuMode ( false ) , TrapHandler ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , EnableDS128 ( false ) , EnablePRTStrictNull ( false ) , DumpCode ( false ) , FP64 ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , GFX8Insts ( false ) , GFX9Insts ( false ) , GFX10Insts ( false ) , GFX7GFX8GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , HasIntClamp ( false ) , HasFmaMixInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasScalarAtomics ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , HasDPP8 ( false ) , HasR128A16 ( false ) , HasNSAEncoding ( false ) , HasDLInsts ( false ) , HasDot1Insts ( false ) , HasDot2Insts ( false ) , HasDot3Insts ( false ) , HasDot4Insts ( false ) , HasDot5Insts ( false ) , HasDot6Insts ( false ) , HasMAIInsts ( false ) , HasPkFmacF16Inst ( false ) , HasAtomicFaddInsts ( false ) , EnableSRAMECC ( false ) , DoesNotSupportSRAMECC ( false ) , HasNoSdstCMPX ( false ) , HasVscnt ( false ) , HasRegisterBanking ( false ) , HasVOP3Literal ( false ) , HasNoDataDepHazard ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , ScalarFlatScratchInsts ( false ) , AddNoCarryInsts ( false ) , HasUnpackedD16VMem ( false ) , LDSMisalignedBug ( false ) , ScalarizeGlobal ( false ) , HasVcmpxPermlaneHazard ( false ) , HasVMEMtoScalarWriteHazard ( false ) , HasSMEMtoVectorWriteHazard ( false ) , HasInstFwdPrefetchBug ( false ) , HasVcmpxExecWARHazard ( false ) , HasLdsBranchVmemWARHazard ( false ) , HasNSAtoVMEMBug ( false ) , HasOffset3fBug ( false ) , HasFlatSegmentOffsetBug ( false ) , FeatureDisable ( false ) , InstrInfo ( initializeSubtargetDependencies ( TT , GPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) {

MaxWavesPerEU = <STR_LIT> :: getMaxWavesPerEU ( this ) ;


<s> unsigned GCNSubtarget :: getOccupancyWithNumVGPRs ( unsigned VGPRs ) const { unsigned MaxWaves = getMaxWavesPerEU ( ) ; unsigned Granule = getVGPRAllocGranule ( ) ;

if ( VGPRs < Granule ) return MaxWaves ;


<s> unsigned MaxWaves = getMaxWavesPerEU ( ) ; unsigned Granule = getVGPRAllocGranule ( ) ; if ( VGPRs < Granule ) return MaxWaves ;

unsigned RoundedRegs = ( ( VGPRs + Granule - <NUM_LIT> ) / Granule ) * Granule ;


<s> Mutations . push_back ( llvm :: make_unique < FillMFMAShadowMutation > ( & InstrInfo ) ) ;


<s> Mutations . push_back ( llvm :: make_unique < MemOpClusterMutation > ( & InstrInfo ) ) ; Mutations . push_back ( llvm :: make_unique < FillMFMAShadowMutation > ( & InstrInfo ) ) ;


<s> for ( SDep & <ISA_LIT> : From -> Succs ) { SUnit * SUv = <ISA_LIT> . getSUnit ( ) ; if ( SUv != From && TII -> isVALU ( * SUv -> getInstr ( ) ) && canAddEdge ( SUv , SU ) ) SUv -> addPred ( SDep ( SU , SDep :: Artificial ) , false ) ; } for ( SDep & <ISA_LIT> : SU -> Succs ) { SUnit * Succ = <ISA_LIT> . getSUnit ( ) ; if ( Succ != SU && isSALU ( Succ ) && canAddEdge ( From , Succ ) ) Worklist . push_back ( Succ ) ; } } return Linked ;


<s> Default . first = MinImpliedByFlatWorkGroupSize ; bool RequestedFlatWorkGroupSize = F . hasFnAttribute ( <STR_LIT> ) ; std :: pair < unsigned , unsigned > Requested = <STR_LIT> ( F , <STR_LIT> , Default , true ) ; if ( Requested . second && Requested . first > Requested . second ) return Default ; if ( Requested . first < getMinWavesPerEU ( ) || Requested . second > getMaxWavesPerEU ( ) ) return Default ; if ( RequestedFlatWorkGroupSize && Requested . first < MinImpliedByFlatWorkGroupSize ) return Default ; return Requested ;


<s> unsigned MinImpliedByFlatWorkGroupSize = getWavesPerEUForWorkGroup ( FlatWorkGroupSizes . second ) ; Default . first = MinImpliedByFlatWorkGroupSize ; bool RequestedFlatWorkGroupSize = F . hasFnAttribute ( <STR_LIT> ) ; std :: pair < unsigned , unsigned > Requested = <STR_LIT> ( F , <STR_LIT> , Default , true ) ; if ( Requested . second && Requested . first > Requested . second ) return Default ; if ( Requested . first < getMinWavesPerEU ( ) || Requested . second > getMaxWavesPerEU ( ) ) return Default ; if ( RequestedFlatWorkGroupSize && Requested . first < MinImpliedByFlatWorkGroupSize ) return Default ; return Requested ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef GPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , TargetTriple ( TT ) , Gen ( TT . getArch ( ) == Triple :: amdgcn ? SOUTHERN_ISLANDS : <ISA_LIT> ) , IsaVersion ( ISAVersion0_0_0 ) , WavefrontSize ( <NUM_LIT> ) , LocalMemorySize ( <NUM_LIT> ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP32Denormals ( false ) , FP64FP16Denormals ( false ) , FPExceptions ( false ) , DX10Clamp ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , TrapHandler ( false ) , DebuggerInsertNops ( false ) , DebuggerReserveRegs ( false ) , DebuggerEmitPrologue ( false ) , EnableVGPRSpilling ( false ) , EnablePromoteAlloca ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , DumpCode ( false ) , FP64 ( false ) , IsGCN ( false ) , GCN1Encoding ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , Has16BitInsts ( false ) , HasVOP3PInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasInv2PiInlineImm ( false ) , HasSDWA ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , AddNoCarryInsts ( false ) , <ISA_LIT>ALUInst ( false ) , CaymanISA ( false ) , CFALUBug ( false ) , HasVertexCache ( false ) , TexVTXClauseSize ( <NUM_LIT> ) , ScalarizeGlobal ( false ) , FeatureDisable ( false ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) {


<s> GCNSubtarget :: GCNSubtarget ( const Triple & TT , StringRef GPU , StringRef FS , const GCNTargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , <ISA_LIT>Subtarget ( TT ) , TargetTriple ( TT ) , Gen ( TT . getOS ( ) == Triple :: AMDHSA ? SEA_ISLANDS : SOUTHERN_ISLANDS ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP64FP16Denormals ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , CodeObjectV3 ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , TrapHandler ( false ) , EnableHugePrivateBuffer ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , EnableDS128 ( false ) , EnablePRTStrictNull ( false ) , DumpCode ( false ) , FP64 ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , VIInsts ( false ) , GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , HasIntClamp ( false ) , HasFmaMixInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasScalarAtomics ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , HasR128A16 ( false ) , HasDLInsts ( false ) , HasDot1Insts ( false ) , HasDot2Insts ( false ) , EnableSRAMECC ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , AddNoCarryInsts ( false ) , HasUnpackedD16VMem ( false ) , ScalarizeGlobal ( false ) , FeatureDisable ( false ) , InstrInfo ( initializeSubtargetDependencies ( TT , GPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) {

CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ;


<s> FullFS += <STR_LIT> ; } FullFS += <STR_LIT> ; FullFS += FS ; ParseSubtargetFeatures ( GPU , FullFS ) ; assert ( ! hasFP64 ( ) || ( getGeneration ( ) >= <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) ) ; if ( ! hasAddr64 ( ) && ! FS . contains ( <STR_LIT> ) ) { FlatForGlobal = true ; } if ( MaxPrivateElementSize == <NUM_LIT> ) MaxPrivateElementSize = <NUM_LIT> ; if ( LDSBankCount == <NUM_LIT> ) LDSBankCount = <NUM_LIT> ; if ( TT . getArch ( ) == Triple :: amdgcn ) { if ( LocalMemorySize == <NUM_LIT> ) LocalMemorySize = <NUM_LIT> ; if ( ! HasMovrel && ! HasVGPRIndexMode ) HasMovrel = true ; }

if ( WavefrontSize == <NUM_LIT> ) WavefrontSize = <NUM_LIT> ;


<s> if ( MaxPrivateElementSize == <NUM_LIT> ) MaxPrivateElementSize = <NUM_LIT> ; if ( LDSBankCount == <NUM_LIT> ) LDSBankCount = <NUM_LIT> ; if ( TT . getArch ( ) == Triple :: amdgcn ) { if ( LocalMemorySize == <NUM_LIT> ) LocalMemorySize = <NUM_LIT> ; if ( ! HasMovrel && ! HasVGPRIndexMode ) HasMovrel = true ; } if ( WavefrontSize == <NUM_LIT> ) WavefrontSize = <NUM_LIT> ;

HasFminFmaxLegacy = getGeneration ( ) < <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ;


<s> <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , <ISA_LIT>Subtarget ( TT ) , TargetTriple ( TT ) , Gen ( TT . getOS ( ) == Triple :: AMDHSA ? SEA_ISLANDS : SOUTHERN_ISLANDS ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP64FP16Denormals ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , CodeObjectV3 ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , DoesNotSupportXNACK ( false ) , EnableCuMode ( false ) , TrapHandler ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , EnableDS128 ( false ) , EnablePRTStrictNull ( false ) , DumpCode ( false ) , FP64 ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , GFX8Insts ( false ) , GFX9Insts ( false ) , GFX10Insts ( false ) , GFX7GFX8GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , HasIntClamp ( false ) , HasFmaMixInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasScalarAtomics ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , HasDPP8 ( false ) , HasR128A16 ( false ) , HasNSAEncoding ( false ) , HasDLInsts ( false ) , HasDot1Insts ( false ) , HasDot2Insts ( false ) , HasDot3Insts ( false ) , HasDot4Insts ( false ) , HasDot5Insts ( false ) , HasDot6Insts ( false ) , HasMAIInsts ( false ) , HasPkFmacF16Inst ( false ) , HasAtomicFaddInsts ( false ) , EnableSRAMECC ( false ) , DoesNotSupportSRAMECC ( false ) , HasNoSdstCMPX ( false ) , HasVscnt ( false ) , HasRegisterBanking ( false ) , HasVOP3Literal ( false ) , HasNoDataDepHazard ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , ScalarFlatScratchInsts ( false ) , AddNoCarryInsts ( false ) , HasUnpackedD16VMem ( false ) , LDSMisalignedBug ( false ) , HasMFMAInlineLiteralBug ( false ) , ScalarizeGlobal ( false ) , HasVcmpxPermlaneHazard ( false ) , HasVMEMtoScalarWriteHazard ( false ) , HasSMEMtoVectorWriteHazard ( false ) , HasInstFwdPrefetchBug ( false ) , HasVcmpxExecWARHazard ( false ) , HasLdsBranchVmemWARHazard ( false ) , HasNSAtoVMEMBug ( false ) , HasOffset3fBug ( false ) , HasFlatSegmentOffsetBug ( false ) , FeatureDisable ( false ) , InstrInfo ( initializeSubtargetDependencies ( TT , GPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) {


<s> return <STR_LIT> :: getMaxWavesPerEU ( this ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const FeatureBitset & FeatureBits ) : TargetTriple ( TT ) , SubtargetFeatureBits ( FeatureBits ) , Has16BitInsts ( false ) , HasMadMixInsts ( false ) , FP32Denormals ( false ) , FPExceptions ( false ) , HasSDWA ( false ) , HasVOP3PInsts ( false ) , HasMulI24 ( true ) , HasMulU24 ( true ) , HasFminFmaxLegacy ( true ) , EnablePromoteAlloca ( false ) , LocalMemorySize ( <NUM_LIT> ) , WavefrontSize ( <NUM_LIT> ) {


<s> for ( const SDep & <ISA_LIT> : SU . Preds ) { if ( <ISA_LIT> . getSUnit ( ) != SUa ) SUa -> addPred ( SDep ( <ISA_LIT> . getSUnit ( ) , SDep :: Artificial ) ) ; } if ( & SU != & DAG -> ExitSU ) { for ( const SDep & <ISA_LIT> : SUa -> Succs ) { if ( <ISA_LIT> . getSUnit ( ) != & SU ) <ISA_LIT> . getSUnit ( ) -> addPred ( SDep ( & SU , SDep :: Artificial ) ) ;


<s> bool d16PreservesUnusedBits ( ) const { return D16PreservesUnusedBits ;


<s> bool debuggerEmitPrologue ( ) const {


<s> bool debuggerInsertNops ( ) const { return DebuggerInsertNops ;


<s> return debuggerInsertNops ( ) && debuggerEmitPrologue ( ) ;


<s> bool enableEarlyIfConversion ( ) const override {


<s> bool enable<ISA_LIT>Scheduler ( ) const {


<s> bool flatScratchIsPointer ( ) const { return getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX9 ;


<s> GCNSubtarget :: GCNSubtarget ( const Triple & TT , StringRef GPU , StringRef FS , const GCNTargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , <ISA_LIT>Subtarget ( TT , getFeatureBits ( ) ) , TargetTriple ( TT ) , Gen ( SOUTHERN_ISLANDS ) , IsaVersion ( ISAVersion0_0_0 ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP64FP16Denormals ( false ) , DX10Clamp ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , CodeObjectV3 ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , TrapHandler ( false ) , DebuggerInsertNops ( false ) , DebuggerEmitPrologue ( false ) , EnableHugePrivateBuffer ( false ) , EnableVGPRSpilling ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , EnableDS128 ( false ) , DumpCode ( false ) , FP64 ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , VIInsts ( false ) , GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , HasIntClamp ( false ) , HasFmaMixInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasScalarAtomics ( false ) , HasInv2PiInlineImm ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , HasDLInsts ( false ) , D16PreservesUnusedBits ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , AddNoCarryInsts ( false ) , HasUnpackedD16VMem ( false ) , ScalarizeGlobal ( false ) , FeatureDisable ( false ) , InstrInfo ( initializeSubtargetDependencies ( TT , GPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) { AS = <STR_LIT> ( TT ) ; CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ;


<s> GCNSubtarget :: GCNSubtarget ( const Triple & TT , StringRef GPU , StringRef FS , const GCNTargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , <ISA_LIT>Subtarget ( TT , getFeatureBits ( ) ) , TargetTriple ( TT ) , Gen ( SOUTHERN_ISLANDS ) , IsaVersion ( ISAVersion0_0_0 ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP64FP16Denormals ( false ) , DX10Clamp ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , CodeObjectV3 ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , TrapHandler ( false ) , DebuggerInsertNops ( false ) , DebuggerEmitPrologue ( false ) , EnableHugePrivateBuffer ( false ) , EnableVGPRSpilling ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , EnableDS128 ( false ) , DumpCode ( false ) , FP64 ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , VIInsts ( false ) , GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , HasIntClamp ( false ) , HasFmaMixInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasScalarAtomics ( false ) , HasInv2PiInlineImm ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , HasDLInsts ( false ) , D16PreservesUnusedBits ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , AddNoCarryInsts ( false ) , HasUnpackedD16VMem ( false ) , ScalarizeGlobal ( false ) , FeatureDisable ( false ) , InstrInfo ( initializeSubtargetDependencies ( TT , GPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) {


<s> const <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: get ( const TargetMachine & TM , const Function & F ) { if ( TM . getTargetTriple ( ) . getArch ( ) == Triple :: amdgcn ) return static_cast < const <ISA_LIT>Subtarget & > ( TM . getSubtarget < GCNSubtarget > ( F ) ) ;

else return static_cast < const <ISA_LIT>Subtarget & > ( TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ) ;


<s> return <STR_LIT> :: getAddressableNumSGPRs ( MCSubtargetInfo :: getFeatureBits ( ) ) ;


<s> return isAmdHsaOS ( ) ? <NUM_LIT> : <NUM_LIT> ;


<s> <ISA_LIT>AS get<ISA_LIT>AS ( ) const {


<s> case CallingConv :: <ISA_LIT>_LS : case CallingConv :: <ISA_LIT>_HS : case CallingConv :: <ISA_LIT>_ES : case CallingConv :: <ISA_LIT>_GS : case CallingConv :: <ISA_LIT>_PS : return std :: make_pair ( <NUM_LIT> , getWavefrontSize ( ) ) ; default : return std :: make_pair ( <NUM_LIT> , <NUM_LIT> * getWavefrontSize ( ) ) ; }


<s> return <STR_LIT> :: getEUsPerCU ( MCSubtargetInfo :: getFeatureBits ( ) ) ;


<s> MaxAlign = <NUM_LIT> ; for ( const Argument & Arg : F . args ( ) ) { Type * ArgTy = Arg . getType ( ) ; unsigned Align = DL . getABITypeAlignment ( ArgTy ) ; uint64_t AllocSize = DL . getTypeAllocSize ( ArgTy ) ; ExplicitArgBytes = alignTo ( ExplicitArgBytes , Align ) + AllocSize ; MaxAlign = std :: max ( MaxAlign , Align ) ; }


<s> const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; uint64_t ExplicitArgBytes = <NUM_LIT> ; MaxAlign = <NUM_LIT> ; for ( const Argument & Arg : F . args ( ) ) { Type * ArgTy = Arg . getType ( ) ;

unsigned Align = DL . getABITypeAlignment ( ArgTy ) ;


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const override { return & FrameLowering ;


<s> Generation getGeneration ( ) const {


<s> Generation getGeneration ( ) const { return ( Generation ) Gen ;


<s> if ( isMesaKernel ( F ) ) return <NUM_LIT> ; return <STR_LIT> ( F , <STR_LIT> , <NUM_LIT> ) ;


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ;


<s> const InstructionSelector * getInstructionSelector ( ) const override {


<s> unsigned ImplicitBytes = getImplicitArgNumBytes ( F ) ; if ( ImplicitBytes != <NUM_LIT> ) { unsigned Alignment = getAlignmentForImplicitArgPtr ( ) ; TotalSize = alignTo ( ExplicitArgBytes , Alignment ) + ImplicitBytes ;


<s> const LegalizerInfo * getLegalizerInfo ( ) const override {


<s> unsigned getMaxFlatWorkGroupSize ( ) const {

return <STR_LIT> :: getMaxFlatWorkGroupSize ( SubtargetFeatureBits ) ;


<s> unsigned WorkGroupSize = getFlatWorkGroupSizes ( F ) . second ; unsigned WorkGroupsPerCu = getMaxWorkGroupsPerCU ( WorkGroupSize ) ; unsigned MaxWaves = getMaxWavesPerEU ( ) ;


<s> unsigned getMaxNumSGPRs ( unsigned WavesPerEU , bool Addressable ) const { return <STR_LIT> :: getMaxNumSGPRs ( MCSubtargetInfo :: getFeatureBits ( ) , WavesPerEU , Addressable ) ;


<s> unsigned getMaxNumVGPRs ( unsigned WavesPerEU ) const {

return <STR_LIT> :: getMaxNumVGPRs ( MCSubtargetInfo :: getFeatureBits ( ) , WavesPerEU ) ;


<s> unsigned getMaxPrivateElementSize ( ) const { return MaxPrivateElementSize ;


<s> return <STR_LIT> :: getMaxWavesPerCU ( MCSubtargetInfo :: getFeatureBits ( ) , FlatWorkGroupSize ) ;


<s> unsigned getMaxWavesPerEU ( ) const { return <STR_LIT> :: getMaxWavesPerEU ( ) ;


<s> return <STR_LIT> :: getMaxWavesPerEU ( ) ;


<s> unsigned getMaxWorkGroupsPerCU ( unsigned FlatWorkGroupSize ) const { return <STR_LIT> :: getMaxWorkGroupsPerCU ( SubtargetFeatureBits , FlatWorkGroupSize ) ;


<s> unsigned getMinNumSGPRs ( unsigned WavesPerEU ) const { return <STR_LIT> :: getMinNumSGPRs ( MCSubtargetInfo :: getFeatureBits ( ) , WavesPerEU ) ;


<s> unsigned getMinNumVGPRs ( unsigned WavesPerEU ) const {

return <STR_LIT> :: getMinNumVGPRs ( MCSubtargetInfo :: getFeatureBits ( ) , WavesPerEU ) ;


<s> return <STR_LIT> :: getMinWavesPerEU ( SubtargetFeatureBits ) ;


<s> unsigned <ISA_LIT>Subtarget :: getOccupancyWithLocalMemSize ( const MachineFunction & MF ) const { const auto * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;

return getOccupancyWithLocalMemSize ( MFI -> getLDSSize ( ) , MF . getFunction ( ) ) ;


<s> unsigned GCNSubtarget :: getOccupancyWithNumSGPRs ( unsigned SGPRs ) const { if ( getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { if ( SGPRs <= <NUM_LIT> ) return <NUM_LIT> ; if ( SGPRs <= <NUM_LIT> ) return <NUM_LIT> ; if ( SGPRs <= <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> if ( VGPRs <= <NUM_LIT> ) return <NUM_LIT> ; if ( VGPRs <= <NUM_LIT> ) return <NUM_LIT> ; if ( VGPRs <= <NUM_LIT> ) return <NUM_LIT> ;


<s> if ( VGPRs <= <NUM_LIT> ) return <NUM_LIT> ; if ( VGPRs <= <NUM_LIT> ) return <NUM_LIT> ; if ( VGPRs <= <NUM_LIT> ) return <NUM_LIT> ; if ( VGPRs <= <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> void GCNSubtarget :: getPostRAMutations ( std :: vector < std :: unique_ptr < ScheduleDAGMutation >> & Mutations ) const {

Mutations . push_back ( llvm :: make_unique < MemOpClusterMutation > ( & InstrInfo ) ) ;


<s> Mutations . push_back ( llvm :: make_unique < MemOpClusterMutation > ( & InstrInfo ) ) ;


<s> const RegisterBankInfo * getRegBankInfo ( ) const override {


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ;


<s> if ( getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) return <NUM_LIT> ; if ( getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS ) return <NUM_LIT> ; } if ( isXNACKEnabled ( ) ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> if ( getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS ) return <NUM_LIT> ; } if ( isXNACKEnabled ( ) ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> unsigned getSGPREncodingGranule ( ) const {

return <STR_LIT> :: getSGPREncodingGranule ( MCSubtargetInfo :: getFeatureBits ( ) ) ;


<s> unsigned getStackAlignment ( ) const {


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override {


<s> return <STR_LIT> :: getTotalNumSGPRs ( MCSubtargetInfo :: getFeatureBits ( ) ) ;


<s> return <STR_LIT> :: getTotalNumVGPRs ( MCSubtargetInfo :: getFeatureBits ( ) ) ;


<s> TrapHandlerAbi getTrapHandlerAbi ( ) const { return isAmdHsaOS ( ) ? TrapHandlerAbiHsa : TrapHandlerAbiNone ;


<s> return isAmdHsaOS ( ) ? TrapHandlerAbiHsa : TrapHandlerAbiNone ;


<s> unsigned getVGPRAllocGranule ( ) const { return <STR_LIT> :: getVGPRAllocGranule ( MCSubtargetInfo :: getFeatureBits ( ) ) ;


<s> return <STR_LIT> :: getVGPRAllocGranule ( MCSubtargetInfo :: getFeatureBits ( ) ) ;


<s> unsigned getVGPREncodingGranule ( ) const {

return <STR_LIT> :: getVGPREncodingGranule ( MCSubtargetInfo :: getFeatureBits ( ) ) ;


<s> unsigned getWavefrontSizeLog2 ( ) const {


<s> std :: pair < unsigned , unsigned > Default ( <NUM_LIT> , getMaxWavesPerEU ( ) ) ; std :: pair < unsigned , unsigned > FlatWorkGroupSizes = getFlatWorkGroupSizes ( F ) ; unsigned MinImpliedByFlatWorkGroupSize = getMaxWavesPerEU ( FlatWorkGroupSizes . second ) ; bool RequestedFlatWorkGroupSize = false ; if ( F . hasFnAttribute ( <STR_LIT> ) || F . hasFnAttribute ( <STR_LIT> ) ) { Default . first = MinImpliedByFlatWorkGroupSize ; RequestedFlatWorkGroupSize = true ; } std :: pair < unsigned , unsigned > Requested = <STR_LIT> ( F , <STR_LIT> , Default , true ) ;

if ( Requested . second && Requested . first > Requested . second ) return Default ;


<s> std :: pair < unsigned , unsigned > FlatWorkGroupSizes = getFlatWorkGroupSizes ( F ) ; unsigned MinImpliedByFlatWorkGroupSize = getMaxWavesPerEU ( FlatWorkGroupSizes . second ) ; bool RequestedFlatWorkGroupSize = false ; if ( F . hasFnAttribute ( <STR_LIT> ) || F . hasFnAttribute ( <STR_LIT> ) ) { Default . first = MinImpliedByFlatWorkGroupSize ;


<s> return <STR_LIT> :: getWavesPerWorkGroup ( MCSubtargetInfo :: getFeatureBits ( ) , FlatWorkGroupSize ) ;


<s> return getGeneration ( ) != <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ;


<s> bool has16BitInsts ( ) const { return Has16BitInsts ;


<s> return ( getGeneration ( ) < <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) ;


return ( getGeneration ( ) < <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) ;


<s> bool hasApertureRegs ( ) const { return HasApertureRegs ;


<s> bool hasAutoWaitcntBeforeBarrier ( ) const {


<s> bool hasBCNT ( unsigned Size ) const {

if ( Size == <NUM_LIT> ) return ( getGeneration ( ) >= EVERGREEN ) ;


<s> bool hasBCNT ( unsigned Size ) const { if ( Size == <NUM_LIT> ) return ( getGeneration ( ) >= EVERGREEN ) ; return false ;


<s> bool hasDPP ( ) const { return HasDPP ;


<s> bool hasFFBH ( ) const { return true ;


<s> bool hasFlatInstOffsets ( ) const { return FlatInstOffsets ;


<s> bool hasFlatLgkmVMemCountInOrder ( ) const { return getGeneration ( ) > GFX9 ;


<s> bool hasFlatLgkmVMemCountInOrder ( ) const {


<s> bool hasFlatScratchInsts ( ) const { return FlatScratchInsts ;


<s> bool hasFmaMixInsts ( ) const { return HasFmaMixInsts ;


<s> bool hasFP16Denormals ( ) const { return FP64FP16Denormals ;


<s> bool hasFP64 ( ) const { return FP64 ;


<s> bool hasInv2PiInlineImm ( ) const { return HasInv2PiInlineImm ;


<s> bool hasMad64_32 ( ) const { return getGeneration ( ) >= SEA_ISLANDS ;


<s> return getGeneration ( ) >= SEA_ISLANDS ;


<s> bool hasMed3_16 ( ) const { return getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX9 ;


<s> bool hasMergedShaders ( ) const { return getGeneration ( ) >= GFX9 ;


<s> bool hasMIMG_R128 ( ) const { return MIMG_R128 ;


<s> bool hasReadM0SendMsgHazard ( ) const { return getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ;


<s> bool hasScalarCompareEq64 ( ) const { return getGeneration ( ) >= VOLCANIC_ISLANDS ;


<s> bool hasScalarStores ( ) const { return HasScalarStores ;


<s> bool hasSDWAMac ( ) const { return HasSDWAMac ;


<s> bool hasSDWAOutModsVOPC ( ) const { return HasSDWAOutModsVOPC ;


return getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX9 ;


<s> bool hasUnalignedBufferAccess ( ) const {


<s> bool hasUnalignedScratchAccess ( ) const {


<s> bool hasVGPRIndexMode ( ) const { return HasVGPRIndexMode ;


<s> bool hasVOP3PInsts ( ) const { return HasVOP3PInsts ;


<s> GCNSubtarget & GCNSubtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef GPU , StringRef FS ) { SmallString < <NUM_LIT> > FullFS ( <STR_LIT> ) ; if ( isAmdHsaOS ( ) ) FullFS += <STR_LIT> ; if ( getGeneration ( ) >= <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) { FullFS += <STR_LIT> ; } else { FullFS += <STR_LIT> ; } FullFS += FS ; ParseSubtargetFeatures ( GPU , FullFS ) ; assert ( ! hasFP64 ( ) || ( getGeneration ( ) >= <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) ) ; if ( ! hasAddr64 ( ) && ! FS . contains ( <STR_LIT> ) ) { FlatForGlobal = true ; } if ( MaxPrivateElementSize == <NUM_LIT> ) MaxPrivateElementSize = <NUM_LIT> ; if ( LDSBankCount == <NUM_LIT> ) LDSBankCount = <NUM_LIT> ; if ( TT . getArch ( ) == Triple :: amdgcn ) {

if ( LocalMemorySize == <NUM_LIT> ) LocalMemorySize = <NUM_LIT> ;


<s> bool isAmdCodeObjectV2 ( const Function & F ) const { return isAmdHsaOS ( ) || isMesaKernel ( F ) ;


<s> bool isAmdPalOS ( ) const { return TargetTriple . getOS ( ) == Triple :: AMDPAL ;


return TargetTriple . getOS ( ) == Triple :: Mesa3D ;


<s> return TargetTriple . getOS ( ) == Triple :: Mesa3D ;


<s> bool isMesaKernel ( const Function & F ) const {

return isMesa3DOS ( ) && ! <STR_LIT> ( F . getCallingConv ( ) ) ;


<s> bool isMesaKernel ( const Function & F ) const { return isMesa3DOS ( ) && ! <STR_LIT> ( F . getCallingConv ( ) ) ;


<s> return EnableVGPRSpilling || ! <STR_LIT> ( F . getCallingConv ( ) ) ;


<s> unsigned Dim = UINT_MAX ; switch ( F -> getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : IdQuery = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Dim = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : IdQuery = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Dim = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : IdQuery = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Dim = <NUM_LIT> ; break ; default : break ; } if ( Dim <= <NUM_LIT> ) {

if ( auto Node = Kernel -> getMetadata ( <STR_LIT> ) ) if ( Node -> getNumOperands ( ) == <NUM_LIT> ) MinSize = MaxSize = mdconst :: extract < ConstantInt > ( Node -> getOperand ( Dim ) ) -> getZExtValue ( ) ;


<s> unsigned MaxSize = getFlatWorkGroupSizes ( * Kernel ) . second ; bool IdQuery = false ; if ( auto * CI = dyn_cast < CallInst > ( I ) ) { const Function * F = CI -> getCalledFunction ( ) ; if ( F ) { unsigned Dim = UINT_MAX ; switch ( F -> getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : IdQuery = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Dim = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : IdQuery = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Dim = <NUM_LIT> ; break ;


<s> MemOpClusterMutation ( const <ISA_LIT>InstrInfo * tii ) : TII ( tii ) {


<s> if ( ! enable<ISA_LIT>Scheduler ( ) ) Policy . ShouldTrackLaneMasks = true ;


<s> bool privateMemoryResourceIsRangeChecked ( ) const {

return getGeneration ( ) < <ISA_LIT>Subtarget :: GFX9 ;


<s> <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , <ISA_LIT>Subtarget ( TT , getFeatureBits ( ) ) , InstrInfo ( * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) , FMA ( false ) , CaymanISA ( false ) , CFALUBug ( false ) , DX10Clamp ( false ) , HasVertexCache ( false ) , <ISA_LIT>ALUInst ( false ) , FP64 ( false ) , TexVTXClauseSize ( <NUM_LIT> ) , Gen ( <ISA_LIT> ) , TLInfo ( TM , initializeSubtargetDependencies ( TT , GPU , FS ) ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) , AS ( <STR_LIT> ( TT ) ) {


<s> bool useDS128 ( ) const { return CIInsts && EnableDS128 ;


<s> bool useVGPRIndexMode ( bool UserEnable ) const { return ! hasMovrel ( ) || ( UserEnable && hasVGPRIndexMode ( ) ) ;


<s> return ! hasMovrel ( ) || ( UserEnable && hasVGPRIndexMode ( ) ) ;


<s> bool vmemWriteNeedsExpWaitcnt ( ) const { return getGeneration ( ) < SEA_ISLANDS ;


<s> static Target The<ISA_LIT>Target ; return The<ISA_LIT>Target ;


<s> Target & llvm :: getTheGCNTarget ( ) {


<s> RegisterTarget < Triple :: amdgcn , false > GCN ( getTheGCNTarget ( ) , <STR_LIT> , <STR_LIT> ) ;


<s> RegisterTarget < Triple :: amdgcn , false > GCN ( TheGCNTarget , <STR_LIT> , <STR_LIT> ) ;


<s> RegisterTarget < Triple :: r600 , false > <ISA_LIT> ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: amdgcn , false > GCN ( TheGCNTarget , <STR_LIT> , <STR_LIT> ) ;


<s> RegisterTarget < Triple :: r600 , false > <ISA_LIT> ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;

RegisterTarget < Triple :: amdgcn , false > GCN ( getTheGCNTarget ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> RegisterTarget < Triple :: amdgcn , false > GCN ( getTheGCNTarget ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> if ( getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createGVNPass ( ) ) ;

else addPass ( createEarlyCSEPass ( ) ) ;


<s> void <ISA_LIT>PassConfig :: addEarlyCSEOrGVNPass ( ) { if ( getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createGVNPass ( ) ) ;


<s> insertPass ( & TwoAddressInstructionPassID , & <ISA_LIT>WholeQuadModeID ) ; insertPass ( & TwoAddressInstructionPassID , & <ISA_LIT>PreAllocateWWMRegsID ) ;

TargetPassConfig :: addFastRegAlloc ( ) ;


<s> void GCNPassConfig :: addFastRegAlloc ( ) {

insertPass ( & PHIEliminationID , & <ISA_LIT>LowerControlFlowID ) ;


<s> bool GCNPassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( getOptLevel ( ) ) ) ; return false ;


<s> TargetPassConfig :: addILPOpts ( ) ; return false ;


<s> TargetPassConfig :: addILPOpts ( ) ;


<s> <ISA_LIT>PassConfig :: addInstSelector ( ) ; addPass ( & <ISA_LIT>FixSGPRCopiesID ) ;

addPass ( create<ISA_LIT>LowerI1CopiesPass ( ) ) ;


<s> bool GCNPassConfig :: addInstSelector ( ) { <ISA_LIT>PassConfig :: addInstSelector ( ) ; addPass ( & <ISA_LIT>FixSGPRCopiesID ) ; addPass ( create<ISA_LIT>LowerI1CopiesPass ( ) ) ; return false ;


<s> bool GCNPassConfig :: addLegalizeMachineIR ( ) { addPass ( new Legalizer ( ) ) ; return false ;


<s> addPass ( new Legalizer ( ) ) ; return false ;


<s> if ( isPassEnabled ( EnableSDWAPeephole ) ) { addPass ( & <ISA_LIT>PeepholeSDWAID ) ; addPass ( & EarlyMachineLICMID ) ; addPass ( & MachineCSEID ) ;


<s> addPass ( & MachineCSEID ) ; addPass ( & <ISA_LIT>FoldOperandsID ) ; } addPass ( & DeadMachineInstructionElimID ) ; addPass ( create<ISA_LIT>ShrinkInstructionsPass ( ) ) ;


<s> if ( isPassEnabled ( EnablePreRAOptimizations ) ) insertPass ( & RenameIndependentSubregsID , & GCNPreRAOptimizationsID ) ; if ( TM -> getOptLevel ( ) > CodeGenOpt :: Less ) insertPass ( & MachineSchedulerID , & <ISA_LIT>FormMemoryClausesID ) ; if ( OptVGPRLiveRange ) insertPass ( & LiveVariablesID , & <ISA_LIT>OptimizeVGPRLiveRangeID ) ; insertPass ( & PHIEliminationID , & <ISA_LIT>LowerControlFlowID ) ; if ( EnableDCEInRA ) insertPass ( & DetectDeadLanesID , & DeadMachineInstructionElimID ) ; TargetPassConfig :: addOptimizedRegAlloc ( ) ;


<s> if ( getOptLevel ( ) > CodeGenOpt :: None ) addPass ( & <ISA_LIT>OptimizeExecMaskingID ) ;

TargetPassConfig :: addPostRegAlloc ( ) ;


<s> if ( TM -> getOptLevel ( ) > CodeGenOpt :: None ) addPass ( create<ISA_LIT>ShrinkInstructionsPass ( ) ) ; addPass ( create<ISA_LIT>ModeRegisterPass ( ) ) ; if ( getOptLevel ( ) > CodeGenOpt :: None ) addPass ( & <ISA_LIT>InsertHardClausesID ) ;

addPass ( & <ISA_LIT>LateBranchLoweringPassID ) ;


<s> if ( ! LateCFGStructurize ) { if ( EnableStructurizerWorkarounds ) { addPass ( createFixIrreduciblePass ( ) ) ; addPass ( createUnifyLoopExitsPass ( ) ) ; } addPass ( createStructurizeCFGPass ( false ) ) ; } addPass ( create<ISA_LIT>AnnotateUniformValues ( ) ) ; if ( ! LateCFGStructurize ) {

addPass ( create<ISA_LIT>AnnotateControlFlowPass ( ) ) ;


<s> bool IsOptNone = getOptLevel ( ) == CodeGenOpt :: None ;

addPass ( create<ISA_LIT>PreLegalizeCombiner ( IsOptNone ) ) ;


<s> void GCNPassConfig :: addPreRegBankSelect ( ) { bool IsOptNone = getOptLevel ( ) == CodeGenOpt :: None ;

addPass ( create<ISA_LIT>PostLegalizeCombiner ( IsOptNone ) ) ;


<s> void GCNPassConfig :: addPreRegBankSelect ( ) {

bool IsOptNone = getOptLevel ( ) == CodeGenOpt :: None ;


<s> bool GCNPassConfig :: addPreRewrite ( ) {

if ( EnableRegReassign ) addPass ( & GCNNSAReassignID ) ;


<s> void GCNPassConfig :: addPreSched2 ( ) {

addPass ( & <ISA_LIT>PostRABundlerID ) ;


<s> if ( ! usingDefaultRegAlloc ( ) ) report_fatal_error ( RegAllocOptNotSupportedMessage ) ;

addPass ( createSGPRAllocPass ( false ) ) ;


<s> addPass ( & <ISA_LIT>LowerSGPRSpillsID ) ; addPass ( createVGPRAllocPass ( false ) ) ;


<s> addPass ( createVirtRegRewriter ( false ) ) ; addPass ( & <ISA_LIT>LowerSGPRSpillsID ) ;

addPass ( createVGPRAllocPass ( true ) ) ;


<s> bool GCNPassConfig :: addRegAssignAndRewriteOptimized ( ) { if ( ! usingDefaultRegAlloc ( ) ) report_fatal_error ( RegAllocOptNotSupportedMessage ) ; addPass ( createSGPRAllocPass ( true ) ) ; addPass ( createVirtRegRewriter ( false ) ) ; addPass ( & <ISA_LIT>LowerSGPRSpillsID ) ;


<s> bool GCNPassConfig :: addRegBankSelect ( ) { addPass ( new RegBankSelect ( ) ) ;


<s> addEarlyCSEOrGVNPass ( ) ; addPass ( createNaryReassociatePass ( ) ) ; addPass ( createEarlyCSEPass ( ) ) ;


<s> Builder . DivergentTarget = true ; bool EnableOpt = getOptLevel ( ) > CodeGenOpt :: None ; bool Internalize = InternalizeSymbols ; bool EarlyInline = EarlyInlineAll && EnableOpt && ! EnableFunctionCalls ; bool <ISA_LIT>AA = Enable<ISA_LIT>AliasAnalysis && EnableOpt ; bool LibCallSimplify = EnableLibCallSimplify && EnableOpt ; bool PromoteKernelArguments = EnablePromoteKernelArguments && getOptLevel ( ) > CodeGenOpt :: Less ; if ( EnableFunctionCalls ) { delete Builder . Inliner ; Builder . Inliner = createFunctionInliningPass ( ) ; } Builder . addExtension ( PassManagerBuilder :: EP_ModuleOptimizerEarly , [ Internalize , EarlyInline , <ISA_LIT>AA , this ] ( const PassManagerBuilder & , legacy :: PassManagerBase & PM ) { if ( <ISA_LIT>AA ) { PM . add ( create<ISA_LIT>AAWrapperPass ( ) ) ; PM . add ( create<ISA_LIT>ExternalAAWrapperPass ( ) ) ; }

PM . add ( create<ISA_LIT>UnifyMetadataPass ( ) ) ;


<s> disablePass ( & FuncletLayoutID ) ; disablePass ( & GCLoweringID ) ;

disablePass ( & ShadowStackGCLoweringID ) ;


<s> static StringRef computeDataLayout ( const Triple & TT ) { if ( TT . getArch ( ) == Triple :: r600 ) {


<s> static StringRef computeDataLayout ( const Triple & TT ) { if ( TT . getArch ( ) == Triple :: r600 ) { return <STR_LIT> <STR_LIT> ;


<s> const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;

return new yaml :: <ISA_LIT>MachineFunctionInfo ( * MFI , * MF . getSubtarget ( ) . getRegisterInfo ( ) , MF ) ;


<s> static FunctionPass * createBasicSGPRRegisterAllocator ( ) { return createBasicRegisterAllocator ( onlyAllocateSGPRs ) ;


<s> return createBasicRegisterAllocator ( onlyAllocateVGPRs ) ;


<s> yaml :: MachineFunctionInfo * GCNTargetMachine :: createDefaultFuncInfoYAML ( ) const { return new yaml :: <ISA_LIT>MachineFunctionInfo ( ) ;


<s> return new yaml :: <ISA_LIT>MachineFunctionInfo ( ) ;


<s> static FunctionPass * createFastVGPRRegisterAllocator ( ) {

return createFastRegisterAllocator ( onlyAllocateVGPRs , true ) ;


<s> return createGreedyRegisterAllocator ( onlyAllocateSGPRs ) ;


<s> static FunctionPass * createGreedySGPRRegisterAllocator ( ) { return createGreedyRegisterAllocator ( onlyAllocateSGPRs ) ;


<s> static FunctionPass * createGreedyVGPRRegisterAllocator ( ) {

return createGreedyRegisterAllocator ( onlyAllocateVGPRs ) ;


<s> auto DAG = new GCNIterativeScheduler ( C , GCNIterativeScheduler :: SCHEDULE_LEGACYMAXOCCUPANCY ) ; DAG -> addMutation ( createLoadClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ;


<s> auto DAG = new GCNIterativeScheduler ( C , GCNIterativeScheduler :: SCHEDULE_ILP ) ;

DAG -> addMutation ( createLoadClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ;


<s> ScheduleDAGInstrs * GCNPassConfig :: createMachineScheduler ( MachineSchedContext * C ) const { const GCNSubtarget & ST = C -> MF -> getSubtarget < GCNSubtarget > ( ) ; if ( ST . enable<ISA_LIT>Scheduler ( ) ) return create<ISA_LIT>MachineScheduler ( C ) ;

return createGCNMaxOccupancyMachineScheduler ( C ) ;


<s> const GCNSubtarget & ST = C -> MF -> getSubtarget < GCNSubtarget > ( ) ; if ( ST . enable<ISA_LIT>Scheduler ( ) ) return create<ISA_LIT>MachineScheduler ( C ) ;


<s> static ScheduleDAGInstrs * createMinRegScheduler ( MachineSchedContext * C ) {

return new GCNIterativeScheduler ( C , GCNIterativeScheduler :: SCHEDULE_MINREGFORCED ) ;


<s> static ScheduleDAGInstrs * createMinRegScheduler ( MachineSchedContext * C ) { return new GCNIterativeScheduler ( C , GCNIterativeScheduler :: SCHEDULE_MINREGFORCED ) ;


<s> TargetPassConfig * GCNTargetMachine :: createPassConfig ( PassManagerBase & PM ) {

return new GCNPassConfig ( * this , PM ) ;


<s> DAG -> addMutation ( createLoadClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; DAG -> addMutation ( ST . createFillMFMAShadowMutation ( DAG -> TII ) ) ;


<s> RegisterRegAlloc :: FunctionPassCtor Ctor = SGPRRegisterRegAlloc :: getDefault ( ) ; if ( Ctor != useDefaultRegisterAllocator ) return Ctor ( ) ; if ( Optimized ) return createGreedyRegisterAllocator ( onlyAllocateSGPRs ) ;

return createFastRegisterAllocator ( onlyAllocateSGPRs , false ) ;


if ( Optimized ) return createGreedyRegisterAllocator ( onlyAllocateSGPRs ) ;


<s> static ScheduleDAGInstrs * create<ISA_LIT>MachineScheduler ( MachineSchedContext * C ) {

return new <ISA_LIT>ScheduleDAGMI ( C ) ;


return createFastVGPRRegisterAllocator ( ) ;


<s> GCNPassConfig ( LLVMTargetMachine & TM , PassManagerBase & PM ) : <ISA_LIT>PassConfig ( TM , PM ) {