<s> getAddrModeInfo ( * MI , * MRI , AddrInfo ) ; if ( AddrInfo . empty ( ) || AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) != <NUM_LIT> ) return None ; const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; if ( ! GEPInfo . Imm || ! isUInt < <NUM_LIT> > ( GEPInfo . Imm ) ) return None ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; Register OffsetReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , OffsetReg ) . addImm ( GEPInfo . Imm ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) {


<s> default : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_ADD : return selectG_ADD ( I ) ; case TargetOpcode :: G_BITCAST : return selectCOPY ( I ) ; case TargetOpcode :: G_CONSTANT : case TargetOpcode :: G_FCONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_GEP : return selectG_GEP ( I ) ; case TargetOpcode :: G_IMPLICIT_DEF : return selectG_IMPLICIT_DEF ( I ) ; case TargetOpcode :: G_INTRIN<ISA_LIT>C :

return selectG_INTRIN<ISA_LIT>C ( I , CoverageInfo ) ;


case TargetOpcode :: G_INSERT_VECTOR_ELT :


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectDS128Bit8ByteAligned ( MachineOperand & Root ) const {

return selectDSReadWrite2 ( Root , true ) ;


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectDS64Bit4ByteAligned ( MachineOperand & Root ) const {

return selectDSReadWrite2 ( Root , false ) ;


<s> [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Reg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset + <NUM_LIT> ) ; } } } ;


<s> int64_t OffsetValue0 = Offset / ( IsDS128 ? <NUM_LIT> : <NUM_LIT> ) ; int64_t OffsetValue1 = OffsetValue0 + <NUM_LIT> ; if ( isDSOffsetLegal ( PtrBase , OffsetValue1 , ( IsDS128 ? <NUM_LIT> : <NUM_LIT> ) ) ) { return std :: make_pair ( PtrBase , OffsetValue0 ) ; }

} else if ( RootDef -> getOpcode ( ) == <STR_LIT> ) {


<s> if ( ! MI . hasOneMemOperand ( ) ) return false ; const MachineMemOperand * MMO = * MI . memoperands_begin ( ) ; const Value * Ptr = MMO -> getValue ( ) ; if ( ! Ptr || isa < UndefValue > ( Ptr ) || isa < Argument > ( Ptr ) || isa < Constant > ( Ptr ) || isa < GlobalValue > ( Ptr ) ) return true ; const Instruction * I = dyn_cast < Instruction > ( Ptr ) ; return I && I -> getMetadata ( <STR_LIT> ) ;


<s> const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; unsigned Opcode ; unsigned LoadSize = RBI . getSizeInBits ( DstReg , MRI , TRI ) ; if ( ! AddrInfo . empty ( ) && AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) == <NUM_LIT> ) { const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; int64_t EncodedImm = <STR_LIT> ( Subtarget , GEPInfo . Imm ) ; if ( <STR_LIT> ( Subtarget , GEPInfo . Imm ) ) { Opcode = getSmrdOpcode ( <STR_LIT> , LoadSize ) ; MachineInstr * SMRD = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , DstReg ) . addReg ( PtrReg ) . addImm ( EncodedImm ) . addImm ( <NUM_LIT> ) ; return constrainSelectedInstRegOperands ( * SMRD , TII , TRI , RBI ) ; } if ( Subtarget . getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS && isUInt < <NUM_LIT> > ( EncodedImm ) ) { Opcode = getSmrdOpcode ( <STR_LIT> , LoadSize ) ; MachineInstr * SMRD = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , DstReg ) . addReg ( PtrReg ) . addImm ( EncodedImm ) . addImm ( <NUM_LIT> ) ; return constrainSelectedInstRegOperands ( * SMRD , TII , TRI , RBI ) ; } if ( isUInt < <NUM_LIT> > ( GEPInfo . Imm ) ) { Opcode = getSmrdOpcode ( <STR_LIT> , LoadSize ) ; unsigned OffsetReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , OffsetReg ) . addImm ( GEPInfo . Imm ) ;

MachineInstr * SMRD = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , DstReg ) . addReg ( PtrReg ) . addReg ( OffsetReg ) . addImm ( <NUM_LIT> ) ;


<s> if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) return true ; switch ( I . getOpcode ( ) ) { default : break ; case TargetOpcode :: G_ADD : return selectG_ADD ( I ) ; case TargetOpcode :: G_CONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_GEP :


<s> bool <ISA_LIT>InstructionSelector :: select ( MachineInstr & I , CodeGenCoverage & CoverageInfo ) const { if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { if ( I . isCopy ( ) ) return selectCOPY ( I ) ; return true ; } switch ( I . getOpcode ( ) ) { default : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_ADD : return selectG_ADD ( I ) ; case TargetOpcode :: G_INTTOPTR :


<s> BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcVec ) . addReg ( SrcVec ) ; } } else if ( Mask [ <NUM_LIT> ] == <NUM_LIT> && Mask [ <NUM_LIT> ] == <NUM_LIT> ) { if ( IsVALU ) { MachineInstr * MovSDWA = BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcVec ) . addImm ( <NUM_LIT> ) . addImm ( <STR_LIT> :: WORD_0 ) . addImm ( <STR_LIT> :: UNUSED_PRESERVE ) . addImm ( <STR_LIT> :: WORD_1 ) . addReg ( SrcVec , RegState :: Implicit ) ; MovSDWA -> tieOperands ( <NUM_LIT> , MovSDWA -> getNumOperands ( ) - <NUM_LIT> ) ; } else { BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcVec ) . addReg ( SrcVec ) ; } } else if ( Mask [ <NUM_LIT> ] == <NUM_LIT> && Mask [ <NUM_LIT> ] == <NUM_LIT> ) { if ( IsVALU ) { BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcVec ) . addReg ( SrcVec ) . addImm ( <NUM_LIT> ) ; } else { Register TmpReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , TmpReg ) . addReg ( SrcVec ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( TmpReg ) . addReg ( SrcVec ) ; } } else llvm_unreachable ( <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true ;


<s> Register LHS = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RHS = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto LHSDef = getDefSrcRegIgnoringCopies ( LHS , * MRI ) ; auto RHSDef = getDefSrcRegIgnoringCopies ( RHS , * MRI ) ; if ( LHSDef && RHSDef && LHSDef -> MI -> getOpcode ( ) == <STR_LIT> && isSGPR ( RHSDef -> Reg ) ) { int FI = LHSDef -> MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; MachineInstr & I = * Root . getParent ( ) ; MachineBasicBlock * BB = I . getParent ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; SAddr = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , SAddr ) . addFrameIndex ( FI ) . addReg ( RHSDef -> Reg ) ; } } if ( ! isSGPR ( SAddr ) ) return None ;


<s> void <ISA_LIT>InstructionSelector :: renderTruncImm32 ( MachineInstrBuilder & MIB , const MachineInstr & MI , int OpIdx ) const {

assert ( MI . getOpcode ( ) == TargetOpcode :: G_CONSTANT && OpIdx == - <NUM_LIT> && <STR_LIT> ) ;


<s> LLT SrcTy = MRI -> getType ( SrcReg ) ; const unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const unsigned DstSize = DstTy . getSizeInBits ( ) ; unsigned Offset = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Offset % DstSize != <NUM_LIT> ) return false ; const RegisterBank * SrcBank = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForSizeOnBank ( SrcSize , * SrcBank , * MRI ) ;


<s> if ( ! MRI -> getRegClassOrNull ( CCReg ) ) MRI -> setRegClass ( CCReg , TRI . getConstrainedRegClassForOperand ( CCOp , * MRI ) ) ; MachineInstr * Select = BuildMI ( * BB , & I , DL , TII . get ( SelectOpcode ) , DstReg ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; bool Ret = constrainSelectedInstRegOperands ( * Select , TII , TRI , RBI ) | constrainSelectedInstRegOperands ( * CopySCC , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return Ret ; } if ( Size > <NUM_LIT> ) return false ; MachineInstr * Select = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . add ( I . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ;

bool Ret = constrainSelectedInstRegOperands ( * Select , TII , TRI , RBI ) ;


<s> if ( I . getOpcode ( ) == <STR_LIT> ) return selectCOPY ( I ) ; const RegisterBank * SrcBank = getArtifactRegBank ( SrcReg , * MRI , TRI ) ; if ( SrcBank -> getID ( ) == <STR_LIT> && DstSize <= <NUM_LIT> ) { unsigned Mask ; if ( ! Signed && shouldUseAndMask ( SrcSize , Mask ) ) { MachineInstr * ExtI = BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( Mask ) . addReg ( SrcReg ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * ExtI , TII , TRI , RBI ) ; } const unsigned BFE = Signed ? <STR_LIT> : <STR_LIT> ; MachineInstr * ExtI = BuildMI ( MBB , I , DL , TII . get ( BFE ) , DstReg ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) . addImm ( SrcSize ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * ExtI , TII , TRI , RBI ) ; } if ( SrcBank -> getID ( ) == <STR_LIT> && DstSize <= <NUM_LIT> ) { if ( ! RBI . constrainGenericRegister ( SrcReg , <STR_LIT> , * MRI ) ) return false ; if ( Signed && DstSize == <NUM_LIT> && ( SrcSize == <NUM_LIT> || SrcSize == <NUM_LIT> ) ) { const unsigned SextOpc = SrcSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , TII . get ( SextOpc ) , DstReg ) . addReg ( SrcReg ) ; I . eraseFromParent ( ) ; return RBI . constrainGenericRegister ( DstReg , <STR_LIT> , * MRI ) ; } const unsigned BFE64 = Signed ? <STR_LIT> : <STR_LIT> ; const unsigned BFE32 = Signed ? <STR_LIT> : <STR_LIT> ; if ( DstSize > <NUM_LIT> && SrcSize <= <NUM_LIT> ) { Register ExtReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; Register UndefReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , UndefReg ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , ExtReg ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) . addReg ( UndefReg ) . addImm ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( BFE64 ) , DstReg ) . addReg ( ExtReg ) . addImm ( SrcSize << <NUM_LIT> ) ; I . eraseFromParent ( ) ; return RBI . constrainGenericRegister ( DstReg , <STR_LIT> , * MRI ) ; } unsigned Mask ; if ( ! Signed && shouldUseAndMask ( SrcSize , Mask ) ) {

BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addImm ( Mask ) ;


<s> } else { DstRB = RBI . getRegBank ( DstReg , * MRI , TRI ) ; if ( SrcRB != DstRB ) return false ; } unsigned DstSize = DstTy . getSizeInBits ( ) ; unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForSizeOnBank ( SrcSize , * SrcRB , * MRI ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForSizeOnBank ( DstSize , * DstRB , * MRI ) ; if ( SrcSize > <NUM_LIT> ) { int SubRegIdx = sizeToSubRegIndex ( DstSize ) ; if ( SubRegIdx == - <NUM_LIT> ) return false ;

SrcRC = TRI . getSubClassWithSubReg ( SrcRC , SubRegIdx ) ;


<s> if ( ! TM . Options . NoNaNsFPMath && ! isKnownNeverNaN ( Src , * MRI ) ) return None ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Src ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Mods ) ; } } } ;


<s> [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Src ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Mods ) ; } } } ;


<s> MachineBasicBlock :: iterator OldInsPt = B . getInsertPt ( ) ; MachineBasicBlock & OldMBB = B . getMBB ( ) ; B . setInstr ( * OffsetDef ) ; if ( ! BaseReg ) { BaseReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; B . buildInstr ( <STR_LIT> ) . addDef ( BaseReg ) . addImm ( Overflow ) ; } else { Register OverflowVal = MRI -> createVirtualRegister ( & <STR_LIT> ) ; B . buildInstr ( <STR_LIT> ) . addDef ( OverflowVal ) . addImm ( Overflow ) ; Register NewBaseReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; TII . getAddNoCarry ( B . getMBB ( ) , B . getInsertPt ( ) , B . getDebugLoc ( ) , NewBaseReg ) . addReg ( BaseReg ) . addReg ( OverflowVal , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; BaseReg = NewBaseReg ;


<s> MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; Register DstReg = MRI . createVirtualRegister ( & SubRC ) ; if ( MO . isReg ( ) ) { unsigned ComposedSubIdx = TRI . composeSubRegIndices ( MO . getSubReg ( ) , SubIdx ) ; unsigned Reg = MO . getReg ( ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( Reg , <NUM_LIT> , ComposedSubIdx ) ; return MachineOperand :: CreateReg ( DstReg , MO . isDef ( ) , MO . isImplicit ( ) , MO . isKill ( ) , MO . isDead ( ) , MO . isUndef ( ) , MO . isEarlyClobber ( ) , <NUM_LIT> , MO . isDebug ( ) , MO . isInternalRead ( ) ) ; } assert ( MO . isImm ( ) ) ; APInt Imm ( <NUM_LIT> , MO . getImm ( ) ) ; switch ( SubIdx ) { default : llvm_unreachable ( <STR_LIT> ) ;


<s> const LLT Ty = MRI . getType ( Reg ) ; return Ty . isValid ( ) && Ty . getSizeInBits ( ) == <NUM_LIT> ; } const RegisterBank * RB = RegClassOrBank . get < const RegisterBank * > ( ) ;


<s> auto & RegClassOrBank = MRI . getRegClassOrRegBank ( Reg ) ; const TargetRegisterClass * RC = RegClassOrBank . dyn_cast < const TargetRegisterClass * > ( ) ; if ( RC ) { if ( RC -> getID ( ) != <STR_LIT> ) return false ; const LLT Ty = MRI . getType ( Reg ) ; return Ty . isValid ( ) && Ty . getSizeInBits ( ) == <NUM_LIT> ; } const RegisterBank * RB = RegClassOrBank . get < const RegisterBank * > ( ) ;


<s> auto & RegClassOrBank = MRI . getRegClassOrRegBank ( Reg ) ; const TargetRegisterClass * RC = RegClassOrBank . dyn_cast < const TargetRegisterClass * > ( ) ; if ( RC ) { const LLT Ty = MRI . getType ( Reg ) ; return RC -> hasSuperClassEq ( TRI . getBoolRC ( ) ) && Ty . isValid ( ) && Ty . getSizeInBits ( ) == <NUM_LIT> ; }

const RegisterBank * RB = RegClassOrBank . get < const RegisterBank * > ( ) ;


<s> case TargetOpcode :: G_AND : case TargetOpcode :: G_OR : case TargetOpcode :: G_XOR : if ( selectG_AND_OR_XOR ( I ) ) return true ; return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_ADD : case TargetOpcode :: G_SUB : if ( selectG_ADD_SUB ( I ) ) return true ; LLVM_FALLTHROUGH ; default : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_INTTOPTR : case TargetOpcode :: G_BITCAST : return selectCOPY ( I ) ; case TargetOpcode :: G_CONSTANT : case TargetOpcode :: G_FCONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_EXTRACT : return selectG_EXTRACT ( I ) ; case TargetOpcode :: G_MERGE_VALUES : case TargetOpcode :: G_BUILD_VECTOR : case TargetOpcode :: G_CONCAT_VECTORS : return selectG_MERGE_VALUES ( I ) ; case TargetOpcode :: G_UNMERGE_VALUES : return selectG_UNMERGE_VALUES ( I ) ; case TargetOpcode :: G_GEP : return selectG_GEP ( I ) ; case TargetOpcode :: G_IMPLICIT_DEF : return selectG_IMPLICIT_DEF ( I ) ; case TargetOpcode :: G_INSERT : return selectG_INSERT ( I ) ;

case TargetOpcode :: G_INTRIN<ISA_LIT>C :


<s> MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; I . setDesc ( TII . get ( TargetOpcode :: COPY ) ) ; const MachineOperand & Src = I . getOperand ( <NUM_LIT> ) ; MachineOperand & Dst = I . getOperand ( <NUM_LIT> ) ; Register DstReg = Dst . getReg ( ) ; Register SrcReg = Src . getReg ( ) ; if ( isVCC ( DstReg , MRI ) ) { if ( SrcReg == <STR_LIT> ) { const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( Dst , MRI ) ; if ( ! RC ) return true ; return RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ; } if ( ! isVCC ( SrcReg , MRI ) ) { if ( ! RBI . constrainGenericRegister ( DstReg , * TRI . getBoolRC ( ) , MRI ) ) return false ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) ; if ( ! MRI . getRegClassOrNull ( SrcReg ) ) MRI . setRegClass ( SrcReg , TRI . getConstrainedRegClassForOperand ( Src , MRI ) ) ; I . eraseFromParent ( ) ; return true ;


<s> I . setDesc ( TII . get ( InstOpc ) ) ; if ( Src0 . isUndef ( ) && ! MRI . getRegClassOrNull ( Src0 . getReg ( ) ) ) MRI . setRegClass ( Src0 . getReg ( ) , RC ) ; if ( Src1 . isUndef ( ) && ! MRI . getRegClassOrNull ( Src1 . getReg ( ) ) ) MRI . setRegClass ( Src1 . getReg ( ) , RC ) ; return RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ; } if ( DstRB -> getID ( ) == <STR_LIT> ) { unsigned InstOpc = getLogicalBitOpcode ( I . getOpcode ( ) , Size > <NUM_LIT> ) ; I . setDesc ( TII . get ( InstOpc ) ) ;

const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( Dst , MRI ) ;


<s> if ( isSCC ( CCReg , MRI ) ) { int Opcode = getS_CMPOpcode ( Pred , Size ) ; if ( Opcode == - <NUM_LIT> ) return false ; MachineInstr * ICmp = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , CCReg ) . addReg ( <STR_LIT> ) ; bool Ret = constrainSelectedInstRegOperands ( * ICmp , TII , TRI , RBI ) && RBI . constrainGenericRegister ( CCReg , <STR_LIT> , MRI ) ; I . eraseFromParent ( ) ;


<s> MachineBasicBlock * BB = I . getParent ( ) ; MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ; for ( Register Reg : { DstReg , Src0Reg , Src1Reg } ) { if ( ! MRI . getRegClassOrNull ( Reg ) ) MRI . setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ; } return true ; } default : return selectImpl ( I , CoverageInfo ) ;


<s> int64_t Tgt = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; int64_t Enabled = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; int64_t Done = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; int64_t VM = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; MachineInstr * Exp = buildEXP ( TII , & I , Tgt , I . getOperand ( <NUM_LIT> ) . getReg ( ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) , VM , false , Enabled , Done ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * Exp , TII , TRI , RBI ) ; } case <STR_LIT> : { const DebugLoc & DL = I . getDebugLoc ( ) ; int64_t Tgt = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; int64_t Enabled = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; unsigned Reg0 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg1 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Undef = MRI . createVirtualRegister ( & <STR_LIT> ) ; int64_t Done = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; int64_t VM = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , Undef ) ; MachineInstr * Exp = buildEXP ( TII , & I , Tgt , Reg0 , Reg1 , Undef , Undef , VM , true , Enabled , Done ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * Exp , TII , TRI , RBI ) ; } case <STR_LIT> : { BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ; if ( ! MRI . getRegClassOrNull ( Reg ) ) MRI . setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ; return true ; } default : return selectImpl ( I , CoverageInfo ) ; }


<s> bool <ISA_LIT>InstructionSelector :: selectG_LOAD ( MachineInstr & I ) const {


<s> bool Ret = constrainSelectedInstRegOperands ( * Select , TII , TRI , RBI ) | constrainSelectedInstRegOperands ( * CopySCC , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return Ret ; } if ( Size > <NUM_LIT> ) return false ; MachineInstr * Select = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . add ( I . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; bool Ret = constrainSelectedInstRegOperands ( * Select , TII , TRI , RBI ) ;


<s> unsigned PtrSize = RBI . getSizeInBits ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , TRI ) ; if ( PtrSize != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } unsigned StoreSize = RBI . getSizeInBits ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , TRI ) ; unsigned Opcode ; switch ( StoreSize ) { default : return false ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ;


<s> Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; } MachineInstr * Flat = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; bool Ret = constrainSelectedInstRegOperands ( * Flat , TII , TRI , RBI ) ; I . eraseFromParent ( ) ;


<s> if ( ! RBI . constrainGenericRegister ( SrcReg , <STR_LIT> , MRI ) ) return false ; if ( Signed && DstSize == <NUM_LIT> && ( SrcSize == <NUM_LIT> || SrcSize == <NUM_LIT> ) ) { const unsigned SextOpc = SrcSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , TII . get ( SextOpc ) , DstReg ) . addReg ( SrcReg ) ; return RBI . constrainGenericRegister ( DstReg , <STR_LIT> , MRI ) ; } const unsigned BFE64 = Signed ? <STR_LIT> : <STR_LIT> ; const unsigned BFE32 = Signed ? <STR_LIT> : <STR_LIT> ; if ( DstSize > <NUM_LIT> && SrcSize <= <NUM_LIT> ) { unsigned ExtReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned UndefReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , UndefReg ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , ExtReg ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) . addReg ( UndefReg ) . addImm ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( BFE64 ) , DstReg ) . addReg ( ExtReg ) . addImm ( SrcSize << <NUM_LIT> ) ; return RBI . constrainGenericRegister ( DstReg , <STR_LIT> , MRI ) ; } unsigned Mask ; if ( ! Signed && shouldUseAndMask ( SrcSize , Mask ) ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addImm ( Mask ) ; } else { BuildMI ( MBB , I , DL , TII . get ( BFE32 ) , DstReg ) . addReg ( SrcReg ) . addImm ( SrcSize << <NUM_LIT> ) ; } return RBI . constrainGenericRegister ( DstReg , <STR_LIT> , MRI ) ; } return false ;


<s> std :: tie ( PtrBase , ConstOffset ) = getPtrBaseWithConstantOffset ( Root . getReg ( ) , * MRI ) ; if ( ConstOffset == <NUM_LIT> ) return Default ; unsigned AddrSpace = ( * MI -> memoperands_begin ( ) ) -> getAddrSpace ( ) ; if ( ! TII . isLegalFLATOffset ( ConstOffset , AddrSpace , Signed ) ) return Default ;

return std :: make_pair ( PtrBase , ConstOffset ) ;


<s> unsigned AddrSpace = ( * MI -> memoperands_begin ( ) ) -> getAddrSpace ( ) ; if ( ! TII . isLegalFLATOffset ( ConstOffset , AddrSpace , Signed ) ) return Default ;


<s> if ( AddrDef -> MI -> getOpcode ( ) == <STR_LIT> ) { int FI = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addFrameIndex ( FI ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( ImmOffset ) ; } } } ; } Register SAddr = AddrDef -> Reg ; if ( AddrDef -> MI -> getOpcode ( ) == <STR_LIT> ) { Register LHS = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RHS = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto LHSDef = getDefSrcRegIgnoringCopies ( LHS , * MRI ) ; auto RHSDef = getDefSrcRegIgnoringCopies ( RHS , * MRI ) ; if ( LHSDef && RHSDef && LHSDef -> MI -> getOpcode ( ) == <STR_LIT> && isSGPR ( RHSDef -> Reg ) ) { int FI = LHSDef -> MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; MachineInstr & I = * Root . getParent ( ) ; MachineBasicBlock * BB = I . getParent ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; SAddr = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , SAddr ) . addFrameIndex ( FI ) . addReg ( RHSDef -> Reg ) ; } } if ( ! isSGPR ( SAddr ) ) return None ;


return selectG_<ISA_LIT>_ATOMIC_CMPXCHG ( I ) ;


<s> MachineInstr * Flat = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addReg ( PtrReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; bool Ret = constrainSelectedInstRegOperands ( * Flat , TII , TRI , RBI ) ; I . eraseFromParent ( ) ;


I . setDesc ( TII . get ( <STR_LIT> ) ) ;


<s> Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ; for ( Register Reg : { DstReg , Src0Reg , Src1Reg } ) { if ( ! MRI . getRegClassOrNull ( Reg ) ) MRI . setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ; } return true ; } default :

return selectImpl ( I , CoverageInfo ) ;


<s> bool Signed = I . getOpcode ( ) == <STR_LIT> ; const DebugLoc & DL = I . getDebugLoc ( ) ; MachineBasicBlock & MBB = * I . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType ( DstReg ) ; const LLT SrcTy = MRI . getType ( SrcReg ) ; const LLT S1 = LLT :: scalar ( <NUM_LIT> ) ; const unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const unsigned DstSize = DstTy . getSizeInBits ( ) ; if ( ! DstTy . isScalar ( ) ) return false ; const RegisterBank * SrcBank = RBI . getRegBank ( SrcReg , MRI , TRI ) ; if ( SrcBank -> getID ( ) == <STR_LIT> ) { if ( SrcTy != S1 || DstSize > <NUM_LIT> ) return false ; unsigned Opcode = DstSize > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * DstRC = DstSize > <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , TmpReg ) . addReg ( SrcReg ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( TmpReg ) ; BuildMI ( MBB , I , DL , TII . get ( Opcode ) , DstReg ) . addImm ( <NUM_LIT> ) . addImm ( Signed ? - <NUM_LIT> : <NUM_LIT> ) ; I . eraseFromParent ( ) ; return RBI . constrainGenericRegister ( DstReg , * DstRC , MRI ) ; } if ( SrcBank -> getID ( ) == <STR_LIT> && DstSize <= <NUM_LIT> ) { if ( SrcTy != S1 ) return false ; MachineInstr * ExtI = BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( Signed ? - <NUM_LIT> : <NUM_LIT> ) . addUse ( SrcReg ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * ExtI , TII , TRI , RBI ) ; } if ( I . getOpcode ( ) == <STR_LIT> ) return selectCOPY ( I ) ; if ( SrcBank -> getID ( ) == <STR_LIT> && DstSize <= <NUM_LIT> ) { unsigned Mask ; if ( ! Signed && shouldUseAndMask ( SrcSize , Mask ) ) { MachineInstr * ExtI = BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( Mask ) . addReg ( SrcReg ) ; I . eraseFromParent ( ) ;


<s> default : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_ADD : return selectG_ADD ( I ) ; case TargetOpcode :: G_INTTOPTR : case TargetOpcode :: G_BITCAST : return selectCOPY ( I ) ; case TargetOpcode :: G_CONSTANT : case TargetOpcode :: G_FCONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_EXTRACT : return selectG_EXTRACT ( I ) ; case TargetOpcode :: G_GEP : return selectG_GEP ( I ) ; case TargetOpcode :: G_IMPLICIT_DEF : return selectG_IMPLICIT_DEF ( I ) ; case TargetOpcode :: G_INSERT : return selectG_INSERT ( I ) ;


<s> assert ( Size == <NUM_LIT> ) ; unsigned CCReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isSCC ( CCReg , MRI ) ) { unsigned Opcode = getS_CMPOpcode ( ( CmpInst :: Predicate ) I . getOperand ( <NUM_LIT> ) . getPredicate ( ) , Size ) ; MachineInstr * ICmp = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; MachineInstr * Copy = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , CCReg ) . addReg ( <STR_LIT> ) ; bool Ret = constrainSelectedInstRegOperands ( * ICmp , TII , TRI , RBI ) | constrainSelectedInstRegOperands ( * Copy , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return Ret ; } assert ( Size == <NUM_LIT> || Size == <NUM_LIT> ) ; unsigned Opcode = getV_CMPOpcode ( ( CmpInst :: Predicate ) I . getOperand ( <NUM_LIT> ) . getPredicate ( ) , Size ) ; MachineInstr * ICmp = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; RBI . constrainGenericRegister ( ICmp -> getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> , MRI ) ; bool Ret = constrainSelectedInstRegOperands ( * ICmp , TII , TRI , RBI ) ;


<s> void <ISA_LIT>InstructionSelector :: renderTruncImm32 ( MachineInstrBuilder & MIB , const MachineInstr & MI ) const { assert ( MI . getOpcode ( ) == TargetOpcode :: G_CONSTANT && <STR_LIT> ) ; Optional < int64_t > CstVal = getConstantVRegVal ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , * MRI ) ; assert ( CstVal && <STR_LIT> ) ; MIB . addImm ( CstVal . getValue ( ) ) ;


<s> void <ISA_LIT>InstructionSelector :: renderTruncImm32 ( MachineInstrBuilder & MIB , const MachineInstr & MI ) const { assert ( MI . getOpcode ( ) == TargetOpcode :: G_CONSTANT && <STR_LIT> ) ; Optional < int64_t > CstVal = getConstantVRegVal ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , * MRI ) ;


<s> unsigned IntrinsicID = I . getIntrinsicID ( ) ; switch ( IntrinsicID ) { case <STR_LIT> : { MachineBasicBlock * BB = I . getParent ( ) ; BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ;

Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> case <STR_LIT> : { MachineBasicBlock * BB = I . getParent ( ) ; BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ; for ( Register Reg : { DstReg , Src0Reg , Src1Reg } ) MRI -> setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ; return true ; } case <STR_LIT> : return selectInterpP1F16 ( I ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> :


<s> return RBI . constrainGenericRegister ( Dst , <STR_LIT> , * MRI ) && RBI . constrainGenericRegister ( Src0 , <STR_LIT> , * MRI ) ; } Register ShiftSrc0 ; Register ShiftSrc1 ; bool Shift0 = mi_match ( Src0 , * MRI , m_OneUse ( m_GLShr ( m_Reg ( ShiftSrc0 ) , m_SpecificICst ( <NUM_LIT> ) ) ) ) ; bool Shift1 = mi_match ( Src1 , * MRI , m_OneUse ( m_GLShr ( m_Reg ( ShiftSrc1 ) , m_SpecificICst ( <NUM_LIT> ) ) ) ) ; unsigned Opc = <STR_LIT> ; if ( Shift0 && Shift1 ) { Opc = <STR_LIT> ; MI . getOperand ( <NUM_LIT> ) . setReg ( ShiftSrc0 ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( ShiftSrc1 ) ; } else if ( Shift1 ) { Opc = <STR_LIT> ; MI . getOperand ( <NUM_LIT> ) . setReg ( ShiftSrc1 ) ; } else if ( Shift0 && ConstSrc1 && ConstSrc1 -> Value == <NUM_LIT> ) { auto MIB = BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , Dst ) . addReg ( ShiftSrc0 ) . addImm ( <NUM_LIT> ) ; MI . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ; } MI . setDesc ( TII . get ( Opc ) ) ; return constrainSelectedInstRegOperands ( MI , TII , TRI , RBI ) ;


<s> unsigned Mods = <NUM_LIT> ; MachineInstr * MI = getDefIgnoringCopies ( Src , * MRI ) ; if ( MI && MI -> getOpcode ( ) == <STR_LIT> ) {

Src = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ; for ( Register Reg : { DstReg , Src0Reg , Src1Reg } ) MRI -> setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ; return true ;


<s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const GCNSubtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI , const <ISA_LIT>TargetMachine & TM ) : InstructionSelector ( ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , RBI ( RBI ) , TM ( TM ) , STI ( STI ) , EnableLateStructurizeCFG ( <ISA_LIT>TargetMachine :: EnableLateStructurizeCFG ) , , AMDGPUA<ISA_LIT> ( STI . get<ISA_LIT>AS ( ) ) {


<s> MachineBasicBlock * BB = I . getParent ( ) ; MachineFunction * MF = BB -> getParent ( ) ; const GCNSubtarget & Subtarget = MF -> getSubtarget < GCNSubtarget > ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; unsigned Opcode ; unsigned LoadSize = RBI . getSizeInBits ( DstReg , MRI , TRI ) ; if ( ! AddrInfo . empty ( ) && AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) == <NUM_LIT> ) { const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; int64_t EncodedImm = <STR_LIT> ( Subtarget , GEPInfo . Imm ) ; if ( <STR_LIT> ( Subtarget , GEPInfo . Imm ) ) { Opcode = getSmrdOpcode ( <STR_LIT> , LoadSize ) ; MachineInstr * SMRD = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , DstReg ) . addReg ( PtrReg ) . addImm ( EncodedImm ) . addImm ( <NUM_LIT> ) ; return constrainSelectedInstRegOperands ( * SMRD , TII , TRI , RBI ) ; }

if ( Subtarget . getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS && isUInt < <NUM_LIT> > ( EncodedImm ) ) {


<s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const <ISA_LIT>Subtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI ) : InstructionSelector ( ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , RBI ( RBI ) {


<s> if ( ! isInstrUniform ( I ) ) return false ; if ( hasVgprParts ( AddrInfo ) ) return false ; MachineBasicBlock * BB = I . getParent ( ) ; MachineFunction * MF = BB -> getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; unsigned Opcode ; unsigned LoadSize = RBI . getSizeInBits ( DstReg , MRI , TRI ) ; if ( ! AddrInfo . empty ( ) && AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) == <NUM_LIT> ) { const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; int64_t EncodedImm = <STR_LIT> ( Subtarget , GEPInfo . Imm ) ; if ( <STR_LIT> ( Subtarget , GEPInfo . Imm ) ) { Opcode = getSmrdOpcode ( <STR_LIT> , LoadSize ) ; MachineInstr * SMRD = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , DstReg ) . addReg ( PtrReg ) . addImm ( EncodedImm ) . addImm ( <NUM_LIT> ) ; return constrainSelectedInstRegOperands ( * SMRD , TII , TRI , RBI ) ; } if ( Subtarget . getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS && isUInt < <NUM_LIT> > ( EncodedImm ) ) { Opcode = getSmrdOpcode ( <STR_LIT> , LoadSize ) ; MachineInstr * SMRD = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , DstReg ) . addReg ( PtrReg ) . addImm ( EncodedImm ) . addImm ( <NUM_LIT> ) ;


<s> ArrayRef < int16_t > SubRegs = TRI . getRegSplitParts ( SuperRC , EltSize ) ; if ( static_cast < unsigned > ( Offset ) >= SubRegs . size ( ) ) return std :: make_pair ( IdxReg , SubRegs [ <NUM_LIT> ] ) ;

return std :: make_pair ( IdxBaseReg , SubRegs [ Offset ] ) ;


<s> if ( static_cast < unsigned > ( Offset ) >= SubRegs . size ( ) ) return std :: make_pair ( IdxReg , SubRegs [ <NUM_LIT> ] ) ;


<s> MIB . addImm ( MI . getOperand ( OpIdx ) . getImm ( ) ) ;


<s> if ( I . isPHI ( ) ) return selectPHI ( I ) ; if ( ! I . isPreISelOpcode ( ) ) { if ( I . isCopy ( ) ) return selectCOPY ( I ) ; return true ; } switch ( I . getOpcode ( ) ) { case TargetOpcode :: G_AND : case TargetOpcode :: G_OR : case TargetOpcode :: G_XOR : if ( selectG_AND_OR_XOR ( I ) ) return true ; return selectImpl ( I , * CoverageInfo ) ; case TargetOpcode :: G_ADD : case TargetOpcode :: G_SUB : if ( selectImpl ( I , * CoverageInfo ) ) return true ; return selectG_ADD_SUB ( I ) ; case TargetOpcode :: G_UADDO : case TargetOpcode :: G_USUBO : case TargetOpcode :: G_UADDE : case TargetOpcode :: G_USUBE : return selectG_UADDO_USUBO_UADDE_USUBE ( I ) ; case TargetOpcode :: G_INTTOPTR : case TargetOpcode :: G_BITCAST : case TargetOpcode :: G_PTRTOINT : return selectCOPY ( I ) ; case TargetOpcode :: G_CONSTANT : case TargetOpcode :: G_FCONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_EXTRACT : return selectG_EXTRACT ( I ) ; case TargetOpcode :: G_MERGE_VALUES : case TargetOpcode :: G_BUILD_VECTOR : case TargetOpcode :: G_CONCAT_VECTORS : return selectG_MERGE_VALUES ( I ) ; case TargetOpcode :: G_UNMERGE_VALUES : return selectG_UNMERGE_VALUES ( I ) ; case TargetOpcode :: G_PTR_ADD : return selectG_PTR_ADD ( I ) ; case TargetOpcode :: G_IMPLICIT_DEF : return selectG_IMPLICIT_DEF ( I ) ; case TargetOpcode :: G_INSERT : return selectG_INSERT ( I ) ; case TargetOpcode :: G_INTRIN<ISA_LIT>C : return selectG_INTRIN<ISA_LIT>C ( I ) ;


<s> if ( ! RootDef ) return std :: make_pair ( Root . getReg ( ) , <NUM_LIT> ) ; int64_t ConstAddr = <NUM_LIT> ; if ( isBaseWithConstantOffset ( Root , * MRI ) ) { const MachineOperand & LHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineOperand & RHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineInstr * LHSDef = MRI -> getVRegDef ( LHS . getReg ( ) ) ; const MachineInstr * RHSDef = MRI -> getVRegDef ( RHS . getReg ( ) ) ; if ( LHSDef && RHSDef ) { int64_t PossibleOffset = RHSDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ; if ( isDSOffsetLegal ( LHS . getReg ( ) , PossibleOffset , <NUM_LIT> ) ) { return std :: make_pair ( LHS . getReg ( ) , PossibleOffset ) ; } }

} else if ( RootDef -> getOpcode ( ) == <STR_LIT> ) {


<s> case <STR_LIT> : { BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ; if ( ! MRI -> getRegClassOrNull ( Reg ) ) MRI -> setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ; return true ; } case <STR_LIT> : return selectStoreIntrinsic ( I , false ) ; case <STR_LIT> : return selectStoreIntrinsic ( I , true ) ; case <STR_LIT> : case <STR_LIT> : return selectDSOrderedIntrinsic ( I , IntrinsicID ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>InstructionSelector :: isVCC ( Register Reg , const MachineRegisterInfo & MRI ) const { if ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) return Reg == TRI . getVCC ( ) ; auto & RegClassOrBank = MRI . getRegClassOrRegBank ( Reg ) ; const TargetRegisterClass * RC = RegClassOrBank . dyn_cast < const TargetRegisterClass * > ( ) ; if ( RC ) { return RC -> hasSuperClassEq ( TRI . getBoolRC ( ) ) && MRI . getType ( Reg ) . getSizeInBits ( ) == <NUM_LIT> ;


if ( selectImpl ( I , CoverageInfo ) ) return true ;


<s> unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isVCC ( DstReg , MRI ) ) { const DebugLoc & DL = I . getDebugLoc ( ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) ; if ( ! MRI . getRegClassOrNull ( SrcReg ) ) MRI . setRegClass ( SrcReg , TRI . getConstrainedRegClassForOperand ( Src , MRI ) ) ; I . eraseFromParent ( ) ; return true ; } } for ( const MachineOperand & MO : I . operands ( ) ) { if ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) continue ;

const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( MO , MRI ) ;


<s> return Ret ; } int Opcode = getV_CMPOpcode ( Pred , Size ) ; if ( Opcode == - <NUM_LIT> ) return false ; MachineInstr * ICmp = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; RBI . constrainGenericRegister ( ICmp -> getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> , MRI ) ; bool Ret = constrainSelectedInstRegOperands ( * ICmp , TII , TRI , RBI ) ;


<s> case <STR_LIT> : return selectImpl ( I , CoverageInfo ) ; default : return selectImpl ( I , CoverageInfo ) ;


<s> const DebugLoc & DL = I . getDebugLoc ( ) ; int64_t Tgt = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; int64_t Enabled = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; unsigned Reg0 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg1 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Undef = MRI . createVirtualRegister ( & <STR_LIT> ) ; int64_t Done = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; int64_t VM = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , Undef ) ; MachineInstr * Exp = buildEXP ( TII , & I , Tgt , Reg0 , Reg1 , Undef , Undef , VM , true , Enabled , Done ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * Exp , TII , TRI , RBI ) ;


<s> I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * Exp , TII , TRI , RBI ) ; } case <STR_LIT> : { const DebugLoc & DL = I . getDebugLoc ( ) ; int64_t Tgt = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; int64_t Enabled = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; unsigned Reg0 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg1 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Undef = MRI . createVirtualRegister ( & <STR_LIT> ) ; int64_t Done = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; int64_t VM = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , Undef ) ; MachineInstr * Exp = buildEXP ( TII , & I , Tgt , Reg0 , Reg1 , Undef , Undef , VM , true , Enabled , Done ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * Exp , TII , TRI , RBI ) ; } default : return selectImpl ( I , CoverageInfo ) ; }


<s> break ; default : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MachineInstr * Flat = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addReg ( PtrReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; bool Ret = constrainSelectedInstRegOperands ( * Flat , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return Ret ;


<s> const unsigned DstSize = DstTy . getSizeInBits ( ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForSizeOnBank ( DstSize , * DstBank , MRI ) ; if ( ! DstRC ) return false ; ArrayRef < int16_t > SubRegs = TRI . getRegSplitParts ( DstRC , SrcSize / <NUM_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * BB , & MI , DL , TII . get ( TargetOpcode :: REG_SEQUENCE ) , DstReg ) ;

for ( int I = <NUM_LIT> , E = MI . getNumOperands ( ) - <NUM_LIT> ; I != E ; ++ I ) {


<s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const GCNSubtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI , const <ISA_LIT>TargetMachine & TM ) : InstructionSelector ( ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , RBI ( RBI ) , TM ( TM ) , STI ( STI ) , EnableLateStructurizeCFG ( <ISA_LIT>TargetMachine :: EnableLateStructurizeCFG ) , {


<s> return buildRSRC ( B , MRI , <NUM_LIT> , Hi_32 ( DefaultFormat ) , BasePtr ) ;


<s> static Register buildAddr64RSrc ( MachineIRBuilder & B , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & TII , Register BasePtr ) {

uint64_t DefaultFormat = TII . getDefaultRsrcDataFormat ( ) ;


<s> static Register buildOffsetSrc ( MachineIRBuilder & B , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & TII , Register BasePtr ) { uint64_t DefaultFormat = TII . getDefaultRsrcDataFormat ( ) ; return buildRSRC ( B , MRI , - <NUM_LIT> , Hi_32 ( DefaultFormat ) , BasePtr ) ;


<s> B . buildInstr ( <STR_LIT> ) . addDef ( RSrcHi ) . addReg ( RSrc2 ) . addImm ( <STR_LIT> ) . addReg ( RSrc3 ) . addImm ( <STR_LIT> ) ; Register RSrcLo = BasePtr ; if ( ! BasePtr ) { RSrcLo = MRI . createVirtualRegister ( & <STR_LIT> ) ; B . buildInstr ( <STR_LIT> ) . addDef ( RSrcLo ) . addImm ( <NUM_LIT> ) ;


<s> if ( IdxBaseReg == <STR_LIT> ) { assert ( Offset == <NUM_LIT> ) ; IdxBaseReg = IdxReg ; } ArrayRef < int16_t > SubRegs = TRI . getRegSplitParts ( SuperRC , EltSize ) ; if ( static_cast < unsigned > ( Offset ) >= SubRegs . size ( ) ) return std :: make_pair ( IdxReg , SubRegs [ <NUM_LIT> ] ) ;


<s> MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; if ( MRI -> getType ( Dst . getReg ( ) ) == LLT :: scalar ( <NUM_LIT> ) ) return false ; const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ;

const TargetRegisterClass * SrcRC = TRI . getConstrainedRegClassForOperand ( Src , * MRI ) ;


<s> MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; if ( MRI -> getType ( Dst . getReg ( ) ) == LLT :: scalar ( <NUM_LIT> ) ) return false ;

const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ;


<s> GEPInfo GEPInfo ( * PtrMI ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { const MachineOperand & GEPOp = PtrMI -> getOperand ( i ) ; const MachineInstr * OpDef = MRI . getUniqueVRegDef ( GEPOp . getReg ( ) ) ; assert ( OpDef ) ; if ( i == <NUM_LIT> && isConstant ( * OpDef ) ) { assert ( GEPInfo . Imm == <NUM_LIT> ) ; GEPInfo . Imm = OpDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ; continue ; } const RegisterBank * OpBank = RBI . getRegBank ( GEPOp . getReg ( ) , MRI , TRI ) ; if ( OpBank -> getID ( ) == <STR_LIT> ) GEPInfo . SgprParts . push_back ( GEPOp . getReg ( ) ) ;

else GEPInfo . VgprParts . push_back ( GEPOp . getReg ( ) ) ;


<s> const RegClassOrRegBank & RegClassOrBank = MRI . getRegClassOrRegBank ( Reg ) ; if ( auto * RB = RegClassOrBank . dyn_cast < const RegisterBank * > ( ) ) return RB ;

if ( auto * RC = RegClassOrBank . dyn_cast < const TargetRegisterClass * > ( ) ) return & RBI . getRegBankFromRegClass ( * RC , LLT ( ) ) ;


<s> if ( auto * RC = RegClassOrBank . dyn_cast < const TargetRegisterClass * > ( ) ) return & RBI . getRegBankFromRegClass ( * RC , LLT ( ) ) ;


<s> Optional < int64_t > OffsetVal = getConstantVRegVal ( Reg , MRI ) ; if ( ! OffsetVal || ! isInt < <NUM_LIT> > ( * OffsetVal ) ) return None ; return Lo_32 ( * OffsetVal ) ;


<s> Optional < int64_t > OffsetVal = getConstantVRegVal ( Reg , MRI ) ; if ( ! OffsetVal || ! isInt < <NUM_LIT> > ( * OffsetVal ) ) return None ;


<s> switch ( MF . getFunction ( ) . getCallingConv ( ) ) { case CallingConv :: <ISA_LIT>_PS : return <NUM_LIT> ; case CallingConv :: <ISA_LIT>_VS : return <NUM_LIT> ; case CallingConv :: <ISA_LIT>_GS : return <NUM_LIT> ; case CallingConv :: <ISA_LIT>_HS : case CallingConv :: <ISA_LIT>_LS : case CallingConv :: <ISA_LIT>_ES : report_fatal_error ( <STR_LIT> ) ; case CallingConv :: <ISA_LIT>_CS : case CallingConv :: <ISA_LIT>_KERNEL :


<s> case CallingConv :: <ISA_LIT>_LS : case CallingConv :: <ISA_LIT>_ES : report_fatal_error ( <STR_LIT> ) ; case CallingConv :: <ISA_LIT>_CS : case CallingConv :: <ISA_LIT>_KERNEL :


<s> static unsigned getLogicalBitOpcode ( unsigned Opc , bool Is64 ) { switch ( Opc ) { case <STR_LIT> : return Is64 ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return Is64 ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> :


<s> MachineOperand & RHS = RootI -> getOperand ( <NUM_LIT> ) ; Optional < ValueAndVReg > MaybeOffset = getConstantVRegValWithLookThrough ( RHS . getReg ( ) , MRI , true ) ; if ( ! MaybeOffset ) return { Root , <NUM_LIT> } ;

return { RootI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MaybeOffset -> Value } ;


<s> Register DstReg = MRI -> createVirtualRegister ( & SubRC ) ; if ( MO . isReg ( ) ) { unsigned ComposedSubIdx = TRI . composeSubRegIndices ( MO . getSubReg ( ) , SubIdx ) ; Register Reg = MO . getReg ( ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( Reg , <NUM_LIT> , ComposedSubIdx ) ; return MachineOperand :: CreateReg ( DstReg , MO . isDef ( ) , MO . isImplicit ( ) , MO . isKill ( ) , MO . isDead ( ) , MO . isUndef ( ) , MO . isEarlyClobber ( ) , <NUM_LIT> , MO . isDebug ( ) , MO . isInternalRead ( ) ) ; } assert ( MO . isImm ( ) ) ; APInt Imm ( <NUM_LIT> , MO . getImm ( ) ) ;


<s> MachineBasicBlock * BB = MO . getParent ( ) -> getParent ( ) ; Register DstReg = MRI -> createVirtualRegister ( & SubRC ) ; if ( MO . isReg ( ) ) { unsigned ComposedSubIdx = TRI . composeSubRegIndices ( MO . getSubReg ( ) , SubIdx ) ; Register Reg = MO . getReg ( ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( Reg , <NUM_LIT> , ComposedSubIdx ) ; return MachineOperand :: CreateReg ( DstReg , MO . isDef ( ) , MO . isImplicit ( ) , MO . isKill ( ) , MO . isDead ( ) , MO . isUndef ( ) , MO . isEarlyClobber ( ) , <NUM_LIT> , MO . isDebug ( ) , MO . isInternalRead ( ) ) ; } assert ( MO . isImm ( ) ) ; APInt Imm ( <NUM_LIT> , MO . getImm ( ) ) ; switch ( SubIdx ) {


<s> return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; case CmpInst :: ICMP_EQ : return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; case CmpInst :: ICMP_SGT : return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; case CmpInst :: ICMP_SGE : return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; case CmpInst :: ICMP_SLT : return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; case CmpInst :: ICMP_SLE : return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; case CmpInst :: ICMP_UGT : return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; case CmpInst :: ICMP_UGE : return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; case CmpInst :: ICMP_ULT :


<s> if ( ! GEPInfo . VgprParts . empty ( ) ) return true ;


<s> unsigned AS = PtrTy . getAddressSpace ( ) ; if ( ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS || AS == <ISA_LIT>AS :: REGION_ADDRESS ) && STI . ldsRequiresM0Init ( ) ) { BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; }


<s> return MI . getOpcode ( ) == TargetOpcode :: G_CONSTANT ;


<s> return TII . isInlineConstant ( Imm ) ;


<s> return <STR_LIT> ( Imm , STI . hasInv2PiInlineImm ( ) ) ;


<s> bool <ISA_LIT>InstructionSelector :: isInlineImmediate16 ( int64_t Imm ) const { return <STR_LIT> ( Imm , STI . hasInv2PiInlineImm ( ) ) ;


<s> if ( MMO -> getAddrSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) return true ; const Instruction * I = dyn_cast < Instruction > ( Ptr ) ; return I && I -> getMetadata ( <STR_LIT> ) ;


<s> return X == <NUM_LIT> || X == - <NUM_LIT> ;


<s> auto PSV = PtrInfo . V . dyn_cast < const PseudoSourceValue * > ( ) ;


<s> static bool isStackPtrRelative ( const MachinePointerInfo & PtrInfo ) { auto PSV = PtrInfo . V . dyn_cast < const PseudoSourceValue * > ( ) ;


<s> if ( RC ) { const LLT Ty = MRI . getType ( Reg ) ; return RC -> hasSuperClassEq ( TRI . getBoolRC ( ) ) && Ty . isValid ( ) && Ty . getSizeInBits ( ) == <NUM_LIT> ; }

const RegisterBank * RB = RegClassOrBank . get < const RegisterBank * > ( ) ;


<s> static bool isZero ( Register Reg , const MachineRegisterInfo & MRI ) { int64_t Val ;

return mi_match ( Reg , MRI , m_ICst ( Val ) ) && Val == <NUM_LIT> ;


<s> static bool isZeroOrOneOrUndef ( int X ) {

return X == <NUM_LIT> || X == <NUM_LIT> || X == - <NUM_LIT> ;


<s> return X == <NUM_LIT> || X == <NUM_LIT> || X == - <NUM_LIT> ;


<s> NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] ; if ( isZeroOrOneOrUndef ( Mask [ <NUM_LIT> ] ) && isZeroOrOneOrUndef ( Mask [ <NUM_LIT> ] ) ) return Src0 ; assert ( NewMask [ <NUM_LIT> ] == <NUM_LIT> || NewMask [ <NUM_LIT> ] == <NUM_LIT> || NewMask [ <NUM_LIT> ] == - <NUM_LIT> ) ; assert ( NewMask [ <NUM_LIT> ] == <NUM_LIT> || NewMask [ <NUM_LIT> ] == <NUM_LIT> || NewMask [ <NUM_LIT> ] == - <NUM_LIT> ) ; NewMask [ <NUM_LIT> ] = NewMask [ <NUM_LIT> ] == - <NUM_LIT> ? - <NUM_LIT> : NewMask [ <NUM_LIT> ] - <NUM_LIT> ;


<s> static Register normalizeVOP3PMask ( int NewMask [ <NUM_LIT> ] , Register Src0 , Register Src1 , ArrayRef < int > Mask ) { NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] ; if ( isZeroOrOneOrUndef ( Mask [ <NUM_LIT> ] ) && isZeroOrOneOrUndef ( Mask [ <NUM_LIT> ] ) ) return Src0 ; assert ( NewMask [ <NUM_LIT> ] == <NUM_LIT> || NewMask [ <NUM_LIT> ] == <NUM_LIT> || NewMask [ <NUM_LIT> ] == - <NUM_LIT> ) ; assert ( NewMask [ <NUM_LIT> ] == <NUM_LIT> || NewMask [ <NUM_LIT> ] == <NUM_LIT> || NewMask [ <NUM_LIT> ] == - <NUM_LIT> ) ; NewMask [ <NUM_LIT> ] = NewMask [ <NUM_LIT> ] == - <NUM_LIT> ? - <NUM_LIT> : NewMask [ <NUM_LIT> ] - <NUM_LIT> ; NewMask [ <NUM_LIT> ] = NewMask [ <NUM_LIT> ] == - <NUM_LIT> ? - <NUM_LIT> : NewMask [ <NUM_LIT> ] - <NUM_LIT> ; return Src1 ;


<s> } if ( SLC ) { * SLC = ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; Value &= ~ ( uint64_t ) <NUM_LIT> ; } if ( DLC ) { * DLC = ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; Value &= ~ ( uint64_t ) <NUM_LIT> ; } return Value == <NUM_LIT> ;


<s> if ( MachineInstr * InputAdd = getOpcodeDef ( TargetOpcode :: G_PTR_ADD , Data . N0 , * MRI ) ) { Data . N2 = InputAdd -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Data . N3 = InputAdd -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Data . N2 = getDefIgnoringCopies ( Data . N2 , * MRI ) -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Data . N3 = getDefIgnoringCopies ( Data . N3 , * MRI ) -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> Data . Offset = Offset ; } if ( MachineInstr * InputAdd = getOpcodeDef ( TargetOpcode :: G_PTR_ADD , Data . N0 , * MRI ) ) { Data . N2 = InputAdd -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Data . N3 = InputAdd -> getOperand ( <NUM_LIT> ) . getReg ( ) ;

Data . N2 = getDefIgnoringCopies ( Data . N2 , * MRI ) -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> static bool parseTexFail ( uint64_t TexFailCtrl , bool & TFE , bool & LWE , bool & IsTexFail ) { if ( TexFailCtrl ) IsTexFail = true ; TFE = ( TexFailCtrl & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; TexFailCtrl &= ~ ( uint64_t ) <NUM_LIT> ; LWE = ( TexFailCtrl & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; TexFailCtrl &= ~ ( uint64_t ) <NUM_LIT> ;


<s> if ( MI . getOpcode ( ) == TargetOpcode :: G_FCONSTANT ) MIB . addImm ( Op . getFPImm ( ) -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ) ; else { assert ( MI . getOpcode ( ) == TargetOpcode :: G_CONSTANT && <STR_LIT> ) ; MIB . addImm ( Op . getCImm ( ) -> getSExtValue ( ) ) ; }


<s> assert ( OpIdx == - <NUM_LIT> ) ; const MachineOperand & Op = MI . getOperand ( <NUM_LIT> ) ; if ( MI . getOpcode ( ) == TargetOpcode :: G_FCONSTANT ) MIB . addImm ( Op . getFPImm ( ) -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ) ; else {

assert ( MI . getOpcode ( ) == TargetOpcode :: G_CONSTANT && <STR_LIT> ) ;


<s> MIB . addImm ( ( MI . getOperand ( OpIdx ) . getImm ( ) >> <NUM_LIT> ) & <NUM_LIT> ) ;


<s> assert ( OpIdx >= <NUM_LIT> && <STR_LIT> ) ;

MIB . addImm ( ( MI . getOperand ( OpIdx ) . getImm ( ) >> <NUM_LIT> ) & <NUM_LIT> ) ;


<s> MIB . addImm ( MI . getOperand ( OpIdx ) . getImm ( ) & <NUM_LIT> ) ;


<s> void <ISA_LIT>InstructionSelector :: renderExtractGLC ( MachineInstrBuilder & MIB , const MachineInstr & MI , int OpIdx ) const {

assert ( OpIdx >= <NUM_LIT> && <STR_LIT> ) ;


<s> assert ( OpIdx >= <NUM_LIT> && <STR_LIT> ) ; MIB . addImm ( ( MI . getOperand ( OpIdx ) . getImm ( ) >> <NUM_LIT> ) & <NUM_LIT> ) ;


<s> void <ISA_LIT>InstructionSelector :: renderExtractSWZ ( MachineInstrBuilder & MIB , const MachineInstr & MI , int OpIdx ) const { assert ( OpIdx >= <NUM_LIT> && <STR_LIT> ) ;


<s> void <ISA_LIT>InstructionSelector :: renderNegateImm ( MachineInstrBuilder & MIB , const MachineInstr & MI , int OpIdx ) const {

assert ( MI . getOpcode ( ) == TargetOpcode :: G_CONSTANT && OpIdx == - <NUM_LIT> && <STR_LIT> ) ;


<s> void <ISA_LIT>InstructionSelector :: renderNegateImm ( MachineInstrBuilder & MIB , const MachineInstr & MI , int OpIdx ) const { assert ( MI . getOpcode ( ) == TargetOpcode :: G_CONSTANT && OpIdx == - <NUM_LIT> && <STR_LIT> ) ;

MIB . addImm ( - MI . getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ) ;


<s> MIB . addImm ( MI . getOperand ( <NUM_LIT> ) . getCImm ( ) -> getValue ( ) . countPopulation ( ) ) ;


<s> void <ISA_LIT>InstructionSelector :: renderPopcntImm ( MachineInstrBuilder & MIB , const MachineInstr & MI , int OpIdx ) const { assert ( MI . getOpcode ( ) == TargetOpcode :: G_CONSTANT && OpIdx == - <NUM_LIT> && <STR_LIT> ) ; MIB . addImm ( MI . getOperand ( <NUM_LIT> ) . getCImm ( ) -> getValue ( ) . countPopulation ( ) ) ;


<s> assert ( MI . getOpcode ( ) == TargetOpcode :: G_CONSTANT && OpIdx == - <NUM_LIT> && <STR_LIT> ) ;

MIB . addImm ( MI . getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ) ;


<s> MIB . addImm ( MI . getOperand ( OpIdx ) . getImm ( ) ) ;


<s> Register DstReg = Dst . getReg ( ) ; Register SrcReg = Src . getReg ( ) ; if ( isVCC ( DstReg , * MRI ) ) { if ( SrcReg == <STR_LIT> ) { const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ; if ( ! RC ) return true ; return RBI . constrainGenericRegister ( DstReg , * RC , * MRI ) ; } if ( ! isVCC ( SrcReg , * MRI ) ) { if ( ! RBI . constrainGenericRegister ( DstReg , * TRI . getBoolRC ( ) , * MRI ) ) return false ; const TargetRegisterClass * SrcRC = TRI . getConstrainedRegClassForOperand ( Src , * MRI ) ; Register MaskedReg = MRI -> createVirtualRegister ( SrcRC ) ; unsigned AndOpc = TRI . isSGPRClass ( SrcRC ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & I , DL , TII . get ( AndOpc ) , MaskedReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( MaskedReg ) ; if ( ! MRI -> getRegClassOrNull ( SrcReg ) ) MRI -> setRegClass ( SrcReg , SrcRC ) ; I . eraseFromParent ( ) ; return true ; } const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ; if ( RC && ! RBI . constrainGenericRegister ( DstReg , * RC , * MRI ) ) return false ; if ( Src . isUndef ( ) ) { const TargetRegisterClass * SrcRC = TRI . getConstrainedRegClassForOperand ( Src , * MRI ) ; if ( SrcRC && ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; } return true ; } for ( const MachineOperand & MO : I . operands ( ) ) { if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) continue ; const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( MO , * MRI ) ; if ( ! RC ) continue ;

RBI . constrainGenericRegister ( MO . getReg ( ) , * RC , * MRI ) ;


<s> I . eraseFromParent ( ) ; return true ; } const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ; if ( RC && ! RBI . constrainGenericRegister ( DstReg , * RC , * MRI ) ) return false ; if ( Src . isUndef ( ) ) { const TargetRegisterClass * SrcRC = TRI . getConstrainedRegClassForOperand ( Src , * MRI ) ; if ( SrcRC && ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; } return true ; } for ( const MachineOperand & MO : I . operands ( ) ) { if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) continue ; const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( MO , * MRI ) ;


<s> unsigned Opc ; if ( Ty == LLT :: scalar ( <NUM_LIT> ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: scalar ( <NUM_LIT> ) ) Opc = <STR_LIT> ; else return false ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineBasicBlock * MBB = MI . getParent ( ) ; Register Numer = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Denom = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ChooseDenom = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; Register Src0 = ChooseDenom != <NUM_LIT> ? Numer : Denom ; auto MIB = BuildMI ( * MBB , & MI , DL , TII . get ( Opc ) , Dst0 ) . addDef ( Dst1 ) . addUse ( Src0 ) . addUse ( Denom ) . addUse ( Numer ) ; MI . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ;


<s> Register Dst1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI -> getType ( Dst0 ) ; unsigned Opc ; if ( Ty == LLT :: scalar ( <NUM_LIT> ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: scalar ( <NUM_LIT> ) ) Opc = <STR_LIT> ; else return false ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineBasicBlock * MBB = MI . getParent ( ) ; Register Numer = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Denom = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ChooseDenom = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ;

Register Src0 = ChooseDenom != <NUM_LIT> ? Numer : Denom ;


<s> int64_t Offset ; std :: tie ( PtrBase , Offset ) = getPtrBaseWithConstantOffset ( Root . getReg ( ) , * MRI ) ; if ( Offset ) { if ( isDSOffsetLegal ( PtrBase , Offset , <NUM_LIT> ) ) { return std :: make_pair ( PtrBase , Offset ) ; } } else if ( RootDef -> getOpcode ( ) == <STR_LIT> ) {

} else if ( mi_match ( Root . getReg ( ) , * MRI , m_ICst ( ConstAddr ) ) ) {


<s> int64_t ConstAddr = <NUM_LIT> ; Register PtrBase ; int64_t Offset ; std :: tie ( PtrBase , Offset ) = getPtrBaseWithConstantOffset ( Root . getReg ( ) , * MRI ) ; if ( Offset ) { if ( isDSOffsetLegal ( PtrBase , Offset , <NUM_LIT> ) ) { return std :: make_pair ( PtrBase , Offset ) ; } } else if ( RootDef -> getOpcode ( ) == <STR_LIT> ) {


<s> return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Reg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset + <NUM_LIT> ) ;


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectDS64Bit4ByteAligned ( MachineOperand & Root ) const { Register Reg ; unsigned Offset ; std :: tie ( Reg , Offset ) = selectDS64Bit4ByteAlignedImpl ( Root ) ;


<s> std :: pair < Register , unsigned > <ISA_LIT>InstructionSelector :: selectDS64Bit4ByteAlignedImpl ( MachineOperand & Root ) const { const MachineInstr * RootDef = MRI -> getVRegDef ( Root . getReg ( ) ) ; if ( ! RootDef ) return std :: make_pair ( Root . getReg ( ) , <NUM_LIT> ) ; int64_t ConstAddr = <NUM_LIT> ; Register PtrBase ; int64_t Offset ; std :: tie ( PtrBase , Offset ) = getPtrBaseWithConstantOffset ( Root . getReg ( ) , * MRI ) ; if ( Offset ) { int64_t DWordOffset0 = Offset / <NUM_LIT> ; int64_t DWordOffset1 = DWordOffset0 + <NUM_LIT> ; if ( isDSOffsetLegal ( PtrBase , DWordOffset1 , <NUM_LIT> ) ) { return std :: make_pair ( PtrBase , DWordOffset0 ) ;


<s> bool IsGDS = PtrTy . getAddressSpace ( ) == <ISA_LIT>AS :: REGION_ADDRESS ; unsigned Offset ; std :: tie ( PtrBase , Offset ) = selectDS1Addr1OffsetImpl ( MI . getOperand ( <NUM_LIT> ) ) ; if ( ! isDSOffsetLegal ( PtrBase , Offset , <NUM_LIT> ) ) { PtrBase = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Offset = <NUM_LIT> ; } MachineBasicBlock * MBB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; const unsigned Opc = IsAppend ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( PtrBase ) ; BuildMI ( * MBB , & MI , DL , TII . get ( Opc ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( Offset ) . addImm ( IsGDS ? - <NUM_LIT> : <NUM_LIT> ) . cloneMemRefs ( MI ) ; MI . eraseFromParent ( ) ; return true ;


<s> PtrBase = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Offset = <NUM_LIT> ; } MachineBasicBlock * MBB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; const unsigned Opc = IsAppend ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( PtrBase ) ;

BuildMI ( * MBB , & MI , DL , TII . get ( Opc ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( Offset ) . addImm ( IsGDS ? - <NUM_LIT> : <NUM_LIT> ) . cloneMemRefs ( MI ) ;


<s> if ( OffsetRB -> getID ( ) != <STR_LIT> ) return false ; MachineInstr * OffsetDef = getDefIgnoringCopies ( BaseOffset , * MRI ) ; assert ( OffsetDef ) ; unsigned ImmOffset ; MachineBasicBlock * MBB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineInstr * Readfirstlane = nullptr ; if ( OffsetDef -> getOpcode ( ) == <STR_LIT> ) { Readfirstlane = OffsetDef ; BaseOffset = OffsetDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OffsetDef = getDefIgnoringCopies ( BaseOffset , * MRI ) ; } if ( OffsetDef -> getOpcode ( ) == <STR_LIT> ) { ImmOffset = OffsetDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } else {

std :: tie ( BaseOffset , ImmOffset , OffsetDef ) = <STR_LIT> ( * MRI , BaseOffset ) ;


<s> MachineFunction * MF = MBB -> getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned IndexOperand = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; bool WaveRelease = MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ; bool WaveDone = MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ; if ( WaveDone && ! WaveRelease ) report_fatal_error ( <STR_LIT> ) ; unsigned OrderedCountIndex = IndexOperand & <NUM_LIT> ; IndexOperand &= ~ <NUM_LIT> ; unsigned CountDw = <NUM_LIT> ; if ( STI . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) { CountDw = ( IndexOperand >> <NUM_LIT> ) & <NUM_LIT> ; IndexOperand &= ~ ( <NUM_LIT> << <NUM_LIT> ) ; if ( CountDw < <NUM_LIT> || CountDw > <NUM_LIT> ) { report_fatal_error ( <STR_LIT> ) ; } } if ( IndexOperand ) report_fatal_error ( <STR_LIT> ) ; unsigned Instruction = IntrID == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; unsigned ShaderType = getDSShaderTypeValue ( * MF ) ; unsigned Offset0 = OrderedCountIndex << <NUM_LIT> ; unsigned Offset1 = WaveRelease | ( WaveDone << <NUM_LIT> ) | ( ShaderType << <NUM_LIT> ) | ( Instruction << <NUM_LIT> ) ; if ( STI . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) Offset1 |= ( CountDw - <NUM_LIT> ) << <NUM_LIT> ; unsigned Offset = Offset0 | ( Offset1 << <NUM_LIT> ) ; Register M0Val = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( M0Val ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstrBuilder DS = BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( ValReg ) . addImm ( Offset ) . cloneMemRefs ( MI ) ; if ( ! RBI . constrainGenericRegister ( M0Val , <STR_LIT> , * MRI ) ) return false ;

bool Ret = constrainSelectedInstRegOperands ( * DS , TII , TRI , RBI ) ;


<s> Register Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MI . eraseFromParent ( ) ;

if ( ! MRI -> getRegClassOrNull ( Reg ) ) MRI -> setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ;


<s> BuildMI ( * BB , & MI , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; Register Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MI . eraseFromParent ( ) ; if ( ! MRI -> getRegClassOrNull ( Reg ) ) MRI -> setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ;


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectFlatOffset ( MachineOperand & Root ) const {

return selectFlatOffsetImpl < false > ( Root ) ;


<s> } } ; if ( ! STI . hasFlatInstOffsets ( ) ) return Default ; const MachineInstr * OpDef = MRI -> getVRegDef ( Root . getReg ( ) ) ; if ( ! OpDef || OpDef -> getOpcode ( ) != <STR_LIT> ) return Default ; Optional < int64_t > Offset = getConstantVRegVal ( OpDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , * MRI ) ; if ( ! Offset . hasValue ( ) ) return Default ; unsigned AddrSpace = ( * MI -> memoperands_begin ( ) ) -> getAddrSpace ( ) ;

if ( ! TII . isLegalFLATOffset ( Offset . getValue ( ) , AddrSpace , Signed ) ) return Default ;


<s> <STR_LIT> ; } else return selectImpl ( MI , * CoverageInfo ) ; auto MIB = BuildMI ( * BB , & MI , DL , TII . get ( Opcode ) , TmpReg ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( VAddr ) MIB . addReg ( VAddr ) ; MIB . addReg ( RSrcReg ) ; if ( SOffset ) MIB . addReg ( SOffset ) ; else MIB . addImm ( <NUM_LIT> ) ; MIB . addImm ( Offset ) ; MIB . addImm ( <NUM_LIT> ) ; MIB . cloneMemRefs ( MI ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( TmpReg , RegState :: Kill , SubReg ) ; MI . eraseFromParent ( ) ; MRI -> setRegClass ( DstReg , Is64 ? & <STR_LIT> : & <STR_LIT> ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ;


<s> MachineOperand & Src0 = I . getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = I . getOperand ( <NUM_LIT> ) ; Register DstReg = Dst . getReg ( ) ; unsigned Size = RBI . getSizeInBits ( DstReg , * MRI , TRI ) ; const RegisterBank * DstRB = RBI . getRegBank ( DstReg , * MRI , TRI ) ; if ( DstRB -> getID ( ) == <STR_LIT> ) { const TargetRegisterClass * RC = TRI . getBoolRC ( ) ; unsigned InstOpc = getLogicalBitOpcode ( I . getOpcode ( ) , RC == & <STR_LIT> ) ; I . setDesc ( TII . get ( InstOpc ) ) ; I . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , true , true , false , true ) ) ; if ( Src0 . isUndef ( ) && ! MRI -> getRegClassOrNull ( Src0 . getReg ( ) ) ) MRI -> setRegClass ( Src0 . getReg ( ) , RC ) ; if ( Src1 . isUndef ( ) && ! MRI -> getRegClassOrNull ( Src1 . getReg ( ) ) ) MRI -> setRegClass ( Src1 . getReg ( ) , RC ) ; return RBI . constrainGenericRegister ( DstReg , * RC , * MRI ) ; } if ( DstRB -> getID ( ) == <STR_LIT> ) { unsigned InstOpc = getLogicalBitOpcode ( I . getOpcode ( ) , Size > <NUM_LIT> ) ; I . setDesc ( TII . get ( InstOpc ) ) ; I . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , true , true , false , true ) ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ;


<s> MachineOperand & Src1 = I . getOperand ( <NUM_LIT> ) ; Register DstReg = Dst . getReg ( ) ; unsigned Size = RBI . getSizeInBits ( DstReg , * MRI , TRI ) ; const RegisterBank * DstRB = RBI . getRegBank ( DstReg , * MRI , TRI ) ; if ( DstRB -> getID ( ) == <STR_LIT> ) { const TargetRegisterClass * RC = TRI . getBoolRC ( ) ; unsigned InstOpc = getLogicalBitOpcode ( I . getOpcode ( ) , RC == & <STR_LIT> ) ; I . setDesc ( TII . get ( InstOpc ) ) ; I . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , true , true , false , true ) ) ; if ( Src0 . isUndef ( ) && ! MRI -> getRegClassOrNull ( Src0 . getReg ( ) ) ) MRI -> setRegClass ( Src0 . getReg ( ) , RC ) ; if ( Src1 . isUndef ( ) && ! MRI -> getRegClassOrNull ( Src1 . getReg ( ) ) ) MRI -> setRegClass ( Src1 . getReg ( ) , RC ) ; return RBI . constrainGenericRegister ( DstReg , * RC , * MRI ) ; } if ( DstRB -> getID ( ) == <STR_LIT> ) { unsigned InstOpc = getLogicalBitOpcode ( I . getOpcode ( ) , Size > <NUM_LIT> ) ; I . setDesc ( TII . get ( InstOpc ) ) ; I . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , true , true , false , true ) ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } return false ;


<s> MachineBasicBlock * BB = I . getParent ( ) ; MachineOperand & CondOp = I . getOperand ( <NUM_LIT> ) ; Register CondReg = CondOp . getReg ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; unsigned BrOpcode ; Register CondPhysReg ; const TargetRegisterClass * ConstrainRC ; if ( ! isVCC ( CondReg , * MRI ) ) { if ( MRI -> getType ( CondReg ) != LLT :: scalar ( <NUM_LIT> ) ) return false ; CondPhysReg = <STR_LIT> ; BrOpcode = <STR_LIT> ; ConstrainRC = & <STR_LIT> ; } else { CondPhysReg = TRI . getVCC ( ) ; BrOpcode = <STR_LIT> ; ConstrainRC = TRI . getBoolRC ( ) ;


<s> Register Src1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI -> getType ( Src0 ) != S32 ) return false ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineBasicBlock * BB = MI . getParent ( ) ; MachineInstr * Src1Def = getDefIgnoringCopies ( Src1 , * MRI ) ; if ( Src1Def && Src1Def -> getOpcode ( ) == <STR_LIT> ) { MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . RemoveOperand ( <NUM_LIT> ) ; return RBI . constrainGenericRegister ( Dst , <STR_LIT> , * MRI ) && RBI . constrainGenericRegister ( Src0 , <STR_LIT> , * MRI ) ; } Register ShiftSrc0 ; Register ShiftSrc1 ; int64_t ShiftAmt ; bool Shift0 = mi_match ( Src0 , * MRI , m_OneUse ( m_GLShr ( m_Reg ( ShiftSrc0 ) , m_ICst ( ShiftAmt ) ) ) ) && ShiftAmt == <NUM_LIT> ; bool Shift1 = mi_match ( Src1 , * MRI , m_OneUse ( m_GLShr ( m_Reg ( ShiftSrc1 ) , m_ICst ( ShiftAmt ) ) ) ) && ShiftAmt == <NUM_LIT> ; unsigned Opc = <STR_LIT> ; if ( Shift0 && Shift1 ) { Opc = <STR_LIT> ;

MI . getOperand ( <NUM_LIT> ) . setReg ( ShiftSrc0 ) ;


<s> if ( RB ) { IsSgpr = RB -> getID ( ) == <STR_LIT> ; Size = MRI -> getType ( DstReg ) . getSizeInBits ( ) ; } else { const TargetRegisterClass * RC = TRI . getRegClassForReg ( * MRI , DstReg ) ; IsSgpr = TRI . isSGPRClass ( RC ) ; Size = TRI . getRegSizeInBits ( * RC ) ; } if ( Size != <NUM_LIT> && Size != <NUM_LIT> ) return false ; unsigned Opcode = IsSgpr ? <STR_LIT> : <STR_LIT> ; if ( Size == <NUM_LIT> ) { I . setDesc ( TII . get ( Opcode ) ) ; I . addImplicitDefUseOperands ( * MF ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } const DebugLoc & DL = I . getDebugLoc ( ) ; APInt Imm ( Size , I . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; MachineInstr * ResInst ; if ( IsSgpr && TII . isInlineConstant ( Imm ) ) { ResInst = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( I . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; } else { const TargetRegisterClass * RC = IsSgpr ? & <STR_LIT> : & <STR_LIT> ; Register LoReg = MRI -> createVirtualRegister ( RC ) ; Register HiReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , LoReg ) . addImm ( Imm . trunc ( <NUM_LIT> ) . getZExtValue ( ) ) ; BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , HiReg ) . addImm ( Imm . ashr ( <NUM_LIT> ) . getZExtValue ( ) ) ; ResInst = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( LoReg ) . addImm ( <STR_LIT> ) . addReg ( HiReg ) . addImm ( <STR_LIT> ) ; } I . eraseFromParent ( ) ; const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand ( ResInst -> getOperand ( <NUM_LIT> ) , * MRI ) ; if ( ! DstRC ) return true ;

return RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) ;


<s> const TargetRegisterClass * SrcRC = TRI . getRegClassForSizeOnBank ( SrcSize , * SrcBank , * MRI ) ; if ( ! SrcRC ) return false ; unsigned SubReg = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( Offset / <NUM_LIT> , DstSize / <NUM_LIT> ) ; SrcRC = TRI . getSubClassWithSubReg ( SrcRC , SubReg ) ; if ( ! SrcRC ) return false ; SrcReg = constrainOperandRegClass ( * MF , TRI , * MRI , TII , RBI , I , * SrcRC , I . getOperand ( <NUM_LIT> ) ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; BuildMI ( * BB , & I , DL , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( SrcReg , <NUM_LIT> , SubReg ) ; I . eraseFromParent ( ) ; return true ;


<s> const bool Is64 = DstTy . getSizeInBits ( ) == <NUM_LIT> ; unsigned SubReg ; std :: tie ( IdxReg , SubReg ) = computeIndirectRegIndex ( * MRI , TRI , SrcRC , IdxReg , DstTy . getSizeInBits ( ) / <NUM_LIT> ) ; if ( SrcRB -> getID ( ) == <STR_LIT> ) { if ( DstTy . getSizeInBits ( ) != <NUM_LIT> && ! Is64 ) return false ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( IdxReg ) ; unsigned Opc = Is64 ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & MI , DL , TII . get ( Opc ) , DstReg ) . addReg ( SrcReg , <NUM_LIT> , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) ; MI . eraseFromParent ( ) ; return true ; } if ( SrcRB -> getID ( ) != <STR_LIT> || DstTy . getSizeInBits ( ) != <NUM_LIT> ) return false ; if ( ! STI . useVGPRIndexMode ( ) ) { BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( IdxReg ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , RegState :: Undef , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) ; MI . eraseFromParent ( ) ; return true ; }

BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( IdxReg ) . addImm ( <STR_LIT> :: SRC0_ENABLE ) ;


<s> Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register IdxReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DstTy = MRI -> getType ( DstReg ) ; LLT SrcTy = MRI -> getType ( SrcReg ) ; const RegisterBank * DstRB = RBI . getRegBank ( DstReg , * MRI , TRI ) ; const RegisterBank * SrcRB = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; const RegisterBank * IdxRB = RBI . getRegBank ( IdxReg , * MRI , TRI ) ; if ( IdxRB -> getID ( ) != <STR_LIT> ) return false ; const TargetRegisterClass * SrcRC = TRI . getRegClassForTypeOnBank ( SrcTy , * SrcRB , * MRI ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForTypeOnBank ( DstTy , * DstRB , * MRI ) ; if ( ! SrcRC || ! DstRC ) return false ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) || ! RBI . constrainGenericRegister ( IdxReg , <STR_LIT> , * MRI ) ) return false ; MachineBasicBlock * BB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; const bool Is64 = DstTy . getSizeInBits ( ) == <NUM_LIT> ; unsigned SubReg ; std :: tie ( IdxReg , SubReg ) = computeIndirectRegIndex ( * MRI , TRI , SrcRC , IdxReg , DstTy . getSizeInBits ( ) / <NUM_LIT> ) ; if ( SrcRB -> getID ( ) == <STR_LIT> ) { if ( DstTy . getSizeInBits ( ) != <NUM_LIT> && ! Is64 ) return false ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( IdxReg ) ; unsigned Opc = Is64 ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & MI , DL , TII . get ( Opc ) , DstReg ) . addReg ( SrcReg , <NUM_LIT> , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) ; MI . eraseFromParent ( ) ; return true ; } if ( SrcRB -> getID ( ) != <STR_LIT> || DstTy . getSizeInBits ( ) != <NUM_LIT> ) return false ; if ( ! STI . useVGPRIndexMode ( ) ) { BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( IdxReg ) ;

BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , RegState :: Undef , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) ;


<s> Register Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * BB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; Register LoReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; Register HiReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; Register ConstReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; Register OpReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; if ( ! RBI . constrainGenericRegister ( Src , <STR_LIT> , * MRI ) || ! RBI . constrainGenericRegister ( Dst , <STR_LIT> , * MRI ) ) return false ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , LoReg ) . addReg ( Src , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , HiReg ) . addReg ( Src , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , ConstReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , OpReg ) . addReg ( HiReg ) . addReg ( ConstReg ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , Dst ) . addReg ( LoReg ) . addImm ( <STR_LIT> ) . addReg ( OpReg ) . addImm ( <STR_LIT> ) ;


<s> MachineBasicBlock * BB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; Register LoReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; Register HiReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; Register ConstReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; Register OpReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , LoReg ) . addReg ( Src , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , HiReg ) . addReg ( Src , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , ConstReg ) . addImm ( <NUM_LIT> ) ; unsigned Opc = Fabs ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & MI , DL , TII . get ( Opc ) , OpReg ) . addReg ( HiReg ) . addReg ( ConstReg ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , Dst ) . addReg ( LoReg ) . addImm ( <STR_LIT> ) . addReg ( OpReg ) . addImm ( <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true ;


<s> Register OpReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , LoReg ) . addReg ( Src , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , HiReg ) . addReg ( Src , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , ConstReg ) . addImm ( <NUM_LIT> ) ; unsigned Opc = Fabs ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & MI , DL , TII . get ( Opc ) , OpReg ) . addReg ( HiReg ) . addReg ( ConstReg ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , Dst ) . addReg ( LoReg ) . addImm ( <STR_LIT> ) . addReg ( OpReg ) . addImm ( <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true ;


<s> I . setDesc ( TII . get ( IsVGPR ? <STR_LIT> : <STR_LIT> ) ) ; if ( IsVGPR ) I . addOperand ( * MF , MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ;

return RBI . constrainGenericRegister ( DstReg , IsVGPR ? <STR_LIT> : <STR_LIT> , * MRI ) ;


<s> const DebugLoc & DL = I . getDebugLoc ( ) ; Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Size = RBI . getSizeInBits ( SrcReg , * MRI , TRI ) ; auto Pred = ( CmpInst :: Predicate ) I . getOperand ( <NUM_LIT> ) . getPredicate ( ) ; Register CCReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! isVCC ( CCReg , * MRI ) ) { int Opcode = getS_CMPOpcode ( Pred , Size ) ; if ( Opcode == - <NUM_LIT> ) return false ; MachineInstr * ICmp = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , CCReg ) . addReg ( <STR_LIT> ) ; bool Ret = constrainSelectedInstRegOperands ( * ICmp , TII , TRI , RBI ) && RBI . constrainGenericRegister ( CCReg , <STR_LIT> , * MRI ) ;


<s> BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , CCReg ) . addReg ( <STR_LIT> ) ; bool Ret = constrainSelectedInstRegOperands ( * ICmp , TII , TRI , RBI ) && RBI . constrainGenericRegister ( CCReg , <STR_LIT> , * MRI ) ; I . eraseFromParent ( ) ; return Ret ; } int Opcode = getV_CMPOpcode ( Pred , Size ) ; if ( Opcode == - <NUM_LIT> ) return false ;

MachineInstr * ICmp = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ;


<s> if ( ( ! RC && ! MRI -> getRegBankOrNull ( MO . getReg ( ) ) ) || ( RC && RBI . constrainGenericRegister ( MO . getReg ( ) , * RC , * MRI ) ) ) { I . setDesc ( TII . get ( TargetOpcode :: IMPLICIT_DEF ) ) ; return true ; } return false ;


<s> const RegisterBank * DstBank = RBI . getRegBank ( DstReg , * MRI , TRI ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForSizeOnBank ( DstSize , * DstBank , * MRI ) ; if ( ! DstRC ) return false ; const RegisterBank * Src0Bank = RBI . getRegBank ( Src0Reg , * MRI , TRI ) ; const RegisterBank * Src1Bank = RBI . getRegBank ( Src1Reg , * MRI , TRI ) ; const TargetRegisterClass * Src0RC = TRI . getRegClassForSizeOnBank ( DstSize , * Src0Bank , * MRI ) ; const TargetRegisterClass * Src1RC = TRI . getRegClassForSizeOnBank ( InsSize , * Src1Bank , * MRI ) ; Src0RC = TRI . getSubClassWithSubReg ( Src0RC , SubReg ) ;

if ( ! Src0RC || ! Src1RC ) return false ;


<s> if ( ! DstRC ) return false ; const RegisterBank * Src0Bank = RBI . getRegBank ( Src0Reg , * MRI , TRI ) ; const RegisterBank * Src1Bank = RBI . getRegBank ( Src1Reg , * MRI , TRI ) ; const TargetRegisterClass * Src0RC = TRI . getRegClassForSizeOnBank ( DstSize , * Src0Bank , * MRI ) ; const TargetRegisterClass * Src1RC = TRI . getRegClassForSizeOnBank ( InsSize , * Src1Bank , * MRI ) ; Src0RC = TRI . getSubClassWithSubReg ( Src0RC , SubReg ) ; if ( ! Src0RC || ! Src1RC ) return false ;

if ( ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) || ! RBI . constrainGenericRegister ( Src0Reg , * Src0RC , * MRI ) || ! RBI . constrainGenericRegister ( Src1Reg , * Src1RC , * MRI ) ) return false ;


<s> const TargetRegisterClass * VecRC = TRI . getRegClassForTypeOnBank ( VecTy , * VecRB , * MRI ) ; const TargetRegisterClass * ValRC = TRI . getRegClassForTypeOnBank ( ValTy , * ValRB , * MRI ) ; if ( ! RBI . constrainGenericRegister ( VecReg , * VecRC , * MRI ) || ! RBI . constrainGenericRegister ( DstReg , * VecRC , * MRI ) || ! RBI . constrainGenericRegister ( ValReg , * ValRC , * MRI ) || ! RBI . constrainGenericRegister ( IdxReg , <STR_LIT> , * MRI ) ) return false ; if ( VecRB -> getID ( ) == <STR_LIT> && ValSize != <NUM_LIT> ) return false ; unsigned SubReg ; std :: tie ( IdxReg , SubReg ) = computeIndirectRegIndex ( * MRI , TRI , VecRC , IdxReg , ValSize / <NUM_LIT> ) ; const bool IndexMode = VecRB -> getID ( ) == <STR_LIT> && STI . useVGPRIndexMode ( ) ; MachineBasicBlock * BB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ;


<s> LLT ValTy = MRI -> getType ( ValReg ) ; unsigned VecSize = VecTy . getSizeInBits ( ) ; unsigned ValSize = ValTy . getSizeInBits ( ) ; const RegisterBank * VecRB = RBI . getRegBank ( VecReg , * MRI , TRI ) ; const RegisterBank * ValRB = RBI . getRegBank ( ValReg , * MRI , TRI ) ; const RegisterBank * IdxRB = RBI . getRegBank ( IdxReg , * MRI , TRI ) ; assert ( VecTy . getElementType ( ) == ValTy ) ; if ( IdxRB -> getID ( ) != <STR_LIT> ) return false ; const TargetRegisterClass * VecRC = TRI . getRegClassForTypeOnBank ( VecTy , * VecRB , * MRI ) ; const TargetRegisterClass * ValRC = TRI . getRegClassForTypeOnBank ( ValTy , * ValRB , * MRI ) ; if ( ! RBI . constrainGenericRegister ( VecReg , * VecRC , * MRI ) || ! RBI . constrainGenericRegister ( DstReg , * VecRC , * MRI ) || ! RBI . constrainGenericRegister ( ValReg , * ValRC , * MRI ) || ! RBI . constrainGenericRegister ( IdxReg , <STR_LIT> , * MRI ) ) return false ; if ( VecRB -> getID ( ) == <STR_LIT> && ValSize != <NUM_LIT> ) return false ; unsigned SubReg ; std :: tie ( IdxReg , SubReg ) = computeIndirectRegIndex ( * MRI , TRI , VecRC , IdxReg , ValSize / <NUM_LIT> ) ; const bool IndexMode = VecRB -> getID ( ) == <STR_LIT> && STI . useVGPRIndexMode ( ) ; MachineBasicBlock * BB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; if ( IndexMode ) { BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( IdxReg ) . addImm ( <STR_LIT> :: DST_ENABLE ) ; } else {

BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( IdxReg ) ;


<s> BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ; for ( Register Reg : { DstReg , Src0Reg , Src1Reg } ) MRI -> setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ; return true ; } case <STR_LIT> : return selectInterpP1F16 ( I ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : return selectDivScale ( I ) ;


<s> initM0 ( I ) ; return selectImpl ( I , * CoverageInfo ) ;


<s> if ( ! DstRC ) return false ; ArrayRef < int16_t > SubRegs = TRI . getRegSplitParts ( DstRC , SrcSize / <NUM_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * BB , & MI , DL , TII . get ( TargetOpcode :: REG_SEQUENCE ) , DstReg ) ; for ( int I = <NUM_LIT> , E = MI . getNumOperands ( ) - <NUM_LIT> ; I != E ; ++ I ) { MachineOperand & Src = MI . getOperand ( I + <NUM_LIT> ) ; MIB . addReg ( Src . getReg ( ) , getUndefRegState ( Src . isUndef ( ) ) ) ; MIB . addImm ( SubRegs [ I ] ) ; const TargetRegisterClass * SrcRC = TRI . getConstrainedRegClassForOperand ( Src , * MRI ) ; if ( SrcRC && ! RBI . constrainGenericRegister ( Src . getReg ( ) , * SrcRC , * MRI ) ) return false ; } if ( ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) ) return false ; MI . eraseFromParent ( ) ; return true ;


<s> if ( IsVALU ) { BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcVec ) ; } else { BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcVec ) . addImm ( <NUM_LIT> ) ; } } else if ( Mask [ <NUM_LIT> ] == <NUM_LIT> && Mask [ <NUM_LIT> ] == <NUM_LIT> ) { if ( IsVALU ) { MachineInstr * MovSDWA = BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcVec ) . addImm ( <NUM_LIT> ) . addImm ( <STR_LIT> :: WORD_1 ) . addImm ( <STR_LIT> :: UNUSED_PRESERVE ) . addImm ( <STR_LIT> :: WORD_0 ) . addReg ( SrcVec , RegState :: Implicit ) ; MovSDWA -> tieOperands ( <NUM_LIT> , MovSDWA -> getNumOperands ( ) - <NUM_LIT> ) ; } else { BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcVec ) . addReg ( SrcVec ) ; } } else if ( Mask [ <NUM_LIT> ] == <NUM_LIT> && Mask [ <NUM_LIT> ] == <NUM_LIT> ) { if ( IsVALU ) { MachineInstr * MovSDWA = BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcVec ) . addImm ( <NUM_LIT> ) . addImm ( <STR_LIT> :: WORD_0 ) . addImm ( <STR_LIT> :: UNUSED_PRESERVE ) . addImm ( <STR_LIT> :: WORD_1 ) . addReg ( SrcVec , RegState :: Implicit ) ; MovSDWA -> tieOperands ( <NUM_LIT> , MovSDWA -> getNumOperands ( ) - <NUM_LIT> ) ; } else { BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcVec ) . addReg ( SrcVec ) ; } } else if ( Mask [ <NUM_LIT> ] == <NUM_LIT> && Mask [ <NUM_LIT> ] == <NUM_LIT> ) { if ( IsVALU ) { BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcVec ) . addReg ( SrcVec ) . addImm ( <NUM_LIT> ) ;


<s> bool <ISA_LIT>InstructionSelector :: selectG_STORE ( MachineInstr & I ) const { initM0 ( I ) ;

return selectImpl ( I , * CoverageInfo ) ;


<s> MachineInstr * ExtI = BuildMI ( MBB , I , DL , TII . get ( BFE ) , DstReg ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) . addImm ( SrcSize ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * ExtI , TII , TRI , RBI ) ; } if ( SrcBank -> getID ( ) == <STR_LIT> && DstSize <= <NUM_LIT> ) { const TargetRegisterClass & SrcRC = InReg && DstSize > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( ! RBI . constrainGenericRegister ( SrcReg , SrcRC , * MRI ) ) return false ; if ( Signed && DstSize == <NUM_LIT> && ( SrcSize == <NUM_LIT> || SrcSize == <NUM_LIT> ) ) { const unsigned SextOpc = SrcSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , TII . get ( SextOpc ) , DstReg ) . addReg ( SrcReg ) ; I . eraseFromParent ( ) ; return RBI . constrainGenericRegister ( DstReg , <STR_LIT> , * MRI ) ; } const unsigned BFE64 = Signed ? <STR_LIT> : <STR_LIT> ; const unsigned BFE32 = Signed ? <STR_LIT> : <STR_LIT> ; if ( DstSize > <NUM_LIT> && ( SrcSize <= <NUM_LIT> || InReg ) ) { Register ExtReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; Register UndefReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; unsigned SubReg = InReg ? <STR_LIT> : <NUM_LIT> ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , UndefReg ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , ExtReg ) . addReg ( SrcReg , <NUM_LIT> , SubReg ) . addImm ( <STR_LIT> ) . addReg ( UndefReg ) . addImm ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( BFE64 ) , DstReg ) . addReg ( ExtReg ) . addImm ( SrcSize << <NUM_LIT> ) ; I . eraseFromParent ( ) ; return RBI . constrainGenericRegister ( DstReg , <STR_LIT> , * MRI ) ; } unsigned Mask ; if ( ! Signed && shouldUseAndMask ( SrcSize , Mask ) ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addImm ( Mask ) ; } else { BuildMI ( MBB , I , DL , TII . get ( BFE32 ) , DstReg ) . addReg ( SrcReg ) . addImm ( SrcSize << <NUM_LIT> ) ; }


<s> MachineInstr * MovSDWA = BuildMI ( * MBB , I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( HiReg ) . addImm ( <NUM_LIT> ) . addImm ( <STR_LIT> :: WORD_1 ) . addImm ( <STR_LIT> :: UNUSED_PRESERVE ) . addImm ( <STR_LIT> :: WORD_0 ) . addReg ( LoReg , RegState :: Implicit ) ; MovSDWA -> tieOperands ( <NUM_LIT> , MovSDWA -> getNumOperands ( ) - <NUM_LIT> ) ; } else { Register TmpReg0 = MRI -> createVirtualRegister ( DstRC ) ; Register TmpReg1 = MRI -> createVirtualRegister ( DstRC ) ; Register ImmReg = MRI -> createVirtualRegister ( DstRC ) ; if ( IsVALU ) { BuildMI ( * MBB , I , DL , TII . get ( <STR_LIT> ) , TmpReg0 ) . addImm ( <NUM_LIT> ) . addReg ( HiReg ) ; } else { BuildMI ( * MBB , I , DL , TII . get ( <STR_LIT> ) , TmpReg0 ) . addReg ( HiReg ) . addImm ( <NUM_LIT> ) ; } unsigned MovOpc = IsVALU ? <STR_LIT> : <STR_LIT> ; unsigned AndOpc = IsVALU ? <STR_LIT> : <STR_LIT> ; unsigned OrOpc = IsVALU ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MBB , I , DL , TII . get ( MovOpc ) , ImmReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , I , DL , TII . get ( AndOpc ) , TmpReg1 ) . addReg ( LoReg ) . addReg ( ImmReg ) ; BuildMI ( * MBB , I , DL , TII . get ( OrOpc ) , DstReg ) . addReg ( TmpReg0 ) . addReg ( TmpReg1 ) ; } I . eraseFromParent ( ) ; return true ; } if ( ! DstTy . isScalar ( ) ) return false ; if ( SrcSize > <NUM_LIT> ) { int SubRegIdx = sizeToSubRegIndex ( DstSize ) ; if ( SubRegIdx == - <NUM_LIT> ) return false ; const TargetRegisterClass * SrcWithSubRC = TRI . getSubClassWithSubReg ( SrcRC , SubRegIdx ) ; if ( ! SrcWithSubRC ) return false ;


<s> I . addOperand ( * MF , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( HasCarryIn ) { BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } unsigned NoCarryOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; unsigned CarryOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & I , DL , TII . get ( HasCarryIn ? CarryOpc : NoCarryOpc ) , Dst0Reg ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , Dst1Reg ) . addReg ( <STR_LIT> ) ; if ( ! MRI -> getRegClassOrNull ( Dst1Reg ) ) MRI -> setRegClass ( Dst1Reg , & <STR_LIT> ) ;

if ( ! RBI . constrainGenericRegister ( Dst0Reg , <STR_LIT> , * MRI ) || ! RBI . constrainGenericRegister ( Src0Reg , <STR_LIT> , * MRI ) || ! RBI . constrainGenericRegister ( Src1Reg , <STR_LIT> , * MRI ) ) return false ;


<s> I . setDesc ( TII . get ( HasCarryIn ? CarryOpc : NoCarryOpc ) ) ; I . addOperand ( * MF , MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; I . addOperand ( * MF , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( HasCarryIn ) { BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } unsigned NoCarryOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; unsigned CarryOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & I , DL , TII . get ( HasCarryIn ? CarryOpc : NoCarryOpc ) , Dst0Reg ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , Dst1Reg ) . addReg ( <STR_LIT> ) ; if ( ! MRI -> getRegClassOrNull ( Dst1Reg ) ) MRI -> setRegClass ( Dst1Reg , & <STR_LIT> ) ; if ( ! RBI . constrainGenericRegister ( Dst0Reg , <STR_LIT> , * MRI ) || ! RBI . constrainGenericRegister ( Src0Reg , <STR_LIT> , * MRI ) || ! RBI . constrainGenericRegister ( Src1Reg , <STR_LIT> , * MRI ) ) return false ;

if ( HasCarryIn && ! RBI . constrainGenericRegister ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> , * MRI ) ) return false ;


<s> const unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; const RegisterBank * SrcBank = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForSizeOnBank ( SrcSize , * SrcBank , * MRI ) ; if ( ! SrcRC || ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; const unsigned SrcFlags = getUndefRegState ( Src . isUndef ( ) ) ; ArrayRef < int16_t > SubRegs = TRI . getRegSplitParts ( SrcRC , DstSize / <NUM_LIT> ) ; for ( int I = <NUM_LIT> , E = NumDst ; I != E ; ++ I ) { MachineOperand & Dst = MI . getOperand ( I ) ; BuildMI ( * BB , & MI , DL , TII . get ( TargetOpcode :: COPY ) , Dst . getReg ( ) ) . addReg ( SrcReg , SrcFlags , SubRegs [ I ] ) ; const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ; if ( DstRC && ! RBI . constrainGenericRegister ( Dst . getReg ( ) , * DstRC , * MRI ) ) return false ; } MI . eraseFromParent ( ) ; return true ;


<s> MachineBasicBlock * BB = MI . getParent ( ) ; const int NumDst = MI . getNumOperands ( ) - <NUM_LIT> ; MachineOperand & Src = MI . getOperand ( NumDst ) ; Register SrcReg = Src . getReg ( ) ; Register DstReg0 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DstTy = MRI -> getType ( DstReg0 ) ; LLT SrcTy = MRI -> getType ( SrcReg ) ; const unsigned DstSize = DstTy . getSizeInBits ( ) ; const unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ;

const RegisterBank * SrcBank = RBI . getRegBank ( SrcReg , * MRI , TRI ) ;