<s> unsigned SaveExec = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned TmpExec = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , TmpExec ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , SaveExec ) . addReg ( <STR_LIT> ) ; MachineBasicBlock * LoopBB = MF -> CreateMachineBasicBlock ( ) ; MachineBasicBlock * RemainderBB = MF -> CreateMachineBasicBlock ( ) ; MachineFunction :: iterator MBBI ( MBB ) ; ++ MBBI ; MF -> insert ( MBBI , LoopBB ) ; MF -> insert ( MBBI , RemainderBB ) ; LoopBB -> addSuccessor ( LoopBB ) ; LoopBB -> addSuccessor ( RemainderBB ) ; RemainderBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; RemainderBB -> splice ( RemainderBB -> begin ( ) , & MBB , I , MBB . end ( ) ) ; MBB . addSuccessor ( LoopBB ) ; const MachineOperand * Idx = TII -> getNamedOperand ( MI , <STR_LIT> :: idx ) ; auto InsPt = emitLoadM0FromVGPRLoop ( TII , MRI , MBB , * LoopBB , DL , * Idx , InitResultReg , DstReg , PhiReg , TmpExec , Offset , UseGPRIdxMode , IsIndirectSrc ) ; MachineBasicBlock :: iterator First = RemainderBB -> begin ( ) ; BuildMI ( * RemainderBB , First , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SaveExec ) ;


<s> const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( getTargetMachine ( ) ) ; if ( ASC -> getSrcAddressSpace ( ) == <ISA_LIT>AS :: FLAT_ADDRESS ) { unsigned DestAS = ASC -> getDestAddressSpace ( ) ; if ( DestAS == <ISA_LIT>AS :: LOCAL_ADDRESS || DestAS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) { unsigned NullVal = TM . getNullPointerValue ( DestAS ) ; SDValue SegmentNullPtr = DAG . getConstant ( NullVal , SL , <STR_LIT> ) ; SDValue NonNull = DAG . getSetCC ( SL , <STR_LIT> , Src , FlatNullPtr , <STR_LIT> ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NonNull , Ptr , SegmentNullPtr ) ; } }

if ( ASC -> getDestAddressSpace ( ) == <ISA_LIT>AS :: FLAT_ADDRESS ) {


<s> SDValue Addr = Op . getOperand ( <NUM_LIT> ) ; SDValue Old = Op . getOperand ( <NUM_LIT> ) ; SDValue New = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; MVT SimpleVT = VT . getSimpleVT ( ) ;

MVT VecType = <STR_LIT> ( SimpleVT , <NUM_LIT> ) ;


<s> SetCC = Intr ; Intr = SetCC -> getOperand ( <NUM_LIT> ) . getNode ( ) ; } else { BR = findUser ( BRCOND , <STR_LIT> ) ; Target = BR -> getOperand ( <NUM_LIT> ) ; } unsigned CFNode = isCFIntrinsic ( Intr ) ; if ( CFNode == <NUM_LIT> ) { return BRCOND ; } bool HaveChain = Intr -> getOpcode ( ) == <STR_LIT> || Intr -> getOpcode ( ) == <STR_LIT> ; assert ( ! SetCC || ( SetCC -> getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> && cast < CondCodeSDNode > ( SetCC -> getOperand ( <NUM_LIT> ) . getNode ( ) ) -> get ( ) == <STR_LIT> ) ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( HaveChain ) Ops . push_back ( BRCOND . getOperand ( <NUM_LIT> ) ) ; Ops . append ( Intr -> op_begin ( ) + ( HaveChain ? <NUM_LIT> : <NUM_LIT> ) , Intr -> op_end ( ) ) ; Ops . push_back ( Target ) ; ArrayRef < EVT > Res ( Intr -> value_begin ( ) + <NUM_LIT> , Intr -> value_end ( ) ) ; SDNode * Result = DAG . getNode ( CFNode , DL , DAG . getVTList ( Res ) , Ops ) . getNode ( ) ; if ( ! HaveChain ) { SDValue Ops [ ] = { SDValue ( Result , <NUM_LIT> ) , BRCOND . getOperand ( <NUM_LIT> ) } ; Result = DAG . getMergeValues ( Ops , DL ) . getNode ( ) ; }


<s> EVT VT = Op . getValueType ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { EVT HalfVT = <STR_LIT> ( VT . getVectorElementType ( ) . getSimpleVT ( ) , <NUM_LIT> ) ; SDValue Lo = DAG . getBuildVector ( HalfVT , SL , { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ) ; SDValue Hi = DAG . getBuildVector ( HalfVT , SL , { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ) ; SDValue CastLo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo ) ; SDValue CastHi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi ) ; SDValue Blend = DAG . getBuildVector ( <STR_LIT> , SL , { CastLo , CastHi } ) ; return DAG . getNode ( <STR_LIT> , SL , VT , Blend ) ;


<s> assert ( VT == <STR_LIT> || VT == <STR_LIT> ) ; assert ( ! Subtarget -> hasVOP3PInsts ( ) && <STR_LIT> ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; if ( Hi . isUndef ( ) ) { Lo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo ) ; SDValue ExtLo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo ) ; return DAG . getNode ( <STR_LIT> , SL , VT , ExtLo ) ; } Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi ) ; Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi ) ; SDValue ShlHi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; if ( Lo . isUndef ( ) ) return DAG . getNode ( <STR_LIT> , SL , VT , ShlHi ) ; Lo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo ) ;


<s> } else if ( VA . isMemLoc ( ) ) { report_fatal_error ( <STR_LIT> ) ; } else llvm_unreachable ( <STR_LIT> ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Val ) ; break ; case CCValAssign :: ZExt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ; Val = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Val ) ; break ; case CCValAssign :: SExt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ;


<s> SDLoc SL ( Op ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; if ( Subtarget -> getTrapHandlerAbi ( ) != GCNSubtarget :: TrapHandlerAbiHsa || ! Subtarget -> isTrapHandlerEnabled ( ) ) { DiagnosticInfoUnsupported NoTrap ( MF . getFunction ( ) , <STR_LIT> , Op . getDebugLoc ( ) , DS_Warning ) ; LLVMContext & Ctx = MF . getFunction ( ) . getContext ( ) ; Ctx . diagnose ( NoTrap ) ; return Chain ;


<s> if ( Subtarget -> getTrapHandlerAbi ( ) != GCNSubtarget :: TrapHandlerAbiHsa || ! Subtarget -> isTrapHandlerEnabled ( ) ) { DiagnosticInfoUnsupported NoTrap ( MF . getFunction ( ) , <STR_LIT> , Op . getDebugLoc ( ) , DS_Warning ) ; LLVMContext & Ctx = MF . getFunction ( ) . getContext ( ) ; Ctx . diagnose ( NoTrap ) ; return Chain ; }


<s> unsigned EltSize = EltVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( EltSize ) ) ; MVT IntVT = <STR_LIT> ( VecSize ) ; SDValue ScaleFactor = DAG . getConstant ( Log2_32 ( EltSize ) , SL , <STR_LIT> ) ; SDValue ScaledIdx = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Idx , ScaleFactor ) ; SDValue BC = DAG . getNode ( <STR_LIT> , SL , IntVT , Vec ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , SL , IntVT , BC , ScaledIdx ) ; if ( ResultVT == <STR_LIT> ) { SDValue Result = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Elt ) ; return DAG . getNode ( <STR_LIT> , SL , ResultVT , Result ) ; } return DAG . getAnyExtOrTrunc ( Elt , SL , ResultVT ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerFastUnsafeFDIV ( SDValue Op , SelectionDAG & DAG ) const { SDLoc SL ( Op ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; const SDNodeFlags Flags = Op -> getFlags ( ) ; bool Unsafe = DAG . getTarget ( ) . Options . UnsafeFPMath || Flags . hasAllowReciprocal ( ) ; if ( ! Unsafe && VT == <STR_LIT> && Subtarget -> hasFP32Denormals ( ) ) return SDValue ( ) ; if ( const ConstantFPSDNode * CLHS = dyn_cast < ConstantFPSDNode > ( LHS ) ) { if ( Unsafe || VT == <STR_LIT> || VT == <STR_LIT> ) { if ( CLHS -> isExactlyValue ( <NUM_LIT> ) ) {

if ( RHS . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SL , VT , RHS . getOperand ( <NUM_LIT> ) ) ;


<s> if ( Unsafe || VT == <STR_LIT> || VT == <STR_LIT> ) { if ( CLHS -> isExactlyValue ( <NUM_LIT> ) ) { if ( RHS . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SL , VT , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; } if ( CLHS -> isExactlyValue ( - <NUM_LIT> ) ) { SDValue FNegRHS = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; return DAG . getNode ( <STR_LIT> , SL , VT , FNegRHS ) ; } } }


<s> int CondCode = CD -> getSExtValue ( ) ; if ( CondCode < FCmpInst :: Predicate :: FIRST_FCMP_PREDICATE || CondCode > FCmpInst :: Predicate :: LAST_FCMP_PREDICATE ) { return DAG . getUNDEF ( VT ) ; } SDValue Src0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Src1 = N -> getOperand ( <NUM_LIT> ) ; EVT CmpVT = Src0 . getValueType ( ) ; SDLoc SL ( N ) ; if ( CmpVT == <STR_LIT> && ! TLI . isTypeLegal ( CmpVT ) ) { Src0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src0 ) ; Src1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src1 ) ; } FCmpInst :: Predicate IcInput = static_cast < FCmpInst :: Predicate > ( CondCode ) ; <STR_LIT> CCOpcode = getFCmpCondCode ( IcInput ) ; return DAG . getNode ( <STR_LIT> , SL , VT , Src0 , Src1 , DAG . getCondCode ( CCOpcode ) ) ;


<s> if ( VT == <STR_LIT> ) return LowerFDIV64 ( Op , DAG ) ;

if ( VT == <STR_LIT> ) return LowerFDIV16 ( Op , DAG ) ;


<s> SDValue Src1 = Op . getOperand ( <NUM_LIT> ) ; SDValue CvtSrc0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src0 ) ; SDValue CvtSrc1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src1 ) ; SDValue RcpSrc1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , CvtSrc1 ) ;

SDValue Quot = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , CvtSrc0 , RcpSrc1 ) ;


<s> SDLoc SL ( Op ) ; SDValue X = Op . getOperand ( <NUM_LIT> ) ; SDValue Y = Op . getOperand ( <NUM_LIT> ) ; const SDValue One = DAG . getConstantFP ( <NUM_LIT> , SL , <STR_LIT> ) ; SDVTList ScaleVT = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue DivScale0 = DAG . getNode ( <STR_LIT> , SL , ScaleVT , Y , Y , X ) ; SDValue NegDivScale0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ; SDValue Rcp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ; SDValue Fma0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Rcp , One ) ; SDValue Fma1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Rcp , Fma0 , Rcp ) ; SDValue Fma2 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Fma1 , One ) ; SDValue DivScale1 = DAG . getNode ( <STR_LIT> , SL , ScaleVT , X , Y , X ) ;

SDValue Fma3 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Fma1 , Fma2 , Fma1 ) ;


<s> SDLoc SL ( Op ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue r1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , RHS ) ; const APFloat K0Val ( BitsToFloat ( <NUM_LIT> ) ) ; const SDValue K0 = DAG . getConstantFP ( K0Val , SL , <STR_LIT> ) ; const APFloat K1Val ( BitsToFloat ( <NUM_LIT> ) ) ; const SDValue K1 = DAG . getConstantFP ( K1Val , SL , <STR_LIT> ) ; const SDValue One = DAG . getConstantFP ( <NUM_LIT> , SL , <STR_LIT> ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) ; SDValue r2 = DAG . getSetCC ( SL , SetCCVT , r1 , K0 , <STR_LIT> ) ; SDValue r3 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , r2 , K1 , One ) ; r1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , RHS , r3 ) ; SDValue r0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , r1 ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LHS , r0 ) ;

return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , r3 , Mul ) ;


<s> if ( IsIEEEMode ) return expandFMINNUM_FMAXNUM ( Op . getNode ( ) , DAG ) ; if ( VT == <STR_LIT> ) return splitBinaryVectorOp ( Op , DAG ) ;


<s> SDLoc DL ( Op ) ; SDValue FpToFp16 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FpToFp16 ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Trunc ) ;


<s> if ( GSD -> getAddressSpace ( ) == <ISA_LIT>AS :: LOCAL_ADDRESS || GSD -> getAddressSpace ( ) == <ISA_LIT>AS :: REGION_ADDRESS || GSD -> getAddressSpace ( ) == <ISA_LIT>AS :: PRIVATE_ADDRESS ) return <ISA_LIT>TargetLowering :: LowerGlobalAddress ( MFI , Op , DAG ) ; SDLoc DL ( GSD ) ; EVT PtrVT = Op . getValueType ( ) ; if ( shouldEmitFixup ( GV ) ) return buildPCRelGlobalAddress ( DAG , GV , DL , GSD -> getOffset ( ) , PtrVT ) ; else if ( shouldEmitPCReloc ( GV ) ) return buildPCRelGlobalAddress ( DAG , GV , DL , GSD -> getOffset ( ) , PtrVT , <ISA_LIT>InstrInfo :: MO_REL32 ) ; SDValue GOTAddr = buildPCRelGlobalAddress ( DAG , GV , DL , <NUM_LIT> , PtrVT , <ISA_LIT>InstrInfo :: MO_GOTPCREL32 ) ; Type * Ty = PtrVT . getTypeForEVT ( * DAG . getContext ( ) ) ; PointerType * PtrTy = PointerType :: get ( Ty , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ;

const DataLayout & DataLayout = DAG . getDataLayout ( ) ;


<s> else if ( shouldEmitPCReloc ( GV ) ) return buildPCRelGlobalAddress ( DAG , GV , DL , GSD -> getOffset ( ) , PtrVT , <ISA_LIT>InstrInfo :: MO_REL32 ) ; SDValue GOTAddr = buildPCRelGlobalAddress ( DAG , GV , DL , <NUM_LIT> , PtrVT , <ISA_LIT>InstrInfo :: MO_GOTPCREL32 ) ; Type * Ty = PtrVT . getTypeForEVT ( * DAG . getContext ( ) ) ; PointerType * PtrTy = PointerType :: get ( Ty , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; const DataLayout & DataLayout = DAG . getDataLayout ( ) ;

unsigned Align = DataLayout . getABITypeAlignment ( PtrTy ) ;


<s> if ( CondCode < ICmpInst :: Predicate :: FIRST_ICMP_PREDICATE || CondCode > ICmpInst :: Predicate :: LAST_ICMP_PREDICATE ) return DAG . getUNDEF ( VT ) ; ICmpInst :: Predicate IcInput = static_cast < ICmpInst :: Predicate > ( CondCode ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; EVT CmpVT = LHS . getValueType ( ) ; if ( CmpVT == <STR_LIT> && ! TLI . isTypeLegal ( <STR_LIT> ) ) { unsigned PromoteOp = ICmpInst :: isSigned ( IcInput ) ? <STR_LIT> : <STR_LIT> ; LHS = DAG . getNode ( PromoteOp , DL , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( PromoteOp , DL , <STR_LIT> , RHS ) ; }

<STR_LIT> CCOpcode = getICmpCondCode ( IcInput ) ;


<s> SDValue Param = lowerKernargMemParameter ( DAG , <STR_LIT> , <STR_LIT> , SL , DAG . getEntryNode ( ) , Offset , <NUM_LIT> , false ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Param , DAG . getValueType ( VT ) ) ;


<s> SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = Vec . getValueType ( ) ; EVT EltVT = VecVT . getVectorElementType ( ) ; unsigned VecSize = VecVT . getSizeInBits ( ) ; unsigned EltSize = EltVT . getSizeInBits ( ) ; assert ( VecSize <= <NUM_LIT> ) ; unsigned NumElts = VecVT . getVectorNumElements ( ) ; SDLoc SL ( Op ) ; auto KIdx = dyn_cast < ConstantSDNode > ( Idx ) ; if ( NumElts == <NUM_LIT> && EltSize == <NUM_LIT> && KIdx ) { SDValue BCVec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Vec ) ; SDValue LoHalf = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BCVec , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue HiHalf = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BCVec , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue LoVec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LoHalf ) ; SDValue HiVec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , HiHalf ) ; unsigned Idx = KIdx -> getZExtValue ( ) ; bool InsertLo = Idx < <NUM_LIT> ; SDValue InsHalf = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , InsertLo ? LoVec : HiVec , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , InsVal ) , DAG . getConstant ( InsertLo ? Idx : ( Idx - <NUM_LIT> ) , SL , <STR_LIT> ) ) ; InsHalf = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , InsHalf ) ; SDValue Concat = InsertLo ? DAG . getBuildVector ( <STR_LIT> , SL , { InsHalf , HiHalf } ) : DAG . getBuildVector ( <STR_LIT> , SL , { LoHalf , InsHalf } ) ; return DAG . getNode ( <STR_LIT> , SL , VecVT , Concat ) ; }

if ( isa < ConstantSDNode > ( Idx ) ) return SDValue ( ) ;


<s> auto KIdx = dyn_cast < ConstantSDNode > ( Idx ) ; if ( NumElts == <NUM_LIT> && EltSize == <NUM_LIT> && KIdx ) { SDValue BCVec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Vec ) ; SDValue LoHalf = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BCVec , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue HiHalf = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BCVec , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue LoVec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LoHalf ) ; SDValue HiVec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , HiHalf ) ; unsigned Idx = KIdx -> getZExtValue ( ) ; bool InsertLo = Idx < <NUM_LIT> ; SDValue InsHalf = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , InsertLo ? LoVec : HiVec , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , InsVal ) , DAG . getConstant ( InsertLo ? Idx : ( Idx - <NUM_LIT> ) , SL , <STR_LIT> ) ) ; InsHalf = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , InsHalf ) ; SDValue Concat = InsertLo ? DAG . getBuildVector ( <STR_LIT> , SL , { InsHalf , HiHalf } ) : DAG . getBuildVector ( <STR_LIT> , SL , { LoHalf , InsHalf } ) ; return DAG . getNode ( <STR_LIT> , SL , VecVT , Concat ) ;


<s> Type * Ty = MemVT . getTypeForEVT ( * DAG . getContext ( ) ) ; PointerType * PtrTy = PointerType :: get ( Ty , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ) ; if ( MemVT . getStoreSize ( ) < <NUM_LIT> && Align < <NUM_LIT> ) { int64_t AlignDownOffset = alignDown ( Offset , <NUM_LIT> ) ; int64_t OffsetDiff = Offset - AlignDownOffset ; EVT IntVT = MemVT . changeTypeToInteger ( ) ; SDValue Ptr = lowerKernArgParameterPtr ( DAG , SL , Chain , AlignDownOffset ) ; SDValue Load = DAG . getLoad ( <STR_LIT> , SL , Chain , Ptr , PtrInfo , <NUM_LIT> , MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; SDValue ShiftAmt = DAG . getConstant ( OffsetDiff * <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Load , ShiftAmt ) ; SDValue ArgVal = DAG . getNode ( <STR_LIT> , SL , IntVT , Extract ) ; ArgVal = DAG . getNode ( <STR_LIT> , SL , MemVT , ArgVal ) ; ArgVal = convertArgType ( DAG , VT , MemVT , SL , ArgVal , Signed , Arg ) ; return DAG . getMergeValues ( { ArgVal , Load . getValue ( <NUM_LIT> ) } , SL ) ; } SDValue Ptr = lowerKernArgParameterPtr ( DAG , SL , Chain , Offset ) ; SDValue Load = DAG . getLoad ( MemVT , SL , Chain , Ptr , PtrInfo , Align , MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; SDValue Val = convertArgType ( DAG , VT , MemVT , SL , Load , Signed , Arg ) ; return DAG . getMergeValues ( { Val , Load . getValue ( <NUM_LIT> ) } , SL ) ;


<s> const TargetRegisterClass * RC ; std :: tie ( InputPtrReg , RC ) = Info -> getPreloadedValue ( <STR_LIT> ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; MVT PtrVT = getPointerTy ( DL , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; SDValue BasePtr = DAG . getCopyFromReg ( Chain , SL , MRI . getLiveInVirtReg ( InputPtrReg -> getRegister ( ) ) , PtrVT ) ; return DAG . getObjectPtrOffset ( SL , BasePtr , Offset ) ;


<s> const DataLayout & DL = DAG . getDataLayout ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const ArgDescriptor * InputPtrReg ; const TargetRegisterClass * RC ; std :: tie ( InputPtrReg , RC ) = Info -> getPreloadedValue ( <STR_LIT> ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; MVT PtrVT = getPointerTy ( DL , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; SDValue BasePtr = DAG . getCopyFromReg ( Chain , SL , MRI . getLiveInVirtReg ( InputPtrReg -> getRegister ( ) ) , PtrVT ) ;

return DAG . getObjectPtrOffset ( SL , BasePtr , Offset ) ;


<s> LoadSDNode * Load = cast < LoadSDNode > ( Op ) ; <STR_LIT> ExtType = Load -> getExtensionType ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; if ( ExtType == <STR_LIT> && MemVT . getSizeInBits ( ) < <NUM_LIT> ) { if ( MemVT == <STR_LIT> && isTypeLegal ( <STR_LIT> ) ) return SDValue ( ) ; SDValue Chain = Load -> getChain ( ) ; SDValue BasePtr = Load -> getBasePtr ( ) ; MachineMemOperand * MMO = Load -> getMemOperand ( ) ; EVT RealMemVT = ( MemVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue NewLD = DAG . getExtLoad ( <STR_LIT> , DL , <STR_LIT> , Chain , BasePtr , RealMemVT , MMO ) ; SDValue Ops [ ] = { DAG . getNode ( <STR_LIT> , DL , MemVT , NewLD ) , NewLD . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( Ops , DL ) ; } if ( ! MemVT . isVector ( ) ) return SDValue ( ) ; assert ( Op . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned Alignment = Load -> getAlignment ( ) ; unsigned AS = Load -> getAddressSpace ( ) ; if ( ! allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , MemVT , AS , Alignment ) ) { SDValue Ops [ <NUM_LIT> ] ; std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = expandUnalignedLoad ( Load , DAG ) ; return DAG . getMergeValues ( Ops , DL ) ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( AS == <ISA_LIT>AS :: FLAT_ADDRESS ) AS = MFI -> hasFlatScratchInit ( ) ? <ISA_LIT>AS :: PRIVATE_ADDRESS : <ISA_LIT>AS :: GLOBAL_ADDRESS ; unsigned NumElements = MemVT . getVectorNumElements ( ) ; if ( AS == <ISA_LIT>AS :: CONSTANT_ADDRESS || AS == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) { if ( ! Op -> isDivergent ( ) && Alignment >= <NUM_LIT> && NumElements < <NUM_LIT> ) return SDValue ( ) ; } if ( AS == <ISA_LIT>AS :: CONSTANT_ADDRESS || AS == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT || AS == <ISA_LIT>AS :: GLOBAL_ADDRESS ) { if ( Subtarget -> getScalarizeGlobalBehavior ( ) && ! Op -> isDivergent ( ) && ! Load -> isVolatile ( ) && isMemOpHasNoClobberedMemOperand ( Load ) && Alignment >= <NUM_LIT> && NumElements < <NUM_LIT> ) return SDValue ( ) ; } if ( AS == <ISA_LIT>AS :: CONSTANT_ADDRESS || AS == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT || AS == <ISA_LIT>AS :: GLOBAL_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS ) { if ( NumElements > <NUM_LIT> ) return SplitVectorLoad ( Op , DAG ) ; return SDValue ( ) ; }

if ( AS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) {


<s> Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( ! Info -> isEntryFunction ( ) ) { const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const MCPhysReg * I = TRI -> getCalleeSavedRegsViaCopy ( & DAG . getMachineFunction ( ) ) ; if ( I ) { for ( ; * I ; ++ I ) { if ( <STR_LIT> . contains ( * I ) ) RetOps . push_back ( DAG . getRegister ( * I , <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( * I ) ) RetOps . push_back ( DAG . getRegister ( * I , <STR_LIT> ) ) ; else llvm_unreachable ( <STR_LIT> ) ; } } } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back ( Flag ) ;


<s> SDValue Ops [ ] = { DAG . getEntryNode ( ) , Rsrc , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , { } , { } , { } , DAG . getConstant ( CachePolicy , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , } ; setBufferOffsets ( Offset , DAG , & Ops [ <NUM_LIT> ] , NumLoads > <NUM_LIT> ? <NUM_LIT> * NumLoads : <NUM_LIT> ) ; uint64_t InstOffset = cast < ConstantSDNode > ( Ops [ <NUM_LIT> ] ) -> getZExtValue ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumLoads ; ++ i ) { Ops [ <NUM_LIT> ] = DAG . getConstant ( InstOffset + <NUM_LIT> * i , DL , <STR_LIT> ) ; Loads . push_back ( DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTList , Ops , LoadVT , MMO ) ) ; } if ( VT == <STR_LIT> || VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , Loads ) ; return Loads [ <NUM_LIT> ] ;


<s> SDValue Lo = DAG . getSelect ( DL , <STR_LIT> , Cond , Lo0 , Lo1 ) ; SDValue Hi0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , One ) ; SDValue Hi1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RHS , One ) ; SDValue Hi = DAG . getSelect ( DL , <STR_LIT> , Cond , Hi0 , Hi1 ) ;

SDValue Res = DAG . getBuildVector ( <STR_LIT> , DL , { Lo , Hi } ) ;


<s> unsigned AS = Store -> getAddressSpace ( ) ; if ( ! allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , VT , AS , Store -> getAlignment ( ) ) ) { return expandUnalignedStore ( Store , DAG ) ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( AS == <ISA_LIT>AS :: FLAT_ADDRESS ) AS = MFI -> hasFlatScratchInit ( ) ? <ISA_LIT>AS :: PRIVATE_ADDRESS : <ISA_LIT>AS :: GLOBAL_ADDRESS ; unsigned NumElements = VT . getVectorNumElements ( ) ; if ( AS == <ISA_LIT>AS :: GLOBAL_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS ) { if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; return SDValue ( ) ;

} else if ( AS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) {


<s> unsigned AS = Store -> getAddressSpace ( ) ; if ( ! allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , VT , AS , Store -> getAlignment ( ) ) ) { return expandUnalignedStore ( Store , DAG ) ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( AS == <ISA_LIT>AS :: FLAT_ADDRESS ) AS = MFI -> hasFlatScratchInit ( ) ? <ISA_LIT>AS :: PRIVATE_ADDRESS : <ISA_LIT>AS :: GLOBAL_ADDRESS ; unsigned NumElements = VT . getVectorNumElements ( ) ; if ( AS == <ISA_LIT>AS :: GLOBAL_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS ) { if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; return SDValue ( ) ; } else if ( AS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) { switch ( Subtarget -> getMaxPrivateElementSize ( ) ) { case <NUM_LIT> : return scalarizeVectorStore ( Store , DAG ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; return SDValue ( ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; return SDValue ( ) ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> unsigned UserSGPR = Info -> getQueuePtrUserSGPR ( ) ; assert ( UserSGPR != <STR_LIT> ) ; SDValue QueuePtr = CreateLiveInRegister ( DAG , & <STR_LIT> , UserSGPR , <STR_LIT> ) ; SDValue SGPR01 = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue ToReg = DAG . getCopyToReg ( Chain , SL , SGPR01 , QueuePtr , SDValue ( ) ) ; SDValue Ops [ ] = { ToReg , DAG . getTargetConstant ( GCNSubtarget :: TrapIDLLVMTrap , SL , <STR_LIT> ) , SGPR01 , ToReg . getValue ( <NUM_LIT> ) } ;

return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Ops ) ;


<s> if ( Subtarget -> getTrapHandlerAbi ( ) != GCNSubtarget :: TrapHandlerAbiHsa || ! Subtarget -> isTrapHandlerEnabled ( ) ) return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Chain ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;

unsigned UserSGPR = Info -> getQueuePtrUserSGPR ( ) ;


<s> EVT VT = Op . getValueType ( ) ; SDValue Arg = Op . getOperand ( <NUM_LIT> ) ; SDValue TrigVal ; SDValue OneOver2Pi = DAG . getConstantFP ( <NUM_LIT> / M_PI , DL , VT ) ; if ( Subtarget -> hasTrigReducedRange ( ) ) { SDValue MulVal = DAG . getNode ( <STR_LIT> , DL , VT , Arg , OneOver2Pi ) ; TrigVal = DAG . getNode ( <STR_LIT> , DL , VT , MulVal ) ; } else { TrigVal = DAG . getNode ( <STR_LIT> , DL , VT , Arg , OneOver2Pi ) ; } switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , TrigVal ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , TrigVal ) ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> if ( <STR_LIT> ( ParentFn -> getCallingConv ( ) ) ) return false ;

auto Attr = ParentFn -> getFnAttribute ( <STR_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { if ( ! CI -> isTailCall ( ) ) return false ; const Function * ParentFn = CI -> getParent ( ) -> getParent ( ) ; if ( <STR_LIT> ( ParentFn -> getCallingConv ( ) ) ) return false ; auto Attr = ParentFn -> getFnAttribute ( <STR_LIT> ) ;

return ( Attr . getValueAsString ( ) != <STR_LIT> ) ;


<s> static bool mayTailCallThisCC ( CallingConv :: ID CC ) {


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> SDLoc DL ( CachePolicy ) ; if ( GLC ) { * GLC = DAG . getTargetConstant ( ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> , DL , <STR_LIT> ) ; Value &= ~ ( uint64_t ) <NUM_LIT> ; } if ( SLC ) { * SLC = DAG . getTargetConstant ( ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> , DL , <STR_LIT> ) ;


<s> const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; auto & ArgUsageInfo = DAG . getPass ( ) -> getAnalysis < <ISA_LIT>ArgumentUsageInfo > ( ) ; const <ISA_LIT>FunctionArgInfo & CalleeArgInfo = ArgUsageInfo . lookupFuncArgInfo ( * CalleeFunc ) ; const <ISA_LIT>FunctionArgInfo & CallerArgInfo = Info . getArgInfo ( ) ; <STR_LIT> InputRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; for ( auto InputID : InputRegs ) { const ArgDescriptor * OutgoingArg ; const TargetRegisterClass * ArgRC ; std :: tie ( OutgoingArg , ArgRC ) = CalleeArgInfo . getPreloadedValue ( InputID ) ; if ( ! OutgoingArg ) continue ; const ArgDescriptor * IncomingArg ; const TargetRegisterClass * IncomingArgRC ; std :: tie ( IncomingArg , IncomingArgRC ) = CallerArgInfo . getPreloadedValue ( InputID ) ; assert ( IncomingArgRC == ArgRC ) ; EVT ArgVT = TRI -> getSpillSize ( * ArgRC ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue InputReg ; if ( IncomingArg ) { InputReg = loadInputValue ( DAG , ArgRC , ArgVT , DL , * IncomingArg ) ; } else { assert ( InputID == <STR_LIT> ) ; InputReg = getImplicitArgPtr ( DAG , DL ) ; } if ( OutgoingArg -> isRegister ( ) ) { RegsToPass . emplace_back ( OutgoingArg -> getRegister ( ) , InputReg ) ; } else { unsigned SpecialArgOffset = CCInfo . AllocateStack ( ArgVT . getStoreSize ( ) , <NUM_LIT> ) ;

SDValue ArgStore = storeStackInputValue ( DAG , DL , Chain , InputReg , SpecialArgOffset ) ;


<s> if ( ( LHSOpc == <STR_LIT> && Opc == <STR_LIT> ) || ( LHSOpc == <STR_LIT> && Opc == <STR_LIT> ) ) { SDValue Args [ ] = { LHS . getOperand ( <NUM_LIT> ) , LHS . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; return DAG . getNode ( Opc , SDLoc ( N ) , N -> getVTList ( ) , Args ) ;


<s> SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( ( LHS . getOpcode ( ) == <STR_LIT> || RHS . getOpcode ( ) == <STR_LIT> ) && Subtarget -> hasMad64_32 ( ) && ! VT . isVector ( ) && VT . getScalarSizeInBits ( ) > <NUM_LIT> && VT . getScalarSizeInBits ( ) <= <NUM_LIT> ) { if ( LHS . getOpcode ( ) != <STR_LIT> ) std :: swap ( LHS , RHS ) ; SDValue MulLHS = LHS . getOperand ( <NUM_LIT> ) ; SDValue MulRHS = LHS . getOperand ( <NUM_LIT> ) ; SDValue AddRHS = RHS ; if ( numBitsUnsigned ( MulLHS , DAG ) <= <NUM_LIT> && numBitsUnsigned ( MulRHS , DAG ) <= <NUM_LIT> ) { MulLHS = DAG . getZExtOrTrunc ( MulLHS , SL , <STR_LIT> ) ; MulRHS = DAG . getZExtOrTrunc ( MulRHS , SL , <STR_LIT> ) ; AddRHS = DAG . getZExtOrTrunc ( AddRHS , SL , <STR_LIT> ) ; return getMad64_32 ( DAG , SL , VT , MulLHS , MulRHS , AddRHS , false ) ;


<s> return getMad64_32 ( DAG , SL , VT , MulLHS , MulRHS , AddRHS , true ) ; } return SDValue ( ) ; } if ( VT != <STR_LIT> || ! DCI . isAfterLegalizeDAG ( ) ) return SDValue ( ) ; unsigned Opc = LHS . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) std :: swap ( RHS , LHS ) ; Opc = RHS . getOpcode ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { auto Cond = RHS . getOperand ( <NUM_LIT> ) ; if ( ! isBoolSGPR ( Cond ) ) break ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Args [ ] = { LHS , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) , Cond } ; Opc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , SL , VTList , Args ) ; } case <STR_LIT> : {

auto C = dyn_cast < ConstantSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) ;


<s> APFloat Zero = APFloat :: getZero ( F . getSemantics ( ) ) ; APFloat :: cmpResult Cmp0 = F . compare ( Zero ) ; if ( Cmp0 == APFloat :: cmpLessThan || ( Cmp0 == APFloat :: cmpUnordered && Subtarget -> enableDX10Clamp ( ) ) ) { return DCI . DAG . getConstantFP ( Zero , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; } APFloat One ( F . getSemantics ( ) , <STR_LIT> ) ; APFloat :: cmpResult Cmp1 = F . compare ( One ) ;

if ( Cmp1 == APFloat :: cmpGreaterThan ) return DCI . DAG . getConstantFP ( One , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ;


<s> APFloat Zero = APFloat :: getZero ( F . getSemantics ( ) ) ; APFloat :: cmpResult Cmp0 = F . compare ( Zero ) ; if ( Cmp0 == APFloat :: cmpLessThan || ( Cmp0 == APFloat :: cmpUnordered && Subtarget -> enableDX10Clamp ( ) ) ) { return DCI . DAG . getConstantFP ( Zero , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; }

APFloat One ( F . getSemantics ( ) , <STR_LIT> ) ;


<s> SelectionDAG & DAG = DCI . DAG ; SDValue Mask = N -> getOperand ( <NUM_LIT> ) ;

if ( const ConstantSDNode * CMask = dyn_cast < ConstantSDNode > ( Mask ) ) {


<s> return DAG . getNode ( <STR_LIT> + SrcOffset / <NUM_LIT> , SL , <STR_LIT> , Srl ) ; } } } APInt Demanded = APInt :: getBitsSet ( <NUM_LIT> , <NUM_LIT> * Offset , <NUM_LIT> * Offset + <NUM_LIT> ) ; KnownBits Known ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . ShrinkDemandedConstant ( Src , Demanded , TLO ) || TLI . SimplifyDemandedBits ( Src , Demanded , Known , TLO ) ) { DCI . CommitTargetLoweringOpt ( TLO ) ;


<s> if ( Srl . getOpcode ( ) == <STR_LIT> ) { if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Srl . getOperand ( <NUM_LIT> ) ) ) { Srl = DAG . getZExtOrTrunc ( Srl . getOperand ( <NUM_LIT> ) , SDLoc ( Srl . getOperand ( <NUM_LIT> ) ) , EVT ( <STR_LIT> ) ) ; unsigned SrcOffset = C -> getZExtValue ( ) + <NUM_LIT> * Offset ; if ( SrcOffset < <NUM_LIT> && SrcOffset % <NUM_LIT> == <NUM_LIT> ) { return DAG . getNode ( <STR_LIT> + SrcOffset / <NUM_LIT> , SL , <STR_LIT> , Srl ) ; } } } APInt Demanded = APInt :: getBitsSet ( <NUM_LIT> , <NUM_LIT> * Offset , <NUM_LIT> * Offset + <NUM_LIT> ) ; KnownBits Known ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ;

if ( TLI . ShrinkDemandedConstant ( Src , Demanded , TLO ) || TLI . SimplifyDemandedBits ( Src , Demanded , Known , TLO ) ) {


<s> SDValue Src1 = N -> getOperand ( <NUM_LIT> ) ; if ( Src0 . isUndef ( ) && Src1 . isUndef ( ) ) return DCI . DAG . getUNDEF ( N -> getValueType ( <NUM_LIT> ) ) ;


<s> return performSetCCCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performMinMaxCombine ( N , DCI ) ; case <STR_LIT> : return performFMACombine ( N , DCI ) ; case <STR_LIT> : { if ( SDValue Widended = widenLoad ( cast < LoadSDNode > ( N ) , DCI ) ) return Widended ; LLVM_FALLTHROUGH ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( DCI . isBeforeLegalize ( ) ) break ; return performMemSDNodeCombine ( cast < MemSDNode > ( N ) , DCI ) ; case <STR_LIT> : return performAndCombine ( N , DCI ) ; case <STR_LIT> : return performOrCombine ( N , DCI ) ; case <STR_LIT> : return performXorCombine ( N , DCI ) ; case <STR_LIT> : return performZeroExtendCombine ( N , DCI ) ; case <STR_LIT> : return performClassCombine ( N , DCI ) ; case <STR_LIT> : return performFCanonicalizeCombine ( N , DCI ) ; case <STR_LIT> : return performRcpCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . isUndef ( ) ) return Src ; break ; } case <STR_LIT> : case <STR_LIT> : return performUCharToFloatCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :

return performCvtF32UByteNCombine ( N , DCI ) ;


<s> } } unsigned VecSize = VecVT . getSizeInBits ( ) ; unsigned EltSize = EltVT . getSizeInBits ( ) ; if ( VecSize <= <NUM_LIT> && ( VecSize > <NUM_LIT> || EltSize >= <NUM_LIT> ) && ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) { SDLoc SL ( N ) ; SDValue Idx = N -> getOperand ( <NUM_LIT> ) ; EVT IdxVT = Idx . getValueType ( ) ; SDValue V ; for ( unsigned I = <NUM_LIT> , E = VecVT . getVectorNumElements ( ) ; I < E ; ++ I ) { SDValue IC = DAG . getConstant ( I , SL , IdxVT ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , SL , EltVT , Vec , IC ) ; if ( I == <NUM_LIT> ) V = Elt ; else V = DAG . getSelectCC ( SL , Idx , IC , Elt , V , <STR_LIT> ) ; } return V ; } if ( ! DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; auto * Idx = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( isa < MemSDNode > ( Vec ) && EltSize <= <NUM_LIT> && EltVT . isByteSized ( ) && VecSize > <NUM_LIT> && VecSize % <NUM_LIT> == <NUM_LIT> && Idx ) { EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VecVT ) ; unsigned BitIndex = Idx -> getZExtValue ( ) * EltSize ; unsigned EltIdx = BitIndex / <NUM_LIT> ; unsigned LeftoverBitIdx = BitIndex % <NUM_LIT> ; SDLoc SL ( N ) ; SDValue Cast = DAG . getNode ( <STR_LIT> , SL , NewVT , Vec ) ; DCI . AddToWorklist ( Cast . getNode ( ) ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Cast , DAG . getConstant ( EltIdx , SL , <STR_LIT> ) ) ; DCI . AddToWorklist ( Elt . getNode ( ) ) ; SDValue Srl = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Elt , DAG . getConstant ( LeftoverBitIdx , SL , <STR_LIT> ) ) ; DCI . AddToWorklist ( Srl . getNode ( ) ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , SL , EltVT . changeTypeToInteger ( ) , Srl ) ; DCI . AddToWorklist ( Trunc . getNode ( ) ) ; return DAG . getNode ( <STR_LIT> , SL , EltVT , Trunc ) ;


<s> SDValue <ISA_LIT>TargetLowering :: performExtractVectorEltCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SDValue Vec = N -> getOperand ( <NUM_LIT> ) ; SelectionDAG & DAG = DCI . DAG ; EVT VecVT = Vec . getValueType ( ) ; EVT EltVT = VecVT . getVectorElementType ( ) ; if ( ( Vec . getOpcode ( ) == <STR_LIT> || Vec . getOpcode ( ) == <STR_LIT> ) && allUsesHaveSourceMods ( N ) ) { SDLoc SL ( N ) ; EVT EltVT = N -> getValueType ( <NUM_LIT> ) ; SDValue Idx = N -> getOperand ( <NUM_LIT> ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , SL , EltVT , Vec . getOperand ( <NUM_LIT> ) , Idx ) ; return DAG . getNode ( Vec . getOpcode ( ) , SL , EltVT , Elt ) ; } if ( Vec . hasOneUse ( ) && DCI . isBeforeLegalize ( ) ) { SDLoc SL ( N ) ; EVT EltVT = N -> getValueType ( <NUM_LIT> ) ; SDValue Idx = N -> getOperand ( <NUM_LIT> ) ; unsigned Opc = Vec . getOpcode ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Elt0 = DAG . getNode ( <STR_LIT> , SL , EltVT , Vec . getOperand ( <NUM_LIT> ) , Idx ) ; SDValue Elt1 = DAG . getNode ( <STR_LIT> , SL , EltVT , Vec . getOperand ( <NUM_LIT> ) , Idx ) ; DCI . AddToWorklist ( Elt0 . getNode ( ) ) ; DCI . AddToWorklist ( Elt1 . getNode ( ) ) ; return DAG . getNode ( Opc , SL , EltVT , Elt0 , Elt1 , Vec -> getFlags ( ) ) ; } }


<s> unsigned FusedOp = getFusedOpcode ( DAG , N , LHS . getNode ( ) ) ; if ( FusedOp != <NUM_LIT> ) { const SDValue Two = DAG . getConstantFP ( <NUM_LIT> , SL , VT ) ; return DAG . getNode ( FusedOp , SL , VT , A , Two , RHS ) ; } } } if ( RHS . getOpcode ( ) == <STR_LIT> ) { SDValue A = RHS . getOperand ( <NUM_LIT> ) ; if ( A == RHS . getOperand ( <NUM_LIT> ) ) { unsigned FusedOp = getFusedOpcode ( DAG , N , RHS . getNode ( ) ) ; if ( FusedOp != <NUM_LIT> ) { const SDValue Two = DAG . getConstantFP ( <NUM_LIT> , SL , VT ) ; return DAG . getNode ( FusedOp , SL , VT , A , Two , LHS ) ; }


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( N0 . isUndef ( ) ) { APFloat QNaN = APFloat :: getQNaN ( SelectionDAG :: EVTToAPFloatSemantics ( VT ) ) ; return DAG . getConstantFP ( QNaN , SDLoc ( N ) , VT ) ; } if ( ConstantFPSDNode * CFP = isConstOrConstSplatFP ( N0 ) ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; return getCanonicalConstantFP ( DAG , SDLoc ( N ) , VT , CFP -> getValueAPF ( ) ) ; } if ( N0 . getOpcode ( ) == <STR_LIT> && VT == <STR_LIT> && isTypeLegal ( <STR_LIT> ) ) { SDLoc SL ( N ) ; SDValue NewElts [ <NUM_LIT> ] ; SDValue Lo = N0 . getOperand ( <NUM_LIT> ) ; SDValue Hi = N0 . getOperand ( <NUM_LIT> ) ; EVT EltVT = Lo . getValueType ( ) ; if ( vectorEltWillFoldAway ( Lo ) || vectorEltWillFoldAway ( Hi ) ) { for ( unsigned I = <NUM_LIT> ; I != <NUM_LIT> ; ++ I ) { SDValue Op = N0 . getOperand ( I ) ;

if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Op ) ) {


<s> SDValue <ISA_LIT>TargetLowering :: performFMACombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc SL ( N ) ; if ( ! Subtarget -> hasDLInsts ( ) || VT != <STR_LIT> ) return SDValue ( ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op2 = N -> getOperand ( <NUM_LIT> ) ; SDValue FMA = N -> getOperand ( <NUM_LIT> ) ; if ( FMA . getOpcode ( ) != <STR_LIT> || Op1 . getOpcode ( ) != <STR_LIT> || Op2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; const TargetOptions & Options = DAG . getTarget ( ) . Options ; if ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath || ( N -> getFlags ( ) . hasAllowContract ( ) && FMA -> getFlags ( ) . hasAllowContract ( ) ) ) { Op1 = Op1 . getOperand ( <NUM_LIT> ) ;


<s> SDValue Src1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Src2 = N -> getOperand ( <NUM_LIT> ) ; if ( isClampZeroToOne ( Src0 , Src1 ) ) { return DAG . getNode ( <STR_LIT> , SL , VT , Src2 ) ; } if ( Subtarget -> enableDX10Clamp ( ) ) {

if ( isa < ConstantFPSDNode > ( Src0 ) && ! isa < ConstantFPSDNode > ( Src1 ) ) std :: swap ( Src0 , Src1 ) ;


<s> APFloat :: cmpResult Cmp = K0 -> getValueAPF ( ) . compare ( K1 -> getValueAPF ( ) ) ; if ( Cmp == APFloat :: cmpGreaterThan ) return SDValue ( ) ; EVT VT = Op0 . getValueType ( ) ; if ( Subtarget -> enableDX10Clamp ( ) ) { if ( K1 -> isExactlyValue ( <NUM_LIT> ) && K0 -> isExactlyValue ( <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , SL , VT , Op0 . getOperand ( <NUM_LIT> ) ) ; }

if ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget -> hasMed3_16 ( ) ) ) {


<s> if ( ! K0 ) return SDValue ( ) ; APFloat :: cmpResult Cmp = K0 -> getValueAPF ( ) . compare ( K1 -> getValueAPF ( ) ) ; if ( Cmp == APFloat :: cmpGreaterThan ) return SDValue ( ) ; EVT VT = Op0 . getValueType ( ) ; if ( Subtarget -> enableDX10Clamp ( ) ) { if ( K1 -> isExactlyValue ( <NUM_LIT> ) && K0 -> isExactlyValue ( <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , SL , VT , Op0 . getOperand ( <NUM_LIT> ) ) ; } if ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget -> hasMed3_16 ( ) ) ) { SDValue Var = Op0 . getOperand ( <NUM_LIT> ) ; if ( ! DAG . isKnownNeverSNaN ( Var ) ) return SDValue ( ) ; const <ISA_LIT>InstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; if ( ( ! K0 -> hasOneUse ( ) || TII -> isInlineConstant ( K0 -> getValueAPF ( ) . bitcastToAPInt ( ) ) ) && ( ! K1 -> hasOneUse ( ) || TII -> isInlineConstant ( K1 -> getValueAPF ( ) . bitcastToAPInt ( ) ) ) ) {

return DAG . getNode ( <STR_LIT> , SL , K0 -> getValueType ( <NUM_LIT> ) , Var , SDValue ( K0 , <NUM_LIT> ) , SDValue ( K1 , <NUM_LIT> ) ) ;


<s> SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> ) { SDValue A = LHS . getOperand ( <NUM_LIT> ) ; if ( A == LHS . getOperand ( <NUM_LIT> ) ) { unsigned FusedOp = getFusedOpcode ( DAG , N , LHS . getNode ( ) ) ; if ( FusedOp != <NUM_LIT> ) { const SDValue Two = DAG . getConstantFP ( <NUM_LIT> , SL , VT ) ; SDValue NegRHS = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; return DAG . getNode ( FusedOp , SL , VT , A , Two , NegRHS ) ; } } } if ( RHS . getOpcode ( ) == <STR_LIT> ) { SDValue A = RHS . getOperand ( <NUM_LIT> ) ; if ( A == RHS . getOperand ( <NUM_LIT> ) ) { unsigned FusedOp = getFusedOpcode ( DAG , N , RHS . getNode ( ) ) ; if ( FusedOp != <NUM_LIT> ) { const SDValue NegTwo = DAG . getConstantFP ( - <NUM_LIT> , SL , VT ) ; return DAG . getNode ( FusedOp , SL , VT , A , NegTwo , LHS ) ; }


<s> SelectionDAG & DAG = DCI . DAG ; SDLoc SL ( N ) ; SDValue Ins = N -> getOperand ( <NUM_LIT> ) ; EVT IdxVT = Idx . getValueType ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned I = <NUM_LIT> , E = VecVT . getVectorNumElements ( ) ; I < E ; ++ I ) { SDValue IC = DAG . getConstant ( I , SL , IdxVT ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , SL , EltVT , Vec , IC ) ; SDValue V = DAG . getSelectCC ( SL , Idx , IC , Ins , Elt , <STR_LIT> ) ; Ops . push_back ( V ) ; }

return DAG . getBuildVector ( VecVT , SL , Ops ) ;


<s> if ( ! K0 ) return SDValue ( ) ; if ( Signed ) { if ( K0 -> getAPIntValue ( ) . sge ( K1 -> getAPIntValue ( ) ) ) return SDValue ( ) ; } else { if ( K0 -> getAPIntValue ( ) . uge ( K1 -> getAPIntValue ( ) ) ) return SDValue ( ) ; } EVT VT = K0 -> getValueType ( <NUM_LIT> ) ; unsigned Med3Opc = Signed ? <STR_LIT> : <STR_LIT> ; if ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget -> hasMed3_16 ( ) ) ) { return DAG . getNode ( Med3Opc , SL , VT , Op0 . getOperand ( <NUM_LIT> ) , SDValue ( K0 , <NUM_LIT> ) , SDValue ( K1 , <NUM_LIT> ) ) ; } MVT NVT = <STR_LIT> ;

unsigned ExtOp = Signed ? <STR_LIT> : <STR_LIT> ;


<s> if ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget -> hasMed3_16 ( ) ) ) { return DAG . getNode ( Med3Opc , SL , VT , Op0 . getOperand ( <NUM_LIT> ) , SDValue ( K0 , <NUM_LIT> ) , SDValue ( K1 , <NUM_LIT> ) ) ; } MVT NVT = <STR_LIT> ; unsigned ExtOp = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Tmp1 = DAG . getNode ( ExtOp , SL , NVT , Op0 -> getOperand ( <NUM_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( ExtOp , SL , NVT , Op0 -> getOperand ( <NUM_LIT> ) ) ; SDValue Tmp3 = DAG . getNode ( ExtOp , SL , NVT , Op1 ) ;

SDValue Med3 = DAG . getNode ( Med3Opc , SL , NVT , Tmp1 , Tmp2 , Tmp3 ) ;


<s> SDValue Ptr = N -> getBasePtr ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc SL ( N ) ; if ( Ptr . getOpcode ( ) == <STR_LIT> ) { SDValue NewPtr = performSHLPtrCombine ( Ptr . getNode ( ) , N -> getAddressSpace ( ) , N -> getMemoryVT ( ) , DCI ) ; if ( NewPtr ) { SmallVector < SDValue , <NUM_LIT> > NewOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; NewOps [ N -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ] = NewPtr ;

return SDValue ( DAG . UpdateNodeOperands ( N , NewOps ) , <NUM_LIT> ) ;


<s> SmallVector < SDValue , <NUM_LIT> > NewOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; NewOps [ N -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ] = NewPtr ; return SDValue ( DAG . UpdateNodeOperands ( N , NewOps ) , <NUM_LIT> ) ; } } return SDValue ( ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned Opc = N -> getOpcode ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && ! VT . isVector ( ) && VT != <STR_LIT> && ( ( VT != <STR_LIT> && VT != <STR_LIT> ) || Subtarget -> hasMin3Max3_16 ( ) ) ) { if ( Op0 . getOpcode ( ) == Opc && Op0 . hasOneUse ( ) ) { SDLoc DL ( N ) ; return DAG . getNode ( minMaxOpcToMin3Max3Opc ( Opc ) , DL , N -> getValueType ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) , Op1 ) ; } if ( Op1 . getOpcode ( ) == Opc && Op1 . hasOneUse ( ) ) { SDLoc DL ( N ) ; return DAG . getNode ( minMaxOpcToMin3Max3Opc ( Opc ) , DL , N -> getValueType ( <NUM_LIT> ) , Op0 , Op1 . getOperand ( <NUM_LIT> ) , Op1 . getOperand ( <NUM_LIT> ) ) ; } } if ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) ) { if ( SDValue Med3 = performIntMed3ImmCombine ( DAG , SDLoc ( N ) , Op0 , Op1 , true ) ) return Med3 ; }


<s> if ( VT == <STR_LIT> && ( N0 . getOpcode ( ) == <STR_LIT> || N0 . getOpcode ( ) == <STR_LIT> ) ) {

return DCI . DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N0 , N -> getFlags ( ) ) ;


if ( VT == <STR_LIT> && ( N0 . getOpcode ( ) == <STR_LIT> || N0 . getOpcode ( ) == <STR_LIT> ) ) {


<s> if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && LHS . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) && LHS . getConstantOperandVal ( <NUM_LIT> ) != LHS . getConstantOperandVal ( <NUM_LIT> ) && isBoolSGPR ( LHS . getOperand ( <NUM_LIT> ) ) ) { uint64_t CT = LHS . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t CF = LHS . getConstantOperandVal ( <NUM_LIT> ) ; if ( ( CF == CRHSVal && CC == <STR_LIT> ) || ( CT == CRHSVal && CC == <STR_LIT> ) ) return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LHS . getOperand ( <NUM_LIT> ) , DAG . getConstant ( - <NUM_LIT> , SL , <STR_LIT> ) ) ; if ( ( CF == CRHSVal && CC == <STR_LIT> ) || ( CT == CRHSVal && CC == <STR_LIT> ) ) return LHS . getOperand ( <NUM_LIT> ) ; } } if ( VT != <STR_LIT> && VT != <STR_LIT> && ( Subtarget -> has16BitInsts ( ) && VT != <STR_LIT> ) ) return SDValue ( ) ; if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && LHS . getOpcode ( ) == <STR_LIT> ) { const ConstantFPSDNode * CRHS = dyn_cast < ConstantFPSDNode > ( RHS ) ; if ( ! CRHS ) return SDValue ( ) ; const APFloat & APF = CRHS -> getValueAPF ( ) ; if ( APF . isInfinity ( ) && ! APF . isNegative ( ) ) { const unsigned IsInfMask = <STR_LIT> | <STR_LIT> ;


<s> SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( ( N0 . getOpcode ( ) != <STR_LIT> && N0 . getOpcode ( ) != <STR_LIT> ) || N0 -> hasOneUse ( ) ) return SDValue ( ) ; const ConstantSDNode * CN1 = dyn_cast < ConstantSDNode > ( N1 ) ; if ( ! CN1 ) return SDValue ( ) ; const ConstantSDNode * CAdd = dyn_cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; if ( ! CAdd ) return SDValue ( ) ; APInt Offset = CAdd -> getAPIntValue ( ) << CN1 -> getAPIntValue ( ) ; Type * Ty = MemVT . getTypeForEVT ( * DCI . DAG . getContext ( ) ) ; AddrMode AM ; AM . HasBaseReg = true ; AM . BaseOffs = Offset . getSExtValue ( ) ; if ( ! isLegalAddressingMode ( DCI . DAG . getDataLayout ( ) , AM , Ty , AddrSpace ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc SL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue ShlX = DAG . getNode ( <STR_LIT> , SL , VT , N0 . getOperand ( <NUM_LIT> ) , N1 ) ; SDValue COffset = DAG . getConstant ( Offset , SL , <STR_LIT> ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; SDLoc SL ( N ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; unsigned Opc = LHS . getOpcode ( ) ; if ( Opc != <STR_LIT> ) std :: swap ( RHS , LHS ) ; if ( LHS . getOpcode ( ) == <STR_LIT> ) { auto C = dyn_cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) ; if ( ! C || C -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ;

SDValue Args [ ] = { LHS . getOperand ( <NUM_LIT> ) , RHS , LHS . getOperand ( <NUM_LIT> ) } ;


<s> SDLoc DL ( N ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; if ( DCI . isAfterLegalizeDAG ( ) && SrcVT == <STR_LIT> ) {

if ( DAG . MaskedValueIsZero ( Src , APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ) {


<s> if ( DAG . MaskedValueIsZero ( Src , APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ) { SDValue Cvt = DAG . getNode ( <STR_LIT> , DL , VT , Src ) ; DCI . AddToWorklist ( Cvt . getNode ( ) ) ; return Cvt ; } } return SDValue ( ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; const ConstantSDNode * CRHS = dyn_cast < ConstantSDNode > ( RHS ) ; if ( CRHS ) { if ( SDValue Split = splitBinaryBitConstantOp ( DCI , SDLoc ( N ) , <STR_LIT> , LHS , CRHS ) ) return Split ;


<s> SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ;

const ConstantSDNode * CRHS = dyn_cast < ConstantSDNode > ( RHS ) ;


<s> SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( Src . getOpcode ( ) == <STR_LIT> ) { SDValue BCSrc = Src . getOperand ( <NUM_LIT> ) ; if ( BCSrc . getValueType ( ) == <STR_LIT> && fp16SrcZerosHighBits ( BCSrc . getOpcode ( ) ) ) return DCI . DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , BCSrc ) ; } return SDValue ( ) ;


<s> if ( VT != <STR_LIT> ) return SDValue ( ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( Src . getOpcode ( ) == <STR_LIT> ) {

SDValue BCSrc = Src . getOperand ( <NUM_LIT> ) ;


<s> const <ISA_LIT>InstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; unsigned Opcode = Node -> getMachineOpcode ( ) ; if ( TII -> isMIMG ( Opcode ) && ! TII -> get ( Opcode ) . mayStore ( ) && ! TII -> isGather4 ( Opcode ) ) { return adjustWritemask ( Node , DAG ) ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { legalizeTargetIndependentNode ( Node , DAG ) ; return Node ; } switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : { SDValue Src0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Src1 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Src2 = Node -> getOperand ( <NUM_LIT> ) ; if ( ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) != <STR_LIT> ) && ( Src0 == Src1 || Src0 == Src2 ) ) break ; MVT VT = Src0 . getValueType ( ) . getSimpleVT ( ) ; const TargetRegisterClass * RC = getRegClassFor ( VT ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue UndefReg = DAG . getRegister ( MRI . createVirtualRegister ( RC ) , VT ) ; SDValue ImpDef = DAG . getCopyToReg ( DAG . getEntryNode ( ) , SDLoc ( Node ) , UndefReg , Src0 , SDValue ( ) ) ; if ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) == <STR_LIT> ) { if ( Src1 . isMachineOpcode ( ) && Src1 . getMachineOpcode ( ) != <STR_LIT> ) Src0 = Src1 ; else if ( Src2 . isMachineOpcode ( ) && Src2 . getMachineOpcode ( ) != <STR_LIT> ) Src0 = Src2 ; else { assert ( Src1 . getMachineOpcode ( ) == <STR_LIT> ) ; Src0 = UndefReg ;


<s> if ( Arg -> Flags . isSplit ( ) ) { while ( ! Arg -> Flags . isSplitEnd ( ) ) { assert ( ! Arg -> VT . isVector ( ) && <STR_LIT> ) ; if ( ! SkipArg ) Splits . push_back ( * Arg ) ; Arg = & Ins [ ++ I ] ; } } if ( SkipArg ) { Skipped . set ( Arg -> getOrigArgIndex ( ) ) ; ++ P<ISA_LIT>nputNum ; continue ; }

Info -> markP<ISA_LIT>nputAllocated ( P<ISA_LIT>nputNum ) ;


<s> Results . push_back ( DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Cvt ) ) ; } return ; } } break ; } case <STR_LIT> : { if ( SDValue Res = LowerINTRIN<ISA_LIT>C_W_CHAIN ( SDValue ( N , <NUM_LIT> ) , DAG ) ) { Results . push_back ( Res ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; return ; } break ; } case <STR_LIT> : { SDLoc SL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue LHS = DAG . getNode ( <STR_LIT> , SL , NewVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getNode ( <STR_LIT> , SL , NewVT , N -> getOperand ( <NUM_LIT> ) ) ; EVT SelectVT = NewVT ; if ( NewVT . bitsLT ( <STR_LIT> ) ) { LHS = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , RHS ) ; SelectVT = <STR_LIT> ; } SDValue NewSelect = DAG . getNode ( <STR_LIT> , SL , SelectVT , N -> getOperand ( <NUM_LIT> ) , LHS , RHS ) ; if ( NewVT != SelectVT ) NewSelect = DAG . getNode ( <STR_LIT> , SL , NewVT , NewSelect ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , SL , VT , NewSelect ) ) ; return ; } case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) break ; SDLoc SL ( N ) ; SDValue BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Op = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BC , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Op ) ) ; return ; } case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) break ; SDLoc SL ( N ) ; SDValue BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Op = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BC , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Op ) ) ; return ; } default : break ;


<s> } case <STR_LIT> : { if ( SDValue Res = lowerEXTRACT_VECTOR_ELT ( SDValue ( N , <NUM_LIT> ) , DAG ) ) Results . push_back ( Res ) ; return ; } case <STR_LIT> : { unsigned IID = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IID ) { case <STR_LIT> : { SDValue Src0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Src1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc SL ( N ) ; SDValue Cvt = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src0 , Src1 ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Cvt ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Src0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Src1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc SL ( N ) ; unsigned Opcode ; if ( IID == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( IID == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( IID == <STR_LIT> ) Opcode = <STR_LIT> ; else Opcode = <STR_LIT> ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( isTypeLegal ( VT ) ) Results . push_back ( DAG . getNode ( Opcode , SL , VT , Src0 , Src1 ) ) ; else { SDValue Cvt = DAG . getNode ( Opcode , SL , <STR_LIT> , Src0 , Src1 ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Cvt ) ) ; } return ; } } break ; } case <STR_LIT> : {

if ( SDValue Res = LowerINTRIN<ISA_LIT>C_W_CHAIN ( SDValue ( N , <NUM_LIT> ) , DAG ) ) {


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; bool HasStackObjects = MFI . hasStackObjects ( ) ; if ( HasStackObjects ) Info . setHasNonSpillStackObjects ( true ) ; if ( TM . getOptLevel ( ) == CodeGenOpt :: None ) HasStackObjects = true ; bool RequiresStackAccess = HasStackObjects || MFI . hasCalls ( ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; if ( ST . isAmdHsaOrMesa ( MF . getFunction ( ) ) ) { if ( RequiresStackAccess ) { unsigned PrivateSegmentBufferReg = Info . getPreloadedReg ( <STR_LIT> ) ; Info . setScratchRSrcReg ( PrivateSegmentBufferReg ) ; if ( MFI . hasCalls ( ) ) { unsigned ReservedOffsetReg = TRI . reservedPrivateSegmentWaveByteOffsetReg ( MF ) ; Info . setScratchWaveOffsetReg ( ReservedOffsetReg ) ; } else { unsigned PrivateSegmentWaveByteOffsetReg = Info . getPreloadedReg ( <STR_LIT> ) ; Info . setScratchWaveOffsetReg ( PrivateSegmentWaveByteOffsetReg ) ; } } else { unsigned ReservedBufferReg = TRI . reservedPrivateSegmentBufferReg ( MF ) ; unsigned ReservedOffsetReg = TRI . reservedPrivateSegmentWaveByteOffsetReg ( MF ) ; Info . setScratchRSrcReg ( ReservedBufferReg ) ; Info . setScratchWaveOffsetReg ( ReservedOffsetReg ) ; } } else { unsigned ReservedBufferReg = TRI . reservedPrivateSegmentBufferReg ( MF ) ; Info . setScratchRSrcReg ( ReservedBufferReg ) ; if ( HasStackObjects && ! MFI . hasCalls ( ) ) { unsigned ScratchWaveOffsetReg = Info . getPreloadedReg ( <STR_LIT> ) ; Info . setScratchWaveOffsetReg ( ScratchWaveOffsetReg ) ; } else { unsigned ReservedOffsetReg = TRI . reservedPrivateSegmentWaveByteOffsetReg ( MF ) ; Info . setScratchWaveOffsetReg ( ReservedOffsetReg ) ; }


<s> Offsets [ <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Offsets [ <NUM_LIT> ] = DAG . getConstant ( SOffset , DL , <STR_LIT> ) ; Offsets [ <NUM_LIT> ] = DAG . getConstant ( ImmOffset , DL , <STR_LIT> ) ; return ; } } if ( DAG . isBaseWithConstantOffset ( CombinedOffset ) ) { SDValue N0 = CombinedOffset . getOperand ( <NUM_LIT> ) ; SDValue N1 = CombinedOffset . getOperand ( <NUM_LIT> ) ; uint32_t SOffset , ImmOffset ; int Offset = cast < ConstantSDNode > ( N1 ) -> getSExtValue ( ) ; if ( Offset >= <NUM_LIT> && <STR_LIT> ( Offset , SOffset , ImmOffset , Subtarget , Align ) ) { Offsets [ <NUM_LIT> ] = N0 ; Offsets [ <NUM_LIT> ] = DAG . getConstant ( SOffset , DL , <STR_LIT> ) ; Offsets [ <NUM_LIT> ] = DAG . getConstant ( ImmOffset , DL , <STR_LIT> ) ; return ; } } Offsets [ <NUM_LIT> ] = CombinedOffset ; Offsets [ <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Offsets [ <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ;


<s> MachineInstr * SetOn = BuildMI ( * MBB , I , DL , TII -> get ( <STR_LIT> ) ) . add ( * Idx ) . addImm ( IdxMode ) ; SetOn -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; } else { unsigned Tmp = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , I , DL , TII -> get ( <STR_LIT> ) , Tmp ) . add ( * Idx ) . addImm ( Offset ) ; MachineInstr * SetOn = BuildMI ( * MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Tmp , RegState :: Kill ) . addImm ( IdxMode ) ; SetOn -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; } return true ; } if ( Offset == <NUM_LIT> ) {

BuildMI ( * MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . add ( * Idx ) ;


<s> bool <ISA_LIT>TargetLowering :: shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const {


<s> bool <ISA_LIT>TargetLowering :: shouldEmitFixup ( const GlobalValue * GV ) const { const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ; return ( GV -> getType ( ) -> getAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS || GV -> getType ( ) -> getAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) && <STR_LIT> ( TT ) ;


<s> return ( GV -> getType ( ) -> getAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS || GV -> getType ( ) -> getAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) && <STR_LIT> ( TT ) ;


<s> return ( GV -> getType ( ) -> getAddressSpace ( ) == <ISA_LIT>AS :: GLOBAL_ADDRESS || GV -> getType ( ) -> getAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS || GV -> getType ( ) -> getAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) && ! shouldEmitFixup ( GV ) && ! getTargetMachine ( ) . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ;


<s> return ! shouldEmitFixup ( GV ) && ! shouldEmitGOTReloc ( GV ) ;


<s> if ( ( bitOpWithConstantIsReducible ( Opc , ValLo ) || bitOpWithConstantIsReducible ( Opc , ValHi ) ) || ( CRHS -> hasOneUse ( ) && ! TII -> isInlineConstant ( CRHS -> getAPIntValue ( ) ) ) ) { return splitBinaryBitConstantOpImpl ( DCI , SL , Opc , LHS , ValLo , ValHi ) ;


<s> SDValue <ISA_LIT>TargetLowering :: splitBinaryBitConstantOp ( DAGCombinerInfo & DCI , const SDLoc & SL , unsigned Opc , SDValue LHS , const ConstantSDNode * CRHS ) const { uint64_t Val = CRHS -> getZExtValue ( ) ; uint32_t ValLo = Lo_32 ( Val ) ; uint32_t ValHi = Hi_32 ( Val ) ;

const <ISA_LIT>InstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ;


<s> std :: tie ( Lo1 , Hi1 ) = DAG . SplitVectorOperand ( Op . getNode ( ) , <NUM_LIT> ) ; SDLoc SL ( Op ) ; SDValue OpLo = DAG . getNode ( Opc , SL , Lo0 . getValueType ( ) , Lo0 , Lo1 , Op -> getFlags ( ) ) ;

SDValue OpHi = DAG . getNode ( Opc , SL , Hi0 . getValueType ( ) , Hi0 , Hi1 , Op -> getFlags ( ) ) ;


<s> MachineFunction * MF = BB -> getParent ( ) ; MachineBasicBlock * SplitBB = MF -> CreateMachineBasicBlock ( BB -> getBasicBlock ( ) ) ; MF -> insert ( ++ MachineFunction :: iterator ( BB ) , SplitBB ) ; SplitBB -> splice ( SplitBB -> begin ( ) , BB , SplitPoint , BB -> end ( ) ) ; SplitBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( SplitBB ) ; MI . setDesc ( TII -> getKillTerminatorFromPseudo ( MI . getOpcode ( ) ) ) ;


<s> MachineBasicBlock * SplitBB = MF -> CreateMachineBasicBlock ( BB -> getBasicBlock ( ) ) ; MF -> insert ( ++ MachineFunction :: iterator ( BB ) , SplitBB ) ; SplitBB -> splice ( SplitBB -> begin ( ) , BB , SplitPoint , BB -> end ( ) ) ;

SplitBB -> transferSuccessorsAndUpdatePHIs ( BB ) ;


<s> bool <ISA_LIT>TargetLowering :: supportSplitCSR ( MachineFunction * MF ) const { const <ISA_LIT>MachineFunctionInfo * Info = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;


<s> EVT TruncVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , MemVT . getSizeInBits ( ) ) ; if ( MemVT . isFloatingPoint ( ) ) { assert ( Ld -> getExtensionType ( ) == <STR_LIT> && <STR_LIT> ) ; TruncVT = MemVT . changeTypeToInteger ( ) ; } SDValue Cvt = NewLoad ; if ( Ld -> getExtensionType ( ) == <STR_LIT> ) { Cvt = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NewLoad , DAG . getValueType ( TruncVT ) ) ; } else if ( Ld -> getExtensionType ( ) == <STR_LIT> || Ld -> getExtensionType ( ) == <STR_LIT> ) { Cvt = DAG . getZeroExtendInReg ( NewLoad , SL , TruncVT ) ; } else { assert ( Ld -> getExtensionType ( ) == <STR_LIT> ) ; } EVT VT = Ld -> getValueType ( <NUM_LIT> ) ; EVT IntVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , VT . getSizeInBits ( ) ) ; DCI . AddToWorklist ( Cvt . getNode ( ) ) ; Cvt = getLoadExtOrTrunc ( DAG , Ld -> getExtensionType ( ) , Cvt , SL , IntVT ) ; DCI . AddToWorklist ( Cvt . getNode ( ) ) ; Cvt = DAG . getNode ( <STR_LIT> , SL , VT , Cvt ) ; return DAG . getMergeValues ( { Cvt , NewLoad . getValue ( <NUM_LIT> ) } , SL ) ;


<s> const SDValue Ops0 [ ] = { DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , buildSMovImm32 ( DAG , DL , <NUM_LIT> ) , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , buildSMovImm32 ( DAG , DL , TII -> getDefaultRsrcDataFormat ( ) >> <NUM_LIT> ) , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) } ; SDValue SubRegHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops0 ) , <NUM_LIT> ) ;


<s> SDValue SubRegHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops0 ) , <NUM_LIT> ) ; const SDValue Ops1 [ ] = {

DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , Ptr , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , SubRegHi , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) } ;


<s> TII -> legalizeOperandsVOP3 ( MRI , MI ) ; return ; } if ( TII -> isMIMG ( * MI ) ) { unsigned VReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Writemask = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned BitsSet = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) BitsSet += Writemask & ( <NUM_LIT> << i ) ? <NUM_LIT> : <NUM_LIT> ; const TargetRegisterClass * RC ; switch ( BitsSet ) { default : return ; case <NUM_LIT> : RC = & <STR_LIT> ; break ; case <NUM_LIT> : RC = & <STR_LIT> ; break ; case <NUM_LIT> : RC = & <STR_LIT> ; break ; } unsigned NewOpcode = TII -> getMaskedMIMGOp ( MI -> getOpcode ( ) , BitsSet ) ; MI -> setDesc ( TII -> get ( NewOpcode ) ) ; MRI . setRegClass ( VReg , RC ) ; return ; } int NoRetAtomicOp = <STR_LIT> ( MI -> getOpcode ( ) ) ; if ( NoRetAtomicOp != - <NUM_LIT> ) {

if ( ! Node -> hasAnyUseOfValue ( <NUM_LIT> ) ) {


<s> Lane = SubIdx2Lane ( I -> getConstantOperandVal ( <NUM_LIT> ) ) ; unsigned Comp ; for ( unsigned i = <NUM_LIT> , Dmask = OldDmask ; i <= Lane ; i ++ ) { assert ( Dmask ) ; Comp = countTrailingZeros ( Dmask ) ; Dmask &= ~ ( <NUM_LIT> << Comp ) ; } if ( Users [ Lane ] ) return ; Users [ Lane ] = * I ; NewDmask |= <NUM_LIT> << Comp ; } if ( NewDmask == OldDmask ) return ; std :: vector < SDValue > Ops ; Ops . push_back ( DAG . getTargetConstant ( NewDmask , SDLoc ( Node ) , <STR_LIT> ) ) ; Ops . insert ( Ops . end ( ) , Node -> op_begin ( ) + <NUM_LIT> , Node -> op_end ( ) ) ; Node = ( MachineSDNode * ) DAG . UpdateNodeOperands ( Node , Ops ) ; if ( NewDmask && ( NewDmask & ( NewDmask - <NUM_LIT> ) ) == <NUM_LIT> ) { SDValue RC = DAG . getTargetConstant ( <STR_LIT> , SDLoc ( ) , <STR_LIT> ) ; SDNode * Copy = DAG . getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , SDLoc ( ) , Users [ Lane ] -> getValueType ( <NUM_LIT> ) , SDValue ( Node , <NUM_LIT> ) , RC ) ; DAG . ReplaceAllUsesWith ( Users [ Lane ] , Copy ) ; return ; } for ( unsigned i = <NUM_LIT> , Idx = <STR_LIT> ; i < <NUM_LIT> ; ++ i ) { SDNode * User = Users [ i ] ; if ( ! User ) continue ; SDValue Op = DAG . getTargetConstant ( Idx , SDLoc ( User ) , <STR_LIT> ) ; DAG . UpdateNodeOperands ( User , User -> getOperand ( <NUM_LIT> ) , Op ) ; switch ( Idx ) { default : break ; case <STR_LIT> : Idx = <STR_LIT> ; break ; case <STR_LIT> : Idx = <STR_LIT> ; break ; case <STR_LIT> : Idx = <STR_LIT> ; break ; }


<s> return AlignedBy4 ; } if ( VT . bitsLT ( <STR_LIT> ) ) return false ; if ( IsFast ) * IsFast = true ;

return VT . bitsGT ( <STR_LIT> ) && Align % <NUM_LIT> == <NUM_LIT> ;


<s> int32_t <ISA_LIT>TargetLowering :: analyzeImmediate ( const SDNode * N ) const { const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; if ( const ConstantSDNode * Node = dyn_cast < ConstantSDNode > ( N ) ) { if ( TII -> isInlineConstant ( Node -> getAPIntValue ( ) ) ) return <NUM_LIT> ;

uint64_t Val = Node -> getZExtValue ( ) ;


<s> MachineSDNode * <ISA_LIT>TargetLowering :: buildRSRC ( SelectionDAG & DAG , SDLoc DL , SDValue Ptr , uint32_t RsrcDword1 , uint64_t RsrcDword2And3 ) const { SDValue PtrLo = DAG . getTargetExtractSubreg ( <STR_LIT> , DL , <STR_LIT> , Ptr ) ; SDValue PtrHi = DAG . getTargetExtractSubreg ( <STR_LIT> , DL , <STR_LIT> , Ptr ) ; if ( RsrcDword1 ) {

PtrHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , PtrHi , DAG . getConstant ( RsrcDword1 , DL , <STR_LIT> ) ) , <NUM_LIT> ) ;


<s> DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , PtrLo , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , PtrHi , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , DataLo , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , DataHi , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) } ;

return DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops ) ;


<s> SDValue K = DAG . getTargetConstant ( Val , DL , <STR_LIT> ) ; return SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , K ) , <NUM_LIT> ) ;


<s> static SDValue buildSMovImm32 ( SelectionDAG & DAG , SDLoc DL , uint64_t Val ) {

SDValue K = DAG . getTargetConstant ( Val , DL , <STR_LIT> ) ;


<s> } case <ISA_LIT>AS :: CONSTANT_ADDRESS : { if ( STI . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) return isUInt < <NUM_LIT> > ( OffsetSize ) ; else return ( OffsetSize % <NUM_LIT> == <NUM_LIT> ) && isUInt < <NUM_LIT> > ( OffsetSize / <NUM_LIT> ) ; } case <ISA_LIT>AS :: LOCAL_ADDRESS : case <ISA_LIT>AS :: REGION_ADDRESS : { return isUInt < <NUM_LIT> > ( OffsetSize ) ; } case <ISA_LIT>AS :: PRIVATE_ADDRESS : default : return <NUM_LIT> ;


<s> SDNode * M0 = DAG . getMachineNode ( <STR_LIT> , DL , V . getValueType ( ) , V ) ;

return DAG . getCopyToReg ( Chain , DL , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , SDValue ( M0 , <NUM_LIT> ) , SDValue ( ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: copyToM0 ( SelectionDAG & DAG , SDValue Chain , SDLoc DL , SDValue V ) const {

SDNode * M0 = DAG . getMachineNode ( <STR_LIT> , DL , V . getValueType ( ) , V ) ;


<s> SDValue <ISA_LIT>TargetLowering :: CreateLiveInRegister ( SelectionDAG & DAG , const TargetRegisterClass * RC , unsigned Reg , EVT VT ) const {

SDValue VReg = <ISA_LIT>TargetLowering :: CreateLiveInRegister ( DAG , RC , Reg , VT ) ;


<s> SDValue VReg = <ISA_LIT>TargetLowering :: CreateLiveInRegister ( DAG , RC , Reg , VT ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , SDLoc ( DAG . getEntryNode ( ) ) , cast < RegisterSDNode > ( VReg ) -> getReg ( ) , VT ) ;


<s> bool <ISA_LIT>TargetLowering :: enableAggressiveFMAFusion ( EVT VT ) const { return true ;


<s> static SDNode * findUser ( SDValue Value , unsigned Opcode ) { SDNode * Parent = Value . getNode ( ) ; for ( SDNode :: use_iterator I = Parent -> use_begin ( ) , E = Parent -> use_end ( ) ; I != E ; ++ I ) { if ( I . getUse ( ) . get ( ) != Value ) continue ; if ( I -> getOpcode ( ) == Opcode ) return * I ; } return nullptr ;


<s> for ( SDNode :: use_iterator I = Parent -> use_begin ( ) , E = Parent -> use_end ( ) ; I != E ; ++ I ) {

if ( I . getUse ( ) . get ( ) != Value ) continue ;


<s> <ISA_LIT>TargetLowering :: ConstraintType <ISA_LIT>TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == <NUM_LIT> ) {


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { if ( Size >= <NUM_LIT> && DstAlign >= <NUM_LIT> ) return <STR_LIT> ;


<s> TargetLoweringBase :: LegalizeTypeAction <ISA_LIT>TargetLowering :: getPreferredVectorAction ( EVT VT ) const { if ( VT . getVectorNumElements ( ) != <NUM_LIT> && VT . getScalarType ( ) . bitsLE ( <STR_LIT> ) ) return TypeSplitVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ;


<s> return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } case 'v' : switch ( VT . getSizeInBits ( ) ) { default : return std :: make_pair ( <NUM_LIT> , nullptr ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } } if ( Constraint . size ( ) > <NUM_LIT> ) { const TargetRegisterClass * RC = nullptr ; if ( Constraint [ <NUM_LIT> ] == 'v' ) { RC = & <STR_LIT> ; } else if ( Constraint [ <NUM_LIT> ] == 's' ) { RC = & <STR_LIT> ; } if ( RC ) { uint32_t Idx ; bool Failed = Constraint . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , Idx ) ;

if ( ! Failed && Idx < RC -> getNumRegs ( ) ) return std :: make_pair ( RC -> getRegister ( Idx ) , RC ) ;


<s> MVT <ISA_LIT>TargetLowering :: getScalarShiftAmountTy ( const DataLayout & , EVT ) const { return <STR_LIT> ;


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & Ctx , EVT VT ) const {


<s> if ( ! VT . isVector ( ) ) { return <STR_LIT> ; } return EVT :: getVectorVT ( Ctx , <STR_LIT> , VT . getVectorNumElements ( ) ) ;


<s> static bool isFlatGlobalAddrSpace ( unsigned AS ) {

return AS == <ISA_LIT>AS :: GLOBAL_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS || AS == <ISA_LIT>AS :: CONSTANT_ADDRESS ;


<s> VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : return Subtarget -> hasFP32Denormals ( ) && Subtarget -> hasFastFMAF32 ( ) ; case <STR_LIT> : return true ;


<s> if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : return Subtarget -> hasFP32Denormals ( ) && Subtarget -> hasFastFMAF32 ( ) ; case <STR_LIT> :


<s> static bool isFrameIndexOp ( SDValue Op ) { if ( Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ;

return isa < FrameIndexSDNode > ( Op ) ;


<s> return isLegalFlatAddressingMode ( AM ) ; } return isLegalMUBUFAddressingMode ( AM ) ; } case <ISA_LIT>AS :: CONSTANT_ADDRESS : { if ( AM . BaseOffs % <NUM_LIT> != <NUM_LIT> ) return isLegalMUBUFAddressingMode ( AM ) ; if ( DL . getTypeStoreSize ( Ty ) < <NUM_LIT> ) return isLegalMUBUFAddressingMode ( AM ) ; if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs / <NUM_LIT> ) ) return false ; } else if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs / <NUM_LIT> ) ) return false ; } else if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) {

if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ;


<s> } else if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs / <NUM_LIT> ) ) return false ; } else if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ; } else llvm_unreachable ( <STR_LIT> ) ; if ( AM . Scale == <NUM_LIT> ) return true ; if ( AM . Scale == <NUM_LIT> && AM . HasBaseReg ) return true ; return false ; } case <ISA_LIT>AS :: PRIVATE_ADDRESS : case <ISA_LIT>AS :: UNKNOWN_ADDRESS_SPACE : return isLegalMUBUFAddressingMode ( AM ) ; case <ISA_LIT>AS :: LOCAL_ADDRESS : case <ISA_LIT>AS :: REGION_ADDRESS : { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ; if ( AM . Scale == <NUM_LIT> ) return true ;


<s> bool <ISA_LIT>TargetLowering :: isLegalFlatAddressingMode ( const AddrMode & AM ) const {

return AM . BaseOffs == <NUM_LIT> && ( AM . Scale == <NUM_LIT> || AM . Scale == <NUM_LIT> ) ;


<s> return AM . BaseOffs == <NUM_LIT> && ( AM . Scale == <NUM_LIT> || AM . Scale == <NUM_LIT> ) ;


<s> switch ( AM . Scale ) { case <NUM_LIT> : return true ; case <NUM_LIT> : return true ; case <NUM_LIT> : if ( AM . HasBaseReg ) {


<s> switch ( AM . Scale ) { case <NUM_LIT> : return true ; case <NUM_LIT> : return true ; case <NUM_LIT> : if ( AM . HasBaseReg ) { return false ;


<s> if ( isa < UndefValue > ( Ptr ) || isa < Argument > ( Ptr ) || isa < Constant > ( Ptr ) || isa < GlobalValue > ( Ptr ) ) return true ; const Instruction * I = dyn_cast_or_null < Instruction > ( Ptr ) ;

return I && I -> getMetadata ( <STR_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & , EVT ) const {


<s> for ( unsigned i = <NUM_LIT> ; i < Node -> getNumOperands ( ) ; ++ i ) { if ( ! isFrameIndexOp ( Node -> getOperand ( i ) ) ) { Ops . push_back ( Node -> getOperand ( i ) ) ; continue ;


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < Node -> getNumOperands ( ) ; ++ i ) { if ( ! isFrameIndexOp ( Node -> getOperand ( i ) ) ) { Ops . push_back ( Node -> getOperand ( i ) ) ; continue ; }


<s> Ops . push_back ( Target ) ; SDNode * Result = DAG . getNode ( Res . size ( ) > <NUM_LIT> ? <STR_LIT> : <STR_LIT> , DL , DAG . getVTList ( Res ) , Ops ) . getNode ( ) ; if ( BR ) { SDValue Ops [ ] = { BR -> getOperand ( <NUM_LIT> ) , BRCOND . getOperand ( <NUM_LIT> ) } ; SDValue NewBR = DAG . getNode ( <STR_LIT> , DL , BR -> getVTList ( ) , Ops ) ; DAG . ReplaceAllUsesWith ( BR , NewBR . getNode ( ) ) ; BR = NewBR . getNode ( ) ; } SDValue Chain = SDValue ( Result , Result -> getNumValues ( ) - <NUM_LIT> ) ;

for ( unsigned i = <NUM_LIT> , e = Intr -> getNumValues ( ) - <NUM_LIT> ; i != e ; ++ i ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerFastFDIV ( SDValue Op , SelectionDAG & DAG ) const { SDLoc SL ( Op ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; bool Unsafe = DAG . getTarget ( ) . Options . UnsafeFPMath ; if ( const ConstantFPSDNode * CLHS = dyn_cast < ConstantFPSDNode > ( LHS ) ) { if ( ( Unsafe || ( VT == <STR_LIT> && ! Subtarget -> hasFP32Denormals ( ) ) ) && CLHS -> isExactlyValue ( <NUM_LIT> ) ) { if ( RHS . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SL , VT , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; } } if ( Unsafe ) { SDNodeFlags Flags ; Flags . setUnsafeAlgebra ( true ) ; SDValue Recip = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; return DAG . getNode ( <STR_LIT> , SL , VT , LHS , Recip , & Flags ) ;


<s> bool Unsafe = DAG . getTarget ( ) . Options . UnsafeFPMath ; if ( const ConstantFPSDNode * CLHS = dyn_cast < ConstantFPSDNode > ( LHS ) ) { if ( ( Unsafe || ( VT == <STR_LIT> && ! Subtarget -> hasFP32Denormals ( ) ) ) && CLHS -> isExactlyValue ( <NUM_LIT> ) ) { if ( RHS . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SL , VT , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; } } if ( Unsafe ) { SDNodeFlags Flags ; Flags . setUnsafeAlgebra ( true ) ; SDValue Recip = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; return DAG . getNode ( <STR_LIT> , SL , VT , LHS , Recip , & Flags ) ; } return SDValue ( ) ;


<s> if ( VT == <STR_LIT> ) return LowerFDIV32 ( Op , DAG ) ; if ( VT == <STR_LIT> ) return LowerFDIV64 ( Op , DAG ) ; llvm_unreachable ( <STR_LIT> ) ;


<s> SDValue r2 = DAG . getSetCC ( SL , SetCCVT , r1 , K0 , <STR_LIT> ) ; SDValue r3 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , r2 , K1 , One ) ; r1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , RHS , r3 ) ; SDValue r0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , r1 ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LHS , r0 ) ;

return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , r3 , Mul ) ;


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue r1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , RHS ) ; const APFloat K0Val ( BitsToFloat ( <NUM_LIT> ) ) ; const SDValue K0 = DAG . getConstantFP ( K0Val , SL , <STR_LIT> ) ; const APFloat K1Val ( BitsToFloat ( <NUM_LIT> ) ) ; const SDValue K1 = DAG . getConstantFP ( K1Val , SL , <STR_LIT> ) ; const SDValue One = DAG . getConstantFP ( <NUM_LIT> , SL , <STR_LIT> ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) ; SDValue r2 = DAG . getSetCC ( SL , SetCCVT , r1 , K0 , <STR_LIT> ) ; SDValue r3 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , r2 , K1 , One ) ; r1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , RHS , r3 ) ; SDValue r0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , r1 ) ;

SDValue Mul = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LHS , r0 ) ;


<s> const SDValue One = DAG . getConstantFP ( <NUM_LIT> , SL , <STR_LIT> ) ; SDVTList ScaleVT = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue DivScale0 = DAG . getNode ( <STR_LIT> , SL , ScaleVT , Y , Y , X ) ; SDValue NegDivScale0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ; SDValue Rcp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ; SDValue Fma0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Rcp , One ) ; SDValue Fma1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Rcp , Fma0 , Rcp ) ; SDValue Fma2 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Fma1 , One ) ; SDValue DivScale1 = DAG . getNode ( <STR_LIT> , SL , ScaleVT , X , Y , X ) ; SDValue Fma3 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Fma1 , Fma2 , Fma1 ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale1 , Fma3 ) ; SDValue Fma4 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Mul , DivScale1 ) ; SDValue Scale ; if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) { const SDValue Hi = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue NumBC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , X ) ; SDValue DenBC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Y ) ;

SDValue Scale0BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ;


<s> SDValue DivScale0 = DAG . getNode ( <STR_LIT> , SL , ScaleVT , Y , Y , X ) ; SDValue NegDivScale0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ; SDValue Rcp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ; SDValue Fma0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Rcp , One ) ; SDValue Fma1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Rcp , Fma0 , Rcp ) ; SDValue Fma2 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Fma1 , One ) ; SDValue DivScale1 = DAG . getNode ( <STR_LIT> , SL , ScaleVT , X , Y , X ) ; SDValue Fma3 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Fma1 , Fma2 , Fma1 ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale1 , Fma3 ) ; SDValue Fma4 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Mul , DivScale1 ) ; SDValue Scale ; if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) { const SDValue Hi = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue NumBC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , X ) ; SDValue DenBC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Y ) ; SDValue Scale0BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ; SDValue Scale1BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale1 ) ; SDValue NumHi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NumBC , Hi ) ; SDValue DenHi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DenBC , Hi ) ; SDValue Scale0Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Scale0BC , Hi ) ; SDValue Scale1Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Scale1BC , Hi ) ;

SDValue CmpDen = DAG . getSetCC ( SL , <STR_LIT> , DenHi , Scale0Hi , <STR_LIT> ) ;


<s> if ( GSD -> getAddressSpace ( ) != <ISA_LIT>AS :: CONSTANT_ADDRESS ) return <ISA_LIT>TargetLowering :: LowerGlobalAddress ( MFI , Op , DAG ) ; SDLoc DL ( GSD ) ;

const GlobalValue * GV = GSD -> getGlobal ( ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( <ISA_LIT>MachineFunction * MFI , SDValue Op , SelectionDAG & DAG ) const { GlobalAddressSDNode * GSD = cast < GlobalAddressSDNode > ( Op ) ; if ( GSD -> getAddressSpace ( ) != <ISA_LIT>AS :: CONSTANT_ADDRESS ) return <ISA_LIT>TargetLowering :: LowerGlobalAddress ( MFI , Op , DAG ) ; SDLoc DL ( GSD ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerImplicitZextParam ( SelectionDAG & DAG , SDValue Op , MVT VT , unsigned Offset ) const { SDLoc SL ( Op ) ; SDValue Param = LowerParameter ( DAG , <STR_LIT> , <STR_LIT> , SL , DAG . getEntryNode ( ) , Offset , false ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Param , DAG . getValueType ( VT ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerImplicitZextParam ( SelectionDAG & DAG , SDValue Op , MVT VT , unsigned Offset ) const { SDLoc SL ( Op ) ; SDValue Param = LowerParameter ( DAG , <STR_LIT> , <STR_LIT> , SL , DAG . getEntryNode ( ) , Offset , false ) ;

return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Param , DAG . getValueType ( VT ) ) ;


<s> SDLoc DL ( Op ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; unsigned IntrinsicID = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntrinsicID ) { case <STR_LIT> : { Chain = copyToM0 ( DAG , Chain , DL , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Glue = Chain . getValue ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , Op . getOperand ( <NUM_LIT> ) , Glue ) ; }


<s> case <STR_LIT> : { Chain = copyToM0 ( DAG , Chain , DL , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Glue = Chain . getValue ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , Op . getOperand ( <NUM_LIT> ) , Glue ) ; } case <STR_LIT> : { SDValue Ops [ ] = { Chain , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ; EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ;

MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore , VT . getStoreSize ( ) , <NUM_LIT> ) ;


<s> assert ( Op . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned NumElements = Op . getValueType ( ) . getVectorNumElements ( ) ; assert ( NumElements != <NUM_LIT> && <STR_LIT> ) ; switch ( Load -> getAddressSpace ( ) ) { default : break ;


<s> default : return <ISA_LIT>TargetLowering :: LowerOperation ( Op , DAG ) ; case <STR_LIT> : return LowerFrameIndex ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : { SDValue Result = LowerLOAD ( Op , DAG ) ; assert ( ( ! Result . getNode ( ) || Result . getNode ( ) -> getNumValues ( ) == <NUM_LIT> ) && <STR_LIT> ) ; return Result ; } case <STR_LIT> :


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( Subtarget -> getRegisterInfo ( ) ) ; unsigned InputPtrReg = TRI -> getPreloadedValue ( MF , <ISA_LIT>RegisterInfo :: KERNARG_SEGMENT_PTR ) ; Type * Ty = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; MVT PtrVT = getPointerTy ( DL , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; PointerType * PtrTy = PointerType :: get ( Ty , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; SDValue BasePtr = DAG . getCopyFromReg ( Chain , SL , MRI . getLiveInVirtReg ( InputPtrReg ) , PtrVT ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( Offset , SL , PtrVT ) ) ;

SDValue PtrOffset = DAG . getUNDEF ( PtrVT ) ;


<s> Type * Ty = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; MVT PtrVT = getPointerTy ( DL , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; PointerType * PtrTy = PointerType :: get ( Ty , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; SDValue BasePtr = DAG . getCopyFromReg ( Chain , SL , MRI . getLiveInVirtReg ( InputPtrReg ) , PtrVT ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( Offset , SL , PtrVT ) ) ; SDValue PtrOffset = DAG . getUNDEF ( PtrVT ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ) ;

unsigned Align = DL . getABITypeAlignment ( Ty ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerSampleIntrinsic ( unsigned Opcode , const SDValue & Op , SelectionDAG & DAG ) const {

return DAG . getNode ( Opcode , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerSELECT ( SDValue Op , SelectionDAG & DAG ) const { if ( Op . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( Op ) ; SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue LHS = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Lo0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , Zero ) ; SDValue Lo1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RHS , Zero ) ; SDValue Lo = DAG . getSelect ( DL , <STR_LIT> , Cond , Lo0 , Lo1 ) ; SDValue Hi0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , One ) ; SDValue Hi1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RHS , One ) ;

SDValue Hi = DAG . getSelect ( DL , <STR_LIT> , Cond , Hi0 , Hi1 ) ;


<s> if ( Ret . getNode ( ) ) return Ret ; if ( VT . isVector ( ) && VT . getVectorNumElements ( ) >= <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; if ( VT == <STR_LIT> ) return DAG . getTruncStore ( Store -> getChain ( ) , DL , DAG . getSExtOrTrunc ( Store -> getValue ( ) , DL , <STR_LIT> ) , Store -> getBasePtr ( ) , <STR_LIT> , Store -> getMemOperand ( ) ) ;


<s> switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , FractPart ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , FractPart ) ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> SDValue FractPart = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Arg , DAG . getConstantFP ( <NUM_LIT> / M_PI , DL , VT ) ) ) ; switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , FractPart ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , FractPart ) ; default :


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default :


<s> SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> && RHS . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> LCC = cast < CondCodeSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) -> get ( ) ; <STR_LIT> RCC = cast < CondCodeSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue X = LHS . getOperand ( <NUM_LIT> ) ; SDValue Y = RHS . getOperand ( <NUM_LIT> ) ; if ( Y . getOpcode ( ) != <STR_LIT> || Y . getOperand ( <NUM_LIT> ) != X ) return SDValue ( ) ; if ( LCC == <STR_LIT> ) { if ( X != LHS . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; if ( RCC == <STR_LIT> ) { const ConstantFPSDNode * C1 = dyn_cast < ConstantFPSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) ; if ( ! C1 || ! C1 -> isInfinity ( ) || C1 -> isNegative ( ) ) return SDValue ( ) ; const uint32_t Mask = <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> ;

static_assert ( ( ( ~ ( <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> ) ) & <NUM_LIT> ) == Mask , <STR_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: performClassCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; SDValue Mask = N -> getOperand ( <NUM_LIT> ) ; if ( const ConstantSDNode * CMask = dyn_cast < ConstantSDNode > ( Mask ) ) { if ( CMask -> isNullValue ( ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; } return SDValue ( ) ;


<s> if ( CMask -> isNullValue ( ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; } return SDValue ( ) ;


<s> return DAG . getNode ( minMaxOpcToMin3Max3Opc ( Opc ) , DL , N -> getValueType ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) , Op1 ) ; } if ( Op1 . getOpcode ( ) == Opc && Op1 . hasOneUse ( ) ) { SDLoc DL ( N ) ;

return DAG . getNode ( minMaxOpcToMin3Max3Opc ( Opc ) , DL , N -> getValueType ( <NUM_LIT> ) , Op0 , Op1 . getOperand ( <NUM_LIT> ) , Op1 . getOperand ( <NUM_LIT> ) ) ;


<s> SelectionDAG & DAG = DCI . DAG ; unsigned Opc = N -> getOpcode ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == Opc && Op0 . hasOneUse ( ) ) { SDLoc DL ( N ) ; return DAG . getNode ( minMaxOpcToMin3Max3Opc ( Opc ) , DL , N -> getValueType ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) , Op1 ) ; } if ( Op1 . getOpcode ( ) == Opc && Op1 . hasOneUse ( ) ) { SDLoc DL ( N ) ; return DAG . getNode ( minMaxOpcToMin3Max3Opc ( Opc ) , DL , N -> getValueType ( <NUM_LIT> ) , Op0 , Op1 . getOperand ( <NUM_LIT> ) , Op1 . getOperand ( <NUM_LIT> ) ) ; } return SDValue ( ) ;


<s> SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> && RHS . getOpcode ( ) == <STR_LIT> ) { SDValue Src = LHS . getOperand ( <NUM_LIT> ) ; if ( Src != RHS . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; const ConstantSDNode * CLHS = dyn_cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) ; const ConstantSDNode * CRHS = dyn_cast < ConstantSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) ; if ( ! CLHS || ! CRHS ) return SDValue ( ) ;

static const uint32_t MaxMask = <NUM_LIT> ;


<s> SDValue Src = LHS . getOperand ( <NUM_LIT> ) ; if ( Src != RHS . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; const ConstantSDNode * CLHS = dyn_cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) ; const ConstantSDNode * CRHS = dyn_cast < ConstantSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) ; if ( ! CLHS || ! CRHS ) return SDValue ( ) ; static const uint32_t MaxMask = <NUM_LIT> ; uint32_t NewMask = ( CLHS -> getZExtValue ( ) | CRHS -> getZExtValue ( ) ) & MaxMask ; SDLoc DL ( N ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src , DAG . getConstant ( NewMask , DL , <STR_LIT> ) ) ; } return SDValue ( ) ;


<s> if ( ! CRHS ) return SDValue ( ) ; const APFloat & APF = CRHS -> getValueAPF ( ) ; if ( APF . isInfinity ( ) && ! APF . isNegative ( ) ) { unsigned Mask = <STR_LIT> | <STR_LIT> ;

return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LHS . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Mask , SL , <STR_LIT> ) ) ;


<s> if ( ! canFoldOffset ( Offset . getZExtValue ( ) , AddrSpace , * Subtarget ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc SL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue ShlX = DAG . getNode ( <STR_LIT> , SL , VT , N0 . getOperand ( <NUM_LIT> ) , N1 ) ;

SDValue COffset = DAG . getConstant ( Offset , SL , <STR_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: performSHLPtrCombine ( SDNode * N , unsigned AddrSpace , DAGCombinerInfo & DCI ) const { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; const ConstantSDNode * CN1 = dyn_cast < ConstantSDNode > ( N1 ) ; if ( ! CN1 ) return SDValue ( ) ; const ConstantSDNode * CAdd = dyn_cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; if ( ! CAdd ) return SDValue ( ) ; APInt Offset = CAdd -> getAPIntValue ( ) << CN1 -> getAPIntValue ( ) ;

if ( ! canFoldOffset ( Offset . getZExtValue ( ) , AddrSpace , * Subtarget ) ) return SDValue ( ) ;


<s> LoadSDNode * Load = cast < LoadSDNode > ( Src ) ; unsigned AS = Load -> getAddressSpace ( ) ; unsigned Align = Load -> getAlignment ( ) ; Type * Ty = LoadVT . getTypeForEVT ( * DAG . getContext ( ) ) ; unsigned ABIAlignment = DAG . getDataLayout ( ) . getABITypeAlignment ( Ty ) ; if ( Align < ABIAlignment && ! allowsMisalignedMemoryAccesses ( LoadVT , AS , Align , nullptr ) ) { return SDValue ( ) ; } SDValue NewLoad = DAG . getExtLoad ( <STR_LIT> , DL , RegVT , Load -> getChain ( ) , Load -> getBasePtr ( ) , LoadVT , Load -> getMemOperand ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Load , <NUM_LIT> ) , NewLoad . getValue ( <NUM_LIT> ) ) ; SmallVector < SDValue , <NUM_LIT> > Elts ; if ( RegVT . isVector ( ) ) DAG . ExtractVectorElements ( NewLoad , Elts ) ; else Elts . push_back ( NewLoad ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned EltIdx = <NUM_LIT> ; for ( SDValue Elt : Elts ) { unsigned ComponentsInElt = std :: min ( <NUM_LIT> , NElts - <NUM_LIT> * EltIdx ) ; for ( unsigned I = <NUM_LIT> ; I < ComponentsInElt ; ++ I ) { unsigned Opc = <STR_LIT> + I ; SDValue Cvt = DAG . getNode ( Opc , DL , <STR_LIT> , Elt ) ; DCI . AddToWorklist ( Cvt . getNode ( ) ) ; Ops . push_back ( Cvt ) ; } ++ EltIdx ; }