<s> UseMI . setDesc ( get ( IsF32 ? <STR_LIT> : <STR_LIT> ) ) ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; if ( DeleteDef ) DefMI . eraseFromParent ( ) ; return true ; } if ( Src2 -> isReg ( ) && Src2 -> getReg ( ) == Reg ) { bool Src0Inlined = false ; if ( Src0 -> isReg ( ) ) { MachineInstr * Def = MRI -> getUniqueVRegDef ( Src0 -> getReg ( ) ) ; if ( Def && Def -> isMoveImmediate ( ) && isInlineConstant ( Def -> getOperand ( <NUM_LIT> ) ) && MRI -> hasOneUse ( Src0 -> getReg ( ) ) ) { Src0 -> ChangeToImmediate ( Def -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; Src0Inlined = true ; } else if ( ( RI . isPhysicalRegister ( Src0 -> getReg ( ) ) && RI . isSGPRClass ( RI . getPhysRegClass ( Src0 -> getReg ( ) ) ) ) || ( RI . isVirtualRegister ( Src0 -> getReg ( ) ) && RI . isSGPRClass ( MRI -> getRegClass ( Src0 -> getReg ( ) ) ) ) ) return false ; } if ( Src1 -> isReg ( ) && ! Src0Inlined ) { MachineInstr * Def = MRI -> getUniqueVRegDef ( Src1 -> getReg ( ) ) ; if ( Def && Def -> isMoveImmediate ( ) && isInlineConstant ( Def -> getOperand ( <NUM_LIT> ) ) && MRI -> hasOneUse ( Src1 -> getReg ( ) ) && commuteInstruction ( UseMI ) ) { Src0 -> ChangeToImmediate ( Def -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; } else if ( ( RI . isPhysicalRegister ( Src1 -> getReg ( ) ) && RI . isSGPRClass ( RI . getPhysRegClass ( Src1 -> getReg ( ) ) ) ) || ( RI . isVirtualRegister ( Src1 -> getReg ( ) ) && RI . isSGPRClass ( MRI -> getRegClass ( Src1 -> getReg ( ) ) ) ) ) return false ; } const int64_t Imm = ImmOp -> getImm ( ) ; UseMI . RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: omod ) ) ; UseMI . RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: clamp ) ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) UseMI . untieRegOperand ( <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ) ; Src2 -> ChangeToImmediate ( Imm ) ; removeModOperands ( UseMI ) ; UseMI . setDesc ( get ( IsF32 ? <STR_LIT> : <STR_LIT> ) ) ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; if ( DeleteDef ) DefMI . eraseFromParent ( ) ; return true ; }


<s> } else if ( ( RI . isPhysicalRegister ( Src0 -> getReg ( ) ) && RI . isSGPRClass ( RI . getPhysRegClass ( Src0 -> getReg ( ) ) ) ) || ( RI . isVirtualRegister ( Src0 -> getReg ( ) ) && RI . isSGPRClass ( MRI -> getRegClass ( Src0 -> getReg ( ) ) ) ) ) return false ; } if ( Src1 -> isReg ( ) && ! Src0Inlined ) { MachineInstr * Def = MRI -> getUniqueVRegDef ( Src1 -> getReg ( ) ) ; if ( Def && Def -> isMoveImmediate ( ) && isInlineConstant ( Def -> getOperand ( <NUM_LIT> ) ) && MRI -> hasOneUse ( Src1 -> getReg ( ) ) && commuteInstruction ( UseMI ) ) { Src0 -> ChangeToImmediate ( Def -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; } else if ( ( RI . isPhysicalRegister ( Src1 -> getReg ( ) ) && RI . isSGPRClass ( RI . getPhysRegClass ( Src1 -> getReg ( ) ) ) ) || ( RI . isVirtualRegister ( Src1 -> getReg ( ) ) && RI . isSGPRClass ( MRI -> getRegClass ( Src1 -> getReg ( ) ) ) ) ) return false ; } const int64_t Imm = ImmOp -> getImm ( ) ; UseMI . RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: omod ) ) ; UseMI . RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: clamp ) ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) UseMI . untieRegOperand ( <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ) ; Src2 -> ChangeToImmediate ( Imm ) ; removeModOperands ( UseMI ) ; UseMI . setDesc ( get ( IsF32 ? <STR_LIT> : <STR_LIT> ) ) ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; if ( DeleteDef ) DefMI . eraseFromParent ( ) ; return true ; } } return false ;


<s> case PseudoSourceValue :: GOT : case PseudoSourceValue :: JumpTable : case PseudoSourceValue :: GlobalValueCallEntry : case PseudoSourceValue :: ExternalSymbolCallEntry :

case PseudoSourceValue :: TargetCustom :


<s> case PseudoSourceValue :: ConstantPool : case PseudoSourceValue :: GOT : case PseudoSourceValue :: JumpTable : case PseudoSourceValue :: GlobalValueCallEntry : case PseudoSourceValue :: ExternalSymbolCallEntry : case PseudoSourceValue :: TargetCustom :


<s> if ( ST . getGeneration ( ) == <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) RsrcDataFormat |= ( <NUM_LIT> << <NUM_LIT> ) ; } return RsrcDataFormat ;


<s> if ( ST . getGeneration ( ) <= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) RsrcDataFormat |= ( <NUM_LIT> << <NUM_LIT> ) ; if ( ST . getGeneration ( ) == <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) RsrcDataFormat |= ( <NUM_LIT> << <NUM_LIT> ) ;


<s> if ( isLiteralConstantLike ( MI . getOperand ( Src1Idx ) , Desc . OpInfo [ Src1Idx ] ) ) return DescSize + <NUM_LIT> ; int Src2Idx = <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ; if ( Src2Idx == - <NUM_LIT> ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src2Idx ) , Desc . OpInfo [ Src2Idx ] ) ) return DescSize + <NUM_LIT> ; return DescSize ; } switch ( Opc ) { case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : case TargetOpcode :: EH_LABEL : return <NUM_LIT> ; case TargetOpcode :: BUNDLE : return getInstBundleSize ( MI ) ; case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ;

const char * AsmStr = MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ;


<s> return DescSize ; } switch ( Opc ) { case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : case TargetOpcode :: EH_LABEL : return <NUM_LIT> ; case TargetOpcode :: BUNDLE : return getInstBundleSize ( MI ) ; case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } default : return DescSize ;


<s> unsigned Opc = LdSt . getOpcode ( ) ; if ( isDS ( LdSt ) ) { const MachineOperand * OffsetImm = getNamedOperand ( LdSt , <STR_LIT> :: offset ) ; if ( OffsetImm ) { BaseOp = getNamedOperand ( LdSt , <STR_LIT> :: addr ) ; Offset = OffsetImm -> getImm ( ) ; assert ( BaseOp -> isReg ( ) && <STR_LIT> <STR_LIT> ) ; return true ; } const MachineOperand * Offset0Imm = getNamedOperand ( LdSt , <STR_LIT> :: offset0 ) ; const MachineOperand * Offset1Imm = getNamedOperand ( LdSt , <STR_LIT> :: offset1 ) ; uint8_t Offset0 = Offset0Imm -> getImm ( ) ; uint8_t Offset1 = Offset1Imm -> getImm ( ) ; if ( Offset1 > Offset0 && Offset1 - Offset0 == <NUM_LIT> ) { unsigned EltSize ; if ( LdSt . mayLoad ( ) ) EltSize = TRI -> getRegSizeInBits ( * getOpRegClass ( LdSt , <NUM_LIT> ) ) / <NUM_LIT> ; else { assert ( LdSt . mayStore ( ) ) ; int Data0Idx = <STR_LIT> ( Opc , <STR_LIT> :: data0 ) ; EltSize = TRI -> getRegSizeInBits ( * getOpRegClass ( LdSt , Data0Idx ) ) / <NUM_LIT> ; } if ( isStride64 ( Opc ) ) EltSize *= <NUM_LIT> ; BaseOp = getNamedOperand ( LdSt , <STR_LIT> :: addr ) ; Offset = EltSize * Offset0 ; assert ( BaseOp -> isReg ( ) && <STR_LIT> <STR_LIT> ) ; return true ; } return false ; } if ( isMUBUF ( LdSt ) || isMTBUF ( LdSt ) ) { const MachineOperand * SOffset = getNamedOperand ( LdSt , <STR_LIT> :: soffset ) ; if ( SOffset && SOffset -> isReg ( ) ) return false ; MachineOperand * AddrReg = getNamedOperand ( LdSt , <STR_LIT> :: vaddr ) ; if ( ! AddrReg ) return false ;


<s> default : return <NUM_LIT> ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) + <NUM_LIT> ;


<s> case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) + <NUM_LIT> ;


<s> static TargetInstrInfo :: RegSubRegPair getRegOrUndef ( const MachineOperand & RegOpnd ) { assert ( RegOpnd . isReg ( ) ) ;

return RegOpnd . isUndef ( ) ? TargetInstrInfo :: RegSubRegPair ( ) :


<s> return RegOpnd . isUndef ( ) ? TargetInstrInfo :: RegSubRegPair ( ) : getRegSubRegPair ( RegOpnd ) ;


<s> for ( unsigned I = <NUM_LIT> , E = ( MI . getNumOperands ( ) - <NUM_LIT> ) / <NUM_LIT> ; I < E ; ++ I ) if ( MI . getOperand ( <NUM_LIT> + <NUM_LIT> * I + <NUM_LIT> ) . getImm ( ) == SubReg ) { auto & RegOp = MI . getOperand ( <NUM_LIT> + <NUM_LIT> * I ) ; return getRegOrUndef ( RegOp ) ; }

return TargetInstrInfo :: RegSubRegPair ( ) ;


<s> } Rsrc23 |= UINT64_C ( <NUM_LIT> ) << <STR_LIT> ; if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) Rsrc23 &= ~ <STR_LIT> ; return Rsrc23 ;


<s> if ( Op1 . isUndef ( ) ) return nullptr ; RSR = getRegSubRegPair ( Op1 ) ; DefInst = MRI . getVRegDef ( RSR . Reg ) ; } break ; } default : if ( followSubRegDef ( * MI , RSR ) ) { if ( ! RSR . Reg ) return nullptr ; DefInst = MRI . getVRegDef ( RSR . Reg ) ; } }


<s> bool <ISA_LIT>InstrInfo :: hasUnwantedEffectsWhenEXECEmpty ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ;

if ( MI . mayStore ( ) && isSMRD ( MI ) ) return true ;


<s> if ( MI . mayStore ( ) && isSMRD ( MI ) ) return true ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; if ( MI . isInlineAsm ( ) ) return true ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ;


<s> bool <ISA_LIT>InstrInfo :: isAlwaysGDS ( uint16_t Opcode ) const {

return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> int Idx = <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> :: sbase ) ; if ( Idx == - <NUM_LIT> ) return false ;

const auto RCID = MI . getDesc ( ) . OpInfo [ Idx ] . RegClass ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { int32_t Trunc = static_cast < int32_t > ( Imm ) ; return <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( MO . getImm ( ) , ST . hasInv2PiInlineImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( isInt < <NUM_LIT> > ( Imm ) || isUInt < <NUM_LIT> > ( Imm ) ) { int16_t Trunc = static_cast < int16_t > ( Imm ) ; return ST . has16BitInsts ( ) && <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ; } return false ; } case <STR_LIT> : case <STR_LIT> : { if ( isUInt < <NUM_LIT> > ( Imm ) ) { int16_t Trunc = static_cast < int16_t > ( Imm ) ; return ST . has16BitInsts ( ) && <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ; } if ( ! ( Imm & <NUM_LIT> ) ) { return ST . has16BitInsts ( ) && <STR_LIT> ( Imm >> <NUM_LIT> , ST . hasInv2PiInlineImm ( ) ) ; } uint32_t Trunc = static_cast < uint32_t > ( Imm ) ; return <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ; } default : llvm_unreachable ( <STR_LIT> ) ;


<s> case <STR_LIT> : { int32_t Trunc = static_cast < int32_t > ( Imm ) ; return <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( MO . getImm ( ) , ST . hasInv2PiInlineImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( isInt < <NUM_LIT> > ( Imm ) || isUInt < <NUM_LIT> > ( Imm ) ) { int16_t Trunc = static_cast < int16_t > ( Imm ) ; return ST . has16BitInsts ( ) && <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ; } return false ; } case <STR_LIT> : case <STR_LIT> : { if ( isUInt < <NUM_LIT> > ( Imm ) ) { int16_t Trunc = static_cast < int16_t > ( Imm ) ; return ST . has16BitInsts ( ) && <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ; }


<s> if ( ! Addr || ! Addr -> isFI ( ) ) return <STR_LIT> ; assert ( ! MI . memoperands_empty ( ) && ( * MI . memoperands_begin ( ) ) -> getAddrSpace ( ) == <ISA_LIT>AS :: PRIVATE_ADDRESS ) ; FrameIndex = Addr -> getIndex ( ) ;

return getNamedOperand ( MI , <STR_LIT> :: vdata ) -> getReg ( ) ;


<s> void <ISA_LIT>InstrInfo :: legalizeOperandsSMRD ( MachineRegisterInfo & MRI , MachineInstr & MI ) const { MachineOperand * SBase = getNamedOperand ( MI , <STR_LIT> :: sbase ) ; if ( SBase && ! RI . isSGPRClass ( MRI . getRegClass ( SBase -> getReg ( ) ) ) ) {

unsigned SGPR = readlaneVGPRToSGPR ( SBase -> getReg ( ) , MI , MRI ) ;


<s> unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( * MI . getParent ( ) , MI , DL , get ( <STR_LIT> ) , Reg ) . add ( Src1 ) ; Src1 . ChangeToRegister ( Reg , false ) ; return ; } if ( HasImplicitSGPR || ! MI . isCommutable ( ) ) { legalizeOpWithMove ( MI , Src1Idx ) ; return ; } int Src0Idx = <STR_LIT> ( Opc , <STR_LIT> :: src0 ) ; MachineOperand & Src0 = MI . getOperand ( Src0Idx ) ; if ( ( ! Src1 . isImm ( ) && ! Src1 . isReg ( ) ) || ! isLegalRegOperand ( MRI , InstrDesc . OpInfo [ Src1Idx ] , Src0 ) ) { legalizeOpWithMove ( MI , Src1Idx ) ; return ; } int CommutedOpc = commuteOpcode ( MI ) ; if ( CommutedOpc == - <NUM_LIT> ) { legalizeOpWithMove ( MI , Src1Idx ) ; return ; } MI . setDesc ( get ( CommutedOpc ) ) ; unsigned Src0Reg = Src0 . getReg ( ) ; unsigned Src0SubReg = Src0 . getSubReg ( ) ; bool Src0Kill = Src0 . isKill ( ) ; if ( Src1 . isImm ( ) ) Src0 . ChangeToImmediate ( Src1 . getImm ( ) ) ; else if ( Src1 . isReg ( ) ) { Src0 . ChangeToRegister ( Src1 . getReg ( ) , false , false , Src1 . isKill ( ) ) ; Src0 . setSubReg ( Src1 . getSubReg ( ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; Src1 . ChangeToRegister ( Src0Reg , false , false , Src0Kill ) ; Src1 . setSubReg ( Src0SubReg ) ;


<s> MachineFrameInfo & FrameInfo = MF -> getFrameInfo ( ) ; const DebugLoc & DL = MBB . findDebugLoc ( MI ) ; unsigned Align = FrameInfo . getObjectAlignment ( FrameIndex ) ; unsigned Size = FrameInfo . getObjectSize ( FrameIndex ) ; unsigned SpillSize = TRI -> getSpillSize ( * RC ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad , Size , Align ) ; if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; const MCInstrDesc & OpDesc = get ( getSGPRSpillRestoreOpcode ( SpillSize ) ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( DestReg , & <STR_LIT> ) ; } FrameInfo . setStackID ( FrameIndex , <STR_LIT> ) ; MachineInstrBuilder Spill = BuildMI ( MBB , MI , DL , OpDesc , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getFrameOffsetReg ( ) , RegState :: Implicit ) ; if ( ST . hasScalarStores ( ) ) { Spill . addReg ( <STR_LIT> , RegState :: ImplicitDefine | RegState :: Dead ) ; } return ; } assert ( RI . hasVGPRs ( RC ) && <STR_LIT> ) ; unsigned Opcode = getVGPRSpillRestoreOpcode ( SpillSize ) ;

BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) . addFrameIndex ( FrameIndex ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI -> getFrameOffsetReg ( ) ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MachineBasicBlock :: iterator I ( & MI ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned SaveExec = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , SaveExec ) . addReg ( <STR_LIT> ) ; for ( auto & MO : MI . uses ( ) ) { if ( MO . isReg ( ) && MO . isUse ( ) ) { MRI . clearKillFlags ( MO . getReg ( ) ) ; } } MachineBasicBlock * LoopBB = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * RemainderBB = MF . CreateMachineBasicBlock ( ) ; MachineFunction :: iterator MBBI ( MBB ) ; ++ MBBI ; MF . insert ( MBBI , LoopBB ) ; MF . insert ( MBBI , RemainderBB ) ; LoopBB -> addSuccessor ( LoopBB ) ;

LoopBB -> addSuccessor ( RemainderBB ) ;


<s> MachineBasicBlock & MBB = * Inst . getParent ( ) ; MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; MachineBasicBlock :: iterator MII = Inst ; const DebugLoc & DL = Inst . getDebugLoc ( ) ; MachineOperand & Dest = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src0 = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = Inst . getOperand ( <NUM_LIT> ) ; if ( ST . hasDLInsts ( ) ) { unsigned NewDest = MRI . createVirtualRegister ( & <STR_LIT> ) ; legalizeGenericOperand ( MBB , MII , & <STR_LIT> , Src0 , MRI , DL ) ; legalizeGenericOperand ( MBB , MII , & <STR_LIT> , Src1 , MRI , DL ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , NewDest ) . add ( Src0 ) . add ( Src1 ) ; MRI . replaceRegWith ( Dest . getReg ( ) , NewDest ) ; addUsersToMoveToVALUWorklist ( NewDest , MRI , Worklist ) ; } else { bool Src0IsSGPR = Src0 . isReg ( ) && RI . isSGPRClass ( MRI . getRegClass ( Src0 . getReg ( ) ) ) ; bool Src1IsSGPR = Src1 . isReg ( ) && RI . isSGPRClass ( MRI . getRegClass ( Src1 . getReg ( ) ) ) ; MachineInstr * Not = nullptr ; MachineInstr * Xor = nullptr ; unsigned Temp = MRI . createVirtualRegister ( & <STR_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: mayAccessFlatAddressSpace ( const MachineInstr & MI ) const { if ( ! isFLAT ( MI ) ) return false ; if ( MI . memoperands_empty ( ) ) return true ; for ( const MachineMemOperand * MMO : MI . memoperands ( ) ) {

if ( MMO -> getAddrSpace ( ) == <ISA_LIT>AS :: FLAT_ADDRESS ) return true ;


<s> if ( MI . memoperands_empty ( ) ) return true ; for ( const MachineMemOperand * MMO : MI . memoperands ( ) ) { if ( MMO -> getAddrSpace ( ) == <ISA_LIT>AS :: FLAT_ADDRESS ) return true ; }


<s> if ( ! MI1 . hasOneMemOperand ( ) || ! MI2 . hasOneMemOperand ( ) ) return false ; auto MO1 = * MI1 . memoperands_begin ( ) ; auto MO2 = * MI2 . memoperands_begin ( ) ; if ( MO1 -> getAddrSpace ( ) != MO2 -> getAddrSpace ( ) ) return false ; auto Base1 = MO1 -> getValue ( ) ; auto Base2 = MO2 -> getValue ( ) ; if ( ! Base1 || ! Base2 ) return false ;

const MachineFunction & MF = * MI1 . getParent ( ) -> getParent ( ) ;


<s> assert ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; unsigned NewOpc = Opc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; Inst . RemoveOperand ( <NUM_LIT> ) ; Inst . setDesc ( get ( NewOpc ) ) ; Inst . addImplicitDefUseOperands ( * MBB . getParent ( ) ) ; MRI . replaceRegWith ( OldDstReg , ResultReg ) ; legalizeOperands ( Inst , MDT ) ;

addUsersToMoveToVALUWorklist ( ResultReg , MRI , Worklist ) ;


<s> case <STR_LIT> : if ( ST . hasDLInsts ( ) ) splitScalar64BitBinaryOp ( Worklist , Inst , <STR_LIT> , MDT ) ; else splitScalar64BitXnor ( Worklist , Inst , MDT ) ; Inst . eraseFromParent ( ) ; continue ; case <STR_LIT> : splitScalar64BitBinaryOp ( Worklist , Inst , <STR_LIT> , MDT ) ; Inst . eraseFromParent ( ) ; continue ; case <STR_LIT> : splitScalar64BitBinaryOp ( Worklist , Inst , <STR_LIT> , MDT ) ; Inst . eraseFromParent ( ) ; continue ; case <STR_LIT> : splitScalar64BitUnaryOp ( Worklist , Inst , <STR_LIT> ) ; Inst . eraseFromParent ( ) ; continue ; case <STR_LIT> : splitScalar64BitBCNT ( Worklist , Inst ) ; Inst . eraseFromParent ( ) ; continue ; case <STR_LIT> : splitScalar64BitBFE ( Worklist , Inst ) ; Inst . eraseFromParent ( ) ; continue ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : lowerScalarAbs ( Worklist , Inst ) ; Inst . eraseFromParent ( ) ; continue ; case <STR_LIT> : case <STR_LIT> : BuildMI ( * MBB , Inst , Inst . getDebugLoc ( ) , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : movePackToVALU ( Worklist , MRI , Inst ) ; Inst . eraseFromParent ( ) ; continue ; case <STR_LIT> : lowerScalarXnor ( Worklist , Inst ) ; Inst . eraseFromParent ( ) ; continue ; case <STR_LIT> : splitScalarNotBinop ( Worklist , Inst , <STR_LIT> ) ; Inst . eraseFromParent ( ) ; continue ; case <STR_LIT> : splitScalarNotBinop ( Worklist , Inst , <STR_LIT> ) ; Inst . eraseFromParent ( ) ; continue ; case <STR_LIT> : splitScalarBinOpN2 ( Worklist , Inst , <STR_LIT> ) ; Inst . eraseFromParent ( ) ; continue ;


<s> <ISA_LIT>EncodingFamily Gen = subtargetEncodingFamily ( ST ) ; if ( ( get ( Opcode ) . TSFlags & <STR_LIT> ) != <NUM_LIT> && ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX9 ) Gen = <STR_LIT> ; if ( get ( Opcode ) . TSFlags & <STR_LIT> ) Gen = ST . getGeneration ( ) == <ISA_LIT>Subtarget :: GFX9 ? <STR_LIT> : <STR_LIT> ; if ( ST . hasUnpackedD16VMem ( ) && ( get ( Opcode ) . TSFlags & <STR_LIT> ) ) Gen = <STR_LIT> ; int MCOp = <STR_LIT> ( Opcode , Gen ) ; if ( MCOp == - <NUM_LIT> ) return Opcode ;

if ( MCOp == ( uint16_t ) - <NUM_LIT> ) return - <NUM_LIT> ;


<s> unsigned <ISA_LIT>InstrInfo :: readlaneVGPRToSGPR ( unsigned SrcReg , MachineInstr & UseMI , MachineRegisterInfo & MRI ) const { const TargetRegisterClass * VRC = MRI . getRegClass ( SrcReg ) ; const TargetRegisterClass * SRC = RI . getEquivalentSGPRClass ( VRC ) ; unsigned DstReg = MRI . createVirtualRegister ( SRC ) ; unsigned SubRegs = RI . getRegSizeInBits ( * VRC ) / <NUM_LIT> ; if ( SubRegs == <NUM_LIT> ) { BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) ; return DstReg ; } SmallVector < unsigned , <NUM_LIT> > SRegs ; for ( unsigned i = <NUM_LIT> ; i < SubRegs ; ++ i ) { unsigned SGPR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( <STR_LIT> ) , SGPR ) . addReg ( SrcReg , <NUM_LIT> , RI . getSubRegFromChannel ( i ) ) ; SRegs . push_back ( SGPR ) ; }

MachineInstrBuilder MIB = BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( <STR_LIT> ) , DstReg ) ;


<s> const MachineOperand * FirstDst = nullptr ; const MachineOperand * SecondDst = nullptr ; if ( ( isMUBUF ( FirstLdSt ) && isMUBUF ( SecondLdSt ) ) || ( isMTBUF ( FirstLdSt ) && isMTBUF ( SecondLdSt ) ) || ( isFLAT ( FirstLdSt ) && isFLAT ( SecondLdSt ) ) ) { const unsigned MaxGlobalLoadCluster = <NUM_LIT> ; if ( NumLoads > MaxGlobalLoadCluster ) return false ; FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdata ) ; if ( ! FirstDst ) FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdata ) ; if ( ! SecondDst ) SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdst ) ; } else if ( isSMRD ( FirstLdSt ) && isSMRD ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: sdst ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: sdst ) ;

} else if ( isDS ( FirstLdSt ) && isDS ( SecondLdSt ) ) {


<s> bool <ISA_LIT>InstrInfo :: shouldScheduleLoadsNear ( SDNode * Load0 , SDNode * Load1 , int64_t Offset0 , int64_t Offset1 , unsigned NumLoads ) const {

assert ( Offset1 > Offset0 && <STR_LIT> ) ;


<s> assert ( Offset1 > Offset0 && <STR_LIT> ) ; return ( NumLoads <= <NUM_LIT> && ( Offset1 - Offset0 ) < <NUM_LIT> ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const GCNSubtarget & ST ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ST ) , ST ( ST ) {


<s> const TargetRegisterClass * Src1RC = MRI . getRegClass ( Src1 . getReg ( ) ) ; const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; const TargetRegisterClass * Src1SubRC = RI . getSubRegClass ( Src1RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; unsigned LoOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; MachineInstr * LoHalf = BuildMI ( MBB , MII , DL , get ( LoOpc ) , DestSub0 ) . addReg ( CarryReg , RegState :: Define ) . add ( SrcReg0Sub0 ) . add ( SrcReg1Sub0 ) ; unsigned HiOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; MachineInstr * HiHalf = BuildMI ( MBB , MII , DL , get ( HiOpc ) , DestSub1 ) . addReg ( DeadCarryReg , RegState :: Define | RegState :: Dead ) . add ( SrcReg0Sub1 ) . add ( SrcReg1Sub1 ) . addReg ( CarryReg , RegState :: Kill ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ;

MRI . replaceRegWith ( Dest . getReg ( ) , FullDestReg ) ;


<s> const DebugLoc & DL = Inst . getDebugLoc ( ) ; MachineOperand & Dest = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = Inst . getOperand ( <NUM_LIT> ) ; const MCInstrDesc & InstDesc = get ( <STR_LIT> ) ; const TargetRegisterClass * SrcRC = Src . isReg ( ) ? MRI . getRegClass ( Src . getReg ( ) ) : & <STR_LIT> ; unsigned MidReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ;

const TargetRegisterClass * SrcSubRC = RI . getSubRegClass ( SrcRC , <STR_LIT> ) ;


<s> if ( BitWidth < <NUM_LIT> ) { unsigned MidRegLo = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned MidRegHi = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , MidRegLo ) . addReg ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( BitWidth ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , MidRegHi ) . addImm ( <NUM_LIT> ) . addReg ( MidRegLo ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , ResultReg ) . addReg ( MidRegLo ) . addImm ( <STR_LIT> ) . addReg ( MidRegHi ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , ResultReg ) ; addUsersToMoveToVALUWorklist ( ResultReg , MRI , Worklist ) ;


<s> MachineOperand & Dest = Inst . getOperand ( <NUM_LIT> ) ; uint32_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; uint32_t Offset = Imm & <NUM_LIT> ; uint32_t BitWidth = ( Imm & <NUM_LIT> ) >> <NUM_LIT> ; ( void ) Offset ; assert ( Inst . getOpcode ( ) == <STR_LIT> && BitWidth <= <NUM_LIT> && Offset == <NUM_LIT> && <STR_LIT> ) ; if ( BitWidth < <NUM_LIT> ) { unsigned MidRegLo = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned MidRegHi = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , MidRegLo ) . addReg ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( BitWidth ) ;

BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , MidRegHi ) . addImm ( <NUM_LIT> ) . addReg ( MidRegLo ) ;


<s> MachineInstr & LoHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . add ( SrcReg0Sub0 ) . add ( SrcReg1Sub0 ) ; unsigned DestSub1 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & HiHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . add ( SrcReg0Sub1 ) . add ( SrcReg1Sub1 ) ; unsigned FullDestReg = MRI . createVirtualRegister ( NewDestRC ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , FullDestReg ) ; Worklist . insert ( & LoHalf ) ; Worklist . insert ( & HiHalf ) ; addUsersToMoveToVALUWorklist ( FullDestReg , MRI , Worklist ) ;


<s> MachineBasicBlock & MBB = * Inst . getParent ( ) ; MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; MachineOperand & Dest = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src0 = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = Inst . getOperand ( <NUM_LIT> ) ; DebugLoc DL = Inst . getDebugLoc ( ) ; MachineBasicBlock :: iterator MII = Inst ; const MCInstrDesc & InstDesc = get ( Opcode ) ; const TargetRegisterClass * Src0RC = Src0 . isReg ( ) ? MRI . getRegClass ( Src0 . getReg ( ) ) : & <STR_LIT> ; const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; const TargetRegisterClass * Src1RC = Src1 . isReg ( ) ? MRI . getRegClass ( Src1 . getReg ( ) ) : & <STR_LIT> ; const TargetRegisterClass * Src1SubRC = RI . getSubRegClass ( Src1RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; const TargetRegisterClass * DestRC = MRI . getRegClass ( Dest . getReg ( ) ) ; const TargetRegisterClass * NewDestRC = RI . getEquivalentVGPRClass ( DestRC ) ; const TargetRegisterClass * NewDestSubRC = RI . getSubRegClass ( NewDestRC , <STR_LIT> ) ; unsigned DestSub0 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & LoHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . add ( SrcReg0Sub0 ) . add ( SrcReg1Sub0 ) ; unsigned DestSub1 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & HiHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . add ( SrcReg0Sub1 ) . add ( SrcReg1Sub1 ) ; unsigned FullDestReg = MRI . createVirtualRegister ( NewDestRC ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , FullDestReg ) ; Worklist . insert ( & LoHalf ) ; Worklist . insert ( & HiHalf ) ; addUsersToMoveToVALUWorklist ( FullDestReg , MRI , Worklist ) ;


<s> MachineBasicBlock :: iterator MII = Inst ; const MCInstrDesc & InstDesc = get ( Opcode ) ; const TargetRegisterClass * Src0RC = Src0 . isReg ( ) ? MRI . getRegClass ( Src0 . getReg ( ) ) : & <STR_LIT> ; const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; const TargetRegisterClass * DestRC = MRI . getRegClass ( Dest . getReg ( ) ) ; const TargetRegisterClass * NewDestRC = RI . getEquivalentVGPRClass ( DestRC ) ; const TargetRegisterClass * NewDestSubRC = RI . getSubRegClass ( NewDestRC , <STR_LIT> ) ; unsigned DestSub0 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & LoHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . add ( SrcReg0Sub0 ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; unsigned DestSub1 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & HiHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . add ( SrcReg0Sub1 ) ; unsigned FullDestReg = MRI . createVirtualRegister ( NewDestRC ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , FullDestReg ) ; Worklist . insert ( & LoHalf ) ; Worklist . insert ( & HiHalf ) ; addUsersToMoveToVALUWorklist ( FullDestReg , MRI , Worklist ) ;


<s> Op1 = & Src0 ; } BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , Interm ) . add ( * Op0 ) ; unsigned NewDest = MRI . createVirtualRegister ( DestRC ) ; MachineInstr & Xor = * BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , NewDest ) . addReg ( Interm ) . add ( * Op1 ) ; MRI . replaceRegWith ( Dest . getReg ( ) , NewDest ) ;


<s> BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , Interm ) . add ( * Op0 ) ; unsigned NewDest = MRI . createVirtualRegister ( DestRC ) ; MachineInstr & Xor = * BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , NewDest ) . addReg ( Interm ) . add ( * Op1 ) ; MRI . replaceRegWith ( Dest . getReg ( ) , NewDest ) ; Worklist . insert ( & Xor ) ;


<s> MachineOperand & Src1 = Inst . getOperand ( <NUM_LIT> ) ; unsigned NewDest = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned Interm = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr & Not = * BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , Interm ) . add ( Src1 ) ; MachineInstr & Op = * BuildMI ( MBB , MII , DL , get ( Opcode ) , NewDest ) . add ( Src0 ) . addReg ( Interm ) ;


<s> MachineOperand & Dest = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src0 = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = Inst . getOperand ( <NUM_LIT> ) ; unsigned NewDest = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned Interm = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr & Op = * BuildMI ( MBB , MII , DL , get ( Opcode ) , Interm ) . add ( Src0 ) . add ( Src1 ) ; MachineInstr & Not = * BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , NewDest ) . addReg ( Interm ) ; Worklist . insert ( & Op ) ;


<s> MachineOperand & Src0 = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = Inst . getOperand ( <NUM_LIT> ) ; unsigned NewDest = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned Interm = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr & Op = * BuildMI ( MBB , MII , DL , get ( Opcode ) , Interm ) . add ( Src0 ) . add ( Src1 ) ; MachineInstr & Not = * BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , NewDest ) . addReg ( Interm ) ; Worklist . insert ( & Op ) ;


<s> MachineFunction * MF = MBB . getParent ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineFrameInfo & FrameInfo = MF -> getFrameInfo ( ) ; const DebugLoc & DL = MBB . findDebugLoc ( MI ) ; unsigned Size = FrameInfo . getObjectSize ( FrameIndex ) ; unsigned Align = FrameInfo . getObjectAlignment ( FrameIndex ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , Size , Align ) ; unsigned SpillSize = TRI -> getSpillSize ( * RC ) ; if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; const MCInstrDesc & OpDesc = get ( getSGPRSpillSaveOpcode ( SpillSize ) ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; } MachineInstrBuilder Spill = BuildMI ( MBB , MI , DL , OpDesc ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getFrameOffsetReg ( ) , RegState :: Implicit ) ;

FrameInfo . setStackID ( FrameIndex , <STR_LIT> ) ;


<s> MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , Size , Align ) ; unsigned SpillSize = TRI -> getSpillSize ( * RC ) ; if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; const MCInstrDesc & OpDesc = get ( getSGPRSpillSaveOpcode ( SpillSize ) ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; }

MachineInstrBuilder Spill = BuildMI ( MBB , MI , DL , OpDesc ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getFrameOffsetReg ( ) , RegState :: Implicit ) ;


<s> static <ISA_LIT>EncodingFamily subtargetEncodingFamily ( const GCNSubtarget & ST ) {


<s> } if ( Src2 -> isReg ( ) && Src2 -> getReg ( ) == Reg ) { bool Src0Inlined = false ; if ( Src0 -> isReg ( ) ) { MachineInstr * Def = MRI -> getUniqueVRegDef ( Src0 -> getReg ( ) ) ; if ( Def && Def -> isMoveImmediate ( ) && isInlineConstant ( Def -> getOperand ( <NUM_LIT> ) ) && MRI -> hasOneUse ( Src0 -> getReg ( ) ) ) { Src0 -> ChangeToImmediate ( Def -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; Src0Inlined = true ; } else if ( ( Register :: isPhysicalRegister ( Src0 -> getReg ( ) ) && ( ST . getConstantBusLimit ( Opc ) <= <NUM_LIT> && RI . isSGPRClass ( RI . getPhysRegClass ( Src0 -> getReg ( ) ) ) ) ) || ( Register :: isVirtualRegister ( Src0 -> getReg ( ) ) && ( ST . getConstantBusLimit ( Opc ) <= <NUM_LIT> && RI . isSGPRClass ( MRI -> getRegClass ( Src0 -> getReg ( ) ) ) ) ) ) return false ; } if ( Src1 -> isReg ( ) && ! Src0Inlined ) { MachineInstr * Def = MRI -> getUniqueVRegDef ( Src1 -> getReg ( ) ) ; if ( Def && Def -> isMoveImmediate ( ) && isInlineConstant ( Def -> getOperand ( <NUM_LIT> ) ) && MRI -> hasOneUse ( Src1 -> getReg ( ) ) && commuteInstruction ( UseMI ) ) { Src0 -> ChangeToImmediate ( Def -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; } else if ( ( Register :: isPhysicalRegister ( Src1 -> getReg ( ) ) && RI . isSGPRClass ( RI . getPhysRegClass ( Src1 -> getReg ( ) ) ) ) || ( Register :: isVirtualRegister ( Src1 -> getReg ( ) ) && RI . isSGPRClass ( MRI -> getRegClass ( Src1 -> getReg ( ) ) ) ) ) return false ; } unsigned NewOpc = IsFMA ? ( IsF32 ? <STR_LIT> : <STR_LIT> ) : ( IsF32 ? <STR_LIT> : <STR_LIT> ) ; if ( pseudoToMCOpcode ( NewOpc ) == - <NUM_LIT> ) return false ; const int64_t Imm = ImmOp -> getImm ( ) ; UseMI . RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: omod ) ) ; UseMI . RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: clamp ) ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) UseMI . untieRegOperand ( <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ) ; Src2 -> ChangeToImmediate ( Imm ) ;


<s> Register VecReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsUndef = MI . getOperand ( <NUM_LIT> ) . isUndef ( ) ; unsigned SubReg = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( VecReg == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , OpDesc ) . addReg ( RI . getSubReg ( VecReg , SubReg ) , RegState :: Undef ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( VecReg , RegState :: ImplicitDefine ) . addReg ( VecReg , RegState :: Implicit | ( IsUndef ? RegState :: Undef : <NUM_LIT> ) ) ; const int ImpDefIdx = OpDesc . getNumOperands ( ) + OpDesc . getNumImplicitUses ( ) ; const int ImpUseIdx = ImpDefIdx + <NUM_LIT> ; MIB -> tieOperands ( ImpDefIdx , ImpUseIdx ) ; MI . eraseFromParent ( ) ; break ; } case <STR_LIT> : { MachineFunction & MF = * MBB . getParent ( ) ; Register Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RegLo = RI . getSubReg ( Reg , <STR_LIT> ) ; Register RegHi = RI . getSubReg ( Reg , <STR_LIT> ) ; MIBundleBuilder Bundler ( MBB , MI ) ; Bundler . append ( BuildMI ( MF , DL , get ( <STR_LIT> ) , Reg ) ) ; Bundler . append ( BuildMI ( MF , DL , get ( <STR_LIT> ) , RegLo ) . addReg ( RegLo ) . add ( MI . getOperand ( <NUM_LIT> ) ) ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) , RegHi ) . addReg ( RegHi ) ; MIB . add ( MI . getOperand ( <NUM_LIT> ) ) ; Bundler . append ( MIB ) ; finalizeBundle ( MBB , Bundler . begin ( ) ) ; MI . eraseFromParent ( ) ; break ; } case <STR_LIT> : { MI . setDesc ( get ( ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ) ) ; break ; } case <STR_LIT> : { MI . setDesc ( get ( ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ) ) ; break ; } case TargetOpcode :: BUNDLE : { if ( ! MI . mayLoad ( ) || MI . hasUnmodeledSideEffects ( ) ) return false ; for ( MachineBasicBlock :: instr_iterator I = MI . getIterator ( ) ; I -> isBundledWithSucc ( ) ; ++ I ) { I -> unbundleFromSucc ( ) ; for ( MachineOperand & MO : I -> operands ( ) ) if ( MO . isReg ( ) ) MO . setIsInternalRead ( false ) ; } MI . eraseFromParent ( ) ;


<s> auto E = UseMI ? UseMI -> getIterator ( ) : DefBB -> end ( ) ; for ( auto I = std :: next ( DefMI . getIterator ( ) ) ; I != E ; ++ I ) { if ( I -> isDebugInstr ( ) ) continue ; if ( NumScan ++ > MaxInstScan ) return true ;

if ( I -> modifiesRegister ( <STR_LIT> , TRI ) ) return true ;


<s> return NeedsCFI ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return NeedsCFI ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return NeedsCFI ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return NeedsCFI ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return NeedsCFI ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return NeedsCFI ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> :


<s> case <NUM_LIT> : return NeedsCFI ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return NeedsCFI ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return NeedsCFI ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return NeedsCFI ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return NeedsCFI ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return NeedsCFI ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return NeedsCFI ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return NeedsCFI ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return NeedsCFI ? <STR_LIT> : <STR_LIT> ;


<s> return NeedsCFI ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return NeedsCFI ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return NeedsCFI ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return NeedsCFI ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return NeedsCFI ? <STR_LIT> : <STR_LIT> ;


<s> MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , FrameInfo . getObjectSize ( FrameIndex ) , FrameInfo . getObjectAlign ( FrameIndex ) ) ; unsigned SpillSize = TRI -> getSpillSize ( * RC ) ; if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; assert ( SrcReg != <STR_LIT> && <STR_LIT> ) ; assert ( SrcReg != <STR_LIT> && SrcReg != <STR_LIT> && SrcReg != <STR_LIT> && <STR_LIT> ) ; const MCInstrDesc & OpDesc = get ( getSGPRSpillSaveOpcode ( SpillSize , NeedsCFI ) ) ; if ( SrcReg . isVirtual ( ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; }

BuildMI ( MBB , MI , DL , OpDesc ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getStackPtrOffsetReg ( ) , RegState :: Implicit ) ;


<s> int CommutedOpcode = commuteOpcode ( * MI ) ; if ( CommutedOpcode == - <NUM_LIT> ) return nullptr ; int Src0Idx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: src0 ) ; MachineOperand & Src0 = MI -> getOperand ( Src0Idx ) ; if ( ! Src0 . isReg ( ) ) return nullptr ; int Src1Idx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: src1 ) ; if ( ( OpIdx0 != static_cast < unsigned > ( Src0Idx ) || OpIdx1 != static_cast < unsigned > ( Src1Idx ) ) && ( OpIdx0 != static_cast < unsigned > ( Src1Idx ) || OpIdx1 != static_cast < unsigned > ( Src0Idx ) ) ) return nullptr ;

MachineOperand & Src1 = MI -> getOperand ( Src1Idx ) ;


<s> const MachineOperand & MO = MI -> getOperand ( Idx ) ; if ( RI . isSGPRClassID ( Desc . OpInfo [ Idx ] . RegClass ) ) SGPRReg = MO . getReg ( ) ; if ( MO . isReg ( ) && RI . isSGPRClass ( MRI . getRegClass ( MO . getReg ( ) ) ) ) UsedSGPRs [ i ] = MO . getReg ( ) ; } if ( SGPRReg != <STR_LIT> ) return SGPRReg ; if ( UsedSGPRs [ <NUM_LIT> ] != <STR_LIT> ) { if ( UsedSGPRs [ <NUM_LIT> ] == UsedSGPRs [ <NUM_LIT> ] || UsedSGPRs [ <NUM_LIT> ] == UsedSGPRs [ <NUM_LIT> ] ) SGPRReg = UsedSGPRs [ <NUM_LIT> ] ; } if ( SGPRReg == <STR_LIT> && UsedSGPRs [ <NUM_LIT> ] != <STR_LIT> ) { if ( UsedSGPRs [ <NUM_LIT> ] == UsedSGPRs [ <NUM_LIT> ] ) SGPRReg = UsedSGPRs [ <NUM_LIT> ] ; } return SGPRReg ;


<s> const MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const MCInstrDesc & InstDesc = get ( MI -> getOpcode ( ) ) ; const MCOperandInfo & OpInfo = InstDesc . OpInfo [ OpIdx ] ; const TargetRegisterClass * DefinedRC = OpInfo . RegClass != - <NUM_LIT> ? RI . getRegClass ( OpInfo . RegClass ) : nullptr ; if ( ! MO ) MO = & MI -> getOperand ( OpIdx ) ; if ( isVALU ( * MI ) && usesConstantBus ( MRI , * MO , DefinedRC -> getSize ( ) ) ) { unsigned SGPRUsed = MO -> isReg ( ) ? MO -> getReg ( ) : ( unsigned ) <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i == OpIdx ) continue ; const MachineOperand & Op = MI -> getOperand ( i ) ; if ( Op . isReg ( ) && Op . getReg ( ) != SGPRUsed && usesConstantBus ( MRI , Op , getOpSize ( * MI , i ) ) ) { return false ; } } } if ( MO -> isReg ( ) ) { assert ( DefinedRC ) ; const TargetRegisterClass * RC = TargetRegisterInfo :: isVirtualRegister ( MO -> getReg ( ) ) ? MRI . getRegClass ( MO -> getReg ( ) ) : RI . getPhysRegClass ( MO -> getReg ( ) ) ; return RI . getCommonSubClass ( RC , RI . getRegClass ( OpInfo . RegClass ) ) == RC ; } assert ( MO -> isImm ( ) || MO -> isTargetIndex ( ) || MO -> isFI ( ) ) ; if ( ! DefinedRC ) { return true ; } return isImmOperandLegal ( MI , OpIdx , * MO ) ;


<s> const MCInstrDesc & InstDesc = get ( MI -> getOpcode ( ) ) ; const MCOperandInfo & OpInfo = InstDesc . OpInfo [ OpIdx ] ; const TargetRegisterClass * DefinedRC = OpInfo . RegClass != - <NUM_LIT> ? RI . getRegClass ( OpInfo . RegClass ) : nullptr ; if ( ! MO ) MO = & MI -> getOperand ( OpIdx ) ; if ( isVALU ( * MI ) && usesConstantBus ( MRI , * MO , DefinedRC -> getSize ( ) ) ) { unsigned SGPRUsed = MO -> isReg ( ) ? MO -> getReg ( ) : ( unsigned ) <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i == OpIdx ) continue ; const MachineOperand & Op = MI -> getOperand ( i ) ; if ( Op . isReg ( ) && Op . getReg ( ) != SGPRUsed && usesConstantBus ( MRI , Op , getOpSize ( * MI , i ) ) ) { return false ; } } }


<s> return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { const TargetRegisterClass * RC = nullptr , * SRC = nullptr , * VRC = nullptr ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; i += <NUM_LIT> ) { if ( ! MI -> getOperand ( i ) . isReg ( ) || ! TargetRegisterInfo :: isVirtualRegister ( MI -> getOperand ( i ) . getReg ( ) ) ) continue ; const TargetRegisterClass * OpRC = MRI . getRegClass ( MI -> getOperand ( i ) . getReg ( ) ) ; if ( RI . hasVGPRs ( OpRC ) ) { VRC = OpRC ; } else { SRC = OpRC ; } } if ( VRC || ! RI . isSGPRClass ( getOpRegClass ( * MI , <NUM_LIT> ) ) ) { if ( ! VRC ) { assert ( SRC ) ; VRC = RI . getEquivalentVGPRClass ( SRC ) ; } RC = VRC ; } else { RC = SRC ; } for ( unsigned I = <NUM_LIT> , E = MI -> getNumOperands ( ) ; I != E ; I += <NUM_LIT> ) { MachineOperand & Op = MI -> getOperand ( I ) ; if ( ! Op . isReg ( ) || ! TargetRegisterInfo :: isVirtualRegister ( Op . getReg ( ) ) ) continue ; unsigned DstReg = MRI . createVirtualRegister ( RC ) ; MachineBasicBlock * InsertBB = MI -> getOperand ( I + <NUM_LIT> ) . getMBB ( ) ; MachineBasicBlock :: iterator Insert = InsertBB -> getFirstTerminator ( ) ; BuildMI ( * InsertBB , Insert , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DstReg ) . addOperand ( Op ) ; Op . setReg ( DstReg ) ; } } if ( MI -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock * MBB = MI -> getParent ( ) ; const TargetRegisterClass * DstRC = getOpRegClass ( * MI , <NUM_LIT> ) ; if ( RI . hasVGPRs ( DstRC ) ) { for ( unsigned I = <NUM_LIT> , E = MI -> getNumOperands ( ) ; I != E ; I += <NUM_LIT> ) { MachineOperand & Op = MI -> getOperand ( I ) ; if ( ! Op . isReg ( ) || ! TargetRegisterInfo :: isVirtualRegister ( Op . getReg ( ) ) ) continue ; const TargetRegisterClass * OpRC = MRI . getRegClass ( Op . getReg ( ) ) ; const TargetRegisterClass * VRC = RI . getEquivalentVGPRClass ( OpRC ) ; if ( VRC == OpRC ) continue ; unsigned DstReg = MRI . createVirtualRegister ( VRC ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DstReg ) . addOperand ( Op ) ; Op . setReg ( DstReg ) ; Op . setIsKill ( ) ; } } return ; }


<s> moveSMRDToVALU ( Inst , MRI , Worklist ) ; continue ; } break ; case <STR_LIT> : splitScalar64BitBinaryOp ( Worklist , Inst , <STR_LIT> ) ; Inst -> eraseFromParent ( ) ; continue ; case <STR_LIT> : splitScalar64BitBinaryOp ( Worklist , Inst , <STR_LIT> ) ; Inst -> eraseFromParent ( ) ; continue ; case <STR_LIT> : splitScalar64BitBinaryOp ( Worklist , Inst , <STR_LIT> ) ; Inst -> eraseFromParent ( ) ; continue ; case <STR_LIT> : splitScalar64BitUnaryOp ( Worklist , Inst , <STR_LIT> ) ; Inst -> eraseFromParent ( ) ; continue ; case <STR_LIT> : splitScalar64BitBCNT ( Worklist , Inst ) ; Inst -> eraseFromParent ( ) ; continue ; case <STR_LIT> : { splitScalar64BitBFE ( Worklist , Inst ) ; Inst -> eraseFromParent ( ) ; continue ; } case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; } if ( NewOpcode == <STR_LIT> ) { legalizeOperands ( Inst ) ; continue ; } const MCInstrDesc & NewDesc = get ( NewOpcode ) ; Inst -> setDesc ( NewDesc ) ; for ( unsigned i = Inst -> getNumOperands ( ) - <NUM_LIT> ; i > <NUM_LIT> ; -- i ) { MachineOperand & Op = Inst -> getOperand ( i ) ; if ( Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> ) Inst -> RemoveOperand ( i ) ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Size = ( Opcode == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( Size ) ) ; } else if ( Opcode == <STR_LIT> ) { Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; }

Inst -> addImplicitDefUseOperands ( * Inst -> getParent ( ) -> getParent ( ) ) ;


<s> break ; } } const MachineOperand * Dst = getNamedOperand ( MI , <STR_LIT> :: vdst ) ; const MachineOperand * Src0 = getNamedOperand ( MI , <STR_LIT> :: src0 ) ; const MachineOperand * Src0Mods = getNamedOperand ( MI , <STR_LIT> :: src0_modifiers ) ; const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; const MachineOperand * Src1Mods = getNamedOperand ( MI , <STR_LIT> :: src1_modifiers ) ; const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ; const MachineOperand * Clamp = getNamedOperand ( MI , <STR_LIT> :: clamp ) ; const MachineOperand * Omod = getNamedOperand ( MI , <STR_LIT> :: omod ) ; MachineInstrBuilder MIB ; MachineBasicBlock & MBB = * MI . getParent ( ) ; if ( ! Src0Mods && ! Src1Mods && ! Clamp && ! Omod && ! IsF64 && ( ST . getConstantBusLimit ( Opc ) > <NUM_LIT> || ! Src0 -> isReg ( ) || ! RI . isSGPRReg ( MBB . getParent ( ) -> getRegInfo ( ) , Src0 -> getReg ( ) ) ) ) { int64_t Imm ; if ( getFoldableImm ( Src2 , Imm ) ) { unsigned NewOpc = IsFMA ? ( IsF16 ? <STR_LIT> : <STR_LIT> ) : ( IsF16 ? <STR_LIT> : <STR_LIT> ) ; if ( pseudoToMCOpcode ( NewOpc ) != - <NUM_LIT> ) { MIB = BuildMI ( MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( * Dst ) . add ( * Src0 ) . add ( * Src1 ) . addImm ( Imm ) ; updateLiveVariables ( LV , MI , * MIB ) ; if ( LIS ) LIS -> ReplaceMachineInstrInMaps ( MI , * MIB ) ; return MIB ; } } unsigned NewOpc = IsFMA ? ( IsF16 ? <STR_LIT> : <STR_LIT> ) : ( IsF16 ? <STR_LIT> : <STR_LIT> ) ; if ( getFoldableImm ( Src1 , Imm ) ) { if ( pseudoToMCOpcode ( NewOpc ) != - <NUM_LIT> ) { MIB = BuildMI ( MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( * Dst ) . add ( * Src0 ) . addImm ( Imm ) . add ( * Src2 ) ; updateLiveVariables ( LV , MI , * MIB ) ; if ( LIS ) LIS -> ReplaceMachineInstrInMaps ( MI , * MIB ) ;


<s> const MachineOperand * Src0 = & MI . getOperand ( Src0Idx ) ; if ( ! Src0 -> isReg ( ) && ! Src0 -> isImm ( ) ) return nullptr ; if ( Src0 -> isImm ( ) && ! isInlineConstant ( MI , Src0Idx , * Src0 ) ) return nullptr ; break ; } } const MachineOperand * Dst = getNamedOperand ( MI , <STR_LIT> :: vdst ) ; const MachineOperand * Src0 = getNamedOperand ( MI , <STR_LIT> :: src0 ) ; const MachineOperand * Src0Mods = getNamedOperand ( MI , <STR_LIT> :: src0_modifiers ) ; const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; const MachineOperand * Src1Mods = getNamedOperand ( MI , <STR_LIT> :: src1_modifiers ) ; const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ; const MachineOperand * Clamp = getNamedOperand ( MI , <STR_LIT> :: clamp ) ; const MachineOperand * Omod = getNamedOperand ( MI , <STR_LIT> :: omod ) ; MachineInstrBuilder MIB ; MachineBasicBlock & MBB = * MI . getParent ( ) ; if ( ! Src0Mods && ! Src1Mods && ! Clamp && ! Omod && ! IsF64 && ( ST . getConstantBusLimit ( Opc ) > <NUM_LIT> || ! Src0 -> isReg ( ) || ! RI . isSGPRReg ( MBB . getParent ( ) -> getRegInfo ( ) , Src0 -> getReg ( ) ) ) ) { int64_t Imm ; if ( getFoldableImm ( Src2 , Imm ) ) { unsigned NewOpc = IsFMA ? ( IsF16 ? <STR_LIT> : <STR_LIT> ) : ( IsF16 ? <STR_LIT> : <STR_LIT> ) ; if ( pseudoToMCOpcode ( NewOpc ) != - <NUM_LIT> ) { MIB = BuildMI ( MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( * Dst ) . add ( * Src0 ) . add ( * Src1 ) . addImm ( Imm ) ; updateLiveVariables ( LV , MI , * MIB ) ; if ( LIS ) LIS -> ReplaceMachineInstrInMaps ( MI , * MIB ) ; return MIB ; } } unsigned NewOpc = IsFMA ? ( IsF16 ? <STR_LIT> : <STR_LIT> ) : ( IsF16 ? <STR_LIT> : <STR_LIT> ) ; if ( getFoldableImm ( Src1 , Imm ) ) { if ( pseudoToMCOpcode ( NewOpc ) != - <NUM_LIT> ) { MIB = BuildMI ( MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( * Dst ) . add ( * Src0 ) . addImm ( Imm ) . add ( * Src2 ) ; updateLiveVariables ( LV , MI , * MIB ) ; if ( LIS ) LIS -> ReplaceMachineInstrInMaps ( MI , * MIB ) ; return MIB ; } }


<s> MRI . constrainRegClass ( DestReg , & <STR_LIT> ) ; } if ( RI . spillSGPRToVGPR ( ) ) FrameInfo . setStackID ( FrameIndex , TargetStackID :: SGPRSpill ) ; BuildMI ( MBB , MI , DL , OpDesc , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getStackPtrOffsetReg ( ) , RegState :: Implicit ) ; return ; } unsigned Opcode = RI . hasAGPRs ( RC ) ? getAGPRSpillRestoreOpcode ( SpillSize ) : getVGPRSpillRestoreOpcode ( SpillSize ) ;

auto MIB = BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) ;


<s> if ( RI . spillSGPRToVGPR ( ) ) FrameInfo . setStackID ( FrameIndex , TargetStackID :: SGPRSpill ) ; BuildMI ( MBB , MI , DL , OpDesc , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getStackPtrOffsetReg ( ) , RegState :: Implicit ) ; return ; } unsigned Opcode = RI . hasAGPRs ( RC ) ? getAGPRSpillRestoreOpcode ( SpillSize ) : getVGPRSpillRestoreOpcode ( SpillSize ) ; auto MIB = BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) ; if ( RI . hasAGPRs ( RC ) ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; Register Tmp = MRI . createVirtualRegister ( & <STR_LIT> ) ; MIB . addReg ( Tmp , RegState :: Define ) ;


<s> const MCInstrDesc & OpDesc = get ( getSGPRSpillSaveOpcode ( SpillSize ) ) ; if ( Register :: isVirtualRegister ( SrcReg ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; } BuildMI ( MBB , MI , DL , OpDesc ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getStackPtrOffsetReg ( ) , RegState :: Implicit ) ; if ( RI . spillSGPRToVGPR ( ) ) FrameInfo . setStackID ( FrameIndex , TargetStackID :: SGPRSpill ) ; return ; } unsigned Opcode = RI . hasAGPRs ( RC ) ? getAGPRSpillSaveOpcode ( SpillSize ) : getVGPRSpillSaveOpcode ( SpillSize ) ;


<s> return MO . getReg ( ) == <STR_LIT> && MO . isImplicit ( ) && isVALU ( * MO . getParent ( ) ) && ! readsExecAsData ( * MO . getParent ( ) ) ;


<s> int MCOp = <STR_LIT> ( Opcode , Gen ) ; if ( MCOp == - <NUM_LIT> ) return Opcode ; if ( ST . hasGFX90AInsts ( ) ) { uint16_t NMCOp = ( uint16_t ) - <NUM_LIT> ; NMCOp = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NMCOp == ( uint16_t ) - <NUM_LIT> ) NMCOp = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NMCOp != ( uint16_t ) - <NUM_LIT> ) MCOp = NMCOp ; } if ( MCOp == ( uint16_t ) - <NUM_LIT> ) return - <NUM_LIT> ; if ( isAsmOnlyOpcode ( MCOp ) ) return - <NUM_LIT> ; return MCOp ;


<s> if ( MI . isCompare ( ) ) return true ; switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : return true ; } return false ;


<s> if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; assert ( DestReg != <STR_LIT> && <STR_LIT> ) ; assert ( DestReg != <STR_LIT> && DestReg != <STR_LIT> && DestReg != <STR_LIT> && <STR_LIT> ) ; const MCInstrDesc & OpDesc = get ( getSGPRSpillRestoreOpcode ( SpillSize ) ) ; if ( DestReg . isVirtual ( ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( DestReg , & <STR_LIT> ) ; } if ( RI . spillSGPRToVGPR ( ) ) FrameInfo . setStackID ( FrameIndex , TargetStackID :: SGPRSpill ) ; BuildMI ( MBB , MI , DL , OpDesc , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getStackPtrOffsetReg ( ) , RegState :: Implicit ) ; return ; } unsigned Opcode = RI . isAGPRClass ( RC ) ? getAGPRSpillRestoreOpcode ( SpillSize ) : getVGPRSpillRestoreOpcode ( SpillSize ) ; BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) . addFrameIndex ( FrameIndex ) . addReg ( MFI -> getStackPtrOffsetReg ( ) ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> assert ( SrcReg != <STR_LIT> && <STR_LIT> ) ; assert ( SrcReg != <STR_LIT> && SrcReg != <STR_LIT> && SrcReg != <STR_LIT> && <STR_LIT> ) ; const MCInstrDesc & OpDesc = get ( getSGPRSpillSaveOpcode ( SpillSize ) ) ; if ( SrcReg . isVirtual ( ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; } BuildMI ( MBB , MI , DL , OpDesc ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getStackPtrOffsetReg ( ) , RegState :: Implicit ) ; if ( RI . spillSGPRToVGPR ( ) ) FrameInfo . setStackID ( FrameIndex , TargetStackID :: SGPRSpill ) ; return ; } unsigned Opcode = RI . isAGPRClass ( RC ) ? getAGPRSpillSaveOpcode ( SpillSize ) : getVGPRSpillSaveOpcode ( SpillSize ) ; MFI -> setHasSpilledVGPRs ( ) ;

BuildMI ( MBB , MI , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addReg ( MFI -> getStackPtrOffsetReg ( ) ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> unsigned STmp0 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; unsigned STmp1 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp0 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Z ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Y ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( STmp1 ) . addReg ( STmp0 ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp1 ) . addReg ( TIDIGXReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp0 ) . addReg ( TIDIGYReg ) . addReg ( TIDReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( TIDReg ) . addReg ( TIDIGZReg ) ;


<s> if ( BaseReg1 == BaseReg2 ) return true ; if ( ! MI1 . hasOneMemOperand ( ) || ! MI2 . hasOneMemOperand ( ) ) return false ; auto MO1 = * MI1 . memoperands_begin ( ) ; auto MO2 = * MI2 . memoperands_begin ( ) ; if ( MO1 -> getAddrSpace ( ) != MO2 -> getAddrSpace ( ) ) return false ; auto Base1 = MO1 -> getValue ( ) ; auto Base2 = MO2 -> getValue ( ) ; if ( ! Base1 || ! Base2 ) return false ; const MachineFunction & MF = * MI1 . getParent ( ) -> getParent ( ) ;

const DataLayout & DL = MF . getFunction ( ) -> getParent ( ) -> getDataLayout ( ) ;


<s> auto MO2 = * MI2 . memoperands_begin ( ) ; if ( MO1 -> getAddrSpace ( ) != MO2 -> getAddrSpace ( ) ) return false ; auto Base1 = MO1 -> getValue ( ) ; auto Base2 = MO2 -> getValue ( ) ; if ( ! Base1 || ! Base2 ) return false ; const MachineFunction & MF = * MI1 . getParent ( ) -> getParent ( ) ; const DataLayout & DL = MF . getFunction ( ) -> getParent ( ) -> getDataLayout ( ) ; Base1 = GetUnderlyingObject ( Base1 , DL ) ;

Base2 = GetUnderlyingObject ( Base1 , DL ) ;


<s> splitScalar64BitBinaryOp ( Worklist , Inst , <STR_LIT> ) ; Inst . eraseFromParent ( ) ; continue ; case <STR_LIT> : splitScalar64BitBinaryOp ( Worklist , Inst , <STR_LIT> ) ; Inst . eraseFromParent ( ) ; continue ; case <STR_LIT> : splitScalar64BitBinaryOp ( Worklist , Inst , <STR_LIT> ) ; Inst . eraseFromParent ( ) ; continue ; case <STR_LIT> : splitScalar64BitUnaryOp ( Worklist , Inst , <STR_LIT> ) ; Inst . eraseFromParent ( ) ; continue ; case <STR_LIT> : splitScalar64BitBCNT ( Worklist , Inst ) ; Inst . eraseFromParent ( ) ; continue ; case <STR_LIT> : splitScalar64BitBFE ( Worklist , Inst ) ; Inst . eraseFromParent ( ) ; continue ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : lowerScalarAbs ( Worklist , Inst ) ; Inst . eraseFromParent ( ) ; continue ; case <STR_LIT> : case <STR_LIT> : BuildMI ( * MBB , Inst , Inst . getDebugLoc ( ) , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : movePackToVALU ( Worklist , MRI , Inst ) ; Inst . eraseFromParent ( ) ; continue ; case <STR_LIT> : lowerScalarXnor ( Worklist , Inst ) ; Inst . eraseFromParent ( ) ; continue ; case <STR_LIT> : splitScalar64BitBinaryOp ( Worklist , Inst , <STR_LIT> ) ; Inst . eraseFromParent ( ) ; continue ;


<s> DebugLoc DL = MBB . findDebugLoc ( MI ) ; assert ( SrcReg != MFI -> getStackPtrOffsetReg ( ) && SrcReg != MFI -> getFrameOffsetReg ( ) && SrcReg != MFI -> getScratchWaveOffsetReg ( ) ) ; unsigned Size = FrameInfo . getObjectSize ( FrameIndex ) ; unsigned Align = FrameInfo . getObjectAlignment ( FrameIndex ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , Size , Align ) ; unsigned SpillSize = TRI -> getSpillSize ( * RC ) ; if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; const MCInstrDesc & OpDesc = get ( getSGPRSpillSaveOpcode ( SpillSize ) ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; } MachineInstrBuilder Spill = BuildMI ( MBB , MI , DL , OpDesc ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getFrameOffsetReg ( ) , RegState :: Implicit ) ; FrameInfo . setStackID ( FrameIndex , <NUM_LIT> ) ; if ( ST . hasScalarStores ( ) ) { Spill . addReg ( <STR_LIT> , RegState :: ImplicitDefine | RegState :: Dead ) ; } return ; } if ( ! ST . isVGPRSpillingEnabled ( * MF -> getFunction ( ) ) ) { LLVMContext & Ctx = MF -> getFunction ( ) -> getContext ( ) ; Ctx . emitError ( <STR_LIT> <STR_LIT> ) ;

BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg ) ;


<s> assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) ; return ; } unsigned EltSize = <NUM_LIT> ; unsigned Opcode = <STR_LIT> ; if ( RI . isSGPRClass ( RC ) ) { if ( RI . getRegSizeInBits ( * RC ) > <NUM_LIT> ) { Opcode = <STR_LIT> ; EltSize = <NUM_LIT> ; } else { Opcode = <STR_LIT> ; EltSize = <NUM_LIT> ; } if ( ! RI . isSGPRClass ( RI . getPhysRegClass ( SrcReg ) ) ) { reportIllegalCopy ( this , MBB , MI , DL , DestReg , SrcReg , KillSrc ) ; return ; } } ArrayRef < int16_t > SubIndices = RI . getRegSplitParts ( RC , EltSize ) ; bool Forward = RI . getHWRegIndex ( DestReg ) <= RI . getHWRegIndex ( SrcReg ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < SubIndices . size ( ) ; ++ Idx ) { unsigned SubIdx ; if ( Forward ) SubIdx = SubIndices [ Idx ] ; else SubIdx = SubIndices [ SubIndices . size ( ) - Idx - <NUM_LIT> ] ;

MachineInstrBuilder Builder = BuildMI ( MBB , MI , DL , get ( Opcode ) , RI . getSubReg ( DestReg , SubIdx ) ) ;


<s> const MCInstrDesc & OpDesc = get ( getSGPRSpillRestoreOpcode ( SpillSize ) ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( DestReg , & <STR_LIT> ) ; } MachineInstrBuilder Spill = BuildMI ( MBB , MI , DL , OpDesc , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getScratchWaveOffsetReg ( ) , RegState :: Implicit ) ; if ( ST . hasScalarStores ( ) ) { Spill . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; } return ; } if ( ! ST . isVGPRSpillingEnabled ( * MF -> getFunction ( ) ) ) { LLVMContext & Ctx = MF -> getFunction ( ) -> getContext ( ) ; Ctx . emitError ( <STR_LIT> <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) ;


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineFrameInfo & FrameInfo = MF -> getFrameInfo ( ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; unsigned Size = FrameInfo . getObjectSize ( FrameIndex ) ; unsigned Align = FrameInfo . getObjectAlignment ( FrameIndex ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , Size , Align ) ; unsigned SpillSize = TRI -> getSpillSize ( * RC ) ; if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; const MCInstrDesc & OpDesc = get ( getSGPRSpillSaveOpcode ( SpillSize ) ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; } MachineInstrBuilder Spill = BuildMI ( MBB , MI , DL , OpDesc ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getScratchWaveOffsetReg ( ) , RegState :: Implicit ) ; if ( ST . hasScalarStores ( ) ) { Spill . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; } return ; } if ( ! ST . isVGPRSpillingEnabled ( * MF -> getFunction ( ) ) ) { LLVMContext & Ctx = MF -> getFunction ( ) -> getContext ( ) ; Ctx . emitError ( <STR_LIT> <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg ) ; return ; }

assert ( RI . hasVGPRs ( RC ) && <STR_LIT> ) ;


<s> int Src0Idx = <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> :: src0 ) ; const MachineOperand * Src0 = & MI . getOperand ( Src0Idx ) ; if ( Src0 -> isImm ( ) && ! isInlineConstant ( MI , Src0Idx , * Src0 ) ) return nullptr ; break ; } } const MachineOperand * Dst = getNamedOperand ( MI , <STR_LIT> :: vdst ) ; const MachineOperand * Src0 = getNamedOperand ( MI , <STR_LIT> :: src0 ) ; const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ;

return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( IsF16 ? <STR_LIT> : <STR_LIT> ) ) . addOperand ( * Dst ) . addImm ( <NUM_LIT> ) . addOperand ( * Src0 ) . addImm ( <NUM_LIT> ) . addOperand ( * Src1 ) . addImm ( <NUM_LIT> ) . addOperand ( * Src2 ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MCInstrDesc & MovRelDesc = get ( <STR_LIT> ) ; unsigned VecReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsUndef = MI . getOperand ( <NUM_LIT> ) . isUndef ( ) ; unsigned SubReg = <STR_LIT> + MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( VecReg == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineInstr * MovRel = BuildMI ( MBB , MI , DL , MovRelDesc ) . addReg ( RI . getSubReg ( VecReg , SubReg ) , RegState :: Undef ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( VecReg , RegState :: ImplicitDefine ) . addReg ( VecReg , RegState :: Implicit | ( IsUndef ? RegState :: Undef : <NUM_LIT> ) ) ; const int ImpDefIdx = MovRelDesc . getNumOperands ( ) + MovRelDesc . getNumImplicitUses ( ) ; const int ImpUseIdx = ImpDefIdx + <NUM_LIT> ; MovRel -> tieOperands ( ImpDefIdx , ImpUseIdx ) ; MI . eraseFromParent ( ) ; break ; } case <STR_LIT> : { MachineFunction & MF = * MBB . getParent ( ) ; unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned RegLo = RI . getSubReg ( Reg , <STR_LIT> ) ; unsigned RegHi = RI . getSubReg ( Reg , <STR_LIT> ) ; MIBundleBuilder Bundler ( MBB , MI ) ; Bundler . append ( BuildMI ( MF , DL , get ( <STR_LIT> ) , Reg ) ) ; Bundler . append ( BuildMI ( MF , DL , get ( <STR_LIT> ) , RegLo ) . addReg ( RegLo ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) , RegHi ) . addReg ( RegHi ) ;

if ( MI . getOperand ( <NUM_LIT> ) . getTargetFlags ( ) == <ISA_LIT>InstrInfo :: MO_NONE ) MIB . addImm ( <NUM_LIT> ) ;


<s> unsigned <ISA_LIT>InstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const { if ( ! FBB && Cond . empty ( ) ) { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded = <NUM_LIT> ; return <NUM_LIT> ; } assert ( TBB && Cond [ <NUM_LIT> ] . isImm ( ) ) ; unsigned Opcode = getBranchOpcode ( static_cast < BranchPredicate > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; if ( ! FBB ) { Cond [ <NUM_LIT> ] . isUndef ( ) ;

MachineInstr * CondBr = BuildMI ( & MBB , DL , get ( Opcode ) ) . addMBB ( TBB ) ;


<s> return <STR_LIT> ( MO . getImm ( ) , ST . hasInv2PiInlineImm ( ) ) ; } case <NUM_LIT> : { if ( isInt < <NUM_LIT> > ( Imm ) || isUInt < <NUM_LIT> > ( Imm ) ) { int16_t Trunc = static_cast < int16_t > ( Imm ) ; return <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ; } return false ;


<s> void <ISA_LIT>InstrInfo :: legalizeGenericOperand ( MachineBasicBlock & InsertMBB , MachineBasicBlock :: iterator I , const TargetRegisterClass * DstRC , MachineOperand & Op , MachineRegisterInfo & MRI , const DebugLoc & DL ) const { unsigned OpReg = Op . getReg ( ) ; unsigned OpSubReg = Op . getSubReg ( ) ; const TargetRegisterClass * OpRC = RI . getSubClassWithSubReg ( RI . getRegClassForReg ( MRI , OpReg ) , OpSubReg ) ; if ( DstRC == OpRC ) return ; unsigned DstReg = MRI . createVirtualRegister ( DstRC ) ; MachineInstr * Copy = BuildMI ( InsertMBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addOperand ( Op ) ; Op . setReg ( DstReg ) ; Op . setSubReg ( <NUM_LIT> ) ; MachineInstr * Def = MRI . getVRegDef ( OpReg ) ; if ( ! Def ) return ;

if ( Def -> isMoveImmediate ( ) ) FoldImmediate ( * Copy , * Def , OpReg , & MRI ) ;


<s> FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdata ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdata ) ; } else if ( isSMRD ( FirstLdSt ) && isSMRD ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: sdst ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: sdst ) ;

} else if ( isDS ( FirstLdSt ) && isDS ( SecondLdSt ) ) {


<s> if ( isMUBUF ( LdSt ) || isMTBUF ( LdSt ) ) { const MachineOperand * SOffset = getNamedOperand ( LdSt , <STR_LIT> :: soffset ) ; if ( SOffset && SOffset -> isReg ( ) ) { const MachineOperand * AddrReg = getNamedOperand ( LdSt , <STR_LIT> :: vaddr ) ; if ( AddrReg && ! AddrReg -> isFI ( ) ) return false ; const MachineOperand * RSrc = getNamedOperand ( LdSt , <STR_LIT> :: srsrc ) ; const <ISA_LIT>MachineFunctionInfo * MFI = LdSt . getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( RSrc -> getReg ( ) != MFI -> getScratchRSrcReg ( ) ) return false ; const MachineOperand * OffsetImm = getNamedOperand ( LdSt , <STR_LIT> :: offset ) ; BaseOps . push_back ( RSrc ) ; BaseOps . push_back ( SOffset ) ; Offset = OffsetImm -> getImm ( ) ; MOp = getNamedOperand ( LdSt , <STR_LIT> :: vdst ) ; if ( ! MOp ) MOp = getNamedOperand ( LdSt , <STR_LIT> :: vdata ) ; Width = getOperandSizeInBytes ( LdSt , MOp ) ; return true ; } BaseOp = getNamedOperand ( LdSt , <STR_LIT> :: srsrc ) ; if ( ! BaseOp ) return false ; BaseOps . push_back ( BaseOp ) ; BaseOp = getNamedOperand ( LdSt , <STR_LIT> :: vaddr ) ; if ( BaseOp ) BaseOps . push_back ( BaseOp ) ; const MachineOperand * OffsetImm = getNamedOperand ( LdSt , <STR_LIT> :: offset ) ; Offset = OffsetImm -> getImm ( ) ; if ( SOffset ) Offset += SOffset -> getImm ( ) ; MOp = getNamedOperand ( LdSt , <STR_LIT> :: vdst ) ; if ( ! MOp ) MOp = getNamedOperand ( LdSt , <STR_LIT> :: vdata ) ; Width = getOperandSizeInBytes ( LdSt , MOp ) ; return true ; } if ( isSMRD ( LdSt ) ) {

BaseOp = getNamedOperand ( LdSt , <STR_LIT> :: sbase ) ;


<s> assert ( MOp && <STR_LIT> ) ; const MachineRegisterInfo & MRI = LdSt . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const Register Reg = MOp -> getReg ( ) ; const TargetRegisterClass * DstRC = Register :: isVirtualRegister ( Reg ) ? MRI . getRegClass ( Reg ) : RI . getPhysRegClass ( Reg ) ; return ( RI . getRegSizeInBits ( * DstRC ) / <NUM_LIT> ) ;


<s> unsigned <ISA_LIT>InstrInfo :: getOperandSizeInBytes ( const MachineInstr & LdSt , const MachineOperand * MOp ) const { assert ( MOp && <STR_LIT> ) ; const MachineRegisterInfo & MRI = LdSt . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const Register Reg = MOp -> getReg ( ) ; const TargetRegisterClass * DstRC = Register :: isVirtualRegister ( Reg ) ? MRI . getRegClass ( Reg ) : RI . getPhysRegClass ( Reg ) ;

return ( RI . getRegSizeInBits ( * DstRC ) / <NUM_LIT> ) ;


<s> bool isLDSDIR ( uint16_t Opcode ) const { return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> bool isLDSDIR ( uint16_t Opcode ) const {

return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI . isTerminator ( ) || MI . isPosition ( ) ) return true ;

return MI . modifiesRegister ( <STR_LIT> , & RI ) || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || changesVGPRIndexingMode ( MI ) ;


<s> bool <ISA_LIT>InstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const {

if ( MI . isTerminator ( ) || MI . isPosition ( ) ) return true ;


<s> if ( ! memOpsHaveSameBasePtr ( FirstLdSt , BaseOps1 , SecondLdSt , BaseOps2 ) ) return false ; const MachineOperand * FirstDst = nullptr ; const MachineOperand * SecondDst = nullptr ; if ( ( isMUBUF ( FirstLdSt ) && isMUBUF ( SecondLdSt ) ) || ( isMTBUF ( FirstLdSt ) && isMTBUF ( SecondLdSt ) ) || ( isFLAT ( FirstLdSt ) && isFLAT ( SecondLdSt ) ) ) { const unsigned MaxGlobalLoadCluster = <NUM_LIT> ; if ( NumLoads > MaxGlobalLoadCluster ) return false ; FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdata ) ; if ( ! FirstDst ) FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdata ) ; if ( ! SecondDst ) SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdst ) ; } else if ( isSMRD ( FirstLdSt ) && isSMRD ( SecondLdSt ) ) {

FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: sdst ) ;


<s> int RSrcIdx = <STR_LIT> ( Opc , <STR_LIT> :: srsrc ) ; return <NUM_LIT> + <NUM_LIT> * ( ( RSrcIdx - VAddr0Idx + <NUM_LIT> ) / <NUM_LIT> ) ; } switch ( Opc ) { case TargetOpcode :: BUNDLE : return getInstBundleSize ( MI ) ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ;

return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) , & ST ) ;


<s> } return HasLiteral ? DescSize + <NUM_LIT> : DescSize ; } if ( isMIMG ( MI ) ) { int VAddr0Idx = <STR_LIT> ( Opc , <STR_LIT> :: vaddr0 ) ; if ( VAddr0Idx < <NUM_LIT> ) return <NUM_LIT> ; int RSrcIdx = <STR_LIT> ( Opc , <STR_LIT> :: srsrc ) ; return <NUM_LIT> + <NUM_LIT> * ( ( RSrcIdx - VAddr0Idx + <NUM_LIT> ) / <NUM_LIT> ) ; } switch ( Opc ) { case TargetOpcode :: BUNDLE : return getInstBundleSize ( MI ) ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) , & ST ) ; } default : if ( MI . isMetaInstruction ( ) ) return <NUM_LIT> ; return DescSize ; }


<s> const MachineOperand * Src0Mods = getNamedOperand ( MI , <STR_LIT> :: src0_modifiers ) ; const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; const MachineOperand * Src1Mods = getNamedOperand ( MI , <STR_LIT> :: src1_modifiers ) ; const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ; const MachineOperand * Clamp = getNamedOperand ( MI , <STR_LIT> :: clamp ) ; const MachineOperand * Omod = getNamedOperand ( MI , <STR_LIT> :: omod ) ; MachineInstrBuilder MIB ; if ( ! Src0Mods && ! Src1Mods && ! Clamp && ! Omod && ! IsF64 && ( ST . getConstantBusLimit ( Opc ) > <NUM_LIT> || ! Src0 -> isReg ( ) || ! RI . isSGPRReg ( MBB -> getParent ( ) -> getRegInfo ( ) , Src0 -> getReg ( ) ) ) ) { int64_t Imm ; if ( getFoldableImm ( Src2 , Imm ) ) { unsigned NewOpc = IsFMA ? ( IsF16 ? <STR_LIT> : <STR_LIT> ) : ( IsF16 ? <STR_LIT> : <STR_LIT> ) ; if ( pseudoToMCOpcode ( NewOpc ) != - <NUM_LIT> ) { MIB = BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( * Dst ) . add ( * Src0 ) . add ( * Src1 ) . addImm ( Imm ) ; updateLiveVariables ( LV , MI , * MIB ) ; return MIB ; } } unsigned NewOpc = IsFMA ? ( IsF16 ? <STR_LIT> : <STR_LIT> ) : ( IsF16 ? <STR_LIT> : <STR_LIT> ) ; if ( getFoldableImm ( Src1 , Imm ) ) { if ( pseudoToMCOpcode ( NewOpc ) != - <NUM_LIT> ) { MIB = BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( * Dst ) . add ( * Src0 ) . addImm ( Imm ) . add ( * Src2 ) ; updateLiveVariables ( LV , MI , * MIB ) ; return MIB ; } } if ( getFoldableImm ( Src0 , Imm ) ) {

if ( pseudoToMCOpcode ( NewOpc ) != - <NUM_LIT> && isOperandLegal ( MI , <STR_LIT> ( NewOpc , <STR_LIT> :: src0 ) , Src1 ) ) {


<s> if ( CmpValue != ExpectedValue ) { if ( ! IsReversable ) return false ; IsReversedCC = CmpValue == ( ExpectedValue ^ Mask ) ; if ( ! IsReversedCC ) return false ; } Register DefReg = Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( IsReversedCC && ! MRI -> hasOneNonDBGUse ( DefReg ) ) return false ; for ( auto I = std :: next ( Def -> getIterator ( ) ) , E = CmpInstr . getIterator ( ) ; I != E ; ++ I ) { if ( I -> modifiesRegister ( <STR_LIT> , & RI ) || I -> killsRegister ( <STR_LIT> , & RI ) ) return false ; } MachineOperand * SccDef = Def -> findRegisterDefOperand ( <STR_LIT> ) ; SccDef -> setIsDead ( false ) ; CmpInstr . eraseFromParent ( ) ; if ( ! MRI -> use_nodbg_empty ( DefReg ) ) { assert ( ! IsReversedCC ) ; return true ; } MachineBasicBlock * MBB = Def -> getParent ( ) ; unsigned NewOpc = ( SrcSize == <NUM_LIT> ) ? IsReversedCC ? <STR_LIT> : <STR_LIT> : IsReversedCC ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MBB , Def , Def -> getDebugLoc ( ) , get ( NewOpc ) ) . add ( * SrcOp ) . addImm ( Log2_64 ( Mask ) ) ; Def -> eraseFromParent ( ) ; return true ; } ; switch ( CmpInstr . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return optimizeCmpAnd ( <NUM_LIT> , <NUM_LIT> , true , false ) ; case <STR_LIT> : case <STR_LIT> : return optimizeCmpAnd ( <NUM_LIT> , <NUM_LIT> , false , false ) ; case <STR_LIT> : case <STR_LIT> : return optimizeCmpAnd ( <NUM_LIT> , <NUM_LIT> , false , true ) ;


<s> Register Undef = MRI . createVirtualRegister ( IsAGPR ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , get ( <STR_LIT> ) , Undef ) ; Register NewVR = MRI . createVirtualRegister ( IsAGPR ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , get ( <STR_LIT> ) , NewVR ) . addReg ( DataReg , <NUM_LIT> , Op . getSubReg ( ) ) . addImm ( <STR_LIT> ) . addReg ( Undef ) . addImm ( <STR_LIT> ) ;


<s> int NumUse = <NUM_LIT> ; for ( auto & Use : MRI . use_nodbg_operands ( VReg ) ) { auto & UseInst = * Use . getParent ( ) ; if ( UseInst . getParent ( ) != DefBB || UseInst . isPHI ( ) ) return true ; if ( ++ NumUse > MaxUseScan ) return true ; } if ( NumUse == <NUM_LIT> ) return false ; const int MaxInstScan = <NUM_LIT> ; int NumInst = <NUM_LIT> ;

for ( auto I = std :: next ( DefMI . getIterator ( ) ) ; ; ++ I ) {


<s> assert ( UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) . isVirtual ( ) ) ; } UseMI . setDesc ( get ( NewOpc ) ) ; UseMI . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( Imm . getSExtValue ( ) ) ; UseMI . addImplicitDefUseOperands ( * UseMI . getParent ( ) -> getParent ( ) ) ; return true ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) { if ( hasAnyModifiersSet ( UseMI ) ) return false ; MachineOperand * Src0 = getNamedOperand ( UseMI , <STR_LIT> :: src0 ) ; if ( isInlineConstant ( UseMI , * Src0 , * ImmOp ) ) return false ; bool IsF32 = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; bool IsFMA = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; MachineOperand * Src1 = getNamedOperand ( UseMI , <STR_LIT> :: src1 ) ; MachineOperand * Src2 = getNamedOperand ( UseMI , <STR_LIT> :: src2 ) ; if ( Src0 -> isReg ( ) && Src0 -> getReg ( ) == Reg ) { if ( ! Src1 -> isReg ( ) || RI . isSGPRClass ( MRI -> getRegClass ( Src1 -> getReg ( ) ) ) ) return false ; if ( ! Src2 -> isReg ( ) || RI . isSGPRClass ( MRI -> getRegClass ( Src2 -> getReg ( ) ) ) ) return false ; unsigned NewOpc = IsFMA ? ( IsF32 ? <STR_LIT> : <STR_LIT> ) : ( IsF32 ? <STR_LIT> : <STR_LIT> ) ; if ( pseudoToMCOpcode ( NewOpc ) == - <NUM_LIT> ) return false ; const int64_t Imm = ImmOp -> getImm ( ) ; Register Src1Reg = Src1 -> getReg ( ) ; unsigned Src1SubReg = Src1 -> getSubReg ( ) ; Src0 -> setReg ( Src1Reg ) ; Src0 -> setSubReg ( Src1SubReg ) ; Src0 -> setIsKill ( Src1 -> isKill ( ) ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) UseMI . untieRegOperand ( <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ) ; Src1 -> ChangeToImmediate ( Imm ) ; removeModOperands ( UseMI ) ;


<s> if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) { int64_t Format = ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX11 ? <STR_LIT> :: UFMT_32_FLOAT : <STR_LIT> :: UFMT_32_FLOAT ; return ( Format << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ; } uint64_t RsrcDataFormat = <STR_LIT> ; if ( ST . isAmdHsaOS ( ) ) { if ( ST . getGeneration ( ) <= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) RsrcDataFormat |= ( <NUM_LIT> << <NUM_LIT> ) ;

if ( ST . getGeneration ( ) == <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) RsrcDataFormat |= ( <NUM_LIT> << <NUM_LIT> ) ;


<s> int64_t Format = ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX11 ? <STR_LIT> :: UFMT_32_FLOAT : <STR_LIT> :: UFMT_32_FLOAT ; return ( Format << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ;


<s> int Data0Idx = <STR_LIT> ( Opc , <STR_LIT> :: data0 ) ; EltSize = TRI -> getRegSizeInBits ( * getOpRegClass ( LdSt , Data0Idx ) ) / <NUM_LIT> ; } if ( isStride64 ( Opc ) ) EltSize *= <NUM_LIT> ; BaseOps . push_back ( BaseOp ) ; Offset = EltSize * Offset0 ; DataOpIdx = <STR_LIT> ( Opc , <STR_LIT> :: vdst ) ; if ( DataOpIdx == - <NUM_LIT> ) { DataOpIdx = <STR_LIT> ( Opc , <STR_LIT> :: data0 ) ; Width = getOpSize ( LdSt , DataOpIdx ) ; DataOpIdx = <STR_LIT> ( Opc , <STR_LIT> :: data1 ) ; Width += getOpSize ( LdSt , DataOpIdx ) ; } else { Width = getOpSize ( LdSt , DataOpIdx ) ; } } return true ; } if ( isMUBUF ( LdSt ) || isMTBUF ( LdSt ) ) { const MachineOperand * RSrc = getNamedOperand ( LdSt , <STR_LIT> :: srsrc ) ; if ( ! RSrc ) return false ; BaseOps . push_back ( RSrc ) ; BaseOp = getNamedOperand ( LdSt , <STR_LIT> :: vaddr ) ; if ( BaseOp && ! BaseOp -> isFI ( ) ) BaseOps . push_back ( BaseOp ) ; const MachineOperand * OffsetImm = getNamedOperand ( LdSt , <STR_LIT> :: offset ) ; Offset = OffsetImm -> getImm ( ) ; const MachineOperand * SOffset = getNamedOperand ( LdSt , <STR_LIT> :: soffset ) ; if ( SOffset ) { if ( SOffset -> isReg ( ) ) BaseOps . push_back ( SOffset ) ; else Offset += SOffset -> getImm ( ) ; } DataOpIdx = <STR_LIT> ( Opc , <STR_LIT> :: vdst ) ; if ( DataOpIdx == - <NUM_LIT> ) DataOpIdx = <STR_LIT> ( Opc , <STR_LIT> :: vdata ) ; if ( DataOpIdx == - <NUM_LIT> ) return false ; Width = getOpSize ( LdSt , DataOpIdx ) ; return true ; } if ( isMIMG ( LdSt ) ) { int SRsrcIdx = <STR_LIT> ( Opc , <STR_LIT> :: srsrc ) ;

BaseOps . push_back ( & LdSt . getOperand ( SRsrcIdx ) ) ;


<s> Width = getOpSize ( LdSt , DataOpIdx ) ; } } return true ; } if ( isMUBUF ( LdSt ) || isMTBUF ( LdSt ) ) { const MachineOperand * RSrc = getNamedOperand ( LdSt , <STR_LIT> :: srsrc ) ; if ( ! RSrc ) return false ; BaseOps . push_back ( RSrc ) ; BaseOp = getNamedOperand ( LdSt , <STR_LIT> :: vaddr ) ; if ( BaseOp && ! BaseOp -> isFI ( ) ) BaseOps . push_back ( BaseOp ) ; const MachineOperand * OffsetImm = getNamedOperand ( LdSt , <STR_LIT> :: offset ) ; Offset = OffsetImm -> getImm ( ) ; const MachineOperand * SOffset = getNamedOperand ( LdSt , <STR_LIT> :: soffset ) ; if ( SOffset ) { if ( SOffset -> isReg ( ) ) BaseOps . push_back ( SOffset ) ; else Offset += SOffset -> getImm ( ) ; } DataOpIdx = <STR_LIT> ( Opc , <STR_LIT> :: vdst ) ; if ( DataOpIdx == - <NUM_LIT> ) DataOpIdx = <STR_LIT> ( Opc , <STR_LIT> :: vdata ) ; if ( DataOpIdx == - <NUM_LIT> ) return false ; Width = getOpSize ( LdSt , DataOpIdx ) ; return true ; } if ( isMIMG ( LdSt ) ) { int SRsrcIdx = <STR_LIT> ( Opc , <STR_LIT> :: srsrc ) ; BaseOps . push_back ( & LdSt . getOperand ( SRsrcIdx ) ) ; int VAddr0Idx = <STR_LIT> ( Opc , <STR_LIT> :: vaddr0 ) ; if ( VAddr0Idx >= <NUM_LIT> ) { for ( int I = VAddr0Idx ; I < SRsrcIdx ; ++ I ) BaseOps . push_back ( & LdSt . getOperand ( I ) ) ; } else { BaseOps . push_back ( getNamedOperand ( LdSt , <STR_LIT> :: vaddr ) ) ; } Offset = <NUM_LIT> ; DataOpIdx = <STR_LIT> ( Opc , <STR_LIT> :: vdata ) ; Width = getOpSize ( LdSt , DataOpIdx ) ; return true ; } if ( isSMRD ( LdSt ) ) { BaseOp = getNamedOperand ( LdSt , <STR_LIT> :: sbase ) ; if ( ! BaseOp ) return false ; BaseOps . push_back ( BaseOp ) ; OffsetOp = getNamedOperand ( LdSt , <STR_LIT> :: offset ) ; Offset = OffsetOp ? OffsetOp -> getImm ( ) : <NUM_LIT> ; DataOpIdx = <STR_LIT> ( Opc , <STR_LIT> :: sdst ) ; Width = getOpSize ( LdSt , DataOpIdx ) ; return true ; } if ( isFLAT ( LdSt ) ) { BaseOp = getNamedOperand ( LdSt , <STR_LIT> :: vaddr ) ; if ( BaseOp ) BaseOps . push_back ( BaseOp ) ; BaseOp = getNamedOperand ( LdSt , <STR_LIT> :: saddr ) ;


<s> switch ( MI . getOpcode ( ) ) { default : if ( MI . isMetaInstruction ( ) ) return <NUM_LIT> ; return <NUM_LIT> ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) + <NUM_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: hasAnyModifiersSet ( const MachineInstr & MI ) const { return any_of ( ModifierOpNames , [ & ] ( unsigned Name ) { return hasModifiersSet ( MI , Name ) ; } ) ;


<s> if ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return true ; return MI . modifiesRegister ( <STR_LIT> , & RI ) || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || changesVGPRIndexingMode ( MI ) ;


<s> MachineOperand * SBase = getNamedOperand ( MI , <STR_LIT> :: sbase ) ; if ( SBase && ! RI . isSGPRClass ( MRI . getRegClass ( SBase -> getReg ( ) ) ) ) { Register SGPR = readlaneVGPRToSGPR ( SBase -> getReg ( ) , MI , MRI ) ; SBase -> setReg ( SGPR ) ; } MachineOperand * SOff = getNamedOperand ( MI , <STR_LIT> :: soffset ) ;

if ( SOff && ! RI . isSGPRClass ( MRI . getRegClass ( SOff -> getReg ( ) ) ) ) {


<s> MachineOperand * SBase = getNamedOperand ( MI , <STR_LIT> :: sbase ) ; if ( SBase && ! RI . isSGPRClass ( MRI . getRegClass ( SBase -> getReg ( ) ) ) ) { Register SGPR = readlaneVGPRToSGPR ( SBase -> getReg ( ) , MI , MRI ) ; SBase -> setReg ( SGPR ) ; } MachineOperand * SOff = getNamedOperand ( MI , <STR_LIT> :: soffset ) ; if ( SOff && ! RI . isSGPRClass ( MRI . getRegClass ( SOff -> getReg ( ) ) ) ) { Register SGPR = readlaneVGPRToSGPR ( SOff -> getReg ( ) , MI , MRI ) ; SOff -> setReg ( SGPR ) ; }


<s> unsigned Opc = MI . getOpcode ( ) ; for ( unsigned Name : reverse ( ModifierOpNames ) ) MI . removeOperand ( <STR_LIT> ( Opc , Name ) ) ;


<s> static <ISA_LIT>EncodingFamily subtargetEncodingFamily ( const GCNSubtarget & ST ) { switch ( ST . getGeneration ( ) ) { default : break ; case <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS : case <ISA_LIT>Subtarget :: SEA_ISLANDS : return <STR_LIT> ; case <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS : case <ISA_LIT>Subtarget :: GFX9 : return <STR_LIT> ; case <ISA_LIT>Subtarget :: GFX10 : return <STR_LIT> ; case <ISA_LIT>Subtarget :: GFX11 : return <STR_LIT> ;


<s> default : return nullptr ; case <STR_LIT> : case <STR_LIT> : IsF16 = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : IsF16 = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { int Src0Idx = <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> :: src0 ) ; const MachineOperand * Src0 = & MI . getOperand ( Src0Idx ) ; if ( ! Src0 -> isReg ( ) && ! Src0 -> isImm ( ) ) return nullptr ; if ( Src0 -> isImm ( ) && ! isInlineConstant ( MI , Src0Idx , * Src0 ) ) return nullptr ; break ; } } const MachineOperand * Dst = getNamedOperand ( MI , <STR_LIT> :: vdst ) ; const MachineOperand * Src0 = getNamedOperand ( MI , <STR_LIT> :: src0 ) ; const MachineOperand * Src0Mods = getNamedOperand ( MI , <STR_LIT> :: src0_modifiers ) ; const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; const MachineOperand * Src1Mods = getNamedOperand ( MI , <STR_LIT> :: src1_modifiers ) ; const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ; const MachineOperand * Clamp = getNamedOperand ( MI , <STR_LIT> :: clamp ) ; const MachineOperand * Omod = getNamedOperand ( MI , <STR_LIT> :: omod ) ; MachineInstrBuilder MIB ; if ( ! Src0Mods && ! Src1Mods && ! Clamp && ! Omod && ! IsF64 && ( ST . getConstantBusLimit ( Opc ) > <NUM_LIT> || ! Src0 -> isReg ( ) || ! RI . isSGPRReg ( MBB -> getParent ( ) -> getRegInfo ( ) , Src0 -> getReg ( ) ) ) ) { if ( auto Imm = getFoldableImm ( Src2 ) ) { unsigned NewOpc = IsFMA ? ( IsF16 ? <STR_LIT> : <STR_LIT> ) : ( IsF16 ? <STR_LIT> : <STR_LIT> ) ; if ( pseudoToMCOpcode ( NewOpc ) != - <NUM_LIT> ) { MIB = BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( * Dst ) . add ( * Src0 ) . add ( * Src1 ) . addImm ( Imm ) ; updateLiveVariables ( LV , MI , * MIB ) ; return MIB ; } } unsigned NewOpc = IsFMA ? ( IsF16 ? <STR_LIT> : <STR_LIT> ) : ( IsF16 ? <STR_LIT> : <STR_LIT> ) ; if ( auto Imm = getFoldableImm ( Src1 ) ) { if ( pseudoToMCOpcode ( NewOpc ) != - <NUM_LIT> ) {

MIB = BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( * Dst ) . add ( * Src0 ) . addImm ( Imm ) . add ( * Src2 ) ;


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumOps = MI . getDesc ( ) . getNumOperands ( ) + MI . getDesc ( ) . getNumImplicitUses ( ) ; return MI . getNumOperands ( ) == NumOps ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> SmallDenseSet < unsigned > SGPRsUsed ; Register SGPRReg = findUsedSGPR ( MI , VOP3Idx ) ; if ( SGPRReg != <STR_LIT> ) { SGPRsUsed . insert ( SGPRReg ) ; -- ConstantBusLimit ; } for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { int Idx = VOP3Idx [ i ] ; if ( Idx == - <NUM_LIT> ) break ; MachineOperand & MO = MI . getOperand ( Idx ) ; if ( ! MO . isReg ( ) ) { if ( ! isLiteralConstantLike ( MO , get ( Opc ) . OpInfo [ Idx ] ) ) continue ; if ( LiteralLimit > <NUM_LIT> && ConstantBusLimit > <NUM_LIT> ) { -- LiteralLimit ; -- ConstantBusLimit ; continue ; } -- LiteralLimit ; -- ConstantBusLimit ; legalizeOpWithMove ( MI , Idx ) ; continue ; } if ( RI . hasAGPRs ( MRI . getRegClass ( MO . getReg ( ) ) ) && ! isOperandLegal ( MI , Idx , & MO ) ) { legalizeOpWithMove ( MI , Idx ) ; continue ; } if ( ! RI . isSGPRClass ( MRI . getRegClass ( MO . getReg ( ) ) ) ) continue ; if ( SGPRsUsed . count ( MO . getReg ( ) ) ) continue ;


<s> void <ISA_LIT>InstrInfo :: legalizeOperandsVOP3 ( MachineRegisterInfo & MRI , MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; int VOP3Idx [ <NUM_LIT> ] = { <STR_LIT> ( Opc , <STR_LIT> :: src0 ) , <STR_LIT> ( Opc , <STR_LIT> :: src1 ) , <STR_LIT> ( Opc , <STR_LIT> :: src2 ) } ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { MachineOperand & Src1 = MI . getOperand ( VOP3Idx [ <NUM_LIT> ] ) ; MachineOperand & Src2 = MI . getOperand ( VOP3Idx [ <NUM_LIT> ] ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; if ( Src1 . isReg ( ) && ! RI . isSGPRClass ( MRI . getRegClass ( Src1 . getReg ( ) ) ) ) { Register Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , DL , get ( <STR_LIT> ) , Reg ) . add ( Src1 ) ; Src1 . ChangeToRegister ( Reg , false ) ; } if ( Src2 . isReg ( ) && ! RI . isSGPRClass ( MRI . getRegClass ( Src2 . getReg ( ) ) ) ) { Register Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , DL , get ( <STR_LIT> ) , Reg ) . add ( Src2 ) ; Src2 . ChangeToRegister ( Reg , false ) ; } } int ConstantBusLimit = ST . getConstantBusLimit ( Opc ) ; int LiteralLimit = ST . hasVOP3Literal ( ) ? <NUM_LIT> : <NUM_LIT> ; SmallDenseSet < unsigned > SGPRsUsed ; Register SGPRReg = findUsedSGPR ( MI , VOP3Idx ) ;


<s> case <STR_LIT> : if ( isLiteralConstant ( MI . getOperand ( i ) , RI . getRegClass ( RegClass ) -> getSize ( ) ) ) { ErrInfo = <STR_LIT> ; return false ; } break ; case MCOI :: OPERAND_IMMEDIATE : case <STR_LIT> : if ( ! MI . getOperand ( i ) . isImm ( ) && ! MI . getOperand ( i ) . isFI ( ) ) { ErrInfo = <STR_LIT> ; return false ; } default : continue ; } if ( ! MI . getOperand ( i ) . isReg ( ) ) continue ; if ( RegClass != - <NUM_LIT> ) { unsigned Reg = MI . getOperand ( i ) . getReg ( ) ; if ( Reg == <STR_LIT> || TargetRegisterInfo :: isVirtualRegister ( Reg ) ) continue ; const TargetRegisterClass * RC = RI . getRegClass ( RegClass ) ; if ( ! RC -> contains ( Reg ) ) { ErrInfo = <STR_LIT> ; return false ; } } } if ( isVOP1 ( MI ) || isVOP2 ( MI ) || isVOP3 ( MI ) || isVOPC ( MI ) ) { const int OpIndices [ ] = { Src0Idx , Src1Idx , Src2Idx } ; unsigned ConstantBusCount = <NUM_LIT> ; if ( <STR_LIT> ( Opcode , <STR_LIT> :: imm ) != - <NUM_LIT> ) ++ ConstantBusCount ; unsigned SGPRUsed = findImplicitSGPRRead ( MI ) ; if ( SGPRUsed != <STR_LIT> ) ++ ConstantBusCount ; for ( int OpIdx : OpIndices ) { if ( OpIdx == - <NUM_LIT> ) break ; const MachineOperand & MO = MI . getOperand ( OpIdx ) ; if ( usesConstantBus ( MRI , MO , getOpSize ( Opcode , OpIdx ) ) ) { if ( MO . isReg ( ) ) { if ( MO . getReg ( ) != SGPRUsed ) ++ ConstantBusCount ; SGPRUsed = MO . getReg ( ) ; } else { ++ ConstantBusCount ; } } } if ( ConstantBusCount > <NUM_LIT> ) {