<s> case <STR_LIT> : { if ( SNaN ) return true ; return false ; } case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SNaN ; case <STR_LIT> : case <STR_LIT> : { return SNaN ; } case <STR_LIT> : { unsigned IntrinsicID = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntrinsicID ) { case <STR_LIT> : return true ; case <STR_LIT> : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ; } case <STR_LIT> : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) && DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return false ; } case <STR_LIT> : return SNaN ; default : return false ; }


<s> if ( SNaN ) return true ; return false ; } case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) && DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) && DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) && DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return false ; } case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SNaN ; case <STR_LIT> : case <STR_LIT> : { return SNaN ; } case <STR_LIT> : { unsigned IntrinsicID = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntrinsicID ) { case <STR_LIT> : return true ; case <STR_LIT> : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ; } case <STR_LIT> : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) && DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return false ; } case <STR_LIT> : return SNaN ; default :


<s> ( unsigned ) <STR_LIT> ; SDValue fr = DAG . getNode ( OpCode , DL , FltVT , fqneg , fb , fa ) ; SDValue iq = DAG . getNode ( ToInt , DL , IntVT , fq ) ; fr = DAG . getNode ( <STR_LIT> , DL , FltVT , fr ) ; fb = DAG . getNode ( <STR_LIT> , DL , FltVT , fb ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue cv = DAG . getSetCC ( DL , SetCCVT , fr , fb , <STR_LIT> ) ; jq = DAG . getNode ( <STR_LIT> , DL , VT , cv , jq , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Div = DAG . getNode ( <STR_LIT> , DL , VT , iq , jq ) ; SDValue Rem = DAG . getNode ( <STR_LIT> , DL , VT , Div , RHS ) ; Rem = DAG . getNode ( <STR_LIT> , DL , VT , LHS , Rem ) ; if ( Sign ) { SDValue InRegSize = DAG . getValueType ( EVT :: getIntegerVT ( * DAG . getContext ( ) , DivBits ) ) ; Div = DAG . getNode ( <STR_LIT> , DL , VT , Div , InRegSize ) ; Rem = DAG . getNode ( <STR_LIT> , DL , VT , Rem , InRegSize ) ; } else { SDValue TruncMask = DAG . getConstant ( ( UINT64_C ( <NUM_LIT> ) << DivBits ) - <NUM_LIT> , DL , VT ) ; Div = DAG . getNode ( <STR_LIT> , DL , VT , Div , TruncMask ) ; Rem = DAG . getNode ( <STR_LIT> , DL , VT , Rem , TruncMask ) ;


<s> GlobalAddressSDNode * G = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = G -> getGlobal ( ) ; if ( G -> getAddressSpace ( ) == <ISA_LIT>AS :: LOCAL_ADDRESS || G -> getAddressSpace ( ) == <ISA_LIT>AS :: REGION_ADDRESS ) { if ( ! MFI -> isEntryFunction ( ) ) { SDLoc DL ( Op ) ; const Function & Fn = DAG . getMachineFunction ( ) . getFunction ( ) ; DiagnosticInfoUnsupported BadLDSDecl ( Fn , <STR_LIT> , DL . getDebugLoc ( ) , DS_Warning ) ; DAG . getContext ( ) -> diagnose ( BadLDSDecl ) ; SDValue Trap = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getEntryNode ( ) ) ; SDValue OutputChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Trap , DAG . getRoot ( ) ) ; DAG . setRoot ( OutputChain ) ; return DAG . getUNDEF ( Op . getValueType ( ) ) ;


<s> if ( ! MFI -> isEntryFunction ( ) ) { SDLoc DL ( Op ) ; const Function & Fn = DAG . getMachineFunction ( ) . getFunction ( ) ; DiagnosticInfoUnsupported BadLDSDecl ( Fn , <STR_LIT> , DL . getDebugLoc ( ) , DS_Warning ) ; DAG . getContext ( ) -> diagnose ( BadLDSDecl ) ; SDValue Trap = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getEntryNode ( ) ) ;

SDValue OutputChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Trap , DAG . getRoot ( ) ) ;


<s> SelectionDAG & DAG = DCI . DAG ; EVT VT = LN -> getMemoryVT ( ) ; unsigned Size = VT . getStoreSize ( ) ; unsigned Align = LN -> getAlignment ( ) ; if ( Align < Size && isTypeLegal ( VT ) ) { bool IsFast ; unsigned AS = LN -> getAddressSpace ( ) ; if ( ! allowsMisalignedMemoryAccesses ( VT , AS , Align , LN -> getMemOperand ( ) -> getFlags ( ) , & IsFast ) ) { SDValue Ops [ <NUM_LIT> ] ; if ( VT . isVector ( ) ) std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = scalarizeVectorLoad ( LN , DAG ) ;

else std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = expandUnalignedLoad ( LN , DAG ) ;


<s> SDValue Ops [ <NUM_LIT> ] ; std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = scalarizeVectorLoad ( Load , DAG ) ; return DAG . getMergeValues ( Ops , SL ) ; } SDValue BasePtr = Load -> getBasePtr ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; const MachinePointerInfo & SrcValue = Load -> getMemOperand ( ) -> getPointerInfo ( ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = getSplitDestVTs ( VT , DAG ) ; std :: tie ( LoMemVT , HiMemVT ) = getSplitDestVTs ( MemVT , DAG ) ; std :: tie ( Lo , Hi ) = splitVector ( Op , SL , LoVT , HiVT , DAG ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned BaseAlign = Load -> getAlignment ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , LoVT , Load -> getChain ( ) , BasePtr , SrcValue , LoMemVT , BaseAlign , Load -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue HiPtr = DAG . getObjectPtrOffset ( SL , BasePtr , Size ) ; SDValue HiLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , HiVT , Load -> getChain ( ) , HiPtr , SrcValue . getWithOffset ( LoMemVT . getStoreSize ( ) ) , HiMemVT , HiAlign , Load -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Join ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> return Res ; } case <STR_LIT> : case <STR_LIT> : { if ( ! mayIgnoreSignedZero ( N0 ) ) return SDValue ( ) ; SDValue LHS = N0 . getOperand ( <NUM_LIT> ) ; SDValue MHS = N0 . getOperand ( <NUM_LIT> ) ; SDValue RHS = N0 . getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> ) LHS = LHS . getOperand ( <NUM_LIT> ) ; else if ( MHS . getOpcode ( ) == <STR_LIT> ) MHS = MHS . getOperand ( <NUM_LIT> ) ; else MHS = DAG . getNode ( <STR_LIT> , SL , VT , MHS ) ; if ( RHS . getOpcode ( ) != <STR_LIT> ) RHS = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; else RHS = RHS . getOperand ( <NUM_LIT> ) ; SDValue Res = DAG . getNode ( Opc , SL , VT , LHS , MHS , RHS ) ; if ( ! N0 . hasOneUse ( ) ) DAG . ReplaceAllUsesWith ( N0 , DAG . getNode ( <STR_LIT> , SL , VT , Res ) ) ; return Res ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue LHS = N0 . getOperand ( <NUM_LIT> ) ; SDValue RHS = N0 . getOperand ( <NUM_LIT> ) ; if ( isConstantCostlierToNegate ( RHS ) ) return SDValue ( ) ; SDValue NegLHS = DAG . getNode ( <STR_LIT> , SL , VT , LHS ) ; SDValue NegRHS = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; unsigned Opposite = inverseMinMax ( Opc ) ; SDValue Res = DAG . getNode ( Opposite , SL , VT , NegLHS , NegRHS , N0 -> getFlags ( ) ) ; if ( ! N0 . hasOneUse ( ) ) DAG . ReplaceAllUsesWith ( N0 , DAG . getNode ( <STR_LIT> , SL , VT , Res ) ) ; return Res ; } case <STR_LIT> : { SDValue Ops [ <NUM_LIT> ] ; for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) Ops [ I ] = DAG . getNode ( <STR_LIT> , SL , VT , N0 -> getOperand ( I ) , N0 -> getFlags ( ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , SL , VT , Ops , N0 -> getFlags ( ) ) ; if ( ! N0 . hasOneUse ( ) ) DAG . ReplaceAllUsesWith ( N0 , DAG . getNode ( <STR_LIT> , SL , VT , Res ) ) ; return Res ; }


<s> EVT OldVT = N -> getValueType ( <NUM_LIT> ) ; unsigned OldSize = OldVT . getStoreSizeInBits ( ) ; MemSDNode * MN = cast < MemSDNode > ( N ) ; unsigned AS = MN -> getAddressSpace ( ) ;

if ( OldSize >= <NUM_LIT> && NewSize < <NUM_LIT> && MN -> getAlignment ( ) >= <NUM_LIT> && ( AS == <ISA_LIT>AS :: CONSTANT_ADDRESS || AS == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT || ( isa < LoadSDNode > ( N ) && AS == <ISA_LIT>AS :: GLOBAL_ADDRESS && MN -> isInvariant ( ) ) ) && <ISA_LIT>InstrInfo :: isUniformMMO ( MN -> getMemOperand ( ) ) ) return false ;


<s> EVT <ISA_LIT>TargetLowering :: getEquivalentBitType ( LLVMContext & Ctx , EVT VT ) {

unsigned StoreSize = VT . getStoreSizeInBits ( ) ;


<s> EVT <ISA_LIT>TargetLowering :: getEquivalentBitType ( LLVMContext & Ctx , EVT VT ) { unsigned StoreSize = VT . getStoreSizeInBits ( ) ; if ( StoreSize <= <NUM_LIT> ) return EVT :: getIntegerVT ( Ctx , StoreSize ) ;

return EVT :: getVectorVT ( Ctx , <STR_LIT> , StoreSize / <NUM_LIT> ) ;


<s> return DAG . getStore ( Chain , DL , DAG . getConstant ( * CI , DL , VT ) , InitPtr , MachinePointerInfo ( UndefValue :: get ( PtrTy ) ) , TD . getPrefTypeAlignment ( InitTy ) ) ; } if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( Init ) ) { EVT VT = EVT :: getEVT ( CFP -> getType ( ) ) ; PointerType * PtrTy = PointerType :: get ( CFP -> getType ( ) , <NUM_LIT> ) ; return DAG . getStore ( Chain , DL , DAG . getConstantFP ( * CFP , DL , VT ) , InitPtr , MachinePointerInfo ( UndefValue :: get ( PtrTy ) ) , TD . getPrefTypeAlignment ( CFP -> getType ( ) ) ) ; } if ( StructType * ST = dyn_cast < StructType > ( InitTy ) ) { const StructLayout * SL = TD . getStructLayout ( ST ) ; EVT PtrVT = InitPtr . getValueType ( ) ; SmallVector < SDValue , <NUM_LIT> > Chains ; for ( unsigned I = <NUM_LIT> , N = ST -> getNumElements ( ) ; I != N ; ++ I ) {

SDValue Offset = DAG . getConstant ( SL -> getElementOffset ( I ) , DL , PtrVT ) ;


<s> TargetLowering :: NegatibleCost <ISA_LIT>TargetLowering :: getNegatibleCost ( SDValue Op , SelectionDAG & DAG , bool LegalOperations , bool ForCodeSize , unsigned Depth ) const { switch ( Op . getOpcode ( ) ) {


<s> jq = DAG . getNode ( <STR_LIT> , DL , VT , jq , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; } SDValue ia = LHS ; SDValue ib = RHS ; SDValue fa = DAG . getNode ( ToFp , DL , FltVT , ia ) ; SDValue fb = DAG . getNode ( ToFp , DL , FltVT , ib ) ; SDValue fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fa , DAG . getNode ( <STR_LIT> , DL , FltVT , fb ) ) ; fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ; SDValue fqneg = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>MachineFunction * MFI = MF . getInfo < <ISA_LIT>MachineFunction > ( ) ; unsigned OpCode = MFI -> getMode ( ) . allFP32Denormals ( ) ? ( unsigned ) <STR_LIT> : ( unsigned ) <STR_LIT> ; SDValue fr = DAG . getNode ( OpCode , DL , FltVT , fqneg , fb , fa ) ; SDValue iq = DAG . getNode ( ToInt , DL , IntVT , fq ) ; fr = DAG . getNode ( <STR_LIT> , DL , FltVT , fr ) ; fb = DAG . getNode ( <STR_LIT> , DL , FltVT , fb ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue cv = DAG . getSetCC ( DL , SetCCVT , fr , fb , <STR_LIT> ) ; jq = DAG . getNode ( <STR_LIT> , DL , VT , cv , jq , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Div = DAG . getNode ( <STR_LIT> , DL , VT , iq , jq ) ; SDValue Rem = DAG . getNode ( <STR_LIT> , DL , VT , Div , RHS ) ; Rem = DAG . getNode ( <STR_LIT> , DL , VT , LHS , Rem ) ; if ( Sign ) {

SDValue InRegSize = DAG . getValueType ( EVT :: getIntegerVT ( * DAG . getContext ( ) , DivBits ) ) ;


<s> EVT VT = Op . getValueType ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; MVT IntVT = <STR_LIT> ; MVT FltVT = <STR_LIT> ; unsigned LHSSignBits = DAG . ComputeNumSignBits ( LHS ) ; if ( LHSSignBits < <NUM_LIT> ) return SDValue ( ) ; unsigned RHSSignBits = DAG . ComputeNumSignBits ( RHS ) ; if ( RHSSignBits < <NUM_LIT> ) return SDValue ( ) ; unsigned BitSize = VT . getSizeInBits ( ) ; unsigned SignBits = std :: min ( LHSSignBits , RHSSignBits ) ; unsigned DivBits = BitSize - SignBits ; if ( Sign ) ++ DivBits ; <STR_LIT> ToFp = Sign ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ToInt = Sign ? <STR_LIT> : <STR_LIT> ; SDValue jq = DAG . getConstant ( <NUM_LIT> , DL , IntVT ) ; if ( Sign ) { jq = DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS ) ; jq = DAG . getNode ( <STR_LIT> , DL , VT , jq , DAG . getConstant ( BitSize - <NUM_LIT> , DL , VT ) ) ; jq = DAG . getNode ( <STR_LIT> , DL , VT , jq , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; } SDValue ia = LHS ; SDValue ib = RHS ; SDValue fa = DAG . getNode ( ToFp , DL , FltVT , ia ) ; SDValue fb = DAG . getNode ( ToFp , DL , FltVT , ib ) ; SDValue fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fa , DAG . getNode ( <STR_LIT> , DL , FltVT , fb ) ) ; fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ; SDValue fqneg = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>MachineFunction * MFI = MF . getInfo < <ISA_LIT>MachineFunction > ( ) ; unsigned OpCode = MFI -> getMode ( ) . allFP32Denormals ( ) ? ( unsigned ) <STR_LIT> : ( unsigned ) <STR_LIT> ; SDValue fr = DAG . getNode ( OpCode , DL , FltVT , fqneg , fb , fa ) ; SDValue iq = DAG . getNode ( ToInt , DL , IntVT , fq ) ;

fr = DAG . getNode ( <STR_LIT> , DL , FltVT , fr ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFROUND ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; if ( isOperationLegal ( <STR_LIT> , VT ) ) return LowerFROUND_LegalFTRUNC ( Op , DAG ) ; if ( VT == <STR_LIT> ) return LowerFROUND64 ( Op , DAG ) ;


<s> SDValue X = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; SDValue T = DAG . getNode ( <STR_LIT> , SL , VT , X ) ; SDValue Diff = DAG . getNode ( <STR_LIT> , SL , VT , X , T ) ; SDValue AbsDiff = DAG . getNode ( <STR_LIT> , SL , VT , Diff ) ; const SDValue Zero = DAG . getConstantFP ( <NUM_LIT> , SL , VT ) ; const SDValue One = DAG . getConstantFP ( <NUM_LIT> , SL , VT ) ; const SDValue Half = DAG . getConstantFP ( <NUM_LIT> , SL , VT ) ; SDValue SignOne = DAG . getNode ( <STR_LIT> , SL , VT , One , X ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ;

SDValue Cmp = DAG . getSetCC ( SL , SetCCVT , AbsDiff , Half , <STR_LIT> ) ;


<s> if ( ! RHS ) return SDValue ( ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; unsigned RHSVal = RHS -> getZExtValue ( ) ; if ( ! RHSVal ) return LHS ; SDLoc SL ( N ) ; SelectionDAG & DAG = DCI . DAG ; switch ( LHS -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( VT != <STR_LIT> ) break ; KnownBits Known ; SDValue X = LHS -> getOperand ( <NUM_LIT> ) ; DAG . computeKnownBits ( X , Known ) ; unsigned LZ = Known . countMinLeadingZeros ( ) ; if ( LZ < RHSVal ) break ; EVT XVT = X . getValueType ( ) ; SDValue Shl = DAG . getNode ( <STR_LIT> , SL , XVT , X , SDValue ( RHS , <NUM_LIT> ) ) ; return DAG . getZExtOrTrunc ( Shl , SL , VT ) ; } case <STR_LIT> : if ( ! isOrEquivalentToAdd ( DAG , LHS ) ) break ; case <STR_LIT> : { if ( ConstantSDNode * C2 = dyn_cast < ConstantSDNode > ( LHS -> getOperand ( <NUM_LIT> ) ) ) { SDValue Shl = DAG . getNode ( <STR_LIT> , SL , VT , LHS -> getOperand ( <NUM_LIT> ) , SDValue ( RHS , <NUM_LIT> ) ) ; SDValue C2V = DAG . getConstant ( C2 -> getAPIntValue ( ) << RHSVal , SDLoc ( C2 ) , VT ) ; return DAG . getNode ( LHS -> getOpcode ( ) , SL , VT , Shl , C2V ) ; } break ; } } if ( VT != <STR_LIT> ) return SDValue ( ) ; if ( RHSVal < <NUM_LIT> ) return SDValue ( ) ; SDValue ShiftAmt = DAG . getConstant ( RHSVal - <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LHS ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo , ShiftAmt ) ; const SDValue Zero = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Vec = DAG . getBuildVector ( <STR_LIT> , SL , { Zero , NewShift } ) ;

return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Vec ) ;


<s> SDValue fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fa , DAG . getNode ( <STR_LIT> , DL , FltVT , fb ) ) ; fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ; SDValue fqneg = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>MachineFunction * MFI = MF . getInfo < <ISA_LIT>MachineFunction > ( ) ; unsigned OpCode = MFI -> getMode ( ) . FP32Denormals ? ( unsigned ) <STR_LIT> : ( unsigned ) <STR_LIT> ; SDValue fr = DAG . getNode ( OpCode , DL , FltVT , fqneg , fb , fa ) ; SDValue iq = DAG . getNode ( ToInt , DL , IntVT , fq ) ; fr = DAG . getNode ( <STR_LIT> , DL , FltVT , fr ) ; fb = DAG . getNode ( <STR_LIT> , DL , FltVT , fb ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue cv = DAG . getSetCC ( DL , SetCCVT , fr , fb , <STR_LIT> ) ; jq = DAG . getNode ( <STR_LIT> , DL , VT , cv , jq , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ;

SDValue Div = DAG . getNode ( <STR_LIT> , DL , VT , iq , jq ) ;


<s> bool <ISA_LIT>TargetLowering :: isFNegFree ( EVT VT ) const { return isFAbsFree ( VT ) ;


<s> SDValue U = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 ) ; SDValue UH = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , U , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; UH = DAG . getZExtOrTrunc ( UH , DL , <STR_LIT> ) ; U = DAG . getZExtOrTrunc ( U , DL , <STR_LIT> ) ; SDValue E = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , UH , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; E = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , E , DAG . getConstant ( ExpMask , DL , <STR_LIT> ) ) ; E = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , E , DAG . getConstant ( - ExpBiasf64 + ExpBiasf16 , DL , <STR_LIT> ) ) ; SDValue M = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , UH , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; M = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , M , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue MaskedSig = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , UH , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; MaskedSig = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MaskedSig , U ) ; SDValue Lo40Set = DAG . getSelectCC ( DL , MaskedSig , Zero , Zero , One , <STR_LIT> ) ; M = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , M , Lo40Set ) ; SDValue I = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getSelectCC ( DL , M , Zero , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Zero , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue N = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , M , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , E , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ;

SDValue OneSubExp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , One , E ) ;


<s> Op -> print ( errs ( ) , & DAG ) ; llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; break ; case <STR_LIT> : return Lower<ISA_LIT>GN_EXTEND_INREG ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerFREM ( Op , DAG ) ; case <STR_LIT> : return LowerFCEIL ( Op , DAG ) ; case <STR_LIT> : return LowerFTRUNC ( Op , DAG ) ; case <STR_LIT> : return LowerFRINT ( Op , DAG ) ; case <STR_LIT> : return LowerFNEARBYINT ( Op , DAG ) ; case <STR_LIT> : return LowerFROUND ( Op , DAG ) ;

case <STR_LIT> : return LowerFFLOOR ( Op , DAG ) ;


<s> return CC_<ISA_LIT>_Kernel ; case CallingConv :: <ISA_LIT>_VS : case CallingConv :: <ISA_LIT>_GS : case CallingConv :: <ISA_LIT>_PS : case CallingConv :: <ISA_LIT>_CS : case CallingConv :: <ISA_LIT>_HS :


<s> return CC_<ISA_LIT>_Kernel ; case CallingConv :: <ISA_LIT>_VS : case CallingConv :: <ISA_LIT>_GS : case CallingConv :: <ISA_LIT>_PS : case CallingConv :: <ISA_LIT>_CS : case CallingConv :: <ISA_LIT>_HS : case CallingConv :: <ISA_LIT>_ES : case CallingConv :: <ISA_LIT>_LS : return RetCC_<ISA_LIT>_Shader ; case CallingConv :: C : case CallingConv :: Fast :


<s> case <STR_LIT> : case <STR_LIT> : { KnownBits LHSKnown , RHSKnown ; DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , LHSKnown , Depth + <NUM_LIT> ) ; DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , RHSKnown , Depth + <NUM_LIT> ) ; unsigned TrailZ = LHSKnown . countMinTrailingZeros ( ) + RHSKnown . countMinTrailingZeros ( ) ; Known . Zero . setLowBits ( std :: min ( TrailZ , <NUM_LIT> ) ) ; unsigned LHSValBits = <NUM_LIT> - std :: max ( LHSKnown . countMinSignBits ( ) , <NUM_LIT> ) ; unsigned RHSValBits = <NUM_LIT> - std :: max ( RHSKnown . countMinSignBits ( ) , <NUM_LIT> ) ; unsigned MaxValBits = std :: min ( LHSValBits + RHSValBits , <NUM_LIT> ) ; if ( MaxValBits >= <NUM_LIT> ) break ; bool Negative = false ; if ( Opc == <STR_LIT> ) { bool LHSNegative = ! ! ( LHSKnown . One & ( <NUM_LIT> << <NUM_LIT> ) ) ; bool LHSPositive = ! ! ( LHSKnown . Zero & ( <NUM_LIT> << <NUM_LIT> ) ) ; bool RHSNegative = ! ! ( RHSKnown . One & ( <NUM_LIT> << <NUM_LIT> ) ) ; bool RHSPositive = ! ! ( RHSKnown . Zero & ( <NUM_LIT> << <NUM_LIT> ) ) ; if ( ( ! LHSNegative && ! LHSPositive ) || ( ! RHSNegative && ! RHSPositive ) ) break ; Negative = ( LHSNegative && RHSPositive ) || ( LHSPositive && RHSNegative ) ;


<s> bool <ISA_LIT>TargetLowering :: isFPExtFoldable ( unsigned Opcode , EVT DestVT , EVT SrcVT ) const { return Opcode == <STR_LIT> && Subtarget -> hasMadMixInsts ( ) && DestVT . getScalarType ( ) == <STR_LIT> && ! Subtarget -> hasFP32Denormals ( ) && SrcVT . getScalarType ( ) == <STR_LIT> ;


<s> bool <ISA_LIT>TargetLowering :: isFPExtFoldable ( unsigned Opcode , EVT DestVT , EVT SrcVT ) const {

return Opcode == <STR_LIT> && Subtarget -> hasMadMixInsts ( ) && DestVT . getScalarType ( ) == <STR_LIT> && ! Subtarget -> hasFP32Denormals ( ) && SrcVT . getScalarType ( ) == <STR_LIT> ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( <ISA_LIT>MachineFunction * MFI , SDValue Op , SelectionDAG & DAG ) const { const DataLayout & DL = DAG . getDataLayout ( ) ; GlobalAddressSDNode * G = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = G -> getGlobal ( ) ; if ( G -> getAddressSpace ( ) == AMDGPUA<ISA_LIT> . LOCAL_ADDRESS ) { assert ( G -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ! hasDefinedInitializer ( GV ) ) { unsigned Offset = MFI -> allocateLDSGlobal ( DL , * GV ) ; return DAG . getConstant ( Offset , SDLoc ( Op ) , Op . getValueType ( ) ) ; } } const Function & Fn = DAG . getMachineFunction ( ) . getFunction ( ) ; DiagnosticInfoUnsupported BadInit ( Fn , <STR_LIT> , SDLoc ( Op ) . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( BadInit ) ; return SDValue ( ) ;


<s> if ( LZ < RHSVal ) break ; EVT XVT = X . getValueType ( ) ; SDValue Shl = DAG . getNode ( <STR_LIT> , SL , XVT , X , SDValue ( RHS , <NUM_LIT> ) ) ; return DAG . getZExtOrTrunc ( Shl , SL , VT ) ; } } if ( VT != <STR_LIT> ) return SDValue ( ) ; if ( RHSVal < <NUM_LIT> ) return SDValue ( ) ; SDValue ShiftAmt = DAG . getConstant ( RHSVal - <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LHS ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo , ShiftAmt ) ; const SDValue Zero = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Vec = DAG . getBuildVector ( <STR_LIT> , SL , { Zero , NewShift } ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Vec ) ;


<s> } assert ( G -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ! hasDefinedInitializer ( GV ) ) { unsigned Offset = MFI -> allocateLDSGlobal ( DL , * cast < GlobalVariable > ( GV ) ) ; return DAG . getConstant ( Offset , SDLoc ( Op ) , Op . getValueType ( ) ) ; } } const Function & Fn = DAG . getMachineFunction ( ) . getFunction ( ) ; DiagnosticInfoUnsupported BadInit ( Fn , <STR_LIT> , SDLoc ( Op ) . getDebugLoc ( ) ) ;

DAG . getContext ( ) -> diagnose ( BadInit ) ;


<s> EVT VT = Op . getValueType ( ) ; EVT LegalVT = TLI . getTypeToTransformTo ( * DAG . getContext ( ) , VT ) ; if ( LegalVT != <STR_LIT> ) return SDValue ( ) ; if ( VT != <STR_LIT> ) Op = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Op ) ; SDValue FFBH = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Op ) ;

if ( VT != <STR_LIT> ) FFBH = DAG . getNode ( <STR_LIT> , SL , VT , FFBH ) ;


<s> static SDValue getFFBH_U32 ( const TargetLowering & TLI , SelectionDAG & DAG , SDLoc SL , SDValue Op ) { EVT VT = Op . getValueType ( ) ;

EVT LegalVT = TLI . getTypeToTransformTo ( * DAG . getContext ( ) , VT ) ;


<s> if ( const ExternalSymbolSDNode * G = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) FuncName = G -> getSymbol ( ) ; else if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) FuncName = G -> getGlobal ( ) -> getName ( ) ; DiagnosticInfoUnsupported NoCalls ( Fn , <STR_LIT> + FuncName , CLI . DL . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( NoCalls ) ; return SDValue ( ) ;


<s> SelectionDAG & DAG = CLI . DAG ; const Function & Fn = * DAG . getMachineFunction ( ) . getFunction ( ) ; StringRef FuncName ( <STR_LIT> ) ;

if ( const ExternalSymbolSDNode * G = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) FuncName = G -> getSymbol ( ) ;


<s> break ; case <STR_LIT> : return Lower<ISA_LIT>GN_EXTEND_INREG ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerFREM ( Op , DAG ) ; case <STR_LIT> : return LowerFCEIL ( Op , DAG ) ; case <STR_LIT> : return LowerFTRUNC ( Op , DAG ) ; case <STR_LIT> : return LowerFRINT ( Op , DAG ) ; case <STR_LIT> : return LowerFNEARBYINT ( Op , DAG ) ; case <STR_LIT> : return LowerFROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFFLOOR ( Op , DAG ) ; case <STR_LIT> : return Lower<ISA_LIT>NT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_<ISA_LIT>NT ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ;


<s> case <STR_LIT> : return Lower<ISA_LIT>GN_EXTEND_INREG ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerFREM ( Op , DAG ) ; case <STR_LIT> : return LowerFCEIL ( Op , DAG ) ; case <STR_LIT> : return LowerFTRUNC ( Op , DAG ) ; case <STR_LIT> : return LowerFRINT ( Op , DAG ) ; case <STR_LIT> : return LowerFNEARBYINT ( Op , DAG ) ;

case <STR_LIT> : return LowerFROUND ( Op , DAG ) ;


<s> SDValue REM = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res . getValue ( <NUM_LIT> ) , zero ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DIV ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , REM ) ) ; return ; } SDValue DIV_Part = DAG . getNode ( <STR_LIT> , DL , HalfVT , LHS_Hi , RHS_Lo ) ; SDValue REM_Part = DAG . getNode ( <STR_LIT> , DL , HalfVT , LHS_Hi , RHS_Lo ) ; SDValue REM_Lo = DAG . getSelectCC ( DL , RHS_Hi , zero , REM_Part , LHS_Hi , <STR_LIT> ) ; SDValue REM = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , REM_Lo , zero ) ; REM = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , REM ) ; SDValue DIV_Hi = DAG . getSelectCC ( DL , RHS_Hi , zero , DIV_Part , zero , <STR_LIT> ) ; SDValue DIV_Lo = zero ; const unsigned halfBitWidth = HalfVT . getSizeInBits ( ) ; for ( unsigned i = <NUM_LIT> ; i < halfBitWidth ; ++ i ) { const unsigned bitPos = halfBitWidth - i - <NUM_LIT> ; SDValue POS = DAG . getConstant ( bitPos , DL , HalfVT ) ;

SDValue HBit = DAG . getNode ( <STR_LIT> , DL , HalfVT , LHS_Lo , POS ) ;


<s> return SDValue ( ) ; } SDLoc SL ( N ) ; SelectionDAG & DAG = DCI . DAG ; SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = split64BitValue ( N -> getOperand ( <NUM_LIT> ) , DAG ) ; SDValue LoRHS = DAG . getConstant ( Lo_32 ( Val ) , SL , <STR_LIT> ) ; SDValue HiRHS = DAG . getConstant ( Hi_32 ( Val ) , SL , <STR_LIT> ) ; SDValue LoAnd = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo , LoRHS ) ; SDValue HiAnd = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi , HiRHS ) ; SDValue Vec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LoAnd , HiAnd ) ;


<s> const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHS ) return SDValue ( ) ; uint64_t Val = RHS -> getZExtValue ( ) ; if ( Lo_32 ( Val ) != <NUM_LIT> && Hi_32 ( Val ) != <NUM_LIT> && ! RHS -> hasOneUse ( ) ) { return SDValue ( ) ; } SDLoc SL ( N ) ; SelectionDAG & DAG = DCI . DAG ; SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = split64BitValue ( N -> getOperand ( <NUM_LIT> ) , DAG ) ;

SDValue LoRHS = DAG . getConstant ( Lo_32 ( Val ) , SL , <STR_LIT> ) ;


<s> SDValue CmpLHS = Cond . getOperand ( <NUM_LIT> ) ; if ( CCOpcode == <STR_LIT> && isCtlzOpc ( RHS . getOpcode ( ) ) && RHS . getOperand ( <NUM_LIT> ) == CmpLHS && isNegativeOne ( LHS ) ) { return getFFBH_U32 ( * this , DAG , SL , CmpLHS ) ; } if ( CCOpcode == <STR_LIT> && isCtlzOpc ( LHS . getOpcode ( ) ) && LHS . getOperand ( <NUM_LIT> ) == CmpLHS && isNegativeOne ( RHS ) ) { return getFFBH_U32 ( * this , DAG , SL , CmpLHS ) ; } return SDValue ( ) ;


<s> return getFFBH_U32 ( * this , DAG , SL , CmpLHS ) ; } if ( CCOpcode == <STR_LIT> && isCtlzOpc ( LHS . getOpcode ( ) ) && LHS . getOperand ( <NUM_LIT> ) == CmpLHS && isNegativeOne ( RHS ) ) { return getFFBH_U32 ( * this , DAG , SL , CmpLHS ) ; }


<s> SDLoc SL ( N ) ; SelectionDAG & DAG = DCI . DAG ; SDValue ShiftAmt = DAG . getConstant ( RHSVal - <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LHS ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo , ShiftAmt ) ; const SDValue Zero = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ;

SDValue Vec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Zero , NewShift ) ;


<s> if ( ! RHS ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc SL ( N ) ; unsigned RHSVal = RHS -> getZExtValue ( ) ; if ( RHSVal == <NUM_LIT> ) { SDValue Hi = getHiHalf64 ( N -> getOperand ( <NUM_LIT> ) , DAG ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue BuildVec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi , NewShift ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BuildVec ) ; } if ( RHSVal == <NUM_LIT> ) { SDValue Hi = getHiHalf64 ( N -> getOperand ( <NUM_LIT> ) , DAG ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue BuildVec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NewShift , NewShift ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BuildVec ) ; } return SDValue ( ) ;


<s> if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHS ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc SL ( N ) ; unsigned RHSVal = RHS -> getZExtValue ( ) ; if ( RHSVal == <NUM_LIT> ) { SDValue Hi = getHiHalf64 ( N -> getOperand ( <NUM_LIT> ) , DAG ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue BuildVec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi , NewShift ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BuildVec ) ; }


<s> SDValue VecOp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , VecOp , One ) ; SDValue NewConst = DAG . getConstant ( ShiftAmt - <NUM_LIT> , SL , <STR_LIT> ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi , NewConst ) ;

SDValue BuildPair = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NewShift , Zero ) ;


<s> const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHS ) return SDValue ( ) ; unsigned ShiftAmt = RHS -> getZExtValue ( ) ; if ( ShiftAmt < <NUM_LIT> ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc SL ( N ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue VecOp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , VecOp , One ) ; SDValue NewConst = DAG . getConstant ( ShiftAmt - <NUM_LIT> , SL , <STR_LIT> ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi , NewConst ) ; SDValue BuildPair = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NewShift , Zero ) ;

return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BuildPair ) ;


<s> EVT PtrVT = Load -> getBasePtr ( ) . getValueType ( ) ; unsigned NumElts = Load -> getMemoryVT ( ) . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > Loads ; SmallVector < SDValue , <NUM_LIT> > Chains ; SDLoc SL ( Op ) ; unsigned BaseAlign = Load -> getAlignment ( ) ; unsigned MemEltSize = MemEltVT . getStoreSize ( ) ; MachinePointerInfo SrcValue ( Load -> getMemOperand ( ) -> getValue ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , PtrVT , Load -> getBasePtr ( ) , DAG . getConstant ( i * MemEltSize , SL , PtrVT ) ) ; SDValue NewLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , EltVT , Load -> getChain ( ) , Ptr , SrcValue . getWithOffset ( i * MemEltSize ) , MemEltVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> isInvariant ( ) , MinAlign ( BaseAlign , i * MemEltSize ) ) ;

Loads . push_back ( NewLoad . getValue ( <NUM_LIT> ) ) ;


<s> SmallVector < SDValue , <NUM_LIT> > Loads ; SmallVector < SDValue , <NUM_LIT> > Chains ; SDLoc SL ( Op ) ; unsigned BaseAlign = Load -> getAlignment ( ) ; unsigned MemEltSize = MemEltVT . getStoreSize ( ) ; MachinePointerInfo SrcValue ( Load -> getMemOperand ( ) -> getValue ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , PtrVT , Load -> getBasePtr ( ) , DAG . getConstant ( i * MemEltSize , SL , PtrVT ) ) ; SDValue NewLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , EltVT , Load -> getChain ( ) , Ptr , SrcValue . getWithOffset ( i * MemEltSize ) , MemEltVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> isInvariant ( ) , MinAlign ( BaseAlign , i * MemEltSize ) ) ; Loads . push_back ( NewLoad . getValue ( <NUM_LIT> ) ) ; Chains . push_back ( NewLoad . getValue ( <NUM_LIT> ) ) ; } SDValue Ops [ ] = { DAG . getNode ( <STR_LIT> , SL , LoadVT , Loads ) , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Chains ) } ; return DAG . getMergeValues ( Ops , SL ) ;


<s> SDValue Offset = DAG . getConstant ( i * MemEltVT . getStoreSize ( ) , SL , PtrVT ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , PtrVT , Store -> getBasePtr ( ) , Offset ) ; SDValue NewStore = DAG . getTruncStore ( Store -> getChain ( ) , SL , Val , Ptr , SrcValue . getWithOffset ( i * EltSize ) , MemEltVT , Store -> isNonTemporal ( ) , Store -> isVolatile ( ) , MinAlign ( BaseAlign , i * EltSize ) ) ;


<s> unsigned NumElts = Store -> getMemoryVT ( ) . getVectorNumElements ( ) ; SDLoc SL ( Op ) ; SmallVector < SDValue , <NUM_LIT> > Chains ; unsigned BaseAlign = Store -> getAlignment ( ) ; unsigned EltSize = MemEltVT . getStoreSize ( ) ; MachinePointerInfo SrcValue ( Store -> getMemOperand ( ) -> getValue ( ) ) ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) { SDValue Val = DAG . getNode ( <STR_LIT> , SL , EltVT , Store -> getValue ( ) , DAG . getConstant ( i , SL , <STR_LIT> ) ) ; SDValue Offset = DAG . getConstant ( i * MemEltVT . getStoreSize ( ) , SL , PtrVT ) ;

SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , PtrVT , Store -> getBasePtr ( ) , Offset ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerINTRIN<ISA_LIT>C_WO_CHAIN ( SDValue Op , SelectionDAG & DAG ) const { unsigned IntrinsicID = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; switch ( IntrinsicID ) { default : return Op ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; switch ( IntrinsicID ) { default : return Op ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> switch ( Op . getOpcode ( ) ) { case <STR_LIT> : { ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) return <NUM_LIT> ; unsigned SignBits = <NUM_LIT> - Width -> getZExtValue ( ) + <NUM_LIT> ; ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! Offset || ! Offset -> isNullValue ( ) ) return SignBits ; unsigned Op0SignBits = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; return std :: max ( SignBits , Op0SignBits ) ; } case <STR_LIT> : { ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; return Width ? <NUM_LIT> - ( Width -> getZExtValue ( ) & <NUM_LIT> ) : <NUM_LIT> ; } case <STR_LIT> :


<s> DiagnosticInfoUnsupported ( const Function & Fn , const Twine & Desc , DiagnosticSeverity Severity = DS_Error ) : DiagnosticInfo ( getKindID ( ) , Severity ) , Description ( Desc ) , Fn ( Fn ) {


<s> bool <ISA_LIT>TargetLowering :: isHWFalseValue ( SDValue Op ) const { if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Op ) ) { return CFP -> getValueAPF ( ) . isZero ( ) ; }

if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) {


<s> if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { return C -> isNullValue ( ) ;


<s> return CFP -> isExactlyValue ( <NUM_LIT> ) ; } if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { return C -> isAllOnesValue ( ) ;


<s> bool <ISA_LIT>TargetLowering :: isHWTrueValue ( SDValue Op ) const { if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Op ) ) {

return CFP -> isExactlyValue ( <NUM_LIT> ) ;


<s> } SDValue BasePtr = Store -> getBasePtr ( ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Dst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , Ptr , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SExtValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Store -> getValue ( ) ) ; SDValue MaskedValue = DAG . getZeroExtendInReg ( SExtValue , DL , MemVT ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MaskedValue , ShiftAmt ) ; SDValue DstMask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( Mask , DL , <STR_LIT> ) , ShiftAmt ) ; DstMask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DstMask , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Dst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Dst , DstMask ) ; SDValue Value = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Dst , ShiftedValue ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , Value , Ptr , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } return SDValue ( ) ;


<s> EVT MemVT = Store -> getMemoryVT ( ) ; if ( Store -> getAddressSpace ( ) == <ISA_LIT>AS :: PRIVATE_ADDRESS && MemVT . bitsLT ( <STR_LIT> ) ) { unsigned Mask = <NUM_LIT> ; if ( Store -> getMemoryVT ( ) == <STR_LIT> ) { Mask = <NUM_LIT> ; } else if ( Store -> getMemoryVT ( ) == <STR_LIT> ) { Mask = <NUM_LIT> ; } SDValue BasePtr = Store -> getBasePtr ( ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Dst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , Ptr , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SExtValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Store -> getValue ( ) ) ; SDValue MaskedValue = DAG . getZeroExtendInReg ( SExtValue , DL , MemVT ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MaskedValue , ShiftAmt ) ;

SDValue DstMask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( Mask , DL , <STR_LIT> ) , ShiftAmt ) ;


<s> DP << <STR_LIT> << getDescription ( ) << <STR_LIT> << Fn . getName ( ) ;


<s> std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Op , SL , LoVT , HiVT ) ; SDValue LoLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , LoVT , Load -> getChain ( ) , BasePtr , SrcValue , LoMemVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> isInvariant ( ) , Load -> getAlignment ( ) ) ; SDValue HiPtr = DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( LoMemVT . getStoreSize ( ) , SL , PtrVT ) ) ; SDValue HiLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , HiVT , Load -> getChain ( ) , HiPtr , SrcValue . getWithOffset ( LoMemVT . getStoreSize ( ) ) , HiMemVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> isInvariant ( ) , Load -> getAlignment ( ) ) ; SDValue Ops [ ] = { DAG . getNode ( <STR_LIT> , SL , VT , LoLoad , HiLoad ) , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LoLoad . getValue ( <NUM_LIT> ) , HiLoad . getValue ( <NUM_LIT> ) ) } ; return DAG . getMergeValues ( Ops , SL ) ;


<s> SDLoc SL ( Op ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Val , SL , LoVT , HiVT ) ; EVT PtrVT = BasePtr . getValueType ( ) ; SDValue HiPtr = DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( LoMemVT . getStoreSize ( ) , SL , PtrVT ) ) ; MachinePointerInfo SrcValue ( Store -> getMemOperand ( ) -> getValue ( ) ) ; SDValue LoStore = DAG . getTruncStore ( Chain , SL , Lo , BasePtr , SrcValue , LoMemVT , Store -> isNonTemporal ( ) , Store -> isVolatile ( ) , Store -> getAlignment ( ) ) ;

SDValue HiStore = DAG . getTruncStore ( Chain , SL , Hi , HiPtr , SrcValue . getWithOffset ( LoMemVT . getStoreSize ( ) ) , HiMemVT , Store -> isNonTemporal ( ) , Store -> isVolatile ( ) , Store -> getAlignment ( ) ) ;


<s> return CreateLiveInRegister ( DAG , RC , Reg , VT , SDLoc ( DAG . getEntryNode ( ) ) ) ;


<s> SDValue CreateLiveInRegisterRaw ( SelectionDAG & DAG , const TargetRegisterClass * RC , Register Reg , EVT VT ) const { return CreateLiveInRegister ( DAG , RC , Reg , VT , SDLoc ( DAG . getEntryNode ( ) ) , true ) ;


<s> return DAG . ComputeMinSignedBits ( Op ) ;


<s> case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerFREM ( Op , DAG ) ; case <STR_LIT> : return LowerFCEIL ( Op , DAG ) ; case <STR_LIT> : return LowerFTRUNC ( Op , DAG ) ; case <STR_LIT> : return LowerFRINT ( Op , DAG ) ; case <STR_LIT> : return LowerFNEARBYINT ( Op , DAG ) ; case <STR_LIT> : return LowerFROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFFLOOR ( Op , DAG ) ; case <STR_LIT> : return LowerFLOG ( Op , DAG , numbers :: ln2f ) ; case <STR_LIT> :

return LowerFLOG ( Op , DAG , numbers :: ln2f / numbers :: ln10f ) ;


<s> if ( Opc == <STR_LIT> ) Known . Zero = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> - Width ) ; break ; } case <STR_LIT> : case <STR_LIT> : { unsigned BitWidth = Known . getBitWidth ( ) ; Known . Zero = APInt :: getHighBitsSet ( BitWidth , BitWidth - <NUM_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : { KnownBits LHSKnown , RHSKnown ; DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , LHSKnown , Depth + <NUM_LIT> ) ; DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , RHSKnown , Depth + <NUM_LIT> ) ; unsigned TrailZ = LHSKnown . countMinTrailingZeros ( ) + RHSKnown . countMinTrailingZeros ( ) ; Known . Zero . setLowBits ( std :: min ( TrailZ , <NUM_LIT> ) ) ; unsigned LHSValBits = <NUM_LIT> - std :: max ( LHSKnown . countMinSignBits ( ) , <NUM_LIT> ) ; unsigned RHSValBits = <NUM_LIT> - std :: max ( RHSKnown . countMinSignBits ( ) , <NUM_LIT> ) ;

unsigned MaxValBits = std :: min ( LHSValBits + RHSValBits , <NUM_LIT> ) ;


<s> unsigned BitWidth = Known . getBitWidth ( ) ; Known . Zero = APInt :: getHighBitsSet ( BitWidth , BitWidth - <NUM_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : { KnownBits LHSKnown , RHSKnown ; DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , LHSKnown , Depth + <NUM_LIT> ) ; DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , RHSKnown , Depth + <NUM_LIT> ) ; unsigned TrailZ = LHSKnown . countMinTrailingZeros ( ) + RHSKnown . countMinTrailingZeros ( ) ; Known . Zero . setLowBits ( std :: min ( TrailZ , <NUM_LIT> ) ) ; unsigned LHSValBits = <NUM_LIT> - std :: max ( LHSKnown . countMinSignBits ( ) , <NUM_LIT> ) ; unsigned RHSValBits = <NUM_LIT> - std :: max ( RHSKnown . countMinSignBits ( ) , <NUM_LIT> ) ; unsigned MaxValBits = std :: min ( LHSValBits + RHSValBits , <NUM_LIT> ) ; if ( MaxValBits >= <NUM_LIT> ) break ; bool Negative = false ; if ( Opc == <STR_LIT> ) { bool LHSNegative = ! ! ( LHSKnown . One & ( <NUM_LIT> << <NUM_LIT> ) ) ; bool LHSPositive = ! ! ( LHSKnown . Zero & ( <NUM_LIT> << <NUM_LIT> ) ) ; bool RHSNegative = ! ! ( RHSKnown . One & ( <NUM_LIT> << <NUM_LIT> ) ) ; bool RHSPositive = ! ! ( RHSKnown . Zero & ( <NUM_LIT> << <NUM_LIT> ) ) ; if ( ( ! LHSNegative && ! LHSPositive ) || ( ! RHSNegative && ! RHSPositive ) ) break ; Negative = ( LHSNegative && RHSPositive ) || ( LHSPositive && RHSNegative ) ;


<s> if ( const ExternalSymbolSDNode * G = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) FuncName = G -> getSymbol ( ) ; else if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) FuncName = G -> getGlobal ( ) -> getName ( ) ; DiagnosticInfoUnsupported NoCalls ( Fn , Reason + FuncName , CLI . DL . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( NoCalls ) ; if ( ! CLI . IsTailCall ) { for ( unsigned I = <NUM_LIT> , E = CLI . Ins . size ( ) ; I != E ; ++ I ) InVals . push_back ( DAG . getUNDEF ( CLI . Ins [ I ] . VT ) ) ; }


<s> case <STR_LIT> : case <STR_LIT> : { SDValue X = LHS -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && RHSVal == <NUM_LIT> && X . getValueType ( ) == <STR_LIT> && isTypeLegal ( <STR_LIT> ) ) { SDValue Vec = DAG . getBuildVector ( <STR_LIT> , SL , { DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) , LHS -> getOperand ( <NUM_LIT> ) } ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Vec ) ; } if ( VT != <STR_LIT> ) break ; KnownBits Known ; DAG . computeKnownBits ( X , Known ) ; unsigned LZ = Known . countMinLeadingZeros ( ) ; if ( LZ < RHSVal ) break ; EVT XVT = X . getValueType ( ) ; SDValue Shl = DAG . getNode ( <STR_LIT> , SL , XVT , X , SDValue ( RHS , <NUM_LIT> ) ) ; return DAG . getZExtOrTrunc ( Shl , SL , VT ) ; } case <STR_LIT> : if ( ! isOrEquivalentToAdd ( DAG , LHS ) ) break ; LLVM_FALLTHROUGH ; case <STR_LIT> : { if ( ConstantSDNode * C2 = dyn_cast < ConstantSDNode > ( LHS -> getOperand ( <NUM_LIT> ) ) ) { SDValue Shl = DAG . getNode ( <STR_LIT> , SL , VT , LHS -> getOperand ( <NUM_LIT> ) , SDValue ( RHS , <NUM_LIT> ) ) ;

SDValue C2V = DAG . getConstant ( C2 -> getAPIntValue ( ) << RHSVal , SDLoc ( C2 ) , VT ) ;


<s> SDLoc SL ( N ) ; SelectionDAG & DAG = DCI . DAG ; switch ( LHS -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue X = LHS -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && RHSVal == <NUM_LIT> && X . getValueType ( ) == <STR_LIT> && isTypeLegal ( <STR_LIT> ) ) { SDValue Vec = DAG . getBuildVector ( <STR_LIT> , SL , { DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) , LHS -> getOperand ( <NUM_LIT> ) } ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Vec ) ; } if ( VT != <STR_LIT> ) break ; KnownBits Known ; DAG . computeKnownBits ( X , Known ) ; unsigned LZ = Known . countMinLeadingZeros ( ) ; if ( LZ < RHSVal ) break ; EVT XVT = X . getValueType ( ) ; SDValue Shl = DAG . getNode ( <STR_LIT> , SL , XVT , X , SDValue ( RHS , <NUM_LIT> ) ) ; return DAG . getZExtOrTrunc ( Shl , SL , VT ) ; } case <STR_LIT> :

if ( ! isOrEquivalentToAdd ( DAG , LHS ) ) break ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachinePointerInfo DstInfo = MachinePointerInfo :: getStack ( MF , Offset ) ; SDValue PtrOffset = DAG . getConstant ( Offset , SL , <STR_LIT> ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , StackPtr , PtrOffset ) ; SDValue Store = DAG . getStore ( Chain , SL , ArgVal , Ptr , DstInfo , <NUM_LIT> , MachineMemOperand :: MODereferenceable ) ; return Store ;


<s> case CallingConv :: SPIR_KERNEL : return CC_<ISA_LIT>_Kernel ; case CallingConv :: <ISA_LIT>_VS : case CallingConv :: <ISA_LIT>_GS : case CallingConv :: <ISA_LIT>_PS : case CallingConv :: <ISA_LIT>_CS : return CC_<ISA_LIT> ;


<s> case <STR_LIT> : { assert ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) && <STR_LIT> ) ; ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) break ; uint32_t WidthVal = Width -> getZExtValue ( ) & <NUM_LIT> ; if ( WidthVal == <NUM_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; SDValue BitsFrom = N -> getOperand ( <NUM_LIT> ) ; uint32_t OffsetVal = Offset -> getZExtValue ( ) & <NUM_LIT> ; bool Signed = N -> getOpcode ( ) == <STR_LIT> ; if ( OffsetVal == <NUM_LIT> ) { unsigned SignBits = Signed ? ( <NUM_LIT> - WidthVal + <NUM_LIT> ) : ( <NUM_LIT> - WidthVal ) ; unsigned OpSignBits = DAG . ComputeNumSignBits ( BitsFrom ) ; if ( OpSignBits >= SignBits ) return BitsFrom ; EVT SmallVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , WidthVal ) ; if ( Signed ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BitsFrom , DAG . getValueType ( SmallVT ) ) ; } return DAG . getZeroExtendInReg ( BitsFrom , DL , SmallVT ) ; } if ( ConstantSDNode * CVal = dyn_cast < ConstantSDNode > ( BitsFrom ) ) { if ( Signed ) { return constantFoldBFE < int32_t > ( DAG , CVal -> getSExtValue ( ) , OffsetVal , WidthVal , DL ) ; } return constantFoldBFE < uint32_t > ( DAG , CVal -> getZExtValue ( ) , OffsetVal , WidthVal , DL ) ; } if ( ( OffsetVal + WidthVal ) >= <NUM_LIT> ) { SDValue ShiftVal = DAG . getConstant ( OffsetVal , DL , <STR_LIT> ) ; return DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , BitsFrom , ShiftVal ) ; } if ( BitsFrom . hasOneUse ( ) ) { APInt Demanded = APInt :: getBitsSet ( <NUM_LIT> , OffsetVal , OffsetVal + WidthVal ) ; APInt KnownZero , KnownOne ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . ShrinkDemandedConstant ( BitsFrom , Demanded , TLO ) || TLI . SimplifyDemandedBits ( BitsFrom , Demanded , KnownZero , KnownOne , TLO ) ) { DCI . CommitTargetLoweringOpt ( TLO ) ; } } break ; } case <STR_LIT> : return performLoadCombine ( N , DCI ) ; case <STR_LIT> : return performStoreCombine ( N , DCI ) ;


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : return true ; } } break ; case <STR_LIT> : { const LoadSDNode * L = dyn_cast < LoadSDNode > ( N ) ; if ( L -> getMemOperand ( ) -> getAddrSpace ( ) == Subtarget -> get<ISA_LIT>AS ( ) . CONSTANT_ADDRESS_32BIT ) return true ; return false ; } break ;


<s> switch ( N -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : { unsigned IntrID = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntrID ) { default : return false ; case <STR_LIT> : case <STR_LIT> : return true ;


<s> case <STR_LIT> : case <STR_LIT> : { const RegisterSDNode * R = nullptr ; if ( N -> getOpcode ( ) == <STR_LIT> ) { R = dyn_cast < RegisterSDNode > ( N ) ; } else { R = dyn_cast < RegisterSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; } if ( R ) { const MachineFunction * MF = FLI -> MF ; const <ISA_LIT>Subtarget & ST = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const <ISA_LIT>RegisterInfo & TRI = ST . getInstrInfo ( ) -> getRegisterInfo ( ) ; unsigned Reg = R -> getReg ( ) ; if ( TRI . isPhysicalRegister ( Reg ) ) return TRI . isVGPR ( MRI , Reg ) ; if ( MRI . isLiveIn ( Reg ) ) { if ( ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( TRI . isVGPR ( MRI , Reg ) ) ) return true ; else if ( ! <STR_LIT> ( FLI -> Fn -> getCallingConv ( ) ) ) return true ; } return ! DA || DA -> isDivergent ( FLI -> getValueFromVirtualReg ( Reg ) ) ; } } break ; case <STR_LIT> : { const LoadSDNode * L = dyn_cast < LoadSDNode > ( N ) ; if ( L -> getMemOperand ( ) -> getAddrSpace ( ) == Subtarget -> get<ISA_LIT>AS ( ) . PRIVATE_ADDRESS ) return true ; } break ; case <STR_LIT> : return true ; break ; case <STR_LIT> : { } return <STR_LIT> ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; case <STR_LIT> : return <STR_LIT> ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ;


<s> case <STR_LIT> : { const RegisterSDNode * R = nullptr ; if ( N -> getOpcode ( ) == <STR_LIT> ) { R = dyn_cast < RegisterSDNode > ( N ) ; } else { R = dyn_cast < RegisterSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; } if ( R ) { const MachineFunction * MF = FLI -> MF ; const <ISA_LIT>Subtarget & ST = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const <ISA_LIT>RegisterInfo & TRI = ST . getInstrInfo ( ) -> getRegisterInfo ( ) ; unsigned Reg = R -> getReg ( ) ; if ( TRI . isPhysicalRegister ( Reg ) ) return TRI . isVGPR ( MRI , Reg ) ; if ( MRI . isLiveIn ( Reg ) ) { if ( ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( TRI . isVGPR ( MRI , Reg ) ) ) return true ; else if ( ! <STR_LIT> ( FLI -> Fn -> getCallingConv ( ) ) ) return true ; } return ! DA || DA -> isDivergent ( FLI -> getValueFromVirtualReg ( Reg ) ) ; } } break ; case <STR_LIT> : { const LoadSDNode * L = dyn_cast < LoadSDNode > ( N ) ; if ( L -> getMemOperand ( ) -> getAddrSpace ( ) == Subtarget -> get<ISA_LIT>AS ( ) . PRIVATE_ADDRESS ) return true ; } break ; case <STR_LIT> : return true ; break ; case <STR_LIT> : {


<s> if ( getTargetMachine ( ) . Options . UnsafeFPMath ) return true ;

if ( const auto * BO = dyn_cast < BinaryWithFlagsSDNode > ( Op ) ) return BO -> Flags . hasNoSignedZeros ( ) ;


<s> ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; SDValue BitsFrom = N -> getOperand ( <NUM_LIT> ) ; uint32_t OffsetVal = Offset -> getZExtValue ( ) & <NUM_LIT> ; bool Signed = N -> getOpcode ( ) == <STR_LIT> ; if ( OffsetVal == <NUM_LIT> ) { unsigned SignBits = Signed ? ( <NUM_LIT> - WidthVal + <NUM_LIT> ) : ( <NUM_LIT> - WidthVal ) ; unsigned OpSignBits = DAG . ComputeNumSignBits ( BitsFrom ) ; if ( OpSignBits >= SignBits ) return BitsFrom ; EVT SmallVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , WidthVal ) ; if ( Signed ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BitsFrom , DAG . getValueType ( SmallVT ) ) ; } return DAG . getZeroExtendInReg ( BitsFrom , DL , SmallVT ) ; } if ( ConstantSDNode * CVal = dyn_cast < ConstantSDNode > ( BitsFrom ) ) { if ( Signed ) { return constantFoldBFE < int32_t > ( DAG , CVal -> getSExtValue ( ) , OffsetVal , WidthVal , DL ) ; } return constantFoldBFE < uint32_t > ( DAG , CVal -> getZExtValue ( ) , OffsetVal , WidthVal , DL ) ; } if ( ( OffsetVal + WidthVal ) >= <NUM_LIT> && ! ( Subtarget -> hasSDWA ( ) && OffsetVal == <NUM_LIT> && WidthVal == <NUM_LIT> ) ) { SDValue ShiftVal = DAG . getConstant ( OffsetVal , DL , <STR_LIT> ) ; return DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , BitsFrom , ShiftVal ) ; } if ( BitsFrom . hasOneUse ( ) ) { APInt Demanded = APInt :: getBitsSet ( <NUM_LIT> , OffsetVal , OffsetVal + WidthVal ) ; KnownBits Known ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . ShrinkDemandedConstant ( BitsFrom , Demanded , TLO ) || TLI . SimplifyDemandedBits ( BitsFrom , Demanded , Known , TLO ) ) { DCI . CommitTargetLoweringOpt ( TLO ) ; } } break ; } case <STR_LIT> : return performLoadCombine ( N , DCI ) ; case <STR_LIT> : return performStoreCombine ( N , DCI ) ; case <STR_LIT> : return performClampCombine ( N , DCI ) ; case <STR_LIT> : { if ( const auto * CFP = dyn_cast < ConstantFPSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) { const APFloat & Val = CFP -> getValueAPF ( ) ; APFloat One ( Val . getSemantics ( ) , <STR_LIT> ) ; return DAG . getConstantFP ( One / Val , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; } break ;


<s> if ( Vec . getOpcode ( ) == <STR_LIT> ) { SDValue Elt0 = Vec . getOperand ( <NUM_LIT> ) ; EVT EltVT = Elt0 . getValueType ( ) ; if ( VT . getSizeInBits ( ) <= EltVT . getSizeInBits ( ) ) { if ( EltVT . isFloatingPoint ( ) ) { Elt0 = DAG . getNode ( <STR_LIT> , SL , EltVT . changeTypeToInteger ( ) , Elt0 ) ; } return DAG . getNode ( <STR_LIT> , SL , VT , Elt0 ) ; } } } if ( Src . getOpcode ( ) == <STR_LIT> ) { if ( auto K = isConstOrConstSplat ( Src . getOperand ( <NUM_LIT> ) ) ) { if ( <NUM_LIT> * K -> getZExtValue ( ) == Src . getValueType ( ) . getScalarSizeInBits ( ) ) { SDValue BV = stripBitcast ( Src . getOperand ( <NUM_LIT> ) ) ; if ( BV . getOpcode ( ) == <STR_LIT> && BV . getValueType ( ) . getVectorNumElements ( ) == <NUM_LIT> ) { SDValue SrcElt = BV . getOperand ( <NUM_LIT> ) ; EVT SrcEltVT = SrcElt . getValueType ( ) ; if ( SrcEltVT . isFloatingPoint ( ) ) { SrcElt = DAG . getNode ( <STR_LIT> , SL , SrcEltVT . changeTypeToInteger ( ) , SrcElt ) ; } return DAG . getNode ( <STR_LIT> , SL , VT , SrcElt ) ; } } }


<s> Op . getNode ( ) -> dump ( ) ; llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; break ; case <STR_LIT> : return Lower<ISA_LIT>GN_EXTEND_INREG ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerFrameIndex ( Op , DAG ) ; case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerFREM ( Op , DAG ) ; case <STR_LIT> : return LowerFCEIL ( Op , DAG ) ; case <STR_LIT> : return LowerFTRUNC ( Op , DAG ) ; case <STR_LIT> : return LowerFRINT ( Op , DAG ) ; case <STR_LIT> : return LowerFNEARBYINT ( Op , DAG ) ; case <STR_LIT> : return LowerFROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFFLOOR ( Op , DAG ) ; case <STR_LIT> : return Lower<ISA_LIT>NT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_<ISA_LIT>NT ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTLZ ( Op , DAG ) ;

case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ;


<s> SDValue False = N -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && Cond . hasOneUse ( ) ) return CombineFMinMaxLegacy ( SDLoc ( N ) , VT , LHS , RHS , True , False , CC , DCI ) ; return performCtlzCombine ( SDLoc ( N ) , Cond , True , False , DCI ) ;


<s> SDValue LHS = Cond . getOperand ( <NUM_LIT> ) ; SDValue RHS = Cond . getOperand ( <NUM_LIT> ) ; SDValue CC = Cond . getOperand ( <NUM_LIT> ) ; SDValue True = N -> getOperand ( <NUM_LIT> ) ;

SDValue False = N -> getOperand ( <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return false ;


<s> return performMulLoHi24Combine ( N , DCI ) ; case <STR_LIT> : return performSelectCombine ( N , DCI ) ; case <STR_LIT> : return performFNegCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : { assert ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) && <STR_LIT> ) ; ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) break ; uint32_t WidthVal = Width -> getZExtValue ( ) & <NUM_LIT> ; if ( WidthVal == <NUM_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; SDValue BitsFrom = N -> getOperand ( <NUM_LIT> ) ; uint32_t OffsetVal = Offset -> getZExtValue ( ) & <NUM_LIT> ; bool Signed = N -> getOpcode ( ) == <STR_LIT> ; if ( OffsetVal == <NUM_LIT> ) { unsigned SignBits = Signed ? ( <NUM_LIT> - WidthVal + <NUM_LIT> ) : ( <NUM_LIT> - WidthVal ) ; unsigned OpSignBits = DAG . ComputeNumSignBits ( BitsFrom ) ; if ( OpSignBits >= SignBits ) return BitsFrom ; EVT SmallVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , WidthVal ) ; if ( Signed ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BitsFrom , DAG . getValueType ( SmallVT ) ) ; } return DAG . getZeroExtendInReg ( BitsFrom , DL , SmallVT ) ; } if ( ConstantSDNode * CVal = dyn_cast < ConstantSDNode > ( BitsFrom ) ) { if ( Signed ) { return constantFoldBFE < int32_t > ( DAG , CVal -> getSExtValue ( ) , OffsetVal , WidthVal , DL ) ; } return constantFoldBFE < uint32_t > ( DAG , CVal -> getZExtValue ( ) , OffsetVal , WidthVal , DL ) ; } if ( ( OffsetVal + WidthVal ) >= <NUM_LIT> ) { SDValue ShiftVal = DAG . getConstant ( OffsetVal , DL , <STR_LIT> ) ; return DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , BitsFrom , ShiftVal ) ; } if ( BitsFrom . hasOneUse ( ) ) { APInt Demanded = APInt :: getBitsSet ( <NUM_LIT> , OffsetVal , OffsetVal + WidthVal ) ; APInt KnownZero , KnownOne ;

TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ;


<s> SDValue RHS = N0 . getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) != <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , SL , VT , LHS ) ; else LHS = LHS . getOperand ( <NUM_LIT> ) ; if ( RHS . getOpcode ( ) != <STR_LIT> ) RHS = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; else RHS = RHS . getOperand ( <NUM_LIT> ) ; SDValue Res = DAG . getNode ( <STR_LIT> , SL , VT , LHS , RHS , N0 -> getFlags ( ) ) ; if ( ! N0 . hasOneUse ( ) ) DAG . ReplaceAllUsesWith ( N0 , DAG . getNode ( <STR_LIT> , SL , VT , Res ) ) ; return Res ; } case <STR_LIT> : case <STR_LIT> : { SDValue LHS = N0 . getOperand ( <NUM_LIT> ) ; SDValue RHS = N0 . getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> ) LHS = LHS . getOperand ( <NUM_LIT> ) ; else if ( RHS . getOpcode ( ) == <STR_LIT> ) RHS = RHS . getOperand ( <NUM_LIT> ) ; else RHS = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; SDValue Res = DAG . getNode ( Opc , SL , VT , LHS , RHS , N0 -> getFlags ( ) ) ; if ( ! N0 . hasOneUse ( ) ) DAG . ReplaceAllUsesWith ( N0 , DAG . getNode ( <STR_LIT> , SL , VT , Res ) ) ; return Res ; } case <STR_LIT> : case <STR_LIT> : {

if ( ! mayIgnoreSignedZero ( N0 ) ) return SDValue ( ) ;


<s> if ( SDValue Folded = foldFreeOpFromSelect ( DCI , SDValue ( N , <NUM_LIT> ) ) ) return Folded ; SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; if ( Cond . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue LHS = Cond . getOperand ( <NUM_LIT> ) ; SDValue RHS = Cond . getOperand ( <NUM_LIT> ) ; SDValue CC = Cond . getOperand ( <NUM_LIT> ) ; SDValue True = N -> getOperand ( <NUM_LIT> ) ; SDValue False = N -> getOperand ( <NUM_LIT> ) ; if ( Cond . hasOneUse ( ) ) { SelectionDAG & DAG = DCI . DAG ; if ( ( DAG . isConstantValueOfAnyType ( True ) || DAG . isConstantValueOfAnyType ( True ) ) && ( ! DAG . isConstantValueOfAnyType ( False ) && ! DAG . isConstantValueOfAnyType ( False ) ) ) { SDLoc SL ( N ) ; <STR_LIT> NewCC = getSetCCInverse ( cast < CondCodeSDNode > ( CC ) -> get ( ) , LHS . getValueType ( ) . isInteger ( ) ) ; SDValue NewCond = DAG . getSetCC ( SL , Cond . getValueType ( ) , LHS , RHS , NewCC ) ; return DAG . getNode ( <STR_LIT> , SL , VT , NewCond , False , True ) ; } }

if ( VT == <STR_LIT> && Cond . hasOneUse ( ) ) {


<s> else std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = expandUnalignedLoad ( LN , DAG ) ; return DAG . getMergeValues ( Ops , SDLoc ( N ) ) ; } if ( ! IsFast ) return SDValue ( ) ; } if ( ! shouldCombineMemoryType ( VT ) ) return SDValue ( ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue NewLoad = DAG . getLoad ( NewVT , SL , LN -> getChain ( ) , LN -> getBasePtr ( ) , LN -> getMemOperand ( ) ) ; SDValue BC = DAG . getNode ( <STR_LIT> , SL , VT , NewLoad ) ; DCI . CombineTo ( N , BC , NewLoad . getValue ( <NUM_LIT> ) ) ;


<s> if ( ! SN -> isSimple ( ) || ! <STR_LIT> ( SN ) ) return SDValue ( ) ; EVT VT = SN -> getMemoryVT ( ) ; unsigned Size = VT . getStoreSize ( ) ; SDLoc SL ( N ) ; SelectionDAG & DAG = DCI . DAG ; unsigned Align = SN -> getAlignment ( ) ; if ( Align < Size && isTypeLegal ( VT ) ) { bool IsFast ; unsigned AS = SN -> getAddressSpace ( ) ; if ( ! allowsMisalignedMemoryAccesses ( VT , AS , Align , SN -> getMemOperand ( ) -> getFlags ( ) , & IsFast ) ) { if ( VT . isVector ( ) ) return scalarizeVectorStore ( SN , DAG ) ; return expandUnalignedStore ( SN , DAG ) ; } if ( ! IsFast ) return SDValue ( ) ; }

if ( ! shouldCombineMemoryType ( VT ) ) return SDValue ( ) ;


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) { R = dyn_cast < RegisterSDNode > ( N ) ; } else { R = dyn_cast < RegisterSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; } if ( R ) { const MachineFunction * MF = FLI -> MF ; const <ISA_LIT>Subtarget & ST = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const <ISA_LIT>RegisterInfo & TRI = ST . getInstrInfo ( ) -> getRegisterInfo ( ) ; unsigned Reg = R -> getReg ( ) ; if ( TRI . isPhysicalRegister ( Reg ) ) return TRI . isVGPR ( MRI , Reg ) ; if ( MRI . isLiveIn ( Reg ) ) { if ( ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) ) return true ; else if ( ! <STR_LIT> ( FLI -> Fn -> getCallingConv ( ) ) ) return true ; } return ! DA || DA -> isDivergent ( FLI -> getValueFromVirtualReg ( Reg ) ) ; } } break ; case <STR_LIT> : { const LoadSDNode * L = dyn_cast < LoadSDNode > ( N ) ; if ( L -> getMemOperand ( ) -> getAddrSpace ( ) == Subtarget -> get<ISA_LIT>AS ( ) . PRIVATE_ADDRESS ) return true ; } break ;


<s> if ( MRI . isLiveIn ( Reg ) ) { if ( ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) ) return true ; else if ( ! <STR_LIT> ( FLI -> Fn -> getCallingConv ( ) ) ) return true ; } return ! DA || DA -> isDivergent ( FLI -> getValueFromVirtualReg ( Reg ) ) ; } } break ; case <STR_LIT> : {

const LoadSDNode * L = dyn_cast < LoadSDNode > ( N ) ;


<s> if ( DestVT == <STR_LIT> && ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) ) { SDLoc DL ( Op ) ; SDValue FpToInt32 = DAG . getNode ( OpOpcode , DL , <STR_LIT> , Src ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FpToInt32 ) ; } if ( SrcVT == <STR_LIT> || ( SrcVT == <STR_LIT> && Src . getOpcode ( ) == <STR_LIT> ) ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerINTRIN<ISA_LIT>C_WO_CHAIN ( SDValue Op , SelectionDAG & DAG ) const { unsigned IntrinsicID = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; switch ( IntrinsicID ) { default : return Op ; case <STR_LIT> :

return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> default : return Op ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> SDValue NEG_RCP_LO = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , RCP_LO ) ; const SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; const EVT CCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue CmpRcpHiZero = DAG . getSetCC ( DL , CCVT , RCP_HI , Zero , <STR_LIT> ) ; SDValue ABS_RCP_LO = DAG . getNode ( <STR_LIT> , DL , VT , CmpRcpHiZero , NEG_RCP_LO , RCP_LO ) ; SDValue E = DAG . getNode ( <STR_LIT> , DL , VT , ABS_RCP_LO , RCP ) ; SDValue RCP_A_E = DAG . getNode ( <STR_LIT> , DL , VT , RCP , E ) ; SDValue RCP_S_E = DAG . getNode ( <STR_LIT> , DL , VT , RCP , E ) ; SDValue Tmp0 = DAG . getNode ( <STR_LIT> , DL , VT , CmpRcpHiZero , RCP_A_E , RCP_S_E ) ; SDValue Quotient = DAG . getNode ( <STR_LIT> , DL , VT , Tmp0 , Num ) ; SDValue Num_S_Remainder = DAG . getNode ( <STR_LIT> , DL , VT , Quotient , Den ) ; SDValue Remainder = DAG . getNode ( <STR_LIT> , DL , VT , Num , Num_S_Remainder ) ; SDValue Remainder_GE_Den = DAG . getSetCC ( DL , CCVT , Remainder , Den , <STR_LIT> ) ; SDValue Remainder_GE_Zero = DAG . getSetCC ( DL , CCVT , Num , Num_S_Remainder , <STR_LIT> ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , DL , CCVT , Remainder_GE_Den , Remainder_GE_Zero ) ; SDValue Quotient_A_One = DAG . getNode ( <STR_LIT> , DL , VT , Quotient , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Quotient_S_One = DAG . getNode ( <STR_LIT> , DL , VT , Quotient , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ;

SDValue Div = DAG . getNode ( <STR_LIT> , DL , VT , Tmp1 , Quotient_A_One , Quotient ) ;


<s> SDValue Tmp0 = DAG . getNode ( <STR_LIT> , DL , VT , CmpRcpHiZero , RCP_A_E , RCP_S_E ) ; SDValue Quotient = DAG . getNode ( <STR_LIT> , DL , VT , Tmp0 , Num ) ; SDValue Num_S_Remainder = DAG . getNode ( <STR_LIT> , DL , VT , Quotient , Den ) ; SDValue Remainder = DAG . getNode ( <STR_LIT> , DL , VT , Num , Num_S_Remainder ) ; SDValue Remainder_GE_Den = DAG . getSetCC ( DL , CCVT , Remainder , Den , <STR_LIT> ) ; SDValue Remainder_GE_Zero = DAG . getSetCC ( DL , CCVT , Num , Num_S_Remainder , <STR_LIT> ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , DL , CCVT , Remainder_GE_Den , Remainder_GE_Zero ) ; SDValue Quotient_A_One = DAG . getNode ( <STR_LIT> , DL , VT , Quotient , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Quotient_S_One = DAG . getNode ( <STR_LIT> , DL , VT , Quotient , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Div = DAG . getNode ( <STR_LIT> , DL , VT , Tmp1 , Quotient_A_One , Quotient ) ; Div = DAG . getNode ( <STR_LIT> , DL , VT , Remainder_GE_Zero , Div , Quotient_S_One ) ; SDValue Remainder_S_Den = DAG . getNode ( <STR_LIT> , DL , VT , Remainder , Den ) ; SDValue Remainder_A_Den = DAG . getNode ( <STR_LIT> , DL , VT , Remainder , Den ) ; SDValue Rem = DAG . getNode ( <STR_LIT> , DL , VT , Tmp1 , Remainder_S_Den , Remainder ) ; Rem = DAG . getNode ( <STR_LIT> , DL , VT , Remainder_GE_Zero , Rem , Remainder_A_Den ) ; SDValue Ops [ <NUM_LIT> ] = { Div , Rem } ; return DAG . getMergeValues ( Ops , DL ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return false ; }


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue LHS = N0 . getOperand ( <NUM_LIT> ) ; SDValue RHS = N0 . getOperand ( <NUM_LIT> ) ; if ( isConstantFPZero ( RHS ) ) return SDValue ( ) ; SDValue NegLHS = DAG . getNode ( <STR_LIT> , SL , VT , LHS ) ; SDValue NegRHS = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; unsigned Opposite = inverseMinMax ( Opc ) ; SDValue Res = DAG . getNode ( Opposite , SL , VT , NegLHS , NegRHS , N0 -> getFlags ( ) ) ; if ( ! N0 . hasOneUse ( ) ) DAG . ReplaceAllUsesWith ( N0 , DAG . getNode ( <STR_LIT> , SL , VT , Res ) ) ; return Res ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue CvtSrc = N0 . getOperand ( <NUM_LIT> ) ; if ( CvtSrc . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( Opc , SL , VT , CvtSrc . getOperand ( <NUM_LIT> ) ) ; } if ( ! N0 . hasOneUse ( ) ) return SDValue ( ) ; SDValue Neg = DAG . getNode ( <STR_LIT> , SL , CvtSrc . getValueType ( ) , CvtSrc ) ; return DAG . getNode ( Opc , SL , VT , Neg , N0 -> getFlags ( ) ) ; } case <STR_LIT> : { SDValue CvtSrc = N0 . getOperand ( <NUM_LIT> ) ; if ( CvtSrc . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , SL , VT , CvtSrc . getOperand ( <NUM_LIT> ) , N0 . getOperand ( <NUM_LIT> ) ) ; } if ( ! N0 . hasOneUse ( ) ) return SDValue ( ) ; SDValue Neg = DAG . getNode ( <STR_LIT> , SL , CvtSrc . getValueType ( ) , CvtSrc ) ; return DAG . getNode ( <STR_LIT> , SL , VT , Neg , N0 . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : { SDLoc SL ( N ) ;

SDValue Src = N0 . getOperand ( <NUM_LIT> ) ;


<s> MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; Type * EltType = GV -> getValueType ( ) ; unsigned Size = DL . getTypeAllocSize ( EltType ) ; unsigned Alignment = DL . getPrefTypeAlignment ( EltType ) ; MVT PrivPtrVT = getPointerTy ( DL , <ISA_LIT>AS :: PRIVATE_ADDRESS ) ; MVT ConstPtrVT = getPointerTy ( DL , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; int FI = FrameInfo -> CreateStackObject ( Size , Alignment , false ) ; SDValue InitPtr = DAG . getFrameIndex ( FI , PrivPtrVT ) ; const GlobalVariable * Var = cast < GlobalVariable > ( GV ) ; if ( ! Var -> hasInitializer ( ) ) { return DAG . getZExtOrTrunc ( InitPtr , SDLoc ( Op ) , ConstPtrVT ) ; } const Constant * Init = Var -> getInitializer ( ) ; SmallVector < SDNode * , <NUM_LIT> > WorkList ; for ( SDNode :: use_iterator I = DAG . getEntryNode ( ) -> use_begin ( ) , E = DAG . getEntryNode ( ) -> use_end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) continue ; WorkList . push_back ( * I ) ; } SDValue Chain = LowerConstantInitializer ( Init , GV , InitPtr , DAG . getEntryNode ( ) , DAG ) ; for ( SmallVector < SDNode * , <NUM_LIT> > :: iterator I = WorkList . begin ( ) , E = WorkList . end ( ) ; I != E ; ++ I ) { SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; for ( unsigned i = <NUM_LIT> ; i < ( * I ) -> getNumOperands ( ) ; ++ i ) { Ops . push_back ( ( * I ) -> getOperand ( i ) ) ; } DAG . UpdateNodeOperands ( * I , Ops ) ; }


<s> case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> :


<s> return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : { unsigned Opc = ( LHS == True ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , DL , VT , LHS , RHS ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned Opc = ( LHS == True ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , DL , VT , LHS , RHS ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned Opc = ( LHS == True ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , DL , VT , LHS , RHS ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned Opc = ( LHS == True ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , DL , VT , LHS , RHS ) ; } default :


<s> SDValue <ISA_LIT>TargetLowering :: LowerFrameIndex ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>FrameLowering * TFL = Subtarget -> getFrameLowering ( ) ; FrameIndexSDNode * FIN = cast < FrameIndexSDNode > ( Op ) ; unsigned FrameIndex = FIN -> getIndex ( ) ;

unsigned Offset = TFL -> getFrameIndexOffset ( MF , FrameIndex ) ;


<s> uint32_t WidthVal = Width -> getZExtValue ( ) & <NUM_LIT> ; if ( WidthVal == <NUM_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; SDValue BitsFrom = N -> getOperand ( <NUM_LIT> ) ; uint32_t OffsetVal = Offset -> getZExtValue ( ) & <NUM_LIT> ; bool Signed = N -> getOpcode ( ) == <STR_LIT> ; if ( OffsetVal == <NUM_LIT> ) { unsigned SignBits = Signed ? ( <NUM_LIT> - WidthVal + <NUM_LIT> ) : ( <NUM_LIT> - WidthVal ) ; unsigned OpSignBits = DAG . ComputeNumSignBits ( BitsFrom ) ; if ( OpSignBits >= SignBits ) return BitsFrom ; EVT SmallVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , WidthVal ) ; if ( Signed ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BitsFrom , DAG . getValueType ( SmallVT ) ) ; } return DAG . getZeroExtendInReg ( BitsFrom , DL , SmallVT ) ; } if ( ConstantSDNode * CVal = dyn_cast < ConstantSDNode > ( BitsFrom ) ) { if ( Signed ) { return constantFoldBFE < int32_t > ( DAG , CVal -> getSExtValue ( ) , OffsetVal , WidthVal , DL ) ; } return constantFoldBFE < uint32_t > ( DAG , CVal -> getZExtValue ( ) , OffsetVal , WidthVal , DL ) ; } if ( ( OffsetVal + WidthVal ) >= <NUM_LIT> ) { SDValue ShiftVal = DAG . getConstant ( OffsetVal , DL , <STR_LIT> ) ; return DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , BitsFrom , ShiftVal ) ; } if ( BitsFrom . hasOneUse ( ) ) { APInt Demanded = APInt :: getBitsSet ( <NUM_LIT> , OffsetVal , OffsetVal + WidthVal ) ; APInt KnownZero , KnownOne ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLO . ShrinkDemandedConstant ( BitsFrom , Demanded ) || TLI . SimplifyDemandedBits ( BitsFrom , Demanded , KnownZero , KnownOne , TLO ) ) { DCI . CommitTargetLoweringOpt ( TLO ) ; }


<s> if ( getTargetMachine ( ) . Options . NoSignedZerosFPMath ) return true ; const auto Flags = Op . getNode ( ) -> getFlags ( ) ; if ( Flags . hasNoSignedZeros ( ) ) return true ; return false ;


<s> if ( RegisterVT . isInteger ( ) ) { MemVT = EVT :: getIntegerVT ( State . getContext ( ) , MemoryBits ) ; } else if ( RegisterVT . isVector ( ) ) { assert ( ! RegisterVT . getScalarType ( ) . isFloatingPoint ( ) ) ; unsigned NumElements = RegisterVT . getVectorNumElements ( ) ; assert ( MemoryBits % NumElements == <NUM_LIT> ) ; EVT ScalarVT = EVT :: getIntegerVT ( State . getContext ( ) , MemoryBits / NumElements ) ; MemVT = EVT :: getVectorVT ( State . getContext ( ) , ScalarVT , NumElements ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } } if ( MemVT . isVector ( ) && MemVT . getVectorNumElements ( ) == <NUM_LIT> ) MemVT = MemVT . getScalarType ( ) ; if ( MemVT . isExtended ( ) ) { assert ( MemVT . isVector ( ) && MemVT . getVectorNumElements ( ) == <NUM_LIT> ) ; MemVT = MemVT . getPow2VectorType ( State . getContext ( ) ) ; } unsigned PartOffset = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumRegs ; ++ i ) {

State . addLoc ( CCValAssign :: getCustomMem ( InIndex ++ , RegisterVT , BasePartOffset + PartOffset , MemVT . getSimpleVT ( ) , CCValAssign :: Full ) ) ;


<s> ExplicitArgOffset = alignTo ( ExplicitArgOffset , Align ) + AllocSize ; SmallVector < EVT , <NUM_LIT> > ValueVTs ; SmallVector < uint64_t , <NUM_LIT> > Offsets ; ComputeValueVTs ( * this , DL , BaseArgTy , ValueVTs , & Offsets , ArgOffset ) ; for ( unsigned Value = <NUM_LIT> , NumValues = ValueVTs . size ( ) ; Value != NumValues ; ++ Value ) { uint64_t BasePartOffset = Offsets [ Value ] ; EVT ArgVT = ValueVTs [ Value ] ; EVT MemVT = ArgVT ; MVT RegisterVT = getRegisterTypeForCallingConv ( Ctx , ArgVT ) ; unsigned NumRegs = getNumRegistersForCallingConv ( Ctx , ArgVT ) ; if ( ! Subtarget -> isAmdHsaOS ( ) && ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) ) { MemVT = ArgVT . isInteger ( ) ? <STR_LIT> : <STR_LIT> ; } else if ( NumRegs == <NUM_LIT> ) { if ( ArgVT . isExtended ( ) ) { MemVT = RegisterVT ; } else { MemVT = ArgVT ; } } else if ( ArgVT . isVector ( ) && RegisterVT . isVector ( ) && ArgVT . getScalarType ( ) == RegisterVT . getScalarType ( ) ) { assert ( ArgVT . getVectorNumElements ( ) > RegisterVT . getVectorNumElements ( ) ) ; MemVT = RegisterVT ; } else if ( ArgVT . isVector ( ) && ArgVT . getVectorNumElements ( ) == NumRegs ) { MemVT = ArgVT . getScalarType ( ) ; } else if ( ArgVT . isExtended ( ) ) { MemVT = RegisterVT ; } else { unsigned MemoryBits = ArgVT . getStoreSizeInBits ( ) / NumRegs ; assert ( ArgVT . getStoreSizeInBits ( ) % NumRegs == <NUM_LIT> ) ; if ( RegisterVT . isInteger ( ) ) { MemVT = EVT :: getIntegerVT ( State . getContext ( ) , MemoryBits ) ; } else if ( RegisterVT . isVector ( ) ) { assert ( ! RegisterVT . getScalarType ( ) . isFloatingPoint ( ) ) ; unsigned NumElements = RegisterVT . getVectorNumElements ( ) ; assert ( MemoryBits % NumElements == <NUM_LIT> ) ;

EVT ScalarVT = EVT :: getIntegerVT ( State . getContext ( ) , MemoryBits / NumElements ) ;


<s> const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned ExplicitArgOffset = ST . getExplicitKernelArgOffset ( MF . getFunction ( ) ) ; unsigned Alignment = ST . getAlignmentForImplicitArgPtr ( ) ;

uint64_t ArgOffset = alignTo ( MFI -> getExplicitKernArgSize ( ) , Alignment ) + ExplicitArgOffset ;


<s> uint32_t <ISA_LIT>TargetLowering :: getImplicitParameterOffset ( const MachineFunction & MF , const ImplicitParameter Param ) const { const <ISA_LIT>MachineFunction * MFI = MF . getInfo < <ISA_LIT>MachineFunction > ( ) ; const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

unsigned ExplicitArgOffset = ST . getExplicitKernelArgOffset ( MF . getFunction ( ) ) ;


<s> if ( In . VT . isInteger ( ) ) { MemVT = EVT :: getIntegerVT ( State . getContext ( ) , MemoryBits ) ; } else if ( In . VT . isVector ( ) ) { assert ( ! In . VT . getScalarType ( ) . isFloatingPoint ( ) ) ; unsigned NumElements = In . VT . getVectorNumElements ( ) ; assert ( MemoryBits % NumElements == <NUM_LIT> ) ; EVT ScalarVT = EVT :: getIntegerVT ( State . getContext ( ) , MemoryBits / NumElements ) ; MemVT = EVT :: getVectorVT ( State . getContext ( ) , ScalarVT , NumElements ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } } if ( MemVT . isVector ( ) && MemVT . getVectorNumElements ( ) == <NUM_LIT> ) MemVT = MemVT . getScalarType ( ) ; if ( MemVT . isExtended ( ) ) { assert ( MemVT . isVector ( ) && MemVT . getVectorNumElements ( ) == <NUM_LIT> ) ;

MemVT = MemVT . getPow2VectorType ( State . getContext ( ) ) ;


<s> case <STR_LIT> : return LowerFCEIL ( Op , DAG ) ; case <STR_LIT> : return LowerFTRUNC ( Op , DAG ) ; case <STR_LIT> : return LowerFRINT ( Op , DAG ) ; case <STR_LIT> : return LowerFNEARBYINT ( Op , DAG ) ; case <STR_LIT> : return LowerFROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFFLOOR ( Op , DAG ) ; case <STR_LIT> : return Lower<ISA_LIT>NT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_FP16 ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_<ISA_LIT>NT ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerCTLZ_CTTZ ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; } return Op ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> case <STR_LIT> : return LowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerFREM ( Op , DAG ) ; case <STR_LIT> : return LowerFCEIL ( Op , DAG ) ; case <STR_LIT> : return LowerFTRUNC ( Op , DAG ) ; case <STR_LIT> : return LowerFRINT ( Op , DAG ) ; case <STR_LIT> : return LowerFNEARBYINT ( Op , DAG ) ; case <STR_LIT> : return LowerFROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFFLOOR ( Op , DAG ) ; case <STR_LIT> : return Lower<ISA_LIT>NT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_FP16 ( Op , DAG ) ;

case <STR_LIT> : return LowerFP_TO_<ISA_LIT>NT ( Op , DAG ) ;


<s> Op -> dump ( & DAG ) ; llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; break ; case <STR_LIT> : return Lower<ISA_LIT>GN_EXTEND_INREG ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerFREM ( Op , DAG ) ; case <STR_LIT> : return LowerFCEIL ( Op , DAG ) ; case <STR_LIT> : return LowerFTRUNC ( Op , DAG ) ; case <STR_LIT> : return LowerFRINT ( Op , DAG ) ; case <STR_LIT> : return LowerFNEARBYINT ( Op , DAG ) ; case <STR_LIT> : return LowerFROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFFLOOR ( Op , DAG ) ; case <STR_LIT> : return Lower<ISA_LIT>NT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ;

case <STR_LIT> : return LowerFP_TO_FP16 ( Op , DAG ) ;


<s> static bool allocateCCRegs ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State , const TargetRegisterClass * RC , unsigned NumRegs ) { ArrayRef < MCPhysReg > RegList = makeArrayRef ( RC -> begin ( ) , NumRegs ) ; unsigned RegResult = State . AllocateReg ( RegList ) ; if ( RegResult == <STR_LIT> ) return false ; State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , RegResult , LocVT , LocInfo ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { return allocateCCRegs ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State , & <STR_LIT> , <NUM_LIT> ) ; } default :


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : {

return allocateCCRegs ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State , & <STR_LIT> , <NUM_LIT> ) ;


<s> for ( const Argument & Arg : Fn . args ( ) ) { Type * BaseArgTy = Arg . getType ( ) ; unsigned Align = DL . getABITypeAlignment ( BaseArgTy ) ; MaxAlign = std :: max ( Align , MaxAlign ) ; unsigned AllocSize = DL . getTypeAllocSize ( BaseArgTy ) ; uint64_t ArgOffset = alignTo ( ExplicitArgOffset , Align ) + ExplicitOffset ; ExplicitArgOffset = alignTo ( ExplicitArgOffset , Align ) + AllocSize ; SmallVector < EVT , <NUM_LIT> > ValueVTs ; SmallVector < uint64_t , <NUM_LIT> > Offsets ; ComputeValueVTs ( * this , DL , BaseArgTy , ValueVTs , & Offsets , ArgOffset ) ; for ( unsigned Value = <NUM_LIT> , NumValues = ValueVTs . size ( ) ; Value != NumValues ; ++ Value ) { uint64_t BasePartOffset = Offsets [ Value ] ; EVT ArgVT = ValueVTs [ Value ] ; EVT MemVT = ArgVT ; MVT RegisterVT = getRegisterTypeForCallingConv ( Ctx , CC , ArgVT ) ; unsigned NumRegs = getNumRegistersForCallingConv ( Ctx , CC , ArgVT ) ; if ( NumRegs == <NUM_LIT> ) { if ( ArgVT . isExtended ( ) ) { MemVT = RegisterVT ; } else { MemVT = ArgVT ; } } else if ( ArgVT . isVector ( ) && RegisterVT . isVector ( ) && ArgVT . getScalarType ( ) == RegisterVT . getScalarType ( ) ) { assert ( ArgVT . getVectorNumElements ( ) > RegisterVT . getVectorNumElements ( ) ) ; MemVT = RegisterVT ; } else if ( ArgVT . isVector ( ) && ArgVT . getVectorNumElements ( ) == NumRegs ) { MemVT = ArgVT . getScalarType ( ) ; } else if ( ArgVT . isExtended ( ) ) { MemVT = RegisterVT ; } else { unsigned MemoryBits = ArgVT . getStoreSizeInBits ( ) / NumRegs ; assert ( ArgVT . getStoreSizeInBits ( ) % NumRegs == <NUM_LIT> ) ; if ( RegisterVT . isInteger ( ) ) { MemVT = EVT :: getIntegerVT ( State . getContext ( ) , MemoryBits ) ;

} else if ( RegisterVT . isVector ( ) ) {


<s> case CallingConv :: <ISA_LIT>_GS : case CallingConv :: <ISA_LIT>_PS : case CallingConv :: <ISA_LIT>_CS : case CallingConv :: <ISA_LIT>_HS : case CallingConv :: <ISA_LIT>_ES : case CallingConv :: <ISA_LIT>_LS : return CC_<ISA_LIT> ; case CallingConv :: C : case CallingConv :: Fast : case CallingConv :: Cold : return CC_<ISA_LIT>_Func ; default :


<s> bool LHSPositive = ! ! ( LHSKnown . Zero & ( <NUM_LIT> << <NUM_LIT> ) ) ; bool RHSNegative = ! ! ( RHSKnown . One & ( <NUM_LIT> << <NUM_LIT> ) ) ; bool RHSPositive = ! ! ( RHSKnown . Zero & ( <NUM_LIT> << <NUM_LIT> ) ) ; if ( ( ! LHSNegative && ! LHSPositive ) || ( ! RHSNegative && ! RHSPositive ) ) break ; Negative = ( LHSNegative && RHSPositive ) || ( LHSPositive && RHSNegative ) ; } if ( Negative ) Known . One . setHighBits ( <NUM_LIT> - MaxValBits ) ; else Known . Zero . setHighBits ( <NUM_LIT> - MaxValBits ) ; break ; } case <STR_LIT> : { ConstantSDNode * CMask = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! CMask ) return ; KnownBits LHSKnown , RHSKnown ; DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , LHSKnown , Depth + <NUM_LIT> ) ; DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , RHSKnown , Depth + <NUM_LIT> ) ; unsigned Sel = CMask -> getZExtValue ( ) ; for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; I += <NUM_LIT> ) { unsigned SelBits = Sel & <NUM_LIT> ; if ( SelBits < <NUM_LIT> ) { SelBits *= <NUM_LIT> ; Known . One |= ( ( RHSKnown . One . getZExtValue ( ) >> SelBits ) & <NUM_LIT> ) << I ; Known . Zero |= ( ( RHSKnown . Zero . getZExtValue ( ) >> SelBits ) & <NUM_LIT> ) << I ; } else if ( SelBits < <NUM_LIT> ) { SelBits = ( SelBits & <NUM_LIT> ) * <NUM_LIT> ; Known . One |= ( ( LHSKnown . One . getZExtValue ( ) >> SelBits ) & <NUM_LIT> ) << I ; Known . Zero |= ( ( LHSKnown . Zero . getZExtValue ( ) >> SelBits ) & <NUM_LIT> ) << I ; } else if ( SelBits == <NUM_LIT> ) { Known . Zero |= <NUM_LIT> << I ;


<s> switch ( Op . getOpcode ( ) ) { case <STR_LIT> : { ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) return <NUM_LIT> ; unsigned SignBits = <NUM_LIT> - Width -> getZExtValue ( ) + <NUM_LIT> ; if ( ! isNullConstant ( Op . getOperand ( <NUM_LIT> ) ) ) return SignBits ; unsigned Op0SignBits = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; return std :: max ( SignBits , Op0SignBits ) ; } case <STR_LIT> : {


<s> SDValue CreateLiveInRegister ( SelectionDAG & DAG , const TargetRegisterClass * RC , unsigned Reg , EVT VT ) const {

return CreateLiveInRegister ( DAG , RC , Reg , VT , SDLoc ( DAG . getEntryNode ( ) ) ) ;


<s> return CreateLiveInRegister ( DAG , RC , Reg , VT , SDLoc ( DAG . getEntryNode ( ) ) , true ) ;


<s> LLVM_READNONE static bool fnegFoldsIntoOp ( unsigned Opc ) { switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> MVT getFenceOperandTy ( const DataLayout & DL ) const override { return <STR_LIT> ;


<s> MVT getFenceOperandTy ( const DataLayout & DL ) const override {


<s> if ( ! GVar || ! GVar -> hasInitializer ( ) ) return false ;

return ! isa < UndefValue > ( GVar -> getInitializer ( ) ) ;


<s> switch ( N -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; default : return true ;


<s> switch ( Opc ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> static bool isConstantFPZero ( SDValue N ) {

if ( const ConstantFPSDNode * C = isConstOrConstSplatFP ( N ) ) return C -> isZero ( ) && ! C -> isNegative ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return false ; } case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) && DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) && DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) && DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return false ; } case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SNaN ; case <STR_LIT> : case <STR_LIT> : { return SNaN ; } case <STR_LIT> : { unsigned IntrinsicID = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntrinsicID ) { case <STR_LIT> :


<s> assert ( LoadTy . getSizeInBits ( ) == CastTy . getSizeInBits ( ) ) ; if ( LoadTy . getScalarType ( ) == <STR_LIT> ) return false ; unsigned LScalarSize = LoadTy . getScalarSizeInBits ( ) ; unsigned CastScalarSize = CastTy . getScalarSizeInBits ( ) ;

return ( LScalarSize < CastScalarSize ) || ( CastScalarSize >= <NUM_LIT> ) ;


<s> return true ; case <STR_LIT> : { unsigned IntrID = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntrID ) { default : return false ; case <STR_LIT> : case <STR_LIT> : return true ; } } break ; case <STR_LIT> : { const LoadSDNode * L = dyn_cast < LoadSDNode > ( N ) ;

if ( L -> getMemOperand ( ) -> getAddrSpace ( ) == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS_32BIT ) return true ;