<s> case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; } MachineInstr * Flat = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; bool Ret = constrainSelectedInstRegOperands ( * Flat , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return Ret ;


<s> } MachineInstr * Flat = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; bool Ret = constrainSelectedInstRegOperands ( * Flat , TII , TRI , RBI ) ; I . eraseFromParent ( ) ;


<s> const unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const unsigned DstSize = DstTy . getSizeInBits ( ) ; if ( ! DstTy . isScalar ( ) ) return false ; const RegisterBank * SrcBank = RBI . getRegBank ( SrcReg , MRI , TRI ) ; if ( SrcBank -> getID ( ) == <STR_LIT> ) { if ( SrcTy != S1 || DstSize > <NUM_LIT> ) return false ; unsigned Opcode = DstSize > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * DstRC = DstSize > <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , TmpReg ) . addReg ( SrcReg ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( TmpReg ) ; BuildMI ( MBB , I , DL , TII . get ( Opcode ) , DstReg ) . addImm ( <NUM_LIT> ) . addImm ( Signed ? - <NUM_LIT> : <NUM_LIT> ) ; return RBI . constrainGenericRegister ( DstReg , * DstRC , MRI ) ; } if ( SrcBank -> getID ( ) == <STR_LIT> && DstSize <= <NUM_LIT> ) { if ( SrcTy != S1 ) return false ; MachineInstr * ExtI = BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( Signed ? - <NUM_LIT> : <NUM_LIT> ) . addUse ( SrcReg ) ; return constrainSelectedInstRegOperands ( * ExtI , TII , TRI , RBI ) ; } if ( I . getOpcode ( ) == <STR_LIT> ) return selectCOPY ( I ) ; if ( SrcBank -> getID ( ) == <STR_LIT> && DstSize <= <NUM_LIT> ) { const unsigned BFE = Signed ? <STR_LIT> : <STR_LIT> ;

MachineInstr * ExtI = BuildMI ( MBB , I , DL , TII . get ( BFE ) , DstReg ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) . addImm ( SrcSize ) ;


<s> bool <ISA_LIT>InstructionSelector :: selectG_TRUNC ( MachineInstr & I ) const { MachineBasicBlock * BB = I . getParent ( ) ; MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType ( DstReg ) ; const LLT SrcTy = MRI . getType ( SrcReg ) ; if ( ! DstTy . isScalar ( ) ) return false ; const RegisterBank * DstRB = RBI . getRegBank ( DstReg , MRI , TRI ) ;

const RegisterBank * SrcRB = RBI . getRegBank ( SrcReg , MRI , TRI ) ;


<s> MachineInstr * MI = Root . getParent ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; SmallVector < GEPInfo , <NUM_LIT> > AddrInfo ; getAddrModeInfo ( * MI , MRI , AddrInfo ) ; if ( AddrInfo . empty ( ) || AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) != <NUM_LIT> ) return None ; const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; if ( ! GEPInfo . Imm || ! isUInt < <NUM_LIT> > ( GEPInfo . Imm ) ) return None ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; unsigned OffsetReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , OffsetReg ) . addImm ( GEPInfo . Imm ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) {


<s> MachineInstr * MI = Root . getParent ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; SmallVector < GEPInfo , <NUM_LIT> > AddrInfo ; getAddrModeInfo ( * MI , MRI , AddrInfo ) ; if ( AddrInfo . empty ( ) || AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) != <NUM_LIT> ) return None ;

const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ;


<s> Optional < ValueAndVReg > MaybeOffset = getConstantVRegValWithLookThrough ( RHS . getReg ( ) , MRI , true ) ; if ( ! MaybeOffset ) return { Root , <NUM_LIT> } ; return { RootI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MaybeOffset -> Value } ;


<s> if ( ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS || AS == <ISA_LIT>AS :: REGION_ADDRESS ) && STI . ldsRequiresM0Init ( ) ) { MachineBasicBlock * BB = I . getParent ( ) ;

BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( - <NUM_LIT> ) ;


<s> const LLT PtrTy = MRI -> getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned AS = PtrTy . getAddressSpace ( ) ; if ( ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS || AS == <ISA_LIT>AS :: REGION_ADDRESS ) && STI . ldsRequiresM0Init ( ) ) { MachineBasicBlock * BB = I . getParent ( ) ; BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; }


<s> if ( ! isUInt < <NUM_LIT> > ( Offset0 / Size ) || ! isUInt < <NUM_LIT> > ( Offset1 / Size ) ) return false ; if ( STI . hasUsableDSOffset ( ) || STI . unsafeDSOffsetFoldingEnabled ( ) ) return true ;

return KnownBits -> signBitIsZero ( Base ) ;


<s> if ( ! isUInt < <NUM_LIT> > ( Offset ) ) return false ; if ( STI . hasUsableDSOffset ( ) || STI . unsafeDSOffsetFoldingEnabled ( ) ) return true ;


<s> const TargetRegisterClass * RC = RegClassOrBank . dyn_cast < const TargetRegisterClass * > ( ) ; if ( RC ) { const LLT Ty = MRI . getType ( Reg ) ; return RC -> hasSuperClassEq ( TRI . getBoolRC ( ) ) && Ty . isValid ( ) && Ty . getSizeInBits ( ) == <NUM_LIT> ; } const RegisterBank * RB = RegClassOrBank . get < const RegisterBank * > ( ) ; return RB -> getID ( ) == <STR_LIT> ;


<s> bool <ISA_LIT>InstructionSelector :: isVCC ( Register Reg , const MachineRegisterInfo & MRI ) const { if ( Reg . isPhysical ( ) ) return false ; auto & RegClassOrBank = MRI . getRegClassOrRegBank ( Reg ) ; const TargetRegisterClass * RC = RegClassOrBank . dyn_cast < const TargetRegisterClass * > ( ) ; if ( RC ) { const LLT Ty = MRI . getType ( Reg ) ; return RC -> hasSuperClassEq ( TRI . getBoolRC ( ) ) && Ty . isValid ( ) && Ty . getSizeInBits ( ) == <NUM_LIT> ; } const RegisterBank * RB = RegClassOrBank . get < const RegisterBank * > ( ) ;


<s> static Register matchZeroExtendFromS32 ( MachineRegisterInfo & MRI , Register Reg ) { Register ZExtSrc ; if ( mi_match ( Reg , MRI , m_GZExt ( m_Reg ( ZExtSrc ) ) ) ) return MRI . getType ( ZExtSrc ) == LLT :: scalar ( <NUM_LIT> ) ? ZExtSrc : Register ( ) ; const MachineInstr * Def = getDefIgnoringCopies ( Reg , MRI ) ; if ( Def -> getOpcode ( ) != <STR_LIT> ) return false ; int64_t MergeRHS ;

if ( mi_match ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_ICst ( MergeRHS ) ) && MergeRHS == <NUM_LIT> ) {


<s> if ( mi_match ( Reg , MRI , m_GZExt ( m_Reg ( ZExtSrc ) ) ) ) return MRI . getType ( ZExtSrc ) == LLT :: scalar ( <NUM_LIT> ) ? ZExtSrc : Register ( ) ; const MachineInstr * Def = getDefIgnoringCopies ( Reg , MRI ) ; if ( Def -> getOpcode ( ) != <STR_LIT> ) return false ; int64_t MergeRHS ; if ( mi_match ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_ICst ( MergeRHS ) ) && MergeRHS == <NUM_LIT> ) {

return Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> void <ISA_LIT>InstructionSelector :: renderFrameIndex ( MachineInstrBuilder & MIB , const MachineInstr & MI , int OpIdx ) const { MIB . addFrameIndex ( ( MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ) ) ;


<s> MIB . addFrameIndex ( ( MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ) ) ;


<s> renderTruncTImm ( MIB , MI , OpIdx ) ;


<s> void renderTruncTImm32 ( MachineInstrBuilder & MIB , const MachineInstr & MI , int OpIdx ) const { renderTruncTImm ( MIB , MI , OpIdx ) ;


<s> if ( ! MRI -> use_nodbg_empty ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { Function & F = MBB -> getParent ( ) -> getFunction ( ) ; DiagnosticInfoUnsupported NoFpRet ( F , <STR_LIT> , MI . getDebugLoc ( ) , DS_Error ) ; F . getContext ( ) . diagnose ( NoFpRet ) ; return false ; } MachineOperand & VDataIn = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & VIndex = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & VOffset = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & SOffset = MI . getOperand ( <NUM_LIT> ) ; int16_t Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; bool HasVOffset = ! isOperandImmEqual ( VOffset , <NUM_LIT> , * MRI ) ; bool HasVIndex = ! isOperandImmEqual ( VIndex , <NUM_LIT> , * MRI ) ; unsigned Opcode ; if ( HasVOffset ) { Opcode = HasVIndex ? <STR_LIT> : <STR_LIT> ; } else { Opcode = HasVIndex ? <STR_LIT> : <STR_LIT> ; } if ( MRI -> getType ( VDataIn . getReg ( ) ) . isVector ( ) ) { switch ( Opcode ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } } auto I = BuildMI ( * MBB , MI , DL , TII . get ( Opcode ) ) ; I . add ( VDataIn ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { Register IdxReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , & * I , DL , TII . get ( <STR_LIT> ) , IdxReg ) . addReg ( VIndex . getReg ( ) ) . addImm ( <STR_LIT> ) . addReg ( VOffset . getReg ( ) ) . addImm ( <STR_LIT> ) ; I . addReg ( IdxReg ) ; } else if ( HasVIndex ) { I . add ( VIndex ) ; } else if ( HasVOffset ) { I . add ( VOffset ) ; } I . add ( MI . getOperand ( <NUM_LIT> ) ) ; I . add ( SOffset ) ; I . addImm ( Offset ) ; renderExtractSLC ( I , MI , <NUM_LIT> ) ; I . cloneMemRefs ( MI ) ; MI . eraseFromParent ( ) ; return true ;


<s> const DebugLoc & DL = I . getDebugLoc ( ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned Size = MRI -> getType ( DstReg ) . getSizeInBits ( ) ; const bool Is64 = Size == <NUM_LIT> ; if ( Size != STI . getWavefrontSize ( ) ) return false ; Optional < ValueAndVReg > Arg = getConstantVRegValWithLookThrough ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , * MRI , true ) ; if ( Arg . hasValue ( ) ) { const int64_t Value = Arg . getValue ( ) . Value ; if ( Value == <NUM_LIT> ) { unsigned Opcode = Is64 ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , DstReg ) . addImm ( <NUM_LIT> ) ; } else if ( Value == - <NUM_LIT> ) { Register SrcReg = Is64 ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) ; } else return false ;


<s> MI . setDesc ( TII . get ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ;


<s> if ( ! RBI . constrainGenericRegister ( DstReg , * TRI . getBoolRC ( ) , * MRI ) ) return false ; const TargetRegisterClass * SrcRC = TRI . getConstrainedRegClassForOperand ( Src , * MRI ) ; Register MaskedReg = MRI -> createVirtualRegister ( SrcRC ) ; unsigned AndOpc = TRI . isSGPRClass ( SrcRC ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & I , DL , TII . get ( AndOpc ) , MaskedReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( MaskedReg ) ; if ( ! MRI -> getRegClassOrNull ( SrcReg ) ) MRI -> setRegClass ( SrcReg , SrcRC ) ; I . eraseFromParent ( ) ; return true ; } const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ; if ( RC && ! RBI . constrainGenericRegister ( DstReg , * RC , * MRI ) ) return false ; return true ; } for ( const MachineOperand & MO : I . operands ( ) ) {

if ( MO . getReg ( ) . isPhysical ( ) ) continue ;


<s> Register Src0 = ChooseDenom != <NUM_LIT> ? Numer : Denom ; auto MIB = BuildMI ( * MBB , & MI , DL , TII . get ( Opc ) , Dst0 ) . addDef ( Dst1 ) . addImm ( <NUM_LIT> ) . addUse ( Src0 ) . addImm ( <NUM_LIT> ) . addUse ( Denom ) . addImm ( <NUM_LIT> ) . addUse ( Numer ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectDS128Bit8ByteAligned ( MachineOperand & Root ) const { return selectDSReadWrite2 ( Root , <NUM_LIT> ) ;


<s> if ( ! RootDef ) return std :: make_pair ( Root . getReg ( ) , <NUM_LIT> ) ; int64_t ConstAddr = <NUM_LIT> ; Register PtrBase ; int64_t Offset ; std :: tie ( PtrBase , Offset ) = getPtrBaseWithConstantOffset ( Root . getReg ( ) , * MRI ) ; if ( Offset ) { if ( isDSOffsetLegal ( PtrBase , Offset ) ) { return std :: make_pair ( PtrBase , Offset ) ; }

} else if ( RootDef -> getOpcode ( ) == <STR_LIT> ) {


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectDS64Bit4ByteAligned ( MachineOperand & Root ) const { return selectDSReadWrite2 ( Root , <NUM_LIT> ) ;


<s> bool IsGDS = PtrTy . getAddressSpace ( ) == <ISA_LIT>AS :: REGION_ADDRESS ; unsigned Offset ; std :: tie ( PtrBase , Offset ) = selectDS1Addr1OffsetImpl ( MI . getOperand ( <NUM_LIT> ) ) ; if ( ! isDSOffsetLegal ( PtrBase , Offset ) ) { PtrBase = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Offset = <NUM_LIT> ; } MachineBasicBlock * MBB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; const unsigned Opc = IsAppend ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( PtrBase ) ; if ( ! RBI . constrainGenericRegister ( PtrBase , <STR_LIT> , * MRI ) ) return false ; auto MIB = BuildMI ( * MBB , & MI , DL , TII . get ( Opc ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( Offset ) . addImm ( IsGDS ? - <NUM_LIT> : <NUM_LIT> ) . cloneMemRefs ( MI ) ;


<s> Register PtrBase = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT PtrTy = MRI -> getType ( PtrBase ) ; bool IsGDS = PtrTy . getAddressSpace ( ) == <ISA_LIT>AS :: REGION_ADDRESS ; unsigned Offset ; std :: tie ( PtrBase , Offset ) = selectDS1Addr1OffsetImpl ( MI . getOperand ( <NUM_LIT> ) ) ; if ( ! isDSOffsetLegal ( PtrBase , Offset ) ) { PtrBase = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Offset = <NUM_LIT> ; }

MachineBasicBlock * MBB = MI . getParent ( ) ;


<s> assert ( HasVSrc || MI . getNumOperands ( ) == <NUM_LIT> ) ; Register BaseOffset = MI . getOperand ( HasVSrc ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; const RegisterBank * OffsetRB = RBI . getRegBank ( BaseOffset , * MRI , TRI ) ; if ( OffsetRB -> getID ( ) != <STR_LIT> ) return false ; MachineInstr * OffsetDef = getDefIgnoringCopies ( BaseOffset , * MRI ) ; assert ( OffsetDef ) ; unsigned ImmOffset ; MachineBasicBlock * MBB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineInstr * Readfirstlane = nullptr ; if ( OffsetDef -> getOpcode ( ) == <STR_LIT> ) { Readfirstlane = OffsetDef ; BaseOffset = OffsetDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OffsetDef = getDefIgnoringCopies ( BaseOffset , * MRI ) ; } if ( OffsetDef -> getOpcode ( ) == <STR_LIT> ) { ImmOffset = OffsetDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } else { std :: tie ( BaseOffset , ImmOffset , OffsetDef ) = <STR_LIT> ( * MRI , BaseOffset ) ; if ( Readfirstlane ) { if ( ! RBI . constrainGenericRegister ( BaseOffset , <STR_LIT> , * MRI ) ) return false ; Readfirstlane -> getOperand ( <NUM_LIT> ) . setReg ( BaseOffset ) ; BaseOffset = Readfirstlane -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } else { if ( ! RBI . constrainGenericRegister ( BaseOffset , <STR_LIT> , * MRI ) ) return false ; } Register M0Base = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , M0Base ) . addReg ( BaseOffset ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( M0Base ) ; } auto MIB = BuildMI ( * MBB , & MI , DL , TII . get ( gwsIntrinToOpcode ( IID ) ) ) ; if ( HasVSrc ) { Register VSrc = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MIB . addReg ( VSrc ) ; if ( ! RBI . constrainGenericRegister ( VSrc , <STR_LIT> , * MRI ) ) return false ; } MIB . addImm ( ImmOffset ) . cloneMemRefs ( MI ) ; MI . eraseFromParent ( ) ; return true ;


<s> if ( ! RBI . constrainGenericRegister ( BaseOffset , <STR_LIT> , * MRI ) ) return false ; Readfirstlane -> getOperand ( <NUM_LIT> ) . setReg ( BaseOffset ) ; BaseOffset = Readfirstlane -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } else { if ( ! RBI . constrainGenericRegister ( BaseOffset , <STR_LIT> , * MRI ) ) return false ; } Register M0Base = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , M0Base ) . addReg ( BaseOffset ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( M0Base ) ; } auto MIB = BuildMI ( * MBB , & MI , DL , TII . get ( gwsIntrinToOpcode ( IID ) ) ) ; if ( HasVSrc ) { Register VSrc = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MIB . addReg ( VSrc ) ; if ( ! RBI . constrainGenericRegister ( VSrc , <STR_LIT> , * MRI ) ) return false ; } MIB . addImm ( ImmOffset ) . cloneMemRefs ( MI ) ;


<s> } if ( IndexOperand ) report_fatal_error ( <STR_LIT> ) ; unsigned Instruction = IntrID == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; unsigned ShaderType = <ISA_LIT>InstrInfo :: getDSShaderTypeValue ( * MF ) ; unsigned Offset0 = OrderedCountIndex << <NUM_LIT> ; unsigned Offset1 = WaveRelease | ( WaveDone << <NUM_LIT> ) | ( ShaderType << <NUM_LIT> ) | ( Instruction << <NUM_LIT> ) ; if ( STI . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) Offset1 |= ( CountDw - <NUM_LIT> ) << <NUM_LIT> ; unsigned Offset = Offset0 | ( Offset1 << <NUM_LIT> ) ; Register M0Val = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( M0Val ) ;

Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Reg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset + <NUM_LIT> ) ; }


<s> Register Reg ; unsigned Offset ; std :: tie ( Reg , Offset ) = selectDSReadWrite2Impl ( Root , Size ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Reg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset + <NUM_LIT> ) ;


<s> const MachineInstr * RootDef = MRI -> getVRegDef ( Root . getReg ( ) ) ; if ( ! RootDef ) return std :: make_pair ( Root . getReg ( ) , <NUM_LIT> ) ; int64_t ConstAddr = <NUM_LIT> ; Register PtrBase ; int64_t Offset ;

std :: tie ( PtrBase , Offset ) = getPtrBaseWithConstantOffset ( Root . getReg ( ) , * MRI ) ;


<s> return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrWithOffset . first ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( PtrWithOffset . second ) ; } , } } ;


<s> auto Default = std :: make_pair ( Root . getReg ( ) , <NUM_LIT> ) ; if ( ! STI . hasFlatInstOffsets ( ) ) return Default ; const MachineInstr * OpDef = MRI -> getVRegDef ( Root . getReg ( ) ) ; if ( ! OpDef || OpDef -> getOpcode ( ) != <STR_LIT> ) return Default ; Optional < int64_t > Offset = getConstantVRegVal ( OpDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , * MRI ) ; if ( ! Offset . hasValue ( ) ) return Default ; unsigned AddrSpace = ( * MI -> memoperands_begin ( ) ) -> getAddrSpace ( ) ; if ( ! TII . isLegalFLATOffset ( Offset . getValue ( ) , AddrSpace , Signed ) ) return Default ; Register BasePtr = OpDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ;

return std :: make_pair ( BasePtr , Offset . getValue ( ) ) ;


<s> std :: pair < Register , int > <ISA_LIT>InstructionSelector :: selectFlatOffsetImpl ( MachineOperand & Root ) const { MachineInstr * MI = Root . getParent ( ) ; auto Default = std :: make_pair ( Root . getReg ( ) , <NUM_LIT> ) ; if ( ! STI . hasFlatInstOffsets ( ) ) return Default ; const MachineInstr * OpDef = MRI -> getVRegDef ( Root . getReg ( ) ) ; if ( ! OpDef || OpDef -> getOpcode ( ) != <STR_LIT> ) return Default ; Optional < int64_t > Offset = getConstantVRegVal ( OpDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , * MRI ) ; if ( ! Offset . hasValue ( ) ) return Default ; unsigned AddrSpace = ( * MI -> memoperands_begin ( ) ) -> getAddrSpace ( ) ; if ( ! TII . isLegalFLATOffset ( Offset . getValue ( ) , AddrSpace , Signed ) ) return Default ; Register BasePtr = OpDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return std :: make_pair ( BasePtr , Offset . getValue ( ) ) ;


<s> auto PtrWithOffset = selectFlatOffsetImpl < true > ( Root ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrWithOffset . first ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( PtrWithOffset . second ) ; } , } } ;


[ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrWithOffset . first ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( PtrWithOffset . second ) ; } , } } ;


<s> auto MIB = BuildMI ( * MBB , & MI , DL , TII . get ( Opc ) ) . addReg ( Addr . first ) . addReg ( Data ) . addImm ( Addr . second ) . addImm ( <NUM_LIT> ) . cloneMemRefs ( MI ) ; MI . eraseFromParent ( ) ;

return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ;


<s> Register Data = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned Opc = MRI -> getType ( Data ) . isVector ( ) ? <STR_LIT> : <STR_LIT> ; auto MIB = BuildMI ( * MBB , & MI , DL , TII . get ( Opc ) ) . addReg ( Addr . first ) . addReg ( Data ) . addImm ( Addr . second ) . addImm ( <NUM_LIT> ) . cloneMemRefs ( MI ) ; MI . eraseFromParent ( ) ;


<s> const MachineInstr * PtrBaseDef = getDefIgnoringCopies ( PtrBase , * MRI ) ; if ( PtrBaseDef -> getOpcode ( ) != <STR_LIT> ) return None ; Register PtrBaseSrc = getSrcRegIgnoringCopies ( PtrBaseDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , * MRI ) ; if ( ! PtrBaseSrc ) return None ; const RegisterBank * BaseRB = RBI . getRegBank ( PtrBaseSrc , * MRI , TRI ) ; if ( BaseRB -> getID ( ) != <STR_LIT> ) return None ; Register SAddr = PtrBaseSrc ;

Register PtrBaseOffset = PtrBaseDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> const unsigned Opc = Sub ? <STR_LIT> : <STR_LIT> ; MachineInstr * Add = BuildMI ( * BB , & I , DL , TII . get ( Opc ) , DstReg ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * Add , TII , TRI , RBI ) ; } if ( STI . hasAddNoCarry ( ) ) { const unsigned Opc = Sub ? <STR_LIT> : <STR_LIT> ; I . setDesc ( TII . get ( Opc ) ) ; I . addOperand ( * MF , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; I . addOperand ( * MF , MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } const unsigned Opc = Sub ? <STR_LIT> : <STR_LIT> ; Register UnusedCarry = MRI -> createVirtualRegister ( TRI . getWaveMaskRegClass ( ) ) ; MachineInstr * Add = BuildMI ( * BB , & I , DL , TII . get ( Opc ) , DstReg ) . addDef ( UnusedCarry , RegState :: Dead ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * Add , TII , TRI , RBI ) ; } assert ( ! Sub && <STR_LIT> ) ;

const TargetRegisterClass & RC = IsSALU ? <STR_LIT> : <STR_LIT> ;


<s> } else return selectImpl ( MI , * CoverageInfo ) ; auto MIB = BuildMI ( * BB , & MI , DL , TII . get ( Opcode ) , TmpReg ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( VAddr ) MIB . addReg ( VAddr ) ; MIB . addReg ( RSrcReg ) ; if ( SOffset ) MIB . addReg ( SOffset ) ; else MIB . addImm ( <NUM_LIT> ) ; MIB . addImm ( Offset ) ; MIB . addImm ( <NUM_LIT> ) ; MIB . addImm ( <NUM_LIT> ) ; MIB . cloneMemRefs ( MI ) ;

BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( TmpReg , RegState :: Kill , SubReg ) ;


<s> I . setDesc ( TII . get ( getLogicalBitOpcode ( I . getOpcode ( ) , Is64 ) ) ) ; I . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , true , true , false , true ) ) ;

return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ;


<s> if ( DstRB -> getID ( ) != <STR_LIT> && DstRB -> getID ( ) != <STR_LIT> ) return false ; bool Is64 = Size > <NUM_LIT> || ( DstRB -> getID ( ) == <STR_LIT> && STI . isWave64 ( ) ) ; I . setDesc ( TII . get ( getLogicalBitOpcode ( I . getOpcode ( ) , Is64 ) ) ) ;

I . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , true , true , false , true ) ) ;


<s> ConstrainRC = TRI . getBoolRC ( ) ; } if ( ! MRI -> getRegClassOrNull ( CondReg ) ) MRI -> setRegClass ( CondReg , ConstrainRC ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , CondPhysReg ) . addReg ( CondReg ) ; BuildMI ( * BB , & I , DL , TII . get ( BrOpcode ) ) . addMBB ( I . getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; I . eraseFromParent ( ) ;


<s> auto ConstSrc1 = getConstantVRegValWithLookThrough ( Src1 , * MRI , true , true ) ; if ( ConstSrc1 ) { auto ConstSrc0 = getConstantVRegValWithLookThrough ( Src0 , * MRI , true , true ) ; if ( ConstSrc0 ) { uint32_t Lo16 = static_cast < uint32_t > ( ConstSrc0 -> Value ) & <NUM_LIT> ; uint32_t Hi16 = static_cast < uint32_t > ( ConstSrc1 -> Value ) & <NUM_LIT> ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , Dst ) . addImm ( Lo16 | ( Hi16 << <NUM_LIT> ) ) ; MI . eraseFromParent ( ) ; return RBI . constrainGenericRegister ( Dst , <STR_LIT> , * MRI ) ; } } MachineInstr * Src1Def = getDefIgnoringCopies ( Src1 , * MRI ) ; if ( Src1Def && Src1Def -> getOpcode ( ) == <STR_LIT> ) { MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . RemoveOperand ( <NUM_LIT> ) ; return RBI . constrainGenericRegister ( Dst , <STR_LIT> , * MRI ) && RBI . constrainGenericRegister ( Src0 , <STR_LIT> , * MRI ) ; } Register ShiftSrc0 ; Register ShiftSrc1 ; int64_t ShiftAmt ; bool Shift0 = mi_match ( Src0 , * MRI , m_OneUse ( m_GLShr ( m_Reg ( ShiftSrc0 ) , m_ICst ( ShiftAmt ) ) ) ) && ShiftAmt == <NUM_LIT> ; bool Shift1 = mi_match ( Src1 , * MRI , m_OneUse ( m_GLShr ( m_Reg ( ShiftSrc1 ) , m_ICst ( ShiftAmt ) ) ) ) && ShiftAmt == <NUM_LIT> ; unsigned Opc = <STR_LIT> ; if ( Shift0 && Shift1 ) { Opc = <STR_LIT> ; MI . getOperand ( <NUM_LIT> ) . setReg ( ShiftSrc0 ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( ShiftSrc1 ) ; } else if ( Shift1 ) { Opc = <STR_LIT> ; MI . getOperand ( <NUM_LIT> ) . setReg ( ShiftSrc1 ) ; } else if ( Shift0 && ConstSrc1 && ConstSrc1 -> Value == <NUM_LIT> ) {

auto MIB = BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , Dst ) . addReg ( ShiftSrc0 ) . addImm ( <NUM_LIT> ) ;


<s> MachineInstr * ResInst ; if ( IsSgpr && TII . isInlineConstant ( Imm ) ) { ResInst = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( I . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; } else { const TargetRegisterClass * RC = IsSgpr ? & <STR_LIT> : & <STR_LIT> ; Register LoReg = MRI -> createVirtualRegister ( RC ) ; Register HiReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , LoReg ) . addImm ( Imm . trunc ( <NUM_LIT> ) . getZExtValue ( ) ) ; BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , HiReg ) . addImm ( Imm . ashr ( <NUM_LIT> ) . getZExtValue ( ) ) ; ResInst = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( LoReg ) . addImm ( <STR_LIT> ) . addReg ( HiReg ) . addImm ( <STR_LIT> ) ; }


<s> const APInt & Imm = ImmOp . getFPImm ( ) -> getValueAPF ( ) . bitcastToAPInt ( ) ; ImmOp . ChangeToImmediate ( Imm . getZExtValue ( ) ) ; } else if ( ImmOp . isCImm ( ) ) { ImmOp . ChangeToImmediate ( ImmOp . getCImm ( ) -> getSExtValue ( ) ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } const RegisterBank * DstRB = RBI . getRegBank ( DstReg , * MRI , TRI ) ; const bool IsSgpr = DstRB -> getID ( ) == <STR_LIT> ; unsigned Opcode ; if ( DstRB -> getID ( ) == <STR_LIT> ) { Opcode = STI . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; } else { Opcode = IsSgpr ? <STR_LIT> : <STR_LIT> ; if ( Size == <NUM_LIT> ) return false ; } if ( Size != <NUM_LIT> ) { I . setDesc ( TII . get ( Opcode ) ) ; I . addImplicitDefUseOperands ( * MF ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } const DebugLoc & DL = I . getDebugLoc ( ) ; APInt Imm ( Size , I . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; MachineInstr * ResInst ; if ( IsSgpr && TII . isInlineConstant ( Imm ) ) { ResInst = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( I . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; } else { const TargetRegisterClass * RC = IsSgpr ? & <STR_LIT> : & <STR_LIT> ; Register LoReg = MRI -> createVirtualRegister ( RC ) ; Register HiReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , LoReg ) . addImm ( Imm . trunc ( <NUM_LIT> ) . getZExtValue ( ) ) ;

BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , HiReg ) . addImm ( Imm . ashr ( <NUM_LIT> ) . getZExtValue ( ) ) ;


<s> const TargetRegisterClass * DstRC = TRI . getRegClassForTypeOnBank ( DstTy , * DstRB , * MRI ) ; if ( ! SrcRC || ! DstRC ) return false ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) || ! RBI . constrainGenericRegister ( IdxReg , <STR_LIT> , * MRI ) ) return false ; MachineBasicBlock * BB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; const bool Is64 = DstTy . getSizeInBits ( ) == <NUM_LIT> ; unsigned SubReg ; std :: tie ( IdxReg , SubReg ) = computeIndirectRegIndex ( * MRI , TRI , SrcRC , IdxReg , DstTy . getSizeInBits ( ) / <NUM_LIT> ) ; if ( SrcRB -> getID ( ) == <STR_LIT> ) { if ( DstTy . getSizeInBits ( ) != <NUM_LIT> && ! Is64 ) return false ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( IdxReg ) ;


<s> Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const RegisterBank * DstRB = RBI . getRegBank ( DstReg , * MRI , TRI ) ; const bool IsVGPR = DstRB -> getID ( ) == <STR_LIT> ;

I . setDesc ( TII . get ( IsVGPR ? <STR_LIT> : <STR_LIT> ) ) ;


<s> const RegisterBank * DstRB = RBI . getRegBank ( DstReg , * MRI , TRI ) ; const bool IsVGPR = DstRB -> getID ( ) == <STR_LIT> ; I . setDesc ( TII . get ( IsVGPR ? <STR_LIT> : <STR_LIT> ) ) ; if ( IsVGPR ) I . addOperand ( * MF , MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ;

return RBI . constrainGenericRegister ( DstReg , IsVGPR ? <STR_LIT> : <STR_LIT> , * MRI ) ;


<s> LLT Src1Ty = MRI -> getType ( Src1Reg ) ; unsigned DstSize = MRI -> getType ( DstReg ) . getSizeInBits ( ) ; unsigned InsSize = Src1Ty . getSizeInBits ( ) ; int64_t Offset = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Offset % <NUM_LIT> != <NUM_LIT> || InsSize % <NUM_LIT> != <NUM_LIT> ) return false ; if ( InsSize > <NUM_LIT> ) return false ; unsigned SubReg = TRI . getSubRegFromChannel ( Offset / <NUM_LIT> , InsSize / <NUM_LIT> ) ; if ( SubReg == <STR_LIT> ) return false ; const RegisterBank * DstBank = RBI . getRegBank ( DstReg , * MRI , TRI ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForSizeOnBank ( DstSize , * DstBank , * MRI ) ; if ( ! DstRC ) return false ; const RegisterBank * Src0Bank = RBI . getRegBank ( Src0Reg , * MRI , TRI ) ;

const RegisterBank * Src1Bank = RBI . getRegBank ( Src1Reg , * MRI , TRI ) ;


<s> MachineBasicBlock * BB = I . getParent ( ) ; BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ;

for ( Register Reg : { DstReg , Src0Reg , Src1Reg } ) MRI -> setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ;


return selectDSAppendConsume ( I , true ) ;


<s> bool <ISA_LIT>InstructionSelector :: selectG_LOAD_STORE_ATOMICRMW ( MachineInstr & I ) const { initM0 ( I ) ; return selectImpl ( I , * CoverageInfo ) ;


return selectImpl ( I , * CoverageInfo ) ;


<s> BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } unsigned NoCarryOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; unsigned CarryOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & I , DL , TII . get ( HasCarryIn ? CarryOpc : NoCarryOpc ) , Dst0Reg ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , Dst1Reg ) . addReg ( <STR_LIT> ) ; if ( ! MRI -> getRegClassOrNull ( Dst1Reg ) ) MRI -> setRegClass ( Dst1Reg , & <STR_LIT> ) ; if ( ! RBI . constrainGenericRegister ( Dst0Reg , <STR_LIT> , * MRI ) || ! RBI . constrainGenericRegister ( Src0Reg , <STR_LIT> , * MRI ) || ! RBI . constrainGenericRegister ( Src1Reg , <STR_LIT> , * MRI ) ) return false ; if ( HasCarryIn && ! RBI . constrainGenericRegister ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> , * MRI ) ) return false ; I . eraseFromParent ( ) ; return true ;


<s> const unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; const RegisterBank * SrcBank = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForSizeOnBank ( SrcSize , * SrcBank , * MRI ) ; if ( ! SrcRC || ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; ArrayRef < int16_t > SubRegs = TRI . getRegSplitParts ( SrcRC , DstSize / <NUM_LIT> ) ; for ( int I = <NUM_LIT> , E = NumDst ; I != E ; ++ I ) {

MachineOperand & Dst = MI . getOperand ( I ) ;


<s> ArrayRef < int16_t > SubRegs = TRI . getRegSplitParts ( SrcRC , DstSize / <NUM_LIT> ) ; for ( int I = <NUM_LIT> , E = NumDst ; I != E ; ++ I ) { MachineOperand & Dst = MI . getOperand ( I ) ; BuildMI ( * BB , & MI , DL , TII . get ( TargetOpcode :: COPY ) , Dst . getReg ( ) ) . addReg ( SrcReg , <NUM_LIT> , SubRegs [ I ] ) ; SrcRC = TRI . getSubClassWithSubReg ( SrcRC , SubRegs [ I ] ) ; if ( ! SrcRC || ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ; if ( DstRC && ! RBI . constrainGenericRegister ( Dst . getReg ( ) , * DstRC , * MRI ) ) return false ; } MI . eraseFromParent ( ) ;


<s> MachineBasicBlock * BB = I . getParent ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Size = RBI . getSizeInBits ( SrcReg , * MRI , TRI ) ; auto Pred = static_cast < CmpInst :: Predicate > ( I . getOperand ( <NUM_LIT> ) . getImm ( ) ) ;

int Opcode = getV_CMPOpcode ( Pred , Size ) ;


<s> bool <ISA_LIT>InstructionSelector :: selectIntrinsicIcmp ( MachineInstr & I ) const { Register Dst = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isVCC ( Dst , * MRI ) ) return false ; if ( MRI -> getType ( Dst ) . getSizeInBits ( ) != STI . getWavefrontSize ( ) ) return false ; MachineBasicBlock * BB = I . getParent ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Size = RBI . getSizeInBits ( SrcReg , * MRI , TRI ) ; auto Pred = static_cast < CmpInst :: Predicate > ( I . getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> bool <ISA_LIT>InstructionSelector :: selectMUBUFOffsetImpl ( MachineOperand & Root , Register & RSrcReg , Register & SOffset , int64_t & Offset ) const { if ( STI . useFlatForGlobal ( ) ) return false ; MUBUFAddressData AddrData = parseMUBUFAddress ( Root . getReg ( ) ) ; if ( shouldUseAddr64 ( AddrData ) ) return false ; Register SRDPtr = AddrData . N0 ; Offset = AddrData . Offset ;

MachineIRBuilder B ( * Root . getParent ( ) ) ;


<s> const MDNode * Metadata = I . getOperand ( <NUM_LIT> ) . getMetadata ( ) ; auto SymbolName = cast < MDString > ( Metadata -> getOperand ( <NUM_LIT> ) ) -> getString ( ) ; auto RelocSymbol = cast < GlobalVariable > ( M -> getOrInsertGlobal ( SymbolName , Type :: getInt32Ty ( M -> getContext ( ) ) ) ) ; MachineBasicBlock * BB = I . getParent ( ) ; BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( IsVALU ? <STR_LIT> : <STR_LIT> ) , DstReg ) . addGlobalAddress ( RelocSymbol , <NUM_LIT> , <ISA_LIT>InstrInfo :: MO_ABS32_LO ) ; I . eraseFromParent ( ) ; return true ;


<s> bool <ISA_LIT>InstructionSelector :: selectRelocConstant ( MachineInstr & I ) const { Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const RegisterBank * DstBank = RBI . getRegBank ( DstReg , * MRI , TRI ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForSizeOnBank ( <NUM_LIT> , * DstBank , * MRI ) ; if ( ! DstRC || ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) ) return false ; const bool IsVALU = DstBank -> getID ( ) == <STR_LIT> ; Module * M = MF -> getFunction ( ) . getParent ( ) ; const MDNode * Metadata = I . getOperand ( <NUM_LIT> ) . getMetadata ( ) ;

auto SymbolName = cast < MDString > ( Metadata -> getOperand ( <NUM_LIT> ) ) -> getString ( ) ;


<s> MachineFunction & MF = * MBB -> getParent ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; MachineOperand & Dst = I . getOperand ( <NUM_LIT> ) ; Register DstReg = Dst . getReg ( ) ; unsigned Depth = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ; if ( ! RC -> hasSubClassEq ( & <STR_LIT> ) || ! RBI . constrainGenericRegister ( DstReg , * RC , * MRI ) ) return false ;

if ( Depth != <NUM_LIT> || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> isEntryFunction ( ) ) {


<s> MachineBasicBlock * MBB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) ) ; MI . eraseFromParent ( ) ; return true ; } }

return selectImpl ( MI , * CoverageInfo ) ;


<s> std :: tie ( Src , Mods ) = selectVOP3ModsImpl ( Root , false ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Src ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Mods ) ; } } } ;


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectVOP3BMods ( MachineOperand & Root ) const { Register Src ; unsigned Mods ; std :: tie ( Src , Mods ) = selectVOP3ModsImpl ( Root , false ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Src ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Mods ) ; } } } ;


<s> [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Src ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Mods ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } } } ;


<s> [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Src ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Mods ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; }


<s> MI = getDefIgnoringCopies ( Src , * MRI ) ; } if ( AllowAbs && MI && MI -> getOpcode ( ) == <STR_LIT> ) { Src = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Mods |= <STR_LIT> ; } if ( Mods != <NUM_LIT> && RBI . getRegBank ( Src , * MRI , TRI ) -> getID ( ) != <STR_LIT> ) { MachineInstr * UseMI = Root . getParent ( ) ; Register VGPRSrc = MRI -> cloneVirtualRegister ( OrigSrc ) ; BuildMI ( * UseMI -> getParent ( ) , UseMI , UseMI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , VGPRSrc ) . addReg ( Src ) ; Src = VGPRSrc ; } return std :: make_pair ( Src , Mods ) ;


<s> if ( Mods != <NUM_LIT> && RBI . getRegBank ( Src , * MRI , TRI ) -> getID ( ) != <STR_LIT> ) { MachineInstr * UseMI = Root . getParent ( ) ; Register VGPRSrc = MRI -> cloneVirtualRegister ( OrigSrc ) ; BuildMI ( * UseMI -> getParent ( ) , UseMI , UseMI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , VGPRSrc ) . addReg ( Src ) ; Src = VGPRSrc ;


<s> std :: tie ( Src , Mods ) = selectVOP3ModsImpl ( Root ) ; if ( ! isKnownNeverNaN ( Src , * MRI ) ) return None ;


[ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Src ) ; } , [ = ] ( MachineInstrBuilder & MIB ) {


<s> Optional < ValueAndVReg > ConstSelect = getConstantVRegValWithLookThrough ( LaneSelect , * MRI , true , true ) ; if ( ConstSelect ) { MIB . addReg ( Val ) ; MIB . addImm ( ConstSelect -> Value & maskTrailingOnes < uint64_t > ( STI . getWavefrontSizeLog2 ( ) ) ) ; } else { Optional < ValueAndVReg > ConstVal = getConstantVRegValWithLookThrough ( Val , * MRI , true , true ) ; if ( ConstVal && <STR_LIT> ( ConstVal -> Value , STI . hasInv2PiInlineImm ( ) ) ) { MIB . addImm ( ConstVal -> Value ) ; MIB . addReg ( LaneSelect ) ; } else { MIB . addReg ( Val ) ; RBI . constrainGenericRegister ( LaneSelect , <STR_LIT> , * MRI ) ; BuildMI ( * MBB , * MIB , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( LaneSelect ) ; MIB . addReg ( <STR_LIT> ) ; } } MIB . addReg ( VDstIn ) ;


<s> Subtarget = & MF . getSubtarget < GCNSubtarget > ( ) ; InstructionSelector :: setupMF ( MF , KB , CoverageInfo ) ;


<s> void <ISA_LIT>InstructionSelector :: setupMF ( MachineFunction & MF , GISelKnownBits & KB , CodeGenCoverage & CoverageInfo ) { MRI = & MF . getRegInfo ( ) ;

Subtarget = & MF . getSubtarget < GCNSubtarget > ( ) ;


<s> void <ISA_LIT>InstructionSelector :: setupMF ( MachineFunction & MF , GISelKnownBits * KB , CodeGenCoverage & CoverageInfo , ProfileSummaryInfo * P<ISA_LIT> , BlockFrequencyInfo * BFI , AAResults * AA ) {


<s> bool <ISA_LIT>InstructionSelector :: selectDSGW<ISA_LIT>ntrinsic ( MachineInstr & MI , <STR_LIT> IID ) const { if ( IID == <STR_LIT> && ! STI . hasGWSSemaReleaseAll ( ) ) return false ; const bool HasVSrc = MI . getNumOperands ( ) == <NUM_LIT> ; assert ( HasVSrc || MI . getNumOperands ( ) == <NUM_LIT> ) ; Register BaseOffset = MI . getOperand ( HasVSrc ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; const RegisterBank * OffsetRB = RBI . getRegBank ( BaseOffset , * MRI , TRI ) ; if ( OffsetRB -> getID ( ) != <STR_LIT> ) return false ; MachineInstr * OffsetDef = getDefIgnoringCopies ( BaseOffset , * MRI ) ; assert ( OffsetDef ) ; unsigned ImmOffset ; MachineBasicBlock * MBB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineInstr * Readfirstlane = nullptr ; if ( OffsetDef -> getOpcode ( ) == <STR_LIT> ) { Readfirstlane = OffsetDef ; BaseOffset = OffsetDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OffsetDef = getDefIgnoringCopies ( BaseOffset , * MRI ) ; } if ( OffsetDef -> getOpcode ( ) == <STR_LIT> ) { ImmOffset = OffsetDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } else { std :: tie ( BaseOffset , ImmOffset ) = <STR_LIT> ( * MRI , BaseOffset ) ; if ( Readfirstlane ) { if ( ! RBI . constrainGenericRegister ( BaseOffset , <STR_LIT> , * MRI ) ) return false ; Readfirstlane -> getOperand ( <NUM_LIT> ) . setReg ( BaseOffset ) ; BaseOffset = Readfirstlane -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } else { if ( ! RBI . constrainGenericRegister ( BaseOffset , <STR_LIT> , * MRI ) ) return false ; }

Register M0Base = MRI -> createVirtualRegister ( & <STR_LIT> ) ;


<s> Register Src1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI -> getType ( Src0 ) != S32 ) return false ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineBasicBlock * BB = MI . getParent ( ) ; auto ConstSrc1 = getConstantVRegValWithLookThrough ( Src1 , * MRI , true , true ) ; if ( ConstSrc1 ) { auto ConstSrc0 = getConstantVRegValWithLookThrough ( Src0 , * MRI , true , true ) ; if ( ConstSrc0 ) { uint32_t Lo16 = static_cast < uint32_t > ( ConstSrc0 -> Value ) & <NUM_LIT> ; uint32_t Hi16 = static_cast < uint32_t > ( ConstSrc1 -> Value ) & <NUM_LIT> ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , Dst ) . addImm ( Lo16 | ( Hi16 << <NUM_LIT> ) ) ; MI . eraseFromParent ( ) ; return RBI . constrainGenericRegister ( Dst , <STR_LIT> , * MRI ) ; } } MachineInstr * Src1Def = getDefIgnoringCopies ( Src1 , * MRI ) ;

if ( Src1Def && Src1Def -> getOpcode ( ) == <STR_LIT> ) {


<s> const unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const unsigned DstSize = DstTy . getSizeInBits ( ) ; unsigned Offset = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Offset % <NUM_LIT> != <NUM_LIT> || DstSize > <NUM_LIT> ) return false ; const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand ( I . getOperand ( <NUM_LIT> ) , * MRI ) ; if ( ! DstRC || ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) ) return false ; const RegisterBank * SrcBank = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForSizeOnBank ( SrcSize , * SrcBank , * MRI ) ; if ( ! SrcRC ) return false ; unsigned SubReg = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( Offset / <NUM_LIT> , DstSize / <NUM_LIT> ) ; SrcRC = TRI . getSubClassWithSubReg ( SrcRC , SubReg ) ; if ( ! SrcRC ) return false ; SrcReg = constrainOperandRegClass ( * MF , TRI , * MRI , TII , RBI , I , * SrcRC , I . getOperand ( <NUM_LIT> ) ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; BuildMI ( * BB , & I , DL , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( SrcReg , <NUM_LIT> , SubReg ) ; I . eraseFromParent ( ) ;


<s> Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DstTy = MRI -> getType ( DstReg ) ; LLT SrcTy = MRI -> getType ( SrcReg ) ; const unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const unsigned DstSize = DstTy . getSizeInBits ( ) ; unsigned Offset = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Offset % <NUM_LIT> != <NUM_LIT> || DstSize > <NUM_LIT> ) return false ; const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand ( I . getOperand ( <NUM_LIT> ) , * MRI ) ; if ( ! DstRC || ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) ) return false ; const RegisterBank * SrcBank = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForSizeOnBank ( SrcSize , * SrcBank , * MRI ) ; if ( ! SrcRC ) return false ; unsigned SubReg = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( Offset / <NUM_LIT> , DstSize / <NUM_LIT> ) ; SrcRC = TRI . getSubClassWithSubReg ( SrcRC , SubReg ) ; if ( ! SrcRC ) return false ; SrcReg = constrainOperandRegClass ( * MF , TRI , * MRI , TII , RBI , I , * SrcRC , I . getOperand ( <NUM_LIT> ) ) ;

const DebugLoc & DL = I . getDebugLoc ( ) ;


<s> if ( SubReg == <STR_LIT> ) return false ; const RegisterBank * DstBank = RBI . getRegBank ( DstReg , * MRI , TRI ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForSizeOnBank ( DstSize , * DstBank , * MRI ) ; if ( ! DstRC ) return false ; const RegisterBank * Src0Bank = RBI . getRegBank ( Src0Reg , * MRI , TRI ) ; const RegisterBank * Src1Bank = RBI . getRegBank ( Src1Reg , * MRI , TRI ) ; const TargetRegisterClass * Src0RC = TRI . getRegClassForSizeOnBank ( DstSize , * Src0Bank , * MRI ) ; const TargetRegisterClass * Src1RC = TRI . getRegClassForSizeOnBank ( InsSize , * Src1Bank , * MRI ) ; Src0RC = TRI . getSubClassWithSubReg ( Src0RC , SubReg ) ; if ( ! Src0RC || ! Src1RC ) return false ; if ( ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) || ! RBI . constrainGenericRegister ( Src0Reg , * Src0RC , * MRI ) || ! RBI . constrainGenericRegister ( Src1Reg , * Src1RC , * MRI ) ) return false ; const DebugLoc & DL = I . getDebugLoc ( ) ; BuildMI ( * BB , & I , DL , TII . get ( TargetOpcode :: INSERT_SUBREG ) , DstReg ) . addReg ( Src0Reg ) . addReg ( Src1Reg ) . addImm ( SubReg ) ; I . eraseFromParent ( ) ; return true ;


<s> const bool IsVGPR = DstRB -> getID ( ) == <STR_LIT> ; unsigned NewOpc = IsVGPR ? <STR_LIT> : <STR_LIT> ; unsigned MovOpc = IsVGPR ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass & RegRC = IsVGPR ? <STR_LIT> : <STR_LIT> ; LLT Ty = MRI -> getType ( DstReg ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForTypeOnBank ( Ty , * DstRB , * MRI ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForTypeOnBank ( Ty , * SrcRB , * MRI ) ; if ( ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) || ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; const DebugLoc & DL = I . getDebugLoc ( ) ; Register ImmReg = MRI -> createVirtualRegister ( & RegRC ) ;

BuildMI ( * BB , & I , DL , TII . get ( MovOpc ) , ImmReg ) . addImm ( Mask ) ;


<s> unsigned MovOpc = IsVGPR ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass & RegRC = IsVGPR ? <STR_LIT> : <STR_LIT> ; LLT Ty = MRI -> getType ( DstReg ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForTypeOnBank ( Ty , * DstRB , * MRI ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForTypeOnBank ( Ty , * SrcRB , * MRI ) ; if ( ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) || ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; const DebugLoc & DL = I . getDebugLoc ( ) ; Register ImmReg = MRI -> createVirtualRegister ( & RegRC ) ; BuildMI ( * BB , & I , DL , TII . get ( MovOpc ) , ImmReg ) . addImm ( Mask ) ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) { BuildMI ( * BB , & I , DL , TII . get ( NewOpc ) , DstReg ) . addReg ( SrcReg ) . addReg ( ImmReg ) ; I . eraseFromParent ( ) ;


<s> MIB . addReg ( Info -> getScratchRSrcReg ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( HighBits ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { const MachineMemOperand * MMO = * MI -> memoperands_begin ( ) ; const MachinePointerInfo & PtrInfo = MMO -> getPointerInfo ( ) ; if ( isStackPtrRelative ( PtrInfo ) ) MIB . addReg ( Info -> getStackPtrOffsetReg ( ) ) ; else MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset & <NUM_LIT> ) ; } } } ; } assert ( Offset == <NUM_LIT> ) ; Optional < int > FI ; Register VAddr = Root . getReg ( ) ; if ( const MachineInstr * RootDef = MRI -> getVRegDef ( Root . getReg ( ) ) ) { if ( isBaseWithConstantOffset ( Root , * MRI ) ) { const MachineOperand & LHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineOperand & RHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineInstr * LHSDef = MRI -> getVRegDef ( LHS . getReg ( ) ) ; const MachineInstr * RHSDef = MRI -> getVRegDef ( RHS . getReg ( ) ) ; if ( LHSDef && RHSDef ) { int64_t PossibleOffset = RHSDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ; if ( <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( PossibleOffset ) && ( ! STI . privateMemoryResourceIsRangeChecked ( ) || KnownBits -> signBitIsZero ( LHS . getReg ( ) ) ) ) { if ( LHSDef -> getOpcode ( ) == <STR_LIT> ) FI = LHSDef -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; else VAddr = LHS . getReg ( ) ; Offset = PossibleOffset ; } } } else if ( RootDef -> getOpcode ( ) == <STR_LIT> ) { FI = RootDef -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; } } return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Info -> getScratchRSrcReg ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { if ( FI . hasValue ( ) ) MIB . addFrameIndex ( FI . getValue ( ) ) ; else MIB . addReg ( VAddr ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { if ( ! Info -> isEntryFunction ( ) && FI . hasValue ( ) ) MIB . addReg ( Info -> getStackPtrOffsetReg ( ) ) ; else MIB . addImm ( <NUM_LIT> ) ;


<s> } const RegisterBank & RB = * RegClassOrBank . get < const RegisterBank * > ( ) ; DefRC = TRI . getRegClassForTypeOnBank ( DefTy , RB , * MRI ) ; if ( ! DefRC ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } I . setDesc ( TII . get ( TargetOpcode :: PHI ) ) ; return RBI . constrainGenericRegister ( DefReg , * DefRC , * MRI ) ;


<s> const Register DefReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DefTy = MRI -> getType ( DefReg ) ; const RegClassOrRegBank & RegClassOrBank = MRI -> getRegClassOrRegBank ( DefReg ) ; const TargetRegisterClass * DefRC = RegClassOrBank . dyn_cast < const TargetRegisterClass * > ( ) ; if ( ! DefRC ) { if ( ! DefTy . isValid ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } const RegisterBank & RB = * RegClassOrBank . get < const RegisterBank * > ( ) ;

DefRC = TRI . getRegClassForTypeOnBank ( DefTy , RB , * MRI ) ;


<s> if ( SrcReg == <STR_LIT> ) { const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ; if ( ! RC ) return true ; return RBI . constrainGenericRegister ( DstReg , * RC , * MRI ) ; } if ( ! isVCC ( SrcReg , * MRI ) ) { if ( ! RBI . constrainGenericRegister ( DstReg , * TRI . getBoolRC ( ) , * MRI ) ) return false ; const TargetRegisterClass * SrcRC = TRI . getConstrainedRegClassForOperand ( Src , * MRI ) ; Register MaskedReg = MRI -> createVirtualRegister ( SrcRC ) ; unsigned AndOpc = TRI . isSGPRClass ( SrcRC ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & I , DL , TII . get ( AndOpc ) , MaskedReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) ;

BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( MaskedReg ) ;


<s> BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( PtrBase ) ; if ( ! RBI . constrainGenericRegister ( PtrBase , <STR_LIT> , * MRI ) ) return false ; auto MIB = BuildMI ( * MBB , & MI , DL , TII . get ( Opc ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( Offset ) . addImm ( IsGDS ? - <NUM_LIT> : <NUM_LIT> ) . cloneMemRefs ( MI ) ;


<s> Register HiReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , LoReg ) . addImm ( Imm . trunc ( <NUM_LIT> ) . getZExtValue ( ) ) ; BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , HiReg ) . addImm ( Imm . ashr ( <NUM_LIT> ) . getZExtValue ( ) ) ; ResInst = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( LoReg ) . addImm ( <STR_LIT> ) . addReg ( HiReg ) . addImm ( <STR_LIT> ) ; } I . eraseFromParent ( ) ; const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand ( ResInst -> getOperand ( <NUM_LIT> ) , * MRI ) ; if ( ! DstRC ) return true ; return RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) ;


<s> case <STR_LIT> : { MachineBasicBlock * BB = I . getParent ( ) ; BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> Register DstReg0 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DstTy = MRI -> getType ( DstReg0 ) ; LLT SrcTy = MRI -> getType ( SrcReg ) ; const unsigned DstSize = DstTy . getSizeInBits ( ) ; const unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; const RegisterBank * SrcBank = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForSizeOnBank ( SrcSize , * SrcBank , * MRI ) ; if ( ! SrcRC || ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; const unsigned SrcFlags = getUndefRegState ( Src . isUndef ( ) ) ; ArrayRef < int16_t > SubRegs = TRI . getRegSplitParts ( SrcRC , DstSize / <NUM_LIT> ) ; for ( int I = <NUM_LIT> , E = NumDst ; I != E ; ++ I ) { MachineOperand & Dst = MI . getOperand ( I ) ;

BuildMI ( * BB , & MI , DL , TII . get ( TargetOpcode :: COPY ) , Dst . getReg ( ) ) . addReg ( SrcReg , SrcFlags , SubRegs [ I ] ) ;


<s> const RegisterBank * SrcBank = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForSizeOnBank ( SrcSize , * SrcBank , * MRI ) ; if ( ! SrcRC || ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; const unsigned SrcFlags = getUndefRegState ( Src . isUndef ( ) ) ; ArrayRef < int16_t > SubRegs = TRI . getRegSplitParts ( SrcRC , DstSize / <NUM_LIT> ) ; for ( int I = <NUM_LIT> , E = NumDst ; I != E ; ++ I ) {


<s> static unsigned extractDLC ( unsigned AuxiliaryData ) {

return ( AuxiliaryData >> <NUM_LIT> ) & <NUM_LIT> ;


<s> static unsigned extractDLC ( unsigned AuxiliaryData ) { return ( AuxiliaryData >> <NUM_LIT> ) & <NUM_LIT> ;


<s> static unsigned extractGLC ( unsigned AuxiliaryData ) { return AuxiliaryData & <NUM_LIT> ;


<s> static unsigned extractSLC ( unsigned AuxiliaryData ) { return ( AuxiliaryData >> <NUM_LIT> ) & <NUM_LIT> ;


<s> return ( AuxiliaryData >> <NUM_LIT> ) & <NUM_LIT> ;


<s> static unsigned extractSWZ ( unsigned AuxiliaryData ) { return ( AuxiliaryData >> <NUM_LIT> ) & <NUM_LIT> ;


<s> } int64_t Offset ; if ( Def -> getOpcode ( ) == <STR_LIT> ) { if ( mi_match ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_ICst ( Offset ) ) ) return std :: make_tuple ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , Offset , Def ) ;

if ( mi_match ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_Copy ( m_ICst ( Offset ) ) ) ) return std :: make_tuple ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , Offset , Def ) ;


<s> static unsigned getBufferStoreFormatOpcode ( LLT Ty , const unsigned MemSize , const bool Offen ) { bool IsD16Packed = Ty . getScalarSizeInBits ( ) == <NUM_LIT> ; bool IsD16Unpacked = <NUM_LIT> * MemSize < Ty . getSizeInBits ( ) ; int NumElts = Ty . isVector ( ) ? Ty . getNumElements ( ) : <NUM_LIT> ; if ( IsD16Packed ) { switch ( NumElts ) { case <NUM_LIT> : return Offen ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return Offen ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return Offen ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return Offen ? <STR_LIT> : <STR_LIT> ; default : return - <NUM_LIT> ; } } if ( IsD16Unpacked ) { switch ( NumElts ) { case <NUM_LIT> : return Offen ? <STR_LIT> : <STR_LIT> ;


<s> <STR_LIT> ; case <NUM_LIT> : return Offen ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return Offen ? <STR_LIT> : <STR_LIT> ; default : return - <NUM_LIT> ; } } if ( IsD16Unpacked ) { switch ( NumElts ) { case <NUM_LIT> : return Offen ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return Offen ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return Offen ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return Offen ? <STR_LIT> : <STR_LIT> ; default : return - <NUM_LIT> ; } } switch ( NumElts ) { case <NUM_LIT> : return Offen ? <STR_LIT> :


<s> <STR_LIT> ; default : unsigned Opc = Offen ? <STR_LIT> : <STR_LIT> ; if ( Size > <NUM_LIT> ) Opc = <STR_LIT> ( Opc , Size / <NUM_LIT> ) ; return Opc ; }


<s> if ( ( OffsetBits == <NUM_LIT> && ! isUInt < <NUM_LIT> > ( Offset ) ) || ( OffsetBits == <NUM_LIT> && ! isUInt < <NUM_LIT> > ( Offset ) ) ) return false ; if ( STI . hasUsableDSOffset ( ) || STI . unsafeDSOffsetFoldingEnabled ( ) ) return true ;

return KnownBits -> signBitIsZero ( Base . getReg ( ) ) ;


<s> if ( STI . hasUsableDSOffset ( ) || STI . unsafeDSOffsetFoldingEnabled ( ) ) return true ; return KnownBits -> signBitIsZero ( Base . getReg ( ) ) ;


<s> return mi_match ( Reg , MRI , m_Copy ( m_ICst ( C ) ) ) && C == <NUM_LIT> ;


<s> if ( mi_match ( Reg , MRI , m_ICst ( C ) ) && C == <NUM_LIT> ) return true ;

return mi_match ( Reg , MRI , m_Copy ( m_ICst ( C ) ) ) && C == <NUM_LIT> ;


<s> assert ( MI . getOpcode ( ) == TargetOpcode :: G_CONSTANT && <STR_LIT> ) ; Optional < int64_t > CstVal = getConstantVRegVal ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ;


<s> if ( ! MRI -> getRegClassOrNull ( SrcReg ) ) MRI -> setRegClass ( SrcReg , TRI . getConstrainedRegClassForOperand ( Src , * MRI ) ) ; I . eraseFromParent ( ) ; return true ; } const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ; if ( RC && ! RBI . constrainGenericRegister ( DstReg , * RC , * MRI ) ) return false ; if ( Src . isUndef ( ) ) { const TargetRegisterClass * SrcRC = TRI . getConstrainedRegClassForOperand ( Src , * MRI ) ; if ( SrcRC && ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; } return true ; } for ( const MachineOperand & MO : I . operands ( ) ) { if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) continue ; const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( MO , * MRI ) ;


<s> return true ; } const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ; if ( RC && ! RBI . constrainGenericRegister ( DstReg , * RC , * MRI ) ) return false ; if ( Src . isUndef ( ) ) { const TargetRegisterClass * SrcRC = TRI . getConstrainedRegClassForOperand ( Src , * MRI ) ; if ( SrcRC && ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; } return true ; } for ( const MachineOperand & MO : I . operands ( ) ) { if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) continue ; const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( MO , * MRI ) ; if ( ! RC ) continue ; RBI . constrainGenericRegister ( MO . getReg ( ) , * RC , * MRI ) ; } return true ;


<s> if ( isDSOffsetLegal ( * MRI , LHS , PossibleOffset , <NUM_LIT> ) ) { return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . add ( LHS ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( PossibleOffset ) ; } } } ; } } } else if ( RootDef -> getOpcode ( ) == <STR_LIT> ) { } else if ( mi_match ( Root . getReg ( ) , * MRI , m_ICst ( ConstAddr ) ) ) { }


<s> MachineInstr * Add = BuildMI ( * BB , & I , DL , TII . get ( Opc ) , DstReg ) . addDef ( UnusedCarry , RegState :: Dead ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * Add , TII , TRI , RBI ) ; } assert ( ! Sub && <STR_LIT> ) ; const TargetRegisterClass & RC = IsSALU ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass & HalfRC = IsSALU ? <STR_LIT> : <STR_LIT> ; MachineOperand Lo1 ( getSubOperand64 ( I . getOperand ( <NUM_LIT> ) , HalfRC , <STR_LIT> ) ) ; MachineOperand Lo2 ( getSubOperand64 ( I . getOperand ( <NUM_LIT> ) , HalfRC , <STR_LIT> ) ) ; MachineOperand Hi1 ( getSubOperand64 ( I . getOperand ( <NUM_LIT> ) , HalfRC , <STR_LIT> ) ) ; MachineOperand Hi2 ( getSubOperand64 ( I . getOperand ( <NUM_LIT> ) , HalfRC , <STR_LIT> ) ) ; Register DstLo = MRI -> createVirtualRegister ( & HalfRC ) ; Register DstHi = MRI -> createVirtualRegister ( & HalfRC ) ; if ( IsSALU ) { BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstLo ) . add ( Lo1 ) . add ( Lo2 ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstHi ) . add ( Hi1 ) . add ( Hi2 ) ; } else { const TargetRegisterClass * CarryRC = TRI . getWaveMaskRegClass ( ) ; Register CarryReg = MRI -> createVirtualRegister ( CarryRC ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstLo ) . addDef ( CarryReg ) . add ( Lo1 ) . add ( Lo2 ) . addImm ( <NUM_LIT> ) ; MachineInstr * Addc = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstHi ) . addDef ( MRI -> createVirtualRegister ( CarryRC ) , RegState :: Dead ) . add ( Hi1 ) . add ( Hi2 ) . addReg ( CarryReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; if ( ! constrainSelectedInstRegOperands ( * Addc , TII , TRI , RBI ) ) return false ; } BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( DstLo ) . addImm ( <STR_LIT> ) . addReg ( DstHi ) . addImm ( <STR_LIT> ) ; if ( ! RBI . constrainGenericRegister ( DstReg , RC , * MRI ) ) return false ;


<s> MachineOperand & Src1 = I . getOperand ( <NUM_LIT> ) ; Register DstReg = Dst . getReg ( ) ; unsigned Size = RBI . getSizeInBits ( DstReg , * MRI , TRI ) ; const RegisterBank * DstRB = RBI . getRegBank ( DstReg , * MRI , TRI ) ; if ( DstRB -> getID ( ) == <STR_LIT> ) { const TargetRegisterClass * RC = TRI . getBoolRC ( ) ; unsigned InstOpc = getLogicalBitOpcode ( I . getOpcode ( ) , RC == & <STR_LIT> ) ; I . setDesc ( TII . get ( InstOpc ) ) ; if ( Src0 . isUndef ( ) && ! MRI -> getRegClassOrNull ( Src0 . getReg ( ) ) ) MRI -> setRegClass ( Src0 . getReg ( ) , RC ) ; if ( Src1 . isUndef ( ) && ! MRI -> getRegClassOrNull ( Src1 . getReg ( ) ) ) MRI -> setRegClass ( Src1 . getReg ( ) , RC ) ;

return RBI . constrainGenericRegister ( DstReg , * RC , * MRI ) ;


<s> Register DstReg = Dst . getReg ( ) ; unsigned Size = RBI . getSizeInBits ( DstReg , * MRI , TRI ) ; const RegisterBank * DstRB = RBI . getRegBank ( DstReg , * MRI , TRI ) ; if ( DstRB -> getID ( ) == <STR_LIT> ) { const TargetRegisterClass * RC = TRI . getBoolRC ( ) ; unsigned InstOpc = getLogicalBitOpcode ( I . getOpcode ( ) , RC == & <STR_LIT> ) ; I . setDesc ( TII . get ( InstOpc ) ) ; if ( Src0 . isUndef ( ) && ! MRI -> getRegClassOrNull ( Src0 . getReg ( ) ) ) MRI -> setRegClass ( Src0 . getReg ( ) , RC ) ; if ( Src1 . isUndef ( ) && ! MRI -> getRegClassOrNull ( Src1 . getReg ( ) ) ) MRI -> setRegClass ( Src1 . getReg ( ) , RC ) ; return RBI . constrainGenericRegister ( DstReg , * RC , * MRI ) ; } if ( DstRB -> getID ( ) == <STR_LIT> ) { unsigned InstOpc = getLogicalBitOpcode ( I . getOpcode ( ) , Size > <NUM_LIT> ) ; I . setDesc ( TII . get ( InstOpc ) ) ; I . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , true , true , false , true ) ) ;

return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ;


<s> } else return false ; if ( ! MRI -> getRegClassOrNull ( CondReg ) ) MRI -> setRegClass ( CondReg , ConstrainRC ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , CondPhysReg ) . addReg ( CondReg ) ;

BuildMI ( * BB , & I , DL , TII . get ( BrOpcode ) ) . addMBB ( I . getOperand ( <NUM_LIT> ) . getMBB ( ) ) ;


<s> if ( Offset % <NUM_LIT> != <NUM_LIT> ) return false ; unsigned SubReg = TRI . getSubRegFromChannel ( Offset / <NUM_LIT> ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; MachineInstr * Copy = BuildMI ( * BB , & I , DL , TII . get ( TargetOpcode :: COPY ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> , SubReg ) ; for ( const MachineOperand & MO : Copy -> operands ( ) ) { const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( MO , * MRI ) ; if ( ! RC ) continue ; RBI . constrainGenericRegister ( MO . getReg ( ) , * RC , * MRI ) ;


<s> if ( IsVGPR ) I . addOperand ( * MF , MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ;

return RBI . constrainGenericRegister ( DstReg , IsVGPR ? <STR_LIT> : <STR_LIT> , * MRI ) ;


<s> unsigned Size = RBI . getSizeInBits ( SrcReg , * MRI , TRI ) ; auto Pred = ( CmpInst :: Predicate ) I . getOperand ( <NUM_LIT> ) . getPredicate ( ) ; Register CCReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isSCC ( CCReg , * MRI ) ) { int Opcode = getS_CMPOpcode ( Pred , Size ) ; if ( Opcode == - <NUM_LIT> ) return false ; MachineInstr * ICmp = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , CCReg ) . addReg ( <STR_LIT> ) ; bool Ret = constrainSelectedInstRegOperands ( * ICmp , TII , TRI , RBI ) && RBI . constrainGenericRegister ( CCReg , <STR_LIT> , * MRI ) ; I . eraseFromParent ( ) ; return Ret ; } int Opcode = getV_CMPOpcode ( Pred , Size ) ; if ( Opcode == - <NUM_LIT> ) return false ;

MachineInstr * ICmp = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ;


<s> const RegisterBank * Src1Bank = RBI . getRegBank ( Src1Reg , * MRI , TRI ) ; const TargetRegisterClass * Src0RC = TRI . getRegClassForSizeOnBank ( DstSize , * Src0Bank , * MRI ) ; const TargetRegisterClass * Src1RC = TRI . getRegClassForSizeOnBank ( InsSize , * Src1Bank , * MRI ) ; Src0RC = TRI . getSubClassWithSubReg ( Src0RC , SubReg ) ; if ( ! Src0RC ) return false ; if ( ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) || ! RBI . constrainGenericRegister ( Src0Reg , * Src0RC , * MRI ) || ! RBI . constrainGenericRegister ( Src1Reg , * Src1RC , * MRI ) ) return false ;


<s> switch ( IntrinsicID ) { case <STR_LIT> : { MachineBasicBlock * BB = I . getParent ( ) ; BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ; for ( Register Reg : { DstReg , Src0Reg , Src1Reg } ) MRI -> setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ; return true ; } default : return selectImpl ( I , * CoverageInfo ) ; }


<s> Register Undef = MRI -> createVirtualRegister ( & <STR_LIT> ) ; int64_t Done = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VM = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , Undef ) ; MachineInstr * Exp = buildEXP ( TII , & I , Tgt , Reg0 , Reg1 , Undef , Undef , VM , true , Enabled , Done ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * Exp , TII , TRI , RBI ) ; } case <STR_LIT> : { BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ; if ( ! MRI -> getRegClassOrNull ( Reg ) ) MRI -> setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ; return true ;


<s> int64_t Enabled = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t Done = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VM = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineInstr * Exp = buildEXP ( TII , & I , Tgt , I . getOperand ( <NUM_LIT> ) . getReg ( ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) , VM , false , Enabled , Done ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * Exp , TII , TRI , RBI ) ; } case <STR_LIT> : { const DebugLoc & DL = I . getDebugLoc ( ) ; int64_t Tgt = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t Enabled = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; Register Reg0 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ;

Register Reg1 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> const unsigned SrcSize = SrcTy . getSizeInBits ( ) ; if ( SrcSize < <NUM_LIT> ) return false ; const DebugLoc & DL = MI . getDebugLoc ( ) ; const RegisterBank * DstBank = RBI . getRegBank ( DstReg , * MRI , TRI ) ; const unsigned DstSize = DstTy . getSizeInBits ( ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForSizeOnBank ( DstSize , * DstBank , * MRI ) ; if ( ! DstRC ) return false ; ArrayRef < int16_t > SubRegs = TRI . getRegSplitParts ( DstRC , SrcSize / <NUM_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * BB , & MI , DL , TII . get ( TargetOpcode :: REG_SEQUENCE ) , DstReg ) ; for ( int I = <NUM_LIT> , E = MI . getNumOperands ( ) - <NUM_LIT> ; I != E ; ++ I ) { MachineOperand & Src = MI . getOperand ( I + <NUM_LIT> ) ; MIB . addReg ( Src . getReg ( ) , getUndefRegState ( Src . isUndef ( ) ) ) ; MIB . addImm ( SubRegs [ I ] ) ; const TargetRegisterClass * SrcRC = TRI . getConstrainedRegClassForOperand ( Src , * MRI ) ; if ( SrcRC && ! RBI . constrainGenericRegister ( Src . getReg ( ) , * SrcRC , * MRI ) ) return false ; } if ( ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) ) return false ; MI . eraseFromParent ( ) ; return true ;


<s> const DebugLoc & DL = I . getDebugLoc ( ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Size = RBI . getSizeInBits ( DstReg , * MRI , TRI ) ; assert ( Size <= <NUM_LIT> || Size == <NUM_LIT> ) ; const MachineOperand & CCOp = I . getOperand ( <NUM_LIT> ) ; Register CCReg = CCOp . getReg ( ) ; if ( isSCC ( CCReg , * MRI ) ) { unsigned SelectOpcode = Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; MachineInstr * CopySCC = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( CCReg ) ; if ( ! MRI -> getRegClassOrNull ( CCReg ) ) MRI -> setRegClass ( CCReg , TRI . getConstrainedRegClassForOperand ( CCOp , * MRI ) ) ; MachineInstr * Select = BuildMI ( * BB , & I , DL , TII . get ( SelectOpcode ) , DstReg ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; bool Ret = constrainSelectedInstRegOperands ( * Select , TII , TRI , RBI ) | constrainSelectedInstRegOperands ( * CopySCC , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return Ret ; } if ( Size > <NUM_LIT> ) return false ;

MachineInstr * Select = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . add ( I . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ;


<s> bool Signed = I . getOpcode ( ) == <STR_LIT> ; const DebugLoc & DL = I . getDebugLoc ( ) ; MachineBasicBlock & MBB = * I . getParent ( ) ; const Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI -> getType ( DstReg ) ; const LLT SrcTy = MRI -> getType ( SrcReg ) ; const LLT S1 = LLT :: scalar ( <NUM_LIT> ) ; const unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const unsigned DstSize = DstTy . getSizeInBits ( ) ; if ( ! DstTy . isScalar ( ) ) return false ; const RegisterBank * SrcBank = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; if ( SrcBank -> getID ( ) == <STR_LIT> ) { if ( SrcTy != S1 || DstSize > <NUM_LIT> ) return false ; unsigned Opcode = DstSize > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * DstRC = DstSize > <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ; Register TmpReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , TmpReg ) . addReg ( SrcReg ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( TmpReg ) ; BuildMI ( MBB , I , DL , TII . get ( Opcode ) , DstReg ) . addImm ( <NUM_LIT> ) . addImm ( Signed ? - <NUM_LIT> : <NUM_LIT> ) ; I . eraseFromParent ( ) ; return RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) ;


<s> const RegisterBank * SrcRB = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; if ( SrcRB != DstRB ) return false ; unsigned DstSize = DstTy . getSizeInBits ( ) ; unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForSizeOnBank ( SrcSize , * SrcRB , * MRI ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForSizeOnBank ( DstSize , * DstRB , * MRI ) ; if ( SrcSize > <NUM_LIT> ) { int SubRegIdx = sizeToSubRegIndex ( DstSize ) ; if ( SubRegIdx == - <NUM_LIT> ) return false ; SrcRC = TRI . getSubClassWithSubReg ( SrcRC , SubRegIdx ) ; if ( ! SrcRC ) return false ; I . getOperand ( <NUM_LIT> ) . setSubReg ( SubRegIdx ) ;


<s> bool <ISA_LIT>InstructionSelector :: selectG_UADDO_USUBO ( MachineInstr & I ) const { MachineBasicBlock * BB = I . getParent ( ) ; MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; Register Dst0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Dst1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const bool IsAdd = I . getOpcode ( ) == <STR_LIT> ; if ( ! isSCC ( Dst1Reg , MRI ) ) { unsigned NewOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; I . setDesc ( TII . get ( NewOpc ) ) ; I . addOperand ( * MF , MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; I . addOperand ( * MF , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & I , DL , TII . get ( NewOpc ) , Dst0Reg ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , Dst1Reg ) . addReg ( <STR_LIT> ) ; if ( ! MRI . getRegClassOrNull ( Dst1Reg ) ) MRI . setRegClass ( Dst1Reg , & <STR_LIT> ) ; if ( ! RBI . constrainGenericRegister ( Dst0Reg , <STR_LIT> , MRI ) || ! RBI . constrainGenericRegister ( Src0Reg , <STR_LIT> , MRI ) || ! RBI . constrainGenericRegister ( Src1Reg , <STR_LIT> , MRI ) ) return false ; I . eraseFromParent ( ) ; return true ;


<s> MachineBasicBlock * BB = I . getParent ( ) ; MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; Register Dst0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Dst1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const bool IsAdd = I . getOpcode ( ) == <STR_LIT> ; if ( ! isSCC ( Dst1Reg , MRI ) ) { unsigned NewOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; I . setDesc ( TII . get ( NewOpc ) ) ; I . addOperand ( * MF , MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; I . addOperand ( * MF , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & I , DL , TII . get ( NewOpc ) , Dst0Reg ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , Dst1Reg ) . addReg ( <STR_LIT> ) ; if ( ! MRI . getRegClassOrNull ( Dst1Reg ) ) MRI . setRegClass ( Dst1Reg , & <STR_LIT> ) ;

if ( ! RBI . constrainGenericRegister ( Dst0Reg , <STR_LIT> , MRI ) || ! RBI . constrainGenericRegister ( Src0Reg , <STR_LIT> , MRI ) || ! RBI . constrainGenericRegister ( Src1Reg , <STR_LIT> , MRI ) ) return false ;


<s> if ( isBaseWithConstantOffset ( Root , * MRI ) ) { const MachineOperand & LHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineOperand & RHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineInstr * LHSDef = MRI -> getVRegDef ( LHS . getReg ( ) ) ; const MachineInstr * RHSDef = MRI -> getVRegDef ( RHS . getReg ( ) ) ; if ( LHSDef && RHSDef ) { int64_t PossibleOffset = RHSDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ; if ( <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( PossibleOffset ) && ( ! STI . privateMemoryResourceIsRangeChecked ( ) || KnownBits -> signBitIsZero ( LHS . getReg ( ) ) ) ) { if ( LHSDef -> getOpcode ( ) == <STR_LIT> ) FI = LHSDef -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; else VAddr = LHS . getReg ( ) ; Offset = PossibleOffset ; } } } else if ( RootDef -> getOpcode ( ) == <STR_LIT> ) { FI = RootDef -> getOperand ( <NUM_LIT> ) . getIndex ( ) ;


<s> const MachineOperand & RHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineInstr * LHSDef = MRI -> getVRegDef ( LHS . getReg ( ) ) ; const MachineInstr * RHSDef = MRI -> getVRegDef ( RHS . getReg ( ) ) ; if ( LHSDef && RHSDef ) { int64_t PossibleOffset = RHSDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ; if ( <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( PossibleOffset ) && ( ! STI . privateMemoryResourceIsRangeChecked ( ) || KnownBits -> signBitIsZero ( LHS . getReg ( ) ) ) ) { if ( LHSDef -> getOpcode ( ) == <STR_LIT> ) FI = LHSDef -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; else VAddr = LHS . getReg ( ) ; Offset = PossibleOffset ; } } } else if ( RootDef -> getOpcode ( ) == <STR_LIT> ) { FI = RootDef -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; } } Register SOffset = FI . hasValue ( ) ? Info -> getStackPtrOffsetReg ( ) : Info -> getScratchWaveOffsetReg ( ) ;

return { { [ = ] ( MachineInstrBuilder & MIB ) {


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectMUBUFScratchOffset ( MachineOperand & Root ) const { MachineInstr * MI = Root . getParent ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; int64_t Offset = <NUM_LIT> ; if ( ! mi_match ( Root . getReg ( ) , * MRI , m_ICst ( Offset ) ) || ! <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( Offset ) ) return { } ; const MachineFunction * MF = MBB -> getParent ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const MachineMemOperand * MMO = * MI -> memoperands_begin ( ) ;

const MachinePointerInfo & PtrInfo = MMO -> getPointerInfo ( ) ;


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; int64_t Offset = <NUM_LIT> ; if ( ! mi_match ( Root . getReg ( ) , * MRI , m_ICst ( Offset ) ) || ! <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( Offset ) ) return { } ; const MachineFunction * MF = MBB -> getParent ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const MachineMemOperand * MMO = * MI -> memoperands_begin ( ) ; const MachinePointerInfo & PtrInfo = MMO -> getPointerInfo ( ) ; Register SOffsetReg = isStackPtrRelative ( PtrInfo ) ? Info -> getStackPtrOffsetReg ( ) : Info -> getScratchWaveOffsetReg ( ) ;


<s> const TargetRegisterClass * DefRC = RegClassOrBank . dyn_cast < const TargetRegisterClass * > ( ) ; if ( ! DefRC ) { if ( ! DefTy . isValid ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } const RegisterBank & RB = * RegClassOrBank . get < const RegisterBank * > ( ) ; if ( RB . getID ( ) == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } DefRC = TRI . getRegClassForTypeOnBank ( DefTy , RB , * MRI ) ;


<s> const TargetRegisterClass * DefRC = RegClassOrBank . dyn_cast < const TargetRegisterClass * > ( ) ; if ( ! DefRC ) { if ( ! DefTy . isValid ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } const RegisterBank & RB = * RegClassOrBank . get < const RegisterBank * > ( ) ; if ( RB . getID ( ) == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ;


<s> if ( ! <STR_LIT> ( STI , GEPInfo . Imm ) ) return None ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; int64_t EncodedImm = <STR_LIT> ( STI , GEPInfo . Imm ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( EncodedImm ) ; } } } ;


<s> int64_t EncodedImm = <STR_LIT> ( STI , GEPInfo . Imm ) ; if ( ! isUInt < <NUM_LIT> > ( EncodedImm ) ) return None ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) {


<s> SmallVector < GEPInfo , <NUM_LIT> > AddrInfo ; getAddrModeInfo ( * MI , * MRI , AddrInfo ) ; if ( AddrInfo . empty ( ) || AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) != <NUM_LIT> ) return None ; const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; if ( ! GEPInfo . Imm || ! isUInt < <NUM_LIT> > ( GEPInfo . Imm ) ) return None ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; Register OffsetReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , OffsetReg ) . addImm ( GEPInfo . Imm ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) {


<s> getBufferStoreOpcode ( Ty , MemSize , Offen ) ; if ( Opc == - <NUM_LIT> ) return false ; MachineInstrBuilder MIB = B . buildInstr ( Opc ) . addUse ( VData ) ; if ( Offen ) MIB . addUse ( VOffset ) ; MIB . addUse ( RSrc ) . addUse ( SOffset ) . addImm ( ImmOffset ) . addImm ( extractGLC ( AuxiliaryData ) ) . addImm ( extractSLC ( AuxiliaryData ) ) . addImm ( <NUM_LIT> ) . addImm ( extractDLC ( AuxiliaryData ) ) . addImm ( extractSWZ ( AuxiliaryData ) ) . addMemOperand ( MMO ) ; MI . eraseFromParent ( ) ;

return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ;


<s> getBufferStoreOpcode ( Ty , MemSize , Offen ) ; if ( Opc == - <NUM_LIT> ) return false ; MachineInstrBuilder MIB = B . buildInstr ( Opc ) . addUse ( VData ) ; if ( Offen ) MIB . addUse ( VOffset ) ;

MIB . addUse ( RSrc ) . addUse ( SOffset ) . addImm ( ImmOffset ) . addImm ( extractGLC ( AuxiliaryData ) ) . addImm ( extractSLC ( AuxiliaryData ) ) . addImm ( <NUM_LIT> ) . addImm ( extractDLC ( AuxiliaryData ) ) . addImm ( extractSWZ ( AuxiliaryData ) ) . addMemOperand ( MMO ) ;


<s> return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Src ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Mods ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; }


<s> std :: tie ( Src , Mods ) = selectVOP3ModsImpl ( Root . getReg ( ) ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Src ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Mods ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } } } ;


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectVOP3Mods0Clamp0OMod ( MachineOperand & Root ) const { Register Src ; unsigned Mods ; std :: tie ( Src , Mods ) = selectVOP3ModsImpl ( Root . getReg ( ) ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Src ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Mods ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; }


<s> return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Src ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Mods ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ;


<s> Mods |= <STR_LIT> ; MI = MRI -> getVRegDef ( Src ) ; } if ( MI && MI -> getOpcode ( ) == <STR_LIT> ) {

Src = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> std :: pair < Register , unsigned > <ISA_LIT>InstructionSelector :: selectVOP3ModsImpl ( Register Src ) const { unsigned Mods = <NUM_LIT> ; MachineInstr * MI = MRI -> getVRegDef ( Src ) ; if ( MI && MI -> getOpcode ( ) == <STR_LIT> ) { Src = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Mods |= <STR_LIT> ; MI = MRI -> getVRegDef ( Src ) ; } if ( MI && MI -> getOpcode ( ) == <STR_LIT> ) { Src = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Mods |= <STR_LIT> ; } return std :: make_pair ( Src , Mods ) ;


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectVOP3OpSelMods0 ( MachineOperand & Root ) const { return { {

[ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Root . getReg ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) {


<s> if ( Overflow != <NUM_LIT> ) { MachineBasicBlock :: iterator OldInsPt = B . getInsertPt ( ) ; MachineBasicBlock & OldMBB = B . getMBB ( ) ; B . setInstr ( * OffsetDef ) ; if ( ! BaseReg ) { BaseReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; B . buildInstr ( <STR_LIT> ) . addDef ( BaseReg ) . addImm ( Overflow ) ; } else { Register OverflowVal = MRI -> createVirtualRegister ( & <STR_LIT> ) ; B . buildInstr ( <STR_LIT> ) . addDef ( OverflowVal ) . addImm ( Overflow ) ; Register NewBaseReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; TII . getAddNoCarry ( B . getMBB ( ) , B . getInsertPt ( ) , B . getDebugLoc ( ) , NewBaseReg ) . addReg ( BaseReg ) . addReg ( OverflowVal , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; BaseReg = NewBaseReg ; } B . setInsertPt ( OldMBB , OldInsPt ) ; } return std :: make_tuple ( BaseReg , ImmOffset , TotalConstOffset ) ;


<s> unsigned SubReg ; std :: tie ( IdxReg , SubReg ) = computeIndirectRegIndex ( * MRI , TRI , SrcRC , IdxReg , DstTy . getSizeInBits ( ) / <NUM_LIT> ) ; if ( SrcRB -> getID ( ) == <STR_LIT> ) { if ( DstTy . getSizeInBits ( ) != <NUM_LIT> && ! Is64 ) return false ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( IdxReg ) ; unsigned Opc = Is64 ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & MI , DL , TII . get ( Opc ) , DstReg ) . addReg ( SrcReg , <NUM_LIT> , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) ; MI . eraseFromParent ( ) ; return true ; } if ( SrcRB -> getID ( ) != <STR_LIT> || DstTy . getSizeInBits ( ) != <NUM_LIT> ) return false ; if ( ! STI . useVGPRIndexMode ( ) ) { BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( IdxReg ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , RegState :: Undef , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) ; MI . eraseFromParent ( ) ;


<s> MachineBasicBlock * BB = I . getParent ( ) ; BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ; for ( Register Reg : { DstReg , Src0Reg , Src1Reg } ) MRI -> setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ;


<s> I . eraseFromParent ( ) ; for ( Register Reg : { DstReg , Src0Reg , Src1Reg } ) MRI -> setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ; return true ; } case <STR_LIT> : return selectInterpP1F16 ( I ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; default : return selectImpl ( I , * CoverageInfo ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return selectDSGW<ISA_LIT>ntrinsic ( I , IntrinsicID ) ; case <STR_LIT> : return selectDSAppendConsume ( I , true ) ; case <STR_LIT> : return selectDSAppendConsume ( I , false ) ; default : return selectImpl ( I , * CoverageInfo ) ; }


<s> Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI -> getType ( DstReg ) ; const LLT SrcTy = MRI -> getType ( SrcReg ) ; const LLT S1 = LLT :: scalar ( <NUM_LIT> ) ; const RegisterBank * SrcRB = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; const RegisterBank * DstRB ; if ( DstTy == S1 ) { DstRB = SrcRB ; } else { DstRB = RBI . getRegBank ( DstReg , * MRI , TRI ) ; if ( SrcRB != DstRB ) return false ; } const bool IsVALU = DstRB -> getID ( ) == <STR_LIT> ; unsigned DstSize = DstTy . getSizeInBits ( ) ; unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForSizeOnBank ( SrcSize , * SrcRB , * MRI ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForSizeOnBank ( DstSize , * DstRB , * MRI ) ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( DstTy == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) && SrcTy == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { MachineBasicBlock * MBB = I . getParent ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; Register LoReg = MRI -> createVirtualRegister ( DstRC ) ; Register HiReg = MRI -> createVirtualRegister ( DstRC ) ; BuildMI ( * MBB , I , DL , TII . get ( <STR_LIT> ) , LoReg ) . addReg ( SrcReg , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * MBB , I , DL , TII . get ( <STR_LIT> ) , HiReg ) . addReg ( SrcReg , <NUM_LIT> , <STR_LIT> ) ; if ( IsVALU && STI . hasSDWA ( ) ) { MachineInstr * MovSDWA = BuildMI ( * MBB , I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( HiReg ) . addImm ( <NUM_LIT> ) . addImm ( <STR_LIT> :: WORD_1 ) . addImm ( <STR_LIT> :: UNUSED_PRESERVE ) . addImm ( <STR_LIT> :: WORD_0 ) . addReg ( LoReg , RegState :: Implicit ) ; MovSDWA -> tieOperands ( <NUM_LIT> , MovSDWA -> getNumOperands ( ) - <NUM_LIT> ) ; } else { Register TmpReg0 = MRI -> createVirtualRegister ( DstRC ) ; Register TmpReg1 = MRI -> createVirtualRegister ( DstRC ) ; Register ImmReg = MRI -> createVirtualRegister ( DstRC ) ; if ( IsVALU ) {

BuildMI ( * MBB , I , DL , TII . get ( <STR_LIT> ) , TmpReg0 ) . addImm ( <NUM_LIT> ) . addReg ( HiReg ) ;


<s> Optional < uint64_t > OffsetVal = getConstantZext32Val ( Root . getReg ( ) , * MRI ) ; if ( ! OffsetVal ) return { } ;

Optional < int64_t > EncodedImm = <STR_LIT> ( STI , * OffsetVal ) ;


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectSMRDBufferImm ( MachineOperand & Root ) const { Optional < uint64_t > OffsetVal = getConstantZext32Val ( Root . getReg ( ) , * MRI ) ;


<s> unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( * EncodedImm ) ;


<s> if ( AddrInfo . empty ( ) || AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) != <NUM_LIT> ) return None ; const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; Optional < int64_t > EncodedImm = <STR_LIT> ( STI , GEPInfo . Imm ) ; if ( ! EncodedImm ) return None ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) {


<s> if ( AddrInfo . empty ( ) || AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) != <NUM_LIT> ) return None ; const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; Optional < int64_t > EncodedImm = <STR_LIT> ( STI , GEPInfo . Imm ) ; if ( ! EncodedImm ) return None ; return { {

[ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) {


<s> case <NUM_LIT> : return Signed ? <NUM_LIT> : <NUM_LIT> ; case <NUM_LIT> : return Signed ? <NUM_LIT> : <NUM_LIT> ; case <NUM_LIT> :


<s> switch ( Size ) { case <NUM_LIT> : return Signed ? <NUM_LIT> : <NUM_LIT> ; case <NUM_LIT> : return Signed ? <NUM_LIT> : <NUM_LIT> ; case <NUM_LIT> : return Signed ? <NUM_LIT> : <NUM_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> if ( ! TII . isLegalFLATOffset ( Offset . getValue ( ) , AddrSpace , Signed ) ) return Default ; Register BasePtr = OpDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( BasePtr ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset . getValue ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) {


<s> const TargetRegisterClass * RC = TRI . getBoolRC ( ) ; unsigned InstOpc = getLogicalBitOpcode ( I . getOpcode ( ) , RC == & <STR_LIT> ) ; I . setDesc ( TII . get ( InstOpc ) ) ; if ( Src0 . isUndef ( ) && ! MRI -> getRegClassOrNull ( Src0 . getReg ( ) ) ) MRI -> setRegClass ( Src0 . getReg ( ) , RC ) ; if ( Src1 . isUndef ( ) && ! MRI -> getRegClassOrNull ( Src1 . getReg ( ) ) ) MRI -> setRegClass ( Src1 . getReg ( ) , RC ) ; return RBI . constrainGenericRegister ( DstReg , * RC , * MRI ) ; } if ( DstRB -> getID ( ) == <STR_LIT> ) { unsigned InstOpc = getLogicalBitOpcode ( I . getOpcode ( ) , Size > <NUM_LIT> ) ;


<s> Register CondReg = CondOp . getReg ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; unsigned BrOpcode ; Register CondPhysReg ; const TargetRegisterClass * ConstrainRC ; if ( isSCC ( CondReg , * MRI ) ) { CondPhysReg = <STR_LIT> ; BrOpcode = <STR_LIT> ; ConstrainRC = & <STR_LIT> ; } else if ( isVCC ( CondReg , * MRI ) ) { CondPhysReg = TRI . getVCC ( ) ; BrOpcode = <STR_LIT> ; ConstrainRC = TRI . getBoolRC ( ) ; } else return false ; if ( ! MRI -> getRegClassOrNull ( CondReg ) ) MRI -> setRegClass ( CondReg , ConstrainRC ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , CondPhysReg ) . addReg ( CondReg ) ; BuildMI ( * BB , & I , DL , TII . get ( BrOpcode ) ) . addMBB ( I . getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; I . eraseFromParent ( ) ; return true ;


<s> Size = TRI . getRegSizeInBits ( * RC ) ; } if ( Size != <NUM_LIT> && Size != <NUM_LIT> ) return false ; unsigned Opcode = IsSgpr ? <STR_LIT> : <STR_LIT> ; if ( Size == <NUM_LIT> ) { I . setDesc ( TII . get ( Opcode ) ) ; I . addImplicitDefUseOperands ( * MF ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } const DebugLoc & DL = I . getDebugLoc ( ) ; APInt Imm ( Size , I . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; MachineInstr * ResInst ; if ( IsSgpr && TII . isInlineConstant ( Imm ) ) { ResInst = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( I . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; } else { const TargetRegisterClass * RC = IsSgpr ? & <STR_LIT> : & <STR_LIT> ; Register LoReg = MRI -> createVirtualRegister ( RC ) ; Register HiReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , LoReg ) . addImm ( Imm . trunc ( <NUM_LIT> ) . getZExtValue ( ) ) ; BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , HiReg ) . addImm ( Imm . ashr ( <NUM_LIT> ) . getZExtValue ( ) ) ; ResInst = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( LoReg ) . addImm ( <STR_LIT> ) . addReg ( HiReg ) . addImm ( <STR_LIT> ) ;


<s> Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ; for ( Register Reg : { DstReg , Src0Reg , Src1Reg } ) { if ( ! MRI -> getRegClassOrNull ( Reg ) ) MRI -> setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ; } return true ;


<s> MachineBasicBlock * BB = I . getParent ( ) ; BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ; for ( Register Reg : { DstReg , Src0Reg , Src1Reg } ) { if ( ! MRI -> getRegClassOrNull ( Reg ) ) MRI -> setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ; } return true ; } default :

return selectImpl ( I , * CoverageInfo ) ;


<s> bool <ISA_LIT>InstructionSelector :: selectG_<ISA_LIT>TOFP_UITOFP ( MachineInstr & I ) const { MachineBasicBlock * MBB = I . getParent ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; Register Src = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! isSCC ( Src , MRI ) ) return selectImpl ( I , * CoverageInfo ) ; bool Signed = I . getOpcode ( ) == <STR_LIT> ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ;

const LLT DstTy = MRI . getType ( DstReg ) ;


<s> bool Signed = I . getOpcode ( ) == <STR_LIT> ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType ( DstReg ) ; const unsigned DstSize = DstTy . getSizeInBits ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; BuildMI ( * MBB , I , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Src ) ; unsigned NewOpc = DstSize > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; auto MIB = BuildMI ( * MBB , I , DL , TII . get ( NewOpc ) , DstReg ) . addImm ( <NUM_LIT> ) . addImm ( getFPTrueImmVal ( DstSize , Signed ) ) ; if ( ! constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ) return false ; I . eraseFromParent ( ) ;