<s> } SDLoc SL ( N ) ; SDValue VCC = CurDAG -> getCopyToReg ( N -> getOperand ( <NUM_LIT> ) , SL , <STR_LIT> , Cond ) ; CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , VCC . getValue ( <NUM_LIT> ) ) ;


<s> } if ( isCBranchSCC ( N ) ) { SelectCode ( N ) ; return ; } SDLoc SL ( N ) ;

SDValue VCC = CurDAG -> getCopyToReg ( N -> getOperand ( <NUM_LIT> ) , SL , <STR_LIT> , Cond ) ;


<s> SDLoc DL ( Addr ) ; MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Rsrc = CurDAG -> getRegister ( Info -> getScratchRSrcReg ( ) , <STR_LIT> ) ; SOffset = CurDAG -> getRegister ( Info -> getScratchWaveOffsetReg ( ) , <STR_LIT> ) ; if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ;


<s> Offset = CurDAG -> getTargetConstant ( EncodedOffset , SL , <STR_LIT> ) ; Imm = true ; return true ; } if ( ! isUInt < <NUM_LIT> > ( EncodedOffset ) || ! isUInt < <NUM_LIT> > ( ByteOffset ) ) return false ; if ( Gen == <ISA_LIT>Subtarget :: SEA_ISLANDS && isUInt < <NUM_LIT> > ( EncodedOffset ) ) { Offset = CurDAG -> getTargetConstant ( EncodedOffset , SL , <STR_LIT> ) ; } else { SDValue C32Bit = CurDAG -> getTargetConstant ( ByteOffset , SL , <STR_LIT> ) ; Offset = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , C32Bit ) , <NUM_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: isConstantLoad ( const MemSDNode * N , int CbId ) const {

if ( ! N -> readMem ( ) ) return false ;


<s> if ( ! N -> readMem ( ) ) return false ; if ( CbId == - <NUM_LIT> ) return N -> getAddressSpace ( ) == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS || N -> getAddressSpace ( ) == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS_32BIT ; return N -> getAddressSpace ( ) == AMDGPUA<ISA_LIT> . CONSTANT_BUFFER_0 + CbId ;


<s> switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned NumVectorElts = VT . getVectorNumElements ( ) ; unsigned RegClassID ; switch ( NumVectorElts ) { case <NUM_LIT> : RegClassID = <STR_LIT> ; break ; case <NUM_LIT> : if ( Opc == <STR_LIT> ) RegClassID = <STR_LIT> ; else RegClassID = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> case <NUM_LIT> : RegClassID = <STR_LIT> ; break ; case <NUM_LIT> : if ( Opc == <STR_LIT> ) RegClassID = <STR_LIT> ; else RegClassID = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } SelectBuildVector ( N , RegClassID ) ; return ;


<s> if ( ( C = dyn_cast < ConstantSDNode > ( Addr ) ) ) { Base = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( C -> getZExtValue ( ) , DL , <STR_LIT> ) ; } else if ( ( Addr . getOpcode ( ) == <STR_LIT> ) && ( C = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) ) { Base = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( C -> getZExtValue ( ) , DL , <STR_LIT> ) ; } else if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) && ( C = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( C -> getZExtValue ( ) , DL , <STR_LIT> ) ;


<s> Offset = CurDAG -> getTargetConstant ( C -> getZExtValue ( ) , DL , <STR_LIT> ) ; } else if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) && ( C = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) ) { Base = Addr . getOperand ( <NUM_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectADDRVTX_READ ( SDValue Addr , SDValue & Base , SDValue & Offset ) { ConstantSDNode * IMMOffset ; if ( Addr . getOpcode ( ) == <STR_LIT> && ( IMMOffset = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && isInt < <NUM_LIT> > ( IMMOffset -> getZExtValue ( ) ) ) { Base = Addr . getOperand ( <NUM_LIT> ) ;

Offset = CurDAG -> getTargetConstant ( IMMOffset -> getZExtValue ( ) , SDLoc ( Addr ) , <STR_LIT> ) ;


<s> SDValue Sub0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Sub1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDNode * Lo0 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , LHS , Sub0 ) ; SDNode * Hi0 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , LHS , Sub1 ) ; SDNode * Lo1 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , RHS , Sub0 ) ; SDNode * Hi1 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , RHS , Sub1 ) ; SDVTList VTList = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; unsigned Opc = IsAdd ? <STR_LIT> : <STR_LIT> ; unsigned CarryOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; SDNode * AddLo ; if ( ! ConsumeCarry ) { SDValue Args [ ] = { SDValue ( Lo0 , <NUM_LIT> ) , SDValue ( Lo1 , <NUM_LIT> ) } ;

AddLo = CurDAG -> getMachineNode ( Opc , DL , VTList , Args ) ;


<s> break ; } RegSeqArgs [ <NUM_LIT> + ( <NUM_LIT> * i ) ] = N -> getOperand ( i ) ; RegSeqArgs [ <NUM_LIT> + ( <NUM_LIT> * i ) + <NUM_LIT> ] = CurDAG -> getTargetConstant ( TRI -> getSubRegFromChannel ( i ) , DL , <STR_LIT> ) ; } if ( NOps != NumVectorElts ) { assert ( N -> getOpcode ( ) == <STR_LIT> && NOps < NumVectorElts ) ; MachineSDNode * ImpDef = CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , DL , EltVT ) ; for ( unsigned i = NOps ; i < NumVectorElts ; ++ i ) {

RegSeqArgs [ <NUM_LIT> + ( <NUM_LIT> * i ) ] = SDValue ( ImpDef , <NUM_LIT> ) ;


<s> unsigned Src0Mods , Src1Mods , Src2Mods ; bool Sel0 = SelectVOP3PMadMixModsImpl ( Src0 , Src0 , Src0Mods ) ; bool Sel1 = SelectVOP3PMadMixModsImpl ( Src1 , Src1 , Src1Mods ) ; bool Sel2 = SelectVOP3PMadMixModsImpl ( Src2 , Src2 , Src2Mods ) ; assert ( ! Subtarget -> hasFP32Denormals ( ) && <STR_LIT> ) ; if ( Sel0 || Sel1 || Sel2 ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { CurDAG -> getTargetConstant ( Src0Mods , SDLoc ( ) , <STR_LIT> ) , Src0 , CurDAG -> getTargetConstant ( Src1Mods , SDLoc ( ) , <STR_LIT> ) , Src1 , CurDAG -> getTargetConstant ( Src2Mods , SDLoc ( ) , <STR_LIT> ) , Src2 , CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( ) , <STR_LIT> ) , Zero , Zero } ; CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops ) ; } else { SelectCode ( N ) ; }


<s> SDValue Src1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Src2 = N -> getOperand ( <NUM_LIT> ) ; unsigned Src0Mods , Src1Mods , Src2Mods ; bool Sel0 = SelectVOP3PMadMixModsImpl ( Src0 , Src0 , Src0Mods ) ; bool Sel1 = SelectVOP3PMadMixModsImpl ( Src1 , Src1 , Src1Mods ) ; bool Sel2 = SelectVOP3PMadMixModsImpl ( Src2 , Src2 , Src2Mods ) ; assert ( ! Subtarget -> hasFP32Denormals ( ) && <STR_LIT> ) ; if ( Sel0 || Sel1 || Sel2 ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { CurDAG -> getTargetConstant ( Src0Mods , SDLoc ( ) , <STR_LIT> ) , Src0 , CurDAG -> getTargetConstant ( Src1Mods , SDLoc ( ) , <STR_LIT> ) , Src1 , CurDAG -> getTargetConstant ( Src2Mods , SDLoc ( ) , <STR_LIT> ) , Src2 , CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( ) , <STR_LIT> ) , Zero , Zero } ;

CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops ) ;


<s> SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( N0 . getOpcode ( ) == <STR_LIT> ) { SDValue N2 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N3 = N0 . getOperand ( <NUM_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = N2 ; VAddr = N3 ; } else { VAddr = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = N0 ; } if ( <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( C1 -> getZExtValue ( ) ) ) { Offset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ; return true ; } if ( isUInt < <NUM_LIT> > ( C1 -> getZExtValue ( ) ) ) { Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SOffset = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; return true ; } } if ( Addr . getOpcode ( ) == <STR_LIT> ) {

SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( TargetMachine * TM = nullptr , CodeGenOpt :: Level OptLevel = CodeGenOpt :: Default ) : SelectionDAGISel ( * TM , OptLevel ) {

EnableLateStructurizeCFG = <ISA_LIT>TargetMachine :: EnableLateStructurizeCFG ;


<s> explicit <ISA_LIT>DAGToDAGISel ( TargetMachine * TM = nullptr , CodeGenOpt :: Level OptLevel = CodeGenOpt :: Default ) : SelectionDAGISel ( * TM , OptLevel ) { EnableLateStructurizeCFG = <ISA_LIT>TargetMachine :: EnableLateStructurizeCFG ;


<s> AU . addRequired < <ISA_LIT>PerfHintAnalysis > ( ) ; AU . addRequired < LegacyDivergenceAnalysis > ( ) ;

SelectionDAGISel :: getAnalysisUsage ( AU ) ;


<s> if ( cast < MemSDNode > ( N ) -> getAddressSpace ( ) != <ISA_LIT>AS :: LOCAL_ADDRESS || ! Subtarget -> ldsRequiresM0Init ( ) ) return N ; const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; SDValue M0 = Lowering . copyToM0 ( * CurDAG , CurDAG -> getEntryNode ( ) , SDLoc ( N ) , CurDAG -> getTargetConstant ( - <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ) ; SDValue Glue = M0 . getValue ( <NUM_LIT> ) ;

SmallVector < SDValue , <NUM_LIT> > Ops ;


<s> explicit <ISA_LIT>DAGToDAGISel ( TargetMachine * TM , CodeGenOpt :: Level OptLevel ) :

<ISA_LIT>DAGToDAGISel ( TM , OptLevel ) {


<s> SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { CmpVal , VAddr , SRsrc , SOffset , Offset , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SDValue SRsrc , SOffset , Offset , SLC ; if ( SelectMUBUFOffset ( Mem -> getBasePtr ( ) , SRsrc , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { CmpVal , SRsrc , SOffset , Offset , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) {


<s> if ( ( Addr . getValueType ( ) != <STR_LIT> || Addr -> getFlags ( ) . hasNoUnsignedWrap ( ) ) && CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; if ( SelectSMRDOffset ( N1 , Offset , Imm ) ) { SBase = Expand32BitAddress ( N0 ) ; return true ;


<s> } MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; bool Is32 = ( VT == <STR_LIT> ) ; SDLoc SL ( N ) ; MachineSDNode * CmpSwap = nullptr ; if ( Subtarget -> hasAddr64 ( ) ) { SDValue SRsrc , VAddr , SOffset , Offset , SLC ; if ( SelectMUBUFAddr64 ( Mem -> getBasePtr ( ) , SRsrc , VAddr , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { CmpVal , VAddr , SRsrc , SOffset , Offset , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SDValue SRsrc , SOffset , Offset , SLC ; if ( SelectMUBUFOffset ( Mem -> getBasePtr ( ) , SRsrc , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { CmpVal , SRsrc , SOffset , Offset , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; }


<s> SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { CmpVal , VAddr , SRsrc , SOffset , Offset , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SDValue SRsrc , SOffset , Offset , SLC ; if ( SelectMUBUFOffset ( Mem -> getBasePtr ( ) , SRsrc , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { CmpVal , SRsrc , SOffset , Offset , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; }


<s> return false ; } } const Value * MemVal = N -> getMemOperand ( ) -> getValue ( ) ; return ! checkType ( MemVal , <ISA_LIT>AS :: LOCAL_ADDRESS ) && ! checkType ( MemVal , <ISA_LIT>AS :: GLOBAL_ADDRESS ) && ! checkType ( MemVal , <ISA_LIT>AS :: FLAT_ADDRESS ) && ! checkType ( MemVal , <ISA_LIT>AS :: REGION_ADDRESS ) && ! checkType ( MemVal , <ISA_LIT>AS :: CONSTANT_ADDRESS ) && ! checkType ( MemVal , <ISA_LIT>AS :: PARAM_D_ADDRESS ) && ! checkType ( MemVal , <ISA_LIT>AS :: PARAM_I_ADDRESS ) ;


<s> const BasicBlock * BB = FuncInfo -> MBB -> getBasicBlock ( ) ;

return BB -> getTerminator ( ) -> getMetadata ( <STR_LIT> ) ;


<s> if ( SrcSize > DestSize ) { assert ( SrcSize == <NUM_LIT> && DestSize == <NUM_LIT> ) ; return CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , DestVT , Src , CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) ; } if ( DestSize > SrcSize ) { assert ( SrcSize == <NUM_LIT> && DestSize == <NUM_LIT> ) ; SDValue RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; const SDValue Ops [ ] = { RC , Src , CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ; } assert ( SrcSize == <NUM_LIT> && DestSize == <NUM_LIT> ) ; return CurDAG -> getNode ( <STR_LIT> , DL , DestVT , Src ) . getNode ( ) ;


<s> assert ( Subtarget -> hasFlatAddressSpace ( ) && <STR_LIT> ) ; assert ( ( ASC -> getSrcAddressSpace ( ) == <ISA_LIT>AS :: FLAT_ADDRESS || ASC -> getDestAddressSpace ( ) == <ISA_LIT>AS :: FLAT_ADDRESS ) && <STR_LIT> ) ; SDValue Src = ASC -> getOperand ( <NUM_LIT> ) ; EVT DestVT = ASC -> getValueType ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; unsigned SrcSize = SrcVT . getSizeInBits ( ) ; unsigned DestSize = DestVT . getSizeInBits ( ) ; if ( SrcSize > DestSize ) { assert ( SrcSize == <NUM_LIT> && DestSize == <NUM_LIT> ) ; return CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , DestVT , Src , CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) ;


<s> SDNode * MaskedCond = CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) , Cond ) ;

SDValue VCC = CurDAG -> getCopyToReg ( N -> getOperand ( <NUM_LIT> ) , SL , <STR_LIT> , SDValue ( MaskedCond , <NUM_LIT> ) , SDValue ( ) ) ;


<s> const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Rsrc = CurDAG -> getRegister ( Info -> getScratchRSrcReg ( ) , <STR_LIT> ) ; SOffset = CurDAG -> getRegister ( Info -> getScratchWaveOffsetReg ( ) , <STR_LIT> ) ; if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ;

SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ;


<s> const MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( auto FI = dyn_cast < FrameIndexSDNode > ( N ) ) { SDValue TFI = CurDAG -> getTargetFrameIndex ( FI -> getIndex ( ) , FI -> getValueType ( <NUM_LIT> ) ) ;

return std :: make_pair ( TFI , CurDAG -> getRegister ( Info -> getStackPtrOffsetReg ( ) , <STR_LIT> ) ) ;


<s> std :: pair < SDValue , SDValue > <ISA_LIT>DAGToDAGISel :: foldFrameIndex ( SDValue N ) const { SDLoc DL ( N ) ; const MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( auto FI = dyn_cast < FrameIndexSDNode > ( N ) ) { SDValue TFI = CurDAG -> getTargetFrameIndex ( FI -> getIndex ( ) , FI -> getValueType ( <NUM_LIT> ) ) ; return std :: make_pair ( TFI , CurDAG -> getRegister ( Info -> getStackPtrOffsetReg ( ) , <STR_LIT> ) ) ; }

return std :: make_pair ( N , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> Subtarget = & MF . getSubtarget < GCNSubtarget > ( ) ; Mode = <STR_LIT> ( MF . getFunction ( ) ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> bool IsAdd = Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; SDValue Sub0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Sub1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDNode * Lo0 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , LHS , Sub0 ) ; SDNode * Hi0 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , LHS , Sub1 ) ; SDNode * Lo1 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , RHS , Sub0 ) ; SDNode * Hi1 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , RHS , Sub1 ) ; SDVTList VTList = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; static const unsigned OpcMap [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } } ; unsigned Opc = OpcMap [ <NUM_LIT> ] [ N -> isDivergent ( ) ] [ IsAdd ] ; unsigned CarryOpc = OpcMap [ <NUM_LIT> ] [ N -> isDivergent ( ) ] [ IsAdd ] ; SDNode * AddLo ; if ( ! ConsumeCarry ) { SDValue Args [ ] = { SDValue ( Lo0 , <NUM_LIT> ) , SDValue ( Lo1 , <NUM_LIT> ) } ; AddLo = CurDAG -> getMachineNode ( Opc , DL , VTList , Args ) ; } else { SDValue Args [ ] = { SDValue ( Lo0 , <NUM_LIT> ) , SDValue ( Lo1 , <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; AddLo = CurDAG -> getMachineNode ( CarryOpc , DL , VTList , Args ) ; } SDValue AddHiArgs [ ] = { SDValue ( Hi0 , <NUM_LIT> ) , SDValue ( Hi1 , <NUM_LIT> ) , SDValue ( AddLo , <NUM_LIT> ) } ; SDNode * AddHi = CurDAG -> getMachineNode ( CarryOpc , DL , VTList , AddHiArgs ) ;


<s> bool ProduceCarry = ConsumeCarry || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; bool IsAdd = Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; SDValue Sub0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Sub1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDNode * Lo0 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , LHS , Sub0 ) ; SDNode * Hi0 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , LHS , Sub1 ) ; SDNode * Lo1 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , RHS , Sub0 ) ; SDNode * Hi1 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , RHS , Sub1 ) ; SDVTList VTList = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; static const unsigned OpcMap [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } } ; unsigned Opc = OpcMap [ <NUM_LIT> ] [ N -> isDivergent ( ) ] [ IsAdd ] ; unsigned CarryOpc = OpcMap [ <NUM_LIT> ] [ N -> isDivergent ( ) ] [ IsAdd ] ; SDNode * AddLo ; if ( ! ConsumeCarry ) { SDValue Args [ ] = { SDValue ( Lo0 , <NUM_LIT> ) , SDValue ( Lo1 , <NUM_LIT> ) } ; AddLo = CurDAG -> getMachineNode ( Opc , DL , VTList , Args ) ;


<s> } const GCNSubtarget * ST = static_cast < const GCNSubtarget * > ( Subtarget ) ; const <ISA_LIT>RegisterInfo * TRI = ST -> getRegisterInfo ( ) ; bool UseSCCBr = isCBranchSCC ( N ) && isUniformBr ( N ) ; unsigned BrOp = UseSCCBr ? <STR_LIT> : <STR_LIT> ; Register CondReg = UseSCCBr ? <STR_LIT> : TRI -> getVCC ( ) ; SDLoc SL ( N ) ; if ( ! UseSCCBr ) {

Cond = SDValue ( CurDAG -> getMachineNode ( ST -> isWave32 ( ) ? <STR_LIT> : <STR_LIT> , SL , <STR_LIT> , CurDAG -> getRegister ( ST -> isWave32 ( ) ? <STR_LIT> : <STR_LIT> , <STR_LIT> ) , Cond ) , <NUM_LIT> ) ;


<s> bool UseSCCBr = isCBranchSCC ( N ) && isUniformBr ( N ) ; unsigned BrOp = UseSCCBr ? <STR_LIT> : <STR_LIT> ; Register CondReg = UseSCCBr ? <STR_LIT> : TRI -> getVCC ( ) ; SDLoc SL ( N ) ; if ( ! UseSCCBr ) { Cond = SDValue ( CurDAG -> getMachineNode ( ST -> isWave32 ( ) ? <STR_LIT> : <STR_LIT> , SL , <STR_LIT> , CurDAG -> getRegister ( ST -> isWave32 ( ) ? <STR_LIT> : <STR_LIT> , <STR_LIT> ) , Cond ) , <NUM_LIT> ) ; }

SDValue VCC = CurDAG -> getCopyToReg ( N -> getOperand ( <NUM_LIT> ) , SL , CondReg , Cond ) ;


<s> MachineSDNode * MovHighBits = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , HighBits ) ; VAddr = SDValue ( MovHighBits , <NUM_LIT> ) ; const MachinePointerInfo & PtrInfo = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) ; SOffset = isStackPtrRelative ( PtrInfo ) ? CurDAG -> getRegister ( Info -> getStackPtrOffsetReg ( ) , <STR_LIT> ) : CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ImmOffset = CurDAG -> getTargetConstant ( Imm & <NUM_LIT> , DL , <STR_LIT> ) ; return true ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( C1 -> getZExtValue ( ) ) && ( ! Subtarget -> privateMemoryResourceIsRangeChecked ( ) || CurDAG -> SignBitIsZero ( N0 ) ) ) { std :: tie ( VAddr , SOffset ) = foldFrameIndex ( N0 ) ;

ImmOffset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ;


<s> return true ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( C1 -> getZExtValue ( ) ) && ( ! Subtarget -> privateMemoryResourceIsRangeChecked ( ) || CurDAG -> SignBitIsZero ( N0 ) ) ) { std :: tie ( VAddr , SOffset ) = foldFrameIndex ( N0 ) ; ImmOffset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ; return true ;


<s> const MachinePointerInfo & PtrInfo = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) ; SOffset = isStackPtrRelative ( PtrInfo ) ? CurDAG -> getRegister ( Info -> getStackPtrOffsetReg ( ) , <STR_LIT> ) : CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ;

Offset = CurDAG -> getTargetConstant ( CAddr -> getZExtValue ( ) , DL , <STR_LIT> ) ;


<s> MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SRsrc = CurDAG -> getRegister ( Info -> getScratchRSrcReg ( ) , <STR_LIT> ) ; const MachinePointerInfo & PtrInfo = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) ; SOffset = isStackPtrRelative ( PtrInfo ) ? CurDAG -> getRegister ( Info -> getStackPtrOffsetReg ( ) , <STR_LIT> ) : CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CAddr -> getZExtValue ( ) , DL , <STR_LIT> ) ;


<s> if ( auto Imm = <STR_LIT> ( * Subtarget , C -> getZExtValue ( ) , true ) ) {

Offset = CurDAG -> getTargetConstant ( * Imm , SDLoc ( Addr ) , <STR_LIT> ) ;


<s> Offset = ByteOffsetNode ; Imm = false ; return true ; } if ( ByteOffsetNode . getOpcode ( ) == <STR_LIT> ) { if ( ByteOffsetNode . getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> ) { Offset = ByteOffsetNode . getOperand ( <NUM_LIT> ) ; Imm = false ; return true ; } } return false ; } SDLoc SL ( ByteOffsetNode ) ; int64_t ByteOffset = C -> getSExtValue ( ) ; Optional < int64_t > EncodedOffset = <STR_LIT> ( * Subtarget , ByteOffset , false ) ; if ( EncodedOffset ) { Offset = CurDAG -> getTargetConstant ( * EncodedOffset , SL , <STR_LIT> ) ; Imm = true ; return true ; } if ( ByteOffset < <NUM_LIT> ) return false ; EncodedOffset = <STR_LIT> ( * Subtarget , ByteOffset ) ; if ( EncodedOffset ) { Offset = CurDAG -> getTargetConstant ( * EncodedOffset , SL , <STR_LIT> ) ; return true ; } if ( ! isUInt < <NUM_LIT> > ( ByteOffset ) && ! isInt < <NUM_LIT> > ( ByteOffset ) ) return false ; SDValue C32Bit = CurDAG -> getTargetConstant ( ByteOffset , SL , <STR_LIT> ) ;

Offset = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , C32Bit ) , <NUM_LIT> ) ;


<s> if ( ByteOffsetNode . getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> ) { Offset = ByteOffsetNode . getOperand ( <NUM_LIT> ) ; Imm = false ; return true ; } } return false ; } SDLoc SL ( ByteOffsetNode ) ; int64_t ByteOffset = C -> getSExtValue ( ) ; Optional < int64_t > EncodedOffset = <STR_LIT> ( * Subtarget , ByteOffset , false ) ; if ( EncodedOffset ) { Offset = CurDAG -> getTargetConstant ( * EncodedOffset , SL , <STR_LIT> ) ; Imm = true ; return true ; } if ( ByteOffset < <NUM_LIT> ) return false ; EncodedOffset = <STR_LIT> ( * Subtarget , ByteOffset ) ; if ( EncodedOffset ) { Offset = CurDAG -> getTargetConstant ( * EncodedOffset , SL , <STR_LIT> ) ; return true ; } if ( ! isUInt < <NUM_LIT> > ( ByteOffset ) && ! isInt < <NUM_LIT> > ( ByteOffset ) ) return false ; SDValue C32Bit = CurDAG -> getTargetConstant ( ByteOffset , SL , <STR_LIT> ) ; Offset = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , C32Bit ) , <NUM_LIT> ) ;


<s> LoopInfo * LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; for ( auto & L : LI -> getLoopsInPreorder ( ) ) { assert ( L -> isLCSSAForm ( DT ) ) ; } Subtarget = & MF . getSubtarget < GCNSubtarget > ( ) ;

return SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> for ( auto & L : LI -> getLoopsInPreorder ( ) ) { assert ( L -> isLCSSAForm ( DT ) ) ; } Subtarget = & MF . getSubtarget < GCNSubtarget > ( ) ;


<s> MemIntrinsicSDNode * M = cast < MemIntrinsicSDNode > ( N ) ; MachineMemOperand * MMO = M -> getMemOperand ( ) ; if ( ConstantSDNode * ConstOffset = dyn_cast < ConstantSDNode > ( BaseOffset ) ) { glueCopyToM0 ( N , CurDAG -> getTargetConstant ( - <NUM_LIT> , SL , <STR_LIT> ) ) ; ImmOffset = ConstOffset -> getZExtValue ( ) + <NUM_LIT> ; } else { if ( CurDAG -> isBaseWithConstantOffset ( BaseOffset ) ) { ImmOffset = BaseOffset . getConstantOperandVal ( <NUM_LIT> ) ; BaseOffset = BaseOffset . getOperand ( <NUM_LIT> ) ; } SDNode * SGPROffset = CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , BaseOffset ) ; SDNode * M0Base = CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , SDValue ( SGPROffset , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; glueCopyToM0 ( N , SDValue ( M0Base , <NUM_LIT> ) ) ; } SDValue V0 ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Glue ; if ( HasVSrc ) { SDValue VSrc0 = N -> getOperand ( <NUM_LIT> ) ; V0 = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue CopyToV0 = CurDAG -> getCopyToReg ( N -> getOperand ( <NUM_LIT> ) , SL , V0 , VSrc0 , N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ) ; Chain = CopyToV0 ; Glue = CopyToV0 . getValue ( <NUM_LIT> ) ; } SDValue OffsetField = CurDAG -> getTargetConstant ( ImmOffset , SL , <STR_LIT> ) ; SDValue GDS = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; const unsigned Opc = gwsIntrinToOpcode ( IntrID ) ;


<s> ConstantSDNode * C = cast < ConstantSDNode > ( Addr64 ) ; if ( C -> getSExtValue ( ) ) { SDLoc DL ( Addr ) ; const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; SRsrc = SDValue ( Lowering . wrapAddr64Rsrc ( * CurDAG , DL , Ptr ) , <NUM_LIT> ) ; return true ; }


<s> bool <ISA_LIT>DAGToDAGISel :: isConstantLoad ( const MemSDNode * N , int CbId ) const { if ( ! N -> readMem ( ) ) return false ; if ( CbId == - <NUM_LIT> ) return N -> getAddressSpace ( ) == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS ; return N -> getAddressSpace ( ) == AMDGPUA<ISA_LIT> . CONSTANT_BUFFER_0 + CbId ;


<s> <ISA_LIT>DAGToDAGISel :: <ISA_LIT>DAGToDAGISel ( TargetMachine * TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( * TM , OptLevel ) {


<s> SDValue TFI = FI ? CurDAG -> getTargetFrameIndex ( FI -> getIndex ( ) , FI -> getValueType ( <NUM_LIT> ) ) : N ; return std :: make_pair ( TFI , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> AU . addRequired < LoopInfoWrapperPass > ( ) ; SelectionDAGISel :: getAnalysisUsage ( AU ) ;


<s> void <ISA_LIT>DAGToDAGISel :: getAnalysisUsage ( AnalysisUsage & AU ) const {

AU . addRequired < <ISA_LIT>ArgumentUsageInfo > ( ) ;


<s> SDValue BaseLo = Lo . getOperand ( <NUM_LIT> ) ; SDValue BaseHi = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( BaseLo . getOpcode ( ) == <STR_LIT> && BaseHi . getOpcode ( ) == <STR_LIT> && BaseLo . getOperand ( <NUM_LIT> ) == BaseHi . getOperand ( <NUM_LIT> ) && isa < ConstantSDNode > ( BaseLo . getOperand ( <NUM_LIT> ) ) && BaseLo . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> && isa < ConstantSDNode > ( BaseHi . getOperand ( <NUM_LIT> ) ) && BaseHi . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> ) { N0 = BaseLo . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; N1 = Lo . getOperand ( <NUM_LIT> ) ; return true ; } } }


<s> unsigned Opcode = IsSigned ? <STR_LIT> : <STR_LIT> ; uint32_t PackedVal = Offset | ( Width << <NUM_LIT> ) ; SDValue PackedConst = CurDAG -> getTargetConstant ( PackedVal , DL , <STR_LIT> ) ; return CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , Val , PackedConst ) ;


<s> return TRI -> getPhysRegClass ( Reg ) ; } return nullptr ; } switch ( N -> getMachineOpcode ( ) ) { default : { const MCInstrDesc & Desc = Subtarget -> getInstrInfo ( ) -> get ( N -> getMachineOpcode ( ) ) ; unsigned OpIdx = Desc . getNumDefs ( ) + OpNo ; if ( OpIdx >= Desc . getNumOperands ( ) ) return nullptr ; int RegClass = Desc . OpInfo [ OpIdx ] . RegClass ; if ( RegClass == - <NUM_LIT> ) return nullptr ; return Subtarget -> getRegisterInfo ( ) -> getRegClass ( RegClass ) ; } case <STR_LIT> : {

unsigned RCID = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;


<s> return MRI . getRegClass ( Reg ) ; } const <ISA_LIT>RegisterInfo * TRI = static_cast < const GCNSubtarget * > ( Subtarget ) -> getRegisterInfo ( ) ; return TRI -> getPhysRegClass ( Reg ) ; } return nullptr ; } switch ( N -> getMachineOpcode ( ) ) { default : { const MCInstrDesc & Desc = Subtarget -> getInstrInfo ( ) -> get ( N -> getMachineOpcode ( ) ) ; unsigned OpIdx = Desc . getNumDefs ( ) + OpNo ; if ( OpIdx >= Desc . getNumOperands ( ) ) return nullptr ;

int RegClass = Desc . OpInfo [ OpIdx ] . RegClass ;


<s> RHS = Addr . getOperand ( <NUM_LIT> ) ; return true ; }

if ( getBaseWithOffsetUsingSplitOR ( * CurDAG , Addr , LHS , RHS ) ) {


<s> auto RC = TRI . getPhysRegClass ( cast < RegisterSDNode > ( Val . getOperand ( <NUM_LIT> ) ) -> getReg ( ) ) ; return RC && TRI . isSGPRClass ( RC ) ;


<s> if ( Offset0 % Size != <NUM_LIT> || Offset1 % Size != <NUM_LIT> ) return false ;

if ( ! isUInt < <NUM_LIT> > ( Offset0 / Size ) || ! isUInt < <NUM_LIT> > ( Offset1 / Size ) ) return false ;


<s> bool <ISA_LIT>DAGToDAGISel :: isDSOffsetLegal ( SDValue Base , unsigned Offset ) const { if ( ! isUInt < <NUM_LIT> > ( Offset ) ) return false ;

if ( ! Base || Subtarget -> hasUsableDSOffset ( ) || Subtarget -> unsafeDSOffsetFoldingEnabled ( ) ) return true ;


<s> if ( ! Base || Subtarget -> hasUsableDSOffset ( ) || Subtarget -> unsafeDSOffsetFoldingEnabled ( ) ) return true ;

return CurDAG -> SignBitIsZero ( Base ) ;


<s> } } if ( In . getOpcode ( ) != <STR_LIT> ) return false ; SDValue Srl = In . getOperand ( <NUM_LIT> ) ; if ( Srl . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * ShiftAmt = dyn_cast < ConstantSDNode > ( Srl . getOperand ( <NUM_LIT> ) ) ) { if ( ShiftAmt -> getZExtValue ( ) == <NUM_LIT> ) { Out = stripBitcast ( Srl . getOperand ( <NUM_LIT> ) ) ; return true ; }


<s> Out = In . getOperand ( <NUM_LIT> ) ; return true ; } } if ( In . getOpcode ( ) != <STR_LIT> ) return false ; SDValue Srl = In . getOperand ( <NUM_LIT> ) ; if ( Srl . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * ShiftAmt = dyn_cast < ConstantSDNode > ( Srl . getOperand ( <NUM_LIT> ) ) ) { if ( ShiftAmt -> getZExtValue ( ) == <NUM_LIT> ) {

Out = stripBitcast ( Srl . getOperand ( <NUM_LIT> ) ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: isNoNanSrc ( SDValue N ) const { if ( TM . Options . NoNaNsFPMath ) return true ;

if ( N -> getFlags ( ) . hasNoNaNs ( ) ) return true ;


<s> auto Ld = cast < LoadSDNode > ( N ) ; return Ld -> getAlignment ( ) >= <NUM_LIT> && ( ( ( Ld -> getAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS || Ld -> getAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) && ! N -> isDivergent ( ) ) || ( Subtarget -> getScalarizeGlobalBehavior ( ) && Ld -> getAddressSpace ( ) == <ISA_LIT>AS :: GLOBAL_ADDRESS && Ld -> isSimple ( ) && ! N -> isDivergent ( ) && static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) -> isMemOpHasNoClobberedMemOperand ( N ) ) ) ;


<s> static SDValue matchZExtFromI32 ( SDValue Op ) { if ( Op . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue ExtSrc = Op . getOperand ( <NUM_LIT> ) ; return ( ExtSrc . getValueType ( ) == <STR_LIT> ) ? ExtSrc : SDValue ( ) ;


<s> if ( N -> isDivergent ( ) ) { unsigned Opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; CurDAG -> SelectNodeTo ( N , Opc , N -> getVTList ( ) , { LHS , RHS , CI , CurDAG -> getTargetConstant ( <NUM_LIT> , { } , <STR_LIT> ) } ) ; } else { unsigned Opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; CurDAG -> SelectNodeTo ( N , Opc , N -> getVTList ( ) , { LHS , RHS , CI } ) ; }


<s> SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; SDValue CI = N -> getOperand ( <NUM_LIT> ) ; if ( N -> isDivergent ( ) ) { unsigned Opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; CurDAG -> SelectNodeTo ( N , Opc , N -> getVTList ( ) , { LHS , RHS , CI , CurDAG -> getTargetConstant ( <NUM_LIT> , { } , <STR_LIT> ) } ) ; } else { unsigned Opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; CurDAG -> SelectNodeTo ( N , Opc , N -> getVTList ( ) , { LHS , RHS , CI } ) ; }


<s> SDLoc DL ( N ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; unsigned Opcode = N -> getOpcode ( ) ; bool ConsumeCarry = ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; bool ProduceCarry = ConsumeCarry || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; bool IsAdd = Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; SDValue Sub0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Sub1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDNode * Lo0 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , LHS , Sub0 ) ; SDNode * Hi0 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , LHS , Sub1 ) ; SDNode * Lo1 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , RHS , Sub0 ) ; SDNode * Hi1 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , RHS , Sub1 ) ; SDVTList VTList = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; static const unsigned OpcMap [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } } ; unsigned Opc = OpcMap [ <NUM_LIT> ] [ N -> isDivergent ( ) ] [ IsAdd ] ;

unsigned CarryOpc = OpcMap [ <NUM_LIT> ] [ N -> isDivergent ( ) ] [ IsAdd ] ;


<s> SDVTList VTList = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; static const unsigned OpcMap [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } } ; unsigned Opc = OpcMap [ <NUM_LIT> ] [ N -> isDivergent ( ) ] [ IsAdd ] ; unsigned CarryOpc = OpcMap [ <NUM_LIT> ] [ N -> isDivergent ( ) ] [ IsAdd ] ; SDNode * AddLo ; if ( ! ConsumeCarry ) { SDValue Args [ ] = { SDValue ( Lo0 , <NUM_LIT> ) , SDValue ( Lo1 , <NUM_LIT> ) } ; AddLo = CurDAG -> getMachineNode ( Opc , DL , VTList , Args ) ; } else { SDValue Args [ ] = { SDValue ( Lo0 , <NUM_LIT> ) , SDValue ( Lo1 , <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; AddLo = CurDAG -> getMachineNode ( CarryOpc , DL , VTList , Args ) ;


<s> SDLoc SL ( N ) ; MachineSDNode * CmpSwap = nullptr ; if ( Subtarget -> hasAddr64 ( ) ) { SDValue SRsrc , VAddr , SOffset , Offset ; if ( SelectMUBUFAddr64 ( Mem -> getBasePtr ( ) , SRsrc , VAddr , SOffset , Offset ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue CPol = CurDAG -> getTargetConstant ( <STR_LIT> :: GLC , SL , <STR_LIT> ) ; SDValue Ops [ ] = { CmpVal , VAddr , SRsrc , SOffset , Offset , CPol , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SDValue SRsrc , SOffset , Offset ; if ( SelectMUBUFOffset ( Mem -> getBasePtr ( ) , SRsrc , SOffset , Offset ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue CPol = CurDAG -> getTargetConstant ( <STR_LIT> :: GLC , SL , <STR_LIT> ) ; SDValue Ops [ ] = { CmpVal , SRsrc , SOffset , Offset , CPol , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SelectCode ( N ) ; return ; } MachineMemOperand * MMO = Mem -> getMemOperand ( ) ; CurDAG -> setNodeMemRefs ( CmpSwap , { MMO } ) ; unsigned SubReg = Is32 ? <STR_LIT> : <STR_LIT> ;

SDValue Extract = CurDAG -> getTargetExtractSubreg ( SubReg , SL , VT , SDValue ( CmpSwap , <NUM_LIT> ) ) ;


<s> void <ISA_LIT>DAGToDAGISel :: SelectDIV_SCALE ( SDNode * N ) { SDLoc SL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( VT == <STR_LIT> || VT == <STR_LIT> ) ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ <NUM_LIT> ] ; SelectVOP3BMods0 ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ;

SelectVOP3BMods ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ;


<s> SmallVector < SDValue , <NUM_LIT> > Opnds ; Opnds . push_back ( Zero ) ; Opnds . push_back ( Addr . getOperand ( <NUM_LIT> ) ) ; unsigned SubOp = <STR_LIT> ; if ( Subtarget -> hasAddNoCarry ( ) ) { SubOp = <STR_LIT> ; Opnds . push_back ( CurDAG -> getTargetConstant ( <NUM_LIT> , { } , <STR_LIT> ) ) ; } MachineSDNode * MachineSub = CurDAG -> getMachineNode ( SubOp , DL , <STR_LIT> , Opnds ) ; Base = SDValue ( MachineSub , <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( ByteOffset , DL , <STR_LIT> ) ; return true ; } } } } else if ( const ConstantSDNode * CAddr = dyn_cast < ConstantSDNode > ( Addr ) ) { SDLoc DL ( Addr ) ; if ( isDSOffsetLegal ( SDValue ( ) , CAddr -> getZExtValue ( ) ) ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; MachineSDNode * MovZero = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Zero ) ; Base = SDValue ( MovZero , <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CAddr -> getZExtValue ( ) , DL , <STR_LIT> ) ; return true ; } }


<s> bool <ISA_LIT>DAGToDAGISel :: SelectDS64Bit4ByteAligned ( SDValue Addr , SDValue & Base , SDValue & Offset0 , SDValue & Offset1 ) const {

return SelectDSReadWrite2 ( Addr , Base , Offset0 , Offset1 , <NUM_LIT> ) ;


<s> void <ISA_LIT>DAGToDAGISel :: SelectDSAppendConsume ( SDNode * N , unsigned IntrID ) { unsigned Opc = IntrID == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Ptr = N -> getOperand ( <NUM_LIT> ) ; MemIntrinsicSDNode * M = cast < MemIntrinsicSDNode > ( N ) ; MachineMemOperand * MMO = M -> getMemOperand ( ) ; bool IsGDS = M -> getAddressSpace ( ) == <ISA_LIT>AS :: REGION_ADDRESS ; SDValue Offset ; if ( CurDAG -> isBaseWithConstantOffset ( Ptr ) ) { SDValue PtrBase = Ptr . getOperand ( <NUM_LIT> ) ; SDValue PtrOffset = Ptr . getOperand ( <NUM_LIT> ) ; const APInt & OffsetVal = cast < ConstantSDNode > ( PtrOffset ) -> getAPIntValue ( ) ; if ( isDSOffsetLegal ( PtrBase , OffsetVal . getZExtValue ( ) ) ) { N = glueCopyToM0 ( N , PtrBase ) ; Offset = CurDAG -> getTargetConstant ( OffsetVal , SDLoc ( ) , <STR_LIT> ) ; } } if ( ! Offset ) {


<s> N = glueCopyToM0 ( N , Ptr ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( ) , <STR_LIT> ) ; } SDValue Ops [ ] = { Offset , CurDAG -> getTargetConstant ( IsGDS , SDLoc ( ) , <STR_LIT> ) , Chain , N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) } ; SDNode * Selected = CurDAG -> SelectNodeTo ( N , Opc , N -> getVTList ( ) , Ops ) ; CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( Selected ) , { MMO } ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectDSReadWrite2 ( SDValue Addr , SDValue & Base , SDValue & Offset0 , SDValue & Offset1 , unsigned Size ) const { SDLoc DL ( Addr ) ; if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; unsigned OffsetValue0 = C1 -> getZExtValue ( ) ; unsigned OffsetValue1 = OffsetValue0 + Size ; if ( isDSOffset2Legal ( N0 , OffsetValue0 , OffsetValue1 , Size ) ) { Base = N0 ; Offset0 = CurDAG -> getTargetConstant ( OffsetValue0 / Size , DL , <STR_LIT> ) ; Offset1 = CurDAG -> getTargetConstant ( OffsetValue1 / Size , DL , <STR_LIT> ) ; return true ; } } else if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { unsigned OffsetValue0 = C -> getZExtValue ( ) ; unsigned OffsetValue1 = OffsetValue0 + Size ; if ( isDSOffset2Legal ( SDValue ( ) , OffsetValue0 , OffsetValue1 , Size ) ) { SDLoc DL ( Addr ) ;

SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ;


<s> return ; } const bool HasVSrc = N -> getNumOperands ( ) == <NUM_LIT> ; assert ( HasVSrc || N -> getNumOperands ( ) == <NUM_LIT> ) ; SDLoc SL ( N ) ; SDValue BaseOffset = N -> getOperand ( HasVSrc ? <NUM_LIT> : <NUM_LIT> ) ; int ImmOffset = <NUM_LIT> ; MemIntrinsicSDNode * M = cast < MemIntrinsicSDNode > ( N ) ; MachineMemOperand * MMO = M -> getMemOperand ( ) ; if ( ConstantSDNode * ConstOffset = dyn_cast < ConstantSDNode > ( BaseOffset ) ) { glueCopyToM0 ( N , CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; ImmOffset = ConstOffset -> getZExtValue ( ) ; } else {

if ( CurDAG -> isBaseWithConstantOffset ( BaseOffset ) ) {


<s> BaseOffset = BaseOffset . getOperand ( <NUM_LIT> ) ; } SDNode * SGPROffset = CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , BaseOffset ) ; SDNode * M0Base = CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , SDValue ( SGPROffset , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; glueCopyToM0 ( N , SDValue ( M0Base , <NUM_LIT> ) ) ; } SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue OffsetField = CurDAG -> getTargetConstant ( ImmOffset , SL , <STR_LIT> ) ; const unsigned Opc = gwsIntrinToOpcode ( IntrID ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( HasVSrc ) Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( OffsetField ) ; Ops . push_back ( Chain ) ;

SDNode * Selected = CurDAG -> SelectNodeTo ( N , Opc , N -> getVTList ( ) , Ops ) ;


<s> Opnds . push_back ( N0 ) ; Opnds . push_back ( AddOffsetLo ) ; unsigned AddOp = <STR_LIT> ; if ( Subtarget -> hasAddNoCarry ( ) ) { AddOp = <STR_LIT> ; Opnds . push_back ( Clamp ) ; } Addr = SDValue ( CurDAG -> getMachineNode ( AddOp , DL , <STR_LIT> , Opnds ) , <NUM_LIT> ) ; } else { SDValue Sub0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Sub1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDNode * N0Lo = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , N0 , Sub0 ) ; SDNode * N0Hi = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , N0 , Sub1 ) ; SDValue AddOffsetHi = getMaterializedScalarImm32 ( Hi_32 ( RemainderOffset ) , DL ) ; SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; SDNode * Add = CurDAG -> getMachineNode ( <STR_LIT> , DL , VTs , { AddOffsetLo , SDValue ( N0Lo , <NUM_LIT> ) , Clamp } ) ; SDNode * Addc = CurDAG -> getMachineNode ( <STR_LIT> , DL , VTs , { AddOffsetHi , SDValue ( N0Hi , <NUM_LIT> ) , SDValue ( Add , <NUM_LIT> ) , Clamp } ) ; SDValue RegSequenceArgs [ ] = { CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , SDValue ( Add , <NUM_LIT> ) , Sub0 , SDValue ( Addc , <NUM_LIT> ) , Sub1 } ; Addr = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , RegSequenceArgs ) , <NUM_LIT> ) ; } }


<s> bool UseFMAC = Subtarget -> hasDLInsts ( ) && cast < ConstantSDNode > ( Ops [ <NUM_LIT> ] ) -> isZero ( ) && cast < ConstantSDNode > ( Ops [ <NUM_LIT> ] ) -> isZero ( ) && cast < ConstantSDNode > ( Ops [ <NUM_LIT> ] ) -> isZero ( ) ; unsigned Opcode = UseFMAC ? <STR_LIT> : <STR_LIT> ;

CurDAG -> SelectNodeTo ( N , Opcode , N -> getVTList ( ) , Ops ) ;


<s> SDLoc SL ( N ) ; SDValue Ops [ <NUM_LIT> ] ; SelectVOP3Mods0 ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; SelectVOP3Mods ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; SelectVOP3Mods ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; Ops [ <NUM_LIT> ] = N -> getOperand ( <NUM_LIT> ) ; Ops [ <NUM_LIT> ] = N -> getOperand ( <NUM_LIT> ) ;

bool UseFMAC = Subtarget -> hasDLInsts ( ) && cast < ConstantSDNode > ( Ops [ <NUM_LIT> ] ) -> isZero ( ) && cast < ConstantSDNode > ( Ops [ <NUM_LIT> ] ) -> isZero ( ) && cast < ConstantSDNode > ( Ops [ <NUM_LIT> ] ) -> isZero ( ) ;


<s> return SelectFlatOffsetImpl ( N , Addr , VAddr , Offset , <STR_LIT> ) ;


<s> unsigned Opc = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Clamp = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Clamp } ;

CurDAG -> SelectNodeTo ( N , Opc , N -> getVTList ( ) , Ops ) ;


<s> bool Signed = N -> getOpcode ( ) == <STR_LIT> ; unsigned Opc = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Clamp = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Clamp } ;


<s> SDLoc DL ( Index ) ; if ( CurDAG -> isBaseWithConstantOffset ( Index ) ) { SDValue N0 = Index . getOperand ( <NUM_LIT> ) ; SDValue N1 = Index . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( C1 -> getSExtValue ( ) <= <NUM_LIT> || CurDAG -> SignBitIsZero ( N0 ) || ( Index -> getOpcode ( ) == <STR_LIT> && C1 -> getSExtValue ( ) >= <NUM_LIT> ) ) { Base = N0 ; Offset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ; return true ; } } if ( isa < ConstantSDNode > ( Index ) ) return false ;


<s> SDLoc DL ( Addr ) ; const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; SRsrc = SDValue ( Lowering . wrapAddr64Rsrc ( * CurDAG , DL , Ptr ) , <NUM_LIT> ) ; return true ; } return false ;


<s> if ( ! SelectMUBUF ( Addr , Ptr , VAddr , SOffset , Offset , Offen , Idxen , Addr64 ) ) return false ; if ( ! cast < ConstantSDNode > ( Offen ) -> getSExtValue ( ) && ! cast < ConstantSDNode > ( Idxen ) -> getSExtValue ( ) && ! cast < ConstantSDNode > ( Addr64 ) -> getSExtValue ( ) ) { uint64_t Rsrc = TII -> getDefaultRsrcDataFormat ( ) | APInt :: getAllOnes ( <NUM_LIT> ) . getZExtValue ( ) ; SDLoc DL ( Addr ) ; const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; SRsrc = SDValue ( Lowering . buildRSRC ( * CurDAG , DL , Ptr , <NUM_LIT> , Rsrc ) , <NUM_LIT> ) ; return true ; }


<s> SDValue HighBits = CurDAG -> getTargetConstant ( Imm & ~ <NUM_LIT> , DL , <STR_LIT> ) ; MachineSDNode * MovHighBits = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , HighBits ) ; VAddr = SDValue ( MovHighBits , <NUM_LIT> ) ; SOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ImmOffset = CurDAG -> getTargetConstant ( Imm & <NUM_LIT> , DL , <STR_LIT> ) ; return true ; } } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( C1 -> getZExtValue ( ) ) && ( ! Subtarget -> privateMemoryResourceIsRangeChecked ( ) || CurDAG -> SignBitIsZero ( N0 ) ) ) { std :: tie ( VAddr , SOffset ) = foldFrameIndex ( N0 ) ; ImmOffset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ; return true ; } } std :: tie ( VAddr , SOffset ) = foldFrameIndex ( Addr ) ;

ImmOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ;


<s> MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Rsrc = CurDAG -> getRegister ( Info -> getScratchRSrcReg ( ) , <STR_LIT> ) ; if ( ConstantSDNode * CAddr = dyn_cast < ConstantSDNode > ( Addr ) ) { int64_t Imm = CAddr -> getSExtValue ( ) ; const int64_t NullPtr = <ISA_LIT>TargetMachine :: getNullPointerValue ( <ISA_LIT>AS :: PRIVATE_ADDRESS ) ; if ( Imm != NullPtr ) { SDValue HighBits = CurDAG -> getTargetConstant ( Imm & ~ <NUM_LIT> , DL , <STR_LIT> ) ; MachineSDNode * MovHighBits = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , HighBits ) ; VAddr = SDValue ( MovHighBits , <NUM_LIT> ) ; SOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ImmOffset = CurDAG -> getTargetConstant ( Imm & <NUM_LIT> , DL , <STR_LIT> ) ; return true ;


<s> ConstantSDNode * CAddr ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { CAddr = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( ! CAddr || ! <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( CAddr -> getZExtValue ( ) ) ) return false ; if ( ! IsCopyFromSGPR ( * TRI , Addr . getOperand ( <NUM_LIT> ) ) ) return false ; SOffset = Addr . getOperand ( <NUM_LIT> ) ; } else if ( ( CAddr = dyn_cast < ConstantSDNode > ( Addr ) ) && <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( CAddr -> getZExtValue ( ) ) ) { SOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } else { return false ; }

SRsrc = CurDAG -> getRegister ( Info -> getScratchRSrcReg ( ) , <STR_LIT> ) ;


<s> CAddr = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( ! CAddr || ! <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( CAddr -> getZExtValue ( ) ) ) return false ; if ( ! IsCopyFromSGPR ( * TRI , Addr . getOperand ( <NUM_LIT> ) ) ) return false ; SOffset = Addr . getOperand ( <NUM_LIT> ) ; } else if ( ( CAddr = dyn_cast < ConstantSDNode > ( Addr ) ) && <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( CAddr -> getZExtValue ( ) ) ) { SOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } else { return false ; } SRsrc = CurDAG -> getRegister ( Info -> getScratchRSrcReg ( ) , <STR_LIT> ) ;

Offset = CurDAG -> getTargetConstant ( CAddr -> getZExtValue ( ) , DL , <STR_LIT> ) ;


<s> } else if ( SAddr . getOpcode ( ) == <STR_LIT> && isa < FrameIndexSDNode > ( SAddr . getOperand ( <NUM_LIT> ) ) ) { auto FI = cast < FrameIndexSDNode > ( SAddr . getOperand ( <NUM_LIT> ) ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI -> getIndex ( ) , FI -> getValueType ( <NUM_LIT> ) ) ; SAddr = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( SAddr ) , <STR_LIT> , TFI , SAddr . getOperand ( <NUM_LIT> ) ) , <NUM_LIT> ) ; } return SAddr ;


<s> int64_t SplitImmOffset , RemainderOffset ; std :: tie ( SplitImmOffset , RemainderOffset ) = TII -> splitFlatOffset ( COffsetVal , <ISA_LIT>AS :: PRIVATE_ADDRESS , <STR_LIT> ) ; COffsetVal = SplitImmOffset ; SDValue AddOffset = SAddr . getOpcode ( ) == <STR_LIT> ? getMaterializedScalarImm32 ( Lo_32 ( RemainderOffset ) , DL ) : CurDAG -> getTargetConstant ( RemainderOffset , DL , <STR_LIT> ) ; SAddr = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , SAddr , AddOffset ) , <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( COffsetVal , DL , <STR_LIT> ) ; return true ;


<s> if ( CurDAG -> isBaseWithConstantOffset ( Addr ) || Addr . getOpcode ( ) == <STR_LIT> ) { N0 = Addr . getOperand ( <NUM_LIT> ) ; N1 = Addr . getOperand ( <NUM_LIT> ) ; } else if ( getBaseWithOffsetUsingSplitOR ( * CurDAG , Addr , N0 , N1 ) ) { assert ( N0 && N1 && isa < ConstantSDNode > ( N1 ) ) ; } if ( N0 && N1 ) { if ( SelectSMRDOffset ( N1 , Offset , Imm ) ) { SBase = Expand32BitAddress ( N0 ) ; return true ; } } }


<s> break ; case <STR_LIT> : if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { const SDValue & And = N -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * Shift = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * Mask = dyn_cast < ConstantSDNode > ( And -> getOperand ( <NUM_LIT> ) ) ; if ( Shift && Mask ) { uint32_t ShiftVal = Shift -> getZExtValue ( ) ; uint32_t MaskVal = Mask -> getZExtValue ( ) >> ShiftVal ; if ( isMask_32 ( MaskVal ) ) { uint32_t WidthVal = countPopulation ( MaskVal ) ; ReplaceNode ( N , getBFE32 ( false , SDLoc ( N ) , And . getOperand ( <NUM_LIT> ) , ShiftVal , WidthVal ) ) ; return ; } } } else if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SelectS_BFEFromShifts ( N ) ; return ;


<s> uint32_t BVal = B -> getZExtValue ( ) ; uint32_t CVal = C -> getZExtValue ( ) ; if ( <NUM_LIT> < BVal && BVal <= CVal && CVal < <NUM_LIT> ) { bool Signed = N -> getOpcode ( ) == <STR_LIT> ; ReplaceNode ( N , getBFE32 ( Signed , SDLoc ( N ) , Shl . getOperand ( <NUM_LIT> ) , CVal - BVal , <NUM_LIT> - CVal ) ) ; return ; }


<s> CurDAG -> SelectNodeTo ( N , Opc , N -> getVTList ( ) , { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , { } , <STR_LIT> ) } ) ; } else { unsigned Opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; CurDAG -> SelectNodeTo ( N , Opc , N -> getVTList ( ) , { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ) ;


<s> bool IsAdd = N -> getOpcode ( ) == <STR_LIT> ; bool IsVALU = N -> isDivergent ( ) ; for ( SDNode :: use_iterator UI = N -> use_begin ( ) , E = N -> use_end ( ) ; UI != E ; ++ UI ) if ( UI . getUse ( ) . getResNo ( ) == <NUM_LIT> ) { if ( ( IsAdd && ( UI -> getOpcode ( ) != <STR_LIT> ) ) || ( ! IsAdd && ( UI -> getOpcode ( ) != <STR_LIT> ) ) ) { IsVALU = true ; break ; } } if ( IsVALU ) { unsigned Opc = IsAdd ? <STR_LIT> : <STR_LIT> ; CurDAG -> SelectNodeTo ( N , Opc , N -> getVTList ( ) , { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , { } , <STR_LIT> ) } ) ; } else { unsigned Opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; CurDAG -> SelectNodeTo ( N , Opc , N -> getVTList ( ) , { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ) ;


<s> if ( SelectVOP3ModsImpl ( In , Src , Mods , false ) ) { SrcMods = CurDAG -> getTargetConstant ( Mods , SDLoc ( In ) , <STR_LIT> ) ; return true ; } return false ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectVOP3BMods ( SDValue In , SDValue & Src , SDValue & SrcMods ) const { unsigned Mods ; if ( SelectVOP3ModsImpl ( In , Src , Mods , false ) ) { SrcMods = CurDAG -> getTargetConstant ( Mods , SDLoc ( In ) , <STR_LIT> ) ; return true ; }


<s> bool <ISA_LIT>DAGToDAGISel :: SelectVOP3BMods0 ( SDValue In , SDValue & Src , SDValue & SrcMods , SDValue & Clamp , SDValue & Omod ) const { SDLoc DL ( In ) ; Clamp = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Omod = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; return SelectVOP3BMods ( In , Src , SrcMods ) ;


<s> Clamp = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ;

Omod = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ;


<s> if ( AllowAbs && Src . getOpcode ( ) == <STR_LIT> ) { Mods |= <STR_LIT> ; Src = Src . getOperand ( <NUM_LIT> ) ; }


<s> Mods = <NUM_LIT> ; Src = In ; if ( Src . getOpcode ( ) == <STR_LIT> ) { Mods |= <STR_LIT> ; Src = Src . getOperand ( <NUM_LIT> ) ; }

if ( AllowAbs && Src . getOpcode ( ) == <STR_LIT> ) {


<s> Mods ^= <STR_LIT> ; } if ( isExtractHiElt ( Lo , Lo ) ) Mods |= <STR_LIT> ; if ( isExtractHiElt ( Hi , Hi ) ) Mods |= <STR_LIT> ; unsigned VecSize = Src . getValueSizeInBits ( ) ; Lo = stripExtractLoElt ( Lo ) ; Hi = stripExtractLoElt ( Hi ) ; if ( Lo . getValueSizeInBits ( ) > VecSize ) { Lo = CurDAG -> getTargetExtractSubreg ( ( VecSize > <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> , SDLoc ( In ) , <STR_LIT> ( VecSize ) , Lo ) ; } if ( Hi . getValueSizeInBits ( ) > VecSize ) { Hi = CurDAG -> getTargetExtractSubreg ( ( VecSize > <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> , SDLoc ( In ) , <STR_LIT> ( VecSize ) , Hi ) ; } assert ( Lo . getValueSizeInBits ( ) <= VecSize && Hi . getValueSizeInBits ( ) <= VecSize ) ; if ( Lo == Hi && ! isInlineImmediate ( Lo . getNode ( ) ) ) { if ( VecSize == <NUM_LIT> || VecSize == Lo . getValueSizeInBits ( ) ) { Src = Lo ; } else { assert ( Lo . getValueSizeInBits ( ) == <NUM_LIT> && VecSize == <NUM_LIT> ) ; SDLoc SL ( In ) ; SDValue Undef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , SL , Lo . getValueType ( ) ) , <NUM_LIT> ) ; auto RC = Lo -> isDivergent ( ) ? <STR_LIT> : <STR_LIT> ; const SDValue Ops [ ] = {

CurDAG -> getTargetConstant ( RC , SL , <STR_LIT> ) , Lo , CurDAG -> getTargetConstant ( <STR_LIT> , SL , <STR_LIT> ) , Undef , CurDAG -> getTargetConstant ( <STR_LIT> , SL , <STR_LIT> ) } ;


<s> Lo = stripBitcast ( Lo . getOperand ( <NUM_LIT> ) ) ; Mods ^= <STR_LIT> ; } if ( Hi . getOpcode ( ) == <STR_LIT> ) { Hi = stripBitcast ( Hi . getOperand ( <NUM_LIT> ) ) ; Mods ^= <STR_LIT> ; } if ( isExtractHiElt ( Lo , Lo ) ) Mods |= <STR_LIT> ; if ( isExtractHiElt ( Hi , Hi ) ) Mods |= <STR_LIT> ; unsigned VecSize = Src . getValueSizeInBits ( ) ; Lo = stripExtractLoElt ( Lo ) ; Hi = stripExtractLoElt ( Hi ) ; if ( Lo . getValueSizeInBits ( ) > VecSize ) { Lo = CurDAG -> getTargetExtractSubreg ( ( VecSize > <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> , SDLoc ( In ) , <STR_LIT> ( VecSize ) , Lo ) ; } if ( Hi . getValueSizeInBits ( ) > VecSize ) { Hi = CurDAG -> getTargetExtractSubreg ( ( VecSize > <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> , SDLoc ( In ) , <STR_LIT> ( VecSize ) , Hi ) ; } assert ( Lo . getValueSizeInBits ( ) <= VecSize && Hi . getValueSizeInBits ( ) <= VecSize ) ; if ( Lo == Hi && ! isInlineImmediate ( Lo . getNode ( ) ) ) { if ( VecSize == <NUM_LIT> || VecSize == Lo . getValueSizeInBits ( ) ) { Src = Lo ; } else { assert ( Lo . getValueSizeInBits ( ) == <NUM_LIT> && VecSize == <NUM_LIT> ) ; SDLoc SL ( In ) ; SDValue Undef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , SL , Lo . getValueType ( ) ) , <NUM_LIT> ) ; auto RC = Lo -> isDivergent ( ) ? <STR_LIT> : <STR_LIT> ; const SDValue Ops [ ] = { CurDAG -> getTargetConstant ( RC , SL , <STR_LIT> ) , Lo , CurDAG -> getTargetConstant ( <STR_LIT> , SL , <STR_LIT> ) , Undef , CurDAG -> getTargetConstant ( <STR_LIT> , SL , <STR_LIT> ) } ; Src = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , SL , Src . getValueType ( ) , Ops ) , <NUM_LIT> ) ; } SrcMods = CurDAG -> getTargetConstant ( Mods , SDLoc ( In ) , <STR_LIT> ) ; return true ; } if ( VecSize == <NUM_LIT> && Lo == Hi && isa < ConstantFPSDNode > ( Lo ) ) { uint64_t Lit = cast < ConstantFPSDNode > ( Lo ) -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ;

if ( <STR_LIT> ( Lit , Subtarget -> hasInv2PiInlineImm ( ) ) ) {


<s> if ( In . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * Idx = dyn_cast < ConstantSDNode > ( In . getOperand ( <NUM_LIT> ) ) ) { if ( Idx -> isZero ( ) && In . getValueSizeInBits ( ) <= <NUM_LIT> ) return In . getOperand ( <NUM_LIT> ) ; } } if ( In . getOpcode ( ) == <STR_LIT> ) { SDValue Src = In . getOperand ( <NUM_LIT> ) ; if ( Src . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> ) return stripBitcast ( Src ) ; } return In ;


<s> if ( ConstantSDNode * Idx = dyn_cast < ConstantSDNode > ( In . getOperand ( <NUM_LIT> ) ) ) {

if ( Idx -> isZero ( ) && In . getValueSizeInBits ( ) <= <NUM_LIT> ) return In . getOperand ( <NUM_LIT> ) ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectAddrSpaceCast ( SDNode * N ) { AddrSpaceCastSDNode * ASC = cast < AddrSpaceCastSDNode > ( N ) ; SDLoc DL ( N ) ; assert ( Subtarget -> hasFlatAddressSpace ( ) && <STR_LIT> ) ; assert ( ( ASC -> getSrcAddressSpace ( ) != <ISA_LIT>AS :: CONSTANT_ADDRESS && ASC -> getDestAddressSpace ( ) != <ISA_LIT>AS :: CONSTANT_ADDRESS ) && <STR_LIT> ) ; assert ( ( ASC -> getSrcAddressSpace ( ) == <ISA_LIT>AS :: FLAT_ADDRESS || ASC -> getDestAddressSpace ( ) == <ISA_LIT>AS :: FLAT_ADDRESS ) && <STR_LIT> ) ; SDValue Src = ASC -> getOperand ( <NUM_LIT> ) ; EVT DestVT = ASC -> getValueType ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; unsigned SrcSize = SrcVT . getSizeInBits ( ) ; unsigned DestSize = DestVT . getSizeInBits ( ) ; if ( SrcSize > DestSize ) { assert ( SrcSize == <NUM_LIT> && DestSize == <NUM_LIT> ) ; return CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , DestVT , Src , CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) ; } if ( DestSize > SrcSize ) { assert ( SrcSize == <NUM_LIT> && DestSize == <NUM_LIT> ) ; SDValue RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; const SDValue Ops [ ] = { RC , Src , CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ; } assert ( SrcSize == <NUM_LIT> && DestSize == <NUM_LIT> ) ; return CurDAG -> getNode ( <STR_LIT> , DL , DestVT , Src ) . getNode ( ) ;


<s> if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( N0 . getOpcode ( ) == <STR_LIT> ) { SDValue N2 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N3 = N0 . getOperand ( <NUM_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = N2 ; VAddr = N3 ; } else { VAddr = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = N0 ; } if ( isLegalMUBUFImmOffset ( C1 ) ) { Offset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ; return ; } else if ( isUInt < <NUM_LIT> > ( C1 -> getZExtValue ( ) ) ) { Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SOffset = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; return ; } } if ( Addr . getOpcode ( ) == <STR_LIT> ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ;


<s> GLC = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SLC = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; TFE = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Idxen = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Offen = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( N0 . getOpcode ( ) == <STR_LIT> ) { SDValue N2 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N3 = N0 . getOperand ( <NUM_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = N2 ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectMUBUFAddr64 ( SDValue Addr , SDValue & SRsrc , SDValue & VAddr , SDValue & SOffset , SDValue & Offset , SDValue & GLC , SDValue & SLC , SDValue & TFE ) const { SDValue Ptr , Offen , Idxen , Addr64 ;

if ( Subtarget -> getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) return false ;


<s> SDLoc DL ( Addr ) ; const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; SRsrc = SDValue ( Lowering . wrapAddr64Rsrc ( * CurDAG , DL , Ptr ) , <NUM_LIT> ) ; return true ; } return false ;


<s> SelectMUBUF ( Addr , Ptr , VAddr , SOffset , Offset , Offen , Idxen , Addr64 , GLC , SLC , TFE ) ;

if ( ! cast < ConstantSDNode > ( Offen ) -> getSExtValue ( ) && ! cast < ConstantSDNode > ( Idxen ) -> getSExtValue ( ) && ! cast < ConstantSDNode > ( Addr64 ) -> getSExtValue ( ) ) {


<s> uint64_t Rsrc = TII -> getDefaultRsrcDataFormat ( ) | APInt :: getAllOnesValue ( <NUM_LIT> ) . getZExtValue ( ) ; SDLoc DL ( Addr ) ; const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ;

SRsrc = SDValue ( Lowering . buildRSRC ( * CurDAG , DL , Ptr , <NUM_LIT> , Rsrc ) , <NUM_LIT> ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( TargetMachine * TM = nullptr , CodeGenOpt :: Level OptLevel = CodeGenOpt :: Default ) : SelectionDAGISel ( * TM , OptLevel ) { AMDGPUA<ISA_LIT> = <STR_LIT> ( * TM ) ;


<s> SDValue M0 = Lowering . copyToM0 ( * CurDAG , CurDAG -> getEntryNode ( ) , SDLoc ( N ) , CurDAG -> getTargetConstant ( - <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ) ; SDValue Glue = M0 . getValue ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { Ops . push_back ( N -> getOperand ( i ) ) ; } Ops . push_back ( Glue ) ; CurDAG -> MorphNodeTo ( N , N -> getOpcode ( ) , N -> getVTList ( ) , Ops ) ;


<s> SDValue Glue = M0 . getValue ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { Ops . push_back ( N -> getOperand ( i ) ) ; }


<s> CmpVal , VAddr , SRsrc , SOffset , Offset , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SDValue SRsrc , SOffset , Offset , SLC ; if ( SelectMUBUFOffset ( Mem -> getBasePtr ( ) , SRsrc , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { CmpVal , SRsrc , SOffset , Offset , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SelectCode ( N ) ; return ; } MachineSDNode :: mmo_iterator MMOs = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; * MMOs = Mem -> getMemOperand ( ) ; CmpSwap -> setMemRefs ( MMOs , MMOs + <NUM_LIT> ) ; unsigned SubReg = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue Extract = CurDAG -> getTargetExtractSubreg ( SubReg , SL , VT , SDValue ( CmpSwap , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , Extract ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( CmpSwap , <NUM_LIT> ) ) ;


<s> SelectCode ( N ) ; return ; } MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; bool Is32 = ( VT == <STR_LIT> ) ; SDLoc SL ( N ) ; MachineSDNode * CmpSwap = nullptr ; if ( Subtarget -> hasAddr64 ( ) ) { SDValue SRsrc , VAddr , SOffset , Offset , GLC , SLC ; if ( SelectMUBUFAddr64 ( Mem -> getBasePtr ( ) , SRsrc , VAddr , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { CmpVal , VAddr , SRsrc , SOffset , Offset , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SDValue SRsrc , SOffset , Offset , SLC ; if ( SelectMUBUFOffset ( Mem -> getBasePtr ( ) , SRsrc , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { CmpVal , SRsrc , SOffset , Offset , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SelectCode ( N ) ; return ; } MachineSDNode :: mmo_iterator MMOs = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; * MMOs = Mem -> getMemOperand ( ) ; CmpSwap -> setMemRefs ( MMOs , MMOs + <NUM_LIT> ) ; unsigned SubReg = Is32 ? <STR_LIT> : <STR_LIT> ;

SDValue Extract = CurDAG -> getTargetExtractSubreg ( SubReg , SL , VT , SDValue ( CmpSwap , <NUM_LIT> ) ) ;


<s> unsigned Imm = CAddr -> getZExtValue ( ) ; assert ( ! isLegalMUBUFImmOffset ( Imm ) && <STR_LIT> ) ; SDValue HighBits = CurDAG -> getTargetConstant ( Imm & ~ <NUM_LIT> , DL , <STR_LIT> ) ; MachineSDNode * MovHighBits = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , HighBits ) ; VAddr = SDValue ( MovHighBits , <NUM_LIT> ) ; const MachinePointerInfo & PtrInfo = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) ; unsigned SOffsetReg = isStackPtrRelative ( PtrInfo ) ? Info -> getStackPtrOffsetReg ( ) : Info -> getScratchWaveOffsetReg ( ) ; SOffset = CurDAG -> getRegister ( SOffsetReg , <STR_LIT> ) ; ImmOffset = CurDAG -> getTargetConstant ( Imm & <NUM_LIT> , DL , <STR_LIT> ) ; return true ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ;

ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ;


<s> ConstantSDNode * CAddr = dyn_cast < ConstantSDNode > ( Addr ) ; if ( ! CAddr || ! isLegalMUBUFImmOffset ( CAddr ) ) return false ; SDLoc DL ( Addr ) ; MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SRsrc = CurDAG -> getRegister ( Info -> getScratchRSrcReg ( ) , <STR_LIT> ) ; const MachinePointerInfo & PtrInfo = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) ; unsigned SOffsetReg = isStackPtrRelative ( PtrInfo ) ? Info -> getStackPtrOffsetReg ( ) : Info -> getScratchWaveOffsetReg ( ) ; SOffset = CurDAG -> getRegister ( SOffsetReg , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CAddr -> getZExtValue ( ) , DL , <STR_LIT> ) ; return true ;


<s> SDLoc DL ( Addr ) ; MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SRsrc = CurDAG -> getRegister ( Info -> getScratchRSrcReg ( ) , <STR_LIT> ) ; const MachinePointerInfo & PtrInfo = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) ; unsigned SOffsetReg = isStackPtrRelative ( PtrInfo ) ? Info -> getStackPtrOffsetReg ( ) : Info -> getScratchWaveOffsetReg ( ) ; SOffset = CurDAG -> getRegister ( SOffsetReg , <STR_LIT> ) ;


<s> Mods = <NUM_LIT> ; SelectVOP3ModsImpl ( In , Src , Mods ) ; if ( Src . getOpcode ( ) == <STR_LIT> ) {


<s> assert ( Src . getValueType ( ) == <STR_LIT> ) ; Src = stripBitcast ( Src ) ; Mods |= <STR_LIT> ; if ( isExtractHiElt ( Src , Src ) ) Mods |= <STR_LIT> ; return true ; }


<s> explicit <ISA_LIT>DAGToDAGISel ( TargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) { AMDGPUA<ISA_LIT> = <STR_LIT> ( TM ) ;


<s> const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; SDValue M0 = Lowering . copyToM0 ( * CurDAG , CurDAG -> getEntryNode ( ) , SDLoc ( N ) , CurDAG -> getTargetConstant ( - <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ) ;

SDValue Glue = M0 . getValue ( <NUM_LIT> ) ;


<s> MemSDNode * Mem = cast < MemSDNode > ( N ) ; unsigned AS = Mem -> getAddressSpace ( ) ; if ( AS == AMDGPUA<ISA_LIT> . FLAT_ADDRESS ) { SelectCode ( N ) ; return ; } MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; bool Is32 = ( VT == <STR_LIT> ) ; SDLoc SL ( N ) ; MachineSDNode * CmpSwap = nullptr ; if ( Subtarget -> hasAddr64 ( ) ) { SDValue SRsrc , VAddr , SOffset , Offset , GLC , SLC ; if ( SelectMUBUFAddr64 ( Mem -> getBasePtr ( ) , SRsrc , VAddr , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { CmpVal , VAddr , SRsrc , SOffset , Offset , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; }


<s> MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SRsrc = CurDAG -> getRegister ( Info -> getScratchRSrcReg ( ) , <STR_LIT> ) ;

SOffset = CurDAG -> getRegister ( Info -> getScratchWaveOffsetReg ( ) , <STR_LIT> ) ;


<s> MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SRsrc = CurDAG -> getRegister ( Info -> getScratchRSrcReg ( ) , <STR_LIT> ) ; SOffset = CurDAG -> getRegister ( Info -> getScratchWaveOffsetReg ( ) , <STR_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectVOP3OMods ( SDValue In , SDValue & Src , SDValue & Clamp , SDValue & Omod ) const { Src = In ; SDLoc DL ( In ) ; Clamp = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectVOP3OMods ( SDValue In , SDValue & Src , SDValue & Clamp , SDValue & Omod ) const {


<s> Src = Src . getOperand ( <NUM_LIT> ) ; } Mods |= <STR_LIT> ; SrcMods = CurDAG -> getTargetConstant ( Mods , SDLoc ( In ) , <STR_LIT> ) ; return true ;


<s> AU . addRequired < <ISA_LIT>ArgumentUsageInfo > ( ) ;

AU . addRequired < DivergenceAnalysis > ( ) ;


<s> AU . addRequired < <ISA_LIT>ArgumentUsageInfo > ( ) ; AU . addRequired < DivergenceAnalysis > ( ) ; SelectionDAGISel :: getAnalysisUsage ( AU ) ;


<s> ReplaceNode ( N , CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) != <NUM_LIT> || isInlineImmediate ( N ) ) break ; uint64_t Imm ; if ( ConstantFPSDNode * FP = dyn_cast < ConstantFPSDNode > ( N ) ) Imm = FP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ; else { ConstantSDNode * C = cast < ConstantSDNode > ( N ) ; Imm = C -> getZExtValue ( ) ; } SDLoc DL ( N ) ; SDNode * Lo = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getConstant ( Imm & <NUM_LIT> , DL , <STR_LIT> ) ) ; SDNode * Hi = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getConstant ( Imm >> <NUM_LIT> , DL , <STR_LIT> ) ) ; const SDValue Ops [ ] = { CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , SDValue ( Lo , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , SDValue ( Hi , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { N = glueCopyToM0 ( N ) ; break ; } case <STR_LIT> : case <STR_LIT> : { ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) break ; bool Signed = Opc == <STR_LIT> ; uint32_t OffsetVal = Offset -> getZExtValue ( ) ; uint32_t WidthVal = Width -> getZExtValue ( ) ; ReplaceNode ( N , getS_BFE ( Signed ? <STR_LIT> : <STR_LIT> , SDLoc ( N ) , N -> getOperand ( <NUM_LIT> ) , OffsetVal , WidthVal ) ) ; return ; } case <STR_LIT> : { SelectDIV_SCALE ( N ) ; return ; } case <STR_LIT> : case <STR_LIT> : { SelectMAD_64_32 ( N ) ; return ; } case <STR_LIT> : { const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; N = Lowering . legalizeTargetIndependentNode ( N , * CurDAG ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) break ; SelectS_BFE ( N ) ; return ; case <STR_LIT> : SelectBRCOND ( N ) ; return ; case <STR_LIT> : case <STR_LIT> : SelectFMAD_FMA ( N ) ;


<s> } case <STR_LIT> : { SelectFMA_W_CHAIN ( N ) ; return ; } case <STR_LIT> : case <STR_LIT> : { EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned NumVectorElts = VT . getVectorNumElements ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { if ( Opc == <STR_LIT> ) { uint32_t LHSVal , RHSVal ; if ( getConstantValue ( N -> getOperand ( <NUM_LIT> ) , LHSVal ) && getConstantValue ( N -> getOperand ( <NUM_LIT> ) , RHSVal ) ) { uint32_t K = LHSVal | ( RHSVal << <NUM_LIT> ) ; CurDAG -> SelectNodeTo ( N , <STR_LIT> , VT , CurDAG -> getTargetConstant ( K , SDLoc ( N ) , <STR_LIT> ) ) ; return ; } } break ; } assert ( VT . getVectorElementType ( ) . bitsEq ( <STR_LIT> ) ) ; unsigned RegClassID = selectSGPRVectorRegClassID ( NumVectorElts ) ; SelectBuildVector ( N , RegClassID ) ; return ; } case <STR_LIT> : { SDValue RC , SubReg0 , SubReg1 ; SDLoc DL ( N ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } const SDValue Ops [ ] = { RC , N -> getOperand ( <NUM_LIT> ) , SubReg0 , N -> getOperand ( <NUM_LIT> ) , SubReg1 } ; ReplaceNode ( N , CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ) ;


<s> unsigned AS = findMemSDNode ( N ) -> getAddressSpace ( ) ; if ( TII -> isLegalFLATOffset ( COffsetVal , AS , IsSigned ) ) { Addr = N0 ; OffsetVal = COffsetVal ; } else { SDLoc DL ( N ) ; uint64_t ImmField ; const unsigned NumBits = TII -> getNumFlatOffsetBits ( AS , IsSigned ) ; if ( IsSigned ) { ImmField = SignExtend64 ( COffsetVal , NumBits ) ; if ( static_cast < int64_t > ( COffsetVal ) > <NUM_LIT> ) { if ( static_cast < int64_t > ( ImmField ) < <NUM_LIT> ) { const uint64_t OffsetMask = maskTrailingOnes < uint64_t > ( NumBits - <NUM_LIT> ) ; ImmField = COffsetVal & OffsetMask ; } } } else { const uint64_t OffsetMask = maskTrailingOnes < uint64_t > ( NumBits ) ; ImmField = COffsetVal & OffsetMask ; } uint64_t RemainderOffset = COffsetVal - ImmField ; assert ( TII -> isLegalFLATOffset ( ImmField , AS , IsSigned ) ) ; assert ( RemainderOffset + ImmField == COffsetVal ) ; OffsetVal = ImmField ; SDValue Sub0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ;

SDValue Sub1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ;


<s> MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Rsrc = CurDAG -> getRegister ( Info -> getScratchRSrcReg ( ) , <STR_LIT> ) ; if ( ConstantSDNode * CAddr = dyn_cast < ConstantSDNode > ( Addr ) ) { int64_t Imm = CAddr -> getSExtValue ( ) ; const int64_t NullPtr = <ISA_LIT>TargetMachine :: getNullPointerValue ( <ISA_LIT>AS :: PRIVATE_ADDRESS ) ; if ( Imm != NullPtr ) { SDValue HighBits = CurDAG -> getTargetConstant ( Imm & ~ <NUM_LIT> , DL , <STR_LIT> ) ; MachineSDNode * MovHighBits = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , HighBits ) ; VAddr = SDValue ( MovHighBits , <NUM_LIT> ) ; const MachinePointerInfo & PtrInfo = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) ; SOffset = isStackPtrRelative ( PtrInfo ) ? CurDAG -> getRegister ( Info -> getStackPtrOffsetReg ( ) , <STR_LIT> ) : CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ImmOffset = CurDAG -> getTargetConstant ( Imm & <NUM_LIT> , DL , <STR_LIT> ) ; return true ; } } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( C1 -> getZExtValue ( ) ) && ( ! Subtarget -> privateMemoryResourceIsRangeChecked ( ) || CurDAG -> SignBitIsZero ( N0 ) ) ) { std :: tie ( VAddr , SOffset ) = foldFrameIndex ( N0 ) ; ImmOffset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ; return true ;


<s> } if ( IsVALU ) { unsigned Opc = IsAdd ? <STR_LIT> : <STR_LIT> ; CurDAG -> SelectNodeTo ( N , Opc , N -> getVTList ( ) , { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , { } , <STR_LIT> ) } ) ; } else {

unsigned Opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ;


<s> } case <STR_LIT> : { SelectFMUL_W_CHAIN ( N ) ; return ; } case <STR_LIT> : { SelectFMA_W_CHAIN ( N ) ; return ; } case <STR_LIT> : case <STR_LIT> : { EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned NumVectorElts = VT . getVectorNumElements ( ) ; if ( VT . getScalarSizeInBits ( ) == <NUM_LIT> ) { if ( Opc == <STR_LIT> && NumVectorElts == <NUM_LIT> ) { if ( SDNode * Packed = packConstantV2I16 ( N , * CurDAG ) ) { ReplaceNode ( N , Packed ) ; return ; } } break ; } assert ( VT . getVectorElementType ( ) . bitsEq ( <STR_LIT> ) ) ; unsigned RegClassID = <ISA_LIT>RegisterInfo :: getSGPRClassForBitWidth ( NumVectorElts * <NUM_LIT> ) -> getID ( ) ; SelectBuildVector ( N , RegClassID ) ; return ; } case <STR_LIT> : { SDValue RC , SubReg0 , SubReg1 ; SDLoc DL ( N ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } const SDValue Ops [ ] = { RC , N -> getOperand ( <NUM_LIT> ) , SubReg0 , N -> getOperand ( <NUM_LIT> ) , SubReg1 } ; ReplaceNode ( N , CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) != <NUM_LIT> || isInlineImmediate ( N ) ) break ; uint64_t Imm ; if ( ConstantFPSDNode * FP = dyn_cast < ConstantFPSDNode > ( N ) ) Imm = FP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ; else { ConstantSDNode * C = cast < ConstantSDNode > ( N ) ; Imm = C -> getZExtValue ( ) ; } SDLoc DL ( N ) ; ReplaceNode ( N , buildSMovImm64 ( DL , Imm , N -> getValueType ( <NUM_LIT> ) ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : {

ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned NumVectorElts = VT . getVectorNumElements ( ) ; if ( VT . getScalarSizeInBits ( ) == <NUM_LIT> ) { if ( Opc == <STR_LIT> && NumVectorElts == <NUM_LIT> ) { if ( SDNode * Packed = packConstantV2I16 ( N , * CurDAG ) ) { ReplaceNode ( N , Packed ) ; return ; } } break ; } assert ( VT . getVectorElementType ( ) . bitsEq ( <STR_LIT> ) ) ; unsigned RegClassID = selectSGPRVectorRegClassID ( NumVectorElts ) ; SelectBuildVector ( N , RegClassID ) ; return ; } case <STR_LIT> : { SDValue RC , SubReg0 , SubReg1 ; SDLoc DL ( N ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } const SDValue Ops [ ] = { RC , N -> getOperand ( <NUM_LIT> ) , SubReg0 , N -> getOperand ( <NUM_LIT> ) , SubReg1 } ; ReplaceNode ( N , CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) != <NUM_LIT> || isInlineImmediate ( N ) ) break ; uint64_t Imm ; if ( ConstantFPSDNode * FP = dyn_cast < ConstantFPSDNode > ( N ) ) Imm = FP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ; else { ConstantSDNode * C = cast < ConstantSDNode > ( N ) ; Imm = C -> getZExtValue ( ) ; } SDLoc DL ( N ) ; ReplaceNode ( N , buildSMovImm64 ( DL , Imm , N -> getValueType ( <NUM_LIT> ) ) ) ; return ; }


<s> for ( unsigned i = <NUM_LIT> ; i < NOps ; i ++ ) { if ( isa < RegisterSDNode > ( N -> getOperand ( i ) ) ) { IsRegSeq = false ; break ; } unsigned Sub = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( i ) ; RegSeqArgs [ <NUM_LIT> + ( <NUM_LIT> * i ) ] = N -> getOperand ( i ) ; RegSeqArgs [ <NUM_LIT> + ( <NUM_LIT> * i ) + <NUM_LIT> ] = CurDAG -> getTargetConstant ( Sub , DL , <STR_LIT> ) ; } if ( NOps != NumVectorElts ) { assert ( N -> getOpcode ( ) == <STR_LIT> && NOps < NumVectorElts ) ; MachineSDNode * ImpDef = CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , DL , EltVT ) ; for ( unsigned i = NOps ; i < NumVectorElts ; ++ i ) { unsigned Sub = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( i ) ; RegSeqArgs [ <NUM_LIT> + ( <NUM_LIT> * i ) ] = SDValue ( ImpDef , <NUM_LIT> ) ; RegSeqArgs [ <NUM_LIT> + ( <NUM_LIT> * i ) + <NUM_LIT> ] = CurDAG -> getTargetConstant ( Sub , DL , <STR_LIT> ) ; } } if ( ! IsRegSeq ) SelectCode ( N ) ; CurDAG -> SelectNodeTo ( N , <STR_LIT> , N -> getVTList ( ) , RegSeqArgs ) ;


<s> case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : SelectCode ( N ) ; return ; } SDValue Src = N -> getOperand ( <NUM_LIT> ) ; CurDAG -> SelectNodeTo ( N , Opcode , N -> getVTList ( ) , { Src } ) ;


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> :


<s> if ( In . getValueType ( ) == <STR_LIT> ) return SelectVOP3Mods ( In , Src , SrcMods ) ;


<s> const APInt & LHSKnownZeros = CurDAG -> computeKnownBits ( N -> getOperand ( <NUM_LIT> ) ) . Zero ; return ( LHSKnownZeros | RHS ) . countTrailingOnes ( ) >= ShAmtBits ;


<s> const APInt & LHSKnownZeros = CurDAG -> computeKnownBits ( N -> getOperand ( <NUM_LIT> ) ) . Zero ;

return ( LHSKnownZeros | RHS ) . countTrailingOnes ( ) >= ShAmtBits ;


<s> SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } const SDValue Ops [ ] = { RC , N -> getOperand ( <NUM_LIT> ) , SubReg0 , N -> getOperand ( <NUM_LIT> ) , SubReg1 } ; ReplaceNode ( N , CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) != <NUM_LIT> || isInlineImmediate ( N ) ) break ; uint64_t Imm ; if ( ConstantFPSDNode * FP = dyn_cast < ConstantFPSDNode > ( N ) ) Imm = FP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ; else { ConstantSDNode * C = cast < ConstantSDNode > ( N ) ; Imm = C -> getZExtValue ( ) ; } SDLoc DL ( N ) ; ReplaceNode ( N , buildSMovImm64 ( DL , Imm , N -> getValueType ( <NUM_LIT> ) ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) break ; bool Signed = Opc == <STR_LIT> ; uint32_t OffsetVal = Offset -> getZExtValue ( ) ; uint32_t WidthVal = Width -> getZExtValue ( ) ; ReplaceNode ( N , getBFE32 ( Signed , SDLoc ( N ) , N -> getOperand ( <NUM_LIT> ) , OffsetVal , WidthVal ) ) ; return ; } case <STR_LIT> : { SelectDIV_SCALE ( N ) ; return ; } case <STR_LIT> : case <STR_LIT> : { SelectMAD_64_32 ( N ) ; return ; } case <STR_LIT> : case <STR_LIT> : return SelectMUL_LOHI ( N ) ; case <STR_LIT> : { const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; N = Lowering . legalizeTargetIndependentNode ( N , * CurDAG ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) break ; SelectS_BFE ( N ) ; return ; case <STR_LIT> : SelectBRCOND ( N ) ; return ; case <STR_LIT> : case <STR_LIT> : SelectFMAD_FMA ( N ) ; return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool Signed = N -> getOpcode ( ) == <STR_LIT> ; unsigned Opc = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Clamp = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Zero , Clamp } ; SDNode * Mad = CurDAG -> getMachineNode ( Opc , SL , N -> getVTList ( ) , Ops ) ; if ( ! SDValue ( N , <NUM_LIT> ) . use_empty ( ) ) { SDValue Sub0 = CurDAG -> getTargetConstant ( <STR_LIT> , SL , <STR_LIT> ) ; SDNode * Lo = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , SL , <STR_LIT> , SDValue ( Mad , <NUM_LIT> ) , Sub0 ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( Lo , <NUM_LIT> ) ) ; } if ( ! SDValue ( N , <NUM_LIT> ) . use_empty ( ) ) { SDValue Sub1 = CurDAG -> getTargetConstant ( <STR_LIT> , SL , <STR_LIT> ) ; SDNode * Hi = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , SL , <STR_LIT> , SDValue ( Mad , <NUM_LIT> ) , Sub1 ) ;

ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( Hi , <NUM_LIT> ) ) ;


<s> SDValue LHS , RHS ; if ( isBaseWithConstantOffset64 ( Addr , LHS , RHS ) ) { int64_t COffsetVal = cast < ConstantSDNode > ( RHS ) -> getSExtValue ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; if ( TII -> isLegalFLATOffset ( COffsetVal , <ISA_LIT>AS :: PRIVATE_ADDRESS , true ) ) { Addr = LHS ; ImmOffset = COffsetVal ; } else if ( ! LHS -> isDivergent ( ) && COffsetVal > <NUM_LIT> ) { SDLoc SL ( N ) ; int64_t SplitImmOffset , RemainderOffset ; std :: tie ( SplitImmOffset , RemainderOffset ) = TII -> splitFlatOffset ( COffsetVal , <ISA_LIT>AS :: PRIVATE_ADDRESS , true ) ; if ( isUInt < <NUM_LIT> > ( RemainderOffset ) ) {

SDNode * VMov = CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , CurDAG -> getTargetConstant ( RemainderOffset , SDLoc ( ) , <STR_LIT> ) ) ;


<s> const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; if ( TII -> isLegalFLATOffset ( COffsetVal , <ISA_LIT>AS :: PRIVATE_ADDRESS , true ) ) { Addr = LHS ; ImmOffset = COffsetVal ; } else if ( ! LHS -> isDivergent ( ) && COffsetVal > <NUM_LIT> ) { SDLoc SL ( N ) ; int64_t SplitImmOffset , RemainderOffset ; std :: tie ( SplitImmOffset , RemainderOffset ) = TII -> splitFlatOffset ( COffsetVal , <ISA_LIT>AS :: PRIVATE_ADDRESS , true ) ; if ( isUInt < <NUM_LIT> > ( RemainderOffset ) ) { SDNode * VMov = CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , CurDAG -> getTargetConstant ( RemainderOffset , SDLoc ( ) , <STR_LIT> ) ) ;


<s> Lo = stripExtractLoElt ( Lo ) ; Hi = stripExtractLoElt ( Hi ) ; if ( Lo . getValueSizeInBits ( ) > VecSize ) { Lo = CurDAG -> getTargetExtractSubreg ( ( VecSize > <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> , SDLoc ( In ) , <STR_LIT> ( VecSize ) , Lo ) ; } if ( Hi . getValueSizeInBits ( ) > VecSize ) { Hi = CurDAG -> getTargetExtractSubreg ( ( VecSize > <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> , SDLoc ( In ) , <STR_LIT> ( VecSize ) , Hi ) ; } assert ( Lo . getValueSizeInBits ( ) <= VecSize && Hi . getValueSizeInBits ( ) <= VecSize ) ; if ( Lo == Hi && ! isInlineImmediate ( Lo . getNode ( ) ) ) { if ( VecSize == <NUM_LIT> || VecSize == Lo . getValueSizeInBits ( ) ) { Src = Lo ; } else { assert ( Lo . getValueSizeInBits ( ) == <NUM_LIT> && VecSize == <NUM_LIT> ) ; SDLoc SL ( In ) ; SDValue Undef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , SL , Lo . getValueType ( ) ) , <NUM_LIT> ) ; auto RC = Lo -> isDivergent ( ) ? <STR_LIT> : <STR_LIT> ; const SDValue Ops [ ] = { CurDAG -> getTargetConstant ( RC , SL , <STR_LIT> ) , Lo , CurDAG -> getTargetConstant ( <STR_LIT> , SL , <STR_LIT> ) , Undef , CurDAG -> getTargetConstant ( <STR_LIT> , SL , <STR_LIT> ) } ; Src = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , SL , Src . getValueType ( ) , Ops ) , <NUM_LIT> ) ; } SrcMods = CurDAG -> getTargetConstant ( Mods , SDLoc ( In ) , <STR_LIT> ) ; return true ; } if ( VecSize == <NUM_LIT> && Lo == Hi && isa < ConstantFPSDNode > ( Lo ) ) { uint64_t Lit = cast < ConstantFPSDNode > ( Lo ) -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ; if ( <STR_LIT> ( Lit , Subtarget -> hasInv2PiInlineImm ( ) ) ) { Src = CurDAG -> getTargetConstant ( Lit , SDLoc ( In ) , <STR_LIT> ) ; ; SrcMods = CurDAG -> getTargetConstant ( Mods , SDLoc ( In ) , <STR_LIT> ) ; return true ; }


<s> if ( Subtarget -> hasAddr64 ( ) ) { SDValue SRsrc , VAddr , SOffset , Offset , SLC ; if ( SelectMUBUFAddr64 ( Mem -> getBasePtr ( ) , SRsrc , VAddr , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue GLC = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Ops [ ] = { CmpVal , VAddr , SRsrc , SOffset , Offset , GLC , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SDValue SRsrc , SOffset , Offset , SLC ; if ( SelectMUBUFOffset ( Mem -> getBasePtr ( ) , SRsrc , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue GLC = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Ops [ ] = { CmpVal , SRsrc , SOffset , Offset , GLC , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } }


<s> bool Is32 = ( VT == <STR_LIT> ) ; SDLoc SL ( N ) ; MachineSDNode * CmpSwap = nullptr ; if ( Subtarget -> hasAddr64 ( ) ) { SDValue SRsrc , VAddr , SOffset , Offset , SLC ; if ( SelectMUBUFAddr64 ( Mem -> getBasePtr ( ) , SRsrc , VAddr , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue GLC = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Ops [ ] = { CmpVal , VAddr , SRsrc , SOffset , Offset , GLC , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SDValue SRsrc , SOffset , Offset , SLC ; if ( SelectMUBUFOffset ( Mem -> getBasePtr ( ) , SRsrc , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue GLC = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Ops [ ] = { CmpVal , SRsrc , SOffset , Offset , GLC , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SelectCode ( N ) ; return ; } MachineMemOperand * MMO = Mem -> getMemOperand ( ) ; CurDAG -> setNodeMemRefs ( CmpSwap , { MMO } ) ; unsigned SubReg = Is32 ? <STR_LIT> : <STR_LIT> ;


<s> if ( Addr . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> ) { SmallVector < SDValue , <NUM_LIT> > Opnds ; Opnds . push_back ( N0 ) ; Opnds . push_back ( AddOffsetLo ) ; unsigned AddOp = <STR_LIT> ; if ( Subtarget -> hasAddNoCarry ( ) ) { AddOp = <STR_LIT> ; Opnds . push_back ( Clamp ) ; } Addr = SDValue ( CurDAG -> getMachineNode ( AddOp , DL , <STR_LIT> , Opnds ) , <NUM_LIT> ) ; } else { SDValue Sub0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Sub1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDNode * N0Lo = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , N0 , Sub0 ) ; SDNode * N0Hi = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , N0 , Sub1 ) ; SDValue AddOffsetHi = getMaterializedScalarImm32 ( Hi_32 ( RemainderOffset ) , DL ) ; SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; SDNode * Add = CurDAG -> getMachineNode ( <STR_LIT> , DL , VTs , { AddOffsetLo , SDValue ( N0Lo , <NUM_LIT> ) , Clamp } ) ; SDNode * Addc = CurDAG -> getMachineNode ( <STR_LIT> , DL , VTs , { AddOffsetHi , SDValue ( N0Hi , <NUM_LIT> ) , SDValue ( Add , <NUM_LIT> ) , Clamp } ) ; SDValue RegSequenceArgs [ ] = { CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , SDValue ( Add , <NUM_LIT> ) , Sub0 , SDValue ( Addc , <NUM_LIT> ) , Sub1 } ; Addr = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , RegSequenceArgs ) , <NUM_LIT> ) ; } } } }


<s> void <ISA_LIT>DAGToDAGISel :: SelectFMA_W_CHAIN ( SDNode * N ) { SDLoc SL ( N ) ; SDValue Ops [ <NUM_LIT> ] ; SelectVOP3Mods0 ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; SelectVOP3Mods ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; SelectVOP3Mods ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ;

Ops [ <NUM_LIT> ] = N -> getOperand ( <NUM_LIT> ) ;


<s> void <ISA_LIT>DAGToDAGISel :: SelectFMA_W_CHAIN ( SDNode * N ) { SDLoc SL ( N ) ; SDValue Ops [ <NUM_LIT> ] ; SelectVOP3Mods0 ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; SelectVOP3Mods ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; SelectVOP3Mods ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; Ops [ <NUM_LIT> ] = N -> getOperand ( <NUM_LIT> ) ; Ops [ <NUM_LIT> ] = N -> getOperand ( <NUM_LIT> ) ; CurDAG -> SelectNodeTo ( N , <STR_LIT> , N -> getVTList ( ) , Ops ) ;