<s>
SDValue
AVRTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
auto
CCFunction
=
CCAssignFnForReturn
(
CallConv
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
CCFunction
)
;
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
unsigned
e
=
RVLocs
.
size
(
)
;
if
(
e
>
1
)
{
std
::
reverse
(
RVLocs
.
begin
(
)
,
RVLocs
.
end
(
)
)
;
}
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
if
(
MF
.
getFunction
(
)
->
getAttributes
(
)
.
hasAttribute
(
AttributeList
::
FunctionIndex
,
Attribute
::
Naked
)
)
{
return
Chain
;
}
unsigned
RetOpc
=
(
CallConv
==
CallingConv
::
AVR_INTR
||
CallConv
==
CallingConv
::
AVR_SIGNAL
)
AVRISD
::
RETI_FLAG
:
AVRISD
::
RET_FLAG
;
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
RetOpc
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>


For most targets , an LLVM type must be broken down into multiple smaller types .


<s> bool AVRTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; auto CCFunction = CCAssignFnForReturn ( CallConv ) ; return CCInfo . CheckReturn ( Outs , CCFunction ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> CCAssignFn * AVRTargetLowering :: CCAssignFnForReturn ( CallingConv :: ID CC ) const { switch ( CC ) { case CallingConv :: AVR_BUILTIN : return RetCC_AVR_BUILTIN ; default : return RetCC_AVR ; } } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> AVRTargetLowering :: ConstraintType AVRTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'a' : case 'b' : case 'd' : case 'l' : case 'e' : case 'q' : case 'r' : case 'w' : return C_RegisterClass ; case 't' : case 'x' : case 'X' : case 'y' : case 'Y' : case 'z' : case 'Z' : return C_Register ; case 'Q' : return C_Memory ; case 'G' : case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'O' : case 'P' : case 'R' : return C_Other ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


"don't know how to get the name for this callee"


<s> bool AVRTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { EVT VT ; SDLoc DL ( N ) ; if ( const LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; if ( LD -> getExtensionType ( ) != ISD :: NON_EXTLOAD ) return false ; } else if ( const StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; if ( AVR :: isProgramMemoryAccess ( ST ) ) { return false ; } } else { return false ; } if ( VT != MVT :: i8 && VT != MVT :: i16 ) { return false ; } if ( Op -> getOpcode ( ) != ISD :: ADD && Op -> getOpcode ( ) != ISD :: SUB ) { return false ; } if ( const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) { int RHSC = RHS -> getSExtValue ( ) ; if ( Op -> getOpcode ( ) == ISD :: SUB ) RHSC = - RHSC ; if ( ( VT == MVT :: i16 && RHSC != 2 ) || ( VT == MVT :: i8 && RHSC != 1 ) ) { return false ; } Base = Op -> getOperand ( 0 ) ; Offset = DAG . getConstant ( RHSC , DL , MVT :: i8 ) ; AM = ISD :: POST_INC ; return true ; } return false ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> bool AVRTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { EVT VT ; const SDNode * Op ; SDLoc DL ( N ) ; if ( const LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Op = LD -> getBasePtr ( ) . getNode ( ) ; if ( LD -> getExtensionType ( ) != ISD :: NON_EXTLOAD ) return false ; if ( AVR :: isProgramMemoryAccess ( LD ) ) { return false ; } } else if ( const StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Op = ST -> getBasePtr ( ) . getNode ( ) ; if ( AVR :: isProgramMemoryAccess ( ST ) ) { return false ; } } else { return false ; } if ( VT != MVT :: i8 && VT != MVT :: i16 ) { return false ; } if ( Op -> getOpcode ( ) != ISD :: ADD && Op -> getOpcode ( ) != ISD :: SUB ) { return false ; } if ( const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) { int RHSC = RHS -> getSExtValue ( ) ; if ( Op -> getOpcode ( ) == ISD :: SUB ) RHSC = - RHSC ; if ( ( VT == MVT :: i16 && RHSC != - 2 ) || ( VT == MVT :: i8 && RHSC != - 1 ) ) { return false ; } Base = Op -> getOperand ( 0 ) ; Offset = DAG . getConstant ( RHSC , DL , MVT :: i8 ) ; AM = ISD :: PRE_DEC ; return true ; } return false ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
AVRTargetLowering
::
getRegForInlineAsmConstraint
(
const
TargetRegisterInfo
*
TRI
,
StringRef
Constraint
,
MVT
VT
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'a'
:
return
std
::
make_pair
(
0U
,
&
AVR
::
LD8loRegClass
)
;
case
'b'
:
return
std
::
make_pair
(
0U
,
&
AVR
::
PTRDISPREGSRegClass
)
;
case
'd'
:
return
std
::
make_pair
(
0U
,
&
AVR
::
LD8RegClass
)
;
case
'l'
:
return
std
::
make_pair
(
0U
,
&
AVR
::
GPR8loRegClass
)
;
case
'e'
:
return
std
::
make_pair
(
0U
,
&
AVR
::
PTRREGSRegClass
)
;
case
'q'
:
return
std
::
make_pair
(
0U
,
&
AVR
::
GPRSPRegClass
)
;
case
'r'
:
if
(
VT
==
MVT
::
i8
)
return
std
::
make_pair
(
0U
,
&
AVR
::
GPR8RegClass
)
;
assert
(
VT
==
MVT
::
i16
&&
"inline asm constraint too large"
)
;
return
std
::
make_pair
(
0U
,
&
AVR
::
DREGSRegClass
)
;
case
't'
:
return
std
::
make_pair
(
unsigned
(
AVR
::
R0
)
,
&
AVR
::
GPR8RegClass
)
;
case
'w'
:
return
std
::
make_pair
(
0U
,
&
AVR
::
IWREGSRegClass
)
;
case
'x'
:
case
'X'
:
return
std
::
make_pair
(
unsigned
(
AVR
::
R27R26
)
,
&
AVR
::
PTRREGSRegClass
)
;
case
'y'
:
case
'Y'
:
return
std
::
make_pair
(
unsigned
(
AVR
::
R29R28
)
,
&
AVR
::
PTRREGSRegClass
)
;
case
'z'
:
case
'Z'
:
return
std
::
make_pair
(
unsigned
(
AVR
::
R31R30
)
,
&
AVR
::
PTRREGSRegClass
)
;
default
:
break
;
}
}
return
TargetLowering
::
getRegForInlineAsmConstraint
(
Subtarget
.
getRegisterInfo
(
)
,
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


<s>
EVT
AVRTargetLowering
::
getSetCCResultType
(
const
DataLayout
&
DL
,
LLVMContext
&
,
EVT
VT
)
const
{
assert
(
!
VT
.
isVector
(
)
&&
"No AVR SetCC type for vectors!"
)
;
return
MVT
::
i8
;
}
</s>

Return the value type to use for ISD : :SETCC .

AVR
AVR
"No AVR SetCC type for vectors!"
MVT::i8


<s> const char * AVRTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case AVRISD :: name : \ return # name switch ( Opcode ) { default : return nullptr ; NODE ( RET_FLAG ) ; NODE ( RETI_FLAG ) ; NODE ( CALL ) ; NODE ( WRAPPER ) ; NODE ( LSL ) ; NODE ( LSR ) ; NODE ( ROL ) ; NODE ( ROR ) ; NODE ( ASR ) ; NODE ( LSLLOOP ) ; NODE ( LSRLOOP ) ; NODE ( ASRLOOP ) ; NODE ( BRCOND ) ; NODE ( CMP ) ; NODE ( CMPC ) ; NODE ( TST ) ; NODE ( SELECT_CC ) ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> bool AVRTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { int64_t Offs = AM . BaseOffs ; if ( AM . BaseGV && ! AM . HasBaseReg && AM . Scale == 0 && Offs == 0 ) { return true ; } if ( isa < PointerType > ( Ty ) && AS == AVR :: ProgramMemory ) { return false ; } if ( Offs < 0 ) Offs = - Offs ; if ( AM . BaseGV == 0 && AM . HasBaseReg && AM . Scale == 0 && isUInt < 6 > ( Offs ) ) { return true ; } return false ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool AVRTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return true ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> SDValue AVRTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; auto CCFunction = CCAssignFnForReturn ( CallConv ) ; CCInfo . AnalyzeCallResult ( Ins , CCFunction ) ; if ( CallConv != CallingConv :: AVR_BUILTIN && RVLocs . size ( ) > 1 ) { std :: reverse ( RVLocs . begin ( ) , RVLocs . end ( ) ) ; } for ( CCValAssign const & RVLoc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLoc . getLocReg ( ) , RVLoc . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s>
SDValue
AVRTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom lower this!"
)
;
case
ISD
::
SHL
:
case
ISD
::
SRA
:
case
ISD
::
SRL
:
case
ISD
::
ROTL
:
case
ISD
::
ROTR
:
return
LowerShifts
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
SDIVREM
:
case
ISD
::
UDIVREM
:
return
LowerDivRem
(
Op
,
DAG
)
;
}
return
SDValue
(
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

AVR
AVR
"Don't know how to custom lower this!"
ISD::SHL
ISD::SRA
ISD::SRL
ISD::ROTL
ISD::ROTR
ISD::GlobalAddress
ISD::BlockAddress
ISD::BR_CC
ISD::SELECT_CC
ISD::SETCC
ISD::VASTART
ISD::SDIVREM
ISD::UDIVREM


<s>
SDValue
AVRTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
auto
CCFunction
=
CCAssignFnForReturn
(
CallConv
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
CCFunction
)
;
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
unsigned
e
=
RVLocs
.
size
(
)
;
if
(
e
>
1
)
{
std
::
reverse
(
RVLocs
.
begin
(
)
,
RVLocs
.
end
(
)
)
;
}
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
if
(
MF
.
getFunction
(
)
.
getAttributes
(
)
.
hasAttribute
(
AttributeList
::
FunctionIndex
,
Attribute
::
Naked
)
)
{
return
Chain
;
}
unsigned
RetOpc
=
(
CallConv
==
CallingConv
::
AVR_INTR
||
CallConv
==
CallingConv
::
AVR_SIGNAL
)
AVRISD
::
RETI_FLAG
:
AVRISD
::
RET_FLAG
;
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
RetOpc
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void AVRTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { SDLoc DL ( N ) ; switch ( N -> getOpcode ( ) ) { case ISD :: ADD : { if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) ) { SDValue Sub = DAG . getNode ( ISD :: SUB , DL , N -> getValueType ( 0 ) , N -> getOperand ( 0 ) , DAG . getConstant ( - C -> getAPIntValue ( ) , DL , C -> getValueType ( 0 ) ) ) ; Results . push_back ( Sub ) ; } break ; } default : { SDValue Res = LowerOperation ( SDValue ( N , 0 ) , DAG ) ; for ( unsigned I = 0 , E = Res -> getNumValues ( ) ; I != E ; ++ I ) Results . push_back ( Res . getValue ( I ) ) ; break ; } } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> bool isInterruptOrSignalHandler ( ) const { return isInterruptHandler ( ) || isSignalHandler ( ) ; } </s>

Checks if the function is some form of interrupt service routine .


<s> void AVRMCCodeEmitter :: emitInstruction ( uint64_t Val , unsigned Size , const MCSubtargetInfo & STI , raw_ostream & OS ) const { const uint16_t * Words = reinterpret_cast < uint16_t const * > ( & Val ) ; size_t WordCount = Size / 2 ; for ( int64_t i = WordCount - 1 ; i >= 0 ; -- i ) { uint16_t Word = Words [ i ] ; OS << ( uint8_t ) ( ( Word & 0x00ff ) >> 0 ) ; OS << ( uint8_t ) ( ( Word & 0xff00 ) >> 8 ) ; } } </s>

Targets should implement this to emit instructions .


<s> unsigned AVRMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; if ( MO . isFPImm ( ) ) return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( 32 ) . getLimitedValue ( ) ) ; assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> void AVRMCCodeEmitter :: emitInstruction ( uint64_t Val , unsigned Size , const MCSubtargetInfo & STI , raw_ostream & OS ) const { size_t WordCount = Size / 2 ; for ( int64_t i = WordCount - 1 ; i >= 0 ; -- i ) { uint16_t Word = ( Val >> ( i * 16 ) ) & 0xFFFF ; support :: endian :: write ( OS , Word , support :: endianness :: little ) ; } } </s>


<s>
void
AVRMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
unsigned
Size
=
Desc
.
getSize
(
)
;
assert
(
Size
>
0
&&
"Instruction size cannot be zero"
)
;
uint64_t
BinaryOpCode
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
emitInstruction
(
BinaryOpCode
,
Size
,
STI
,
OS
)
;
}
</s>

Encode the given Inst to bytes and append to CB .

AVR
AVR
0
"Instruction size cannot be zero"


<s> unsigned AVRMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; if ( MO . isDFPImm ( ) ) return static_cast < unsigned > ( bit_cast < double > ( MO . getDFPImm ( ) ) ) ; assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ; } </s>


<s>
AVR
::
Fixups
AVRMCExpr
::
getFixupKind
(
)
const
{
AVR
::
Fixups
Kind
=
AVR
::
Fixups
::
LastTargetFixupKind
;
switch
(
getKind
(
)
)
{
case
VK_AVR_LO8
:
Kind
=
isNegated
(
)
AVR
::
fixup_lo8_ldi_neg
:
AVR
::
fixup_lo8_ldi
;
break
;
case
VK_AVR_HI8
:
Kind
=
isNegated
(
)
AVR
::
fixup_hi8_ldi_neg
:
AVR
::
fixup_hi8_ldi
;
break
;
case
VK_AVR_HH8
:
Kind
=
isNegated
(
)
AVR
::
fixup_hh8_ldi_neg
:
AVR
::
fixup_hh8_ldi
;
break
;
case
VK_AVR_HHI8
:
Kind
=
isNegated
(
)
AVR
::
fixup_ms8_ldi_neg
:
AVR
::
fixup_ms8_ldi
;
break
;
case
VK_AVR_PM_LO8
:
Kind
=
isNegated
(
)
AVR
::
fixup_lo8_ldi_pm_neg
:
AVR
::
fixup_lo8_ldi_pm
;
break
;
case
VK_AVR_PM_HI8
:
Kind
=
isNegated
(
)
AVR
::
fixup_hi8_ldi_pm_neg
:
AVR
::
fixup_hi8_ldi_pm
;
break
;
case
VK_AVR_PM_HH8
:
Kind
=
isNegated
(
)
AVR
::
fixup_hh8_ldi_pm_neg
:
AVR
::
fixup_hh8_ldi_pm
;
break
;
case
VK_AVR_GS
:
Kind
=
AVR
::
fixup_16_pm
;
break
;
case
VK_AVR_LO8_GS
:
Kind
=
AVR
::
fixup_lo8_ldi_gs
;
break
;
case
VK_AVR_HI8_GS
:
Kind
=
AVR
::
fixup_hi8_ldi_gs
;
break
;
case
VK_AVR_None
:
llvm_unreachable
(
"Uninitialized expression"
)
;
}
return
Kind
;
}
</s>

getFixupKind - Get the fixup kind of this expression .


<s>
AVR
::
Fixups
AVRMCExpr
::
getFixupKind
(
)
const
{
AVR
::
Fixups
Kind
=
AVR
::
Fixups
::
LastTargetFixupKind
;
switch
(
getKind
(
)
)
{
case
VK_AVR_LO8
:
Kind
=
isNegated
(
)
AVR
::
fixup_lo8_ldi_neg
:
AVR
::
fixup_lo8_ldi
;
break
;
case
VK_AVR_HI8
:
Kind
=
isNegated
(
)
AVR
::
fixup_hi8_ldi_neg
:
AVR
::
fixup_hi8_ldi
;
break
;
case
VK_AVR_HH8
:
Kind
=
isNegated
(
)
AVR
::
fixup_hh8_ldi_neg
:
AVR
::
fixup_hh8_ldi
;
break
;
case
VK_AVR_HHI8
:
Kind
=
isNegated
(
)
AVR
::
fixup_ms8_ldi_neg
:
AVR
::
fixup_ms8_ldi
;
break
;
case
VK_AVR_PM_LO8
:
Kind
=
isNegated
(
)
AVR
::
fixup_lo8_ldi_pm_neg
:
AVR
::
fixup_lo8_ldi_pm
;
break
;
case
VK_AVR_PM_HI8
:
Kind
=
isNegated
(
)
AVR
::
fixup_hi8_ldi_pm_neg
:
AVR
::
fixup_hi8_ldi_pm
;
break
;
case
VK_AVR_PM_HH8
:
Kind
=
isNegated
(
)
AVR
::
fixup_hh8_ldi_pm_neg
:
AVR
::
fixup_hh8_ldi_pm
;
break
;
case
VK_AVR_PM
:
case
VK_AVR_GS
:
Kind
=
AVR
::
fixup_16_pm
;
break
;
case
VK_AVR_LO8_GS
:
Kind
=
AVR
::
fixup_lo8_ldi_gs
;
break
;
case
VK_AVR_HI8_GS
:
Kind
=
AVR
::
fixup_hi8_ldi_gs
;
break
;
case
VK_AVR_None
:
llvm_unreachable
(
"Uninitialized expression"
)
;
}
return
Kind
;
}
</s>


<s> const char * AVRMCExpr :: getName ( ) const { const auto & Modifier = llvm :: find_if ( ModifierNames , [ this ] ( ModifierEntry const & Mod ) { return Mod . VariantKind == Kind ; } ) ; if ( Modifier != std :: end ( ModifierNames ) ) { return Modifier -> Spelling ; } return nullptr ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> const AVRMCExpr * AVRMCExpr :: create ( VariantKind Kind , const MCExpr * Expr , bool Negated , MCContext & Ctx ) { return new ( Ctx ) AVRMCExpr ( Kind , Expr , Negated ) ; } </s>


<s> bool AVRMCExpr :: evaluateAsConstant ( int64_t & Result ) const { MCValue Value ; bool isRelocatable = getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ; if ( ! isRelocatable ) return false ; if ( Value . isAbsolute ( ) ) { Result = evaluateAsInt64 ( Value . getConstant ( ) ) ; return true ; } return false ; } </s>

Evaluates the fixup as a constant value .


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s>
AVR
::
Fixups
AVRMCExpr
::
getFixupKind
(
)
const
{
AVR
::
Fixups
Kind
=
AVR
::
Fixups
::
LastTargetFixupKind
;
switch
(
getKind
(
)
)
{
case
VK_AVR_LO8
:
Kind
=
isNegated
(
)
AVR
::
fixup_lo8_ldi_neg
:
AVR
::
fixup_lo8_ldi
;
break
;
case
VK_AVR_HI8
:
Kind
=
isNegated
(
)
AVR
::
fixup_hi8_ldi_neg
:
AVR
::
fixup_hi8_ldi
;
break
;
case
VK_AVR_HH8
:
Kind
=
isNegated
(
)
AVR
::
fixup_hh8_ldi_neg
:
AVR
::
fixup_hh8_ldi
;
break
;
case
VK_AVR_HHI8
:
Kind
=
isNegated
(
)
AVR
::
fixup_ms8_ldi_neg
:
AVR
::
fixup_ms8_ldi
;
break
;
case
VK_AVR_PM_LO8
:
Kind
=
isNegated
(
)
AVR
::
fixup_lo8_ldi_pm_neg
:
AVR
::
fixup_lo8_ldi_pm
;
break
;
case
VK_AVR_PM_HI8
:
Kind
=
isNegated
(
)
AVR
::
fixup_hi8_ldi_pm_neg
:
AVR
::
fixup_hi8_ldi_pm
;
break
;
case
VK_AVR_PM_HH8
:
Kind
=
isNegated
(
)
AVR
::
fixup_hh8_ldi_pm_neg
:
AVR
::
fixup_hh8_ldi_pm
;
break
;
case
VK_AVR_None
:
llvm_unreachable
(
"Uninitialized expression"
)
;
}
return
Kind
;
}
</s>


<s> VariantKind getKind ( ) const { return Kind ; } </s>


<s> const char * AVRMCExpr :: getName ( ) const { const auto & Modifier = std :: find_if ( std :: begin ( ModifierNames ) , std :: end ( ModifierNames ) , [ this ] ( ModifierEntry const & Mod ) { return Mod . VariantKind == Kind ; } ) ; if ( Modifier != std :: end ( ModifierNames ) ) { return Modifier -> Spelling ; } return nullptr ; } </s>


<s> const MCExpr * getSubExpr ( ) const { return SubExpr ; } </s>

getSubExpr - Get the child of this expression .


<s>
void
AVRMCInstLower
::
lowerInstruction
(
const
MachineInstr
&
MI
,
MCInst
&
OutMI
)
const
{
OutMI
.
setOpcode
(
MI
.
getOpcode
(
)
)
;
for
(
MachineOperand
const
&
MO
:
MI
.
operands
(
)
)
{
MCOperand
MCOp
;
switch
(
MO
.
getType
(
)
)
{
default
:
MI
.
dump
(
)
;
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
continue
;
MCOp
=
MCOperand
::
createReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
createImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
getSymbol
(
MO
.
getGlobal
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
createExpr
(
MCSymbolRefExpr
::
create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
Ctx
)
)
;
break
;
case
MachineOperand
::
MO_RegisterMask
:
continue
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
}
OutMI
.
addOperand
(
MCOp
)
;
}
}
</s>


<s>
void
AVRMCInstLower
::
lowerInstruction
(
const
MachineInstr
&
MI
,
MCInst
&
OutMI
)
const
{
OutMI
.
setOpcode
(
MI
.
getOpcode
(
)
)
;
for
(
MachineOperand
const
&
MO
:
MI
.
operands
(
)
)
{
MCOperand
MCOp
;
switch
(
MO
.
getType
(
)
)
{
default
:
MI
.
print
(
errs
(
)
)
;
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
continue
;
MCOp
=
MCOperand
::
createReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
createImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
getSymbol
(
MO
.
getGlobal
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
createExpr
(
MCSymbolRefExpr
::
create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
Ctx
)
)
;
break
;
case
MachineOperand
::
MO_RegisterMask
:
continue
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
}
OutMI
.
addOperand
(
MCOp
)
;
}
}
</s>


<s> const uint16_t * AVRRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const AVRMachineFunctionInfo * AFI = MF -> getInfo < AVRMachineFunctionInfo > ( ) ; return AFI -> isInterruptOrSignalHandler ( ) ? CSR_Interrupts_SaveList : CSR_Normal_SaveList ; } </s>


<s> const uint32_t * AVRRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const AVRMachineFunctionInfo * AFI = MF . getInfo < AVRMachineFunctionInfo > ( ) ; return AFI -> isInterruptOrSignalHandler ( ) ? CSR_Interrupts_RegMask : CSR_Normal_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> Register AVRRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { return AVR :: R28 ; } return AVR :: SP ; } </s>


<s> bool AVRRegisterInfo :: shouldCoalesce ( MachineInstr * MI , const TargetRegisterClass * SrcRC , unsigned SubReg , const TargetRegisterClass * DstRC , unsigned DstSubReg , const TargetRegisterClass * NewRC , LiveIntervals & LIS ) const { if ( this -> getRegClass ( AVR :: PTRDISPREGSRegClassID ) -> hasSubClassEq ( NewRC ) ) { return false ; } return TargetRegisterInfo :: shouldCoalesce ( MI , SrcRC , SubReg , DstRC , DstSubReg , NewRC , LIS ) ; } </s>


<s>
void
AVRRegisterInfo
::
splitReg
(
Register
Reg
,
Register
&
LoReg
,
Register
&
HiReg
)
const
{
assert
(
AVR
::
DREGSRegClass
.
contains
(
Reg
)
&&
"can only split 16-bit registers"
)
;
LoReg
=
getSubReg
(
Reg
,
AVR
::
sub_lo
)
;
HiReg
=
getSubReg
(
Reg
,
AVR
::
sub_hi
)
;
}
</s>

Splits a 16-bit DREGS register into the lo/hi register pair .

AVR
AVR
AVR::DREGSRegClass
"can only split 16-bit registers"
AVR::sub_lo
AVR::sub_hi


<s> const uint16_t * AVRRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { CallingConv :: ID CC = MF -> getFunction ( ) . getCallingConv ( ) ; return ( ( CC == CallingConv :: AVR_INTR || CC == CallingConv :: AVR_SIGNAL ) ? CSR_Interrupts_SaveList : CSR_Normal_SaveList ) ; } </s>


<s>
const
TargetRegisterClass
*
AVRRegisterInfo
::
getLargestLegalSuperClass
(
const
TargetRegisterClass
*
RC
,
const
MachineFunction
&
MF
)
const
{
const
TargetRegisterInfo
*
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
if
(
TRI
->
isTypeLegalForClass
(
*
RC
,
MVT
::
i16
)
)
{
return
&
AVR
::
DREGSRegClass
;
}
if
(
TRI
->
isTypeLegalForClass
(
*
RC
,
MVT
::
i8
)
)
{
return
&
AVR
::
GPR8RegClass
;
}
llvm_unreachable
(
"Invalid register size"
)
;
}
</s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


<s> BitVector AVRRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AVR :: R0 ) ; Reserved . set ( AVR :: R1 ) ; Reserved . set ( AVR :: R1R0 ) ; Reserved . set ( AVR :: SPL ) ; Reserved . set ( AVR :: SPH ) ; Reserved . set ( AVR :: SP ) ; Reserved . set ( AVR :: R28 ) ; Reserved . set ( AVR :: R29 ) ; Reserved . set ( AVR :: R29R28 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
void
AVRRegisterInfo
::
splitReg
(
unsigned
Reg
,
unsigned
&
LoReg
,
unsigned
&
HiReg
)
const
{
assert
(
AVR
::
DREGSRegClass
.
contains
(
Reg
)
&&
"can only split 16-bit registers"
)
;
LoReg
=
getSubReg
(
Reg
,
AVR
::
sub_lo
)
;
HiReg
=
getSubReg
(
Reg
,
AVR
::
sub_hi
)
;
}
</s>


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & ) const override { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> const uint32_t * AVRRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CSR_Normal_RegMask ; } </s>


<s> const uint16_t * AVRRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const AVRMachineFunctionInfo * AFI = MF -> getInfo < AVRMachineFunctionInfo > ( ) ; const AVRSubtarget & STI = MF -> getSubtarget < AVRSubtarget > ( ) ; if ( STI . hasTinyEncoding ( ) ) return AFI -> isInterruptOrSignalHandler ( ) ? CSR_InterruptsTiny_SaveList : CSR_NormalTiny_SaveList ; else return AFI -> isInterruptOrSignalHandler ( ) ? CSR_Interrupts_SaveList : CSR_Normal_SaveList ; } </s>


<s> const uint32_t * AVRRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const AVRSubtarget & STI = MF . getSubtarget < AVRSubtarget > ( ) ; return STI . hasTinyEncoding ( ) ? CSR_NormalTiny_RegMask : CSR_Normal_RegMask ; } </s>


<s> BitVector AVRRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AVR :: R0 ) ; Reserved . set ( AVR :: R1 ) ; Reserved . set ( AVR :: R1R0 ) ; Reserved . set ( AVR :: SPL ) ; Reserved . set ( AVR :: SPH ) ; Reserved . set ( AVR :: SP ) ; if ( MF . getSubtarget < AVRSubtarget > ( ) . hasTinyEncoding ( ) ) { for ( unsigned Reg = AVR :: R2 ; Reg <= AVR :: R17 ; Reg ++ ) Reserved . set ( Reg ) ; for ( unsigned Reg = AVR :: R3R2 ; Reg <= AVR :: R18R17 ; Reg ++ ) Reserved . set ( Reg ) ; } Reserved . set ( AVR :: R28 ) ; Reserved . set ( AVR :: R29 ) ; Reserved . set ( AVR :: R29R28 ) ; return Reserved ; } </s>


<s> const uint16_t * AVRRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { CallingConv :: ID CC = MF -> getFunction ( ) -> getCallingConv ( ) ; return ( ( CC == CallingConv :: AVR_INTR || CC == CallingConv :: AVR_SIGNAL ) ? CSR_Interrupts_SaveList : CSR_Normal_SaveList ) ; } </s>


<s> const uint32_t * AVRRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return ( ( CC == CallingConv :: AVR_INTR || CC == CallingConv :: AVR_SIGNAL ) ? CSR_Interrupts_RegMask : CSR_Normal_RegMask ) ; } </s>


<s> unsigned AVRRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { return AVR :: R28 ; } return AVR :: SP ; } </s>


<s>
const
TargetRegisterClass
*
AVRRegisterInfo
::
getLargestLegalSuperClass
(
const
TargetRegisterClass
*
RC
,
const
MachineFunction
&
MF
)
const
{
if
(
RC
->
hasType
(
MVT
::
i16
)
)
{
return
&
AVR
::
DREGSRegClass
;
}
if
(
RC
->
hasType
(
MVT
::
i8
)
)
{
return
&
AVR
::
GPR8RegClass
;
}
llvm_unreachable
(
"Invalid register size"
)
;
}
</s>


<s> const TargetRegisterClass * AVRRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & AVR :: PTRDISPREGSRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> BitVector AVRRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const AVRTargetMachine & TM = static_cast < const AVRTargetMachine & > ( MF . getTarget ( ) ) ; const TargetFrameLowering * TFI = TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ; Reserved . set ( AVR :: R0 ) ; Reserved . set ( AVR :: R1 ) ; Reserved . set ( AVR :: R1R0 ) ; Reserved . set ( AVR :: SPL ) ; Reserved . set ( AVR :: SPH ) ; Reserved . set ( AVR :: SP ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( AVR :: R28 ) ; Reserved . set ( AVR :: R29 ) ; Reserved . set ( AVR :: R29R28 ) ; } return Reserved ; } </s>


<s> StringRef getPassName ( ) const override { return AVR_RELAX_MEM_OPS_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> bool AVRRelaxMem :: runOnMachineFunction ( MachineFunction & MF ) { bool Modified = false ; const AVRSubtarget & STI = MF . getSubtarget < AVRSubtarget > ( ) ; TII = STI . getInstrInfo ( ) ; for ( Block & MBB : MF ) { bool BlockModified = runOnBasicBlock ( MBB ) ; Modified |= BlockModified ; } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


"asked to expand an instruction that is not a shift"

expand - Expand a record into a set of elements if possible .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AVR Shift Expansion"
;
}
</s>


<s> bool AVRShiftExpand :: runOnFunction ( Function & F ) { SmallVector < BinaryOperator * , 1 > ShiftInsts ; auto & Ctx = F . getContext ( ) ; for ( Instruction & I : instructions ( F ) ) { if ( ! I . isShift ( ) ) continue ; if ( I . getType ( ) != Type :: getInt32Ty ( Ctx ) ) continue ; if ( isa < ConstantInt > ( I . getOperand ( 1 ) ) ) continue ; ShiftInsts . push_back ( cast < BinaryOperator > ( & I ) ) ; } for ( auto * I : ShiftInsts ) { expand ( I ) ; } return ShiftInsts . size ( ) > 0 ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> AVRSubtarget :: AVRSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const AVRTargetMachine & TM ) : AVRGenSubtargetInfo ( TT , CPU , FS ) , InstrInfo ( ) , FrameLowering ( ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS , TM ) ) , TSInfo ( ) , m_hasSRAM ( false ) , m_hasJMPCALL ( false ) , m_hasIJMPCALL ( false ) , m_hasEIJMPCALL ( false ) , m_hasADDSUBIW ( false ) , m_hasSmallStack ( false ) , m_hasMOVW ( false ) , m_hasLPM ( false ) , m_hasLPMX ( false ) , m_hasELPM ( false ) , m_hasELPMX ( false ) , m_hasSPM ( false ) , m_hasSPMX ( false ) , m_hasDES ( false ) , m_supportsRMW ( false ) , m_supportsMultiplication ( false ) , m_hasBREAK ( false ) , m_hasTinyEncoding ( false ) , ELFArch ( false ) , m_FeatureSetDummy ( false ) { ParseSubtargetFeatures ( CPU , FS ) ; } </s>


<s> AVRSubtarget & AVRSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , const TargetMachine & TM ) { ParseSubtargetFeatures ( CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> AVRSubtarget :: AVRSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const AVRTargetMachine & TM ) : AVRGenSubtargetInfo ( TT , CPU , CPU , FS ) , ELFArch ( 0 ) , m_hasSRAM ( false ) , m_hasJMPCALL ( false ) , m_hasIJMPCALL ( false ) , m_hasEIJMPCALL ( false ) , m_hasADDSUBIW ( false ) , m_hasSmallStack ( false ) , m_hasMOVW ( false ) , m_hasLPM ( false ) , m_hasLPMX ( false ) , m_hasELPM ( false ) , m_hasELPMX ( false ) , m_hasSPM ( false ) , m_hasSPMX ( false ) , m_hasDES ( false ) , m_supportsRMW ( false ) , m_supportsMultiplication ( false ) , m_hasBREAK ( false ) , m_hasTinyEncoding ( false ) , m_hasMemMappedGPR ( false ) , m_FeatureSetDummy ( false ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS , TM ) ) { ParseSubtargetFeatures ( CPU , CPU , FS ) ; } </s>


<s> int getIORegRAMPZ ( void ) const { return hasELPM ( ) ? 0x3b : - 1 ; } </s>


<s> int getRegTmpIndex ( void ) const { return hasTinyEncoding ( ) ? 16 : 0 ; } </s>


<s> AVRSubtarget :: AVRSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const AVRTargetMachine & TM ) : AVRGenSubtargetInfo ( TT , CPU , FS ) , ELFArch ( 0 ) , m_hasSRAM ( false ) , m_hasJMPCALL ( false ) , m_hasIJMPCALL ( false ) , m_hasEIJMPCALL ( false ) , m_hasADDSUBIW ( false ) , m_hasSmallStack ( false ) , m_hasMOVW ( false ) , m_hasLPM ( false ) , m_hasLPMX ( false ) , m_hasELPM ( false ) , m_hasELPMX ( false ) , m_hasSPM ( false ) , m_hasSPMX ( false ) , m_hasDES ( false ) , m_supportsRMW ( false ) , m_supportsMultiplication ( false ) , m_hasBREAK ( false ) , m_hasTinyEncoding ( false ) , m_hasMemMappedGPR ( false ) , m_FeatureSetDummy ( false ) , InstrInfo ( ) , FrameLowering ( ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS , TM ) ) , TSInfo ( ) { ParseSubtargetFeatures ( CPU , FS ) ; } </s>


<s> int getIORegRAMPZ ( void ) const { return 0x3b ; } </s>


<s> AVRSubtarget :: AVRSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , AVRTargetMachine & TM ) : AVRGenSubtargetInfo ( TT , CPU , FS ) , InstrInfo ( ) , FrameLowering ( ) , TLInfo ( TM ) , TSInfo ( ) , m_hasSRAM ( false ) , m_hasJMPCALL ( false ) , m_hasIJMPCALL ( false ) , m_hasEIJMPCALL ( false ) , m_hasADDSUBIW ( false ) , m_hasSmallStack ( false ) , m_hasMOVW ( false ) , m_hasLPM ( false ) , m_hasLPMX ( false ) , m_hasELPM ( false ) , m_hasELPMX ( false ) , m_hasSPM ( false ) , m_hasSPMX ( false ) , m_hasDES ( false ) , m_supportsRMW ( false ) , m_supportsMultiplication ( false ) , m_hasBREAK ( false ) , m_hasTinyEncoding ( false ) , ELFArch ( false ) , m_FeatureSetDummy ( false ) { ParseSubtargetFeatures ( CPU , FS ) ; } </s>


<s> AVRSubtarget :: AVRSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const AVRTargetMachine & TM ) : AVRGenSubtargetInfo ( TT , CPU , FS ) , ELFArch ( 0 ) , m_hasSRAM ( false ) , m_hasJMPCALL ( false ) , m_hasIJMPCALL ( false ) , m_hasEIJMPCALL ( false ) , m_hasADDSUBIW ( false ) , m_hasSmallStack ( false ) , m_hasMOVW ( false ) , m_hasLPM ( false ) , m_hasLPMX ( false ) , m_hasELPM ( false ) , m_hasELPMX ( false ) , m_hasSPM ( false ) , m_hasSPMX ( false ) , m_hasDES ( false ) , m_supportsRMW ( false ) , m_supportsMultiplication ( false ) , m_hasBREAK ( false ) , m_hasTinyEncoding ( false ) , m_FeatureSetDummy ( false ) , InstrInfo ( ) , FrameLowering ( ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS , TM ) ) , TSInfo ( ) { ParseSubtargetFeatures ( CPU , FS ) ; } </s>


<s> AVRSubtarget :: AVRSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const AVRTargetMachine & TM ) : AVRGenSubtargetInfo ( TT , CPU , CPU , FS ) , ELFArch ( 0 ) , m_hasSRAM ( false ) , m_hasJMPCALL ( false ) , m_hasIJMPCALL ( false ) , m_hasEIJMPCALL ( false ) , m_hasADDSUBIW ( false ) , m_hasSmallStack ( false ) , m_hasMOVW ( false ) , m_hasLPM ( false ) , m_hasLPMX ( false ) , m_hasELPM ( false ) , m_hasELPMX ( false ) , m_hasSPM ( false ) , m_hasSPMX ( false ) , m_hasDES ( false ) , m_supportsRMW ( false ) , m_supportsMultiplication ( false ) , m_hasBREAK ( false ) , m_hasTinyEncoding ( false ) , m_hasMemMappedGPR ( false ) , m_FeatureSetDummy ( false ) , InstrInfo ( ) , FrameLowering ( ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS , TM ) ) , TSInfo ( ) { ParseSubtargetFeatures ( CPU , CPU , FS ) ; } </s>


"every device must have an associate ELF architecture"

Gets the ELF architecture for the e_flags field of an ELF object file .


<s> const AVRInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> const AVRRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> AVRSubtarget & AVRSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , const TargetMachine & TM ) { ParseSubtargetFeatures ( CPU , CPU , FS ) ; return * this ; } </s>


<s> void AVRPassConfig :: addIRPasses ( ) { addPass ( createAVRShiftExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> void AVRPassConfig :: addPreSched2 ( ) { addPass ( createAVRExpandPseudoPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> void AVRPassConfig :: addPreEmitPass ( ) { addPass ( new TestMFP ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> TargetPassConfig * AVRTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new AVRPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( MachineBasicBlock & mbb : MF ) { dbgs ( ) << "\n" ; for ( MachineInstr & mi : mbb ) { dbgs ( ) << ">>>" << TII -> getName ( mi . getOpcode ( ) ) << "\n" ; } } } </s>


<s> bool AVRPassConfig :: addInstSelector ( ) { return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void AVRPassConfig :: addPreEmitPass ( ) { } </s>


<s> void AVRPassConfig :: addPreRegAlloc ( ) { } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> void AVRPassConfig :: addPreSched2 ( ) { } </s>


<s> bool AVRPassConfig :: addInstSelector ( ) { addPass ( createAVRISelDag ( getAVRTargetMachine ( ) , getOptLevel ( ) ) ) ; addPass ( createAVRFrameAnalyzerPass ( ) ) ; return false ; } </s>


<s> void AVRPassConfig :: addPreEmitPass ( ) { addPass ( & BranchRelaxationPassID ) ; } </s>


<s> void AVRPassConfig :: addPreRegAlloc ( ) { addPass ( createAVRDynAllocaSRPass ( ) ) ; } </s>


<s> void AVRPassConfig :: addPreSched2 ( ) { addPass ( createAVRRelaxMemPass ( ) ) ; addPass ( createAVRExpandPseudoPass ( ) ) ; } </s>


<s> TargetPassConfig * AVRTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new AVRPassConfig ( * this , PM ) ; } </s>


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return this -> TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> const AVRSubtarget * AVRTargetMachine :: getSubtargetImpl ( const Function & ) const { return & SubTarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool isMachineVerifierClean ( ) const override { return false ; } </s>

Returns true if the target is expected to pass all machine verifier checks .


<s> void AVRTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { Base :: Initialize ( Ctx , TM ) ; ProgmemDataSection = Ctx . getELFSection ( ".progmem.data" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; Progmem1DataSection = Ctx . getELFSection ( ".progmem1.data" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; Progmem2DataSection = Ctx . getELFSection ( ".progmem2.data" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; Progmem3DataSection = Ctx . getELFSection ( ".progmem3.data" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; Progmem4DataSection = Ctx . getELFSection ( ".progmem4.data" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; Progmem5DataSection = Ctx . getELFSection ( ".progmem5.data" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; } </s>

This method must be called before any actual lowering is done .


<s> void AVRTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { Base :: Initialize ( Ctx , TM ) ; ProgmemDataSection = Ctx . getELFSection ( ".progmem.data" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; } </s>


" Declaring this symbol tells the CRT that it should"

"copy all variables from program memory to RAM on startup"

"clear the zeroed data section on startup"

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s>
AddressSpace
getAddressSpace
(
T
*
V
)
{
auto
*
PT
=
cast
<
PointerType
>
(
V
->
getType
(
)
)
;
assert
(
PT
!=
nullptr
&&
"unexpected MemSDNode"
)
;
unsigned
AS
=
PT
->
getAddressSpace
(
)
;
if
(
AS
<
NumAddrSpaces
)
return
static_cast
<
AddressSpace
>
(
AS
)
;
return
NumAddrSpaces
;
}
</s>

Return the address space of the Pointer type .