<s> static const TargetRegisterClass * guessRegClass ( unsigned Reg , MachineRegisterInfo & MRI , const TargetRegisterInfo & TRI , const RegisterBankInfo & RBI ) { const RegisterBank * RegBank = RBI . getRegBank ( Reg , MRI , TRI ) ; assert ( RegBank && <STR_LIT> ) ; const unsigned Size = MRI . getType ( Reg ) . getSizeInBits ( ) ; assert ( ( RegBank -> getID ( ) == <STR_LIT> || RegBank -> getID ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( RegBank -> getID ( ) == <STR_LIT> ) { if ( Size == <NUM_LIT> ) return & <STR_LIT> ; else if ( Size == <NUM_LIT> ) return & <STR_LIT> ; else if ( Size == <NUM_LIT> ) return & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; } return &


<s> MIB -> eraseFromParent ( ) ; return true ; } auto LHSReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto RHSReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! validOpRegPair ( MRI , LHSReg , RHSReg , Helper . OperandSize , Helper . OperandRegBankID ) ) return false ; auto <ISA_LIT>Conds = getComparePreds ( Cond ) ; auto ZeroReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; putConstant ( I , ZeroReg , <NUM_LIT> ) ; if ( <ISA_LIT>Conds . second == <STR_LIT> ) { if ( ! insertComparison ( Helper , I , ResReg , <ISA_LIT>Conds . first , LHSReg , RHSReg , ZeroReg ) ) return false ; } else { auto IntermediateRes = MRI . createVirtualRegister ( & <STR_LIT> ) ; if ( ! insertComparison ( Helper , I , IntermediateRes , <ISA_LIT>Conds . first , LHSReg , RHSReg , ZeroReg ) ) return false ; if ( ! insertComparison ( Helper , I , ResReg , <ISA_LIT>Conds . second , LHSReg , RHSReg , IntermediateRes ) ) return false ; } MIB -> eraseFromParent (


<s> auto LHSReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto RHSReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! validOpRegPair ( MRI , LHSReg , RHSReg , Helper . OperandSize , Helper . OperandRegBankID ) ) return false ; auto <ISA_LIT>Conds = getComparePreds ( Cond ) ; auto ZeroReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; putConstant ( I , ZeroReg , <NUM_LIT> ) ; if ( <ISA_LIT>Conds . second == <STR_LIT> ) { if ( ! insertComparison ( Helper , I , ResReg , <ISA_LIT>Conds . first , LHSReg , RHSReg , ZeroReg ) ) return false ; } else { auto IntermediateRes = MRI . createVirtualRegister ( & <STR_LIT> ) ; if ( ! insertComparison ( Helper , I , IntermediateRes , <ISA_LIT>Conds .


<s> bool UseMovt = STI . useMovt ( MF ) ; unsigned Size = TM . getPointerSize ( <NUM_LIT> ) ; unsigned Alignment = <NUM_LIT> ; auto addOpsForConstantPoolLoad = [ & MF , Alignment , Size ] ( MachineInstrBuilder & MIB , const GlobalValue * GV , bool IsSBREL ) { assert ( MIB -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; auto ConstPool = MF . getConstantPool ( ) ; auto CPIndex = IsSBREL ? ConstPool -> getConstantPoolIndex ( <ISA_LIT>ConstantPoolConstant :: Create ( GV , <STR_LIT> ) , Alignment ) : ConstPool -> getConstantPoolIndex ( GV , Alignment ) ; MIB . addConstantPoolIndex ( CPIndex , <NUM_LIT> , <NUM_LIT> ) . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( MF ) , MachineMemOperand :: MOLoad , Size , Alignment ) ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } ; if ( TM . isPositionIndependent ( ) ) { bool Indirect = STI . isGVIndirectSymbol ( GV ) ; unsigned Opc = UseMovt && ! STI . isTargetELF ( ) ? ( Indirect ? <STR_LIT> : <STR_LIT> ) : ( Indirect ? <STR_LIT> : <STR_LIT> ) ; MIB -> setDesc ( TII . get ( Opc ) ) ; int TargetFlags = <STR_LIT> ; if ( STI . isTargetDarwin ( ) ) TargetFlags |= <STR_LIT> ; if ( STI . isGVInGOT ( GV ) ) TargetFlags |= <STR_LIT> ; MIB -> getOperand ( <NUM_LIT> ) . setTargetFlags (


<s> } if ( STI . isRWPI ( ) && ! isReadOnly ) { auto Offset = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstrBuilder OffsetMIB ; if ( UseMovt ) { OffsetMIB = BuildMI ( MBB , * MIB , MIB -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , Offset ) ; OffsetMIB . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; } else { OffsetMIB = BuildMI ( MBB , * MIB , MIB -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , Offset ) ; addOpsForConstantPoolLoad ( OffsetMIB , GV , true ) ; } if ( ! constrainSelectedInstRegOperands ( * OffsetMIB , TII , TRI , RBI ) ) return false ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; MIB -> RemoveOperand ( <NUM_LIT> ) ; MIB . addReg ( <STR_LIT> ) . addReg ( Offset ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ; } if ( STI . isTargetELF ( ) ) { if ( UseMovt ) { MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; } else { MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; MIB -> RemoveOperand ( <NUM_LIT> ) ; addOpsForConstantPoolLoad ( MIB , GV , false ) ; } } else if ( STI . isTargetMachO ( ) ) { if ( UseMovt ) MIB -> setDesc ( TII . get (


<s> unsigned <ISA_LIT>InstructionSelector :: selectLoadStoreOpCode ( unsigned Opc , unsigned RegBank , unsigned Size ) const { bool isStore = Opc == TargetOpcode :: G_STORE ; if ( RegBank == <STR_LIT> ) { switch ( Size ) { case <NUM_LIT> : case <NUM_LIT> : return isStore ? Opcodes . STORE8 : Opcodes . LOAD8 ; case


<s> static bool selectMergeValues ( MachineInstrBuilder & MIB , const <ISA_LIT>BaseInstrInfo & TII , MachineRegisterInfo & MRI , const TargetRegisterInfo & TRI , const RegisterBankInfo & RBI ) { assert ( TII . getSubtarget ( ) . hasVFP2 ( ) && <STR_LIT> ) ; unsigned VReg0 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg0 ; assert ( MRI . getType ( VReg0 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg0 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg2 = MIB -> getOperand (


<s> auto InsertBefore = std :: next ( MIB -> getIterator ( ) ) ; auto & DbgLoc = MIB -> getDebugLoc ( ) ; auto CondReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( validReg ( MRI , CondReg , <NUM_LIT> , <STR_LIT> ) && <STR_LIT> ) ; auto CmpI = BuildMI ( MBB , InsertBefore , DbgLoc , TII . get ( <STR_LIT> ) ) . addUse ( CondReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * CmpI , TII , TRI , RBI ) ) return false ; auto ResReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto TrueReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto FalseReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( validOpRegPair ( MRI , ResReg , TrueReg , <NUM_LIT> , <STR_LIT> ) && validOpRegPair ( MRI , TrueReg , FalseReg , <NUM_LIT> , <STR_LIT> ) && <STR_LIT> ) ; auto Mov1I = BuildMI ( MBB , InsertBefore , DbgLoc , TII . get ( <STR_LIT> ) ) . addDef ( ResReg ) . addUse ( TrueReg ) . addUse ( FalseReg ) . add ( predOps ( <STR_LIT> , <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * Mov1I , TII , TRI , RBI ) ) return false ; MIB -> eraseFromParent


<s> bool <ISA_LIT>InstructionSelector :: selectShift ( unsigned ShiftOpc , MachineInstrBuilder & MIB ) const { MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . addImm ( ShiftOpc ) ; MIB . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI ,


<s> if ( Size != <NUM_LIT> && Size != <NUM_LIT> ) return Opc ; if ( Opc == G_SEXT ) return Size == <NUM_LIT> ? Opcodes .


<s> assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg2 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg2 ; assert ( MRI . getType ( VReg2 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg2 , MRI , TRI ) -> getID ( ) ==


<s> unsigned VReg0 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg0 ; assert ( MRI . getType ( VReg0 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg0 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void


<s> bool <ISA_LIT>InstructionSelector :: validOpRegPair ( MachineRegisterInfo & MRI , unsigned LHSReg

, unsigned RHSReg , unsigned ExpectedSize , unsigned ExpectedRegBankID ) const {


<s> if ( MRI . getType ( Reg ) . getSizeInBits ( ) != ExpectedSize ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( RBI . getRegBank ( Reg , MRI , TRI ) -> getID ( ) != ExpectedRegBankID ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> bool <ISA_LIT>InstructionSelector :: validReg ( MachineRegisterInfo & MRI , unsigned Reg , unsigned ExpectedSize , unsigned ExpectedRegBankID ) const { if ( MRI . getType ( Reg ) . getSizeInBits ( ) != ExpectedSize ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( RBI . getRegBank ( Reg , MRI , TRI ) -> getID ( ) != ExpectedRegBankID ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } return true


<s> auto & MRI = MF . getRegInfo ( ) ; if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { if ( I . isCopy ( ) ) return selectCopy ( I , TII , MRI , TRI , RBI ) ; return true ; } MachineInstrBuilder MIB { MF , I } ; using namespace TargetOpcode ; switch ( I . getOpcode ( ) ) { case G_ADD : I . setDesc ( TII . get ( <STR_LIT> ) ) ; AddDefaultCC ( AddDefaultPred ( MIB ) ) ; break ; case G_FRAME_INDEX : I . setDesc ( TII . get ( <STR_LIT> ) ) ; AddDefaultCC ( AddDefaultPred ( MIB . addImm ( <NUM_LIT> ) ) ) ; break ; case G_LOAD : I . setDesc ( TII . get (


<s> assert ( ( DstSize == SrcSize || ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && DstSize <= SrcSize ) ) && <STR_LIT> ) ; assert ( RegBank -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( ! RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( )


<s> const RegisterBank * RegBank = RBI . getRegBank ( Reg , MRI , TRI ) ; assert ( RegBank && <STR_LIT> ) ; const unsigned Size = MRI . getType ( Reg ) . getSizeInBits ( ) ; assert ( ( RegBank -> getID ( ) == <STR_LIT> || RegBank -> getID ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( RegBank -> getID ( ) == <STR_LIT> ) { if ( Size == <NUM_LIT> ) return & <STR_LIT> ; else if ( Size == <NUM_LIT> )


<s> static bool selectCopy ( MachineInstr & I , const TargetInstrInfo & TII , MachineRegisterInfo & MRI , const TargetRegisterInfo & TRI , const RegisterBankInfo & RBI ) { unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DstReg ) ) return true ; const TargetRegisterClass * RC = guessRegClass ( DstReg , MRI , TRI , RBI ) ; if ( ! RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return


<s> if ( STI . isTargetDarwin ( ) ) TargetFlags |= <STR_LIT> ; if ( STI . isGVInGOT ( GV ) ) TargetFlags |= <STR_LIT> ; MIB -> getOperand ( <NUM_LIT> ) . setTargetFlags ( TargetFlags ) ; if ( Indirect ) MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getGOT ( MF ) , MachineMemOperand :: MOLoad , TM . getPointerSize ( ) , Alignment ) ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ; } bool isReadOnly = STI . getTargetLowering ( ) -> isReadOnly ( GV ) ; if ( STI . isROPI ( ) && isReadOnly ) { unsigned Opc = UseMovt ? <STR_LIT> : <STR_LIT> ; MIB -> setDesc ( TII . get ( Opc ) ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ; } if ( STI . isRWPI ( ) && ! isReadOnly ) { auto Offset = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstrBuilder OffsetMIB ; if ( UseMovt ) { OffsetMIB = BuildMI ( MBB , * MIB , MIB -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , Offset ) ; OffsetMIB . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; } else { OffsetMIB = BuildMI ( MBB , * MIB , MIB -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , Offset ) ; addOpsForConstantPoolLoad ( OffsetMIB , GV , true ) ; } if ( ! constrainSelectedInstRegOperands ( * OffsetMIB , TII , TRI , RBI ) ) return false ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; MIB -> RemoveOperand ( <NUM_LIT> ) ; MIB . addReg ( <STR_LIT> ) . addReg ( Offset ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI


<s> switch ( Size ) { case <NUM_LIT> : case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; default : return Opc ; } } if ( RegBank == <STR_LIT> ) { switch ( Size ) { case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; default : return Opc ; } } return Opc


<s> case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; default : return Opc ; } } if ( RegBank


<s> if ( Opc == G_SEXT ) return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( Opc == G_ZEXT ) return Size ==


<s> bool <ISA_LIT>InstructionSelector :: validReg ( MachineRegisterInfo & MRI , unsigned Reg , unsigned ExpectedSize , unsigned ExpectedRegBankID ) const { if ( MRI . getType ( Reg ) . getSizeInBits ( ) != ExpectedSize ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( RBI . getRegBank ( Reg , MRI , TRI ) -> getID ( ) != ExpectedRegBankID ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } return true


<s> if ( ! constrainSelectedInstRegOperands ( * SubI , TII , TRI , RBI ) ) return false ; } break ; } case <NUM_LIT> : case <NUM_LIT> : { unsigned NewOpc = selectSimpleExtOpc ( I . getOpcode ( ) , SrcSize ) ; I . setDesc ( TII . get ( NewOpc ) ) ; MIB . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; break ; } default : DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } break ; } case G_ADD : I . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; break ; case G_FRAME_INDEX : I . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; break ; case G_LOAD : { LLT ValTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; const auto ValSize = ValTy . getSizeInBits ( ) ; if ( ValSize != <NUM_LIT> && ValSize != <NUM_LIT> && ValSize != <NUM_LIT> && ValSize != <NUM_LIT> ) return false ; const auto NewOpc = selectLoadOpCode ( ValSize ) ; I . setDesc ( TII . get ( NewOpc ) ) ; if ( NewOpc == <STR_LIT> ) MIB . addReg ( <NUM_LIT>


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT>


<s> if ( Opc == G_SEXT ) return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( Opc == G_ZEXT ) return Size == <NUM_LIT> ? <STR_LIT>


<s> ( void ) SrcSize ; assert ( ( DstSize == SrcSize || ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && DstSize <= SrcSize ) ) && <STR_LIT> ) ; assert ( ( RegBank -> getID ( ) == <STR_LIT> || RegBank -> getID ( ) == <STR_LIT> ) && <STR_LIT> ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( RegBank -> getID ( ) == <STR_LIT> ) { if ( DstSize == <NUM_LIT> ) RC = & <STR_LIT> ; else if ( DstSize == <NUM_LIT> ) RC = & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; } if ( ! RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return false


<s> static bool selectExtract ( MachineInstrBuilder & MIB , const <ISA_LIT>BaseInstrInfo & TII , MachineRegisterInfo & MRI , const TargetRegisterInfo & TRI , const RegisterBankInfo & RBI ) { assert ( TII . getSubtarget ( ) . hasVFP2 ( ) && <STR_LIT> ) ; unsigned VReg0 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg0 ; assert ( MRI . getType ( VReg0 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg0 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg2 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg2 ; assert ( MRI . getType ( VReg2 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg2 , MRI


<s> LLT Ty = MRI . getType ( MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned ValSize = Ty . getSizeInBits ( ) ; if ( ValSize == <NUM_LIT> ) { if ( TII . getSubtarget ( ) . useNEONForSinglePrecisionFP ( ) ) return false ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; } else { assert ( ValSize == <NUM_LIT> && <STR_LIT>


<s> unsigned VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg2 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg2 ; assert ( MRI . getType ( VReg2 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg2 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; MIB -> RemoveOperand ( <NUM_LIT> ) ; MIB -> RemoveOperand ( <NUM_LIT> ) ; MIB -> setDesc ( TII . get (


<s> bool <ISA_LIT>InstructionSelector :: insertComparison ( CmpConstants Helper , InsertInfo I , unsigned ResReg , <STR_LIT> Cond , unsigned LHSReg , unsigned RHSReg , unsigned PrevRes ) const { auto CmpI = BuildMI ( I . MBB , I . InsertBefore , I . DbgLoc , TII . get ( Helper . ComparisonOpcode ) ) . addUse ( LHSReg ) . addUse ( RHSReg ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * CmpI , TII , TRI , RBI ) ) return false ; if ( Helper . ReadFlagsOpcode != <STR_LIT> ) { auto ReadI = BuildMI ( I . MBB , I . InsertBefore , I . DbgLoc , TII .

get ( Helper . ReadFlagsOpcode ) ) . add ( predOps ( <STR_LIT> ) ) ;


<s> ( void ) BuildMI ( I . MBB , I . InsertBefore , I . DbgLoc , TII . get ( Opcodes . MOVi ) ) . addDef ( DestReg ) . addImm ( Constant )

. add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ;


<s> void <ISA_LIT>InstructionSelector :: renderVFPF32Imm ( MachineInstrBuilder & NewInstBuilder , const MachineInstr & OldInst , int OpIdx ) const { assert ( OldInst . getOpcode ( ) == TargetOpcode :: G_FCONSTANT && OpIdx == - <NUM_LIT> && <STR_LIT> ) ; APFloat FPImmValue = OldInst . getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; int FPImmEncoding = <STR_LIT> (


<s> APFloat FPImmValue = OldInst . getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; int FPImmEncoding = <STR_LIT> ( FPImmValue ) ; assert ( FPImmEncoding != - <NUM_LIT> &&


<s> APFloat FPImmValue = OldInst . getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; int FPImmEncoding = <STR_LIT> ( FPImmValue


<s> void <ISA_LIT>InstructionSelector :: renderVFPF64Imm ( MachineInstrBuilder & NewInstBuilder , const MachineInstr & OldInst , int OpIdx ) const { assert ( OldInst . getOpcode ( ) == TargetOpcode :: G_FCONSTANT && OpIdx == - <NUM_LIT> && <STR_LIT> ) ; APFloat FPImmValue = OldInst . getOperand ( <NUM_LIT> ) . getFPImm ( ) ->


<s> const InsertInfo I ( MIB ) ; auto ResReg = MIB . getReg ( <NUM_LIT> ) ; if ( ! validReg ( MRI , ResReg , <NUM_LIT> , <STR_LIT> ) ) return false ; auto Cond = static_cast < CmpInst :: Predicate > ( MIB -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; if ( Cond == CmpInst :: FCMP_TRUE || Cond == CmpInst :: FCMP_FALSE ) { putConstant ( I , ResReg , Cond == CmpInst :: FCMP_TRUE ? <NUM_LIT> : <NUM_LIT> ) ; MIB -> eraseFromParent ( ) ; return true ; } auto LHSReg = MIB . getReg ( <NUM_LIT> ) ; auto RHSReg = MIB . getReg ( <NUM_LIT> ) ; if ( ! validOpRegPair ( MRI , LHSReg , RHSReg , Helper . OperandSize , Helper . OperandRegBankID ) ) return false ; auto <ISA_LIT>Conds = getComparePreds ( Cond ) ; auto ZeroReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; putConstant ( I , ZeroReg , <NUM_LIT> ) ; if ( <ISA_LIT>Conds . second == <STR_LIT> ) { if ( ! insertComparison ( Helper , I , ResReg , <ISA_LIT>Conds . first , LHSReg , RHSReg , ZeroReg ) ) return false ; } else { auto IntermediateRes = MRI . createVirtualRegister ( & <STR_LIT> ) ; if ( ! insertComparison ( Helper , I , IntermediateRes , <ISA_LIT>Conds . first , LHSReg , RHSReg , ZeroReg ) ) return false ; if ( ! insertComparison ( Helper , I , ResReg , <ISA_LIT>Conds . second , LHSReg , RHSReg , IntermediateRes ) ) return false ; } MIB -> eraseFromParent ( ) ; return true


<s> ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; Register VReg2 = MIB . getReg ( <NUM_LIT> ) ; ( void ) VReg2 ; assert ( MRI . getType ( VReg2 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg2 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; return


<s> auto InsertBefore = std :: next ( MIB -> getIterator ( ) ) ; auto & DbgLoc = MIB -> getDebugLoc ( ) ; auto CondReg = MIB . getReg ( <NUM_LIT> ) ; assert ( validReg ( MRI , CondReg , <NUM_LIT> , <STR_LIT> ) && <STR_LIT> ) ; auto CmpI = BuildMI ( MBB , InsertBefore , DbgLoc , TII . get ( Opcodes . TSTri ) ) . addUse ( CondReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * CmpI , TII , TRI , RBI ) ) return false ; auto ResReg = MIB . getReg ( <NUM_LIT> ) ; auto TrueReg = MIB . getReg ( <NUM_LIT> ) ; auto FalseReg = MIB . getReg ( <NUM_LIT> ) ; assert ( validOpRegPair ( MRI , ResReg , TrueReg , <NUM_LIT> , <STR_LIT> ) && validOpRegPair ( MRI , TrueReg , FalseReg , <NUM_LIT> , <STR_LIT> ) && <STR_LIT> ) ; auto Mov1I = BuildMI ( MBB , InsertBefore , DbgLoc , TII . get ( Opcodes . MOVCCr ) ) . addDef ( ResReg ) . addUse ( TrueReg ) . addUse ( FalseReg ) . add ( predOps ( <STR_LIT> , <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * Mov1I , TII , TRI , RBI ) ) return false ; MIB -> eraseFromParent (


<s> auto InsertBefore = std :: next ( MIB -> getIterator ( ) ) ; auto & DbgLoc = MIB -> getDebugLoc ( ) ; auto CondReg = MIB . getReg ( <NUM_LIT> ) ; assert ( validReg ( MRI , CondReg , <NUM_LIT> , <STR_LIT> ) && <STR_LIT> ) ; auto CmpI = BuildMI ( MBB , InsertBefore , DbgLoc , TII . get ( Opcodes . TSTri ) ) . addUse ( CondReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * CmpI , TII , TRI , RBI ) ) return false ; auto ResReg = MIB . getReg ( <NUM_LIT> ) ; auto TrueReg = MIB . getReg ( <NUM_LIT> ) ; auto FalseReg = MIB . getReg (


<s> assert ( MRI . getType ( VReg0 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg0 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; Register VReg1 = MIB . getReg ( <NUM_LIT> ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI .

getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ;


<s> Register VReg1 = MIB . getReg ( <NUM_LIT> ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; Register VReg2 = MIB . getReg ( <NUM_LIT> ) ; ( void ) VReg2 ; assert ( MRI . getType ( VReg2 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg2 , MRI , TRI )


<s> assert ( validOpRegPair ( MRI , ResReg , TrueReg , <NUM_LIT> , <STR_LIT> ) && validOpRegPair ( MRI , TrueReg , FalseReg , <NUM_LIT> , <STR_LIT> ) && <STR_LIT> ) ; auto Mov1I = BuildMI ( MBB , InsertBefore , DbgLoc , TII . get ( Opcodes . MOVCCr ) ) . addDef ( ResReg ) . addUse ( TrueReg ) . addUse ( FalseReg ) . add ( predOps ( <STR_LIT> , <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * Mov1I , TII , TRI , RBI ) ) return false ; MIB -> eraseFromParent ( ) ; return true


<s> assert ( RegBank && <STR_LIT> ) ; const unsigned DstSize = MRI . getType ( DstReg ) . getSizeInBits ( ) ; ( void ) DstSize ; unsigned SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcSize = RBI . getSizeInBits ( SrcReg , MRI , TRI ) ; ( void ) SrcSize ; assert ( DstSize <= SrcSize && <STR_LIT> ) ; assert ( ( RegBank -> getID ( ) == <STR_LIT> || RegBank -> getID ( )


<s> assert ( TII . getSubtarget ( ) . hasVFP2 ( ) && <STR_LIT> ) ; unsigned VReg0 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg0 ; assert ( MRI . getType ( VReg0 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg0 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( MIB -> getOperand ( <NUM_LIT> ) . getImm ( ) % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; MIB -> getOperand ( <NUM_LIT> ) . setImm ( MIB -> getOperand ( <NUM_LIT> )


<s> MachineInstrBuilder MIB { MF , I } ; bool isSExt = false ; using namespace TargetOpcode ; switch ( I . getOpcode ( ) ) { case G_SEXT : isSExt = true ; LLVM_FALLTHROUGH ; case G_ZEXT : { LLT DstTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( DstTy . getSizeInBits ( ) != <NUM_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } LLT SrcTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned SrcSize = SrcTy . getSizeInBits ( ) ; switch ( SrcSize ) { case <NUM_LIT> : { I . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; if ( isSExt ) { unsigned SExtResult = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AndResult = MRI . createVirtualRegister ( & <STR_LIT> ) ; I . getOperand ( <NUM_LIT> ) . setReg ( AndResult ) ; auto InsertBefore = std :: next ( I . getIterator ( ) ) ; auto SubI = BuildMI ( MBB , InsertBefore , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( SExtResult ) . addUse ( AndResult ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; if ( ! constrainSelectedInstRegOperands ( * SubI , TII , TRI , RBI ) ) return false ; } break ; } case <NUM_LIT> : case <NUM_LIT> : { unsigned NewOpc = selectSimpleExtOpc ( I . getOpcode ( ) , SrcSize ) ; if ( NewOpc == I . getOpcode ( ) ) return false ; I . setDesc ( TII . get ( NewOpc ) ) ; MIB . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; break ; } default : DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } break ; } case G_ADD : case G_GEP : I . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; break ; case G_FADD : if ( ! selectFAdd ( MIB , TII , MRI ) ) return false ; break ; case G_FRAME_INDEX : I . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; break ; case G_CONSTANT : { unsigned Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI . getType ( Reg ) .

getSizeInBits ( ) != <NUM_LIT> ) return false ;


<s> I . getOperand ( <NUM_LIT> ) . setReg ( AndResult ) ; auto InsertBefore = std :: next ( I . getIterator ( ) ) ; auto SubI = BuildMI ( MBB , InsertBefore , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( SExtResult ) . addUse ( AndResult ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; if ( ! constrainSelectedInstRegOperands ( * SubI , TII , TRI , RBI ) ) return false ; } break ; } case <NUM_LIT> : case <NUM_LIT> : { unsigned NewOpc = selectSimpleExtOpc ( I . getOpcode ( ) , SrcSize ) ; if ( NewOpc == I . getOpcode ( ) ) return false ; I . setDesc ( TII . get ( NewOpc ) ) ; MIB . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; break ; } default : DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } break ; } case G_ADD : case G_GEP : I . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; break ; case G_FADD : if ( ! selectFAdd ( MIB , TII , MRI ) ) return false ; break ; case G_FRAME_INDEX : I . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; break ; case G_CONSTANT : { unsigned Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI . getType ( Reg ) . getSizeInBits ( ) != <NUM_LIT> ) return false ; assert ( RBI . getRegBank ( Reg , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; I . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; break ; } case G_STORE : case G_LOAD :


<s> APFloat FPImmValue = OldInst . getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; int FPImmEncoding = <STR_LIT> ( FPImmValue ) ; assert ( FPImmEncoding != - <NUM_LIT> && <STR_LIT> ) ; NewInstBuilder . addImm (


<s> Register VReg0 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg0 ; assert ( MRI . getType ( VReg0 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg0 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; Register VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; Register VReg2 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg2 ; assert ( MRI . getType ( VReg2 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg2 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; MIB -> setDesc ( TII .


<s> static bool selectMergeValues ( MachineInstrBuilder & MIB , const <ISA_LIT>BaseInstrInfo & TII , MachineRegisterInfo & MRI , const TargetRegisterInfo & TRI , const RegisterBankInfo & RBI ) { assert ( TII . getSubtarget ( ) . hasVFP2Base ( ) && <STR_LIT> ) ; Register VReg0 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg0 ; assert ( MRI . getType ( VReg0 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg0 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; Register VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; Register VReg2 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg2 ; assert ( MRI . getType ( VReg2 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg2 , MRI , TRI


<s> auto CondReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( validReg ( MRI , CondReg , <NUM_LIT> , <STR_LIT> ) && <STR_LIT> ) ; auto CmpI = BuildMI ( MBB , InsertBefore , DbgLoc , TII . get ( Opcodes . TSTri ) ) . addUse ( CondReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * CmpI , TII , TRI , RBI ) ) return false ; auto ResReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto TrueReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto FalseReg = MIB -> getOperand ( <NUM_LIT> ) .


<s> assert ( validReg ( MRI , CondReg , <NUM_LIT> , <STR_LIT> ) && <STR_LIT> ) ; auto CmpI = BuildMI ( MBB , InsertBefore , DbgLoc , TII . get ( Opcodes . TSTri ) ) . addUse ( CondReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * CmpI , TII , TRI , RBI ) ) return false ; auto ResReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto TrueReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto FalseReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( validOpRegPair ( MRI , ResReg , TrueReg , <NUM_LIT> , <STR_LIT> ) && validOpRegPair ( MRI , TrueReg , FalseReg , <NUM_LIT> , <STR_LIT> ) && <STR_LIT> ) ; auto Mov1I = BuildMI ( MBB , InsertBefore , DbgLoc , TII . get ( Opcodes . MOVCCr ) ) . addDef ( ResReg ) . addUse ( TrueReg ) . addUse ( FalseReg ) . add ( predOps ( <STR_LIT> , <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * Mov1I , TII , TRI , RBI ) ) return false ; MIB -> eraseFromParent ( ) ; return true


<s> ( void ) VReg0 ; assert ( MRI . getType ( VReg0 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg0 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; Register VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; Register VReg2 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg2 ; assert ( MRI . getType ( VReg2 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg2 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . add ( predOps


<s> assert ( TII . getSubtarget ( ) . hasVFP2Base ( ) && <STR_LIT> ) ; unsigned VReg0 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg0 ; assert ( MRI . getType ( VReg0 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg0 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg2 = MIB -> getOperand (


<s> assert ( MRI . getType ( VReg0 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg0 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI


<s> ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg2 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg2 ; assert ( MRI . getType ( VReg2 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank

( VReg2 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ;


<s> auto InsertBefore = std :: next ( MIB -> getIterator ( ) ) ; auto & DebugLoc = MIB -> getDebugLoc ( ) ; auto Mov0I = BuildMI ( MBB , InsertBefore , DebugLoc , TII . get ( <STR_LIT> ) ) . addDef ( MRI . createVirtualRegister ( & <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; if ( ! constrainSelectedInstRegOperands ( * Mov0I , TII , TRI , RBI ) ) return false ; auto LHSReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto RHSReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MRI . getType ( LHSReg ) == MRI . getType ( RHSReg ) && MRI . getType ( LHSReg ) . getSizeInBits

( ) == <NUM_LIT> && MRI . getType ( RHSReg ) . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ;


<s> } ; if ( TM . isPositionIndependent ( ) ) { bool Indirect = STI . isGVIndirectSymbol ( GV ) ; bool UseOpcodeThatLoads = Indirect && ! STI . isThumb ( ) ; unsigned Opc = UseMovt && ! STI . isTargetELF ( ) ? ( UseOpcodeThatLoads ? ( unsigned ) <STR_LIT> : Opcodes . MOV_ga_pcrel ) : ( UseOpcodeThatLoads ? ( unsigned ) <STR_LIT> : Opcodes . LDRLIT_ga_pcrel ) ; MIB -> setDesc ( TII . get ( Opc ) ) ; int TargetFlags = <STR_LIT> ; if ( STI . isTargetDarwin ( ) ) TargetFlags |= <STR_LIT> ; if ( STI . isGVInGOT ( GV ) ) TargetFlags |= <STR_LIT> ; MIB -> getOperand ( <NUM_LIT> ) . setTargetFlags ( TargetFlags ) ; if ( Indirect ) { if ( ! UseOpcodeThatLoads ) { auto ResultReg = MIB . getReg ( <NUM_LIT> ) ; auto AddressReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MIB -> getOperand ( <NUM_LIT> ) . setReg ( AddressReg ) ; auto InsertBefore = std :: next ( MIB -> getIterator ( ) ) ; auto MIBLoad = BuildMI ( MBB , InsertBefore , MIB -> getDebugLoc ( ) , TII . get ( Opcodes . LOAD32 ) ) . addDef ( ResultReg ) . addReg ( AddressReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; addGOTMemOperand ( MIBLoad ) ; if ( ! constrainSelectedInstRegOperands ( * MIBLoad , TII , TRI , RBI ) ) return false ; } else { addGOTMemOperand ( MIB ) ; } } return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ; } bool isReadOnly = STI . getTargetLowering ( ) -> isReadOnly ( GV ) ; if ( STI . isROPI ( ) && isReadOnly ) { unsigned Opc = UseMovt ? Opcodes . MOV_ga_pcrel : Opcodes . LDRLIT_ga_pcrel ; MIB -> setDesc ( TII . get ( Opc ) ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ; } if ( STI . isRWPI ( ) && ! isReadOnly ) { auto Offset = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstrBuilder OffsetMIB ; if (


<s> auto & MBB = * MIB -> getParent ( ) ; auto InsertBefore = std :: next ( MIB -> getIterator ( ) ) ; auto & DebugLoc = MIB -> getDebugLoc ( ) ; auto CondReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MRI . getType ( CondReg ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( CondReg , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; auto CmpI = BuildMI ( MBB , InsertBefore , DebugLoc , TII . get ( <STR_LIT> ) ) . addUse ( CondReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * CmpI , TII , TRI , RBI ) ) return false ; auto ResReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto TrueReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto FalseReg = MIB -> getOperand (


<s> SDLoc SL ( N ) ; SDVTList VTList = CurDAG -> getVTList ( <STR_LIT> ) ; EVT LdType = N -> getValueType ( <NUM_LIT> ) ; unsigned ImmSum = <NUM_LIT> ; uint16_t MathOpc = ( Inc ) ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; i < N -> getNumOperands ( ) ; ++ i ) { SDValue Val = N -> getOperand ( i ) ; Ptr = CurDAG -> getNode ( MathOpc , SL , VTList , Ptr , Offset ) ; ImmSum += <NUM_LIT> ; Value * NullPtr = <NUM_LIT> ; MachineMemOperand * MMO = new MachineMemOperand ( MachinePointerInfo ( NullPtr , ImmSum ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; UsePtr = ( B ) ? PrevPtr : Ptr ; SDValue ResNode ; if ( Ld ) { if ( Val -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) { Chain = Val -> getOperand ( <NUM_LIT> ) ; } RegisterSDNode * RegNode = dyn_cast < RegisterSDNode > ( Val -> getOperand ( <NUM_LIT> ) ) ; const MCRegisterInfo * RI = Dec -> getDisassembler ( ) -> getMCDirector ( ) -> getMCRegisterInfo ( ) ; if ( RI -> isSubRegisterEq ( RI -> getProgramCounter ( ) , RegNode -> getReg ( ) ) ) { ResNode = CurDAG -> getNode ( <STR_LIT> , SL , <STR_LIT> , CurDAG -> getRoot ( ) ) ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Chain ) ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Ptr ) ; CurDAG -> setRoot ( ResNode ) ; return ; } else { ResNode = CurDAG -> getLoad ( LdType , SL , Chain , UsePtr , MachinePointerInfo :: getConstantPool ( ) , false , false , true , <NUM_LIT> ) ; SDValue C2R = CurDAG -> getCopyToReg ( ResNode . getValue ( <NUM_LIT> ) , SL , RegNode -> getReg ( ) , ResNode ) ; Chain = C2R ; if ( Val -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) { CurDAG -> ReplaceAllUsesOfValueWith ( Val , ResNode ) ; CurDAG -> ReplaceAllUsesOfValueWith ( Val . getValue ( <NUM_LIT> )


<s> bool <ISA_LIT>InvISelDAG :: SelectAddrMode2OffsetImm ( SDNode * Op , SDValue N , SDValue & Offset


<s> bool <ISA_LIT>InvISelDAG :: SelectAddrMode2OffsetImmPre ( SDNode * Op , SDValue N , SDValue & Offset


<s> bool <ISA_LIT>InvISelDAG :: SelectAddrMode2OffsetReg ( SDNode * Op , SDValue N ,


<s> bool <ISA_LIT>InvISelDAG :: SelectAddrMode2OffsetReg ( SDNode * Op , SDValue N , SDValue & Offset , SDValue


<s> bool <ISA_LIT>InvISelDAG :: SelectAddrMode3 ( SDValue N , SDValue & Base , SDValue & Offset , SDValue & Opc ) { return


<s> bool <ISA_LIT>InvISelDAG :: SelectAddrMode3Offset ( SDNode * Op , SDValue N , SDValue & Offset , SDValue & Opc ) { return


<s> bool <ISA_LIT>InvISelDAG :: SelectAddrMode5 ( SDValue N , SDValue & Base , SDValue &


<s> bool <ISA_LIT>InvISelDAG :: SelectAddrMode6Offset ( SDNode * Op , SDValue N


<s> Base = CurDAG -> getNode ( <STR_LIT> , SDLoc ( N . getNode ( ) ) , N . getValueType ( ) , Base , OffImm ) ; return


<s> bool <ISA_LIT>InvISelDAG :: SelectAddrModePC ( SDValue N , SDValue & Offset , SDValue & Label ) { return false


<s> bool <ISA_LIT>InvISelDAG :: SelectAddrModePC ( SDValue N , SDValue &


<s> bool <ISA_LIT>InvISelDAG :: SelectAddrOffsetNone ( SDValue


<s> unsigned Opcode = <NUM_LIT> ; bool Match = false ; if ( LoadedVT == <STR_LIT> && isPre && SelectAddrMode2OffsetImmPre ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Opcode = <STR_LIT> ; Match = true ; } else if ( LoadedVT == <STR_LIT> && ! isPre && SelectAddrMode2OffsetImm ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Opcode = <STR_LIT> ; Match = true ; } else if ( LoadedVT == <STR_LIT> && SelectAddrMode2OffsetReg ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Opcode = isPre ? <STR_LIT> : <STR_LIT> ; Match = true ; } else if ( LoadedVT == <STR_LIT> && SelectAddrMode3Offset ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = ( LD -> getExtensionType ( ) == <STR_LIT> ) ? ( isPre ? <STR_LIT> : <STR_LIT> ) : ( isPre ? <STR_LIT> : <STR_LIT> ) ; } else if ( LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) { if ( LD -> getExtensionType ( ) == <STR_LIT> ) { if ( SelectAddrMode3Offset ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } } else { if ( isPre && SelectAddrMode2OffsetImmPre ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match =


<s> bool <ISA_LIT>InvISelDAG :: SelectImmShifterOperand ( SDValue N , SDValue & BaseReg , SDValue & Opc , bool CheckProfitability ) { return true


<s> OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { if ( SelectT2AddrModeImm8 ( N , Base , OffImm ) ) return false ; int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC


<s> if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( ( RHSC >= - <NUM_LIT> ) && ( RHSC < <NUM_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ; return


<s> bool <ISA_LIT>InvISelDAG :: SelectT2AddrModeImm8Offset ( SDNode * Op , SDValue N


<s> bool <ISA_LIT>InvISelDAG :: SelectT2AddrModeImm8Offset ( SDNode * Op , SDValue N , SDValue & OffImm ) { return false


<s> bool <ISA_LIT>InvISelDAG :: SelectT2AddrModeSoReg ( SDValue N , SDValue & Base , SDValue & OffReg , SDValue & ShImm ) { return true


<s> bool <ISA_LIT>InvISelDAG :: SelectT2AddrModeSoReg ( SDValue N , SDValue & Base

, SDValue & OffReg , SDValue & ShImm ) {


<s> SDValue Offset ; bool isPre = ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ; unsigned Opcode = <NUM_LIT> ; bool Match = false ; if ( SelectT2AddrModeImm8Offset ( N , LD -> getOffset ( ) , Offset ) ) { switch ( LoadedVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; default : return NULL ; } Match = true ; } if ( Match ) { SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ; SDValue Ops [ ] = { Base , Offset , getAL ( CurDAG )

, CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , Chain } ;


<s> bool <ISA_LIT>InvISelDAG :: SelectT2ShifterOperandReg ( SDValue N , SDValue & BaseReg , SDValue & Opc ) { return


<s> return SelectThumbAddrModeImm5S ( N , <NUM_LIT> , Base


<s> bool <ISA_LIT>InvISelDAG :: SelectThumbAddrModeImm5S2 ( SDValue N , SDValue & Base , SDValue & OffImm ) { return SelectThumbAddrModeImm5S ( N , <NUM_LIT> , Base ,


<s> bool <ISA_LIT>InvISelDAG :: SelectThumbAddrModeImm5S2 ( SDValue N , SDValue &


<s> bool <ISA_LIT>InvISelDAG :: SelectThumbAddrModeImm5S4 ( SDValue N , SDValue & Base ,


<s> bool <ISA_LIT>InvISelDAG :: SelectThumbAddrModeImm5S4 ( SDValue N , SDValue & Base , SDValue & OffImm ) { return SelectThumbAddrModeImm5S ( N , <NUM_LIT> , Base ,


<s> if ( Scale == <NUM_LIT> ) { SDValue TmpBase , TmpOffImm ; if ( SelectThumbAddrModeSP ( N , TmpBase , TmpOffImm ) ) return false ; if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; RegisterSDNode * LHSR = dyn_cast < RegisterSDNode > ( N . getOperand (


<s> bool <ISA_LIT>InvISelDAG :: SelectThumbAddrModeRI5S2 ( SDValue N , SDValue & Base , SDValue & Offset ) { return SelectThumbAddrModeRI ( N , Base


<s> bool <ISA_LIT>InvISelDAG :: SelectThumbAddrModeRI5S4 ( SDValue N , SDValue & Base , SDValue & Offset ) { return SelectThumbAddrModeRI ( N , Base , Offset ,


<s> bool <ISA_LIT>InvISelDAG :: SelectThumbAddrModeRI5S4 ( SDValue N , SDValue & Base , SDValue


<s> int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return


<s> case <STR_LIT> : return visitBR_JT ( N ) ; case <STR_LIT> : return visitBR2_JT ( N ) ; case <STR_LIT> : return visitRET_FLAG ( N ) ; case <STR_LIT> : return visitINTRET_FLAG ( N ) ; case <STR_LIT> : return visitPIC_ADD ( N ) ; case <STR_LIT> : return visitCMP ( N ) ; case <STR_LIT> : return visitCMN ( N ) ; case <STR_LIT> : return visitCMPZ ( N ) ; case <STR_LIT> : return visitCMPFP ( N ) ; case <STR_LIT> : return visitCMPFPw0 ( N ) ; case <STR_LIT> : return visitFMSTAT ( N ) ; case <STR_LIT> : return visitCMOV ( N ) ; case <STR_LIT> : return visitBCC_i64 ( N ) ; case <STR_LIT> : return visitRBIT ( N ) ; case <STR_LIT> : return visitFTOSI ( N ) ; case <STR_LIT> : return visitFTOUI ( N ) ; case <STR_LIT> : return visitSITOF ( N ) ; case <STR_LIT> : return visitUITOF ( N ) ; case <STR_LIT> : return visitSRL_FLAG ( N ) ; case <STR_LIT> : return visitSRA_FLAG ( N ) ; case <STR_LIT> : return visitRRX ( N ) ; case <STR_LIT> : return visitADDC ( N ) ; case <STR_LIT> : return visitADDE ( N ) ; case <STR_LIT> : return visitSUBC ( N ) ; case <STR_LIT> : return visitSUBE ( N ) ; case <STR_LIT> : return visitVMOVRRD ( N ) ; case <STR_LIT> : return visitVMOVDRR ( N ) ; case <STR_LIT> : return visitEH_SJLJ_SETJMP ( N ) ; case <STR_LIT> : return visitEH_SJLJ_LONGJMP ( N ) ; case <STR_LIT> : return visitTC_RETURN ( N ) ; case <STR_LIT> : return visitTHREAD_POINTER ( N ) ; case <STR_LIT> : return visitDYN_ALLOC ( N ) ; case <STR_LIT> : return visitMEMBARRIER_MCR ( N ) ; case <STR_LIT> : return visitPRELOAD ( N ) ; case <STR_LIT> : return visitVCEQ ( N ) ; case <STR_LIT> : return visitVCEQZ ( N ) ; case <STR_LIT> : return visitVCGE ( N ) ; case <STR_LIT> : return visitVCGEZ ( N ) ; case <STR_LIT> : return visitVCLEZ ( N ) ; case <STR_LIT> : return visitVCGEU ( N ) ; case <STR_LIT> : return visitVCGT ( N ) ; case <STR_LIT> : return visitVCGTZ ( N ) ; case <STR_LIT> : return visitVCLTZ ( N ) ; case <STR_LIT> : return visitVCGTU ( N ) ; case <STR_LIT> : return visitVTST ( N ) ; case <STR_LIT> : return visitVSHL ( N ) ; case <STR_LIT> : return visitVSHRs ( N ) ; case <STR_LIT> : return visitVSHRu ( N ) ; case <STR_LIT> : return visitVRSHRs ( N ) ; case <STR_LIT> : return visitVRSHRu ( N ) ; case <STR_LIT> : return visitVQSHLs ( N ) ; case <STR_LIT> : return visitVQSHLu ( N ) ; case <STR_LIT> : return visitVQSHLsu ( N ) ; case <STR_LIT> : return visitVQSHRNs ( N ) ; case <STR_LIT> : return visitVQSHRNu ( N ) ; case <STR_LIT> : return visitVQSHRNsu ( N


<s> case <STR_LIT> : return visitFTOUI ( N ) ; case <STR_LIT> : return visitSITOF ( N ) ; case <STR_LIT> : return visitUITOF ( N ) ; case <STR_LIT> : return visitSRL_FLAG ( N ) ; case <STR_LIT> : return visitSRA_FLAG ( N ) ; case <STR_LIT> : return visitRRX ( N ) ; case <STR_LIT> : return visitADDC ( N ) ; case <STR_LIT> : return visitADDE ( N ) ; case <STR_LIT> : return visitSUBC ( N ) ; case <STR_LIT> : return visitSUBE ( N ) ; case <STR_LIT> : return visitVMOVRRD ( N ) ; case <STR_LIT> : return visitVMOVDRR ( N ) ; case <STR_LIT> : return visitEH_SJLJ_SETJMP ( N ) ; case <STR_LIT> : return visitEH_SJLJ_LONGJMP ( N ) ; case <STR_LIT> : return visitTC_RETURN ( N ) ; case <STR_LIT> : return visitTHREAD_POINTER ( N ) ; case <STR_LIT> : return visitDYN_ALLOC ( N ) ; case <STR_LIT> : return visitMEMBARRIER_MCR ( N ) ; case <STR_LIT> : return visitPRELOAD ( N ) ; case <STR_LIT> : return visitVCEQ ( N ) ; case <STR_LIT> : return visitVCEQZ ( N ) ; case <STR_LIT> : return visitVCGE ( N ) ; case <STR_LIT> : return visitVCGEZ ( N ) ; case <STR_LIT> : return visitVCLEZ ( N ) ; case <STR_LIT> : return visitVCGEU ( N ) ; case <STR_LIT> : return visitVCGT ( N ) ; case <STR_LIT> : return visitVCGTZ ( N ) ; case <STR_LIT> : return visitVCLTZ ( N ) ; case <STR_LIT> : return visitVCGTU ( N ) ; case <STR_LIT> : return visitVTST ( N ) ; case <STR_LIT> : return visitVSHL ( N ) ; case <STR_LIT> : return visitVSHRs ( N ) ; case <STR_LIT> : return visitVSHRu ( N ) ; case <STR_LIT> : return visitVRSHRs ( N ) ; case <STR_LIT> : return visitVRSHRu ( N ) ; case <STR_LIT> : return visitVQSHLs ( N ) ; case <STR_LIT> : return visitVQSHLu ( N ) ; case <STR_LIT> : return visitVQSHLsu ( N ) ; case <STR_LIT> : return visitVQSHRNs ( N ) ; case <STR_LIT> : return visitVQSHRNu ( N ) ; case <STR_LIT> : return visitVQSHRNsu ( N ) ; case <STR_LIT> : return visitVQRSHRNs ( N ) ; case <STR_LIT> : return visitVQRSHRNu ( N ) ; case <STR_LIT> : return visitVQRSHRNsu ( N ) ; case <STR_LIT> : return visitVSLI ( N ) ; case <STR_LIT> : return visitVSRI ( N ) ; case <STR_LIT> : return visitVGETLANEu ( N ) ; case <STR_LIT> : return visitVGETLANEs ( N ) ; case <STR_LIT> : return visitVMOVIMM ( N ) ; case <STR_LIT> : return visitVMVNIMM ( N ) ; case <STR_LIT> : return visitVMOVFPIMM ( N ) ; case <STR_LIT> : return visitVDUP ( N ) ; case <STR_LIT> : return visitVDUPLANE ( N ) ; case <STR_LIT> : return visitVEXT ( N ) ; case <STR_LIT> : return visitVREV64 ( N )


<s> Value * <ISA_LIT>IREmitter :: visitADDC ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> Value * <ISA_LIT>IREmitter :: visitBFI ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> Value * <ISA_LIT>IREmitter :: visitBR_JT ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> Value * <ISA_LIT>IREmitter :: visitBR_JT ( const


<s> std :: string FName = Dec -> getDisassembler ( ) -> getFunctionName ( Tgt ) ; Module * Mod = IRB -> GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; FunctionType * FT = FunctionType :: get ( Type :: getPrimitiveType ( Mod -> getContext ( ) , Type :: VoidTyID ) , false ) ; Twine TgtAddr ( Tgt ) ; AttributeSet AS ; AS = AS . addAttribute ( Mod -> getContext ( ) , AttributeSet :: FunctionIndex , <STR_LIT> , TgtAddr . str ( ) ) ; Value * Proto = Mod -> getOrInsertFunction ( FName , FT , AS ) ; IRB -> CreateCall ( dyn_cast < Value > ( Proto ) ) ; VisitMap [ N


<s> Module * Mod = IRB -> GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; FunctionType * FT = FunctionType :: get ( Type :: getPrimitiveType ( Mod -> getContext ( ) , Type :: VoidTyID ) , false ) ; Twine TgtAddr ( Tgt ) ; AttributeSet AS ; AS = AS . addAttribute ( Mod -> getContext ( ) , AttributeSet :: FunctionIndex , <STR_LIT> , TgtAddr . str ( ) ) ; Value * Proto = Mod -> getOrInsertFunction ( FName , FT , AS ) ; IRB -> CreateCall ( dyn_cast < Value > ( Proto ) ) ; VisitMap [ N


<s> Value * <ISA_LIT>IREmitter :: visitCALL_NOLINK ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> Value * <ISA_LIT>IREmitter :: visitCALL_PRED ( const SDNode * N


<s> Value * <ISA_LIT>IREmitter :: visitCMOV ( const SDNode * N


<s> Value * <ISA_LIT>IREmitter :: visitCMOV ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> Value * <ISA_LIT>IREmitter :: visitCMP ( const SDNode * N


<s> Value * <ISA_LIT>IREmitter :: visitCMPFP ( const SDNode *


<s> Value * <ISA_LIT>IREmitter :: visitCMPFPw0 ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> Value * <ISA_LIT>IREmitter :: visitCMPZ ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> Value * <ISA_LIT>IREmitter :: visitDYN_ALLOC ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> Value * <ISA_LIT>IREmitter :: visitEH_SJLJ_LONGJMP ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> Value * <ISA_LIT>IREmitter :: visitEH_SJLJ_LONGJMP ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> Value * <ISA_LIT>IREmitter :: visitEH_SJLJ_SETJMP (


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> Value * <ISA_LIT>IREmitter :: visitFMAX ( const


<s> Value * <ISA_LIT>IREmitter :: visitFMAX ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> Value * <ISA_LIT>IREmitter :: visitFMIN ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> Value * <ISA_LIT>IREmitter :: visitFMSTAT (


<s> Value * <ISA_LIT>IREmitter :: visitFMSTAT ( const SDNode * N


<s> Value * <ISA_LIT>IREmitter :: visitFTOUI ( const


<s> Value * <ISA_LIT>IREmitter :: visitINTRET_FLAG ( const SDNode


<s> Value * <ISA_LIT>IREmitter :: visitMEMBARRIER_MCR ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> Value * <ISA_LIT>IREmitter :: visitPRELOAD ( const SDNode *


<s> Value * <ISA_LIT>IREmitter :: visitRBIT ( const SDNode * N


<s> Value * <ISA_LIT>IREmitter :: visitRET_FLAG ( const SDNode * N ) { return IRB -> CreateRetVoid


<s> Value * <ISA_LIT>IREmitter :: visitRRX ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> Value * <ISA_LIT>IREmitter :: visitSRA_FLAG ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> Value * <ISA_LIT>IREmitter :: visitSRA_FLAG ( const SDNode


<s> Value * <ISA_LIT>IREmitter :: visitSRL_FLAG ( const SDNode


<s> Value * <ISA_LIT>IREmitter :: visittCALL ( const SDNode


<s> Value * <ISA_LIT>IREmitter :: visitTHREAD_POINTER ( const


<s> Value * <ISA_LIT>IREmitter :: visitUMLAL ( const SDNode


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> Value * <ISA_LIT>IREmitter :: visitVBSL ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> Value * <ISA_LIT>IREmitter :: visitVCGE ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> Value * <ISA_LIT>IREmitter :: visitVCGEU ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> Value * <ISA_LIT>IREmitter :: visitVCGTZ ( const SDNode *


<s> Value * <ISA_LIT>IREmitter :: visitVCLEZ ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> Value * <ISA_LIT>IREmitter :: visitVCLTZ ( const SDNode


<s> Value * <ISA_LIT>IREmitter :: visitVCLTZ ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> Value * <ISA_LIT>IREmitter :: visitVDUP ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> Value * <ISA_LIT>IREmitter :: visitVEXT ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> Value * <ISA_LIT>IREmitter :: visitVGETLANEs ( const SDNode *


<s> Value * <ISA_LIT>IREmitter :: visitVGETLANEu ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> Value * <ISA_LIT>IREmitter :: visitVLD2DUP ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> Value * <ISA_LIT>IREmitter :: visitVLD2DUP_UPD ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> Value * <ISA_LIT>IREmitter :: visitVLD2LN_UPD (


<s> Value * <ISA_LIT>IREmitter :: visitVLD3DUP_UPD ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> Value * <ISA_LIT>IREmitter :: visitVLD3DUP_UPD ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> Value * <ISA_LIT>IREmitter :: visitVLD3LN_UPD ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL


<s> Value * <ISA_LIT>IREmitter :: visitVLD4DUP ( const SDNode


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> Value * <ISA_LIT>IREmitter :: visitVLD4_UPD ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> Value * <ISA_LIT>IREmitter :: visitVMINNM ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> Value * <ISA_LIT>IREmitter :: visitVMOVDRR (


<s> Value * <ISA_LIT>IREmitter :: visitVMOVIMM ( const


<s> Value * <ISA_LIT>IREmitter :: visitVMOVRRD ( const SDNode * N


<s> Value * <ISA_LIT>IREmitter :: visitVMOVRRD ( const SDNode *


<s> Value * <ISA_LIT>IREmitter :: visitVMULLs ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> Value * <ISA_LIT>IREmitter :: visitVMULLs ( const SDNode *


<s> Value * <ISA_LIT>IREmitter :: visitVMULLu ( const SDNode * N


<s> Value * <ISA_LIT>IREmitter :: visitVORRIMM (


<s> Value * <ISA_LIT>IREmitter :: visitVQRSHRNs (


<s> Value * <ISA_LIT>IREmitter :: visitVQRSHRNs ( const SDNode * N


<s> Value * <ISA_LIT>IREmitter :: visitVQRSHRNsu ( const SDNode *


<s> Value * <ISA_LIT>IREmitter :: visitVQRSHRNu ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> Value * <ISA_LIT>IREmitter :: visitVQSHRNs ( const SDNode * N


<s> Value * <ISA_LIT>IREmitter :: visitVQSHRNs ( const SDNode *


<s> Value * <ISA_LIT>IREmitter :: visitVQSHRNsu ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> Value * <ISA_LIT>IREmitter :: visitVRSHRN (


<s> Value * <ISA_LIT>IREmitter :: visitVSHL ( const SDNode


<s> Value * <ISA_LIT>IREmitter :: visitVSHL (


<s> Value * <ISA_LIT>IREmitter :: visitVSHLLi ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> Value * <ISA_LIT>IREmitter :: visitVSHRs ( const


<s> Value * <ISA_LIT>IREmitter :: visitVSHRu ( const SDNode * N


<s> Value * <ISA_LIT>IREmitter :: visitVSLI (


<s> Value * <ISA_LIT>IREmitter :: visitVSRI ( const SDNode *


<s> Value * <ISA_LIT>IREmitter :: visitVST2_UPD ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> Value * <ISA_LIT>IREmitter :: visitVST3_UPD ( const


<s> Value * <ISA_LIT>IREmitter :: visitVST4_UPD ( const


<s> Value * <ISA_LIT>IREmitter :: visitVTBL1 ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> Value * <ISA_LIT>IREmitter :: visitVTBL2 ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> Value * <ISA_LIT>IREmitter :: visitVTRN ( const


<s> Value * <ISA_LIT>IREmitter :: visitVTRN ( const SDNode *


<s> Value * <ISA_LIT>IREmitter :: visitVUZP ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> Value * <ISA_LIT>IREmitter :: visitVZIP ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> Value * <ISA_LIT>IREmitter :: visitWrapper ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> Value * <ISA_LIT>IREmitter :: visitWrapper ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL


<s> Value * <ISA_LIT>IREmitter :: visitWrapperJT (


<s> Value * <ISA_LIT>IREmitter :: visitWrapperJT ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> Value * <ISA_LIT>IREmitter :: visitWrapperPIC ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> bool <ISA_LIT>DAGToDAGISel :: canExtractShiftFromMul ( const SDValue & N , unsigned MaxShift , unsigned & PowerOfTwo , SDValue & NewMulConst ) const { assert ( N . getOpcode ( ) == <STR_LIT> ) ; assert ( MaxShift > <NUM_LIT> ) ; if ( ! N . hasOneUse ( ) ) return false ; ConstantSDNode * MulConst = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! MulConst ) return false ; if ( ! MulConst -> hasOneUse ( ) ) return false ; unsigned MulConstVal = MulConst -> getZExtValue ( ) ; if ( MulConstVal == <NUM_LIT> ) return false ; PowerOfTwo = MaxShift ; while ( ( MulConstVal % ( <NUM_LIT> << PowerOfTwo ) ) != <NUM_LIT> ) { -- PowerOfTwo ; if ( PowerOfTwo == <NUM_LIT> )


<s> assert ( MaxShift > <NUM_LIT> ) ; if ( ! N . hasOneUse ( ) ) return false ; ConstantSDNode * MulConst = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! MulConst ) return false ; if ( ! MulConst -> hasOneUse ( ) ) return false ; unsigned MulConstVal = MulConst -> getZExtValue


<s> if ( Subtarget -> hasV6T2Ops ( ) && Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( ~ Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return <NUM_LIT> ; } else { if ( <STR_LIT> ( Val ) != - <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( ~ Val ) != - <NUM_LIT> ) return <NUM_LIT> ; if ( Subtarget -> hasV6T2Ops ( ) &&


<s> SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE ,


<s> SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT


<s> SDLoc dl ( V0 . getNode ( ) ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> ,


<s> SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT> ,


<s> SDNode * <ISA_LIT>DAGToDAGISel :: createQuadDRegsNode ( EVT VT , SDValue V0 , SDValue V1 , SDValue V2 , SDValue V3 ) { SDLoc dl ( V0 . getNode ( ) ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , dl ,


<s> SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 , V2 , SubReg2 , V3 , SubReg3 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT


<s> return CurDAG -> getTargetConstant ( ( uint64_t )


<s> if ( Mask == - <NUM_LIT> ) return - <NUM_LIT> ; return Mask << <NUM_LIT> ; } if ( Reg != <STR_LIT> && Reg != <STR_LIT> ) { return - <NUM_LIT> ; } if ( Flags . empty ( ) || Flags == <STR_LIT> ) return Mask | <NUM_LIT> ; for ( char Flag : Flags ) { int FlagVal ; switch ( Flag ) { case 'c' : FlagVal = <NUM_LIT> ; break ; case 'x' : FlagVal = <NUM_LIT> ; break ; case 's' : FlagVal = <NUM_LIT> ; break ; case 'f' : FlagVal = <NUM_LIT> ; break ; default : FlagVal =


<s> if ( Mask == - <NUM_LIT> ) return - <NUM_LIT> ; return Mask << <NUM_LIT> ; } if ( Reg != <STR_LIT> && Reg != <STR_LIT> ) { return - <NUM_LIT> ; } if ( Flags . empty ( ) || Flags == <STR_LIT> ) return Mask | <NUM_LIT> ; for ( char Flag : Flags ) { int FlagVal ; switch ( Flag ) { case 'c' : FlagVal = <NUM_LIT> ; break ; case 'x' : FlagVal = <NUM_LIT> ; break ; case 's' : FlagVal = <NUM_LIT> ; break ; case 'f' : FlagVal = <NUM_LIT> ; break ; default : FlagVal = <NUM_LIT> ; } if ( ! FlagVal || ( Mask & FlagVal ) ) return - <NUM_LIT> ; Mask |= FlagVal ; } if ( Reg == <STR_LIT> ) Mask |= <NUM_LIT> ; return


<s> inline SDValue getI32Imm ( unsigned Imm


<s> inline SDValue getI32Imm ( unsigned Imm , SDLoc dl ) { return CurDAG -> getTargetConstant ( Imm , dl


<s> bool AllIntFields = true ; for ( StringRef Field : Fields ) { unsigned IntField ; AllIntFields &= ! Field . trim ( <STR_LIT> ) . getAsInteger ( <NUM_LIT> , IntField ) ; Ops . push_back ( CurDAG -> getTargetConstant ( IntField , DL , <STR_LIT> ) ) ; } assert ( AllIntFields &&


<s> static inline int getMClassFlagsMask ( StringRef Flags , bool hasDSP ) { if ( Flags . empty ( ) ) return <NUM_LIT> | ( int


<s> return StringSwitch < int > ( Flags ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case (

<STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ;


<s> if ( ( SYSmvalue < <NUM_LIT> && Mask == - <NUM_LIT> ) || ( SYSmvalue > <NUM_LIT> && ! Flags . empty ( ) ) ) return - <NUM_LIT> ; if ( ! Subtarget -> hasDSP ( ) && ( Mask & <NUM_LIT> ) ) return - <NUM_LIT> ; if ( SYSmvalue < <NUM_LIT> ) return SYSmvalue | Mask << <NUM_LIT> ; return SYSmvalue


<s> static inline int getMClassRegisterSYSmValueMask ( StringRef RegString ) { return StringSwitch < int > ( RegString . lower ( ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT>

, <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ;


<s> return StringSwitch < int > ( RegString . lower ( ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> )

. Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ;


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> SDValue <ISA_LIT>DAGToDAGISel :: GetVLDSTAlign ( SDValue Align , SDLoc dl , unsigned NumVecs , bool is64BitVector ) { unsigned NumRegs = NumVecs ; if ( ! is64BitVector && NumVecs <


<s> if ( OptLevel == CodeGenOpt :: None ) return true ; if ( ! CheckVMLxHazard ) return true ; if ( ! Subtarget -> isCortexA7 ( ) && ! Subtarget -> isCortexA8 ( ) && ! Subtarget -> isCortexA9 ( ) && ! Subtarget -> isSwift ( ) ) return true ; if ( ! N -> hasOneUse ( )


<s> if ( ! CheckVMLxHazard ) return true ; if ( ! Subtarget -> isCortexA7 ( ) && ! Subtarget -> isCortexA8 ( ) && ! Subtarget -> isCortexA9 ( ) && ! Subtarget -> isSwift ( ) ) return true ; if ( ! N -> hasOneUse ( ) ) return false ; SDNode * Use = * N -> use_begin ( ) ; if ( Use -> getOpcode ( ) == <STR_LIT>


<s> default : return false ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return


<s> case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> :


<s> if ( ! Subtarget -> hasV6T2Ops ( ) ) return ; bool isThumb2 = Subtarget -> isThumb ( ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = & * I ++ ; if ( N -> getOpcode ( ) != <STR_LIT> ) continue ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; unsigned And_imm = <NUM_LIT> ; if ( ! isOpcWithIntImmediate ( N1 . getNode ( ) , <STR_LIT> , And_imm ) ) { if ( isOpcWithIntImmediate ( N0 . getNode ( ) , <STR_LIT> , And_imm ) ) std :: swap ( N0 , N1 ) ; } if ( ! And_imm ) continue ; unsigned TZ = countTrailingZeros ( And_imm ) ; if ( TZ != <NUM_LIT> && TZ != <NUM_LIT> ) continue ; And_imm >>= TZ ; if ( And_imm & ( And_imm + <NUM_LIT> ) ) continue ; SDValue Srl = N1 . getOperand ( <NUM_LIT> ) ; unsigned Srl_imm = <NUM_LIT> ; if ( ! isOpcWithIntImmediate ( Srl . getNode ( ) , <STR_LIT> , Srl_imm ) || ( Srl_imm <= <NUM_LIT> ) ) continue ; SDValue CPTmp0 ; SDValue CPTmp1 ; SDValue CPTmp2 ; if ( isThumb2 ) { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) ) continue ; } else { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) || SelectRegShifterOperand ( N0 , CPTmp0 , CPTmp1 , CPTmp2 ) ) continue ; } Srl = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Srl ) , <STR_LIT> , Srl . getOperand ( <NUM_LIT> ) , CurDAG -> getConstant ( Srl_imm + TZ , SDLoc ( Srl ) , <STR_LIT> ) ) ; N1 = CurDAG -> getNode ( <STR_LIT> , SDLoc ( N1 ) , <STR_LIT> , Srl , CurDAG -> getConstant ( And_imm ,


<s> CurDAG -> RepositionNode ( N . getNode ( ) -> getIterator ( ) , M . getNode ( ) ) ; CurDAG -> ReplaceAllUsesWith ( N , M


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; SelectionDAGISel :: runOnMachineFunction


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF


<s> int Val ; if ( isScaledConstantInRange ( N , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Val ) ) { Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , Val , <STR_LIT> ) , SDLoc ( Op ) , <STR_LIT> ) ; return true ; } return


<s> if ( isScaledConstantInRange ( N , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Val ) ) { Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , Val , <STR_LIT> ) , SDLoc ( Op ) , <STR_LIT> ) ; return true ; } return false


<s> if ( isScaledConstantInRange ( N , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Val ) ) { if ( AddSub == <STR_LIT> ) Val *= - <NUM_LIT> ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( Val , SDLoc ( Op ) , <STR_LIT> ) ; return true


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrMode2OffsetReg ( SDNode * Op , SDValue N , SDValue & Offset , SDValue & Opc ) { unsigned Opcode = Op -> getOpcode ( ) ; <STR_LIT> AM = ( Opcode == <STR_LIT> ) ? cast < LoadSDNode > ( Op ) -> getAddressingMode ( ) : cast < StoreSDNode > ( Op ) -> getAddressingMode ( ) ; <STR_LIT> AddSub = ( AM == <STR_LIT> || AM == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; int Val ; if ( isScaledConstantInRange ( N , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Val ) ) return false ; Offset = N ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOpcode


<s> Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , Val ) , SDLoc ( Op ) , <STR_LIT> ) ; return true ; } Offset = N ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , <NUM_LIT>


<s> Addr = N ; unsigned Alignment = <NUM_LIT> ; MemSDNode * MemN = cast < MemSDNode > ( Parent ) ; if ( isa < LSBaseSDNode > ( MemN ) || ( ( MemN -> getOpcode ( ) == <STR_LIT> || MemN -> getOpcode (

) == <STR_LIT> ) && MemN -> getConstantOperandVal ( MemN -> getNumOperands ( ) - <NUM_LIT> ) == <NUM_LIT> ) ) {


<s> Addr = N ; unsigned Alignment = <NUM_LIT> ; MemSDNode * MemN = cast < MemSDNode > ( Parent ) ; if ( isa < LSBaseSDNode > ( MemN ) || ( ( MemN -> getOpcode ( ) == <STR_LIT> || MemN -> getOpcode ( ) == <STR_LIT> ) && MemN -> getConstantOperandVal ( MemN -> getNumOperands


<s> const ConstantSDNode * CN = cast < ConstantSDNode > ( N ) ; Pred = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , SDLoc ( N ) , <STR_LIT> ) ; Reg = CurDAG -> getRegister ( <STR_LIT> ,


<s> SDValue T1 = CurDAG -> getCopyToReg ( Sub1 , dl , Reg1 , Sub1 , T0 . getValue ( <NUM_LIT> ) ) ; std :: vector < SDValue > Ops ( GU -> op_begin ( ) , GU -> op_end ( ) - <NUM_LIT> ) ; Ops . push_back ( T1 . getValue ( <NUM_LIT> ) ) ; CurDAG -> UpdateNodeOperands ( GU , Ops ) ; } else { SDValue Chain = AsmNodeOperands [ InlineAsm :: Op_InputChain ] ; SDValue T0 = CurDAG -> getCopyFromReg ( Chain , dl , Reg0 , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ; SDValue T1 = CurDAG -> getCopyFromReg ( Chain , dl , Reg1 , <STR_LIT> , T0 . getValue ( <NUM_LIT> ) ) ; SDValue Pair = SDValue ( createGPRPairNode ( <STR_LIT> , T0 , T1 ) , <NUM_LIT> ) ; unsigned GPVR = MRI . createVirtualRegister ( & <STR_LIT> ) ; PairedReg = CurDAG -> getRegister ( GPVR , <STR_LIT> ) ; Chain = CurDAG -> getCopyToReg ( T1 , dl , GPVR , Pair , T1 . getValue ( <NUM_LIT> ) ) ; AsmNodeOperands [ InlineAsm :: Op_InputChain ] = Chain ; Glue = Chain . getValue ( <NUM_LIT> ) ; } Changed = true ; if ( PairedReg . getNode ( ) ) { OpChanged [ OpChanged . size ( ) - <NUM_LIT> ] = true ; Flag = InlineAsm :: getFlagWord ( Kind , <NUM_LIT> ) ; if ( IsTiedToChangedOp ) Flag = InlineAsm :: getFlagWordForMatchingOp ( Flag , DefIdx ) ; else Flag = InlineAsm :: getFlagWordForRegClass ( Flag , <STR_LIT> ) ; AsmNodeOperands [ AsmNodeOperands . size ( ) - <NUM_LIT> ] = CurDAG -> getTargetConstant ( Flag , dl , <STR_LIT> ) ; AsmNodeOperands . push_back ( PairedReg ) ; i += <NUM_LIT> ; } } if ( Glue . getNode ( ) ) AsmNodeOperands . push_back ( Glue ) ; if ( ! Changed ) return nullptr ; SDValue New = CurDAG -> getNode ( <STR_LIT> , SDLoc ( N ) , CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) , AsmNodeOperands ) ; New -> setNodeId ( -


<s> case InlineAsm :: Constraint_Q : case InlineAsm :: Constraint_Um : case InlineAsm :: Constraint_Un : case InlineAsm :: Constraint_Uq : case InlineAsm :: Constraint_Us : case InlineAsm :: Constraint_Ut : case InlineAsm :: Constraint_Uv : case InlineAsm :: Constraint_Uy : OutOps . push_back ( Op ) ; return false ; } return true


<s> case InlineAsm :: Constraint_Uq : case InlineAsm :: Constraint_Us : case InlineAsm :: Constraint_Ut : case InlineAsm :: Constraint_Uv : case InlineAsm :: Constraint_Uy : OutOps . push_back ( Op ) ; return


<s> } unsigned Opcode = StringSwitch < unsigned > ( SpecialReg ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Opcode ) { if ( ! Subtarget -> hasVFP2 ( ) ) return nullptr ; if ( Opcode == <STR_LIT> && ! Subtarget -> hasFP<ISA_LIT>v8 ( ) ) return nullptr ; Ops = { getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , <STR_LIT> , Ops ) ; } if ( Subtarget -> isMClass ( ) ) { int SYSmValue = getMClassRegisterMask ( SpecialReg , <STR_LIT> , true , Subtarget ) ; if ( SYSmValue == - <NUM_LIT> ) return nullptr ; SDValue Ops [ ] = { CurDAG -> getTargetConstant ( SYSmValue , DL , <STR_LIT> ) , getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , Ops ) ; } if ( SpecialReg == <STR_LIT> || SpecialReg == <STR_LIT> ) { Ops = { getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( IsThumb2 ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , Ops ) ; } if ( SpecialReg == <STR_LIT>


<s> unsigned ShImmVal = <NUM_LIT> ; ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( RHS ) return false ; ShReg = N . getOperand ( <NUM_LIT> ) ; if ( CheckProfitability && ! isShifterOpProfitable ( N , ShOpcVal ,


<s> OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; if ( N . getOpcode ( ) != <STR_LIT> || ! CurDAG -> isBaseWithConstantOffset ( N ) ) return true ; ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! RHS ) return true ; uint32_t RHSC = ( int ) RHS -> getZExtValue


<s> unsigned Opcode = Op -> getOpcode ( ) ; <STR_LIT> AM = ( Opcode == <STR_LIT> ) ? cast < LoadSDNode > ( Op ) -> getAddressingMode ( ) : cast < StoreSDNode > ( Op ) -> getAddressingMode ( ) ; int


<s> if ( N . getOpcode ( ) == <STR_LIT> ) { return false ; } else if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; } else { Base = N ; } OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , Scale , <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; OffImm = CurDAG -> getTargetConstant ( RHSC , SDLoc (


<s> unsigned And_imm = <NUM_LIT> ; if ( N -> getOpcode ( ) == <STR_LIT> ) { if ( isOpcWithIntImmediate ( N , <STR_LIT> , And_imm ) ) { if ( And_imm & ( And_imm + <NUM_LIT> ) ) return nullptr ; unsigned Srl_imm = <NUM_LIT> ; if ( isOpcWithIntImmediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , Srl_imm ) ) { assert ( Srl_imm > <NUM_LIT> && Srl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Width = countTrailingOnes ( And_imm ) - <NUM_LIT> ; unsigned LSB = Srl_imm ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( ( LSB + Width + <NUM_LIT> ) == N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ) { if ( Subtarget -> isThumb ( ) ) { Opc = isSigned ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( LSB , dl , <STR_LIT> ) , getAL ( CurDAG , dl ) , Reg0 , Reg0 } ; return CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , Ops ) ; } <STR_LIT> ShOpcVal = <STR_LIT> ( <STR_LIT> ) ; SDValue ShOpc = CurDAG -> getTargetConstant ( <STR_LIT> ( ShOpcVal , LSB ) , dl , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , ShOpc , getAL ( CurDAG , dl ) , Reg0 , Reg0 } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops ) ; } SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( LSB , dl , <STR_LIT> ) , CurDAG -> getTargetConstant ( Width , dl , <STR_LIT> ) , getAL ( CurDAG , dl ) , Reg0 } ; return CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> ,


<s> SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDNode * VLd ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( ( NumVecs <= <NUM_LIT> ) && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs > <NUM_LIT> && ! isVLDfixed ( Opc ) ) || ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLd = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; } else { EVT AddrTy = MemAddr . getValueType ( ) ; SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , ResTy ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , Reg0 , ImplDef , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTy , AddrTy , <STR_LIT> , OpsA ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; Ops . push_back ( SDValue ( VLdA , <NUM_LIT> ) ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; assert ( isa < ConstantSDNode > ( Inc . getNode ( ) ) && <STR_LIT> ) ; ( void ) Inc ; Ops . push_back (


<s> Alignment = ( Alignment & - Alignment ) ; if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; } Align = CurDAG -> getTargetConstant ( Alignment , dl , <STR_LIT> ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } std :: vector < EVT > ResTys ; if ( IsLoad ) { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } SDValue SuperReg ; SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) { if ( is64BitVector ) SuperReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; } else { SDValue V2 = N -> getOperand ( Vec0Idx


<s> if ( NumVecs == <NUM_LIT> ) RegSeq = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else { SDValue V2 = N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; RegSeq = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } SmallVector < SDValue , <NUM_LIT> > Ops ; if ( IsExt ) Ops . push_back ( N -> getOperand ( <NUM_LIT>


<s> if ( ! Ops . empty ( ) ) { unsigned Opcode ; if ( Ops . size ( ) == <NUM_LIT> ) { Opcode = IsThumb2 ? <STR_LIT> : <STR_LIT> ; Ops . insert ( Ops . begin ( ) + <NUM_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; } else { assert ( Ops . size ( ) == <NUM_LIT> && <STR_LIT> ) ; Opcode = IsThumb2 ? <STR_LIT> : <STR_LIT> ; SDValue WriteValue [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; Ops . insert ( Ops . begin ( ) + <NUM_LIT> , WriteValue , WriteValue + <NUM_LIT> ) ; } Ops . push_back ( getAL ( CurDAG , DL ) ) ; Ops . push_back ( CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; return CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , Ops ) ; } std :: string SpecialReg = RegString -> getString ( ) . lower ( ) ; int BankedReg = getBankedRegisterMask ( SpecialReg ) ; if ( BankedReg != - <NUM_LIT> ) { Ops = { CurDAG -> getTargetConstant ( BankedReg , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( IsThumb2 ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , Ops ) ; } unsigned Opcode = StringSwitch < unsigned > ( SpecialReg ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Opcode ) { if ( ! Subtarget -> hasVFP2 ( ) ) return nullptr ; Ops = { N -> getOperand ( <NUM_LIT> ) , getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , Ops ) ; } SmallVector < StringRef , <NUM_LIT> > Fields


<s> return new <ISA_LIT>DAGToDAGISel ( TM


<s> SDNode * <ISA_LIT>DAGToDAGISel :: createDRegPairNode ( EVT VT , SDValue V0 , SDValue V1 ) { SDLoc dl ( V0 . getNode ( ) ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT>


<s> SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 ,


<s> SDNode * <ISA_LIT>DAGToDAGISel :: createQRegPairNode ( EVT VT , SDValue V0 , SDValue V1 ) { SDLoc dl ( V0 . getNode ( ) ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl


<s> SDNode * <ISA_LIT>DAGToDAGISel :: createQuadDRegsNode ( EVT VT , SDValue V0 , SDValue V1 , SDValue V2 , SDValue V3 ) { SDLoc dl ( V0 . getNode ( ) ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT>


<s> SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 , V2 , SubReg2 , V3 , SubReg3 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl ,


<s> SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 , V2 , SubReg2 , V3 , SubReg3 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT


<s> SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> if ( Alignment >= <NUM_LIT> && NumRegs == <NUM_LIT> ) Alignment = <NUM_LIT> ; else if ( Alignment >= <NUM_LIT> && ( NumRegs == <NUM_LIT> || NumRegs == <NUM_LIT> ) )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } return


<s> SDNode * Use = * N -> use_begin ( ) ; if ( Use -> getOpcode ( ) == <STR_LIT> ) return true ; if ( Use -> isMachineOpcode ( ) ) { const <ISA_LIT>BaseInstrInfo * TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( TM . getInstrInfo ( ) ) ; const MCInstrDesc & MCID = TII -> get ( Use -> getMachineOpcode ( ) ) ; if ( MCID . mayStore (


<s> bool <ISA_LIT>DAGToDAGISel :: hasNoVMLxHazardUse ( SDNode * N ) const { if ( OptLevel == CodeGenOpt :: None ) return true ; if ( ! CheckVMLxHazard ) return true ; if ( ! Subtarget -> isCortexA8 ( ) && ! Subtarget -> isCortexA9 ( ) && ! Subtarget -> isSwift ( ) ) return true ; if ( ! N -> hasOneUse ( ) ) return false ; SDNode * Use = * N -> use_begin ( ) ; if ( Use -> getOpcode ( ) == <STR_LIT> ) return true ; if ( Use -> isMachineOpcode


<s> return isInt32Immediate ( N . getNode


<s> static bool isInt32Immediate ( SDValue N , unsigned & Imm ) { return isInt32Immediate ( N . getNode ( ) , Imm


<s> static bool isOpcWithIntImmediate ( SDNode * N , unsigned Opc , unsigned & Imm ) { return N -> getOpcode ( ) == Opc && isInt32Immediate ( N -> getOperand ( <NUM_LIT> ) . getNode


<s> return N -> getOpcode ( ) == Opc && isInt32Immediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( )


<s> if ( ! C ) return false ; ScaledConstant = ( int ) C -> getZExtValue ( ) ; if ( ( ScaledConstant % Scale ) != <NUM_LIT> ) return false ; ScaledConstant /= Scale


<s> assert ( Scale > <NUM_LIT> && <STR_LIT> ) ; const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Node ) ; if ( ! C ) return false ; ScaledConstant = ( int ) C -> getZExtValue ( ) ; if ( ( ScaledConstant % Scale ) != <NUM_LIT> ) return false ; ScaledConstant /= Scale ; return ScaledConstant >= RangeMin && ScaledConstant <


<s> return ShOpcVal == <STR_LIT> && ( ShAmt == <NUM_LIT> || ( Subtarget -> isSwift (


<s> inline bool is_so_imm_not ( unsigned Imm )


<s> inline bool is_so_imm_not ( unsigned Imm ) const { return <STR_LIT> ( ~ Imm


<s> inline bool is_t2_so_imm_not ( unsigned


<s> if ( ! isOpcWithIntImmediate ( Srl . getNode ( ) , <STR_LIT> , Srl_imm ) || ( Srl_imm <= <NUM_LIT> ) ) continue ; SDValue CPTmp0 ; SDValue CPTmp1 ; SDValue CPTmp2 ; if ( isThumb2 ) { if ( SelectT2ShifterOperandReg ( N0 , CPTmp0 , CPTmp1 ) ) continue ; } else { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) || SelectRegShifterOperand ( N0 , CPTmp0 , CPTmp1 , CPTmp2 ) ) continue ; } Srl = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Srl ) , <STR_LIT> , Srl . getOperand ( <NUM_LIT> ) , CurDAG -> getConstant ( Srl_imm + TZ , <STR_LIT> ) ) ; N1 = CurDAG -> getNode ( <STR_LIT> , SDLoc ( N1 ) , <STR_LIT> , Srl , CurDAG -> getConstant ( And_imm , <STR_LIT> ) ) ; N1 = CurDAG -> getNode ( <STR_LIT> , SDLoc ( N1 ) , <STR_LIT> , N1 , CurDAG -> getConstant


<s> SDValue ADDSrc1 = XORSrc0 . getOperand ( <NUM_LIT> ) ; SDValue SRASrc0 = XORSrc1 . getOperand ( <NUM_LIT> ) ; SDValue SRASrc1 = XORSrc1 . getOperand ( <NUM_LIT> ) ; ConstantSDNode * SRAConstant = dyn_cast < ConstantSDNode > ( SRASrc1 ) ; EVT XType = SRASrc0 . getValueType ( ) ; unsigned Size = XType . getSizeInBits ( ) - <NUM_LIT> ; if ( ADDSrc1 == XORSrc1 && ADDSrc0 == SRASrc0 && XType . isInteger ( ) && SRAConstant != NULL && Size == SRAConstant -> getZExtValue ( ) ) { unsigned Opcode = Subtarget -> isThumb2 ( ) ? <STR_LIT> :


<s> SDValue ADDSrc1 = XORSrc0 . getOperand ( <NUM_LIT> ) ; SDValue SRASrc0 = XORSrc1 . getOperand ( <NUM_LIT> ) ; SDValue SRASrc1 = XORSrc1 . getOperand ( <NUM_LIT> ) ; ConstantSDNode * SRAConstant = dyn_cast < ConstantSDNode > ( SRASrc1 ) ; EVT XType = SRASrc0 . getValueType ( ) ; unsigned Size = XType . getSizeInBits ( ) - <NUM_LIT> ; if ( ADDSrc1 == XORSrc1 && ADDSrc0 == SRASrc0 && XType . isInteger ( ) && SRAConstant != NULL && Size == SRAConstant -> getZExtValue ( ) ) { unsigned Opcode = Subtarget -> isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; return CurDAG -> SelectNodeTo ( N , Opcode


<s> SelectAddrMode2Worker ( N , Base , Offset , Opc ) ; return


<s> bool SelectAddrMode2Base ( SDValue N , SDValue & Base , SDValue & Offset , SDValue & Opc ) { return SelectAddrMode2Worker ( N , Base , Offset , Opc )


<s> bool SelectAddrMode2Base ( SDValue N , SDValue & Base , SDValue & Offset , SDValue


<s> unsigned Opcode = Op -> getOpcode ( ) ; <STR_LIT> AM = ( Opcode == <STR_LIT> ) ? cast < LoadSDNode > ( Op ) -> getAddressingMode ( ) : cast < StoreSDNode > ( Op ) -> getAddressingMode ( ) ; <STR_LIT> AddSub = ( AM == <STR_LIT> || AM == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; int Val


<s> <STR_LIT> AM = ( Opcode == <STR_LIT> ) ? cast < LoadSDNode > ( Op ) -> getAddressingMode ( ) : cast < StoreSDNode > ( Op ) -> getAddressingMode ( ) ; <STR_LIT> AddSub = ( AM == <STR_LIT> || AM == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; int Val ; if ( isScaledConstantInRange ( N , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Val ) ) { if ( AddSub == <STR_LIT> )


<s> unsigned ShAmt = <NUM_LIT> ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( N , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , ShAmt , ShOpcVal ) , <STR_LIT> ) ; return true


<s> bool SelectAddrMode2ShOp ( SDValue N , SDValue & Base ,


<s> if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } else if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ; return AM2_BASE ; } if ( N . getOpcode ( ) != <STR_LIT> ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC , <STR_LIT> ) , <STR_LIT> ) ; return AM2_BASE ; } } if ( ( Subtarget -> isLikeA9 ( ) || Subtarget -> isSwift ( ) ) && ! N .


<s> int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC ) , <STR_LIT> ) ; return true ; } Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true


<s> return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrMode5 ( SDValue N , SDValue & Base , SDValue & Offset ) { if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { Base = N ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } else if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex


<s> unsigned Alignment = <NUM_LIT> ; if ( LSBaseSDNode * LSN = dyn_cast < LSBaseSDNode > ( Parent ) ) { unsigned LSNAlign = LSN -> getAlignment ( ) ; unsigned MemSize = LSN -> getMemoryVT ( ) . getSizeInBits (


<s> <STR_LIT> AM = LdSt -> getAddressingMode ( ) ; if ( AM != <STR_LIT> ) return false ; Offset = N ; if ( ConstantSDNode * NC = dyn_cast < ConstantSDNode > ( N ) ) { if ( NC -> getZExtValue ( ) * <NUM_LIT> == LdSt -> getMemoryVT ( ) . getSizeInBits ( )

) Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ;


<s> <STR_LIT> AM = LdSt -> getAddressingMode ( ) ; if ( AM != <STR_LIT> ) return false ; Offset = N ; if ( ConstantSDNode * NC = dyn_cast


<s> Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode >


<s> if ( N . getOpcode ( ) == <STR_LIT> && N . hasOneUse ( ) ) { Offset = N . getOperand


<s> Offset = N . getOperand ( <NUM_LIT> ) ; SDValue N1 = N . getOperand ( <NUM_LIT> ) ; Label = CurDAG -> getTargetConstant ( cast < ConstantSDNode > ( N1 ) -> getZExtValue


<s> TrueImm = ~ TrueImm ; Opc = <STR_LIT> ; } else if ( TrueVal . getNode ( ) -> hasOneUse ( ) && ( Subtarget -> hasV6T2Ops ( ) || <STR_LIT> ( TrueImm ) ) ) { Opc = <STR_LIT> ; } if ( Opc ) { SDValue True = CurDAG -> getTargetConstant ( TrueImm , <STR_LIT> ) ; SDValue CC = CurDAG -> getTargetConstant ( CCVal , <STR_LIT> ) ; SDValue Ops [ ] = { FalseVal , True , CC , CCR , InFlag } ; return CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> ,


<s> if ( SelectRegShifterOperand ( TrueVal , CPTmp0 , CPTmp1 , CPTmp2 ) ) { SDValue CC = CurDAG -> getTargetConstant ( CCVal , <STR_LIT> ) ; SDValue Ops [ ] = { FalseVal , CPTmp0 , CPTmp1 , CPTmp2 , CC , CCR , InFlag } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT>


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; if ( Opc == <STR_LIT> ) { Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; } Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( Node ) -> getMemOperand ( ) ; SDNode * ResNode = CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , <STR_LIT> , <STR_LIT>


<s> MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( Node ) -> getMemOperand ( ) ; SDNode * ResNode = CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , <STR_LIT> , <STR_LIT> , <STR_LIT> , Ops ) ; cast < MachineSDNode > ( ResNode ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; return ResNode


<s> BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ; ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! RHS ) return false ; ShImmVal = RHS -> getZExtValue ( ) & <NUM_LIT> ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( ShOpcVal , ShImmVal ) , <STR_LIT> ) ; return true