<s> if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { O << <STR_LIT> ( Mode ) ; } else if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { <STR_LIT> Mode = <STR_LIT> ( MO2 . getImm ( ) ) ; if ( Mode == <STR_LIT> ) O << <STR_LIT> ; } else { printOperand ( MI , OpNum , O


<s> const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; <STR_LIT> Mode = <STR_LIT> ( MO2 . getImm ( ) ) ; if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { O << <STR_LIT>


<s> } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ) { O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) )


<s> printOperand ( MI , OpNum , O ) ; return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ) { O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << ImmOffs * <NUM_LIT> ; } O <<


<s> if ( MO . getReg ( ) == <NUM_LIT> ) O << <STR_LIT> ; else O << <STR_LIT> << getRegisterName (


<s> void <ISA_LIT>InstPrinter :: printAddrMode6Operand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 .


<s> O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( MO2 . getImm ( ) ) { O << <STR_LIT> << ( MO2 . getImm ( ) << <NUM_LIT> ) ; } O <<


<s> void <ISA_LIT>InstPrinter :: printAddrModePCOperand ( const MCInst * MI , unsigned OpNum ,

raw_ostream & O , const char * Modifier ) {


<s> void <ISA_LIT>InstPrinter :: printBitfieldInvMaskImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; uint32_t v = ~ MO . getImm ( ) ; int32_t lsb = CountTrailingZeros_32 ( v


<s> void <ISA_LIT>InstPrinter :: printCPInstOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O , const char * Modifier ) { abort (


<s> const MCOperand & Op = MI -> getOperand ( OpNum ) ; O << '#' ; if ( Op . getImm ( ) < <NUM_LIT> ) O << '-' << ( - Op . getImm


<s> assert ( <NUM_LIT> ) ; } else if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { assert ( <NUM_LIT> ) ; } else { O << getRegisterName ( Reg ) ; } } else if ( Op . isImm ( ) ) { assert ( ( Modifier && ! strcmp ( Modifier , <STR_LIT> ) ) || ( ( Modifier == <NUM_LIT> || Modifier [ <NUM_LIT> ] == <NUM_LIT> ) && <STR_LIT> ) ) ; O << '#' << Op . getImm ( ) ; } else { if ( Modifier && Modifier [ <NUM_LIT> ] != <NUM_LIT> && strcmp ( Modifier , <STR_LIT> ) != <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; assert ( Op . isExpr ( )


<s> void <ISA_LIT>InstPrinter :: printPCLabel ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { abort (


<s> void <ISA_LIT>InstPrinter :: printRegisterList ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> ; for ( unsigned i = OpNum , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i != OpNum ) O


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<s> void <ISA_LIT>InstPrinter :: printSOImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; printSOImm ( O , MO . getImm (


<s> void <ISA_LIT>InstPrinter :: printT2AddrModeImm12Operand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; unsigned OffImm = MO2 . getImm ( ) ; if ( OffImm ) O <<


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand


<s> void <ISA_LIT>InstPrinter :: printT2AddrModeImm8OffsetOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; int32_t OffImm = ( int32_t ) MO1 . getImm ( ) ; if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm ; else if ( OffImm > <NUM_LIT> ) O


<s> const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm ; else if ( OffImm > <NUM_LIT> ) O


<s> const MCOperand & MO3 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; assert ( MO2 . getReg ( ) && <STR_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO2 . getReg ( ) ) ; unsigned ShAmt = MO3 . getImm


<s> if ( MI -> getOpcode ( ) == <STR_LIT> ) O << <STR_LIT> ; O <<


<s> void <ISA_LIT>InstPrinter :: printThumbAddrModeRI5Operand ( const MCInst * MI , unsigned Op , raw_ostream & O , unsigned Scale ) { const MCOperand & MO1 = MI -> getOperand ( Op ) ; const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; const MCOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op , O ) ; return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( MO3 . getReg ( ) ) O << <STR_LIT> << getRegisterName ( MO3 . getReg ( ) ) ; else if ( unsigned ImmOffs = MO2 . getImm ( ) ) O << <STR_LIT> << ImmOffs * Scale ; O <<


<s> O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; O << <STR_LIT> << getRegisterName ( MO2 . getReg


<s> const MCOperand & MO1 = MI -> getOperand ( Op ) ; const MCOperand & MO2 = MI -> getOperand ( Op


<s> void <ISA_LIT>InstPrinter :: printThumbAddrModeS2Operand ( const MCInst * MI , unsigned Op , raw_ostream & O ) { printThumbAddrModeRI5Operand ( MI , Op , O ,


<s> printThumbAddrModeRI5Operand ( MI , Op ,


<s> void <ISA_LIT>InstPrinter :: printThumbAddrModeS4Operand ( const MCInst * MI , unsigned Op , raw_ostream &


<s> unsigned CondBit0 = Mask >> <NUM_LIT> & <NUM_LIT> ; unsigned NumTZ = CountTrailingZeros_32 ( Mask ) ; assert ( NumTZ <= <NUM_LIT> && <STR_LIT> ) ; for ( unsigned Pos = <NUM_LIT> , e = NumTZ ; Pos > e ; -- Pos ) { bool T = ( ( Mask >> Pos ) & <NUM_LIT> ) == CondBit0 ; if ( T ) O << 't' ; else O


<s> O << '#' << MI -> getOperand ( OpNum )


<s> void <ISA_LIT>InstPrinter :: printVFPf32ImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << '#' << MI -> getOperand (


<s> uint32_t Banked = MI -> getOperand ( OpNum ) . getImm ( ) ; uint32_t R = ( Banked & <NUM_LIT> ) >> <NUM_LIT> ; uint32_t SysM = Banked & <NUM_LIT> ; if ( R ) { O << <STR_LIT> ; switch ( SysM ) { case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT>


<s> void <ISA_LIT>InstPrinter :: printBankedRegOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { uint32_t Banked = MI -> getOperand ( OpNum ) . getImm ( ) ; uint32_t R = ( Banked & <NUM_LIT> ) >> <NUM_LIT> ; uint32_t SysM = Banked & <NUM_LIT> ; if ( R ) { O << <STR_LIT> ; switch ( SysM ) { case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; default : llvm_unreachable ( <STR_LIT> ) ; } } assert ( ! R && <STR_LIT> ) ; const char * RegNames [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const char * Name =


<s> StringRef <ISA_LIT>InstPrinter :: getOpcodeName ( unsigned Opcode ) const { return getInstructionName (


<s> O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ) { O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << ImmOffs * <NUM_LIT> ; } O <<


<s> void <ISA_LIT>InstPrinter :: printAddrMode7Operand ( const MCInst * MI , unsigned OpNum , raw_ostream &


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) )


<s> void <ISA_LIT>InstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg


<s> V = <STR_LIT> ( V ) ; assert ( V != - <NUM_LIT> && <STR_LIT> ) ; unsigned Imm = <STR_LIT> ( V ) ; unsigned Rot = <STR_LIT> ( V ) ; if ( Rot ) { O << <STR_LIT> << Imm << <STR_LIT> << Rot ; if ( CommentStream ) * CommentStream << ( int ) <STR_LIT> ( Imm , Rot ) << <STR_LIT> ; } else { O << <STR_LIT>


<s> if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op , O ) ; return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( unsigned ImmOffs = MO2 . getImm ( ) ) O << <STR_LIT> << ImmOffs * Scale ; O <<


<s> const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op ,


<s> const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op , O ) ; return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( unsigned RegNum = MO2 . getReg ( ) ) O << <STR_LIT> << getRegisterName ( RegNum ) ; O <<


<s> } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( unsigned RegNum = MO2 . getReg ( ) ) O << <STR_LIT> << getRegisterName ( RegNum ) ; O <<


<s> void <ISA_LIT>InstPrinter :: printAddrModeTBB ( const MCInst * MI , unsigned Op , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( Op ) ; const MCOperand & MO2 = MI -> getOperand (


<s> O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) << <STR_LIT>

<< getRegisterName ( MO2 . getReg ( ) ) << <STR_LIT> ;


<s> const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) << <STR_LIT> << getRegisterName ( MO2 . getReg (


<s> void <ISA_LIT>InstPrinter :: printAM2PreOrOffsetIndexOp ( const MCInst * MI , unsigned Op , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( Op ) ; const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; const MCOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << <STR_LIT> ( MO3 . getImm ( ) ) ; O <<


<s> void <ISA_LIT>InstPrinter :: printAM3PostIndexOp ( const MCInst * MI , unsigned Op , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( Op ) ; const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; const MCOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) << <STR_LIT> ; if ( MO2 . getReg ( ) ) { O << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << getRegisterName ( MO2 . getReg ( ) ) ; return ; } unsigned ImmOffs = <STR_LIT> ( MO3 . getImm ( ) ) ; O << '#' << <STR_LIT> ( <STR_LIT> ( MO3 . getImm


<s> O << <STR_LIT> << getAddrOpcStr ( <STR_LIT> ( MO3 . getImm ( ) ) ) << getRegisterName ( MO2 . getReg ( ) ) << ']' ; return ; } if ( unsigned ImmOffs = <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << ImmOffs ; O <<


<s> const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; const MCOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; O << '[' << getRegisterName ( MO1 . getReg ( ) ) ; if ( MO2 . getReg


<s> O << <STR_LIT> << <NUM_LIT> - MI -> getOperand ( OpNum ) .


<s> void <ISA_LIT>InstPrinter :: printFBits32 ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << <NUM_LIT> - MI -> getOperand ( OpNum ) . getImm


<s> void <ISA_LIT>InstPrinter :: printFPImmOperand ( const MCInst * MI


<s> return ; } O << <STR_LIT> << translateShiftImm ( <STR_LIT> ( MO2 . getImm ( ) ) ) ; printAnnotation ( O , Annot ) ; return ; } if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getNumOperands ( ) > <NUM_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; if ( Opcode == <STR_LIT> ) O << <STR_LIT> ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( Opcode == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == - <NUM_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) << <STR_LIT> ; printAnnotation ( O , Annot ) ; return ; } if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getNumOperands ( ) > <NUM_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; if ( Opcode == <STR_LIT> ) O << <STR_LIT> ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( Opcode == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) << <STR_LIT> ; printAnnotation ( O , Annot ) ; return ; } if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> )


<s> void <ISA_LIT>InstPrinter :: printNEONModImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { unsigned EncodedImm = MI -> getOperand ( OpNum ) . getImm ( ) ; unsigned


<s> void <ISA_LIT>InstPrinter :: printNEONModImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { unsigned EncodedImm = MI -> getOperand ( OpNum ) . getImm ( ) ; unsigned EltBits


<s> if ( Op . isReg ( ) ) { unsigned Reg = Op . getReg ( ) ; O << getRegisterName ( Reg ) ; } else if ( Op . isImm ( ) ) { O << '#' << Op . getImm ( ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( Op . getExpr ( ) ) ; int64_t Address ; if ( BranchTarget && BranchTarget -> EvaluateAsAbsolute ( Address )


<s> unsigned Imm = MI -> getOperand ( OpNum ) . getImm ( ) ; if ( Imm == <NUM_LIT> )


<s> const MCOperand & MO = MI -> getOperand ( OpNum ) ; unsigned Imm = MO . getImm ( ) ; O << '#' << ( ( Imm & <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) <<


<s> O << ( MO2 . getImm ( ) ? <STR_LIT> : <STR_LIT> ) << getRegisterName ( MO1


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS


<s> void <ISA_LIT>InstPrinter :: printSORegImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << getRegisterName ( MO1 . getReg ( ) ) ; <STR_LIT> ShOpc = <STR_LIT> ( MO2 . getImm ( )


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; const MCOperand & MO3 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << getRegisterName ( MO1 . getReg ( ) ) ; <STR_LIT> ShOpc = <STR_LIT> ( MO3 . getImm ( ) ) ; O << <STR_LIT> << <STR_LIT> ( ShOpc ) ; if ( ShOpc == <STR_LIT>


<s> O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( MO2 . getImm ( ) ) O << <STR_LIT> << MO2 . getImm


<s> if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm ; else O << <STR_LIT> <<


<s> void <ISA_LIT>InstPrinter :: printT2AddrModeImm8Operand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; if ( OffImm == INT32_MIN ) O << <STR_LIT> ; else if ( OffImm < <NUM_LIT> ) O << <STR_LIT> <<


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 .


<s> int32_t OffImm = ( int32_t ) MO1 . getImm ( ) / <NUM_LIT> ; if ( OffImm != <NUM_LIT> ) { O << <STR_LIT> ; if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm


<s> if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm * <NUM_LIT> ; else if ( OffImm > <NUM_LIT> ) O << <STR_LIT>


<s> return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) / <NUM_LIT> ; if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm


<s> assert ( MO2 . isImm ( ) && <STR_LIT> ) ; <STR_LIT> ShOpc = <STR_LIT> ( MO2 . getImm ( ) ) ; O << <STR_LIT> << <STR_LIT> ( ShOpc ) ; if ( ShOpc != <STR_LIT> ) O << <STR_LIT> << translateShiftImm ( <STR_LIT> (


<s> void <ISA_LIT>InstPrinter :: printThumbS4ImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << MI -> getOperand ( OpNum )


<s> void <ISA_LIT>InstPrinter :: printVectorListFour ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI ->

getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> ;


<s> O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> <<

getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printVectorListFourAllLanes ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI

-> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printVectorListFourSpaced ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI ->

getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printVectorListFourSpaced ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( )

+ <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printVectorListFourSpacedAllLanes ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT>

<< getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printVectorListOne ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg (


<s> void <ISA_LIT>InstPrinter :: printVectorListOne ( const MCInst * MI , unsigned OpNum , raw_ostream & O


<s> void <ISA_LIT>InstPrinter :: printVectorListOneAllLanes ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg (


<s> O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg (

) + <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printVectorListThreeSpaced ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( )


<s> unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; unsigned Reg0 = MRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> << getRegisterName ( Reg0 ) << <STR_LIT> <<


<s> void <ISA_LIT>InstPrinter :: printVectorListTwoAllLanes ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; unsigned Reg0 = MRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> << getRegisterName ( Reg0 ) <<

<STR_LIT> << getRegisterName ( Reg1 ) << <STR_LIT> ;


<s> unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> << getRegisterName ( Reg0 ) << <STR_LIT> << getRegisterName (


<s> if ( imm == <NUM_LIT> ) return <NUM_LIT> ; return imm


<s> static unsigned translateShiftImm ( unsigned imm ) { if ( imm == <NUM_LIT> ) return <NUM_LIT> ; return imm


<s> } O << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) ; printRegName ( O , MO1 . getReg ( ) ) ; printRegImmShift ( O , <STR_LIT> ( MO2 . getImm ( ) ) ,

<STR_LIT> ( MO2 . getImm ( ) ) , UseMarkup ) ;


<s> if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op , STI , O ) ; return ; } const MCOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; unsigned IdxMode = <STR_LIT> ( MO3 .


<s> O << getAddrOpcStr ( <STR_LIT> ( MO2 . getImm ( ) ) ) ; printRegName ( O , MO1 . getReg ( ) ) ; return ; } unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; O << markup ( <STR_LIT> ) << '#' << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << ImmOffs <<


<s> assert ( <STR_LIT> ( MI -> getOperand ( Op + <NUM_LIT> ) . getImm ( ) ) != <STR_LIT> && <STR_LIT> ) ; printAM3PreOrOffsetIndexOp ( MI , Op ,


<s> printOperand ( MI , OpNum , STI , O ) ; return ; } O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; unsigned Op = <STR_LIT> ( MO2 . getImm ( ) ) ; if ( AlwaysPrintImm0 || ImmOffs || Op == <STR_LIT>


<s> printRegName ( O , MO1 . getReg ( ) ) ; if ( MO2 . getImm ( ) ) { O << <STR_LIT> << ( MO2 . getImm ( ) << <NUM_LIT> ) ; } O << <STR_LIT> << markup


<s> void <ISA_LIT>InstPrinter :: printAddrMode7Operand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1


<s> void <ISA_LIT>InstPrinter :: printAddrModeTBB ( const MCInst * MI , unsigned Op , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( Op ) ; const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT>


<s> O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MO2 . getReg ( ) ) ; O << <STR_LIT> <<


<s> O << <STR_LIT> ; printRegName ( O , MO2 . getReg ( ) ) ; O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << markup ( <STR_LIT> ) <<


<s> const MCOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; O << markup ( <STR_LIT> ) << '[' ; printRegName ( O , MO1 . getReg ( ) ) ; if ( MO2 . getReg ( ) ) { O << <STR_LIT> << getAddrOpcStr ( <STR_LIT> ( MO3 . getImm ( ) ) ) ; printRegName ( O , MO2 . getReg ( ) ) ; O << ']' << markup ( <STR_LIT> ) ; return ; } unsigned ImmOffs = <STR_LIT> ( MO3 . getImm ( ) ) ; <STR_LIT> op = <STR_LIT> ( MO3 . getImm ( ) ) ; if ( AlwaysPrintImm0 || ImmOffs || ( op == <STR_LIT> ) ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> ( op ) << ImmOffs << markup ( <STR_LIT> ) ; } O << ']' << markup ( <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printBitfieldInvMaskImmOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; uint32_t v = ~ MO . getImm ( ) ; int32_t lsb = countTrailingZeros ( v ) ; int32_t width = ( <NUM_LIT> - countLeadingZeros


<s> void <ISA_LIT>InstPrinter :: printCImmediate ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << <STR_LIT> << MI -> getOperand ( OpNum ) . getImm


<s> unsigned Val = MI -> getOperand ( OpNo ) . getImm ( ) ; O << <STR_LIT> << ( Val * Angle )


<s> void <ISA_LIT>InstPrinter :: printCoprocOptionImm ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo &


<s> void <ISA_LIT>InstPrinter :: printCoprocOptionImm ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << <STR_LIT> << MI -> getOperand ( OpNum ) . getImm


<s> const MCOperand & Op = MI -> getOperand ( OpNum ) ; unsigned IFlags = Op . getImm ( ) ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( IFlags & ( <NUM_LIT> << i )


<s> void <ISA_LIT>InstPrinter :: printCPSIMod ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI


<s> void <ISA_LIT>InstPrinter :: printFBits16 ( const MCInst * MI , unsigned OpNum

, const MCSubtargetInfo & STI , raw_ostream & O ) {


<s> void <ISA_LIT>InstPrinter :: printFBits32 ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << markup ( <STR_LIT> ) << <STR_LIT> << <NUM_LIT> - MI -> getOperand ( OpNum ) . getImm ( ) << markup


<s> void <ISA_LIT>InstPrinter :: printFBits32 ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << markup ( <STR_LIT> ) << <STR_LIT> << <NUM_LIT> - MI -> getOperand ( OpNum ) . getImm (


<s> void <ISA_LIT>InstPrinter :: printFPImmOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI


<s> void <ISA_LIT>InstPrinter :: printInstSyncBOption ( const MCInst * MI , unsigned OpNum ,

const MCSubtargetInfo & STI , raw_ostream & O ) {


<s> unsigned val = MI -> getOperand ( OpNum ) . getImm ( ) ; O << <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printLdStmModeOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { <STR_LIT> Mode = <STR_LIT> ( MI -> getOperand ( OpNum ) . getImm ( ) ) ; O << <STR_LIT> (


<s> void <ISA_LIT>InstPrinter :: printLdStmModeOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { <STR_LIT> Mode = <STR_LIT> ( MI -> getOperand (


<s> <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum ) . getImm


<s> <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum ) . getImm ( ) ; O << <ISA_LIT>CondCodeToString ( CC


<s> void <ISA_LIT>InstPrinter :: printMemBOption ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned val = MI -> getOperand ( OpNum ) .


<s> void <ISA_LIT>InstPrinter :: printModImmOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { MCOperand Op = MI -> getOperand ( OpNum ) ; if ( Op . isExpr ( ) ) return printOperand ( MI , OpNum , STI , O ) ; unsigned Bits = Op . getImm ( ) & <NUM_LIT> ; unsigned Rot = ( Op . getImm ( ) & <NUM_LIT> ) >> <NUM_LIT> ; bool PrintUnsigned =


<s> auto TheReg = <STR_LIT> ( SYSm ) ; if ( TheReg && TheReg -> isInRequiredFeatures ( { <STR_LIT> } ) ) { O << TheReg -> Name ; return ; } } SYSm &= <NUM_LIT> ; if ( Opcode == <STR_LIT> && FeatureBits [ <STR_LIT> ] ) { auto TheReg = <STR_LIT> ( SYSm ) ; if ( TheReg ) { O << TheReg -> Name ; return ; } } auto TheReg = <STR_LIT> ( SYSm ) ; if ( TheReg ) { O << TheReg -> Name ; return ; } O << SYSm ; return ; } unsigned SpecRegRBit = Op . getImm ( ) >> <NUM_LIT> ; unsigned Mask = Op . getImm ( ) & <NUM_LIT> ; if ( ! SpecRegRBit && ( Mask == <NUM_LIT> || Mask == <NUM_LIT> || Mask == <NUM_LIT> ) ) { O << <STR_LIT> ; switch ( Mask ) { default : llvm_unreachable (


<s> void <ISA_LIT>InstPrinter :: printNEONModImmOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned EncodedImm = MI -> getOperand ( OpNum ) . getImm ( ) ; unsigned EltBits ; uint64_t Val = <STR_LIT> (


<s> void <ISA_LIT>InstPrinter :: printNoHashImmediate ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << MI -> getOperand ( OpNum ) .


<s> void <ISA_LIT>InstPrinter :: printPCLabel ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { llvm_unreachable ( <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printPImmediate ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI ,


<s> void <ISA_LIT>InstPrinter :: printPImmediate ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << <STR_LIT> << MI -> getOperand (


<s> assert ( Imm > <NUM_LIT> && Imm <= <NUM_LIT> && <STR_LIT> ) ; O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT>


<s> assert ( Imm > <NUM_LIT> && Imm <= <NUM_LIT> && <STR_LIT> ) ; O << <STR_LIT> << markup ( <STR_LIT> ) <<

<STR_LIT> << Imm << markup ( <STR_LIT> ) ;


<s> void <ISA_LIT>InstPrinter :: printPostIdxImm8Operand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; unsigned Imm = MO . getImm (


<s> void <ISA_LIT>InstPrinter :: printPostIdxRegOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << ( MO2 . getImm ( ) ?


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand (


<s> O << getShiftOpcStr ( ShOpc ) ; if ( ShOpc != <STR_LIT> ) { O << <STR_LIT> ; if ( UseMarkup ) O << <STR_LIT> ; O << <STR_LIT> << translateShiftImm ( ShImm ) ; if ( UseMarkup )


<s> void <ISA_LIT>InstPrinter :: printRegisterList ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { assert ( std :: is_sorted ( MI -> begin ( ) + OpNum , MI -> end ( ) , [ & ] ( const MCOperand & LHS , const MCOperand & RHS ) { return MRI . getEncodingValue ( LHS . getReg ( ) ) < MRI . getEncodingValue ( RHS . getReg ( ) ) ; } ) ) ; O << <STR_LIT> ; for ( unsigned i = OpNum , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i != OpNum ) O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( i ) . getReg ( ) ) ; } O << <STR_LIT>


<s> if ( MI -> getOperand ( OpNum ) . getReg ( ) ) { assert ( MI -> getOperand ( OpNum ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; O << 's'


<s> unsigned ShiftOp = MI -> getOperand ( OpNum ) . getImm ( ) ; bool isASR = ( ShiftOp & ( <NUM_LIT> << <NUM_LIT> ) ) != <NUM_LIT> ; unsigned Amt = ShiftOp & <NUM_LIT> ; if ( isASR ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << ( Amt == <NUM_LIT> ? <NUM_LIT> : Amt ) << markup ( <STR_LIT> ) ; } else if


<s> void <ISA_LIT>InstPrinter :: printSORegRegOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; const MCOperand & MO3 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; printRegName ( O , MO1 . getReg ( ) ) ; <STR_LIT> ShOpc = <STR_LIT> ( MO3 . getImm ( ) ) ; O << <STR_LIT> << <STR_LIT>


<s> O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( MO2 . getImm ( ) * <NUM_LIT> ) << markup ( <STR_LIT> ) ; } O << <STR_LIT> <<


<s> void <ISA_LIT>InstPrinter :: printT2AddrModeImm8OffsetOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; int32_t OffImm = ( int32_t )


<s> void <ISA_LIT>InstPrinter :: printT2AddrModeImm8OffsetOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; int32_t OffImm = ( int32_t ) MO1


<s> int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; bool isSub = OffImm < <NUM_LIT> ; if ( OffImm == INT32_MIN ) OffImm = <NUM_LIT> ; if ( isSub ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << - OffImm << markup ( <STR_LIT> ) ; } else if ( AlwaysPrintImm0 || OffImm


<s> O << <STR_LIT> << markup ( <STR_LIT> ) ; if ( OffImm == INT32_MIN ) O << <STR_LIT> ; else if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm ; else O << <STR_LIT> << OffImm ; O << markup (


<s> const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , OpNum , STI , O ) ; return ; } O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; bool isSub = OffImm < <NUM_LIT> ; assert ( ( ( OffImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( OffImm == INT32_MIN ) OffImm


<s> assert ( MO2 . getReg ( ) && <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MO2 . getReg ( ) ) ; unsigned ShAmt = MO3 . getImm ( ) ; if ( ShAmt ) { assert ( ShAmt <= <NUM_LIT> && <STR_LIT> ) ; O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << ShAmt << markup ( <STR_LIT> ) ; } O << <STR_LIT> << markup


<s> const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; unsigned Reg = MO1 . getReg ( ) ; printRegName ( O , Reg ) ; assert ( MO2 . isImm ( ) && <STR_LIT> ) ; printRegImmShift ( O , <STR_LIT> ( MO2 . getImm ( ) ) , <STR_LIT> ( MO2 . getImm


<s> void <ISA_LIT>InstPrinter :: printThumbAddrModeImm5S2Operand ( const MCInst * MI , unsigned Op , const MCSubtargetInfo & STI ,


<s> printThumbAddrModeImm5SOperand ( MI , Op , STI


<s> void <ISA_LIT>InstPrinter :: printThumbAddrModeRROperand ( const MCInst * MI , unsigned Op , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( Op ) ; const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op , STI , O ) ; return ; } O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; if ( unsigned RegNum = MO2 . getReg ( ) ) { O << <STR_LIT> ; printRegName ( O , RegNum


<s> printThumbAddrModeImm5SOperand ( MI , Op , STI , O


<s> unsigned Mask = MI -> getOperand ( OpNum ) . getImm ( ) ; unsigned Firstcond = MI -> getOperand ( OpNum - <NUM_LIT> ) . getImm ( ) ; unsigned CondBit0 = Firstcond & <NUM_LIT> ; unsigned NumTZ = countTrailingZeros ( Mask ) ; assert ( NumTZ <= <NUM_LIT> && <STR_LIT> ) ; for ( unsigned Pos = <NUM_LIT> , e = NumTZ ; Pos > e ; -- Pos ) { bool T = ( ( Mask >> Pos ) & <NUM_LIT>


<s> unsigned Mask = MI -> getOperand ( OpNum ) . getImm ( ) ; unsigned Firstcond = MI -> getOperand ( OpNum - <NUM_LIT> ) . getImm ( ) ; unsigned CondBit0 = Firstcond & <NUM_LIT> ; unsigned NumTZ = countTrailingZeros ( Mask ) ; assert ( NumTZ <= <NUM_LIT> && <STR_LIT> ) ; for ( unsigned Pos = <NUM_LIT> , e = NumTZ ; Pos > e


<s> return ; } O << markup ( <STR_LIT> ) << <STR_LIT> ; int32_t OffImm = ( int32_t ) MO1 . getImm ( ) ; bool isSub = OffImm < <NUM_LIT> ; if ( OffImm == INT32_MIN ) OffImm = <NUM_LIT> ; if ( isSub ) { O << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( - OffImm ) << markup ( <STR_LIT> ) ; } else { O << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( OffImm ) << markup ( <STR_LIT> ) ; } O << <STR_LIT> << markup ( <STR_LIT>


<s> O << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( MI -> getOperand ( OpNum ) . getImm ( ) *


<s> unsigned Imm = MI -> getOperand ( OpNum ) . getImm ( ) ; O << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( ( Imm == <NUM_LIT> ? <NUM_LIT> : Imm ) ) <<


<s> O << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( ( Imm == <NUM_LIT> ? <NUM_LIT> : Imm ) )


<s> void <ISA_LIT>InstPrinter :: printTraceSyncBOption ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned val = MI -> getOperand ( OpNum ) . getImm ( ) ; O << <STR_LIT> (


<s> void <ISA_LIT>InstPrinter :: printVectorIndex ( const MCInst * MI , unsigned OpNum


<s> printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT>


<s> O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( )


<s> void <ISA_LIT>InstPrinter :: printVectorListFourAllLanes ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) +


<s> printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O <<


<s> void <ISA_LIT>InstPrinter :: printVectorListFourSpaced ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT>


<s> printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg (


<s> printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum


<s> void <ISA_LIT>InstPrinter :: printVectorListOne ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum


<s> printRegName ( O , MI -> getOperand ( OpNum ) .


<s> printRegName ( O , MI -> getOperand ( OpNum ) . getReg


<s> O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT>


<s> printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg (


<s> printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( )


<s> O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( )


<s> O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum )


<s> unsigned Reg0 = MRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , Reg0 ) ; O <<


<s> unsigned Reg0 = MRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , Reg0 ) ; O << <STR_LIT> ; printRegName ( O , Reg1 ) ; O <<


<s> void <ISA_LIT>InstPrinter :: printVectorListTwoAllLanes ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; unsigned Reg0 = MRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , Reg0 ) ; O << <STR_LIT> ; printRegName ( O , Reg1 ) ; O <<


<s> unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; unsigned Reg0 = MRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , Reg0 ) ; O << <STR_LIT> ; printRegName ( O ,


<s> unsigned Reg0 = MRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , Reg0 ) ; O << <STR_LIT> ; printRegName ( O , Reg1 ) ; O << <STR_LIT>


<s> unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; unsigned Reg0 = MRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O <<


<s> if ( MO2 . getReg ( ) ) { O << <STR_LIT> << getAddrOpcStr ( <STR_LIT> ( MO3 . getImm ( ) ) ) << getRegisterName ( MO2 . getReg ( ) ) << ']' ; return ; } unsigned ImmOffs = <STR_LIT> ( MO3 . getImm ( ) ) ; <STR_LIT> op = <STR_LIT> ( MO3 . getImm ( ) ) ; if ( ImmOffs || ( op == <STR_LIT> ) ) O << <STR_LIT> << <STR_LIT> ( op ) << ImmOffs ; O <<


<s> void <ISA_LIT>InstPrinter :: printAM3PreOrOffsetIndexOp ( const MCInst * MI , unsigned Op , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( Op ) ; const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; const MCOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; O << '[' << getRegisterName ( MO1 . getReg ( ) ) ; if ( MO2 . getReg ( ) ) { O << <STR_LIT> << getAddrOpcStr ( <STR_LIT> ( MO3 . getImm ( ) ) ) << getRegisterName ( MO2 . getReg ( ) ) << ']' ; return ; } unsigned ImmOffs = <STR_LIT> ( MO3 . getImm ( ) ) ; <STR_LIT> op = <STR_LIT> ( MO3 . getImm ( ) ) ; if ( ImmOffs || ( op == <STR_LIT> ) ) O << <STR_LIT> << <STR_LIT> ( op ) << ImmOffs ; O <<


<s> } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; bool isSub = OffImm < <NUM_LIT> ; if ( OffImm == INT32_MIN ) OffImm = <NUM_LIT> ; if ( isSub ) O << <STR_LIT> << - OffImm ; else if ( OffImm > <NUM_LIT> ) O << <STR_LIT> << OffImm ; O <<


<s> O << '#' << MI -> getOperand ( OpNum )


<s> O << '#' << MI -> getOperand ( OpNum ) .


<s> <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum ) . getImm ( ) ; if ( CC != <STR_LIT> ) O << <ISA_LIT>CondCodeToString (


<s> return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } } switch ( SYSm ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O <<


<s> void <ISA_LIT>InstPrinter :: printRegisterList ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << <STR_LIT> ; for ( unsigned i = OpNum , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i != OpNum ) O <<


<s> DefaultAltIdx = <STR_LIT> ; return true ; } if ( Opt == <STR_LIT> ) { DefaultAltIdx = <STR_LIT> ; return true ; } return false


<s> if ( ( <STR_LIT> ) MI -> getOperand ( OpNum ) . getImm ( ) == <STR_LIT> )


<s> O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MO2 . getReg (


<s> uint32_t Val = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( Val <= <NUM_LIT> && <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printMveSaturateOp ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo


<s> unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; const char * Prefix = <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumRegs ; i ++ ) { O <<


<s> assert ( std :: is_sorted ( MI -> begin ( ) + OpNum , MI -> end ( ) , [ & ] ( const MCOperand & LHS , const MCOperand & RHS ) { return MRI . getEncodingValue ( LHS . getReg ( ) ) < MRI . getEncodingValue ( RHS . getReg ( ) ) ; } ) ) ; } O << <STR_LIT> ; for ( unsigned i = OpNum , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i != OpNum ) O <<


<s> unsigned Mask = MI -> getOperand ( OpNum ) . getImm ( ) ; unsigned NumTZ = countTrailingZeros ( Mask ) ; assert ( NumTZ <= <NUM_LIT> &&


<s> unsigned EncodedImm = MI -> getOperand ( OpNum ) . getImm ( ) ; unsigned EltBits ; uint64_t Val = <STR_LIT> ( EncodedImm , EltBits ) ; O << markup (


<s> assert ( NumTZ <= <NUM_LIT> && <STR_LIT> ) ; for ( unsigned Pos = <NUM_LIT> , e = NumTZ ; Pos > e ; -- Pos ) { bool T = ( ( Mask >> Pos


<s> void <ISA_LIT>InstPrinter :: printVPTPredicateOperand ( const MCInst * MI , unsigned OpNum


<s> void <ISA_LIT>InstPrinter :: printAddrMode2OffsetOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; if ( ! MO1 .


<s> if ( MO . isExpr ( ) ) { O << * MO . getExpr ( ) ; return ; } int32_t OffImm = ( int32_t ) MO . getImm ( ) ; if ( OffImm == INT32_MIN ) O <<


<s> if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << <STR_LIT> ( MO3 . getImm ( ) ) ; O << <STR_LIT> ; return ; } O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << getRegisterName ( MO2 . getReg ( ) ) ; printRegImmShift ( O , <STR_LIT> ( MO3 . getImm ( ) )


<s> if ( ShOpc == <STR_LIT> || ( ShOpc == <STR_LIT> && ! ShImm ) ) return ; O << <STR_LIT> ; assert ( ! ( ShOpc == <STR_LIT> &&


<s> const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << getRegisterName ( MO1 . getReg ( )


<s> void <ISA_LIT>InstPrinter :: printT2AddrModeImm8s4OffsetOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand


<s> return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; assert ( ( ( OffImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( OffImm == INT32_MIN ) O << <STR_LIT> ; else if ( OffImm < <NUM_LIT> ) O


<s> void <ISA_LIT>InstPrinter :: printT2SOOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum +


<s> void <ISA_LIT>InstPrinter :: printT2SOOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; unsigned Reg = MO1 . getReg ( ) ; O << getRegisterName ( Reg ) ; assert ( MO2 . isImm ( ) && <STR_LIT>


<s> unsigned val = MI -> getOperand ( OpNum ) . getImm ( ) ; O << <STR_LIT> ( val , ( STI . getFeatureBits ( ) & <STR_LIT> )


<s> switch ( Expr -> getKind ( ) ) { case MCExpr :: Binary : O << '#' << * Expr ; break ; case MCExpr :: Constant : { const MCConstantExpr * Constant = cast < MCConstantExpr > ( Expr ) ; int64_t TargetAddress ; if ( ! Constant -> EvaluateAsAbsolute ( TargetAddress ) ) { O << '#' << * Expr ; } else { O << <STR_LIT> ; O . write_hex ( static_cast < uint32_t > ( TargetAddress


<s> if ( Imm == <NUM_LIT> ) return ; O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> ; switch ( Imm ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; } O << markup (


<s> O << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( - OffImm ) << markup ( <STR_LIT> ) ; } else { O << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( OffImm ) << markup ( <STR_LIT> ) ; } O << <STR_LIT> << markup (


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; if ( ! MO1 . getReg ( ) ) { unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; assert ( ImmOffs && <STR_LIT>


<s> return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << <STR_LIT> ( MO3 . getImm ( ) ) ; O << <STR_LIT> ; return ; } O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << getRegisterName ( MO2 . getReg ( ) ) ; if ( unsigned ShImm = <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << <STR_LIT> << ShImm ; O << <STR_LIT>


<s> return ; } unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; assert ( ImmOffs && <STR_LIT> ) ; O << <STR_LIT> << ( char ) <STR_LIT> ( MO2 . getImm (


<s> O << ( char ) <STR_LIT> ( MO2 . getImm ( ) ) << getRegisterName ( MO1 . getReg ( ) ) ; return ; } unsigned ImmOffs = <STR_LIT> ( MO2 . getImm (


<s> O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << getRegisterName ( MO2 . getReg ( ) ) << ']' ; return ; } if ( unsigned ImmOffs = <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm (


<s> void <ISA_LIT>InstPrinter :: printAddrMode4Operand ( const MCInst * MI , unsigned OpNum , const char * Modifier ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; <STR_LIT> Mode = <STR_LIT> ( MO2 . getImm ( ) ) ; if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { if ( MO1 . getReg ( ) == <STR_LIT> ) { bool isLDM = ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ; O << <STR_LIT> ( Mode , isLDM ) ; } else O << <STR_LIT> (


<s> return ; } if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { <STR_LIT> Mode = <STR_LIT> ( MO2 . getImm ( ) ) ; O << <STR_LIT> ( Mode ) ; return ; } else if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { O << getRegisterName ( MO1 . getReg ( ) ) ; if ( <STR_LIT> ( MO2 . getImm ( ) ) ) O << <STR_LIT> ; return ; } O << <STR_LIT> << getRegisterName (


<s> const MCOperand & MO3 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << '[' << getRegisterName ( MO1 . getReg ( ) ) << ']' ; if ( <STR_LIT> ( MO3 . getImm ( ) ) ) { if ( MO2 . getReg ( ) == <NUM_LIT> ) O << '!' ; else O << <STR_LIT> << getRegisterName (


<s> void <ISA_LIT>InstPrinter :: printAddrModePCOperand ( const MCInst * MI , unsigned OpNum , const char * Modifier ) { assert ( <NUM_LIT> &&


<s> void <ISA_LIT>InstPrinter :: printAddrModePCOperand ( const MCInst * MI , unsigned


<s> uint32_t v = ~ MO . getImm ( ) ; int32_t lsb = CountTrailingZeros_32 ( v ) ; int32_t width = ( <NUM_LIT> - CountLeadingZeros_32 ( v )


<s> const MCOperand & MO = MI -> getOperand ( OpNum ) ; uint32_t v = ~ MO . getImm ( ) ; int32_t lsb = CountTrailingZeros_32 (


<s> void <ISA_LIT>InstPrinter :: printCPInstOperand ( const MCInst * MI , unsigned OpNum , const


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst


<s> <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum ) . getImm ( ) ; O << <ISA_LIT>CondCodeToString (


<s> <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand (


<s> assert ( <NUM_LIT> ) ; } else if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { assert ( <NUM_LIT> ) ; } else { O << getRegisterName ( Reg ) ; } } else if ( Op . isImm ( ) ) { assert ( ( Modifier == <NUM_LIT> || Modifier [ <NUM_LIT> ] == <NUM_LIT> ) && <STR_LIT> ) ; O << '#' << Op . getImm ( ) ; } else


<s> void <ISA_LIT>InstPrinter :: printPCLabel ( const MCInst * MI , unsigned


<s> void <ISA_LIT>InstPrinter :: printPredicateOperand ( const MCInst * MI , unsigned OpNum ) { <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum ) . getImm ( ) ; if ( CC != <STR_LIT> ) O <<


<s> for ( unsigned i = OpNum + <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i != OpNum + <NUM_LIT> ) O << <STR_LIT> ; O << getRegisterName ( MI -> getOperand ( i ) . getReg ( ) ) ; } O <<


<s> <ISA_LIT>InstPrinter :: <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCSubtargetInfo &


<s> <ISA_LIT>InstPrinter :: <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCSubtargetInfo


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } } if ( ! SpecRegRBit && ( Mask == <NUM_LIT> || Mask == <NUM_LIT> || Mask == <NUM_LIT> ) ) { O << <STR_LIT> ; switch ( Mask ) { default : assert ( <NUM_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } llvm_unreachable ( <STR_LIT> ) ; } if ( SpecRegRBit ) O << <STR_LIT> ; else O << <STR_LIT> ; if ( Mask ) { O << '_' ; if ( Mask & <NUM_LIT> ) O << 'f' ; if ( Mask & <NUM_LIT>


<s> O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( )


<s> O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName

( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> ;


<s> O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand (

OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printVectorListTwoSpacedAllLanes ( const MCInst * MI , unsigned OpNum , raw_ostream &


<s> O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum

) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> ;


<s> case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } } SYSm &= <NUM_LIT> ; if ( Opcode == <STR_LIT> && FeatureBits [ <STR_LIT> ] ) { switch ( SYSm ) { case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } } switch ( SYSm ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O <<


<s> O << <STR_LIT> ; for ( unsigned i = OpNum , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i != OpNum ) O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( i ) . getReg ( ) ) ; } O <<


<s> O << markup ( <STR_LIT> ) << '#' << formatImm ( Op . getImm ( ) ) << markup ( <STR_LIT> ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = Op . getExpr ( ) ; switch ( Expr -> getKind ( ) ) { case MCExpr :: Binary : O << '#' << * Expr ; break ; case MCExpr :: Constant : { const MCConstantExpr * Constant = cast < MCConstantExpr > ( Expr ) ; int64_t TargetAddress ; if ( ! Constant -> evaluateAsAbsolute


<s> void <ISA_LIT>InstPrinter :: printOperand ( const MCInst * MI , uint64_t Address , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNum ) ; if ( ! Op . isImm ( ) || ! PrintBranchImmAsAddress || getUseMarkup ( ) ) return printOperand ( MI , OpNum , STI , O ) ; uint64_t Target = <ISA_LIT>_MC :: evaluateBranchTarget ( MII . get ( MI -> getOpcode ( ) ) , Address , Op . getImm ( ) ) ; Target &= <NUM_LIT> ; O << formatHex ( Target


<s> void <ISA_LIT>InstPrinter :: printThumbLdrLabelOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; if ( MO1 . isExpr ( ) ) O << * MO1 . getExpr ( ) ; else if ( MO1 . isImm ( ) ) O << <STR_LIT> << MO1 . getImm ( ) << <STR_LIT> ; else llvm_unreachable ( <STR_LIT>


<s> else if ( MO1 . isImm ( ) ) O << <STR_LIT> << MO1 . getImm ( ) << <STR_LIT> ; else llvm_unreachable (


<s> return ; } if ( Opcode == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == - <NUM_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) << <STR_LIT> ; printAnnotation ( O , Annot ) ; return ; } if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; if ( Opcode == <STR_LIT> ) O << <STR_LIT> ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( Opcode == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) << <STR_LIT> ; printAnnotation ( O , Annot ) ; return ; } if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( Opcode == <STR_LIT> ) { bool Writeback = true ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( unsigned i = <NUM_LIT> ; i < MI -> getNumOperands ( ) ; ++ i ) { if ( MI -> getOperand ( i ) . getReg ( ) == BaseReg ) Writeback = false ; } O << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT>


<s> uint32_t Val = MI -> getOperand ( OpNum ) . getImm ( ) ; O << markup ( <STR_LIT>


<s> const MCOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; const MCOperand & MO1 = MI -> getOperand ( <NUM_LIT> ) ; const MCOperand & MO2 = MI -> getOperand ( <NUM_LIT> ) ; const MCOperand & MO3 = MI -> getOperand ( <NUM_LIT> ) ; O << '\t' << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) ; printSBitModifierOperand ( MI , <NUM_LIT> , O ) ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegName ( O , Dst . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MO2 . getReg ( ) ) ; assert ( <STR_LIT> ( MO3 . getImm ( ) ) == <NUM_LIT> ) ; printAnnotation ( O , Annot ) ; return ; } case <STR_LIT> : { const MCOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; const MCOperand & MO1 = MI -> getOperand ( <NUM_LIT> ) ; const MCOperand & MO2 = MI -> getOperand ( <NUM_LIT> ) ; O << '\t' << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) ; printSBitModifierOperand ( MI , <NUM_LIT> , O ) ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegName ( O , Dst . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; if ( <STR_LIT> ( MO2 . getImm ( ) ) == <STR_LIT> ) { printAnnotation ( O , Annot ) ; return ; } O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << translateShiftImm ( <STR_LIT> ( MO2 . getImm ( ) ) ) << markup ( <STR_LIT> ) ; printAnnotation ( O , Annot ) ; return ; } case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getNumOperands ( ) > <NUM_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; if ( Opcode == <STR_LIT> ) O << <STR_LIT> ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } else break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == - <NUM_LIT> ) { O << '\t' <<


<s> return ; } O << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << getRegisterName ( MO1 . getReg ( ) ) ; if ( unsigned ShImm = <STR_LIT> ( MO2 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT>

( <STR_LIT> ( MO2 . getImm ( ) ) ) << <STR_LIT> << ShImm ;


<s> if ( ! MO1 . isReg ( ) ) { printOperand ( MI , OpNum , O ) ; return ; } if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { <STR_LIT> Mode = <STR_LIT> ( MO2 . getImm ( ) ) ; O << <STR_LIT> ( Mode ) ; return ; } else if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { O << getRegisterName ( MO1 . getReg ( ) ) ; return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ) { O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) )


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( MO2 . getImm ( ) ) { O << <STR_LIT> << MO2 . getImm ( ) ; } O <<


<s> const MCOperand & MO = MI -> getOperand ( OpNum ) ; uint32_t v = ~ MO . getImm ( ) ; int32_t lsb = CountTrailingZeros_32 ( v ) ; int32_t width = ( <NUM_LIT> - CountLeadingZeros_32 ( v


<s> void <ISA_LIT>InstPrinter :: printBitfieldInvMaskImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; uint32_t v = ~ MO . getImm ( ) ; int32_t lsb = CountTrailingZeros_32 ( v ) ; int32_t width = ( <NUM_LIT> - CountLeadingZeros_32 ( v ) ) - lsb ; assert ( MO . isImm ( )


<s> printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' << getRegisterName ( Dst . getReg ( ) ) << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( <STR_LIT> ( MO3 . getImm ( ) ) == <STR_LIT> ) return ; O << <STR_LIT> ; if ( MO2 . getReg ( ) ) { O << getRegisterName ( MO2 . getReg ( ) ) ; assert ( <STR_LIT> ( MO3 . getImm ( ) ) == <NUM_LIT> ) ; } else { O << <STR_LIT> << <STR_LIT> ( MO3 . getImm ( ) ) ; } return ; } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { const MCOperand & MO1 = MI -> getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( MO1 . getImm ( ) ) == <STR_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; return ; } } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { const MCOperand & MO1 = MI -> getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( MO1 . getImm ( ) ) == <STR_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; return ; } } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { const MCOperand & MO1 = MI -> getOperand


<s> <ISA_LIT>InstPrinter :: <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCRegisterInfo &


<s> if ( isSub ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( - OffImm ) << markup ( <STR_LIT> ) ; } else if ( AlwaysPrintImm0 || OffImm > <NUM_LIT> ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << formatImm (


<s> if ( ! Subtarget . isGVIndirectSymbol ( GV ) ) { expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; Register Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( * MBB . getParent ( ) ) , Flags , <NUM_LIT> , <NUM_LIT> ) ; MIB . addMemOperand ( MMO ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT>

) . cloneMemRefs ( * MI ) . add ( predOps ( <STR_LIT> ) ) ;


<s> NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } else { NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createReg (


<s> if ( hasNOP ( ) ) { NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } else { NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand ::


<s> FunctionPass * llvm :: create<ISA_LIT>GlobalBaseRegPass ( ) { return new <ISA_LIT>CGBR ( )


<s> NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand ::


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> getGlobalBaseReg ( ) == <NUM_LIT> ) return false ; const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF . getTarget ( ) ) ; if ( TM -> getRelocationModel ( ) != Reloc :: PIC_ ) return false ; LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; GlobalValue * GV = new GlobalVariable ( Type :: getInt32Ty ( * Context ) , false , GlobalValue :: ExternalLinkage , <NUM_LIT> , <STR_LIT> ) ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV ,


<s> case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case


<s> void <ISA_LIT>InstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr * Orig , const TargetRegisterInfo & TRI ) const { DebugLoc dl = Orig -> getDebugLoc ( ) ; unsigned Opcode = Orig -> getOpcode ( ) ; switch ( Opcode ) { default : break ; case <STR_LIT> : { RI . emitLoadConstPool ( MBB , I , dl , DestReg , SubIdx , Orig -> getOperand ( <NUM_LIT> ) . getImm ( ) , ( <STR_LIT> ) Orig -> getOperand ( <NUM_LIT> ) . getImm ( ) , Orig -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineInstr * NewMI = prior ( I ) ; NewMI -> getOperand ( <NUM_LIT> ) . setSubReg


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; unsigned Flag = MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( ) , Flag , <NUM_LIT> , <NUM_LIT> ) ; MIB . addMemOperand ( MMO ) ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; MIB . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; AddDefaultPred (


<s> LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = STI . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * Context , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; unsigned Align = TM . getDataLayout ( ) -> getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned TempReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; unsigned Opc = STI . isThumb2 ( ) ?


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( OpNum == <NUM_LIT> ) { unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RI . isPhysicalRegister ( SrcReg ) && ! RI . isLowRegister ( SrcReg ) ) return false ; } else { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RI . isPhysicalRegister ( DstReg ) && ! RI . isLowRegister ( DstReg ) ) return false ; } return true ; } case <STR_LIT> : case <STR_LIT>


<s> AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ) ; return true ; } } else { if ( DestRC == <STR_LIT> ) { if ( SrcRC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return true ; } else if ( SrcRC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return true ; } } else if ( DestRC == <STR_LIT> ) { if ( SrcRC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg )


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> ) { Pred . push_back ( MO ) ; Found =


<s> if ( ! TID . getImplicitDefs ( ) && ! TID . hasOptionalDef ( ) ) return false ; bool Found = false ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> ) { Pred . push_back (


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int BOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; int BccOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) BuildMI ( & MBB , dl , get ( BOpc ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , dl , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; return <NUM_LIT> ; } BuildMI ( & MBB , dl , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; BuildMI ( & MBB , dl , get ( BOpc ) ) . addMBB (


<s> switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT>


<s> bool <ISA_LIT>InstrInfo :: isMoveInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SrcSubIdx , unsigned & DstSubIdx ) const { SrcSubIdx = DstSubIdx = <NUM_LIT> ; unsigned oc = MI . getOpcode ( ) ; switch ( oc ) { default : return false ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return true ; case <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : assert ( MI . getDesc ( ) . getNumOperands ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; SrcReg = MI . getOperand ( <NUM_LIT> )


<s> } Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else { assert ( RC == <STR_LIT> && <STR_LIT> ) ; Opc = <STR_LIT> ; } MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) , DestReg ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; AddDefaultPred ( MIB ) ; NewMIs . push_back ( MIB


<s> loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == <STR_LIT> ) { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( ! AFI -> isThumbFunction ( ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; } else if ( RC == <STR_LIT> ) { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( AFI -> isThumbFunction ( ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; } else if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ) ; }


<s> unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { MI -> setDesc ( get ( Opc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; MI -> addOperand ( MachineOperand :: CreateImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) ) ; MI -> addOperand ( MachineOperand :: CreateReg ( Pred [ <NUM_LIT> ] . getReg ( ) , false ) ) ; return true ; } int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT>


<s> void <ISA_LIT>InstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , const MachineInstr * Orig ) const { DebugLoc dl = Orig -> getDebugLoc ( ) ; if ( Orig -> getOpcode ( ) == <STR_LIT> ) { RI . emitLoadConstPool ( MBB , I , DestReg , Orig -> getOperand ( <NUM_LIT> ) . getImm ( ) , Orig -> getOperand ( <NUM_LIT> ) . getImm ( ) , Orig -> getOperand ( <NUM_LIT> ) . getReg ( ) , this , false , dl ) ; return ; } MachineInstr * MI = MBB . getParent (


<s> MachineBasicBlock :: iterator I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( I -> getOpcode ( ) != BOpc && I -> getOpcode ( ) != BccOpc ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end


<s> MachineInstr * PopMI = MF . CreateMachineInstr ( get ( <STR_LIT> ) , MI -> getDebugLoc ( ) ) ; MBB . insert ( MI , PopMI ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( Reg ==


<s> bool <ISA_LIT>InstrInfo :: ReverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { <STR_LIT> CC = ( <STR_LIT> ) ( int ) Cond [ <NUM_LIT> ] . getImm ( ) ; Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ( CC ) ) ; return false


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! AFI -> isThumbFunction ( ) || CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT>


<s> MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! AFI -> isThumbFunction ( ) || CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg


<s> if ( RC == <STR_LIT> ) { <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> isThumbFunction ( ) ) { Opc = Addr [ <NUM_LIT> ] . isFI ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; NewMIs . push_back ( MIB ) ; return ; } Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else { assert ( RC == <STR_LIT> &&


<s> DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; unsigned Opc = <NUM_LIT> ; if ( RC == <STR_LIT> ) { <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> isThumbFunction ( ) ) { Opc = Addr [ <NUM_LIT> ] . isFI ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; NewMIs . push_back ( MIB ) ; return ; } Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else { assert ( RC == <STR_LIT>


<s> assert ( ! AFI -> isThumbFunction ( ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; } else if ( RC == <STR_LIT> ) { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( AFI -> isThumbFunction ( ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; } else if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) .

addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ) ;


<s> bool <ISA_LIT>InstrInfo :: SubsumesPredicate ( const SmallVectorImpl < MachineOperand > & Pred1 , const SmallVectorImpl < MachineOperand > & Pred2 ) const { if ( Pred1 . size ( ) > <NUM_LIT> || Pred2 . size ( ) > <NUM_LIT> ) return false ; <STR_LIT> CC1 = ( <STR_LIT> ) Pred1 [ <NUM_LIT> ] . getImm ( ) ; <STR_LIT> CC2 = ( <STR_LIT> ) Pred2 [ <NUM_LIT> ] . getImm ( ) ; if ( CC1 == CC2 )


<s> void <ISA_LIT>InstrInfo :: expandLoadStackGuard ( MachineBasicBlock :: iterator MI ) const { MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; if ( ! Subtarget . useMovt ( MF ) ) { if ( TM . isPositionIndependent ( ) ) expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; else expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } if ( ! TM . isPositionIndependent ( ) ) { expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; if ( ! Subtarget . isGVIndirectSymbol ( GV ) ) { expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable


<s> virtual MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned >


<s> virtual const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return


<s> expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; if ( ! Subtarget . isGVIndirectSymbol ( GV ) ) { expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( * MBB . getParent ( ) ) , Flags , <NUM_LIT> , <NUM_LIT> ) ; MIB . addMemOperand ( MMO ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . cloneMemRefs ( * MI )


<s> return ; } const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; if ( ! Subtarget . isGVIndirectSymbol ( GV ) ) { expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand


<s> reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr * Orig , const TargetRegisterInfo * TRI ) const { DebugLoc dl = Orig -> getDebugLoc ( ) ; unsigned Opcode = Orig -> getOpcode ( ) ; switch ( Opcode ) { default : break ; case <STR_LIT> :


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> getGlobalBaseReg ( ) == <NUM_LIT> ) return false ; const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF . getTarget ( ) ) ; if ( TM -> getRelocationModel ( ) != Reloc :: PIC_ ) return false ; LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * Context , <STR_LIT> ,


<s> MachineInstrBuilder MIB ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; unsigned Flag = MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( ) , Flag , <NUM_LIT> , <NUM_LIT> ) ; MIB . addMemOperand ( MMO ) ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; MIB . setMemRefs ( MI -> memoperands_begin (


<s> unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = STI . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * Context , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; unsigned Align = TM . getDataLayout ( ) -> getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned TempReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; unsigned Opc = STI . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetInstrInfo & TII = * STI


<s> case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ; case <STR_LIT> : { if ( OpNum == <NUM_LIT> ) { unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RI . isPhysicalRegister ( SrcReg ) && ! RI . isLowRegister ( SrcReg ) ) return false ; } else { unsigned DstReg = MI -> getOperand (


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( DestRC == <STR_LIT> ) { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> isThumbFunction ( ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg )


<s> else AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ) ; } else if ( DestRC == <STR_LIT> ) AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; else if ( DestRC == <STR_LIT> ) AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; else return false ; return


<s> unsigned NumOps = TID . getNumOperands ( ) ; MachineOperand JTOP = MI -> getOperand ( NumOps - ( TID . isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOP . getIndex ( ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; assert ( JTI < JT . size ( ) ) ; return getNumJTEntries ( JT , JTI ) * <NUM_LIT> + ( MI -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; } default : return <NUM_LIT> ; } } } return


<s> case <STR_LIT> : case <STR_LIT> : assert ( MI . getDesc ( ) . getNumOperands ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; SrcReg = MI . getOperand ( <NUM_LIT>


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return true ; case <STR_LIT> : case <STR_LIT> : assert ( MI . getDesc ( ) . getNumOperands ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return


<s> unsigned Opc = <NUM_LIT> ; if ( RC == <STR_LIT> ) { <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> isThumbFunction ( ) ) { Opc = Addr [ <NUM_LIT> ] . isFI ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) , DestReg ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; NewMIs . push_back ( MIB ) ; return ; } Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else { assert ( RC == <STR_LIT> && <STR_LIT>


<s> loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == <STR_LIT> ) { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> isThumbFunction ( ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; } else if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ) ; } else { assert ( RC == <STR_LIT> && <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg )


<s> return true ; } int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) { MachineOperand & PMO = MI -> getOperand ( PIdx ) ; PMO . setImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) ; MI -> getOperand ( PIdx + <NUM_LIT> ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; return true ; } return


<s> MI -> setDesc ( get ( Opc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; MI -> addOperand ( MachineOperand :: CreateImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) ) ; MI -> addOperand ( MachineOperand :: CreateReg ( Pred [ <NUM_LIT> ] . getReg ( ) , false ) ) ; return true ; } int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) { MachineOperand & PMO = MI ->


<s> bool <ISA_LIT>InstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! AFI -> isThumbFunction ( ) || CSI . empty ( ) ) return false ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > <NUM_LIT> ; MachineInstr * PopMI = MF . CreateMachineInstr ( get ( <STR_LIT> ) , MI -> getDebugLoc ( ) ) ; MBB . insert ( MI , PopMI ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( Reg == <STR_LIT> ) { if ( isVarArg ) continue ; Reg = <STR_LIT> ; PopMI -> setDesc ( get ( <STR_LIT> ) ) ; MBB . erase ( MI ) ; } PopMI -> addOperand ( MachineOperand :: CreateReg ( Reg


<s> bool <ISA_LIT>InstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! AFI -> isThumbFunction ( ) || CSI . empty ( ) ) return false ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > <NUM_LIT> ; MachineInstr * PopMI = MF . CreateMachineInstr ( get ( <STR_LIT> ) , MI -> getDebugLoc ( ) ) ; MBB . insert ( MI , PopMI ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( Reg == <STR_LIT> ) { if ( isVarArg ) continue ; Reg = <STR_LIT> ; PopMI -> setDesc ( get


<s> for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , false ,


<s> bool <ISA_LIT>InstrInfo :: SubsumesPredicate ( const SmallVectorImpl < MachineOperand > & Pred1 , const SmallVectorImpl < MachineOperand > & Pred2 ) const { if ( Pred1 . size ( ) > <NUM_LIT> || Pred2 . size ( ) > <NUM_LIT> ) return false ; <STR_LIT> CC1 = ( <STR_LIT> ) Pred1 [ <NUM_LIT> ] . getImm ( ) ; <STR_LIT> CC2 = ( <STR_LIT> ) Pred2 [ <NUM_LIT> ] . getImm ( ) ; if ( CC1 == CC2 ) return true ; switch ( CC1 ) { default : return false ; case <STR_LIT> : return true ; case <STR_LIT> : return CC2 == <STR_LIT> ; case <STR_LIT>


<s> DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; unsigned Opc = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetInstrInfo & TII = * TM -> getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred (


<s> unsigned TempReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; unsigned Opc = STI . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , TempReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; Opc = STI . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addReg ( TempReg ) . addImm ( <ISA_LIT>PCLabelIndex ) ; if ( Opc == <STR_LIT> ) AddDefaultPred ( MIB ) ; return


<s> unsigned PCAdj = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * Context , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; unsigned Align = TM -> getSubtargetImpl ( ) -> getDataLayout ( ) -> getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned TempReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; unsigned Opc = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb2 (


<s> const unsigned Mask = <STR_LIT> ; return std :: make_pair ( TF & Mask , TF & ~


<s> const unsigned Mask = <STR_LIT> ; return std :: make_pair ( TF &


<s> void <ISA_LIT>InstrInfo :: expandLoadStackGuard ( MachineBasicBlock :: iterator MI ) const { MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; if ( ! Subtarget . useMovt ( MF ) ) { if ( TM . isPositionIndependent ( ) ) expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; else expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } if ( ! TM . isPositionIndependent ( ) ) { expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; if ( ! Subtarget . isGVIndirectSymbol


<s> unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; unsigned Opc = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetInstrInfo & TII = * TM -> getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == <STR_LIT> ) MIB . addImm ( <NUM_LIT>


<s> NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; NopInst . addOperand ( MCOperand ::


<s> FunctionPass * llvm :: create<ISA_LIT>GlobalBaseRegPass


<s> AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> } else { NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg


<s> unsigned Opc = STI . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , TempReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; Opc = STI . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc )

, GlobalBaseReg ) . addReg ( TempReg ) . addImm ( <ISA_LIT>PCLabelIndex ) ;


<s> <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * Context , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; unsigned Align = MF . getDataLayout ( ) . getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned TempReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; unsigned Opc = STI . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , TempReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; Opc = STI . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addReg ( TempReg ) . addImm ( <ISA_LIT>PCLabelIndex ) ; if ( Opc == <STR_LIT> ) AddDefaultPred ( MIB


<s> return new <ISA_LIT>InstructionSelector ( TM , STI


<s> static const char * getName ( ) { return DEBUG_TYPE


<s> const RegisterBank * RegBank = RBI . getRegBank ( Reg , MRI , TRI ) ; assert ( RegBank && <STR_LIT> ) ; const unsigned Size = MRI . getType ( Reg ) . getSizeInBits ( ) ; assert ( ( RegBank -> getID ( ) == <STR_LIT> || RegBank -> getID ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( RegBank -> getID ( ) == <STR_LIT> ) { if ( Size == <NUM_LIT> ) return & <STR_LIT> ; else if ( Size == <NUM_LIT> ) return & <STR_LIT> ; else if ( Size == <NUM_LIT> ) return &