<s> } unsigned Op2Reg = <NUM_LIT> ; if ( ! UseImm ) { Op2Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2Reg == <NUM_LIT> ) return false ; } unsigned CmpOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; CondReg = constrainOperandRegClass ( TII . get ( CmpOpc ) , CondReg , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CmpOpc ) ) . addReg ( CondReg ) . addImm ( <NUM_LIT> ) ) ; unsigned MovCCOpc ; const TargetRegisterClass * RC ; if ( ! UseImm ) { RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; MovCCOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; } else { RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; if ( ! isNegativeImm ) MovCCOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; else MovCCOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; } unsigned ResultReg = createResultReg ( RC ) ; if ( ! UseImm ) { Op2Reg = constrainOperandRegClass ( TII . get ( MovCCOpc ) , Op2Reg , <NUM_LIT> ) ; Op1Reg = constrainOperandRegClass ( TII . get ( MovCCOpc ) , Op1Reg , <NUM_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( MovCCOpc ) , ResultReg ) . addReg ( Op2Reg ) . addReg ( Op1Reg ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; }


<s> if ( ! isTypeLegal ( I -> getType ( ) , VT ) ) return false ; if ( VT != <STR_LIT> ) return false ; unsigned CondReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( CondReg == <NUM_LIT> ) return false ; unsigned Op1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1Reg == <NUM_LIT> ) return false ; int Imm = <NUM_LIT> ; bool UseImm = false ; bool isNegativeImm = false ; if ( const ConstantInt * ConstInt = dyn_cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) ) { assert ( VT == <STR_LIT> && <STR_LIT> ) ; Imm = ( int ) ConstInt -> getValue ( ) . getZExtValue ( ) ; if ( Imm < <NUM_LIT> ) { isNegativeImm = true ; Imm = ~ Imm ; } UseImm = isThumb2 ? ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) : ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) ; } unsigned Op2Reg = <NUM_LIT> ; if ( ! UseImm ) { Op2Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2Reg == <NUM_LIT> ) return false ; } unsigned CmpOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; CondReg = constrainOperandRegClass ( TII . get ( CmpOpc ) , CondReg , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CmpOpc ) ) . addReg ( CondReg ) . addImm ( <NUM_LIT> ) ) ; unsigned MovCCOpc ; const TargetRegisterClass * RC ; if ( ! UseImm ) { RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; MovCCOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; } else { RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; if ( ! isNegativeImm ) MovCCOpc = isThumb2 ? <STR_LIT> :


<s> case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; } unsigned Op1 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1 == <NUM_LIT> ) return false ; unsigned Op2 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2 == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT . SimpleTy ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( Op1 ) . addReg ( Op2 ) ) ; updateValueMap ( I ,


<s> } case Instruction :: PtrToInt : { if ( TLI . getValueType ( U -> getType ( ) ) == TLI . getPointerTy ( ) ) return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; } case Instruction :: GetElementPtr : { Address SavedAddr = Addr ; int TmpOffset = Addr . Offset ; gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: const_op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { const Value * Op = * i ; if ( StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = TD . getStructLayout ( STy ) ; unsigned Idx = cast < ConstantInt > ( Op ) -> getZExtValue ( ) ; TmpOffset += SL -> getElementOffset ( Idx ) ; } else { uint64_t S = TD . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { TmpOffset += CI -> getSExtValue ( ) * S ; break ; } if ( isa < AddOperator > ( Op ) && ( ! isa < Instruction > ( Op ) || FuncInfo . MBBMap [ cast < Instruction > ( Op ) -> getParent ( ) ] == FuncInfo . MBB ) && isa < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ) { ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; TmpOffset += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } goto unsupported_gep ; } } } Addr . Offset = TmpOffset ; if ( <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ) return true ; Addr = SavedAddr ; unsupported_gep : break ; } case Instruction :: Alloca : { const AllocaInst * AI = cast < AllocaInst > (


<s> ArgFlags . reserve ( I -> getNumOperands ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < I -> getNumOperands ( ) ; ++ i ) { Value * Op = I -> getOperand ( i ) ; unsigned Arg = getRegForValue ( Op ) ; if ( Arg == <NUM_LIT> ) return false ; Type * ArgTy = Op -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) ) return false ; <STR_LIT> Flags ; unsigned OriginalAlignment = TD . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( Op ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes ) ) return false ; MachineInstrBuilder MIB ; unsigned CallOpc = <ISA_LIT>SelectCallOp ( NULL ) ; if ( isThumb ) MIB = AddDefaultPred ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CallOpc ) ) ) . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ; else MIB = AddDefaultPred ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CallOpc ) ) . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ) ; for ( unsigned i = <NUM_LIT> , e = RegArgs . size ( ) ; i != e ; ++ i ) MIB . addReg ( RegArgs [ i ] ) ; SmallVector < unsigned , <NUM_LIT>


<s> unsigned Arg = getRegForValue ( Op ) ; if ( Arg == <NUM_LIT> ) return false ; Type * ArgTy = Op -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) ) return false ; <STR_LIT> Flags ; unsigned OriginalAlignment = TD . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( Op ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes ) ) return false ; MachineInstrBuilder MIB ; unsigned CallOpc = <ISA_LIT>SelectCallOp ( NULL ) ; if ( isThumb ) MIB = AddDefaultPred ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get

( CallOpc ) ) ) . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ;


<s> case <STR_LIT> : Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT ) ; ResultReg = createResultReg ( RC ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) ; AddLoadStoreOperands ( VT , Addr , MIB , MachineMemOperand :: MOLoad ) ; return


<s> case <STR_LIT> : StrOpc = isThumb ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : StrOpc = isThumb ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; StrOpc = <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; StrOpc = <STR_LIT> ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( StrOpc ) ) . addReg ( SrcReg , getKillRegState ( true ) ) ; AddLoadStoreOperands ( VT , Addr , MIB , MachineMemOperand :: MOStore ) ; return true


<s> case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; StrOpc = <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; StrOpc = <STR_LIT> ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( StrOpc ) ) . addReg ( SrcReg , getKillRegState ( true ) ) ; AddLoadStoreOperands ( VT , Addr , MIB , MachineMemOperand :: MOStore ) ; return


<s> } unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , Id , <STR_LIT> , PCAdj ) ; unsigned Idx = MCP . getConstantPoolIndex ( CPV , Align ) ; MachineInstrBuilder MIB ; unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; if ( isThumb ) { unsigned Opc = ( RelocM != Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx ) ; if ( RelocM == Reloc :: PIC_ ) MIB . addImm ( Id ) ; } else { MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ; } AddOptionalDefs ( MIB ) ; if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ) { unsigned NewDestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; if ( isThumb ) MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , NewDestReg ) . addReg ( DestReg ) . addImm ( <NUM_LIT> ) ; else MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , NewDestReg ) . addReg ( DestReg ) .


<s> unsigned <ISA_LIT>FastISel :: <ISA_LIT>SelectCallOp ( const GlobalValue * GV ) { bool isDarwin = Subtarget -> isTargetDarwin ( ) ; if ( isThumb )


<s> case CallingConv :: Fast : ( void ) RetFastCC_<ISA_LIT>_APCS ; ( void ) FastCC_<ISA_LIT>_APCS ; case CallingConv :: C : if ( Subtarget -> isAAPCS_ABI ( ) ) { if ( Subtarget -> hasVFP2 ( ) && FloatABIType == FloatABI :: Hard ) return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; else return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; } else return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS ) ; case CallingConv :: <ISA_LIT>_AAPCS_VFP : return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; case CallingConv :: <ISA_LIT>_AAPCS : return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; case CallingConv :: <ISA_LIT>_APCS : return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS ) ; case CallingConv ::


<s> const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( ! MCID . hasOptionalDef ( ) ) return false ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO


<s> if ( VT == <STR_LIT> || VT == <STR_LIT> ) return true ; return


<s> assert ( Emitted && <STR_LIT> ) ; ( void ) Emitted ; ArgVT = VA . getLocVT ( ) ; break ; } case CCValAssign :: BCvt : { unsigned BC = FastEmit_r ( ArgVT , VA . getLocVT ( ) , <STR_LIT> , Arg , false ) ; assert ( BC != <NUM_LIT> && <STR_LIT> ) ; Arg = BC ; ArgVT = VA . getLocVT ( ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( Arg ) ; RegArgs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) != <STR_LIT> ) return false ; CCValAssign & NextVA = ArgLocs [ ++ i ] ; if ( ! ( VA . isRegLoc ( ) && NextVA . isRegLoc ( ) ) ) return false ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , VA . getLocReg ( ) ) . addReg ( NextVA . getLocReg ( ) , RegState :: Define ) . addReg ( Arg ) ) ; RegArgs . push_back ( VA . getLocReg ( ) ) ; RegArgs . push_back ( NextVA . getLocReg ( ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; Address Addr ; Addr . BaseType = Address :: RegBase ; Addr . Base . Reg = <STR_LIT> ; Addr . Offset = VA . getLocMemOffset (


<s> Type * Ty = I -> getType ( ) ; bool isFloat = ( Ty -> isDoubleTy ( ) || Ty -> isFloatTy ( ) ) ; if ( isFloat && ! Subtarget -> hasVFP2 ( ) ) return false ; unsigned Op1 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1 == <NUM_LIT> ) return false ; unsigned Op2 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2 == <NUM_LIT> ) return false ; unsigned Opc ; bool is64bit = VT == <STR_LIT> || VT == <STR_LIT> ; switch ( ISDOpcode ) { default : return false ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT>


<s> CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = isThumb ? <STR_LIT> : <STR_LIT> ; break ; } CmpInst :: Predicate Predicate = CI -> getPredicate ( ) ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; Predicate = CmpInst :: getInversePredicate ( Predicate ) ; } <STR_LIT> <ISA_LIT>Pred = getComparePred ( Predicate ) ; if ( <ISA_LIT>Pred == <STR_LIT> ) return false ; unsigned Arg1 = getRegForValue ( CI -> getOperand ( <NUM_LIT> ) ) ; if ( Arg1 == <NUM_LIT> ) return false ; unsigned Arg2 = getRegForValue ( CI -> getOperand ( <NUM_LIT> ) ) ; if ( Arg2 == <NUM_LIT> ) return false ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CmpOpc ) ) . addReg ( Arg1 ) . addReg ( Arg2 ) ) ; if ( isFloat ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) ) ) ; unsigned BrOpc = isThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( BrOpc ) ) . addMBB ( TBB ) . addImm ( <ISA_LIT>Pred ) . addReg ( <STR_LIT> ) ; FastEmitBranch ( FBB , DL ) ; FuncInfo . MBB -> addSuccessor ( TBB ) ; return true ; } } else if ( TruncInst * TI = dyn_cast < TruncInst > ( BI -> getCondition ( ) ) ) { MVT SourceVT ; if ( TI -> hasOneUse ( ) && TI -> getParent ( ) == I -> getParent ( ) && ( isLoadTypeLegal ( TI -> getOperand ( <NUM_LIT> ) -> getType ( ) , SourceVT ) ) ) { unsigned TstOpc = isThumb ? <STR_LIT> : <STR_LIT> ; unsigned OpReg = getRegForValue ( TI -> getOperand ( <NUM_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TstOpc ) ) . addReg ( OpReg ) . addImm ( <NUM_LIT> ) ) ; unsigned CCMode = <STR_LIT> ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; CCMode = <STR_LIT> ; } unsigned BrOpc = isThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( BrOpc ) ) . addMBB ( TBB ) . addImm ( CCMode ) . addReg ( <STR_LIT> ) ; FastEmitBranch ( FBB , DL ) ; FuncInfo . MBB -> addSuccessor ( TBB ) ; return


<s> const CallInst * CI = cast < CallInst > ( I ) ; const Value * Callee = CI -> getCalledValue ( ) ; if ( isa < InlineAsm > ( Callee ) || isa < IntrinsicInst > ( CI ) ) return false ; const GlobalValue * GV = dyn_cast < GlobalValue > ( Callee ) ; if ( ! GV ) return false ; ImmutableCallSite CS ( CI ) ; CallingConv :: ID CC = CS . getCallingConv ( ) ; PointerType * PT = cast < PointerType > ( CS . getCalledValue ( ) -> getType ( ) ) ; FunctionType * FTy = cast < FunctionType > ( PT -> getElementType ( ) ) ; if ( FTy -> isVarArg ( ) ) return false ; Type * RetTy = I -> getType ( ) ; MVT RetVT ; if ( RetTy -> isVoidTy ( ) ) RetVT = <STR_LIT> ; else if ( ! isTypeLegal ( RetTy , RetVT ) ) return false ; if ( Enable<ISA_LIT>LongCalls ) return false ; SmallVector < Value * , <NUM_LIT> > Args ; SmallVector < unsigned , <NUM_LIT> > ArgRegs ; SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; Args . reserve ( CS . arg_size ( ) ) ; ArgRegs . reserve ( CS . arg_size ( ) ) ; ArgVTs . reserve ( CS . arg_size ( ) ) ; ArgFlags . reserve ( CS . arg_size ( ) ) ; for ( ImmutableCallSite :: arg_iterator i = CS . arg_begin ( ) , e = CS . arg_end ( ) ; i != e ; ++ i ) { unsigned Arg = getRegForValue ( * i ) ; if ( Arg == <NUM_LIT> ) return false ; <STR_LIT> Flags ; unsigned AttrInd = i - CS . arg_begin ( ) + <NUM_LIT> ; if ( CS . paramHasAttr ( AttrInd , Attribute :: SExt ) ) Flags . setSExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: ZExt ) ) Flags . setZExt


<s> if ( ! isTypeLegal ( Ty , VT ) ) return false ; bool isFloat = ( Ty -> isDoubleTy ( ) || Ty -> isFloatTy ( ) ) ; if ( isFloat && ! Subtarget -> hasVFP2 ( ) ) return false ; unsigned CmpOpc ; unsigned CondReg ; switch ( VT . SimpleTy ) { default : return false ; case <STR_LIT> : CmpOpc = <STR_LIT> ; CondReg = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; CondReg = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = isThumb ? <STR_LIT> : <STR_LIT> ; CondReg = <STR_LIT> ; break ; } <STR_LIT> <ISA_LIT>Pred = getComparePred ( CI -> getPredicate ( ) ) ; if ( <ISA_LIT>Pred == <STR_LIT> ) return false ; unsigned Arg1 = getRegForValue ( CI -> getOperand ( <NUM_LIT> ) ) ; if ( Arg1 == <NUM_LIT> )


<s> if ( ! <ISA_LIT>ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned ResultReg ; if ( ! <ISA_LIT>EmitLoad ( VT , ResultReg , Addr ) ) return false ; UpdateValueMap ( I , ResultReg ) ; return true


<s> if ( ! VA . isRegLoc ( ) ) return false ; if ( TLI . getValueType ( RV -> getType ( ) ) != VA . getValVT ( ) ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; unsigned DstReg = VA . getLocReg ( ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; if ( ! SrcRC -> contains ( DstReg ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( SrcReg ) ; MRI . addLiveOut ( VA .


<s> SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , TM , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , CCAssignFnForCall ( CC , true ) ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; if ( TLI . getValueType ( RV -> getType ( ) ) != VA


<s> bool <ISA_LIT>FastISel :: SelectSIToFP ( const Instruction * I ) { if ( ! Subtarget -> hasVFP2 ( ) ) return false ; MVT DstVT ; Type * Ty = I -> getType ( ) ; if ( ! isTypeLegal ( Ty , DstVT ) ) return false ; if ( ! I -> getOperand ( <NUM_LIT> ) -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) return false ; unsigned Op = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op == <NUM_LIT> ) return false ; unsigned FP = <ISA_LIT>MoveToFPReg ( <STR_LIT> , Op ) ; if ( FP == <NUM_LIT> ) return false ; unsigned Opc ; if ( Ty -> isFloatTy ( ) ) Opc = <STR_LIT> ; else if ( Ty -> isDoubleTy ( ) ) Opc = <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor (


<s> bool <ISA_LIT>FastISel :: SelectStore ( const Instruction * I ) { Value * Op0 = I -> getOperand ( <NUM_LIT> ) ; unsigned SrcReg = <NUM_LIT> ; if ( cast < StoreInst > ( I ) -> isAtomic ( ) ) return false ; MVT VT ; if ( ! isLoadTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( )


<s> } unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addImm ( Imm ) ) ; return DestReg ; } if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( ! Subtarget -> useConstIslands ( ) ) return false ; unsigned Align = TD . getPrefTypeAlignment ( CFP -> getType ( ) ) ; if ( Align ==


<s> if ( ! Subtarget -> useConstIslands ( ) ) return false ; unsigned Align = TD . getPrefTypeAlignment ( GV -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( GV -> getType ( ) ) ; } if ( Subtarget -> isTargetELF ( ) && RelocM == Reloc :: PIC_ ) return <ISA_LIT>LowerPICELF ( GV , Align , VT ) ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , Id , <STR_LIT> , PCAdj ) ; unsigned Idx = MCP . getConstantPoolIndex ( CPV , Align ) ; MachineInstrBuilder MIB ; if ( isThumb2 ) { unsigned Opc = ( RelocM != Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx ) ; if ( RelocM == Reloc :: PIC_ ) MIB . addImm ( Id ) ; AddOptionalDefs ( MIB ) ; } else { DestReg = constrainOperandRegClass ( TII . get ( <STR_LIT> ) , DestReg , <NUM_LIT> ) ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ; AddOptionalDefs ( MIB ) ; if ( RelocM == Reloc :: PIC_ ) { unsigned Opc = IsIndirect ? <STR_LIT> : <STR_LIT> ; unsigned NewDestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , NewDestReg ) . addReg ( DestReg ) . addImm ( Id ) ; AddOptionalDefs (


<s> } if ( VT == <STR_LIT> && Subtarget -> hasV6T2Ops ( ) && CI -> isNegative ( ) ) { unsigned Imm = ( unsigned ) ~ ( CI -> getSExtValue ( ) ) ; bool UseImm = isThumb2 ? ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) : ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) ; if ( UseImm ) { unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned ImmReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ImmReg ) . addImm ( Imm ) ) ; return ImmReg ; } } if ( ! Subtarget -> useConstIslands ( ) && Subtarget -> hasV6T2Ops ( ) && VT == <STR_LIT> ) { unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ImmReg ) . addImm ( CI -> getZExtValue ( ) ) ) ; return ImmReg ; } if ( ! Subtarget -> useConstIslands ( ) ) return false ; if ( VT != <STR_LIT> ) return false ; unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; unsigned Align = TD . getPrefTypeAlignment ( C -> getType ( ) ) ; if ( Align ==


<s> unsigned Opc ; bool useAM3 = false ; TargetRegisterClass * RC ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = isZExt ? <STR_LIT> : <STR_LIT> ; else Opc = isZExt ? <STR_LIT> : <STR_LIT> ; } else { if ( isZExt ) { Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; useAM3 = true ; } } RC = <STR_LIT> ; break ; case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = isZExt ? <STR_LIT> : <STR_LIT> ; else Opc = isZExt ? <STR_LIT> : <STR_LIT> ; } else { Opc = isZExt ? <STR_LIT> : <STR_LIT> ; useAM3 = true ; } RC = <STR_LIT> ; break ; case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; } RC = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; case <STR_LIT> : Opc = <STR_LIT>


<s> unsigned Res = createResultReg ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , Res ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ) ; SrcReg = Res ; } case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else { StrOpc = <STR_LIT> ; } break ; case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else { StrOpc = <STR_LIT> ; useAM3 = true ; } break ; case <STR_LIT> : if ( isThumb2


<s> MachineInstrBuilder MIB ; unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; if ( isThumb2 ) { unsigned Opc = ( RelocM != Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx ) ; if ( RelocM == Reloc :: PIC_ ) MIB . addImm ( Id ) ; } else { MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ; } AddOptionalDefs ( MIB ) ; if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ) { unsigned NewDestReg = createResultReg ( TLI .


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! useAM3 ) { needsLowering = ( ( Addr . Offset & <NUM_LIT> ) != Addr . Offset ) ; if ( needsLowering && isThumb2 ) needsLowering = ! ( Subtarget -> hasV6T2Ops ( ) && Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> ) ; } else { needsLowering = ( Addr . Offset > <NUM_LIT> || Addr . Offset < - <NUM_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : needsLowering = ( ( Addr . Offset & <NUM_LIT> ) != Addr . Offset ) ; break ; } if ( needsLowering && Addr . BaseType == Address :: FrameIndexBase ) { TargetRegisterClass * RC = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , * FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( Addr . Base . FI ) . addImm ( <NUM_LIT> ) ) ; Addr . Base . Reg = ResultReg


<s> while ( Len ) { MVT VT ; if ( Len >= <NUM_LIT> ) VT = <STR_LIT> ; else if ( Len >= <NUM_LIT> ) VT = <STR_LIT> ; else { assert ( Len == <NUM_LIT> ) ; VT = <STR_LIT> ; } bool RV ; unsigned ResultReg ; RV = <ISA_LIT>EmitLoad ( VT , ResultReg , Src ) ; assert ( RV = true && <STR_LIT>


<s> CCState CCInfo ( CC , false , * FuncInfo . MF , TM , ArgLocs , * Context ) ; CCInfo . AnalyzeCallOperands ( ArgVTs , ArgFlags , CCAssignFnForCall ( CC , false ) ) ; NumBytes = CCInfo . getNextStackOffset ( ) ; unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( AdjStackDown ) ) . addImm ( NumBytes ) ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; unsigned Arg = ArgRegs [ VA . getValNo ( ) ] ; MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; if ( ArgVT . isVector ( ) || ArgVT . getSizeInBits ( ) > <NUM_LIT> ) return false ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: SExt : { EVT DestVT = VA . getLocVT ( ) ; unsigned ResultReg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , false ) ; assert ( ResultReg != <NUM_LIT> && <STR_LIT> ) ; Arg = ResultReg ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { EVT DestVT = VA . getLocVT ( ) ; unsigned ResultReg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , true ) ; assert ( ResultReg != <NUM_LIT> && <STR_LIT> ) ; Arg = ResultReg ; break ; } case CCValAssign :: BCvt : { unsigned BC = FastEmit_r ( ArgVT , VA . getLocVT ( ) , <STR_LIT> , Arg , false ) ; assert ( BC != <NUM_LIT> && <STR_LIT> ) ; Arg = BC ; ArgVT = VA . getLocVT ( ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( Arg ) ; RegArgs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) != <STR_LIT>


<s> unsigned ResultReg = createResultReg ( RC ) ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , * FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( SI ->


<s> case <STR_LIT> : case <STR_LIT> : if ( VT != <STR_LIT> ) return false ; break ; } Address Addr ; if ( ! <ISA_LIT>ComputeAddress ( LI -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned ResultReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <ISA_LIT>EmitLoad ( VT , ResultReg , Addr , isZExt , false ) ) return false ; MI -> eraseFromParent (


<s> case <STR_LIT> : case <STR_LIT> : isZExt = false ; case <STR_LIT> : case <STR_LIT> : if ( VT != <STR_LIT> ) return false ; break ; } Address Addr ; if ( ! <ISA_LIT>ComputeAddress ( LI -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned ResultReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <ISA_LIT>EmitLoad ( VT , ResultReg , Addr , isZExt , false ) ) return false ; MI -> eraseFromParent ( ) ; return true


<s> Type * ArgTy = ( * i ) -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> ) return false ; unsigned Arg = getRegForValue ( * i ) ; if ( Arg == <NUM_LIT> ) return false ; unsigned OriginalAlignment = DL . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( * i ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , isVarArg ) ) return false ; bool UseReg = false ; const GlobalValue * GV = dyn_cast < GlobalValue > ( Callee ) ; if ( ! GV || Subtarget -> genLongCalls ( ) ) UseReg = true ; unsigned CalleeReg = <NUM_LIT> ; if ( UseReg ) { if ( IntrMemName ) CalleeReg = getLibcallReg ( IntrMemName ) ; else CalleeReg = getRegForValue ( Callee ) ; if ( CalleeReg == <NUM_LIT> ) return false ; } unsigned CallOpc = <ISA_LIT>SelectCallOp ( UseReg ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CallOpc ) ) ; unsigned char OpFlags = <NUM_LIT> ; if ( Subtarget -> isTargetELF ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) OpFlags = <STR_LIT> ; if ( isThumb2 ) AddDefaultPred ( MIB ) ; if ( UseReg ) MIB . addReg ( CalleeReg ) ; else if ( ! IntrMemName ) MIB . addGlobalAddress ( GV ,


<s> ArgRegs . reserve ( I -> getNumOperands ( ) ) ; ArgVTs . reserve ( I -> getNumOperands ( ) ) ; ArgFlags . reserve ( I -> getNumOperands ( ) ) ; for ( Value * Op : I -> operands ( ) ) { unsigned Arg = getRegForValue ( Op ) ; if ( Arg == <NUM_LIT> ) return false ; Type * ArgTy = Op -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) ) return false ; <STR_LIT> Flags ; Flags . setOrigAlign ( DL . getABITypeAlign ( ArgTy ) ) ; Args . push_back ( Op ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < Register , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , false ) ) return false ; Register CalleeReg ; if ( Subtarget -> genLongCalls ( ) ) { CalleeReg = getLibcallReg ( TLI .


<s> bool <ISA_LIT>FastISel :: SelectCall ( const Instruction * I , const char * IntrMemName = nullptr ) { const CallInst * CI = cast < CallInst > ( I ) ; const Value * Callee = CI -> getCalledOperand ( ) ; if ( isa < InlineAsm > ( Callee ) ) return false ; if ( CI -> isTailCall ( ) ) return false ; CallingConv :: ID CC = CI -> getCallingConv ( ) ; FunctionType * FTy = CI -> getFunctionType ( ) ; bool isVarArg = FTy -> isVarArg ( ) ; Type * RetTy = I -> getType ( ) ; MVT RetVT ; if ( RetTy -> isVoidTy ( ) ) RetVT = <STR_LIT> ; else if ( ! isTypeLegal ( RetTy , RetVT ) && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return false ; if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , isVarArg , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , CCAssignFnForCall ( CC , true , isVarArg ) ) ; if ( RVLocs . size ( ) >= <NUM_LIT> && RetVT != <STR_LIT> ) return false ; } SmallVector < Value * , <NUM_LIT> > Args ; SmallVector < Register , <NUM_LIT> > ArgRegs ; SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; unsigned arg_size = CI -> arg_size ( ) ; Args . reserve ( arg_size ) ; ArgRegs . reserve ( arg_size ) ; ArgVTs . reserve ( arg_size ) ; ArgFlags . reserve ( arg_size ) ; for ( auto ArgI = CI -> arg_begin ( ) , ArgE = CI -> arg_end ( ) ; ArgI != ArgE ; ++ ArgI ) { if ( IntrMemName && ArgE - ArgI <= <NUM_LIT> ) break ; <STR_LIT> Flags ; unsigned ArgIdx = ArgI - CI


<s> break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = isZExt ? <STR_LIT> : <STR_LIT> ; else Opc = isZExt ? <STR_LIT> : <STR_LIT> ; } else { Opc = isZExt ? <STR_LIT> : <STR_LIT> ; useAM3 = true ; } RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; } RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2Base ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { needVMOV = true ; VT = <STR_LIT> ; Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2Base ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) return false ; Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT , useAM3 ) ; if ( allocReg ) ResultReg = createResultReg ( RC ) ; assert ( ResultReg > <NUM_LIT> && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; AddLoadStoreOperands ( VT , Addr , MIB , MachineMemOperand :: MOLoad , useAM3 ) ; if ( needVMOV ) { unsigned MoveReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , MoveReg ) . addReg ( ResultReg ) ) ; ResultReg = MoveReg ; } return


<s> switch ( ArgVT . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2Base ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2Base ( ) ) return false ; break ; } } } NumBytes = CCInfo . getNextStackOffset ( ) ; unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( AdjStackDown ) ) . addImm ( NumBytes ) . addImm ( <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const Value * ArgVal = Args [ VA . getValNo ( ) ] ; unsigned Arg = ArgRegs [ VA . getValNo ( ) ] ; MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; assert ( ( ! ArgVT . isVector ( ) && ArgVT . getSizeInBits ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , false ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , true


<s> if ( Subtarget -> hasV6T2Ops ( ) && isUInt < <NUM_LIT> > ( CI -> getZExtValue ( ) ) ) { unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( CI -> getZExtValue ( ) ) ) ; return ImmReg ; } if ( VT == <STR_LIT> && Subtarget -> hasV6T2Ops ( ) && CI -> isNegative ( ) ) { unsigned Imm = ( unsigned ) ~ ( CI -> getSExtValue ( ) ) ; bool UseImm = isThumb2 ? ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) : ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) ; if ( UseImm ) { unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned ImmReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( Imm ) ) ; return ImmReg ; } } if ( ! Subtarget -> useConstIslands ( ) && Subtarget -> hasV6T2Ops ( ) && VT == <STR_LIT> ) { unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( CI -> getZExtValue ( ) ) ) ; return ImmReg ; } if ( ! Subtarget -> useConstIslands ( ) ) return false ; if ( VT != <STR_LIT> ) return false ; unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT


<s> explicit <ISA_LIT>FastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) : FastISel ( funcInfo , libInfo ) , M ( const_cast < Module & > ( * funcInfo . Fn -> getParent ( ) ) ) , TM ( funcInfo . MF ->

getTarget ( ) ) , TII ( * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) , TLI ( * TM . getSubtargetImpl ( ) -> getTargetLowering ( ) ) {


<s> MFI -> setFrameAddressIsTaken ( true ) ; unsigned LdrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; const <ISA_LIT>BaseRegisterInfo * RegInfo = static_cast < const <ISA_LIT>BaseRegisterInfo * > ( TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( * ( FuncInfo . MF ) ) ; unsigned SrcReg = FramePtr ; unsigned DestReg ; unsigned Depth = cast < ConstantInt > ( I . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { DestReg = createResultReg ( RC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( LdrOpc ) , DestReg ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ) ; SrcReg = DestReg ; } updateValueMap ( & I , SrcReg ) ; return true ; } case <STR_LIT> : case <STR_LIT>


<s> } case <STR_LIT> : case <STR_LIT> : { const MemTransferInst & MTI = cast < MemTransferInst > ( I ) ; if ( MTI . isVolatile ( ) ) return false ; bool isMemCpy = ( I . getIntrinsicID ( ) == <STR_LIT> ) ; if ( isa < ConstantInt > ( MTI . getLength ( ) ) && isMemCpy ) { uint64_t Len = cast < ConstantInt > ( MTI . getLength ( ) ) -> getZExtValue ( ) ; if ( <ISA_LIT>IsMemCpySmall ( Len ) ) { Address Dest , Src ; if ( ! <ISA_LIT>ComputeAddress ( MTI . getRawDest ( ) , Dest ) || ! <ISA_LIT>ComputeAddress ( MTI . getRawSource ( ) , Src ) ) return false ; unsigned Alignment = MTI . getAlignment ( ) ; if ( <ISA_LIT>TryEmitSmallMemCpy ( Dest , Src , Len , Alignment ) ) return true ; } } if ( ! MTI . getLength ( ) -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) return false ; if ( MTI . getSourceAddressSpace ( ) > <NUM_LIT> || MTI . getDestAddressSpace ( ) > <NUM_LIT> ) return false ; const char * IntrMemName = isa < MemCpyInst > ( I ) ?


<s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : needsExt = true ; case <STR_LIT> : if ( isThumb2 ) { if ( ! UseImm ) CmpOpc = <STR_LIT> ; else CmpOpc = isNegativeImm ? <STR_LIT> : <STR_LIT> ; } else { if ( ! UseImm ) CmpOpc = <STR_LIT> ; else CmpOpc = isNegativeImm ? <STR_LIT> : <STR_LIT> ; } break ; } unsigned SrcReg1 = getRegForValue ( Src1Value ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 ; if ( ! UseImm ) { SrcReg2 = getRegForValue ( Src2Value ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } if ( needsExt ) { unsigned ResultReg ; ResultReg = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg1 , <STR_LIT> , isZExt ) ; if ( ResultReg == <NUM_LIT> ) return false ; SrcReg1 = ResultReg ; if ( ! UseImm ) { ResultReg = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg2 , <STR_LIT> , isZExt ) ; if ( ResultReg == <NUM_LIT> ) return false ; SrcReg2 = ResultReg ; } } if ( ! UseImm ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CmpOpc ) ) . addReg ( SrcReg1 ) . addReg ( SrcReg2 ) ) ; } else { MachineInstrBuilder MIB


<s> return ImmReg ; } if ( VT == <STR_LIT> && Subtarget -> hasV6T2Ops ( ) && CI -> isNegative ( ) ) { unsigned Imm = ( unsigned ) ~ ( CI -> getSExtValue ( ) ) ; bool UseImm = isThumb2 ? ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) : ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) ; if ( UseImm ) { unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( Imm ) ) ; return ImmReg ; } } unsigned ResultReg = <NUM_LIT> ; if ( Subtarget -> useMovt ( * FuncInfo . MF ) ) ResultReg = FastEmit_i ( VT , VT , <STR_LIT> , CI -> getZExtValue ( ) ) ; if ( ResultReg ) return ResultReg ; if ( VT != <STR_LIT> ) return <NUM_LIT> ; unsigned Align = DL . getPrefTypeAlignment ( C -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = DL . getTypeAllocSize ( C -> getType ( ) ) ; } unsigned Idx = MCP . getConstantPoolIndex ( C , Align ) ; ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; if ( isThumb2 ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) .


<s> MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; if ( ArgVT . isVector ( ) || ArgVT . getSizeInBits ( ) > <NUM_LIT> ) return false ; if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { continue ; } else if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) != <STR_LIT> || ! VA . isRegLoc ( ) || ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; } else { switch ( ArgVT . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; break ; } } } NumBytes = CCInfo . getNextStackOffset ( ) ; unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( AdjStackDown ) ) . addImm ( NumBytes ) ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const Value * ArgVal = Args [ VA . getValNo ( ) ] ; unsigned Arg = ArgRegs [ VA . getValNo ( ) ] ; MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; assert ( ( ! ArgVT . isVector ( ) && ArgVT . getSizeInBits ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , false ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , true ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: BCvt : { unsigned BC = FastEmit_r ( ArgVT , VA . getLocVT ( ) , <STR_LIT> , Arg , false ) ; assert ( BC != <NUM_LIT> && <STR_LIT> ) ; Arg = BC ; ArgVT = VA . getLocVT ( ) ; break ; } default : llvm_unreachable ( <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; break ; } } } NumBytes = CCInfo . getNextStackOffset ( ) ; unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( AdjStackDown ) ) . addImm ( NumBytes ) ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const Value * ArgVal = Args [ VA . getValNo ( ) ] ; unsigned Arg = ArgRegs [ VA . getValNo ( ) ] ; MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; assert ( ( ! ArgVT . isVector ( ) && ArgVT . getSizeInBits ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , false ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA


<s> default : return false ; case CallingConv :: Fast : case CallingConv :: C : case CallingConv :: <ISA_LIT>_AAPCS_VFP : case CallingConv :: <ISA_LIT>_AAPCS : case CallingConv :: <ISA_LIT>_APCS : break ; } unsigned Idx = <NUM_LIT> ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( Idx > <NUM_LIT> ) return false ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) ) return false ; Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : return false ; } } static const uint16_t GPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const TargetRegisterClass * RC = TLI . getRegClassFor ( <STR_LIT> ) ; Idx = <NUM_LIT> ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F ->


<s> case CallingConv :: Fast : case CallingConv :: C : case CallingConv :: <ISA_LIT>_AAPCS_VFP : case CallingConv :: <ISA_LIT>_AAPCS : case CallingConv :: <ISA_LIT>_APCS : break ; } unsigned Idx = <NUM_LIT> ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( Idx > <NUM_LIT> ) return false ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) ) return false ; Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : return false ; } } static const uint16_t GPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const TargetRegisterClass * RC = TLI . getRegClassFor ( <STR_LIT> ) ; Idx = <NUM_LIT> ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( I -> use_empty ( ) ) continue ; unsigned SrcReg = GPRArgRegs [ Idx ] ; unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( DstReg , getKillRegState ( true ) ) ; UpdateValueMap ( I , ResultReg ) ; } return


<s> break ; case <STR_LIT> : case <STR_LIT> : needsLowering = ( ( Addr . Offset & <NUM_LIT> ) != Addr . Offset ) ; break ; } if ( needsLowering && Addr . BaseType == Address :: FrameIndexBase ) { const TargetRegisterClass * RC = isThumb2 ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( Addr . Base . FI ) . addImm ( <NUM_LIT> ) ) ; Addr . Base . Reg = ResultReg ; Addr . BaseType = Address :: RegBase ; } if ( needsLowering ) { Addr . Base . Reg = fastEmit_ri_ ( <STR_LIT> , <STR_LIT> , Addr . Base . Reg , false , Addr . Offset , <STR_LIT> ) ; Addr . Offset


<s> Constant * Zero = ConstantInt :: get ( Type :: getInt32Ty ( * Context ) , <NUM_LIT> ) ; unsigned ZeroReg = fastMaterializeConstant ( Zero ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( MovCCOpc ) , DestReg ) . addReg ( ZeroReg ) . addImm ( <NUM_LIT> ) . addImm ( <ISA_LIT>Pred


<s> ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned DestReg = createResultReg ( RC ) ; Constant * Zero = ConstantInt :: get ( Type :: getInt32Ty ( * Context ) , <NUM_LIT> ) ; unsigned ZeroReg = fastMaterializeConstant ( Zero ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( MovCCOpc ) , DestReg ) . addReg ( ZeroReg ) . addImm ( <NUM_LIT> ) . addImm ( <ISA_LIT>Pred ) . addReg ( <STR_LIT> ) ; updateValueMap ( I , DestReg ) ; return


<s> if ( isThumb2 ) { LdrOpc = <STR_LIT> ; RC = ( const TargetRegisterClass * ) & <STR_LIT> ; } else { LdrOpc = <STR_LIT> ; RC = ( const TargetRegisterClass * ) & <STR_LIT> ; } const <ISA_LIT>BaseRegisterInfo * RegInfo = static_cast < const <ISA_LIT>BaseRegisterInfo * > ( TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( * ( FuncInfo . MF ) ) ; unsigned SrcReg = FramePtr ; unsigned DestReg ; unsigned Depth = cast < ConstantInt > ( I . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { DestReg = createResultReg ( RC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( LdrOpc ) , DestReg ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ) ; SrcReg = DestReg ; } updateValueMap ( & I , SrcReg ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { const MemTransferInst & MTI = cast < MemTransferInst > ( I ) ; if ( MTI . isVolatile


<s> } const <ISA_LIT>BaseRegisterInfo * RegInfo = static_cast < const <ISA_LIT>BaseRegisterInfo * > ( TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( * ( FuncInfo . MF ) ) ; unsigned SrcReg = FramePtr ; unsigned DestReg ; unsigned Depth = cast < ConstantInt > ( I . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { DestReg = createResultReg ( RC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( LdrOpc ) , DestReg ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ) ; SrcReg = DestReg ; } updateValueMap ( & I , SrcReg ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { const MemTransferInst & MTI = cast < MemTransferInst > ( I ) ; if ( MTI . isVolatile ( ) ) return false ; bool isMemCpy = ( I . getIntrinsicID ( ) == <STR_LIT> ) ; if ( isa < ConstantInt > ( MTI . getLength ( ) ) && isMemCpy ) { uint64_t Len = cast < ConstantInt > ( MTI . getLength ( ) ) -> getZExtValue ( ) ; if ( <ISA_LIT>IsMemCpySmall ( Len ) ) { Address Dest , Src ; if ( ! <ISA_LIT>ComputeAddress ( MTI . getRawDest ( ) , Dest ) || ! <ISA_LIT>ComputeAddress ( MTI . getRawSource ( ) , Src ) ) return false ; unsigned Alignment = MTI . getAlignment ( ) ; if ( <ISA_LIT>TryEmitSmallMemCpy ( Dest , Src , Len , Alignment ) ) return true ; } } if ( ! MTI . getLength ( ) -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) return false ; if ( MTI . getSourceAddressSpace ( ) > <NUM_LIT> || MTI . getDestAddressSpace ( ) > <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ; case <STR_LIT> : return Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> && Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> && Instr -> getOperand ( <NUM_LIT> ) . getReg (


<s> inline bool isV8EligibleForIT ( InstrType * Instr ) { switch ( Instr -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return IsCPSRDead ( Instr ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : return Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ; case <STR_LIT> : case <STR_LIT>


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( MOp . getReg ( ) , TRI ) << <STR_LIT> ) ; continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( MOp . getReg ( ) , TRI ) << <STR_LIT> ) ; NewLoc . Block = & MF . front ( ) ; NewLoc . InsertionPt = & * NewLoc . Block -> begin ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * NewLoc . InsertionPt ) ; FixupLocsForFn . emplace_back ( NewLoc ) ; continue ; } if ( IsLiveIn || UnsafeCount > <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << printReg ( MOp . getReg ( ) , TRI ) << <STR_LIT> ) ; FixupLocsForFn . emplace_back ( NewLoc ) ; continue ; } assert ( UnsafeCount == <NUM_LIT> && ! IsLiveIn && <STR_LIT> <STR_LIT> ) ; SmallPtrSetIterator < MachineInstr * > It = llvm :: find_if ( AllDefs , IsUnsafe ) ; assert ( It != AllDefs . end ( ) && <STR_LIT> ) ; MachineInstr * DefMI = *


<s> continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( MOp . getReg ( ) , TRI ) << <STR_LIT> ) ; NewLoc . Block = & MF . front ( ) ; NewLoc . InsertionPt = & * NewLoc . Block -> begin ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * NewLoc . InsertionPt ) ; FixupLocsForFn . emplace_back ( NewLoc ) ; continue ; } if ( IsLiveIn || UnsafeCount > <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << printReg ( MOp . getReg ( ) , TRI ) << <STR_LIT> ) ; FixupLocsForFn . emplace_back ( NewLoc ) ; continue ; } assert ( UnsafeCount == <NUM_LIT> && ! IsLiveIn && <STR_LIT> <STR_LIT> ) ; SmallPtrSetIterator < MachineInstr * > It = llvm :: find_if ( AllDefs , IsUnsafe ) ; assert ( It != AllDefs . end ( ) && <STR_LIT> ) ; MachineInstr * DefMI = * It ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( MOp . getReg ( ) , TRI ) << <STR_LIT> << * DefMI ) ; MachineBasicBlock :: iterator DefIt = DefMI ; ++ DefIt ; if ( DefIt != DefMI -> getParent ( ) -> end ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * DefMI << <STR_LIT> << * DefIt ) ; NewLoc . Block = DefIt -> getParent ( ) ; NewLoc . InsertionPt = & * DefIt ; } FixupLocsForFn . emplace_back ( NewLoc )


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < ReachingDefAnalysis > ( ) ; AU . setPreservesCFG ( )


<s> assert ( OperandToFixup -> isReg ( ) && <STR_LIT> ) ; Register RegToFixup = OperandToFixup -> getReg ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( RegToFixup , TRI ) << <STR_LIT> << * FixupLoc . InsertionPt ) ; unsigned Renamable = OperandToFixup -> isRenamable ( ) ? RegState :: Renamable : <NUM_LIT> ; BuildMI ( * FixupLoc . Block , FixupLoc . InsertionPt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( RegToFixup , RegState :: Define | Renamable ) . addReg ( RegToFixup

, RegState :: Kill | Renamable ) . addReg ( RegToFixup , RegState :: Kill | Renamable ) . addImm ( ( uint64_t ) <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> bool <ISA_LIT>FixCortexA57AES1742098 :: isFirstAESPairInstr ( MachineInstr & MI ) { unsigned Opc = MI . getOpcode


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; auto & STI = F . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! STI . hasAES ( ) || ! STI . fixCortexA57AES1742098 ( ) ) return false ; const <ISA_LIT>BaseRegisterInfo * TRI = STI . getRegisterInfo ( ) ; const <ISA_LIT>BaseInstrInfo * TII = STI . getInstrInfo ( ) ; auto & RDA = getAnalysis < ReachingDefAnalysis > ( ) ; SmallVector < AESFixupLocation > FixupLocsForFn


<s> bool Changed = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FixupLocsForFn . size ( ) << <STR_LIT> ) ; for ( AESFixupLocation & FixupLoc : FixupLocsForFn ) { insertAESFixup ( FixupLoc , TII , TRI ) ; Changed |= true ; } return


<s> bool <ISA_LIT>FrameInfo :: canSimplifyCallFramePseudos ( const MachineFunction & MF ) const { return hasReservedCallFrame ( MF ) || MF . getFrameInfo ( )


<s> return hasReservedCallFrame ( MF ) || MF . getFrameInfo (


<s> NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ; } } else if ( NumBytes ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; if ( AFI -> getDPRCalleeSavedAreaSize ( ) ) MBBI ++ ; if ( AFI -> getGPRCalleeSavedArea2Size ( ) ) MBBI ++ ; if ( AFI -> getGPRCalleeSavedArea1Size ( ) ) MBBI ++ ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = prior ( MBB . end ( ) ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { unsigned TCOpcode = ( RetOpcode == <STR_LIT> ) ? ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) : ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( TCOpcode ) ) ; if ( JumpTarget . isGlobal ( ) ) MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset

( ) , JumpTarget . getTargetFlags ( ) ) ;


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; SmallVector < unsigned , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; bool DeleteRet = false ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . isTargetDarwin ( ) ) ) continue ; if ( Reg == <STR_LIT> && ! isVarArg ) { Reg = <STR_LIT> ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; DeleteRet = true ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg


<s> if ( ! ( Func ) ( Reg , STI . isTargetDarwin ( ) ) ) continue ; if ( Reg == <STR_LIT> && ! isVarArg ) { Reg = <STR_LIT> ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; DeleteRet = true ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) MI ->


<s> MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const <ISA_LIT>BaseRegisterInfo * RegInfo = static_cast < const <ISA_LIT>BaseRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; bool is<ISA_LIT> = ! AFI -> isThumbFunction ( ) ; unsigned VARegSaveSize = AFI -> getVarArgsRegSaveSize ( ) ; unsigned NumBytes = MFI -> getStackSize ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; unsigned GPRCS1Size = <NUM_LIT> , GPRCS2Size = <NUM_LIT> , DPRCSSize = <NUM_LIT> ; int FramePtrSpillFI = <NUM_LIT> ; if ( VARegSaveSize ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - VARegSaveSize ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - NumBytes ) ; return ; } for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; int FI = CSI [ i ] . getFrameIdx ( ) ; switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetDarwin ( ) ) { AFI -> addGPRCalleeSavedArea2Frame ( FI ) ; GPRCS2Size += <NUM_LIT> ; } else { AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; } break ; default : AFI -> addDPRCalleeSavedAreaFrame ( FI ) ; DPRCSSize += <NUM_LIT> ; } } if ( GPRCS1Size > <NUM_LIT> ) MBBI ++ ; bool HasFP = hasFP ( MF ) ; if ( HasFP ) { unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( ADDriOpc ) , FramePtr ) . addFrameIndex ( FramePtrSpillFI ) . addImm ( <NUM_LIT> ) ; AddDefaultCC ( AddDefaultPred ( MIB ) ) ; } if ( GPRCS2Size > <NUM_LIT> ) MBBI ++ ; unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset


<s> void <ISA_LIT>FrameInfo :: emitPushInst ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , unsigned StmOpc , unsigned StrOpc , bool NoGap , bool ( * Func ) ( unsigned , bool ) ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; SmallVector < std :: pair < unsigned , bool > , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . isTargetDarwin ( ) ) ) continue ; bool isKill = true ; if ( Reg == <STR_LIT> ) { if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; } if ( isKill ) MBB . addLiveIn ( Reg ) ; if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( std :: make_pair ( Reg , isKill ) ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || StrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( StmOpc ) , <STR_LIT> )


<s> if ( Reg == <STR_LIT> ) { if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; } if ( isKill ) MBB . addLiveIn ( Reg ) ; if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( std :: make_pair ( Reg , isKill ) ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || StrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( StmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] . first , getKillRegState ( Regs [ i ] . second ) ) ; } else if ( Regs . size ( ) == <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( StrOpc ) , <STR_LIT> ) . addReg ( Regs [ <NUM_LIT> ] . first , getKillRegState ( Regs [ <NUM_LIT> ] . second ) ) . addReg ( <STR_LIT> ) ; if ( StrOpc == <STR_LIT> ) { MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ) ; } else MIB . addImm ( - <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; } Regs . clear (


<s> switch ( I -> getDesc ( ) . TSFlags & <STR_LIT> ) { case <STR_LIT> : case <STR_LIT> : Limit = std :: min ( Limit , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : Limit = std :: min ( Limit , ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case <STR_LIT> : if ( TFI -> hasFP ( MF ) && AFI -> hasStackFrame ( ) ) Limit = std :: min ( Limit , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT>


<s> int <ISA_LIT>FrameInfo :: getFrameIndexOffset ( const MachineFunction & MF , int FI ) const { unsigned FrameReg ; return getFrameIndexReference ( MF , FI


<s> int <ISA_LIT>FrameInfo :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { return ResolveFrameIndexReference ( MF , FI , FrameReg ,


<s> bool <ISA_LIT>FrameInfo :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; if ( STI . isTargetDarwin ( ) ) return true ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( ( DisableFramePointerElim ( MF ) && MFI -> hasCalls ( ) ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI ->


<s> const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; if ( STI . isTargetDarwin ( ) ) return


<s> unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) / <NUM_LIT> )


<s> for ( int i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if (

! isCalleeSavedRegister ( MI -> getOperand ( i ) . getReg ( ) , CSRegs ) ) return false ;


<s> if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > <NUM_LIT> ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned PopOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; unsigned LdrOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; unsigned FltOpc = <STR_LIT> ; emitPopInst ( MBB , MI , CSI , FltOpc , <NUM_LIT> , isVarArg , true , & is<ISA_LIT>Area3Register ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc

, isVarArg , false , & is<ISA_LIT>Area2Register ) ;


<s> unsigned FltOpc = <STR_LIT> ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & is<ISA_LIT>Area1Register ) ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & is<ISA_LIT>Area2Register ) ; emitPushInst ( MBB , MI , CSI , FltOpc , <NUM_LIT> , true , & is<ISA_LIT>Area3Register ) ; return true


<s> auto Info = std :: find_if ( Insts . begin ( ) , Insts . end ( ) , [ & ] ( InstInfo & Info ) { return Info . I == I ; } ) ; assert ( Info != Insts . end ( ) && <STR_LIT> ) ; Info -> SPAdjust += ExtraBytes


<s> void addInst ( MachineBasicBlock :: iterator I , unsigned SPAdjust , bool BeforeFPSet = false ) { InstInfo Info = { I , SPAdjust ,


<s> bool Carry = ( Value & <NUM_LIT> ) ; Value = ( ( Value & <NUM_LIT> ) >> <NUM_LIT> ) + Carry ; if ( Value & <NUM_LIT> ) Value = Value &


<s> if ( ! SpillAlignedNEONRegs ) return ; if ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: Naked ) ) return ; if ( ! static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) . hasNEON ( ) ) return ; if ( MF . getSubtarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) >= <NUM_LIT> ) return ; if ( ! static_cast < const <ISA_LIT>BaseRegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) -> canRealignStack ( MF ) ) return ; unsigned NumSpills = <NUM_LIT> ; for ( ; NumSpills < <NUM_LIT> ; ++ NumSpills ) if ( ! SavedRegs . test ( <STR_LIT> + NumSpills ) ) break ; if ( NumSpills < <NUM_LIT>


<s> unsigned R4BaseReg = NextReg ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , SupReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } if ( NumAlignedDPRCS2Regs ) AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> * ( NextReg - R4BaseReg ) ) ) ; std :: prev ( MI ) ->


<s> assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; if ( ! AFI -> isThumbFunction ( ) ) { if ( CanUseBFC ) { AddDefaultPred ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( ~ AlignMask ) ) ; } else if ( AlignMask <= <NUM_LIT> ) { AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( AlignMask ) ) ) ; } else { assert ( ! MustBeSingleInstruction && <STR_LIT> <STR_LIT> <STR_LIT> ) ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <STR_LIT> ( <STR_LIT> , NrBitsToZero ) ) ) ) ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <STR_LIT> ( <STR_LIT> , NrBitsToZero ) ) ) ) ; } } else


<s> void emitDefCFAOffsets ( MachineModuleInfo & MMI , MachineBasicBlock & MBB , DebugLoc dl , const <ISA_LIT>BaseInstrInfo & TII , bool HasFP ) { unsigned CFAOffset = <NUM_LIT> ; for ( auto & Info : Insts ) { if ( HasFP && ! Info . BeforeFPSet ) return ; CFAOffset -= Info .


<s> int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( MF . getFunction ( ) -> getCallingConv ( ) == CallingConv :: GHC ) return ; MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes - ArgRegsSaveSize != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes - ArgRegsSaveSize ) ; } else { const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; if ( MBBI != MBB . begin ( ) ) { do { -- MBBI ; } while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , TII , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( ArgRegsSaveSize + AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedGapSize ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( )


<s> if ( Reg == <STR_LIT> ) { if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; } if ( isKill ) MBB . addLiveIn ( Reg ) ; if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( std :: make_pair ( Reg , isKill ) ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || StrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( StmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . setMIFlags ( MIFlags ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] . first , getKillRegState ( Regs [ i ] . second ) ) ; } else if ( Regs . size ( ) == <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( StrOpc ) , <STR_LIT> ) . addReg ( Regs [ <NUM_LIT> ] . first , getKillRegState ( Regs [ <NUM_LIT> ] . second ) ) . addReg ( <STR_LIT> ) . setMIFlags ( MIFlags ) . addImm ( - <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; } Regs . clear


<s> if ( isKill ) MBB . addLiveIn ( Reg ) ; if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( std :: make_pair ( Reg , isKill ) ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || StrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( StmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . setMIFlags ( MIFlags ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] . first , getKillRegState ( Regs [ i ] . second ) ) ; } else if ( Regs . size ( ) == <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( StrOpc ) , <STR_LIT> ) . addReg ( Regs [ <NUM_LIT> ] . first , getKillRegState ( Regs [ <NUM_LIT> ] . second ) ) . addReg ( <STR_LIT> ) . setMIFlags (


<s> static unsigned GetFunctionSizeInBytes ( const MachineFunction & MF , const <ISA_LIT>BaseInstrInfo & TII ) { unsigned FnSize = <NUM_LIT> ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) FnSize += TII . GetInstSizeInBytes (


<s> for ( auto & MBB : MF ) { for ( auto & MI : MBB ) FnSize += TII . GetInstSizeInBytes ( & MI ) ; } return


<s> return ( ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI -> hasCalls ( ) ) || RegInfo

-> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ;


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( STI . isTargetIOS ( ) || STI . isTargetWatchOS ( ) ) return true ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI -> hasCalls ( ) ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects (


<s> } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && isCalleeSavedRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , CSRegs ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return true ; return false


<s> return TargetFrameLowering :: noFramePointerElim ( MF ) || MF . getSubtarget < <ISA_LIT>Subtarget > (


<s> bool isFixed = MFI -> isFixedObjectIndex ( FI ) ; FrameReg = <STR_LIT> ; Offset += SPAdj ; bool hasMovingSP = ! hasReservedCallFrame ( MF ) ; if ( RegInfo -> needsStackRealignment ( MF ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; if ( isFixed ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; Offset = FPOffset ; } else if ( hasMovingSP ) { assert ( RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; FrameReg = RegInfo -> getBaseRegister ( ) ; } return Offset ; } if ( hasFP ( MF ) && AFI -> hasStackFrame ( ) ) { if ( isFixed || ( hasMovingSP && ! RegInfo -> hasBasePointer ( MF ) ) ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return


<s> static bool WindowsRequiresStackProbe ( const MachineFunction & MF , size_t StackSizeInBytes ) { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Function * F = MF . getFunction ( ) ; unsigned StackProbeSize = ( MFI -> getStackProtectorIndex ( ) > <NUM_LIT> ) ?


<s> return hasReservedCallFrame ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects (


<s> return hasReservedCallFrame ( MF ) || MF . getFrameInfo ( )


<s> unsigned Opc = isThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addFrameIndex ( D8SpillFI ) . addImm ( <NUM_LIT> ) ) ) ; unsigned NextReg = <STR_LIT> ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } unsigned R4BaseReg = NextReg ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg +=


<s> unsigned Opc = isThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> * NumAlignedDPRCS2Regs ) ) ) ; Opc = isThumb ? <STR_LIT> : <STR_LIT> ; unsigned MaxAlign = MF . getFrameInfo ( ) -> getMaxAlignment ( ) ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( MaxAlign - <NUM_LIT> ) ) ) ; Opc = isThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MIB = AddDefaultPred ( MIB ) ; if ( ! isThumb ) AddDefaultCC ( MIB ) ; unsigned NextReg = <STR_LIT> ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } unsigned R4BaseReg = NextReg ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT>


<s> if ( AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getGPRCalleeSavedArea2Size ( ) ) MBBI ++ ; if ( AFI -> getGPRCalleeSavedArea1Size ( ) ) MBBI ++ ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; if ( RetOpcode == <STR_LIT> ) { unsigned TCOpcode = STI . isThumb ( ) ? ( STI . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( TCOpcode ) ) ; if ( JumpTarget . isGlobal ( ) ) MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) , JumpTarget . getTargetFlags ( ) ) ; else { assert ( JumpTarget . isSymbol ( ) ) ; MIB . addExternalSymbol ( JumpTarget . getSymbolName ( ) , JumpTarget . getTargetFlags ( ) ) ; } if ( STI . isThumb ( ) ) MIB . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; } else if ( RetOpcode == <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } MachineInstr * NewMI = std :: prev ( MBBI ) ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i !=

e ; ++ i ) NewMI -> addOperand ( MBBI -> getOperand ( i ) ) ;


<s> bool isTailCall = ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) ; bool isInterrupt = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; SmallVector < unsigned , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; bool DeleteRet = false ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . isTargetMachO ( ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; if ( Reg == <STR_LIT> && ! isTailCall && ! isVarArg && ! isInterrupt && STI . hasV5TOps ( ) ) { Reg = <STR_LIT> ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; DeleteRet = true ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg =


<s> while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . isTargetMachO ( ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; bool isKill = true ; if ( Reg == <STR_LIT> ) { if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; } if ( isKill ) MBB . addLiveIn ( Reg ) ; if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( std :: make_pair ( Reg , isKill ) ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || StrOpc == <NUM_LIT>


<s> void <ISA_LIT>FrameLowering :: emitPushInst ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , unsigned StmOpc , unsigned StrOpc , bool NoGap , bool ( * Func ) ( unsigned , bool ) , unsigned NumAlignedDPRCS2Regs , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; SmallVector < std :: pair < unsigned , bool > , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . isTargetMachO ( ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; bool isKill = true ; if ( Reg == <STR_LIT> ) { if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg


<s> static void emitRegPlusImmediate ( bool is<ISA_LIT> , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , const <ISA_LIT>BaseInstrInfo & TII , unsigned DestReg , unsigned SrcReg , int NumBytes , unsigned MIFlags = MachineInstr :: NoFlags , <STR_LIT> Pred = <STR_LIT> , unsigned PredReg = <NUM_LIT> ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , DestReg , SrcReg , NumBytes , Pred , PredReg , TII , MIFlags ) ; else emitT2RegPlusImmediate ( MBB , MBBI , dl , DestReg , SrcReg , NumBytes , Pred , PredReg , TII ,


<s> static void emitSPUpdate ( bool is<ISA_LIT> , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , const <ISA_LIT>BaseInstrInfo & TII , int NumBytes , unsigned MIFlags = MachineInstr

:: NoFlags , <STR_LIT> Pred = <STR_LIT> , unsigned PredReg = <NUM_LIT> ) {


<s> bool enableShrinkWrapping ( const MachineFunction & MF ) const override { return


<s> for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) { for ( MachineBasicBlock :: iterator I = BB -> begin ( ) , E = BB -> end ( ) ; I != E ; ++ I ) { for ( unsigned i = <NUM_LIT> , e = I -> getNumOperands ( ) ; i != e ; ++ i ) { if ( ! I -> getOperand ( i ) . isFI ( ) ) continue ; if ( I -> getOpcode ( ) == <STR_LIT> ) { Limit = std :: min ( Limit , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; break ; } switch ( I -> getDesc ( ) . TSFlags & <STR_LIT> ) { case <STR_LIT> : case <STR_LIT> : Limit = std :: min ( Limit , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : Limit = std :: min ( Limit , ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case <STR_LIT> : if ( TFI -> hasFP ( MF ) && AFI -> hasStackFrame ( ) ) Limit = std :: min ( Limit , (


<s> unsigned FrameReg ; return getFrameIndexReference ( MF , FI , FrameReg


<s> return ResolveFrameIndexReference ( MF , FI , FrameReg


<s> if ( CFSize >= ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) / <NUM_LIT> ) return false ; return ! MF . getFrameInfo ( ) -> hasVarSizedObjects (


<s> if ( isPopOpcode ( MI -> getOpcode ( ) ) ) { for ( int i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( ! isCalleeSavedRegister ( MI -> getOperand ( i ) . getReg ( ) , CSRegs ) ) return false ; return true


<s> } else if ( hasMovingSP ) { assert ( RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; FrameReg = RegInfo -> getBaseRegister ( ) ; } return Offset ; } if ( hasFP ( MF ) && AFI -> hasStackFrame ( ) ) { if ( isFixed || ( hasMovingSP && ! RegInfo -> hasBasePointer ( MF ) ) ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } else if ( hasMovingSP ) { assert ( RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; if ( AFI -> isThumb2Function ( ) ) { if ( FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } } else if ( AFI -> isThumb2Function ( ) ) { if ( Offset >= <NUM_LIT> && ( Offset & <NUM_LIT> ) == <NUM_LIT> && Offset <= <NUM_LIT> ) return Offset ; if ( FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset


<s> if ( hasFP ( MF ) && AFI -> hasStackFrame ( ) ) { if ( isFixed || ( hasMovingSP && ! RegInfo -> hasBasePointer ( MF ) ) ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } else if ( hasMovingSP ) { assert ( RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; if ( AFI -> isThumb2Function ( ) ) { if ( FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } } else if ( AFI -> isThumb2Function ( ) ) { if ( Offset >= <NUM_LIT> && ( Offset & <NUM_LIT> ) == <NUM_LIT> && Offset <= <NUM_LIT> ) return Offset ; if ( FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } else if ( Offset > ( FPOffset < <NUM_LIT> ? - FPOffset : FPOffset ) ) { FrameReg = RegInfo -> getFrameRegister


<s> emitPopInst ( MBB , MI , CSI , FltOpc , <NUM_LIT> , isVarArg , true , & is<ISA_LIT>Area3Register , NumAlignedDPRCS2Regs ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc , isVarArg , false , & is<ISA_LIT>Area2Register , <NUM_LIT> ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc , isVarArg , false , & is<ISA_LIT>Area1Register , <NUM_LIT> ) ; return


<s> assert ( MI -> getOpcode ( ) == <STR_LIT> ) ; int count = <NUM_LIT> ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) count += <NUM_LIT> ; return


<s> static MachineBasicBlock :: iterator skipAlignedDPRCS2Spills ( MachineBasicBlock :: iterator MI , unsigned NumAlignedDPRCS2Regs ) { ++ MI ; ++ MI ; ++ MI ; assert ( MI -> mayStore ( ) && <STR_LIT> ) ; switch ( NumAlignedDPRCS2Regs ) { case <NUM_LIT> : ++ MI ; assert ( MI -> mayStore ( ) && <STR_LIT> ) ; default : ++


<s> emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & is<ISA_LIT>Area2Register , <NUM_LIT> , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , FltOpc , <NUM_LIT> , true , & is<ISA_LIT>Area3Register , NumAlignedDPRCS2Regs , MachineInstr :: FrameSetup ) ; if ( NumAlignedDPRCS2Regs ) emitAlignedDPRCS2Spills ( MBB , MI ,


<s> void addExtraBytes ( const MachineBasicBlock :: iterator I , unsigned ExtraBytes ) { auto Info = llvm :: find_if ( Insts , [ & ] ( InstInfo & Info ) { return Info


<s> bool <ISA_LIT>FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { if ( STI . hasV8_1MMainlineOps ( ) && MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isCmseNSEntryFunction ( ) ) { CSI . emplace_back ( <STR_LIT>


<s> bool <ISA_LIT>FrameLowering :: canSimplifyCallFramePseudos ( const MachineFunction & MF )


<s> return hasReservedCallFrame ( MF ) || MF . getFrameInfo


<s> if ( ! static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) . hasNEON ( ) ) return ; if ( MF . getSubtarget ( ) . getFrameLowering ( ) -> getStackAlign ( ) >= Align ( <NUM_LIT> ) ) return ; if ( ! static_cast < const <ISA_LIT>BaseRegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) -> canRealignStack ( MF ) ) return ; unsigned NumSpills =


<s> if ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: Naked ) ) return ; if ( ! static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) . hasNEON ( ) ) return ; if ( MF . getSubtarget ( ) . getFrameLowering ( ) -> getStackAlign ( ) >= Align ( <NUM_LIT> ) ) return ; if ( ! static_cast < const <ISA_LIT>BaseRegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) -> canRealignStack ( MF ) ) return ; unsigned NumSpills = <NUM_LIT> ; for ( ; NumSpills < <NUM_LIT> ; ++ NumSpills ) if ( ! SavedRegs . test ( <STR_LIT> + NumSpills ) ) break ; if ( NumSpills < <NUM_LIT> )


<s> BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <STR_LIT> ( <STR_LIT> , NrBitsToZero ) ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <STR_LIT> ( <STR_LIT> , NrBitsToZero ) ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; } } else { assert ( CanUseBFC ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState

:: Kill ) . addImm ( ~ AlignMask ) . add ( predOps ( <STR_LIT> ) ) ;


<s> void emitDefCFAOffsets ( MachineBasicBlock & MBB , const DebugLoc & dl , const <ISA_LIT>BaseInstrInfo & TII , bool HasFP ) { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CFAOffset = <NUM_LIT> ; for ( auto & Info : Insts ) { if ( HasFP && ! Info . BeforeFPSet ) return ; CFAOffset += Info . SPAdjust ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , CFAOffset ) ) ; BuildMI ( MBB , std :: next ( Info . I ) , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex

) . setMIFlags ( MachineInstr :: FrameSetup ) ;


<s> LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; Info . setRestored ( false ) ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; llvm :: sort ( Regs , [ & ] ( unsigned LHS , unsigned RHS ) { return TRI . getEncodingValue ( LHS ) < TRI . getEncodingValue ( RHS ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) . setMIFlags ( MachineInstr :: FrameDestroy ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) { if ( MI != MBB . end ( ) ) { MIB . copyImplicitOps ( * MI ) ; MI -> eraseFromParent ( ) ; } } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT> ] = <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) , Regs [ <NUM_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . setMIFlags ( MachineInstr :: FrameDestroy ) ; if ( LdrOpc == <STR_LIT> || LdrOpc


<s> unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; bool DeleteRet = false ; for ( ; i != <NUM_LIT> ; -- i ) { CalleeSavedInfo & Info = CSI [ i - <NUM_LIT> ] ; unsigned Reg = Info . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . splitFramePushPop ( MF ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; if ( Reg == <STR_LIT> && ! isTailCall && ! isVarArg && ! isInterrupt && ! isCmseEntry && ! isTrap && AFI -> getArgumentStackToRestore ( ) == <NUM_LIT> && STI . hasV5TOps ( ) && MBB . succ_empty ( ) && ! hasPAC ) { Reg = <STR_LIT> ; DeleteRet = true ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; Info . setRestored ( false ) ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; llvm :: sort ( Regs , [ & ] ( unsigned LHS , unsigned RHS ) { return TRI . getEncodingValue ( LHS ) < TRI . getEncodingValue ( RHS ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) . setMIFlags ( MachineInstr :: FrameDestroy ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) { if ( MI != MBB . end ( ) ) { MIB . copyImplicitOps ( * MI ) ; MI -> eraseFromParent ( ) ; } } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT> ] = <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) , Regs [ <NUM_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . setMIFlags ( MachineInstr :: FrameDestroy ) ; if ( LdrOpc == <STR_LIT> || LdrOpc == <STR_LIT> ) { MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ) ; } else MIB . addImm (


<s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; DebugLoc DL ; using RegAndKill = std :: pair < unsigned , bool > ; SmallVector < RegAndKill , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . splitFramePushPop ( MF ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool isLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! isLiveIn && ! MRI . isReserved ( Reg ) ) MBB . addLiveIn ( Reg ) ; if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( std :: make_pair ( Reg , ! isLiveIn ) ) ; } if ( Regs . empty ( ) ) continue ; llvm :: sort ( Regs , [ & ] ( const RegAndKill


<s> static void emitRegPlusImmediate ( bool is<ISA_LIT> , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const DebugLoc & dl , const <ISA_LIT>BaseInstrInfo & TII , unsigned DestReg , unsigned SrcReg , int NumBytes , unsigned MIFlags = MachineInstr :: NoFlags , <STR_LIT> Pred = <STR_LIT> , unsigned PredReg = <NUM_LIT> ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , DestReg , SrcReg , NumBytes , Pred , PredReg , TII , MIFlags ) ; else emitT2RegPlusImmediate ( MBB , MBBI , dl , DestReg , SrcReg , NumBytes


<s> bool <ISA_LIT>FrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { if ( STI . hasV8_1MMainlineOps ( ) && MF . getInfo < <ISA_LIT>FunctionInfo >

( ) -> isCmseNSEntryFunction ( ) ) return false ;


<s> } if ( MF . getJumpTableInfo ( ) ) for ( auto & Table : MF . getJumpTableInfo ( ) -> getJumpTables

( ) ) FnSize += Table . MBBs . size ( ) * <NUM_LIT> ;


<s> bool IsTailCallReturn = false ; if ( MBB . end ( ) != MBBI ) { unsigned RetOpcode = MBBI -> getOpcode ( ) ; IsTailCallReturn = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; } <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo


<s> static const SpillSlot FixedSpillOffsets [ ] = { { <STR_LIT> , -


<s> StackOffset <ISA_LIT>FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { return StackOffset :: getFixed ( ResolveFrameIndexReference ( MF , FI , FrameReg ,


<s> StackOffset <ISA_LIT>FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI


<s> if ( CFSize >= ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) / <NUM_LIT> )


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned CFSize = MFI . getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) / <NUM_LIT> ) return false ; return ! MFI . hasVarSizedObjects


<s> bool <ISA_LIT>FrameLowering :: keepFramePointer ( const MachineFunction & MF ) const { return MF . getSubtarget < <ISA_LIT>Subtarget > (


<s> return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . useFastISel (