<s> if ( ReduceLimitLdSt != - <NUM_LIT> && ( ( int ) NumLdSts >= ReduceLimitLdSt ) ) return false ; unsigned Scale = <NUM_LIT> ; bool HasImmOffset = false ; bool HasShift = false ; bool HasOffReg = true ; bool isLdStMul = false ; unsigned Opc = Entry . NarrowOpc1 ; unsigned OpNum = <NUM_LIT> ; uint8_t ImmLimit = Entry . Imm1Limit ; switch ( Entry . WideOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { Opc = Entry . NarrowOpc2 ; ImmLimit = Entry . Imm2Limit ; HasOffReg = false ; } Scale = <NUM_LIT> ; HasImmOffset = true ; HasOffReg = false ; break ; case <STR_LIT> : case <STR_LIT> : HasImmOffset = true ; HasOffReg = false ; break ; case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; HasImmOffset = true ; HasOffReg = false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : HasShift = true ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : { unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! is<ISA_LIT>LowRegister ( BaseReg ) || Entry . WideOpc != <STR_LIT> ) return false ; bool isOK = false ; for ( unsigned i = <NUM_LIT> ; i < MI -> getNumOperands ( ) ; ++ i ) { if ( MI -> getOperand ( i ) . getReg ( ) == BaseReg ) { isOK = true ; break ; } } if ( ! isOK ) return false ; OpNum = <NUM_LIT> ; isLdStMul = true ; break ; } case <STR_LIT> : { unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg != <STR_LIT> ) return false ; Opc = Entry . NarrowOpc2 ; OpNum = <NUM_LIT> ; isLdStMul = true ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { OpNum = <NUM_LIT> ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg == <STR_LIT> && ( Entry . WideOpc == <STR_LIT> || Entry . WideOpc == <STR_LIT> ) ) { Opc = Entry . NarrowOpc2 ; OpNum = <NUM_LIT> ; } else if ( ! is<ISA_LIT>LowRegister ( BaseReg ) || ( Entry . WideOpc != <STR_LIT> && Entry . WideOpc != <STR_LIT> ) ) { return false ; } isLdStMul = true ; break ; } } unsigned OffsetReg = <NUM_LIT> ; bool OffsetKill = false ; if ( HasShift ) { OffsetReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OffsetKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) return false ; } unsigned OffsetImm


<s> MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; goto ProcessNext ; } if ( Entry . NarrowOpc1 && ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ) { Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; } } ProcessNext : bool DefCPSR = false ; LiveCPSR = UpdateCPSRDef ( * MI , LiveCPSR , DefCPSR ) ; if ( MI -> getDesc ( ) . isCall ( ) ) { CPSRDef = <NUM_LIT> ; IsSelfLoop = false ; } else if ( DefCPSR ) { CPSRDef = MI ; IsSelfLoop =


<s> } goto ProcessNext ; } if ( Entry . NarrowOpc2 && ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ) { Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; goto ProcessNext ; } if ( Entry . NarrowOpc1 && ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ) { Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; } } ProcessNext : bool DefCPSR = false ; LiveCPSR = UpdateCPSRDef ( * MI , LiveCPSR , DefCPSR ) ; if ( MI -> getDesc ( ) . isCall ( ) ) { CPSRDef = <NUM_LIT> ; IsSelfLoop = false


<s> unsigned PredReg = <NUM_LIT> ; if ( getInstrPredicate ( MI , PredReg ) == <STR_LIT> ) { switch ( Opc ) { default : break ; case <STR_LIT> : { if ( ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ) return true ; } case <STR_LIT> : return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ; } } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ; break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ; break ; case <STR_LIT> : { static const ReduceEntry NarrowEntry = { <STR_LIT> , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( ReduceToNarrow ( MBB , MI , NarrowEntry , LiveCPSR , CPSRDef , IsSelfLoop ) ) return true ; return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR


<s> } else { unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc2 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , true , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( CPSRDef , MI , IsSelfLoop ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , dl , NewMCID ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef (


<s> if ( Entry . Imm2Limit ) { unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Limit = ( <NUM_LIT> << Entry . Imm2Limit ) - <NUM_LIT> ; if ( Imm > Limit ) return false ; } else { unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc2 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps -

<NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ;


<s> for ( unsigned i = <NUM_LIT> , e = Use -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = Use -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isUndef ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Defs . count ( Reg ) ) return


<s> Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; } goto ProcessNext ; } if ( Entry . NarrowOpc2 && ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , CPSRDef ) ) { Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; goto ProcessNext ; } if ( Entry . NarrowOpc1 && ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef ) ) { Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; } } ProcessNext : bool DefCPSR = false ; LiveCPSR = UpdateCPSRDef ( * MI , LiveCPSR , DefCPSR ) ; if ( MI -> getDesc ( ) . isCall ( ) ) CPSRDef


<s> if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg0 ) ) return false ; if ( Entry . Imm2Limit ) { unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Limit = ( <NUM_LIT> << Entry . Imm2Limit ) - <NUM_LIT> ; if ( Imm > Limit ) return false ; } else { unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc2 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , true , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( CPSRDef , MI ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , dl , NewMCID ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef (


<s> if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , true , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( CPSRDef , MI ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , dl , NewMCID ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef ( ) ) { if ( HasCC ) AddDefaultT1CC ( MIB , CCDead ) ; else AddNoT1CC ( MIB ) ; } unsigned NumOps = MCID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && MCID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( SkipPred && MCID . OpInfo [ i ] . isPredicate ( ) ) continue ; MIB . addOperand ( MI -> getOperand ( i ) ) ; } MIB . setMIFlags ( MI -> getFlags ( )


<s> bool CCDead = false ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , false , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( CPSRDef , MI ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , dl , NewMCID ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef ( ) ) { if ( HasCC ) AddDefaultT1CC ( MIB , CCDead ) ; else AddNoT1CC ( MIB ) ; } unsigned NumOps = MCID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && MCID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( ( MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> ) && i == <NUM_LIT> ) continue ; bool isPred = ( i < NumOps && MCID . OpInfo [ i ] . isPredicate ( ) ) ; if ( SkipPred && isPred ) continue ; const MachineOperand & MO = MI -> getOperand ( i


<s> } } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc1 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , false , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( CPSRDef , MI ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , dl , NewMCID ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef ( ) ) { if ( HasCC ) AddDefaultT1CC ( MIB , CCDead ) ; else AddNoT1CC ( MIB ) ; } unsigned NumOps = MCID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && MCID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( ( MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> ) && i == <NUM_LIT> ) continue ; bool isPred = ( i < NumOps && MCID . OpInfo [ i ]


<s> HasOffReg = false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : HasShift = true ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : { if ( ! MinimizeSize ) return false ; if ( ! MI -> hasOneMemOperand ( ) || ( * MI -> memoperands_begin ( ) ) -> getAlignment ( ) < <NUM_LIT> ) return false ; bool IsStore = Entry . WideOpc == <STR_LIT> ; Register Rt = MI -> getOperand ( IsStore ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; Register Rn = MI -> getOperand ( IsStore ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; unsigned Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned PredImm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; Register PredReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( is<ISA_LIT>LowRegister ( Rt ) ) ; assert ( is<ISA_LIT>LowRegister ( Rn ) ) ; if ( Offset != <NUM_LIT> ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; auto MIB = BuildMI ( MBB , MI , dl , TII -> get ( Entry . NarrowOpc1 ) ) . addReg ( Rn , RegState :: Define ) . addReg ( Rn ) . addImm ( PredImm ) . addReg ( PredReg ) . addReg ( Rt , IsStore ? <NUM_LIT> : RegState :: Define ) ; MIB . setMemRefs ( MI -> memoperands ( ) ) ; MIB . setMIFlags ( MI -> getFlags ( ) ) ; MI -> eraseFromBundle ( ) ; ++ NumLdSts ; return true ; } case <STR_LIT> : { Register BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( is<ISA_LIT>LowRegister ( BaseReg ) ) ; bool isOK = false ; for ( unsigned i = <NUM_LIT> ; i < MI -> getNumOperands ( ) ; ++ i ) { if ( MI -> getOperand ( i ) . getReg ( ) == BaseReg ) { isOK = true ; break ; } } if ( ! isOK ) return false ; OpNum = <NUM_LIT> ; isLdStMul = true ; break ; } case <STR_LIT> : if ( ! MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) return false ; break ; case <STR_LIT> : { Register BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg != <STR_LIT> ) return false ; Opc = Entry . NarrowOpc2 ; OpNum = <NUM_LIT>


<s> const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc1 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , false , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( MI , IsSelfLoop ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl , NewMCID ) ; if ( MCID . getOpcode ( ) == <STR_LIT> ) { MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; MIB -> getOperand ( <NUM_LIT> ) . setIsDef ( true ) ; MIB -> getOperand ( <NUM_LIT> ) . setIsDead ( true ) ; if ( NewMCID . hasOptionalDef ( ) ) MIB . add ( HasCC ? t1CondCodeOp ( CCDead ) : condCodeOp ( ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; } else { MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef ( ) ) MIB . add ( HasCC ? t1CondCodeOp ( CCDead ) : condCodeOp ( ) ) ; } unsigned NumOps = MCID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && MCID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( ( MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> ) && i == <NUM_LIT> ) continue ; bool isPred = ( i < NumOps && MCID .


<s> MinimizeSize = STI -> optForMinSize ( ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; bool Modified = false ; for ( ReversePostOrderTraversal < MachineFunction * > :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I


<s> if ( PredicateFtor && ! PredicateFtor ( MF . getFunction ( ) ) ) return false ; STI = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; if ( STI -> isThumb1Only ( ) || STI -> prefers32BitThumb ( ) ) return false ; TII = static_cast < const Thumb2InstrInfo * > ( STI ->


<s> TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; STI = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AttributeSet FnAttrs = MF . getFunction ( ) -> getAttributes ( ) ; OptimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; MinimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT (


<s> TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; STI = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AttributeSet FnAttrs = MF . getFunction ( ) -> getAttributes ( ) ; OptimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; MinimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; bool Modified = false


<s> Opc = Entry . NarrowOpc2 ; OpNum = <NUM_LIT> ; } else if ( ! is<ISA_LIT>LowRegister ( BaseReg ) || ( Entry . WideOpc != <STR_LIT> && Entry . WideOpc != <STR_LIT> ) ) { return false ; } isLdStMul = true ; break ; } } unsigned OffsetReg = <NUM_LIT> ; bool OffsetKill = false ; bool OffsetInternal = false ; if ( HasShift ) { OffsetReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OffsetKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; OffsetInternal = MI -> getOperand ( <NUM_LIT> ) . isInternalRead ( ) ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) return false ; } unsigned OffsetImm = <NUM_LIT> ; if ( HasImmOffset ) { OffsetImm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned MaxOffset = ( ( <NUM_LIT> << ImmLimit ) - <NUM_LIT> ) * Scale ; if ( ( OffsetImm & ( Scale - <NUM_LIT> ) ) || OffsetImm > MaxOffset ) return false ; } DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl , TII -> get ( Opc ) ) ; if ( Entry . WideOpc == <STR_LIT> ) MIB . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , RegState :: Define | RegState :: Dead ) ; if ( ! isLdStMul ) { MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( HasImmOffset ) MIB . addImm ( OffsetImm / Scale ) ; assert ( ( ! HasShift || OffsetReg ) && <STR_LIT> ) ; if ( HasOffReg ) MIB . addReg ( OffsetReg , getKillRegState ( OffsetKill ) | getInternalReadRegState ( OffsetInternal ) ) ; } for ( unsigned e = MI -> getNumOperands ( ) ; OpNum != e ; ++ OpNum ) MIB . add ( MI -> getOperand ( OpNum ) ) ; MIB . setMemRefs ( MI -> memoperands ( ) ) ; MIB . setMIFlags ( MI -> getFlags ( ) ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> << * MI << <STR_LIT> << * MIB ) ; MBB . erase_instr ( MI ) ; ++


<s> static bool HasImplicitCPSRDef ( const MCInstrDesc & MCID ) { for ( const uint16_t * Regs = MCID . getImplicitDefs ( ) ; * Regs ; ++ Regs ) if ( * Regs ==


<s> for ( unsigned i = <NUM_LIT> , e = array_lengthof ( ReduceTable ) ; i != e ; ++ i ) { unsigned FromOpc = ReduceTable [ i ] .


<s> case <NUM_LIT> : ShOp = <STR_LIT> ; return ( imm5 == <NUM_LIT> ? <NUM_LIT> : imm5 ) ; case <NUM_LIT> : ShOp = <STR_LIT> ; return ( imm5 == <NUM_LIT> ? <NUM_LIT> : imm5 ) ; case


<s> assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRt (


<s> static bool DisassembleThumb1AddSPi ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { assert ( Opcode == <STR_LIT> && <STR_LIT> ) ; const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRt ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; MI . addOperand ( MCOperand :: CreateImm (


<s> if ( ! OpInfo ) return false ; assert ( NumOps == <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && <STR_LIT> ) ; unsigned Imm11 = getT1Imm11 ( insn )


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps == <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && OpInfo [ <NUM_LIT> ] . isPredicate ( ) && OpInfo [ <NUM_LIT> ] . RegClass ==


<s> MI . addOperand ( MCOperand :: CreateReg ( B -> InITBlock ( ) ? <NUM_LIT> : <STR_LIT> ) ) ; ++ OpIdx ; } assert ( OpIdx < NumOps && <STR_LIT> ) ; if ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , UseRt ? getT1tRt ( insn ) : getT1tRn ( insn ) ) ) ) ; ++ OpIdx ; } if ( OpIdx == NumOps ) return true ; if ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRm ( insn ) ) ) ) ; } else


<s> if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && !

OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) ) && <STR_LIT> ) ;


<s> static bool DisassembleThumb1LdSt ( unsigned opA , MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { const TargetInstrDesc & TID = <ISA_LIT>Insts [ Opcode ] ; const TargetOperandInfo * OpInfo = TID . OpInfo ; unsigned & OpIdx = NumOpsAdded ; bool Imm5 = ( opA != <NUM_LIT> ) ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRn ( insn ) ) ) ) ; OpIdx = <NUM_LIT> ; assert ( OpIdx < NumOps && <STR_LIT> ) ; if ( OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) { MI . addOperand ( MCOperand :: CreateImm ( Imm5 ? getT1Imm5 ( insn ) : <NUM_LIT> ) ) ; ++ OpIdx


<s> ++ OpIdx ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( <STR_LIT> ) ) ) ; ++ OpIdx ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ) ) ; MI . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; OpIdx += <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( ( RegListBits >> i ) & <NUM_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , i ) ) ) ; ++ OpIdx ; } } return


<s> assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRt ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( <STR_LIT>


<s> MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( getT1Imm8 ( insn ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { unsigned Option = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | <NUM_LIT> << <NUM_LIT> ; MI . addOperand ( MCOperand :: CreateImm ( Option ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> || OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRd ( insn ) )


<s> unsigned & OpIdx = NumOpsAdded ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ) ) ; MI . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; OpIdx = <NUM_LIT> ; unsigned RegListBits = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << ( Opcode == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) | slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i <


<s> MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ) ) ; MI . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; OpIdx = <NUM_LIT> ; unsigned RegListBits = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << ( Opcode == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) | slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( ( RegListBits >> i ) & <NUM_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , i ) ) ) ; ++


<s> assert ( slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; if ( ( <STR_LIT> <= Opcode && Opcode <= <STR_LIT> ) || ( <STR_LIT> <= Opcode && Opcode <= <STR_LIT> ) ) { return DisassembleThumb2LdStEx ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { return DisassembleThumb2LdStDual ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { return DisassembleThumb2TB ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } } else if ( slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { return DisassembleThumb2DPSoReg ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } break ; case <NUM_LIT> : if ( op == <NUM_LIT> ) { if ( slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { return DisassembleThumb2DPModImm ( MI , Opcode , insn , NumOps , NumOpsAdded


<s> MI . addOperand ( MI . getOperand ( Idx ) ) ; } else { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; } ++ OpIdx ; } assert ( OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; ++ OpIdx ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) MI . addOperand ( MCOperand :: CreateImm ( getIImm3Imm8 ( insn ) ) ) ; else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) MI . addOperand ( MCOperand :: CreateImm ( getImm16 ( insn ) ) ) ; else if ( Opcode == <STR_LIT> ) MI . addOperand ( MCOperand :: CreateImm ( getBitfieldInvMask ( insn ) ) ) ; else { assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateImm ( getLsb ( insn ) ) ) ; if ( Opcode == <STR_LIT> ) { if ( getMsb ( insn ) < getLsb ( insn ) ) { DEBUG ( errs ( ) << <STR_LIT> ) ; return false


<s> unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; bool TwoReg = ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) ; bool NoDstReg = ( decodeRs ( insn ) == <NUM_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , NoDstReg ? decodeRn ( insn ) : decodeRs ( insn ) ) ) ) ; ++ OpIdx ; if ( TwoReg ) { assert ( ! NoDstReg && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; ++ OpIdx ; } assert ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; unsigned imm12 = getIImm3Imm8 ( insn ) ; MI . addOperand ( MCOperand :: CreateImm ( ThumbExpandImm ( imm12 ) ) ) ; ++


<s> ++ OpIdx ; if ( TwoReg ) { assert ( ! NoDstReg && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; ++ OpIdx ; } assert ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; unsigned imm12 = getIImm3Imm8 ( insn ) ; MI . addOperand ( MCOperand :: CreateImm ( ThumbExpandImm


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; ++ OpIdx ; if ( ThreeReg ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; ++ OpIdx ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; ++ OpIdx ; if ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx

] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) {


<s> ++ OpIdx ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; ++ OpIdx ; if ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) { MI . addOperand ( MCOperand :: CreateImm ( decodeRotate ( insn ) ) ) ; ++ OpIdx ; } return true


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> &&

OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && <STR_LIT> ) ;


<s> if ( Load && Rn == <NUM_LIT> ) return DisassembleThumb2Ldpci ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; const TargetInstrDesc & TID = <ISA_LIT>Insts [ Opcode ] ; const TargetOperandInfo * OpInfo = TID . OpInfo ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; bool ThreeReg = ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) ; bool TIED_TO = ThreeReg && TID . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> ; bool Imm12 = ! ThreeReg && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned R0 , R1 , R2 = <NUM_LIT> ; unsigned Rd = decodeRd ( insn ) ; int Imm = <NUM_LIT> ; if ( ! Load && TIED_TO ) { R0 = Rn ; R1 = Rd ; } else { R0 = Rd ; R1 = Rn ; } if ( ThreeReg ) { if ( TIED_TO ) { R2 = Rn ; Imm = decodeImm8 ( insn ) ; } else { R2 = decodeRm ( insn ) ; Imm = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; } } else { if ( Imm12 ) Imm = getImm12 ( insn ) ; else Imm = decodeImm8 ( insn ) ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R0 ) ) ) ; ++ OpIdx ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R1 ) ) ) ; ++ OpIdx ; if ( ThreeReg ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R2 ) ) ) ; ++ OpIdx ; } assert ( OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateImm ( Imm ) ) ; ++ OpIdx ; return


<s> if ( TIED_TO ) { R2 = Rn ; Imm = decodeImm8 ( insn ) ; } else { R2 = decodeRm ( insn ) ; Imm = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; } } else { if ( Imm12 ) Imm = getImm12 ( insn ) ; else Imm = decodeImm8 ( insn ) ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R0 ) ) ) ; ++ OpIdx ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R1 ) ) ) ; ++ OpIdx ; if ( ThreeReg ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R2 ) ) ) ; ++ OpIdx ; } assert ( OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateImm ( Imm ) ) ; ++ OpIdx


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; int Offset = getImm8 ( insn ) * <NUM_LIT> ; if ( getUBit ( insn ) == <NUM_LIT> ) Offset = - Offset ; MI . addOperand ( MCOperand :: CreateImm ( Offset ) ) ; NumOpsAdded = <NUM_LIT> ; return


<s> static bool DisassembleThumb2LdStMul ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { if ( Thumb2SRSOpcode ( Opcode ) ) return DisassembleThumb2SRS ( MI , Opcode , insn , NumOps , NumOpsAdded ) ; if ( Thumb2RFEOpcode ( Opcode ) ) return DisassembleThumb2RFE ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; unsigned Base = getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( Base ) ) ; ++ OpIdx ; } MI . addOperand ( MCOperand :: CreateReg ( Base ) ) ; ++


<s> if ( FourReg ) MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT>


<s> bool FourReg = NumOps > <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; if ( FourReg ) MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; NumOpsAdded = FourReg ? <NUM_LIT> : <NUM_LIT> ; return true


<s> uint32_t Val = <NUM_LIT> ; assert ( lsb <= msb && <STR_LIT> ) ; for ( uint32_t i = lsb ; i <= msb ; ++ i )


<s> assert ( lsb <= msb && <STR_LIT> ) ; for ( uint32_t i = lsb ; i <= msb ; ++ i ) Val |= ( <NUM_LIT> << i ) ; return ~


<s> static inline bool Thumb2PreloadOpcode ( unsigned Opcode ) { switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static inline bool Thumb2SaturateOpcode ( unsigned Opcode ) { switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( getT1Imm8 ( insn ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { unsigned Option = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | <NUM_LIT> << <NUM_LIT> ; MI . addOperand ( MCOperand :: CreateImm ( Option ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> || OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRd ( insn ) ) ) ) ; if ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRn ( insn ) ) ) ) ; } else


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { bool Negative = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned Imm12 = getImm12 ( insn ) ; Offset = Negative ? - <NUM_LIT> - Imm12 : <NUM_LIT> * Imm12 ; } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Imm8 = getImm8 ( insn ) ; Offset = - <NUM_LIT> - Imm8 ; } else Offset = decodeImm12 ( insn ) ; MI . addOperand ( MCOperand :: CreateImm ( Offset ) ) ; } ++ OpIdx ; if ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && !

OpInfo [ OpIdx ] . isOptionalDef ( ) ) {


<s> assert ( NumOps == <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && <STR_LIT> ) ; unsigned Imm11 = getT1Imm11 ( insn ) ; MI . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Imm11 << <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true


<s> const TargetOperandInfo * OpInfo = TID . OpInfo ; unsigned & OpIdx = NumOpsAdded ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRn ( insn ) ) ) ) ; OpIdx = <NUM_LIT> ; assert ( OpIdx < NumOps && <STR_LIT> ) ; if ( OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) { assert ( opA != <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateImm ( getT1Imm5 ( insn ) ) ) ; ++ OpIdx ; }


<s> if ( t2MiscCtrlInstr ( insn ) ) return true ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : break ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; NumOpsAdded = <NUM_LIT> ; return


<s> static bool DisassembleThumb2LdSt ( bool Load , MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { unsigned Rn = decodeRn ( insn ) ; if ( Thumb2PreloadOpcode ( Opcode ) ) return DisassembleThumb2PreLoad ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; if ( Load && Rn == <NUM_LIT> ) return DisassembleThumb2Ldpci ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; const TargetInstrDesc & TID = <ISA_LIT>Insts [ Opcode ] ; const TargetOperandInfo * OpInfo = TID . OpInfo ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; bool ThreeReg = ( OpInfo [ <NUM_LIT> ] . RegClass > <NUM_LIT> ) ; bool TIED_TO = ThreeReg && TID . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> ; bool Imm12 = ! ThreeReg && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned R0 , R1 , R2 = <NUM_LIT> ; unsigned Rd = decodeRd ( insn ) ; int Imm = <NUM_LIT> ; if ( ! Load && TIED_TO ) { R0 = Rn ; R1 = Rd ; } else { R0 = Rd ; R1 = Rn ; } if ( ThreeReg ) { if ( TIED_TO ) { R2 = Rn ; Imm = decodeImm8 ( insn ) ; } else


<s> unsigned RegClassBase = OpInfo [ <NUM_LIT> ] . RegClass ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassPair , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassPair , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassBase , decodeRn ( insn ) ) ) ) ; int Offset = getImm8 ( insn ) * <NUM_LIT> ; if ( getUBit ( insn ) == <NUM_LIT> ) Offset = - Offset ; MI . addOperand ( MCOperand :: CreateImm ( Offset ) ) ; NumOpsAdded =


<s> assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass > <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == OpInfo [ <NUM_LIT> ] . RegClass && OpInfo [ <NUM_LIT> ] . RegClass > <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && <STR_LIT> ) ; unsigned RegClassPair = OpInfo [ <NUM_LIT> ] . RegClass ; unsigned RegClassBase = OpInfo [ <NUM_LIT> ] . RegClass ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassPair , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassPair , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassBase , decodeRn ( insn ) ) ) ) ; int Offset = getImm8 (


<s> assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; NumOpsAdded = <NUM_LIT> ; unsigned Base = getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( Base


<s> ++ OpIdx ; if ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; } else { assert ( OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; int Offset = <NUM_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Imm8 = getImm8 ( insn ) ; Offset = - <NUM_LIT> * Imm8 ; } else Offset = decodeImm12 ( insn ) ; MI . addOperand ( MCOperand :: CreateImm (


<s> bool Imm12 = ! ThreeReg && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned R0 , R1 , R2 = <NUM_LIT> ; unsigned Rd = decodeRd ( insn ) ; int Imm = <NUM_LIT> ; if ( ! Load && TIED_TO ) { R0 = Rn ; R1 = Rd ; } else { R0 = Rd ; R1 = Rn ; } if ( ThreeReg ) { if ( TIED_TO ) { R2 = Rn ; Imm = decodeImm8 ( insn ) ; } else { R2 = decodeRm ( insn ) ; Imm = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; } } else { if ( Imm12 ) Imm = getImm12 ( insn ) ; else Imm = decodeImm8


<s> static bool DisassembleThumb2LdSt ( bool Load , MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { unsigned Rn = decodeRn ( insn ) ; if ( Thumb2PreloadOpcode ( Opcode ) ) return DisassembleThumb2PreLoad ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; const TargetInstrDesc & TID = <ISA_LIT>Insts [ Opcode ] ; const TargetOperandInfo * OpInfo = TID . OpInfo ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; bool ThreeReg = ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) ; bool TIED_TO = ThreeReg && TID . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> ; bool Imm12 = ! ThreeReg && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned R0 , R1 , R2 = <NUM_LIT> ; unsigned Rd = decodeRd ( insn ) ; int Imm = <NUM_LIT> ; if ( ! Load && TIED_TO ) { R0 = Rn ; R1 = Rd ; } else { R0 = Rd ; R1 = Rn ; } if ( ThreeReg ) { if ( TIED_TO ) { R2 = Rn ; Imm = decodeImm8 ( insn ) ; } else { R2 = decodeRm ( insn ) ; Imm = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; } } else { if ( Imm12 ) Imm = getImm12 ( insn ) ; else Imm = decodeImm8 ( insn ) ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R0 ) ) ) ; ++ OpIdx ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R1 ) ) ) ; ++ OpIdx ; if ( ThreeReg ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R2 ) ) ) ; ++ OpIdx ; } assert ( OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateImm ( Imm )


<s> return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ?


<s> return slice ( insn , <NUM_LIT> , <NUM_LIT> )


<s> static inline int decodeImm32_BL ( uint32_t insn ) { unsigned S = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; bool I1 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == S ; bool I2 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == S ; unsigned Imm25 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( S ) Imm25 |= <NUM_LIT> << <NUM_LIT> ; if ( I1 ) Imm25


<s> unsigned S = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; bool I1 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == S ; bool I2 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == S ; unsigned Imm25 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( S ) Imm25 |= <NUM_LIT> << <NUM_LIT> ; if ( I1 ) Imm25 |= <NUM_LIT> << <NUM_LIT> ; if ( I2 ) Imm25 |= <NUM_LIT> <<


<s> bool I2 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == S ; unsigned Imm25 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( S ) Imm25 |= <NUM_LIT> << <NUM_LIT> ; if ( I1 ) Imm25 |= <NUM_LIT> << <NUM_LIT> ; if ( I2 ) Imm25 |= <NUM_LIT> << <NUM_LIT> ; return SignExtend32 < <NUM_LIT>


<s> bool S = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; bool J1 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; bool J2 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Imm21 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( S ) Imm21 |= <NUM_LIT> <<


<s> unsigned Imm25 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( S ) Imm25 |= <NUM_LIT> << <NUM_LIT> ; if ( I1 ) Imm25 |= <NUM_LIT> << <NUM_LIT> ; if ( I2 ) Imm25 |= <NUM_LIT> << <NUM_LIT> ; return SignExtend32 < <NUM_LIT> > ( Imm25


<s> unsigned rotate = slice ( insn , <NUM_LIT> , <NUM_LIT>


<s> static inline unsigned decodeRotate ( uint32_t insn ) { unsigned rotate = slice ( insn , <NUM_LIT> ,


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRt ( insn )


<s> assert ( NumOps == <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && OpInfo [ <NUM_LIT> ] . isPredicate ( ) && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; unsigned Imm8 = getT1Imm8 ( insn ) ; MI . addOperand ( MCOperand :: CreateImm ( Opcode == <STR_LIT> ? SignExtend32 < <NUM_LIT> > ( Imm8 << <NUM_LIT> ) + <NUM_LIT> : ( int ) Imm8 ) ) ; NumOpsAdded = <NUM_LIT> ; return true


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRd ( insn ) ) ) ) ; ++ OpIdx ; if ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) { assert ( OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( B -> InITBlock ( ) ? <NUM_LIT> : <STR_LIT> ) ) ; ++ OpIdx ; } assert ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass == <STR_LIT>


<s> assert ( OpIdx < NumOps && <STR_LIT> ) ; if ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , UseRt ? getT1tRt ( insn ) : getT1tRn ( insn ) ) ) ) ; ++ OpIdx ; } if ( OpIdx == NumOps ) return true ; if ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRm ( insn ) ) ) ) ; } else { assert ( OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateImm ( UseRt ? getT1Imm8 ( insn ) : ( Imm3 ? getT1Imm3 ( insn ) : getT1Imm5 (


<s> return DisassembleThumb1LdStMul ( true , MI , Opcode , insn


<s> static bool DisassembleThumb1LdPC ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRt ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( getT1Imm8 ( insn ) << <NUM_LIT> ) ) ; NumOpsAdded = <NUM_LIT>


<s> assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRn ( insn ) ) ) ) ; OpIdx = <NUM_LIT> ; assert ( OpIdx < NumOps && <STR_LIT> ) ; if ( OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo


<s> static bool DisassembleThumb1LdStMul ( bool Ld , MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; unsigned tRt = getT1tRt ( insn ) ; NumOpsAdded = <NUM_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , tRt ) ) ) ; ++ NumOpsAdded ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , tRt ) ) ) ; ++ NumOpsAdded ; if ( B -> DoPredicateOperands ( MI , Opcode , insn , NumOps ) ) { NumOpsAdded +=


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef


<s> NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( getT1Imm8 ( insn ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> + slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> || OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRd ( insn ) ) ) ) ; if ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRn ( insn ) ) ) ) ; } else { assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateImm ( getT1Imm6 ( insn ) * <NUM_LIT>


<s> static bool DisassembleThumb1PushPop ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; unsigned & OpIdx = NumOpsAdded ; if ( B -> DoPredicateOperands ( MI , Opcode , insn , NumOps ) ) OpIdx += <NUM_LIT> ; else { DEBUG ( errs ( ) << <STR_LIT> ) ; return false ; } unsigned RegListBits = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << ( Opcode == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) | slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( ( RegListBits >> i ) & <NUM_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , i ) ) ) ; ++ OpIdx


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1Rm ( insn ) ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } const TargetInstrDesc & TID = <ISA_LIT>Insts [ Opcode ] ; const TargetOperandInfo * OpInfo = TID . OpInfo ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; unsigned RegClass = OpInfo [ OpIdx ] . RegClass ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClass , IsGPR ( RegClass ) ? getT1Rd ( insn ) : getT1tRd ( insn ) ) ) ) ; ++ OpIdx ; assert ( OpIdx < NumOps && <STR_LIT> ) ; int Idx ; if ( ( Idx = TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) ) != - <NUM_LIT> ) { MI . addOperand ( MI . getOperand ( Idx ) ) ; ++ OpIdx ; } assert ( OpIdx < NumOps


<s> OpIdx = <NUM_LIT> ; unsigned RdRegClassID = OpInfo [ <NUM_LIT> ] . RegClass ; assert ( NumOps >= <NUM_LIT> && ( RdRegClassID == <STR_LIT> || RdRegClassID == <STR_LIT> ) && <STR_LIT> ) ; unsigned RnRegClassID = OpInfo [ <NUM_LIT> ] . RegClass ; bool TwoReg = ( RnRegClassID == <STR_LIT> || RnRegClassID == <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RdRegClassID , decodeRs ( insn ) ) ) ) ; ++ OpIdx ; if ( TwoReg ) { assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; int Idx ; if ( ( Idx = TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) ) != - <NUM_LIT> ) { MI . addOperand ( MI . getOperand ( Idx ) ) ; } else { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RnRegClassID ,


<s> unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; unsigned RdRegClassID = OpInfo [ <NUM_LIT> ] . RegClass ; assert ( NumOps >= <NUM_LIT> && ( RdRegClassID == <STR_LIT> || RdRegClassID == <STR_LIT> ) && <STR_LIT> ) ; unsigned RnRegClassID = OpInfo [ <NUM_LIT> ] . RegClass ; bool TwoReg = ( RnRegClassID == <STR_LIT> || RnRegClassID == <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RdRegClassID , decodeRs ( insn ) ) ) ) ; ++ OpIdx ; if ( TwoReg ) { assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; int Idx ; if ( ( Idx = TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) ) != - <NUM_LIT> ) { MI . addOperand ( MI . getOperand ( Idx ) ) ; } else { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RnRegClassID , decodeRn ( insn ) ) ) ) ; } ++ OpIdx ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RnRegClassID , decodeRn ( insn ) ) ) ) ; ++ OpIdx ; } assert ( OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; ++ OpIdx ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) MI . addOperand ( MCOperand :: CreateImm ( getIImm3Imm8 ( insn


<s> MI . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; MI . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; MI . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } OpIdx = <NUM_LIT> ; assert ( NumOps >= <NUM_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> || OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) && ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> || OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) && <STR_LIT> ) ; bool ThreeReg = ( NumOps > <NUM_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> || OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) ) ; bool NoDstReg = ( decodeRs ( insn ) == <NUM_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , OpInfo [ <NUM_LIT> ] . RegClass , NoDstReg ? decodeRn ( insn ) : decodeRs ( insn ) ) ) ) ; ++ OpIdx ; if ( ThreeReg ) { int Idx ; if ( ( Idx = TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) ) != - <NUM_LIT> ) { MI . addOperand ( MI . getOperand ( Idx ) ) ; ++ OpIdx ; } else if ( ! NoDstReg ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , OpInfo [ <NUM_LIT> ] . RegClass , decodeRn ( insn ) ) ) ) ; ++ OpIdx ; } else { DEBUG ( errs ( ) << <STR_LIT> ) ; return false ; } } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , OpInfo [ OpIdx ] . RegClass , decodeRm ( insn ) ) ) ) ; ++ OpIdx ; if ( NumOps == OpIdx ) return true ; if ( OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) { if ( Thumb2ShiftOpcode ( Opcode ) ) MI . addOperand ( MCOperand :: CreateImm ( getShiftAmtBits ( insn ) ) ) ; else { unsigned bits2 = getShiftTypeBits (


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( decodeImm12 ( insn ) ) ) ; NumOpsAdded =


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( decodeImm12 ( insn ) ) ) ; NumOpsAdded =


<s> if ( Thumb2PreloadOpcode ( Opcode ) ) return DisassembleThumb2PreLoad ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; if ( Load && Rn == <NUM_LIT> ) return DisassembleThumb2Ldpci ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; const TargetInstrDesc & TID = <ISA_LIT>Insts [ Opcode ] ; const TargetOperandInfo * OpInfo = TID . OpInfo ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; bool ThreeReg = ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) ; bool TIED_TO = ThreeReg && TID . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> ; bool Imm12 = ! ThreeReg && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned R0 , R1 , R2 = <NUM_LIT> ; unsigned Rd = decodeRd ( insn ) ; int Imm = <NUM_LIT> ; if ( ! Load && TIED_TO ) { R0 = Rn ; R1 = Rd ; } else { R0 = Rd ; R1 = Rn ; } if ( ThreeReg ) { if ( TIED_TO ) { R2 = Rn ; Imm = decodeImm8 ( insn ) ; } else { R2 = decodeRm ( insn ) ; Imm = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; } } else { if ( Imm12 ) Imm = getImm12 ( insn ) ; else Imm = decodeImm8 ( insn ) ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R0 ) ) ) ; ++ OpIdx


<s> bool ThreeReg = ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) ; bool TIED_TO = ThreeReg && TID . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> ; bool Imm12 = ! ThreeReg && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned R0 , R1 , R2 = <NUM_LIT> ; unsigned Rd = decodeRd ( insn ) ; int Imm = <NUM_LIT> ; if ( ! Load && TIED_TO ) { R0 = Rn ; R1 = Rd ; } else { R0 = Rd ; R1 = Rn ; } if ( ThreeReg ) { if ( TIED_TO ) { R2 = Rn ; Imm = decodeImm8 ( insn ) ; } else { R2 = decodeRm ( insn ) ; Imm = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; } } else { if ( Imm12 ) Imm = getImm12 ( insn ) ; else Imm = decodeImm8 ( insn ) ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R0 ) ) ) ; ++ OpIdx ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R1 ) ) ) ; ++ OpIdx ; if ( ThreeReg


<s> assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; int Offset = getImm8 ( insn ) * <NUM_LIT> ; if ( getUBit ( insn ) == <NUM_LIT> ) Offset = - Offset ; MI . addOperand ( MCOperand :: CreateImm ( Offset ) ) ; NumOpsAdded = <NUM_LIT>


<s> assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; NumOpsAdded = <NUM_LIT> ; unsigned Base = getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg


<s> static bool DisassembleThumb2LdStMul ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { if ( Thumb2SRSOpcode ( Opcode ) ) return DisassembleThumb2SRS ( MI , Opcode , insn , NumOps , NumOpsAdded ) ; if ( Thumb2RFEOpcode ( Opcode ) ) return DisassembleThumb2RFE ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; NumOpsAdded = <NUM_LIT> ; unsigned Base = getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( Base ) ) ; ++


<s> if ( FourReg ) MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; if ( FourReg ) NumOpsAdded = <NUM_LIT> ; else NumOpsAdded =


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; if ( FourReg ) MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd


<s> assert ( OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; int Offset = <NUM_LIT> ; if ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { bool Negative = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned Imm12 = getImm12 ( insn ) ; Offset = Negative ? - <NUM_LIT> - Imm12 : <NUM_LIT> * Imm12 ; } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Imm8 = getImm8 ( insn ) ; Offset = - <NUM_LIT> - Imm8 ; } else Offset = decodeImm12 ( insn


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) )


<s> <STR_LIT> Opc = ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; unsigned ShAmt = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ShAmt == <NUM_LIT> ) { if ( Opc == <STR_LIT> ) ShAmt = <NUM_LIT> ; else Opc = <STR_LIT> ; } MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( Opc , ShAmt ) ) ) ; } return


<s> MI . addOperand ( MCOperand :: CreateImm ( slice


<s> static bool DisassembleThumb2SRS ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps


<s> assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; NumOpsAdded =


<s> static bool DisassembleThumbFrm ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO Builder ) { uint16_t HalfWord = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( HalfWord == <NUM_LIT> ) { uint16_t op = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; return DisassembleThumb1 ( op , MI , Opcode ,

insn , NumOps , NumOpsAdded , Builder ) ;


<s> } for ( uint32_t i = lsb ; i <= msb ; ++ i ) Val |= ( <NUM_LIT> << i ) ; mask = ~ Val


<s> static inline unsigned getIImm3Imm8 ( uint32_t insn ) { return slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | getImm3 ( insn ) << <NUM_LIT> |


<s> static inline unsigned getImm12 ( uint32_t insn


<s> return getImm4 ( insn ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT>

| getImm3 ( insn ) << <NUM_LIT> | getImm8 ( insn ) ;


<s> static inline unsigned getImm2 ( uint32_t insn


<s> static inline unsigned getImm3 ( uint32_t insn ) { return slice ( insn , <NUM_LIT> ,


<s> static inline unsigned getImm4 ( uint32_t insn ) { return slice ( insn , <NUM_LIT>


<s> return slice ( insn , <NUM_LIT> , <NUM_LIT>


<s> static inline unsigned getLsb ( uint32_t


<s> static inline unsigned getMsb ( uint32_t


<s> return getImm3 ( insn ) << <NUM_LIT> | getImm2 (


<s> static inline unsigned getT1Imm3 ( uint32_t insn ) { return slice ( insn , <NUM_LIT>


<s> static inline unsigned getT1Imm5 ( uint32_t insn ) { return slice ( insn , <NUM_LIT>


<s> static inline unsigned getT1Imm6 ( uint32_t insn ) { return slice ( insn , <NUM_LIT> , <NUM_LIT> ) <<

<NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> static inline unsigned getT1Rd ( uint32_t insn ) { return slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn


<s> static inline unsigned getT1tRd ( uint32_t insn ) { return slice ( insn , <NUM_LIT> ,


<s> static inline unsigned getT1tRm ( uint32_t insn ) { return slice ( insn ,


<s> static inline unsigned getT1tRn ( uint32_t insn


<s> static inline unsigned getT1tRn ( uint32_t insn ) { return slice ( insn , <NUM_LIT>


<s> static inline bool IsGPR ( unsigned RegClass ) { return RegClass == <STR_LIT> ||


<s> if ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) return true ; return false


<s> switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; return <NUM_LIT> ; case <NUM_LIT> : return imm8 ; case <NUM_LIT> : return imm8 << <NUM_LIT> | imm8 ; case <NUM_LIT> : return imm8 << <NUM_LIT> | imm8 << <NUM_LIT> ; case <NUM_LIT> : return imm8 << <NUM_LIT> | imm8 << <NUM_LIT> | imm8 << <NUM_LIT> | imm8 ; } } else { unsigned Val = <NUM_LIT> << <NUM_LIT> | slice ( imm12 , <NUM_LIT> , <NUM_LIT> ) ; unsigned Amt = slice ( imm12 , <NUM_LIT> , <NUM_LIT> ) ; return <STR_LIT> ( Val ,


<s> int Offset = TFI -> ResolveFrameIndexReference ( MF , FrameIndex , FrameReg , SPAdj ) ; if ( RS && FrameReg == <STR_LIT> && RS -> isScavengingFrameIndex ( FrameIndex ) ) { assert ( STI . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) && <STR_LIT> <STR_LIT> ) ; assert ( ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) && <STR_LIT> <STR_LIT> ) ; } if ( MI . isDebugValue ( ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } assert ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) && <STR_LIT> ) ; if ( rewriteFrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( Offset && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands ( MI , PIdx ) ; if ( MI . mayLoad ( ) ) { unsigned TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , TmpReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , TmpReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else { emitThumbRegPlusImmediate ( MBB , II , dl , TmpReg , FrameReg , Offset , TII , * this ) ; } MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( TmpReg , false , false


<s> if ( STI . isThumb1Only ( ) ) { assert ( ( is<ISA_LIT>LowRegister ( DestReg ) || isVirtualRegister ( DestReg ) ) && <STR_LIT> ) ; return emitThumb1LoadConstPool ( MBB , MBBI , dl , DestReg , SubIdx , Val , Pred , PredReg , MIFlags ) ; } return emitThumb2LoadConstPool ( MBB , MBBI , dl , DestReg ,


<s> if ( STI . isThumb1Only ( ) ) { assert ( ( is<ISA_LIT>LowRegister ( DestReg ) || isVirtualRegister ( DestReg ) ) && <STR_LIT> ) ; return emitThumb1LoadConstPool ( MBB , MBBI , dl , DestReg ,


<s> static void emitThumb1LoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const DebugLoc & dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg , unsigned MIFlags ) { MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo (


<s> unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . add ( predOps

( <STR_LIT> ) ) . setMIFlags ( MIFlags ) ;


<s> const TargetRegisterClass * ThumbRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb1Only ( ) ) return <ISA_LIT>BaseRegisterInfo :: getLargestLegalSuperClass ( RC , MF ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return & <STR_LIT> ; return <ISA_LIT>BaseRegisterInfo :: getLargestLegalSuperClass (


<s> const TargetRegisterClass * ThumbRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb1Only

( ) ) return <ISA_LIT>BaseRegisterInfo :: getPointerRegClass ( MF , Kind ) ;


<s> void ThumbRegisterInfo :: resolveFrameIndex ( MachineInstr & MI , unsigned BaseReg , int64_t Offset ) const { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! STI . isThumb1Only ( ) ) return <ISA_LIT>BaseRegisterInfo :: resolveFrameIndex ( MI , BaseReg , Offset ) ; const <ISA_LIT>BaseInstrInfo & TII = * STI . getInstrInfo ( ) ; int Off


<s> bool ThumbRegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! STI . isThumb1Only ( ) ) return <ISA_LIT>BaseRegisterInfo :: saveScavengerRegister ( MBB , I , UseMI , RC , Reg ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; DebugLoc DL ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) . add ( predOps ( <STR_LIT> ) ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugInstr ( ) ) continue ; for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( )


<s> Register VReg ; const <ISA_LIT>BaseInstrInfo & TII = * STI . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB ( * MBB . getParent ( ) , & MI ) ; Register FrameReg ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; int Offset = TFI -> ResolveFrameIndexReference ( MF , FrameIndex , FrameReg , SPAdj ) ; if ( RS && FrameReg == <STR_LIT> && RS -> isScavengingFrameIndex ( FrameIndex ) ) { assert ( STI . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) && <STR_LIT> <STR_LIT> ) ; assert ( ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) && <STR_LIT> <STR_LIT> ) ; } if ( MI . isDebugValue ( ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } assert ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) && <STR_LIT> ) ; if ( rewriteFrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( Offset && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands ( MI , PIdx ) ; if ( MI . mayLoad ( ) ) { Register TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , TmpReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , TmpReg


<s> assert ( ( is<ISA_LIT>LowRegister ( DestReg ) || DestReg . isVirtual ( ) ) && <STR_LIT> ) ; return emitThumb1LoadConstPool ( MBB , MBBI , dl , DestReg , SubIdx , Val , Pred , PredReg , MIFlags ) ; } return emitThumb2LoadConstPool ( MBB , MBBI , dl , DestReg ,


<s> static void emitThumb2LoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const DebugLoc & dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg , unsigned MIFlags ) { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool


<s> CopyBits = <NUM_LIT> ; CopyScale = <NUM_LIT> ; } else if ( DestReg == BaseReg ) { } else if ( is<ISA_LIT>LowRegister ( BaseReg ) ) { CopyOpc = isSub ? <STR_LIT> : <STR_LIT> ; CopyBits = <NUM_LIT> ; CopyNeedsCC = true ; } else { CopyOpc = <STR_LIT> ; CopyBits = <NUM_LIT> ; } ExtraOpc = isSub ? <STR_LIT> : <STR_LIT> ; ExtraBits = <NUM_LIT> ; ExtraNeedsCC = true ; } else { if ( DestReg == BaseReg ) { } else { CopyOpc = <STR_LIT> ; CopyBits = <NUM_LIT> ; } ExtraOpc = <NUM_LIT> ; } assert ( ( ( Bytes & <NUM_LIT> ) == <NUM_LIT> || ExtraScale == <NUM_LIT> ) && <STR_LIT> ) ; unsigned CopyRange = ( ( <NUM_LIT> << CopyBits ) - <NUM_LIT> ) * CopyScale ; if ( CopyOpc && Bytes < CopyScale ) { CopyOpc = <STR_LIT> ; CopyScale = <NUM_LIT> ; CopyNeedsCC = false ; CopyRange = <NUM_LIT> ; } unsigned ExtraRange = ( ( <NUM_LIT> << ExtraBits ) - <NUM_LIT> ) * ExtraScale ; unsigned RequiredCopyInstrs = CopyOpc ? <NUM_LIT> : <NUM_LIT> ; unsigned RangeAfterCopy = ( CopyRange > Bytes ) ? <NUM_LIT> : ( Bytes - CopyRange ) ; assert ( RangeAfterCopy % ExtraScale == <NUM_LIT> && <STR_LIT> ) ; unsigned RequiredExtraInstrs ; if ( ExtraRange ) RequiredExtraInstrs = alignTo ( RangeAfterCopy , ExtraRange ) / ExtraRange ; else if ( RangeAfterCopy > <NUM_LIT> ) RequiredExtraInstrs = <NUM_LIT> ; else RequiredExtraInstrs = <NUM_LIT> ; unsigned RequiredInstrs = RequiredCopyInstrs + RequiredExtraInstrs ; unsigned Threshold = ( DestReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( RequiredInstrs > Threshold ) { emitThumbRegPlusImmInReg ( MBB , MBBI , dl , DestReg , BaseReg , NumBytes , true , TII , MRI , MIFlags ) ; return ; } if ( CopyOpc ) { unsigned CopyImm = std :: min ( Bytes , CopyRange ) / CopyScale ; Bytes -= CopyImm * CopyScale ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( CopyOpc ) , DestReg ) ; if ( CopyNeedsCC ) MIB = MIB . add ( t1CondCodeOp ( ) ) ; MIB . addReg ( BaseReg , RegState :: Kill ) ; if ( CopyOpc != <STR_LIT> ) { MIB . addImm ( CopyImm ) ; } MIB . setMIFlags ( MIFlags ) . add ( predOps ( <STR_LIT> ) ) ; BaseReg =


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addReg ( LdReg , RegState :: Kill ) . setMIFlags ( MIFlags ) ; } else if ( ST . genExecuteOnly ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , dl , LdReg , <NUM_LIT> , NumBytes , <STR_LIT> , <NUM_LIT> , MIFlags ) ; int Opc = ( isSub ) ? <STR_LIT> : ( ( isHigh || ! CanChangeCC ) ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII


<s> Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; emitThumbRegPlusImmediate ( MBB , II , dl , DestReg , FrameReg , Offset , TII , * this ) ; MBB . erase ( II ) ; return true ; } else { if ( AddrMode != <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; unsigned ImmIdx = FrameRegIdx + <NUM_LIT> ; int InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; unsigned NumBits = ( FrameReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; Offset += InstrOffs * Scale ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand & ImmOp = MI . getOperand ( ImmIdx ) ; int ImmedOffset = Offset / Scale ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( unsigned ) Offset <= Mask * Scale ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; ImmOp . ChangeToImmediate ( ImmedOffset ) ; unsigned NewOpc = convertToNonSPOpcode


<s> if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb1Only ( ) ) { return false


<s> bool ThumbRegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb1Only ( ) ) { return false


<s> int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands ( MI , PIdx ) ; if ( MI . mayLoad ( ) ) { unsigned TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , TmpReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , TmpReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else { emitThumbRegPlusImmediate ( MBB , II , dl , TmpReg , FrameReg , Offset , TII , * this ) ; } MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( TmpReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else if ( MI . mayStore ( ) ) { VReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , VReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , VReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else emitThumbRegPlusImmediate ( MBB , II , dl , VReg , FrameReg , Offset , TII , * this ) ; MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( VReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( MI . isPredicable ( ) ) MIB . add ( predOps (


<s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( )


<s> const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; DebugLoc DL ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) . add ( predOps ( <STR_LIT> ) ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugValue ( ) ) continue ; for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i


<s> void ThumbRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . isThumb1Only ( )


<s> static void emitThumb1LoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg , unsigned MIFlags ) { MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF .


<s> } ExtraOpc = isSub ? <STR_LIT> : <STR_LIT> ; ExtraBits = <NUM_LIT> ; ExtraScale = <NUM_LIT> ; } else if ( is<ISA_LIT>LowRegister ( DestReg ) ) { if ( BaseReg == <STR_LIT> ) { assert ( ! isSub && <STR_LIT> ) ; CopyOpc = <STR_LIT> ; CopyBits = <NUM_LIT> ; CopyScale = <NUM_LIT> ; } else if ( DestReg == BaseReg ) { } else if ( is<ISA_LIT>LowRegister ( BaseReg ) ) { CopyOpc = isSub ? <STR_LIT> : <STR_LIT> ; CopyBits = <NUM_LIT> ; CopyNeedsCC = true ; } else { CopyOpc = <STR_LIT> ; CopyBits = <NUM_LIT> ; } ExtraOpc = isSub ? <STR_LIT> : <STR_LIT> ; ExtraBits = <NUM_LIT> ; ExtraNeedsCC = true ; } else { if ( DestReg == BaseReg ) { } else { CopyOpc = <STR_LIT> ; CopyBits = <NUM_LIT> ; } ExtraOpc = <NUM_LIT> ; } assert ( ( ( Bytes & <NUM_LIT> ) == <NUM_LIT> || ExtraScale == <NUM_LIT> ) && <STR_LIT> ) ; unsigned CopyRange = ( ( <NUM_LIT> << CopyBits ) - <NUM_LIT> ) * CopyScale ; if ( CopyOpc && Bytes < CopyScale ) { CopyOpc = <STR_LIT> ; CopyScale = <NUM_LIT> ; CopyNeedsCC = false ; CopyRange = <NUM_LIT> ; } unsigned ExtraRange = ( ( <NUM_LIT> << ExtraBits ) - <NUM_LIT> ) * ExtraScale ; unsigned RequiredCopyInstrs = CopyOpc ? <NUM_LIT> : <NUM_LIT> ; unsigned RangeAfterCopy = ( CopyRange > Bytes ) ? <NUM_LIT> : ( Bytes - CopyRange ) ; assert ( RangeAfterCopy % ExtraScale == <NUM_LIT> && <STR_LIT> ) ; unsigned RequiredExtraInstrs ; if ( ExtraRange ) RequiredExtraInstrs = alignTo ( RangeAfterCopy , ExtraRange ) / ExtraRange ; else if ( RangeAfterCopy > <NUM_LIT> ) RequiredExtraInstrs = <NUM_LIT> ; else RequiredExtraInstrs = <NUM_LIT> ; unsigned RequiredInstrs = RequiredCopyInstrs + RequiredExtraInstrs ; unsigned Threshold = ( DestReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( RequiredInstrs > Threshold ) { emitThumbRegPlusImmInReg ( MBB , MBBI , dl , DestReg , BaseReg , NumBytes , true , TII , MRI , MIFlags ) ; return ; } if ( CopyOpc ) { unsigned CopyImm = std :: min ( Bytes , CopyRange ) / CopyScale ; Bytes -= CopyImm * CopyScale ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( CopyOpc ) , DestReg ) ; if ( CopyNeedsCC ) MIB = AddDefaultT1CC ( MIB ) ; MIB . addReg ( BaseReg , RegState :: Kill ) ; if ( CopyOpc != <STR_LIT> ) { MIB . addImm ( CopyImm ) ; } AddDefaultPred ( MIB . setMIFlags ( MIFlags ) ) ; BaseReg = DestReg ; } while ( Bytes ) { unsigned ExtraImm = std :: min (


<s> unsigned TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , TmpReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , TmpReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else { emitThumbRegPlusImmediate ( MBB , II , dl , TmpReg , FrameReg , Offset , TII , * this ) ; } MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( TmpReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else if ( MI . mayStore ( ) ) { VReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , VReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , VReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else emitThumbRegPlusImmediate ( MBB , II , dl , VReg , FrameReg


<s> if ( DestReg == <STR_LIT> ) assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; if ( ! is<ISA_LIT>LowRegister ( DestReg ) && ! MRI . isVirtualRegister ( DestReg ) ) LdReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> && CanChangeCC ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> && CanChangeCC ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addReg ( LdReg , RegState :: Kill ) . setMIFlags ( MIFlags ) ; } else if ( ST . genExecuteOnly ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , dl , LdReg , <NUM_LIT> , NumBytes , <STR_LIT> , <NUM_LIT> , MIFlags ) ; int Opc = ( isSub ) ? <STR_LIT> : ( ( isHigh || ! CanChangeCC ) ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ; if ( Opc != <STR_LIT> ) MIB =


<s> if ( MI . isDebugValue ( ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } assert ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) && <STR_LIT> ) ; if ( rewriteFrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( Offset && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands ( MI , PIdx ) ; if ( MI . mayLoad ( ) ) { Register TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , TmpReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , TmpReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else { emitThumbRegPlusImmediate ( MBB , II , dl , TmpReg , FrameReg , Offset , TII , * this ) ; } MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( TmpReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else if ( MI . mayStore ( ) ) { VReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , VReg , FrameReg ,


<s> void ThumbRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const DebugLoc & dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget


<s> if ( NumBytes < <NUM_LIT> && ! isHigh && CanChangeCC ) { isSub = true ; NumBytes = - NumBytes ; } unsigned LdReg = DestReg ; if ( DestReg == <STR_LIT> ) assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; if ( ! is<ISA_LIT>LowRegister ( DestReg ) && ! Register :: isVirtualRegister ( DestReg ) ) LdReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> && CanChangeCC ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> && CanChangeCC ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addImm (


<s> } unsigned LdReg = DestReg ; if ( DestReg == <STR_LIT> ) assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; if ( ! is<ISA_LIT>LowRegister ( DestReg ) && ! Register :: isVirtualRegister ( DestReg ) ) LdReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> && CanChangeCC ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> && CanChangeCC ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addReg ( LdReg , RegState :: Kill ) . setMIFlags ( MIFlags ) ; } else if ( ST . genExecuteOnly ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , dl , LdReg , <NUM_LIT> , NumBytes , <STR_LIT> , <NUM_LIT> , MIFlags ) ; int Opc = ( isSub ) ? <STR_LIT> : ( ( isHigh || ! CanChangeCC ) ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ; if ( Opc != <STR_LIT> ) MIB = MIB . add ( t1CondCodeOp ( ) ) ; if ( DestReg == <STR_LIT> || isSub ) MIB . addReg ( BaseReg ) . addReg


<s> DebugLoc dl = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB ( * MBB . getParent ( ) , & MI ) ; unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MI . getDesc ( ) ; unsigned AddrMode = ( Desc . TSFlags & <STR_LIT> ) ; if ( Opcode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; emitThumbRegPlusImmediate ( MBB , II , dl , DestReg , FrameReg , Offset , TII , * this ) ; MBB . erase ( II ) ; return true ; } else { if ( AddrMode != <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; unsigned ImmIdx = FrameRegIdx + <NUM_LIT> ; int InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; unsigned NumBits = ( FrameReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; Offset += InstrOffs * Scale ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand & ImmOp = MI . getOperand ( ImmIdx ) ; int ImmedOffset = Offset / Scale ; unsigned Mask = ( <NUM_LIT> << NumBits


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; assert ( MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb1Only ( ) && <STR_LIT> ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB ( * MBB . getParent ( ) , & MI ) ; unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MI . getDesc ( ) ; unsigned AddrMode = ( Desc . TSFlags & <STR_LIT> ) ; if ( Opcode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; emitThumbRegPlusImmediate ( MBB , II , dl , DestReg , FrameReg , Offset , TII , * this ) ; MBB . erase ( II ) ; return true ; } else { if ( AddrMode != <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; unsigned ImmIdx = FrameRegIdx + <NUM_LIT> ; int InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; unsigned NumBits = ( FrameReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; Offset += InstrOffs * Scale ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand & ImmOp = MI .


<s> unsigned Op = i ; for ( unsigned e = MI . getNumOperands ( ) ; i != e ; ++ i ) MI . removeOperand


<s> MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( )

-> getFunction ( ) -> getContext ( ) ) , Val ) ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; bool isHigh = ! is<ISA_LIT>LowRegister ( DestReg ) || ( BaseReg != <NUM_LIT> && ! is<ISA_LIT>LowRegister ( BaseReg ) ) ; bool isSub = false ; if ( NumBytes < <NUM_LIT> && ! isHigh && CanChangeCC ) { isSub = true ; NumBytes = - NumBytes ; } unsigned LdReg = DestReg ; if ( DestReg == <STR_LIT> ) assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; if ( ! is<ISA_LIT>LowRegister ( DestReg ) && ! MRI . isVirtualRegister ( DestReg ) ) LdReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> && CanChangeCC ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> && CanChangeCC ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addReg ( LdReg , RegState :: Kill ) . setMIFlags ( MIFlags ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , dl , LdReg , <NUM_LIT> , NumBytes , <STR_LIT> , <NUM_LIT> , MIFlags ) ; int Opc = ( isSub ) ? <STR_LIT> : ( ( isHigh || ! CanChangeCC ) ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ; if ( Opc != <STR_LIT> ) MIB = AddDefaultT1CC ( MIB ) ; if ( DestReg == <STR_LIT> || isSub ) MIB . addReg ( BaseReg ) . addReg ( LdReg , RegState :: Kill ) ; else MIB . addReg ( LdReg ) . addReg ( BaseReg , RegState :: Kill ) ; AddDefaultPred ( MIB )


<s> if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { UseMI = II ; done = true ; break ; } if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) { UseMI = II ; done = true ; break ; } } } AddDefaultPred ( BuildMI ( MBB , UseMI , DL , TII . get ( <STR_LIT> ) ) .

addReg ( Reg , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) ) ;