<s> SDLoc dl ( Op ) ; SDValue Val = DAG . getUNDEF ( <STR_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; if ( Op1 . getOpcode ( ) != <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode ( <STR_LIT> , dl

, <STR_LIT> , Op1 ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerConstantFP ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget * ST ) const { if ( ! ST -> hasVFP3 ( ) ) return SDValue ( ) ; bool IsDouble = Op . getValueType ( ) == <STR_LIT> ; ConstantFPSDNode * CFP = cast < ConstantFPSDNode > ( Op ) ; APFloat FPVal = CFP -> getValueAPF ( ) ; int ImmVal = IsDouble ? <STR_LIT> ( FPVal ) : <STR_LIT> ( FPVal ) ; if ( ImmVal != - <NUM_LIT> ) { if ( IsDouble || ! ST -> useNEONForSinglePrecisionFP ( ) ) { return Op ; } SDLoc DL ( Op ) ; SDValue NewVal = DAG . getTargetConstant ( ImmVal , <STR_LIT> ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewVal ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } if ( ! ST -> hasNEON ( ) || ( ! IsDouble && ! ST -> useNEONForSinglePrecisionFP ( ) ) ) return SDValue ( ) ; EVT VMovVT ; uint64_t iVal = FPVal . bitcastToAPInt (


<s> assert ( ST -> hasNEON ( ) && <STR_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT>


<s> if ( VT . is64BitVector ( ) ) { SDValue Extended = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BitCounts ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Extended ,

DAG . getIntPtrConstant ( <NUM_LIT> ) ) ;


<s> EVT VT16Bit = VT . is64BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Bitcast = DAG . getNode ( <STR_LIT> , DL , VT16Bit , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Counts16 = lowerCTPOP16BitElements ( Bitcast . getNode ( ) , DAG ) ; SDValue N0 = DAG . getNode ( <STR_LIT> , DL , VT16Bit , Counts16 ) ; SDValue N1 = DAG . getNode ( <STR_LIT> , DL , VT16Bit , Counts16 , N0 ) ; SDValue N2 = DAG . getNode ( <STR_LIT> , DL , VT16Bit , N1 , N1 ) ; if ( VT . is64BitVector ( ) ) { SDValue Extended = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N2 ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT>

, Extended , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( N ) ; if ( ! ST -> hasV6T2Ops ( ) ) return SDValue ( ) ; SDValue rbit = DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT ,


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( N ) ; if ( ! ST -> hasV6T2Ops ( ) ) return


<s> assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; SDValue Words = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Size , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Flag ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , Words , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList (


<s> SDValue <ISA_LIT>TargetLowering :: LowerEH_SJLJ_LONGJMP ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl (


<s> if ( UseNEON ) { unsigned EncodedVal = <STR_LIT> ( <NUM_LIT> , <NUM_LIT> ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getTargetConstant ( EncodedVal , <STR_LIT> ) ) ; EVT OpVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( VT == <STR_LIT> ) Mask = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , OpVT , Mask ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; else Tmp0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp0 ) ; if ( SrcVT == <STR_LIT> ) { Tmp1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp1 ) ; if ( VT == <STR_LIT> ) Tmp1 = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , OpVT , Tmp1 ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } else if ( VT == <STR_LIT> ) Tmp1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp1 ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Tmp0 = DAG . getNode ( <STR_LIT> , dl , OpVT , Tmp0 ) ; Tmp1 = DAG . getNode ( <STR_LIT> , dl , OpVT , Tmp1 ) ; SDValue AllOnes = DAG . getTargetConstant ( <STR_LIT> ( <NUM_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; AllOnes = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AllOnes ) ; SDValue MaskNot = DAG . getNode ( <STR_LIT> , dl , OpVT , Mask , DAG . getNode ( <STR_LIT> , dl , OpVT , AllOnes ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , OpVT , Tmp1 , Mask ) , DAG . getNode ( <STR_LIT> , dl , OpVT , Tmp0 , MaskNot ) ) ; if ( VT == <STR_LIT> ) { Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res ) ; Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } else { Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res ) ; } return Res ; } if ( SrcVT == <STR_LIT> ) Tmp1 = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Tmp1 ) . getValue ( <NUM_LIT> ) ; Tmp1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp1 ) ; SDValue Mask1 = DAG . getConstant ( <NUM_LIT> ,


<s> SDValue FltRounds = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FPSCR , DAG . getConstant ( <NUM_LIT> << <NUM_LIT> , <STR_LIT> ) ) ; SDValue RMODE = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FltRounds ,

DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned FrameReg = ARI . getFrameRegister ( MF ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( )


<s> ArgListEntry Entry ; Entry . Node = SRet ; Entry . Ty = RetTy -> getPointerTo ( ) ; Entry . isSExt = false ; Entry . isZExt = false ; Entry . isSRet = true ; Args . push_back ( Entry ) ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; const char * LibcallName = ( ArgVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , getPointerTy ( ) ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , Callee , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; SDValue LoadSin = DAG . getLoad ( ArgVT , dl , CallResult . second , SRet , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , SRet , DAG . getIntPtrConstant ( ArgVT . getStoreSize ( ) ) ) ; SDValue LoadCos = DAG . getLoad ( ArgVT , dl , LoadSin . getValue ( <NUM_LIT> ) , Add , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( ArgVT ,


<s> SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getNode ( Wrapper , dl , PtrVT , G ) ; if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ; return


<s> const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { bool UseGOTOFF = GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , UseGOTOFF ? <STR_LIT> : <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , GOT ) ; if ( ! UseGOTOFF ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ; return Result ; } if ( Subtarget -> useMovt ( DAG . getMachineFunction ( ) ) ) { ++ NumMovwMovt ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; } else { SDValue CPAddr = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl


<s> assert ( Subtarget -> useMovt ( DAG . getMachineFunction ( ) ) && <STR_LIT> ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; const <STR_LIT> TargetFlags = ( GV -> hasDLLImportStorageClass ( ) ? <STR_LIT> : <STR_LIT> ) ; EVT PtrVT = getPointerTy ( ) ; SDValue Result ; SDLoc DL ( Op ) ; ++ NumMovwMovt ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetGlobalAddress (

GV , DL , PtrVT , <NUM_LIT> , TargetFlags ) ) ;


<s> GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( Op ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GA -> getGlobal ( ) ) ; switch (


<s> assert ( Subtarget -> isTargetELF ( ) && <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( ) ; SDLoc dl ( Op ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * DAG . getContext (

) , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ;


<s> EVT PtrVT = getPointerTy ( ) ; SDLoc dl ( Op ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * DAG . getContext ( ) , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl ,


<s> if ( ! isa < ConstantSDNode > ( Lane ) ) return SDValue ( ) ; return Op


<s> EVT VT = Op . getValueType ( ) ; if ( VT . isVector ( ) ) return LowerVectorINT_TO_FP ( Op , DAG ) ; SDLoc dl ( Op ) ; unsigned Opc ; switch ( Op . getOpcode


<s> PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ; return DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo :: getStack ( LocMemOffset ) , false , false ,


<s> MFI -> setReturnAddressIsTaken ( true ) ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , <STR_LIT>


<s> unsigned ExtractNum = ( VT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , DL , VT , OpLHS , OpLHS , DAG .

getConstant ( ExtractNum , <STR_LIT> ) ) ;


<s> static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16 ( SDValue Op , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; SDValue OpLHS = Op . getOperand ( <NUM_LIT> ) ; EVT VT = OpLHS . getValueType ( ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; OpLHS = DAG . getNode ( <STR_LIT> , DL ,


<s> static SDValue LowerSDIV ( SDValue Op , SelectionDAG & DAG ) { EVT VT = Op . getValueType ( ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; SDValue N2 , N3 ; if ( VT == <STR_LIT> ) { N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N0 = LowerSDIV_v4i8 ( N0 , N1 , dl , DAG ) ; N2 = LowerSDIV_v4i8 ( N2 , N3 , dl , DAG ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = LowerCONCAT_VECTORS ( N0 , DAG


<s> SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; SDValue N2 , N3 ; if ( VT == <STR_LIT> ) { N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N0 = LowerSDIV_v4i8 ( N0 , N1 , dl , DAG ) ; N2 = LowerSDIV_v4i8 ( N2 , N3 , dl , DAG ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = LowerCONCAT_VECTORS ( N0


<s> N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N1 , N1 , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N0 = DAG . getNode ( <STR_LIT> ,


<s> N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , N1 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , N1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N1 , N1 , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0


<s> X = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , X ) ; Y = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Y ) ; Y = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , Y ) ; X = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , X , Y ) ; X = DAG . getNode ( <STR_LIT> , dl ,


<s> SDValue <ISA_LIT>cc ; std :: tie ( Value , OverflowCmp ) = get<ISA_LIT>XALUOOp ( Cond , DAG , <ISA_LIT>cc ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; EVT VT = Op . getValueType ( ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , SelectTrue , SelectFalse , <ISA_LIT>cc , CCR , OverflowCmp ) ; } if ( Cond . getOpcode ( ) == <STR_LIT> && Cond . hasOneUse ( ) ) { const ConstantSDNode * CMOVTrue = dyn_cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ; const ConstantSDNode * CMOVFalse = dyn_cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ; if ( CMOVTrue && CMOVFalse ) { unsigned CMOVTrueVal = CMOVTrue -> getZExtValue ( ) ; unsigned CMOVFalseVal = CMOVFalse -> getZExtValue ( ) ; SDValue True ; SDValue False ; if ( CMOVTrueVal == <NUM_LIT> && CMOVFalseVal == <NUM_LIT> ) { True = SelectTrue ; False = SelectFalse ; } else if ( CMOVTrueVal == <NUM_LIT> && CMOVFalseVal == <NUM_LIT> ) { True = SelectFalse ; False = SelectTrue ; } if ( True . getNode ( ) && False . getNode ( ) ) { EVT VT = Op . getValueType ( ) ; SDValue <ISA_LIT>cc = Cond . getOperand ( <NUM_LIT> ) ; SDValue CCR = Cond . getOperand ( <NUM_LIT> ) ; SDValue Cmp = duplicateCmp ( Cond . getOperand ( <NUM_LIT> ) , DAG ) ; assert ( True . getValueType ( ) == VT ) ; return DAG . getNode ( <STR_LIT> , dl , VT , True


<s> unsigned CMOVTrueVal = CMOVTrue -> getZExtValue ( ) ; unsigned CMOVFalseVal = CMOVFalse -> getZExtValue ( ) ; SDValue True ; SDValue False ; if ( CMOVTrueVal == <NUM_LIT> && CMOVFalseVal == <NUM_LIT> ) { True = SelectTrue ; False = SelectFalse ; } else if ( CMOVTrueVal == <NUM_LIT> && CMOVFalseVal == <NUM_LIT> ) { True = SelectFalse ; False = SelectTrue ; } if ( True . getNode ( ) && False . getNode ( ) ) { EVT VT = Op . getValueType ( ) ; SDValue <ISA_LIT>cc = Cond . getOperand ( <NUM_LIT> ) ; SDValue CCR = Cond . getOperand ( <NUM_LIT> ) ; SDValue Cmp = duplicateCmp ( Cond . getOperand ( <NUM_LIT> ) , DAG ) ; assert ( True . getValueType ( ) == VT ) ; return DAG . getNode ( <STR_LIT> , dl , VT , True , False , <ISA_LIT>cc , CCR ,


<s> CC = getInverseCCForVSEL ( CC ) ; std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp ) ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; if ( getSubtarget ( ) -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { if ( getTargetMachine ( ) . Options . UnsafeFPMath && LHS == TrueVal && RHS == FalseVal ) { if ( CC == <STR_LIT> || CC == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , TrueVal , FalseVal ) ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , TrueVal , FalseVal ) ; } bool swpCmpOps = false ; bool swpVselOps = false ; checkVSELConstraints ( CC , CondCode , swpCmpOps , swpVselOps ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { if ( swpCmpOps ) std :: swap ( LHS , RHS ) ; if ( swpVselOps ) std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp ) ; if ( CondCode2 != <STR_LIT> ) { SDValue <ISA_LIT>cc2 = DAG . getConstant ( CondCode2 , <STR_LIT> ) ; SDValue Cmp2 = getVFPCmp ( LHS , RHS , DAG , dl ) ; Result = DAG . getNode ( <STR_LIT> , dl , VT , Result , TrueVal , <ISA_LIT>cc2 , CCR , Cmp2 ) ; } return Result


<s> assert ( ST -> hasNEON ( ) && <STR_LIT> ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; EVT ShiftVT = N -> getOperand ( <NUM_LIT> ) .


<s> assert ( ST -> hasNEON ( ) && <STR_LIT> ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; EVT ShiftVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue NegatedCount = DAG . getNode ( <STR_LIT> , dl , ShiftVT , getZeroVector ( ShiftVT , DAG , dl ) , N -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> vshiftInt = ( N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( vshiftInt , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> )


<s> SDLoc dl ( Op ) ; SDValue ShOpLo = Op . getOperand ( <NUM_LIT> ) ; SDValue ShOpHi = Op . getOperand ( <NUM_LIT> ) ; SDValue ShAmt = Op . getOperand ( <NUM_LIT> ) ; SDValue <ISA_LIT>cc ; assert ( Op . getOpcode ( ) == <STR_LIT> ) ; SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , RevShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT ,


<s> SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , RevShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue TrueVal = DAG . getNode ( Opc , dl , VT , ShOpHi , ExtraShAmt ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> , <ISA_LIT>cc , DAG , dl ) ; SDValue Hi = DAG . getNode ( Opc , dl , VT , ShOpHi , ShAmt ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp ) ; SDValue Ops [ <NUM_LIT> ] =


<s> <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; Chain = Offset . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT , Offset , PICLabel ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; } else { assert ( model == TLSModel :: LocalExec ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <STR_LIT> ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT


<s> unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Argument . getValue


<s> Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Argument ; Entry . Ty = ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Args . push_back ( Entry


<s> N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N0 = LowerSDIV_v4i16 ( N0 , N1 , dl , DAG ) ; N2 = LowerSDIV_v4i16 ( N2 , N3 , dl , DAG ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = LowerCONCAT_VECTORS ( N0 , DAG ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , N0 ) ; return N0 ; } N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; SDValue BN1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , BN1 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , BN1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , BN1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl


<s> static SDValue LowerVASTART ( SDValue Op , SelectionDAG & DAG ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; SDLoc dl ( Op ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) ,


<s> SDLoc DL ( Op ) ; SmallVector < SDValue , <NUM_LIT> > VTBLMask ; for ( ArrayRef < int > :: iterator I = ShuffleMask . begin ( ) , E = ShuffleMask . end ( ) ; I != E ; ++ I ) VTBLMask . push_back ( DAG . getConstant ( * I , <STR_LIT> ) ) ; if ( V2 . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VTBLMask ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getNode ( <STR_LIT> , DL ,


<s> case <STR_LIT> : Invert = true ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Swap = true ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Swap = true ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Invert = true ; Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Invert = true ; Opc = <STR_LIT> ; break ; case <STR_LIT> : Invert = true ; case <STR_LIT> : TmpOp0 = Op0 ; TmpOp1 = Op1 ; Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , VT , TmpOp1 , TmpOp0 ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , VT , TmpOp0 , TmpOp1 ) ; break ; case <STR_LIT> : Invert = true ; case <STR_LIT> : TmpOp0 = Op0 ; TmpOp1 = Op1 ; Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , VT , TmpOp1 , TmpOp0 ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , VT , TmpOp0 , TmpOp1 ) ; break ; } } else { switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Invert = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } if ( Opc == <STR_LIT> ) { SDValue AndOp ; if ( <STR_LIT> ( Op1 . getNode ( ) ) ) AndOp = Op0 ; else if ( <STR_LIT> ( Op0 . getNode ( ) ) ) AndOp = Op1 ; if ( AndOp . getNode ( ) && AndOp . getOpcode ( ) == <STR_LIT> ) AndOp = AndOp . getOperand ( <NUM_LIT> ) ; if ( AndOp . getNode ( ) && AndOp . getOpcode ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , VT , AndOp .


<s> break ; case <STR_LIT> : Invert = true ; case <STR_LIT> : TmpOp0 = Op0 ; TmpOp1 = Op1 ; Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , VT , TmpOp1 , TmpOp0 ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , VT , TmpOp0 , TmpOp1 ) ; break ; } } else { switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Invert = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } if ( Opc == <STR_LIT> ) { SDValue AndOp ; if ( <STR_LIT> ( Op1 . getNode ( ) ) ) AndOp = Op0 ; else if ( <STR_LIT> ( Op0 . getNode ( ) ) ) AndOp = Op1 ; if ( AndOp . getNode ( ) && AndOp . getOpcode ( ) == <STR_LIT> ) AndOp = AndOp . getOperand ( <NUM_LIT> ) ; if ( AndOp . getNode ( ) && AndOp . getOpcode ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , VT , AndOp . getOperand ( <NUM_LIT> ) ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , VT , AndOp . getOperand ( <NUM_LIT> ) ) ; Invert = ! Invert ; } } } if ( Swap ) std :: swap ( Op0 , Op1 ) ; SDValue SingleOp ; if ( <STR_LIT> ( Op1 . getNode ( ) ) ) SingleOp = Op0 ; else if ( <STR_LIT> ( Op0 . getNode ( ) ) ) { if ( Opc == <STR_LIT> ) Opc = <STR_LIT> ; else if ( Opc == <STR_LIT> ) Opc = <STR_LIT> ; SingleOp = Op1 ; } SDValue Result ; if ( SingleOp . getNode ( ) ) { switch ( Opc ) { case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , SingleOp ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl ,


<s> SDValue TVal = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; EVT VT = Op . getValueType ( ) ; SDValue Overflow = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , TVal , FVal , <ISA_LIT>cc , CCR , OverflowCmp ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType (


<s> unsigned Bytes = Arg . getValueType ( ) . getSizeInBits ( ) / <NUM_LIT> ; int FI = INT_MAX ; if ( Arg . getOpcode ( ) == <STR_LIT> ) { unsigned VR = cast < RegisterSDNode > ( Arg . getOperand ( <NUM_LIT> ) ) -> getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( VR ) ) return false ; MachineInstr * Def = MRI -> getVRegDef ( VR ) ; if ( ! Def ) return false ; if ( ! Flags . isByVal ( ) ) { if ( ! TII -> isLoadFromStackSlot ( Def , FI ) ) return false ; } else { return false ; } } else if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Arg ) ) { if ( Flags . isByVal ( ) ) return false ; SDValue Ptr = Ld -> getBasePtr ( ) ; FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ; if ( ! FINode ) return false ; FI = FINode -> getIndex ( ) ; } else return false ; assert ( FI !=


<s> unsigned Bytes = Arg . getValueType ( ) . getSizeInBits ( ) / <NUM_LIT> ; int FI = INT_MAX ; if ( Arg . getOpcode ( ) == <STR_LIT> ) { unsigned VR = cast < RegisterSDNode > ( Arg . getOperand ( <NUM_LIT> ) ) -> getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( VR ) ) return false ; MachineInstr * Def = MRI -> getVRegDef ( VR ) ; if ( ! Def ) return false ; if ( ! Flags . isByVal ( ) ) { if ( ! TII -> isLoadFromStackSlot ( Def , FI ) ) return false ; } else { return false ; } } else if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Arg ) ) { if ( Flags . isByVal ( ) ) return false ; SDValue Ptr = Ld -> getBasePtr ( ) ; FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ; if ( ! FINode ) return false ; FI = FINode -> getIndex ( ) ; } else return false ; assert ( FI != INT_MAX ) ; if ( ! MFI -> isFixedObjectIndex (


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! Subtarget -> supportsTailCall ( ) )


<s> if ( ! Subtarget -> supportsTailCall ( ) ) return false ; if ( ! CI -> isTailCall ( ) || getTargetMachine ( ) . Options . DisableTailCalls ) return false ; return ! Subtarget ->


<s> static bool memOpAlign ( unsigned DstAlign , unsigned SrcAlign ,


<s> SDValue <ISA_LIT>cc ; if ( LHS . getValueType ( ) == <STR_LIT> ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , bitcastf32Toi32 ( LHS , DAG ) , Mask ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , bitcastf32Toi32 ( RHS , DAG ) , Mask ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } SDValue LHS1 , LHS2 ; SDValue RHS1 , RHS2 ; expandf64Toi32 ( LHS , DAG , LHS1 , LHS2 ) ; expandf64Toi32 ( RHS , DAG , RHS1


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; bool LHSSeenZero = false ; bool LHSOk = canChangeToInt ( LHS , LHSSeenZero , Subtarget ) ; bool RHSSeenZero = false ; bool RHSOk = canChangeToInt ( RHS , RHSSeenZero , Subtarget ) ; if ( LHSOk && RHSOk && ( LHSSeenZero || RHSSeenZero ) ) { if ( CC == <STR_LIT> ) CC = <STR_LIT> ; else if ( CC == <STR_LIT> ) CC = <STR_LIT> ; SDValue Mask = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue <ISA_LIT>cc ; if ( LHS . getValueType ( ) == <STR_LIT> ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , bitcastf32Toi32 ( LHS , DAG ) , Mask ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , bitcastf32Toi32 ( RHS , DAG ) , Mask ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } SDValue LHS1


<s> for ( MachineBasicBlock :: succ_iterator I = MBB -> succ_begin ( ) , E = MBB -> succ_end ( ) ; I != E ; ++ I ) if ( * I != Succ ) return * I ; llvm_unreachable (


<s> return AddCombineTo64bitMLAL ( N , DCI


<s> static SDValue PerformADDCCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { return AddCombineTo64bitMLAL ( N ,


<s> SDValue Result = PerformADDCombineWithOperands ( N , N0 , N1 , DCI , Subtarget ) ; if ( Result . getNode


<s> if ( Result . getNode ( ) ) return Result ; if ( N0 . getNode ( ) -> hasOneUse ( ) ) { SDValue Result = combineSelectAndUse ( N , N0 , N1


<s> bool HasAnyUndefs ; if ( BVN && BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize <= <NUM_LIT> ) { EVT VbicVT ; SDValue Val = isNEONModifiedImm ( ( ~ SplatBits ) . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , VbicVT , VT . is128BitVector ( ) , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VbicVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Vbic = DAG . getNode ( <STR_LIT> , dl


<s> SDValue V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( i ) ) ; Ops . push_back ( V ) ; DCI . AddToWorklist ( V . getNode ( ) ) ; } EVT FloatVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; SDValue BV = DAG . getNode ( <STR_LIT> , dl , FloatVT


<s> SDValue NewCmp = get<ISA_LIT>Cmp ( LHS , RHS , <STR_LIT> , <ISA_LIT>cc , DAG , dl ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , LHS , FalseVal , <ISA_LIT>cc , N -> getOperand ( <NUM_LIT> ) , NewCmp ) ; } if ( Res . getNode ( ) ) { APInt KnownZero , KnownOne ; DAG . computeKnownBits ( SDValue ( N , <NUM_LIT> ) , KnownZero , KnownOne ) ; if ( KnownZero == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getValueType ( <STR_LIT> ) ) ; else if ( KnownZero == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> case <STR_LIT> : return PerformADDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformSUBCombine ( N , DCI ) ; case <STR_LIT> : return PerformMULCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformXORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformANDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformBFICombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVRRDCombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVDRRCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformSTORECombine ( N , DCI ) ; case <STR_LIT> : return PerformBUILD_VECTORCombine ( N , DCI ) ; case <STR_LIT> : return PerformInsertEltCombine ( N , DCI ) ; case <STR_LIT> : return PerformVECTOR_SHUFFLECombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformVDUPLANECombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return PerformVCVTCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformVDIVCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI .


<s> case <STR_LIT> : return PerformADDCCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformADDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformSUBCombine ( N , DCI ) ; case <STR_LIT> : return PerformMULCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformXORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformANDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformBFICombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVRRDCombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVDRRCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformSTORECombine ( N , DCI ) ; case <STR_LIT> : return PerformBUILD_VECTORCombine ( N , DCI ) ; case <STR_LIT> : return PerformInsertEltCombine ( N , DCI ) ; case <STR_LIT> : return PerformVECTOR_SHUFFLECombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformVDUPLANECombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return PerformVCVTCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformVDIVCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformSELECT_CCCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return CombineBaseUpdate ( N , DCI ) ; case <STR_LIT> : return Perform<ISA_LIT>BUILD_VECTORCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> SDValue Vec = N0 . getOperand ( <NUM_LIT> ) ; SDValue Lane = N0 . getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT EltVT = N0 . getValueType ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( VT == <STR_LIT> && ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && TLI . isTypeLegal ( Vec . getValueType ( ) ) && isa < ConstantSDNode > ( Lane ) ) { unsigned Opc = <NUM_LIT> ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; break ; } return DAG . getNode ( Opc , SDLoc ( N ) , VT , Vec , Lane ) ; } } return SDValue (


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; if ( ST -> hasNEON ( ) && N0 . getOpcode ( ) == <STR_LIT> ) { SDValue Vec = N0 . getOperand ( <NUM_LIT> ) ; SDValue Lane = N0 . getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT EltVT = N0 . getValueType ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( VT == <STR_LIT> && ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && TLI . isTypeLegal ( Vec . getValueType ( ) ) && isa < ConstantSDNode > ( Lane ) ) { unsigned Opc = <NUM_LIT> ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case


<s> SDNode * Elt = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( VT . getVectorElementType ( ) != <STR_LIT> || ! <STR_LIT> ( Elt ) || cast < LoadSDNode > ( Elt ) -> isVolatile ( ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc dl ( N ) ; EVT FloatVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; SDValue Vec = DAG . getNode ( <STR_LIT> , dl , FloatVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; DCI . AddToWorklist ( Vec . getNode ( ) ) ; DCI . AddToWorklist ( V . getNode (


<s> if ( VT . getVectorElementType ( ) != <STR_LIT> || ! <STR_LIT> ( Elt ) || cast < LoadSDNode > ( Elt ) -> isVolatile ( ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc dl ( N ) ; EVT FloatVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> ,


<s> SelectionDAG & DAG = DCI . DAG ; if ( Subtarget -> isThumb1Only ( ) ) return SDValue ( ) ; if ( DCI . isBeforeLegalize ( ) || DCI . isCalledByLegalizer ( ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . is64BitVector ( ) || VT . is128BitVector ( ) ) return PerformVMULCombine ( N , DCI , Subtarget ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return SDValue ( ) ; int64_t MulAmt = C -> getSExtValue ( ) ; unsigned ShiftAmt = countTrailingZeros < uint64_t > ( MulAmt ) ; ShiftAmt = ShiftAmt & ( <NUM_LIT> - <NUM_LIT> ) ; SDValue V = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue Res ; MulAmt >>= ShiftAmt ; if ( MulAmt >= <NUM_LIT> ) { if ( isPowerOf2_32 ( MulAmt - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt - <NUM_LIT> ) , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmt + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt + <NUM_LIT> ) , <STR_LIT> ) ) , V ) ; } else return SDValue ( ) ; } else { uint64_t MulAmtAbs = - MulAmt ; if ( isPowerOf2_32 ( MulAmtAbs + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs + <NUM_LIT> ) , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmtAbs - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs - <NUM_LIT> ) , <STR_LIT> ) ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , Res ) ; } else return SDValue ( ) ; } if ( ShiftAmt != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getConstant ( ShiftAmt , <STR_LIT> ) ) ; DCI . CombineTo ( N , Res , false ) ; return SDValue


<s> assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDLoc DL ( St ) ; SDValue WideVec = DAG . getNode ( <STR_LIT> , DL , WideVecVT , StVal ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) ShuffleVec [ i ] = TLI . isBigEndian ( ) ? ( i + <NUM_LIT> ) * SizeRatio - <NUM_LIT> : i * SizeRatio ; if ( ! TLI . isTypeLegal ( WideVecVT ) ) return SDValue ( ) ; SDValue Shuff = DAG . getVectorShuffle ( WideVecVT , DL , WideVec , DAG . getUNDEF ( WideVec . getValueType ( ) ) , ShuffleVec . data ( ) ) ; MVT StoreType = <STR_LIT> ; for ( unsigned tp = <STR_LIT> ; tp < <STR_LIT> ; ++ tp ) { MVT Tp = ( <STR_LIT> ) tp ; if ( TLI . isTypeLegal ( Tp ) && Tp . getSizeInBits ( ) <= NumElems * ToEltSz ) StoreType = Tp ; } if ( ! TLI . isTypeLegal ( StoreType ) ) return SDValue ( ) ; EVT StoreVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StoreType , VT . getSizeInBits ( ) / EVT ( StoreType ) . getSizeInBits ( ) ) ; assert ( StoreVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue ShuffWide = DAG . getNode ( <STR_LIT> , DL , StoreVecVT , Shuff ) ; SmallVector < SDValue , <NUM_LIT> > Chains ; SDValue Increment = DAG . getConstant ( StoreType . getSizeInBits ( ) / <NUM_LIT> , TLI . getPointerTy ( ) ) ; SDValue BasePtr = St -> getBasePtr ( ) ; unsigned E = ( ToEltSz * NumElems ) / StoreType . getSizeInBits ( ) ; for ( unsigned I = <NUM_LIT> ; I < E ; I ++ ) { SDValue SubVec = DAG . getNode ( <STR_LIT> , DL , StoreType , ShuffWide , DAG . getIntPtrConstant ( I ) ) ; SDValue Ch = DAG . getStore ( St -> getChain ( ) , DL , SubVec , BasePtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , St -> getAlignment ( ) ) ; BasePtr = DAG . getNode ( <STR_LIT> , DL , BasePtr . getValueType ( ) , BasePtr , Increment ) ; Chains . push_back ( Ch ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chains ) ; } if ( ! <STR_LIT> ( St ) ) return SDValue ( ) ; if ( StVal . getNode ( ) -> getOpcode ( ) == <STR_LIT> && StVal . getNode ( ) -> hasOneUse ( ) ) { SelectionDAG & DAG = DCI . DAG ; bool isBigEndian = DAG . getTargetLoweringInfo ( ) .


<s> SDValue WideVec = DAG . getNode ( <STR_LIT> , DL , WideVecVT , StVal ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) ShuffleVec [ i ] = TLI . isBigEndian ( ) ? ( i + <NUM_LIT> ) * SizeRatio - <NUM_LIT> : i * SizeRatio ; if ( ! TLI . isTypeLegal ( WideVecVT ) ) return SDValue ( ) ; SDValue Shuff = DAG . getVectorShuffle ( WideVecVT , DL , WideVec , DAG . getUNDEF ( WideVec . getValueType ( ) ) , ShuffleVec . data ( ) ) ; MVT StoreType = <STR_LIT> ; for ( unsigned tp = <STR_LIT> ; tp < <STR_LIT> ; ++ tp ) { MVT Tp = ( <STR_LIT> ) tp ; if ( TLI . isTypeLegal ( Tp ) && Tp . getSizeInBits ( ) <= NumElems * ToEltSz ) StoreType = Tp ; } if ( ! TLI . isTypeLegal ( StoreType ) ) return SDValue ( ) ; EVT StoreVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StoreType , VT . getSizeInBits ( ) / EVT ( StoreType ) . getSizeInBits ( ) ) ; assert ( StoreVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue ShuffWide = DAG . getNode ( <STR_LIT> , DL , StoreVecVT , Shuff ) ; SmallVector < SDValue , <NUM_LIT> > Chains ; SDValue Increment = DAG . getConstant ( StoreType . getSizeInBits ( ) / <NUM_LIT> , TLI . getPointerTy ( ) ) ; SDValue BasePtr = St -> getBasePtr ( ) ; unsigned E = ( ToEltSz * NumElems ) / StoreType . getSizeInBits ( ) ; for ( unsigned I = <NUM_LIT> ; I < E ; I ++ ) { SDValue SubVec = DAG . getNode ( <STR_LIT> , DL , StoreType , ShuffWide , DAG . getIntPtrConstant ( I ) ) ; SDValue Ch = DAG . getStore ( St -> getChain ( ) , DL , SubVec , BasePtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , St -> getAlignment ( ) ) ; BasePtr = DAG . getNode ( <STR_LIT> , DL , BasePtr . getValueType ( ) ,


<s> SDValue N0 = Op -> getOperand ( <NUM_LIT> ) ; SDValue ConstVec = Op -> getOperand ( <NUM_LIT> ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> ; if ( ConstVec . getOpcode ( ) != <STR_LIT> || ! isConstVecPow2 ( ConstVec , isSigned , C ) ) return SDValue ( ) ; MVT FloatTy = Op . getSimpleValueType ( ) . getVectorElementType ( ) ; MVT IntTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; if ( FloatTy . getSizeInBits ( ) != <NUM_LIT> || IntTy . getSizeInBits ( ) > <NUM_LIT> ) { return SDValue ( ) ; } unsigned IntrinsicOpcode = isSigned ? <STR_LIT>


<s> if ( ! Subtarget -> hasNEON ( ) || ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) || ( OpOpcode != <STR_LIT> && OpOpcode != <STR_LIT> ) ) return SDValue ( ) ; uint64_t C ; SDValue ConstVec = N -> getOperand ( <NUM_LIT> ) ; bool isSigned = OpOpcode == <STR_LIT> ; if ( ConstVec . getOpcode ( ) != <STR_LIT> || ! isConstVecPow2 ( ConstVec , isSigned , C ) ) return SDValue ( ) ; MVT FloatTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; MVT IntTy = Op . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) .


<s> SDValue Op = N -> getOperand ( <NUM_LIT> ) ; unsigned OpOpcode = Op . getNode ( ) -> getOpcode ( ) ; if ( ! Subtarget -> hasNEON ( ) || ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) || ( OpOpcode != <STR_LIT> && OpOpcode != <STR_LIT> ) ) return SDValue ( ) ; uint64_t C ; SDValue ConstVec = N -> getOperand ( <NUM_LIT> ) ; bool isSigned = OpOpcode == <STR_LIT> ; if ( ConstVec . getOpcode ( ) != <STR_LIT> || ! isConstVecPow2 ( ConstVec , isSigned , C ) ) return SDValue ( ) ; MVT FloatTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; MVT IntTy = Op . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getVectorElementType ( ) ; if ( FloatTy . getSizeInBits ( ) != <NUM_LIT> || IntTy . getSizeInBits ( ) > <NUM_LIT> ) { return SDValue ( ) ; } SDValue ConvInput = Op . getOperand ( <NUM_LIT> ) ; unsigned NumLanes = Op . getValueType ( ) .


<s> static SDValue PerformVDUPLANECombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI ) { SDValue Op = N -> getOperand ( <NUM_LIT> ) ; if ( CombineVLDDUP ( N , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; while ( Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getOpcode ( ) != <STR_LIT> && Op . getOpcode ( )


<s> SDValue Concat0Op1 = Op0 . getOperand ( <NUM_LIT> ) ; SDValue Concat1Op1 = Op1 . getOperand ( <NUM_LIT> ) ; if ( Concat0Op1 . getOpcode ( ) != <STR_LIT> || Concat1Op1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! TLI . isTypeLegal ( VT ) || ! TLI . isTypeLegal ( Concat0Op1 . getValueType ( ) ) || ! TLI . isTypeLegal ( Concat1Op1 . getValueType ( ) ) ) return SDValue ( ) ; SDValue NewConcat = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 . getOperand ( <NUM_LIT> ) , Op1 . getOperand ( <NUM_LIT> ) ) ; SmallVector < int , <NUM_LIT> > NewMask ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned HalfElts = NumElts


<s> if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getNode ( ) == Op1 . getNode ( ) && Op0 . getResNo ( ) == <NUM_LIT> && Op1 . getResNo ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; return SDValue (


<s> if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getNode ( ) == Op1 . getNode ( ) && Op0 . getResNo ( ) == <NUM_LIT> && Op1 . getResNo ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; return SDValue ( )


<s> SDNode * InNode = InDouble . getNode ( ) ; if ( <STR_LIT> ( InNode ) && InNode -> hasOneUse ( ) && InNode -> getValueType ( <NUM_LIT> ) == <STR_LIT> && InNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && ! cast < LoadSDNode > ( InNode ) -> isVolatile ( ) ) { LoadSDNode * LD = cast < LoadSDNode > ( InNode ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( LD ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; SDValue NewLD1 = DAG . getLoad ( <STR_LIT> , DL , LD -> getChain ( ) , BasePtr , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue NewLD2 = DAG . getLoad ( <STR_LIT> , DL , NewLD1 . getValue ( <NUM_LIT> ) , OffsetPtr , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , std :: min ( <NUM_LIT> , LD -> getAlignment ( ) / <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , NewLD2 . getValue ( <NUM_LIT> ) ) ; if ( DCI . DAG . getTargetLoweringInfo ( ) . isBigEndian ( ) ) std :: swap ( NewLD1 , NewLD2 ) ; SDValue Result = DCI . CombineTo ( N , NewLD1 , NewLD2 ) ; DCI . RemoveFromWorklist ( LD ) ; DAG . DeleteNode ( LD ) ; return Result ; } return SDValue ( )


<s> SDLoc DL ( LD ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; SDValue NewLD1 = DAG . getLoad ( <STR_LIT> , DL , LD -> getChain ( ) , BasePtr , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue NewLD2 = DAG . getLoad ( <STR_LIT> , DL , NewLD1 . getValue ( <NUM_LIT> ) , OffsetPtr , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , std :: min ( <NUM_LIT> , LD -> getAlignment ( ) / <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , NewLD2 . getValue ( <NUM_LIT> ) ) ; if ( DCI . DAG . getTargetLoweringInfo ( ) . isBigEndian ( ) ) std :: swap ( NewLD1 , NewLD2 ) ; SDValue Result = DCI . CombineTo ( N , NewLD1 , NewLD2 ) ; DCI . RemoveFromWorklist ( LD ) ; DAG . DeleteNode (


<s> std :: swap ( N0 , N1 ) ; } if ( N0 == N1 ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue N00 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 -> getOperand ( <NUM_LIT> ) ; return DAG . getNode ( Opcode , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , N00 ,

N1 ) , DAG . getNode ( <STR_LIT> , DL , VT , N01 , N1 ) ) ;


<s> if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> ) { Opcode = N1 . getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> ) return SDValue ( ) ; std :: swap ( N0 , N1 ) ; } if ( N0 == N1 ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue N00 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 -> getOperand (


<s> static SDValue PerformXORCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; SelectionDAG & DAG = DCI .


<s> if ( MaxElts [ i ] - MinElts [ i ] >= NumElts ) { return SDValue ( ) ; } if ( MinElts [ i ] >= NumElts ) { VEXTOffsets [ i ] = NumElts ; ShuffleSrcs [ i ] = DAG . getNode ( <STR_LIT> , dl , VT , SourceVecs [ i ] , DAG . getIntPtrConstant ( NumElts ) ) ; } else if ( MaxElts [ i ] < NumElts ) { VEXTOffsets [ i ] = <NUM_LIT> ; ShuffleSrcs [ i ] = DAG . getNode ( <STR_LIT> , dl , VT , SourceVecs [ i ] , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else { VEXTOffsets [ i ] = MinElts [ i ] ; SDValue VEXTSrc1 = DAG . getNode ( <STR_LIT> , dl , VT , SourceVecs [ i ] , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue VEXTSrc2 = DAG . getNode ( <STR_LIT> , dl , VT , SourceVecs [ i ] , DAG . getIntPtrConstant ( NumElts ) ) ; ShuffleSrcs [ i ] = DAG . getNode ( <STR_LIT> , dl , VT , VEXTSrc1 , VEXTSrc2 , DAG . getConstant ( VEXTOffsets [ i ] , <STR_LIT> ) ) ; } } SmallVector < int , <NUM_LIT> > Mask ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue Entry = Op . getOperand ( i ) ; if ( Entry . getOpcode ( ) == <STR_LIT> ) { Mask . push_back ( - <NUM_LIT> ) ; continue ; } SDValue ExtractVec = Entry . getOperand ( <NUM_LIT> ) ; int ExtractElt = cast < ConstantSDNode > ( Op . getOperand ( i ) . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; if ( ExtractVec == SourceVecs [ <NUM_LIT> ] ) { Mask . push_back ( ExtractElt - VEXTOffsets [ <NUM_LIT> ] ) ; } else { Mask . push_back ( ExtractElt + NumElts - VEXTOffsets [ <NUM_LIT> ]


<s> void <ISA_LIT>TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { SDValue Res ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT>


<s> assert ( Ty -> isIntegerTy ( ) ) ; unsigned Bits = Ty -> getPrimitiveSizeInBits ( ) ; if ( Bits == <NUM_LIT> || Bits > <NUM_LIT> ) return false ; return


<s> bool IsMClass = Subtarget -> isMClass ( ) ; if ( StoreInst * SI = dyn_cast < StoreInst > ( Inst ) ) { unsigned Size = SI -> getValueOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return Size == <NUM_LIT> && ! IsMClass ; } else if ( LoadInst * LI = dyn_cast < LoadInst > ( Inst ) ) { return LI -> getType ( ) -> getPrimitiveSizeInBits ( ) == <NUM_LIT>


<s> SDNode * BVN = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; assert ( BVN -> getOpcode ( ) == <STR_LIT> && BVN -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; unsigned LowElt = DAG . getTargetLoweringInfo ( ) . isBigEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , BVN -> getOperand ( LowElt ) , BVN -> getOperand ( LowElt + <NUM_LIT> ) ) ; } assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumElts = VT . getVectorNumElements ( ) ; MVT TruncVT = <STR_LIT>


<s> if ( ExtendedTy == LD -> getMemoryVT ( ) ) return DAG . getLoad ( LD -> getMemoryVT ( ) , SDLoc ( LD ) , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ; return DAG . getExtLoad ( LD -> getExtensionType ( ) , SDLoc ( LD ) , ExtendedTy , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getPointerInfo ( ) , LD -> getMemoryVT ( )

, LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> getAlignment ( ) ) ;


<s> return DAG . getExtLoad ( LD -> getExtensionType ( ) , SDLoc ( LD ) , ExtendedTy , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getPointerInfo ( ) , LD ->

getMemoryVT ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> getAlignment ( ) ) ;


<s> } int FrameIndex = MFI -> CreateFixedObject ( ArgRegsSaveSize , Padding + ByValStoreOffset - ( int64_t ) TotalArgRegsSaveSize , false ) ; SDValue FIN = DAG . getFrameIndex ( FrameIndex , getPointerTy ( ) ) ; if ( Padding ) { MFI -> CreateFixedObject ( Padding , ArgOffset + ByValStoreOffset - ( int64_t ) ArgRegsSaveSize , false ) ; } SmallVector < SDValue , <NUM_LIT> > MemOps ; for ( unsigned i = <NUM_LIT> ; firstRegToSaveIndex < lastRegToSaveIndex ; ++ firstRegToSaveIndex , ++ i ) { const TargetRegisterClass * RC ; if ( AFI -> isThumb1OnlyFunction ( ) ) RC = & <STR_LIT> ; else RC = & <STR_LIT> ; unsigned VReg = MF . addLiveIn ( GPRArgRegs [ firstRegToSaveIndex ] , RC ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( OrigArg , OffsetFromOrigArg + <NUM_LIT> * i ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FIN , DAG . getConstant


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FrameIndex = StoreByValRegs ( CCInfo , DAG , dl , Chain , nullptr , CCInfo . getInRegsParamsCount ( ) , <NUM_LIT> , ArgOffset , <NUM_LIT> , ForceMutable , <NUM_LIT> , TotalArgRegsSaveSize ) ; AFI -> setVarArgsFrameIndex (


<s> int FrameIndex = StoreByValRegs ( CCInfo , DAG , dl , Chain , nullptr , CCInfo . getInRegsParamsCount ( ) , <NUM_LIT> , ArgOffset , <NUM_LIT> , ForceMutable , <NUM_LIT> , TotalArgRegsSaveSize ) ; AFI -> setVarArgsFrameIndex ( FrameIndex


<s> Opcode = <STR_LIT> ; Op0 = Mul . getOperand ( <NUM_LIT> ) ; Op1 = Mul . getOperand ( <NUM_LIT> ) ; } else if ( isS16 ( Mul . getOperand ( <NUM_LIT> ) , DAG ) && isSRA16 ( Mul . getOperand ( <NUM_LIT> ) ) ) { Opcode = <STR_LIT> ; Op0 = Mul . getOperand ( <NUM_LIT> ) ; Op1 = Mul . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; } else if ( isSRA16 ( Mul . getOperand ( <NUM_LIT> ) ) && isS16 ( Mul . getOperand ( <NUM_LIT> ) , DAG ) ) { Opcode = <STR_LIT> ; Op0 = Mul . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Op1 = Mul . getOperand ( <NUM_LIT> ) ; } else if ( isSRA16 ( Mul . getOperand ( <NUM_LIT> ) ) && isSRA16 ( Mul . getOperand ( <NUM_LIT> ) ) ) { Opcode = <STR_LIT> ; Op0 = Mul -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Op1 = Mul -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; } if ( ! Op0 || ! Op1 ) return SDValue ( ) ; SDValue SMLAL = DAG . getNode ( Opcode , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Op0 , Op1 , Lo , Hi ) ; SDValue HiMLALResult ( SMLAL . getNode ( ) , <NUM_LIT> ) ; SDValue LoMLALResult ( SMLAL . getNode ( ) , <NUM_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( AddcNode , <NUM_LIT> ) ,


<s> } setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; if ( VT . isInteger ( ) ) { setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } if ( VT . isInteger ( ) && VT != PromotedBitwiseVT ) { setOperationAction ( <STR_LIT> , VT , Promote ) ; AddPromotedToType ( <STR_LIT> , VT , PromotedBitwiseVT ) ; setOperationAction ( <STR_LIT> , VT , Promote ) ; AddPromotedToType ( <STR_LIT> , VT , PromotedBitwiseVT ) ; setOperationAction ( <STR_LIT> , VT , Promote ) ; AddPromotedToType ( <STR_LIT> , VT , PromotedBitwiseVT ) ; } setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT ,


<s> if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } return false ; } case <STR_LIT> : case <STR_LIT> : { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || Subtarget -> isLittle (


<s> } case <STR_LIT> : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : case <STR_LIT> : { EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } } case <STR_LIT> : { Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; ConstantSDNode * CI = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; const APInt & Mask = CI -> getAPIntValue ( ) ; Known . Zero &= Mask ; Known . One &= Mask ; return ; } case <STR_LIT> : case <STR_LIT> : { const SDValue & SrcSV = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = SrcSV . getValueType ( ) ; assert ( VecVT . isVector ( ) && <STR_LIT> ) ; const unsigned NumSrcElts = VecVT . getVectorNumElements ( ) ; ConstantSDNode * Pos = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; assert ( Pos -> getAPIntValue ( ) . ult ( NumSrcElts ) && <STR_LIT> ) ; unsigned Idx = Pos -> getZExtValue ( ) ; APInt DemandedElt = APInt :: getOneBitSet ( NumSrcElts , Idx ) ; Known = DAG . computeKnownBits ( SrcSV , DemandedElt , Depth + <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; const unsigned DstSz = VT . getScalarSizeInBits ( ) ; const unsigned SrcSz = VecVT . getVectorElementType ( ) .


<s> BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) . addExternalSymbol ( <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; } } BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlags ( MachineInstr :: FrameSetup ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; MI . eraseFromParent (


<s> unsigned OpNum = ( PFEntry >> <NUM_LIT> ) & <NUM_LIT> ; unsigned LHSID = ( PFEntry >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned RHSID = ( PFEntry >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; enum { OP_COPY = <NUM_LIT> , OP_VREV , OP_VDUP0 , OP_VDUP1 , OP_VDUP2 , OP_VDUP3 , OP_VEXT1 , OP_VEXT2 , OP_VEXT3 , OP_VUZPL , OP_VUZPR , OP_VZIPL , OP_VZIPR , OP_VTRNL , OP_VTRNR } ; if ( OpNum == OP_COPY ) { if ( LHSID == ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) return LHS ; assert ( LHSID == ( ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> && <STR_LIT> ) ; return RHS ; } SDValue OpLHS , OpRHS ; OpLHS = GeneratePerfectShuffle ( PerfectShuffleTable [ LHSID ] , LHS , RHS , DAG , dl ) ; OpRHS = GeneratePerfectShuffle ( PerfectShuffleTable [ RHSID ] , LHS , RHS , DAG , dl ) ; EVT VT = OpLHS . getValueType ( ) ; switch ( OpNum ) { default : llvm_unreachable ( <STR_LIT> ) ; case OP_VREV : if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; case OP_VDUP0


<s> return std :: min ( DL . getABITypeAlignment ( ArgTy ) , DL .


<s> if ( Subtarget -> isFPOnlySP ( ) && VT == <STR_LIT> ) { FalseVal = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , FalseVal ) ; TrueVal = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , TrueVal ) ; SDValue TrueLow = TrueVal . getValue ( <NUM_LIT> ) ; SDValue TrueHigh = TrueVal . getValue ( <NUM_LIT> ) ; SDValue FalseLow = FalseVal . getValue ( <NUM_LIT> ) ; SDValue FalseHigh = FalseVal . getValue ( <NUM_LIT> ) ; SDValue Low = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FalseLow , TrueLow , <ISA_LIT>cc , CCR , Cmp ) ; SDValue High = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FalseHigh , TrueHigh , <ISA_LIT>cc , CCR , duplicateCmp ( Cmp , DAG ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Low , High ) ; }


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function & F = MF . getFunction ( ) ; if ( ( ! IsMemset || ZeroMemset ) && Subtarget -> hasNEON ( ) &&

! F . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) {


<s> VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; isNonExt = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; isNonExt = ! ST -> isTruncatingStore ( ) ; } else return false ; if ( Subtarget -> isThumb1Only ( ) ) { assert ( Op -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; if ( Op -> getOpcode ( ) != <STR_LIT> || ! isNonExt ) return false ; auto * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHS || RHS -> getZExtValue ( ) != <NUM_LIT> ) return false ; Offset = Op -> getOperand ( <NUM_LIT> ) ; Base = Op -> getOperand ( <NUM_LIT> ) ; AM = <STR_LIT> ; return


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> SDValue C = DAG . getConstant ( InvalidOnQNaN , dl , <STR_LIT> ) ; if ( ! isFloatingPointZero ( RHS ) ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> if ( ! isFloatingPointZero ( RHS ) ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS , C ) ; else Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> void <ISA_LIT>TargetLowering :: insertCopiesSplitCSR ( MachineBasicBlock * Entry , const SmallVectorImpl < MachineBasicBlock * > & Exits ) const { const <ISA_LIT>BaseRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const MCPhysReg * IStart = TRI -> getCalleeSavedRegsViaCopy ( Entry -> getParent ( ) ) ; if ( ! IStart ) return ; const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; MachineRegisterInfo * MRI = & Entry -> getParent ( ) -> getRegInfo ( ) ; MachineBasicBlock :: iterator MBBI = Entry -> begin ( ) ; for ( const MCPhysReg * I = IStart ; * I ; ++ I ) { const TargetRegisterClass * RC = nullptr ; if ( <STR_LIT> . contains ( * I ) ) RC = & <STR_LIT> ; else if ( <STR_LIT> . contains ( * I ) ) RC = & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned NewVR = MRI -> createVirtualRegister ( RC ) ; assert ( Entry -> getParent ( ) -> getFunction ( ) . hasFnAttribute ( Attribute ::


<s> if ( Level == BeforeLegalizeTypes ) return true ; if ( Subtarget -> isThumb ( ) && Subtarget -> isThumb1Only ( ) ) return true ; if ( N -> getOpcode ( ) !=


<s> if ( CalleeCC != CallerCC ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } const <ISA_LIT>FunctionInfo * AFI_Caller = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI_Caller -> getArgRegsSaveSize ( ) ) return false ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , isVarArg ) ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , realArgIdx = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i , ++ realArgIdx ) { CCValAssign & VA = ArgLocs [ i ] ; EVT RegVT = VA . getLocVT ( ) ; SDValue Arg = OutVals [ realArgIdx ] ; <STR_LIT> Flags = Outs [ realArgIdx ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( VA . needsCustom ( )


<s> if ( VT == <STR_LIT> ) return <STR_LIT> ( Imm ) != - <NUM_LIT> ; if ( VT == <STR_LIT> && ! Subtarget -> isFPOnlySP ( ) ) return <STR_LIT> ( Imm ) != - <NUM_LIT> ; return


<s> if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } return SDValue ( ) ; case <NUM_LIT> : VT = is128Bits ? <STR_LIT> : <STR_LIT> ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( type == OtherModImm ) return SDValue ( ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } return SDValue ( ) ; case <NUM_LIT> : { if ( type != VMOVModImm ) return SDValue ( ) ; uint64_t BitMask = <NUM_LIT> ; uint64_t Val = <NUM_LIT> ; unsigned ImmMask = <NUM_LIT> ; Imm =


<s> if ( ! getVShiftImm ( Op , ElementBits , Cnt ) ) return false ; return ( Cnt >= <NUM_LIT> && ( isLong ? Cnt - <NUM_LIT> : Cnt )


<s> int64_t ElementBits = VT . getScalarSizeInBits ( ) ; if ( ! getVShiftImm ( Op , ElementBits , Cnt ) ) return false ; return ( Cnt >= <NUM_LIT> && ( isLong ? Cnt


<s> if ( ! isIntrinsic ) return ( Cnt >= <NUM_LIT> && Cnt <= ( isNarrow ? ElementBits / <NUM_LIT> : ElementBits ) ) ; if ( Cnt >= - ( isNarrow ? ElementBits / <NUM_LIT> : ElementBits ) && Cnt <= -


<s> unsigned Opc = LHS . getOpcode ( ) ; bool OptimizeMul = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ! Subtarget -> isThumb1Only ( ) ; if ( LHS . getResNo ( ) == <NUM_LIT> && ( isOneConstant ( RHS ) || isNullConstant ( RHS ) ) && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || OptimizeMul ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( LHS -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue Value , OverflowCmp ; SDValue <ISA_LIT>cc ; std :: tie ( Value , OverflowCmp ) = get<ISA_LIT>XALUOOp ( LHS . getValue ( <NUM_LIT> ) , DAG , <ISA_LIT>cc ) ; if ( ( CC == <STR_LIT> ) != isOneConstant ( RHS ) ) { <STR_LIT> CondCode = ( <STR_LIT> ) cast < const ConstantSDNode > ( <ISA_LIT>cc ) -> getZExtValue ( ) ; CondCode = <STR_LIT> ( CondCode ) ; <ISA_LIT>cc = DAG . getConstant ( CondCode , SDLoc ( <ISA_LIT>cc ) , <STR_LIT> ) ; } SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , OverflowCmp ) ; } if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue


<s> if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } if ( getTargetMachine ( ) . Options . UnsafeFPMath && ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue Result = OptimizeVFPBrcond ( Op , DAG ) ) return Result ; } <STR_LIT> CondCode , CondCode2 ; bool InvalidOnQNaN ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 , InvalidOnQNaN ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl , InvalidOnQNaN ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Dest , <ISA_LIT>cc , CCR , Cmp } ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , VTList , Ops ) ; if ( CondCode2 != <STR_LIT> ) { <ISA_LIT>cc = DAG . getConstant ( CondCode2 , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Res , Dest , <ISA_LIT>cc , CCR , Res . getValue ( <NUM_LIT> ) } ; Res = DAG . getNode ( <STR_LIT> , dl , VTList


<s> if ( ! Op0 . isUndef ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; if ( ! Op1 . isUndef ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op1 ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType


<s> default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : { SDValue Lo = DAG . getConstant ( INTVal . trunc ( <NUM_LIT> ) , DL , <STR_LIT> ) ; SDValue Hi = DAG . getConstant ( INTVal . lshr ( <NUM_LIT> ) . trunc ( <NUM_LIT> ) , DL , <STR_LIT> ) ; if ( ! ST -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ; } case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( INTVal , DL , <STR_LIT> ) ) ; } } if ( ! ST -> hasVFP3 ( ) ) return SDValue ( ) ; if ( IsDouble && Subtarget -> isFPOnlySP ( ) ) return SDValue ( ) ; int ImmVal = IsDouble ? <STR_LIT> ( FPVal ) : <STR_LIT> ( FPVal ) ; if ( ImmVal != - <NUM_LIT> ) { if ( IsDouble || ! ST -> useNEONForSinglePrecisionFP ( ) ) { return Op ; } SDLoc DL ( Op ) ; SDValue NewVal = DAG . getTargetConstant ( ImmVal , DL , <STR_LIT> ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewVal ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } if ( ! ST -> hasNEON ( ) || ( ! IsDouble && ! ST -> useNEONForSinglePrecisionFP ( ) ) ) return SDValue ( ) ; EVT VMovVT ; uint64_t iVal = FPVal . bitcastToAPInt ( ) . getZExtValue ( ) ; if ( IsDouble && ( iVal & <NUM_LIT> ) != ( iVal >> <NUM_LIT> ) ) return SDValue ( ) ; SDValue NewVal = isNEONModifiedImm ( iVal & <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , DAG , SDLoc ( Op ) , VMovVT , false , VMOVModImm ) ; if ( NewVal != SDValue ( ) ) { SDLoc DL ( Op ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , VMovVT , NewVal ) ; if ( IsDouble ) return DAG . getNode ( <STR_LIT> , DL


<s> if ( IsDouble || ! ST -> useNEONForSinglePrecisionFP ( ) ) { return Op ; } SDLoc DL ( Op ) ; SDValue NewVal = DAG . getTargetConstant ( ImmVal , DL , <STR_LIT> ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewVal ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } if ( ! ST -> hasNEON ( ) || ( ! IsDouble && ! ST -> useNEONForSinglePrecisionFP ( ) ) ) return SDValue ( ) ; EVT VMovVT ; uint64_t iVal = FPVal . bitcastToAPInt ( ) . getZExtValue ( ) ; if ( IsDouble && ( iVal & <NUM_LIT> ) != ( iVal >> <NUM_LIT> ) ) return SDValue ( ) ; SDValue NewVal = isNEONModifiedImm ( iVal & <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , DAG , SDLoc ( Op ) , VMovVT , false , VMOVModImm ) ; if ( NewVal != SDValue ( ) ) { SDLoc DL ( Op ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , VMovVT , NewVal ) ; if ( IsDouble ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant ) ; SDValue VecFConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecFConstant , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } NewVal = isNEONModifiedImm ( ~ iVal & <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , DAG , SDLoc ( Op ) , VMovVT , false , VMVNModImm ) ; if ( NewVal != SDValue ( ) ) { SDLoc DL ( Op ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , VMovVT , NewVal ) ; if ( IsDouble ) return DAG . getNode ( <STR_LIT>


<s> SDValue WidthMinus1 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant ( NumBits - <NUM_LIT> , dl , ElemTy ) ) ; SDValue CTLZ = DAG . getNode ( <STR_LIT> , dl , VT , LSB ) ; return DAG . getNode ( <STR_LIT> , dl , VT , WidthMinus1 , CTLZ ) ; } SDValue Bits ; if ( ElemTy == <STR_LIT> ) { SDValue FF = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Bits = DAG . getNode ( <STR_LIT> , dl , VT , LSB , FF ) ; } else { SDValue One = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant ( <NUM_LIT> , dl , ElemTy ) ) ; Bits = DAG . getNode ( <STR_LIT> , dl , VT , LSB


<s> if ( Op . getValueType ( ) == <STR_LIT> && Vec . getScalarValueSizeInBits ( ) < <NUM_LIT> ) { SDLoc dl ( Op ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Lane ) ; } return


<s> SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> && Vec . getScalarValueSizeInBits ( ) < <NUM_LIT> ) { SDLoc dl ( Op ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Lane


<s> EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned FrameReg = ARI . getFrameRegister ( MF ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode


<s> unsigned FrameReg = ARI . getFrameRegister ( MF ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) ) ; return


<s> assert ( ! Subtarget -> isROPI ( ) && ! Subtarget -> isRWPI ( ) && <STR_LIT> ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc dl ( Op ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; if ( Subtarget -> useMovt ( DAG . getMachineFunction ( ) ) ) ++ NumMovwMovt ; unsigned Wrapper = isPositionIndependent ( ) ? <STR_LIT> : <STR_LIT> ; SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getNode ( Wrapper


<s> <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; RelAddr = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; } SDValue SB = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , PtrVT ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , SB , RelAddr ) ; return Result ; } if ( Subtarget -> useMovt ( DAG . getMachineFunction ( ) ) ) { ++ NumMovwMovt ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; } else { SDValue CPAddr = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG .


<s> SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , G ) ; return Result ; } else if ( Subtarget -> isRWPI ( ) && ! IsRO ) { SDValue RelAddr ; if ( Subtarget -> useMovt ( DAG . getMachineFunction ( ) ) ) { ++ NumMovwMovt ; SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; RelAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , G ) ; } else { <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; RelAddr = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( )

, CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalTLSAddressWindows ( SDValue Op , SelectionDAG & DAG ) const { assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; SDValue Chain = DAG . getEntryNode ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc DL ( Op ) ; SDValue Ops [ ] = { Chain , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) } ; SDValue CurrentTEB = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; SDValue TEB = CurrentTEB . getValue ( <NUM_LIT> ) ; Chain = CurrentTEB . getValue ( <NUM_LIT> ) ; SDValue TLSArray = DAG . getNode ( <STR_LIT> , DL , PtrVT , TEB , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; TLSArray = DAG . getLoad ( PtrVT , DL , Chain , TLSArray , MachinePointerInfo ( ) ) ; SDValue TLSIndex = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; TLSIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex ) ; TLSIndex = DAG . getLoad ( PtrVT , DL , Chain , TLSIndex


<s> SDLoc DL ( Op ) ; SDValue Ops [ ] = { Chain , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) } ; SDValue CurrentTEB = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; SDValue TEB = CurrentTEB . getValue ( <NUM_LIT> ) ; Chain = CurrentTEB . getValue ( <NUM_LIT> ) ; SDValue TLSArray = DAG . getNode ( <STR_LIT> , DL , PtrVT , TEB , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; TLSArray = DAG . getLoad ( PtrVT , DL , Chain , TLSArray , MachinePointerInfo ( ) ) ; SDValue TLSIndex = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; TLSIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex ) ; TLSIndex = DAG . getLoad ( PtrVT , DL , Chain , TLSIndex , MachinePointerInfo ( ) ) ; SDValue Slot = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue TLS = DAG . getLoad ( PtrVT , DL , Chain , DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSArray , Slot ) , MachinePointerInfo ( ) ) ; const auto * GA = cast < GlobalAddressSDNode > ( Op ) ; auto * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal


<s> if ( LoadCount > <NUM_LIT> ) BaseAddr = Builder . CreateConstGEP1_32 ( BaseAddr , VecTy -> getVectorNumElements ( ) * Factor ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , Int8Ptr ) ) ; Ops . push_back ( Builder . getInt32 ( LI -> getAlignment ( ) ) ) ; CallInst * VldN = Builder . CreateCall ( VldnFunc , Ops , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < Shuffles . size ( ) ; i ++ ) { ShuffleVectorInst * SV = Shuffles [ i ] ; unsigned Index = Indices [ i ] ; Value * SubVec = Builder . CreateExtractValue ( VldN , Index ) ; if ( EltTy -> isPointerTy ( ) ) SubVec = Builder . CreateIntToPtr ( SubVec , VectorType :: get ( SV -> getType ( ) -> getVectorElementType ( ) , VecTy -> getVectorNumElements ( ) ) ) ; SubVecs [ SV ] . push_back ( SubVec ) ; } } for ( ShuffleVectorInst * SVI : Shuffles ) { auto & SubVec = SubVecs [


<s> if ( EltTy -> isPointerTy ( ) ) { Type * IntTy = DL . getIntPtrType ( EltTy ) ; Type * IntVecTy = VectorType :: get ( IntTy , Op0 -> getType ( ) -> getVectorNumElements ( ) ) ; Op0 = Builder . CreatePtrToInt ( Op0 , IntVecTy ) ; Op1 = Builder . CreatePtrToInt ( Op1 , IntVecTy ) ; SubVecTy = VectorType :: get ( IntTy , LaneLen ) ; } Value * BaseAddr = SI -> getPointerOperand ( ) ; if ( NumStores > <NUM_LIT> ) { LaneLen /= NumStores ; SubVecTy = VectorType :: get ( SubVecTy -> getVectorElementType ( ) , LaneLen ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , SubVecTy -> getVectorElementType ( ) -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ) ; } assert ( isTypeLegal ( EVT :: getEVT ( SubVecTy ) ) && <STR_LIT> ) ; auto Mask = SVI -> getShuffleMask ( ) ; Type * Int8Ptr = Builder . getInt8PtrTy ( SI -> getPointerAddressSpace ( ) ) ; Type * Tys [ ] = { Int8Ptr , SubVecTy } ; static const <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; for ( unsigned StoreCount = <NUM_LIT> ; StoreCount < NumStores ; ++ StoreCount ) { if ( StoreCount > <NUM_LIT> ) BaseAddr = Builder . CreateConstGEP1_32 ( BaseAddr , LaneLen * Factor ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , Int8Ptr ) ) ; Function * VstNFunc = <STR_LIT> ( SI -> getModule ( ) , StoreInts [ Factor - <NUM_LIT> ] , Tys ) ; for ( unsigned i = <NUM_LIT> ; i < Factor ; i


<s> case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op ,


<s> if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) == <STR_LIT> ) { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { CC = <STR_LIT> ( CC , true ) ; std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; bool InvalidOnQNaN ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 , InvalidOnQNaN ) ; if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ! isFloatingPointZero ( RHS ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { bool swpCmpOps = false ; bool swpVselOps = false ; checkVSELConstraints ( CC , CondCode , swpCmpOps , swpVselOps ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { if ( swpCmpOps ) std :: swap


<s> N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , N0 ) ; return N0 ; } N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; SDValue BN1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , BN1 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , BN1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , BN1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0


<s> const char * <ISA_LIT>TargetLowering :: LowerXConstraint ( EVT ConstraintVT ) const { if ( ! Subtarget -> hasVFP2 ( ) ) return <STR_LIT> ; if ( ConstraintVT . isFloatingPoint ( ) ) return <STR_LIT> ; if ( ConstraintVT . isVector ( ) && Subtarget -> hasNEON ( ) && ( ConstraintVT . getSizeInBits ( ) == <NUM_LIT> || ConstraintVT . getSizeInBits ( ) == <NUM_LIT> ) ) return <STR_LIT> ; return <STR_LIT>


<s> if ( ! Flags . isByVal ( ) ) { if ( ! TII -> isLoadFromStackSlot ( * Def , FI ) ) return false ; } else { return false ; } } else if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Arg ) ) { if ( Flags . isByVal ( ) ) return false ; SDValue Ptr = Ld -> getBasePtr ( ) ; FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ; if ( ! FINode ) return


<s> SDValue Vbic = DAG . getNode ( <STR_LIT> , dl , VbicVT , Input , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vbic ) ; } } } if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , true , DCI ) ) return Result ; if ( SDValue Result = PerformSHLSimplify ( N , DCI , Subtarget ) ) return Result ; } if ( Subtarget -> isThumb1Only ( ) ) if ( SDValue Result = CombineANDShift ( N , DCI , Subtarget ) ) return Result ; return SDValue ( )


<s> auto * LHS0C = dyn_cast < ConstantSDNode > ( LHS -> getOperand ( <NUM_LIT> ) ) ; auto * LHS1C = dyn_cast < ConstantSDNode > ( LHS -> getOperand ( <NUM_LIT> ) ) ; auto * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ; if ( ( LHS0C && LHS0C -> getZExtValue ( ) == <NUM_LIT> ) && ( LHS1C && LHS1C -> getZExtValue ( ) == <NUM_LIT> ) && ( RHSC && RHSC -> getZExtValue ( ) == <NUM_LIT> ) ) { return DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , LHS -> getOperand ( <NUM_LIT> ) , LHS -> getOperand ( <NUM_LIT> ) , LHS -> getOperand ( <NUM_LIT> ) ) ; } } if ( ! VT . isInteger ( ) ) return SDValue ( ) ; if ( isNullConstant ( FalseVal ) ) { if ( CC == <STR_LIT> && isOneConstant ( TrueVal ) ) { if ( ! Subtarget -> isThumb1Only ( ) && Subtarget -> hasV5TOps ( ) ) { SDValue Sub = DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Sub ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } else { SDValue Sub = DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; SDValue Neg = DAG . getNode ( <STR_LIT> , dl , VTs , FalseVal , Sub ) ; SDValue Carry = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , Neg . getValue ( <NUM_LIT> ) ) ; Res = DAG . getNode ( <STR_LIT> , dl , VTs , Sub , Neg , Carry ) ; } } else if ( CC == <STR_LIT> && ! isNullConstant ( RHS ) && ( ! Subtarget -> isThumb1Only ( ) || isPowerOf2Constant ( TrueVal ) ) ) { SDValue Sub = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , <STR_LIT> ) , LHS , RHS ) ; SDValue CPSRGlue = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl

, <STR_LIT> , Sub . getValue ( <NUM_LIT> ) , SDValue ( ) ) ;


<s> if ( St -> isVolatile ( ) ) return SDValue ( ) ; SDValue StVal = St -> getValue ( ) ; EVT VT = StVal . getValueType ( ) ; if ( St -> isTruncatingStore ( ) && VT . isVector ( ) ) { SelectionDAG & DAG = DCI . DAG ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT StVT = St -> getMemoryVT ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; assert ( StVT != VT && <STR_LIT> ) ; unsigned FromEltSz = VT . getScalarSizeInBits ( ) ; unsigned ToEltSz = StVT . getScalarSizeInBits ( ) ; if ( ! isPowerOf2_32 ( NumElems * FromEltSz * ToEltSz ) ) return SDValue ( ) ; if ( <NUM_LIT> != ( NumElems * FromEltSz ) % ToEltSz ) return SDValue ( ) ; unsigned SizeRatio = FromEltSz / ToEltSz ; assert ( SizeRatio * NumElems * ToEltSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDLoc DL ( St ) ; SDValue WideVec = DAG . getNode ( <STR_LIT> , DL , WideVecVT , StVal ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) ShuffleVec [ i ] = DAG . getDataLayout ( ) . isBigEndian ( ) ? ( i + <NUM_LIT> ) * SizeRatio - <NUM_LIT> : i * SizeRatio ; if ( ! TLI . isTypeLegal ( WideVecVT ) ) return SDValue ( ) ; SDValue Shuff = DAG . getVectorShuffle ( WideVecVT , DL , WideVec , DAG . getUNDEF ( WideVec . getValueType ( ) ) , ShuffleVec ) ; MVT StoreType = <STR_LIT> ; for ( MVT Tp : <STR_LIT> ( ) ) { if ( TLI . isTypeLegal ( Tp ) && Tp . getSizeInBits ( ) <= NumElems * ToEltSz ) StoreType = Tp ; } if ( ! TLI . isTypeLegal ( StoreType ) ) return SDValue ( ) ; EVT StoreVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StoreType ,

VT . getSizeInBits ( ) / EVT ( StoreType ) . getSizeInBits ( ) ) ;


<s> uint32_t IntBits = IntTy . getSizeInBits ( ) ; unsigned NumLanes = Op . getValueType ( ) . getVectorNumElements ( ) ; if ( FloatBits != <NUM_LIT> || IntBits > <NUM_LIT> || NumLanes > <NUM_LIT> ) { return SDValue ( ) ; } BitVector UndefElements ; BuildVectorSDNode * BV = cast < BuildVectorSDNode > ( ConstVec ) ; int32_t C = BV -> getConstantFPSplatPow2ToLog2Int ( & UndefElements , <NUM_LIT> ) ; if ( C == - <NUM_LIT> || C == <NUM_LIT> || C > <NUM_LIT> ) return SDValue ( ) ; SDLoc dl ( N ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> ; unsigned IntrinsicOpcode = isSigned ? <STR_LIT> : <STR_LIT> ; SDValue FixConv = DAG . getNode ( <STR_LIT> , dl , NumLanes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> , DAG . getConstant ( IntrinsicOpcode , dl , <STR_LIT> ) , Op -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( C , dl , <STR_LIT> ) ) ; if ( IntBits < FloatBits ) FixConv = DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , FixConv ) ; return