<s> if ( ShOpcVal == <STR_LIT> ) return false ; BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ; ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! RHS )


<s> if ( Kind != InlineAsm :: Kind_RegUse && Kind != InlineAsm :: Kind_RegDef && Kind != InlineAsm :: Kind_RegDefEarlyClobber ) continue ; unsigned RC ; bool HasRC = InlineAsm :: hasRegClassConstraint ( Flag , RC ) ; if ( ( ! IsTiedToChangedOp && ( ! HasRC || RC != <STR_LIT> ) ) || NumRegs != <NUM_LIT> ) continue ; assert ( ( i + <NUM_LIT> < NumOps ) && <STR_LIT> ) ; SDValue V0 = N -> getOperand ( i + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( i + <NUM_LIT> ) ; unsigned Reg0 = cast < RegisterSDNode > ( V0 ) -> getReg ( ) ; unsigned Reg1 = cast < RegisterSDNode > ( V1 ) -> getReg ( ) ; SDValue PairedReg ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; if ( Kind == InlineAsm :: Kind_RegDef || Kind == InlineAsm :: Kind_RegDefEarlyClobber ) { unsigned GPVR = MRI . createVirtualRegister ( & <STR_LIT> ) ; PairedReg = CurDAG -> getRegister ( GPVR , <STR_LIT> ) ; SDValue Chain = SDValue ( N , <NUM_LIT> ) ; SDNode * GU = N -> getGluedUser ( ) ; SDValue RegCopy = CurDAG -> getCopyFromReg ( Chain , dl , GPVR , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ; SDValue Sub0 = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , RegCopy ) ; SDValue Sub1 = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , RegCopy ) ; SDValue T0 = CurDAG -> getCopyToReg ( Sub0 , dl , Reg0 , Sub0 , RegCopy . getValue ( <NUM_LIT> ) ) ; SDValue T1 = CurDAG -> getCopyToReg ( Sub1 , dl , Reg1 , Sub1 , T0 . getValue ( <NUM_LIT> ) ) ; std :: vector < SDValue > Ops ( GU -> op_begin ( ) , GU -> op_end ( ) - <NUM_LIT> ) ; Ops . push_back ( T1 . getValue ( <NUM_LIT> ) ) ; CurDAG -> UpdateNodeOperands ( GU , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; GU = T1 . getNode ( ) ; } else { SDValue Chain = AsmNodeOperands [ InlineAsm :: Op_InputChain ] ; SDValue T0 = CurDAG -> getCopyFromReg ( Chain , dl , Reg0 , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ; SDValue T1 = CurDAG -> getCopyFromReg ( Chain , dl , Reg1 , <STR_LIT> , T0 . getValue ( <NUM_LIT> ) ) ; SDValue Pair = SDValue ( createGPRPairNode ( <STR_LIT> , T0 , T1 ) , <NUM_LIT> ) ; unsigned GPVR = MRI . createVirtualRegister ( &


<s> SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { assert ( ConstraintCode == 'm' && <STR_LIT> ) ; OutOps . push_back ( Op ) ; return


<s> } } if ( N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> && ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; if ( N . getOpcode ( ) == <STR_LIT> || N . getOpcode ( ) == <STR_LIT> ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) return false ; } <STR_LIT> AddSub = N . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( Offset , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } if ( N . getOpcode ( ) != <STR_LIT> && ShOpcVal == <STR_LIT> && ! ( Subtarget -> isLikeA9 ( ) || Subtarget -> isSwift ( ) || N . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) { ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( N . getOperand ( <NUM_LIT> ) , ShOpcVal , ShAmt ) ) { Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Base = N . getOperand ( <NUM_LIT> ) ; } else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , ShAmt , ShOpcVal ) , <STR_LIT> ) ; return true


<s> BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ; ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( RHS ) return false ; ShReg = N . getOperand ( <NUM_LIT> ) ; if ( CheckProfitability && ! isShifterOpProfitable ( N , ShOpcVal , ShImmVal ) )


<s> bool SelectShiftRegShifterOperand ( SDValue N , SDValue & A , SDValue & B , SDValue


<s> Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC /


<s> if ( ! RHS ) return true ; uint32_t RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( RHSC > <NUM_LIT> || RHSC % <NUM_LIT> != <NUM_LIT> ) return true ; Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) ->


<s> if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) return false ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { if ( SelectT2AddrModeImm8 ( N , Base , OffImm ) ) return false ; int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ; return true ; } } Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true


<s> unsigned Opcode = Op -> getOpcode ( ) ; <STR_LIT> AM = ( Opcode == <STR_LIT> ) ? cast < LoadSDNode > ( Op ) -> getAddressingMode ( ) : cast < StoreSDNode > ( Op ) -> getAddressingMode ( ) ; int RHSC ; if ( isScaledConstantInRange ( N , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , RHSC ) ) { OffImm = ( ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ) ? CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) : CurDAG ->

getTargetConstant ( - RHSC , <STR_LIT> ) ;


<s> int RHSC ; if ( isScaledConstantInRange ( N , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , RHSC ) ) { OffImm = ( ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ) ? CurDAG -> getTargetConstant ( RHSC

, <STR_LIT> ) : CurDAG -> getTargetConstant ( - RHSC , <STR_LIT> ) ;


<s> unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; OffReg = N . getOperand ( <NUM_LIT> ) ; <STR_LIT> ShOpcVal = <STR_LIT> ( OffReg . getOpcode ( ) ) ; if ( ShOpcVal != <STR_LIT> ) { ShOpcVal = <STR_LIT> ( Base . getOpcode ( ) ) ; if ( ShOpcVal == <STR_LIT> ) std :: swap ( Base , OffReg ) ; } if ( ShOpcVal == <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( OffReg . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( ShAmt < <NUM_LIT> && isShifterOpProfitable ( OffReg , ShOpcVal , ShAmt ) ) OffReg = OffReg . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } ShImm = CurDAG -> getTargetConstant ( ShAmt , <STR_LIT> ) ; return true


<s> switch ( LoadedVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; default : return NULL ; } Match = true ; } if ( Match ) { SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ; SDValue Ops [ ] = { Base , Offset , getAL ( CurDAG ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT>


<s> if ( ShOpcVal == <STR_LIT> ) return false ; BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { ShImmVal = RHS -> getZExtValue ( ) & <NUM_LIT> ; Opc = getI32Imm ( <STR_LIT> ( ShOpcVal , ShImmVal ) ) ; return


<s> if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; } else { Base = N ; } OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } RegisterSDNode * LHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; RegisterSDNode * RHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ( LHSR && LHSR -> getReg ( ) == <STR_LIT> ) || ( RHSR && RHSR -> getReg ( ) == <STR_LIT> ) ) { ConstantSDNode * LHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; unsigned LHSC = LHS ? LHS -> getZExtValue ( ) : <NUM_LIT> ; unsigned RHSC = RHS ? RHS -> getZExtValue


<s> return SelectThumbAddrModeImm5S ( N , <NUM_LIT>


<s> return SelectThumbAddrModeImm5S ( N , <NUM_LIT> , Base ,


<s> if ( SelectThumbAddrModeSP ( N , TmpBase , TmpOffImm ) ) return false ; if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; RegisterSDNode * LHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; RegisterSDNode * RHSR = dyn_cast < RegisterSDNode > ( N


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeRI5S1 ( SDValue N , SDValue & Base , SDValue & Offset ) { return SelectThumbAddrModeRI ( N , Base , Offset ,


<s> return SelectThumbAddrModeRI ( N , Base


<s> return SelectThumbAddrModeRI ( N , Base ,


<s> return SelectThumbAddrModeRI ( N , Base , Offset , <NUM_LIT>


<s> <STR_LIT> ShOpcVal = <STR_LIT> ( <STR_LIT> ) ; SDValue ShOpc = CurDAG -> getTargetConstant ( <STR_LIT> ( ShOpcVal , LSB ) , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , ShOpc , getAL ( CurDAG ) , Reg0 , Reg0 } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) ; } SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( LSB , <STR_LIT> ) , CurDAG -> getTargetConstant ( Width , <STR_LIT> ) , getAL ( CurDAG ) , Reg0 } ; return CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , Ops , <NUM_LIT> ) ; } } return NULL ; } unsigned Shl_imm = <NUM_LIT> ; if ( isOpcWithIntImmediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , Shl_imm ) ) { assert ( Shl_imm > <NUM_LIT> && Shl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Srl_imm = <NUM_LIT> ; if ( isInt32Immediate ( N -> getOperand ( <NUM_LIT> ) , Srl_imm ) ) { assert ( Srl_imm > <NUM_LIT> && Srl_imm <


<s> if ( ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( Inc ) ; else if ( NumVecs > <NUM_LIT> ) Ops . push_back ( Reg0 ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; std :: vector < EVT > ResTys ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDNode * VLdDup = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; cast < MachineSDNode > ( VLdDup ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; SuperReg = SDValue ( VLdDup , <NUM_LIT> ) ; assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> && <STR_LIT> ) ; unsigned SubIdx = <STR_LIT> ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) ReplaceUses ( SDValue ( N , Vec ) , CurDAG -> getTargetExtractSubreg ( SubIdx + Vec , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( VLdDup , <NUM_LIT> ) ) ; if ( isUpdating ) ReplaceUses ( SDValue ( N , NumVecs + <NUM_LIT> ) , SDValue ( VLdDup


<s> if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; } Align = CurDAG -> getTargetConstant ( Alignment , <STR_LIT> ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } std :: vector < EVT > ResTys ; if ( IsLoad ) { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } SDValue SuperReg ; SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) { if ( is64BitVector ) SuperReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; } else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( is64BitVector ) SuperReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQuadQRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } Ops . push_back ( SuperReg ) ; Ops . push_back ( getI32Imm ( Lane ) ) ; Ops . push_back ( Pred ) ; Ops . push_back (


<s> SDValue V0 = N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) RegSeq = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else { SDValue V2 = N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; RegSeq = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) ,


<s> const ConstantSDNode * RotConstant = dyn_cast < ConstantSDNode > ( V ) ; assert ( RotConstant && <STR_LIT>


<s> assert ( ( Value == <NUM_LIT> || Value == <NUM_LIT> ) && <STR_LIT> ) ; return Value


<s> assert ( ( Value == <NUM_LIT> || Value == <NUM_LIT> ) && <STR_LIT> ) ; return


<s> else if ( MemTy == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( MemTy == <STR_LIT> ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * CmpSwap = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) , Ops ) ; MachineMemOperand * MemOp = cast < MemSDNode > ( N )


<s> int FirstInputOp = Predicated ? <NUM_LIT> : <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( FirstInputOp ) ) ; Ops . push_back ( N -> getOperand ( FirstInputOp + <NUM_LIT> ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( IsAngle270 , Loc , <STR_LIT> ) ) ; if ( Predicated ) AddMVEPredicateToOps ( Ops , Loc , N -> getOperand ( FirstInputOp + <NUM_LIT> ) , N -> getOperand ( FirstInputOp - <NUM_LIT> ) ) ; else AddEmptyMVEPredicateToOps ( Ops , Loc , VT ) ; CurDAG -> SelectNodeTo ( N , Opcode , N -> getVTList (


<s> uint32_t RotValue = GetCMulRotation ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( RotValue , Loc , <STR_LIT> ) ) ; if ( Predicated ) AddMVEPredicateToOps ( Ops , Loc , N -> getOperand ( <NUM_LIT> ) ) ; else AddEmptyMVEPredicateToOps ( Ops , Loc ) ; EVT VT = N -> getValueType (


<s> int FirstInputOp = Predicated ? <NUM_LIT> : <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( FirstInputOp ) ) ; Ops . push_back ( N -> getOperand ( FirstInputOp + <NUM_LIT> ) ) ; uint32_t RotValue = GetCMulRotation ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( RotValue , Loc , <STR_LIT> ) ) ; if ( Predicated ) AddMVEPredicateToOps ( Ops , Loc , N -> getOperand ( FirstInputOp + <NUM_LIT> ) , N -> getOperand ( FirstInputOp - <NUM_LIT> ) ) ; else AddEmptyMVEPredicateToOps ( Ops , Loc , VT ) ; uint16_t Opcode = SelectFPOpcode ( VT ,


<s> int FirstInputOp = Predicated ? <NUM_LIT> : <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( FirstInputOp ) ) ; Ops . push_back ( N -> getOperand ( FirstInputOp + <NUM_LIT> ) ) ; uint32_t RotValue = GetCMulRotation ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( RotValue , Loc , <STR_LIT> ) ) ; if ( Predicated ) AddMVEPredicateToOps ( Ops , Loc , N -> getOperand ( FirstInputOp + <NUM_LIT> ) , N -> getOperand ( FirstInputOp - <NUM_LIT> ) ) ; else AddEmptyMVEPredicateToOps ( Ops , Loc , VT ) ; uint16_t Opcode = SelectFPOpcode ( VT , OpcodeF16


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc Loc ( N ) ; const uint16_t * OurOpcodes ; switch ( VT . getVectorElementType ( ) . getSizeInBits ( ) ) { case <NUM_LIT> : OurOpcodes = Opcodes [ <NUM_LIT> ] ; break ; case <NUM_LIT> : OurOpcodes = Opcodes [ <NUM_LIT> ] ; break ; case <NUM_LIT> : OurOpcodes = Opcodes [ <NUM_LIT> ] ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } EVT DataTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , NumVecs * <NUM_LIT> ) ; EVT ResultTys [ ] = { DataTy , <STR_LIT> } ; auto Data = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , Loc , DataTy ) , <NUM_LIT> ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; for ( unsigned Stage = <NUM_LIT> ; Stage < NumVecs ; ++ Stage ) { SDValue Ops [ ] = { Data , N -> getOperand ( <NUM_LIT> ) , Chain } ; auto LoadInst = CurDAG -> getMachineNode ( OurOpcodes [ Stage ] , Loc , ResultTys , Ops ) ; Data = SDValue ( LoadInst , <NUM_LIT> ) ; Chain = SDValue ( LoadInst , <NUM_LIT> ) ; } for ( unsigned i = <NUM_LIT> ; i < NumVecs ; i ++ ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( <STR_LIT> + i , Loc , VT , Data ) ) ; ReplaceUses ( SDValue ( N ,


<s> void <ISA_LIT>DAGToDAGISel :: SelectMVE_WB ( SDNode * N , const uint16_t * Opcodes , bool Predicated ) { SDLoc Loc ( N ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; uint16_t Opcode ; switch ( N -> getValueType ( <NUM_LIT> ) . getVectorElementType ( ) . getSizeInBits ( ) ) { case <NUM_LIT> : Opcode = Opcodes [ <NUM_LIT> ] ; break ; case <NUM_LIT> : Opcode = Opcodes


<s> if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; if ( RHSC * <NUM_LIT> < MFI . getObjectSize ( FI ) ) { if ( ! MFI . isFixedObjectIndex ( FI ) && MFI . getObjectAlignment ( FI ) < <NUM_LIT> ) MFI . setObjectAlignment ( FI , <NUM_LIT> ) ; if ( MFI . getObjectAlignment ( FI ) >= <NUM_LIT> ) { Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy (


<s> Alignment = ( Alignment & - Alignment ) ; if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; } Align = CurDAG -> getTargetConstant ( Alignment , dl , <STR_LIT> ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } std :: vector < EVT > ResTys ; if ( IsLoad ) { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT . getVectorElementType ( ) , NumVecs ) ; Ops . push_back ( IsImmUpdate ? Reg0 : Inc ) ; } SDValue SuperReg ; SDValue V0 = N -> getOperand ( Vec0Idx +


<s> if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } else if ( Align >= <NUM_LIT> && ( CanChangeType || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else if ( Align >= <NUM_LIT> && ( CanChangeType || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else if ( ( CanChangeType || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else return false ; SDValue Ops [ ] = { Base , NewOffset , CurDAG -> getTargetConstant ( Pred , SDLoc ( N ) , <STR_LIT> ) , PredReg , Chain } ; SDNode * New = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , Ops ) ; transferMemOperands ( N , New ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( New , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( New , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( New , <NUM_LIT> ) ) ; CurDAG -> RemoveDeadNode ( N


<s> bool isSExtLd , isPre ; unsigned Align ; <STR_LIT> Pred ; SDValue PredReg ; SDValue Chain , Base , Offset ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { <STR_LIT> AM = LD -> getAddressingMode ( ) ; if ( AM == <STR_LIT> ) return false ; LoadedVT = LD -> getMemoryVT ( ) ; if ( ! LoadedVT . isVector ( ) ) return false ; Chain = LD -> getChain ( ) ; Base = LD -> getBasePtr ( ) ; Offset = LD -> getOffset ( ) ; Align = LD -> getAlignment ( ) ; isSExtLd = LD -> getExtensionType ( ) == <STR_LIT> ; isPre = ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ; Pred = <STR_LIT> ; PredReg = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; } else if ( MaskedLoadSDNode * LD = dyn_cast < MaskedLoadSDNode > ( N ) ) { <STR_LIT> AM = LD -> getAddressingMode ( ) ; if ( AM == <STR_LIT> ) return false ; LoadedVT = LD -> getMemoryVT ( ) ; if ( ! LoadedVT . isVector ( ) ) return false ; Chain = LD -> getChain ( ) ; Base = LD -> getBasePtr ( ) ; Offset = LD -> getOffset ( ) ; Align = LD -> getAlignment ( ) ; isSExtLd = LD -> getExtensionType ( ) == <STR_LIT> ; isPre = ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ; Pred = <STR_LIT> ; PredReg = LD -> getMask ( ) ; } else llvm_unreachable ( <STR_LIT> ) ; bool CanChangeType = Subtarget -> isLittle ( ) && ! isa < MaskedLoadSDNode > ( N ) ; SDValue NewOffset ; if ( Align >= <NUM_LIT> && LoadedVT == <STR_LIT> && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) { if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> :


<s> if ( ! N -> hasOneUse ( ) ) return false ; SDNode * Use = * N -> use_begin ( ) ; if ( Use -> getOpcode ( ) == <STR_LIT> ) return true ; if ( Use -> isMachineOpcode ( ) ) { const MCInstrDesc & MCID = TII -> get ( Use -> getMachineOpcode ( ) ) ; if ( MCID . mayStore ( )


<s> if ( ! Subtarget -> isCortexA9 ( ) ) return true ; if ( Shift . hasOneUse ( ) ) return true ; return ShOpcVal == <STR_LIT> && ShAmt


<s> SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE ,


<s> DebugLoc dl = V0 . getNode ( ) -> getDebugLoc ( ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT


<s> DebugLoc dl = V0 . getNode ( ) -> getDebugLoc ( ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT>


<s> SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT , Ops ,


<s> SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 , V2 , SubReg2 , V3 , SubReg3 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE ,


<s> SDNode * <ISA_LIT>DAGToDAGISel :: QuadSRegs ( EVT VT , SDValue V0 , SDValue V1 , SDValue V2 , SDValue V3 ) { DebugLoc dl = V0 . getNode ( ) -> getDebugLoc ( ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 , V2 , SubReg2 , V3 ,


<s> if ( Disable<ISA_LIT>IntABS ) return NULL ; if ( Subtarget -> isThumb1Only ( ) ) return NULL ; if ( XORSrc0 . getOpcode ( ) != <STR_LIT> || XORSrc1 . getOpcode ( ) != <STR_LIT> ) return NULL ; SDValue ADDSrc0 = XORSrc0 . getOperand ( <NUM_LIT> ) ; SDValue ADDSrc1 = XORSrc0 . getOperand ( <NUM_LIT> ) ; SDValue SRASrc0 = XORSrc1 . getOperand ( <NUM_LIT> ) ; SDValue SRASrc1 = XORSrc1 . getOperand


<s> if ( Subtarget -> isThumb1Only ( ) ) return NULL ; if ( XORSrc0 . getOpcode ( ) != <STR_LIT> || XORSrc1 . getOpcode ( ) != <STR_LIT> ) return NULL ; SDValue ADDSrc0 = XORSrc0 . getOperand ( <NUM_LIT> ) ; SDValue ADDSrc1 = XORSrc0 . getOperand ( <NUM_LIT> ) ; SDValue SRASrc0 = XORSrc1 . getOperand ( <NUM_LIT> ) ; SDValue SRASrc1 = XORSrc1 . getOperand ( <NUM_LIT> ) ; ConstantSDNode * SRAConstant = dyn_cast < ConstantSDNode > (


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrMode3 ( SDValue N , SDValue & Base , SDValue & Offset , SDValue & Opc ) { if ( N . getOpcode ( ) == <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { Base = N ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy (


<s> Offset = N . getOperand ( <NUM_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { Base = N ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC <


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrModeImm12 ( SDValue N , SDValue & Base , SDValue & OffImm ) { if ( N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> && ! CurDAG -> isBaseWithConstantOffset ( N ) ) { if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return


<s> OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ; return true ; } } Base = N ; OffImm = CurDAG -> getTargetConstant


<s> Match = true ; } else if ( LoadedVT == <STR_LIT> && SelectAddrMode2OffsetReg ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Opcode = isPre ? <STR_LIT> : <STR_LIT> ; Match = true ; } else if ( LoadedVT == <STR_LIT> && SelectAddrMode3Offset ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = ( LD -> getExtensionType ( ) == <STR_LIT> ) ? ( isPre ? <STR_LIT> : <STR_LIT> ) : ( isPre ? <STR_LIT> : <STR_LIT> ) ; } else if ( LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) { if ( LD -> getExtensionType ( ) == <STR_LIT> ) { if ( SelectAddrMode3Offset ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } } else { if ( isPre && SelectAddrMode2OffsetImmPre ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = <STR_LIT> ; } else if ( ! isPre && SelectAddrMode2OffsetImm ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = <STR_LIT> ; } else if ( SelectAddrMode2OffsetReg ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } } } if ( Match ) { if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { SDValue Chain = LD -> getChain


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; if ( Opc == <STR_LIT> ) { Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; } Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( Node ) -> getMemOperand ( ) ; SDNode * ResNode = CurDAG -> getMachineNode ( Opc , Node -> getDebugLoc ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> , Ops . data ( ) , Ops . size ( ) ) ; cast < MachineSDNode > ( ResNode ) -> setMemRefs ( MemOp ,


<s> } if ( Subtarget -> isThumb ( ) ) { SDNode * Res = SelectT2CMOVImmOp ( N , FalseVal , TrueVal , CCVal , CCR , InFlag ) ; if ( ! Res ) Res = SelectT2CMOVImmOp ( N , TrueVal , FalseVal , <STR_LIT> ( CCVal ) , CCR , InFlag ) ; if ( Res ) return Res ; } else { SDNode * Res = Select<ISA_LIT>CMOVImmOp ( N , FalseVal , TrueVal , CCVal , CCR , InFlag ) ; if ( ! Res ) Res = Select<ISA_LIT>CMOVImmOp ( N , TrueVal , FalseVal , <STR_LIT> ( CCVal ) , CCR , InFlag ) ; if ( Res ) return Res ; } } SDValue Tmp2 = CurDAG -> getTargetConstant ( CCVal , <STR_LIT> ) ; SDValue Ops [ ] = { FalseVal , TrueVal , Tmp2 , CCR , InFlag } ; unsigned Opc = <NUM_LIT> ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : assert ( false && <STR_LIT> ) ; break ; case <STR_LIT> : Opc = Subtarget -> isThumb ( ) ? ( Subtarget -> hasThumb2 ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; break ; case


<s> if ( Res ) return Res ; } else { SDNode * Res = Select<ISA_LIT>CMOVShiftOp ( N , FalseVal , TrueVal , CCVal , CCR , InFlag ) ; if ( ! Res ) Res = Select<ISA_LIT>CMOVShiftOp ( N , TrueVal , FalseVal , <STR_LIT> ( CCVal ) , CCR , InFlag ) ; if ( Res ) return Res ; } if ( Subtarget -> isThumb ( ) ) { SDNode * Res = SelectT2CMOVImmOp ( N , FalseVal , TrueVal , CCVal , CCR , InFlag ) ; if ( ! Res ) Res = SelectT2CMOVImmOp ( N , TrueVal , FalseVal , <STR_LIT> ( CCVal ) , CCR , InFlag ) ; if ( Res ) return Res ; } else { SDNode * Res = Select<ISA_LIT>CMOVImmOp ( N , FalseVal , TrueVal , CCVal , CCR , InFlag ) ; if ( ! Res ) Res = Select<ISA_LIT>CMOVImmOp ( N , TrueVal , FalseVal , <STR_LIT> ( CCVal ) , CCR , InFlag ) ; if ( Res ) return Res ; } } SDValue Tmp2 = CurDAG -> getTargetConstant ( CCVal , <STR_LIT> ) ; SDValue Ops [ ] = { FalseVal , TrueVal , Tmp2 , CCR , InFlag } ; unsigned Opc = <NUM_LIT> ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : assert ( false && <STR_LIT>


<s> return PairDRegs ( VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT>


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectConcatVector ( SDNode * N ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . is128BitVector ( ) || N -> getNumOperands ( ) != <NUM_LIT> ) llvm_unreachable


<s> AddSub = <STR_LIT> ; RHSC = - RHSC ; } if ( isPowerOf2_32 ( RHSC ) ) { unsigned ShAmt = Log2_32 ( RHSC ) ; Base = Offset = N . getOperand ( <NUM_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , ShAmt , <STR_LIT> ) , <STR_LIT> ) ; return true ; } } } } if ( N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> && ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; if ( N . getOpcode ( ) == <STR_LIT> || N . getOpcode ( ) == <STR_LIT> ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) return false ; } <STR_LIT> AddSub = N . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( Offset , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } if ( N . getOpcode ( ) != <STR_LIT> && ShOpcVal == <STR_LIT> && ! ( Subtarget -> isCortexA9 ( ) || N . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) { ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; if ( ShOpcVal != <STR_LIT>


<s> if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) return false ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { if ( SelectT2AddrModeImm8 ( N , Base , OffImm ) ) return false ; int RHSC = ( int ) RHS -> getZExtValue


<s> Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ; return true


<s> if ( N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> && ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getSExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( ( RHSC >= - <NUM_LIT> ) && ( RHSC < <NUM_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy


<s> switch ( SOShOp ) { case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } SDValue SOShImm = CurDAG -> getTargetConstant ( <STR_LIT> ( SOVal ) , <STR_LIT> ) ; SDValue CC = CurDAG -> getTargetConstant ( CCVal


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeSP ( SDValue N , SDValue & Base , SDValue & OffImm ) { if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; RegisterSDNode * LHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || ( LHSR && LHSR -> getReg


<s> } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; RegisterSDNode * LHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || ( LHSR && LHSR -> getReg ( ) == <STR_LIT> ) ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant (


<s> assert ( Srl_imm > <NUM_LIT> && Srl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Width = CountTrailingOnes_32 ( And_imm ) - <NUM_LIT> ; unsigned LSB = Srl_imm ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( LSB , <STR_LIT> ) , CurDAG -> getTargetConstant ( Width , <STR_LIT> ) , getAL ( CurDAG ) , Reg0 } ; return CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , Ops , <NUM_LIT> ) ; } } return NULL ; } unsigned Shl_imm = <NUM_LIT> ; if ( isOpcWithIntImmediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , Shl_imm ) ) { assert ( Shl_imm > <NUM_LIT> && Shl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Srl_imm = <NUM_LIT> ; if ( isInt32Immediate ( N -> getOperand ( <NUM_LIT> ) , Srl_imm ) ) { assert ( Srl_imm > <NUM_LIT> && Srl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Width = <NUM_LIT> - Srl_imm - <NUM_LIT> ; int LSB = Srl_imm - Shl_imm ; if ( LSB < <NUM_LIT>


<s> if ( NumVecs == <NUM_LIT> && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs != <NUM_LIT> && Opc != <STR_LIT> ) || ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLd = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops . data ( ) , Ops . size ( ) ) ; } else { EVT AddrTy = MemAddr . getValueType ( ) ; SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , ResTy ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , Reg0 , ImplDef , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTy , AddrTy , <STR_LIT> , OpsA , <NUM_LIT> ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; Ops . push_back ( SDValue ( VLdA , <NUM_LIT> ) ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; assert ( isa < ConstantSDNode > ( Inc . getNode ( ) ) && <STR_LIT> ) ; ( void ) Inc ; Ops . push_back ( Reg0 ) ; } Ops . push_back ( SDValue ( VLdA , <NUM_LIT> ) ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLd = CurDAG -> getMachineNode ( QOpcodes1 [ OpcodeIndex ] , dl , ResTys , Ops . data ( ) , Ops . size ( ) ) ; } MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( VLd ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) return VLd ; SDValue SuperReg = SDValue ( VLd , <NUM_LIT> ) ; assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> && <STR_LIT> == <STR_LIT> + <NUM_LIT> && <STR_LIT> ) ; unsigned Sub0 = ( is64BitVector ? <STR_LIT> : <STR_LIT> ) ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) ReplaceUses ( SDValue ( N ,

Vec ) , CurDAG -> getTargetExtractSubreg ( Sub0 + Vec , dl , VT , SuperReg ) ) ;


<s> MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned Alignment = <NUM_LIT> ; if ( NumVecs != <NUM_LIT> ) { Alignment = cast < ConstantSDNode > ( Align ) -> getZExtValue ( ) ; unsigned NumBytes = NumVecs * VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( Alignment > NumBytes ) Alignment = NumBytes ; if ( Alignment < <NUM_LIT> && Alignment < NumBytes ) Alignment = <NUM_LIT> ; Alignment = ( Alignment & - Alignment ) ; if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; } Align = CurDAG -> getTargetConstant ( Alignment , <STR_LIT> ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDValue SuperReg ; unsigned Opc = Opcodes [ OpcodeIndex ] ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( <NUM_LIT> ) ; Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; std :: vector < EVT > ResTys ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDNode * VLdDup = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops . data ( ) , Ops . size ( ) ) ; cast < MachineSDNode > ( VLdDup ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; SuperReg = SDValue ( VLdDup , <NUM_LIT> ) ; assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT>


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; if ( IsExt ) Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( RegSeq ) ; Ops . push_back ( N -> getOperand ( FirstTblReg + NumVecs ) ) ; Ops . push_back ( getAL ( CurDAG ) ) ; Ops . push_back ( CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ) ; return CurDAG -> getMachineNode ( Opc , dl , VT , Ops . data ( ) , Ops . size (


<s> if ( NumVecs == <NUM_LIT> ) RegSeq = SDValue ( PairDRegs ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else { SDValue V2 = N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; RegSeq = SDValue ( QuadDRegs ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } SmallVector < SDValue , <NUM_LIT> > Ops ; if ( IsExt ) Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( RegSeq ) ; Ops . push_back ( N -> getOperand ( FirstTblReg + NumVecs ) ) ; Ops . push_back ( getAL ( CurDAG ) ) ; Ops . push_back ( CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT>


<s> AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC , <STR_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ; return AM2_BASE ; } } if ( ( Subtarget -> isLikeA9 ( ) || Subtarget -> isSwift ( ) ) && ! N . hasOneUse ( ) ) { Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ; return AM2_BASE ; } <STR_LIT> AddSub = N . getOpcode ( ) != <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( Offset , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } if ( N . getOpcode ( ) != <STR_LIT> && ShOpcVal == <STR_LIT> && ! ( Subtarget -> isLikeA9 ( ) || Subtarget -> isSwift ( ) || N . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) { ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( N . getOperand ( <NUM_LIT> ) , ShOpcVal , ShAmt ) ) { Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Base = N . getOperand ( <NUM_LIT> ) ; } else { ShAmt = <NUM_LIT> ; ShOpcVal =


<s> if ( Range -> second == <NUM_LIT> ) { NewN = EmitShift ( <STR_LIT> , X , <NUM_LIT> - Range -> first ) ; ReplaceNode ( And . getNode ( ) , NewN ) ; } else if ( Range -> first == <NUM_LIT> ) { NewN = EmitShift ( <STR_LIT> , X , Range -> second ) ; ReplaceNode ( And . getNode ( ) , NewN ) ; } else if ( Range -> first == Range -> second ) { NewN = EmitShift ( <STR_LIT> , X , <NUM_LIT> - Range -> first ) ; ReplaceNode ( And . getNode ( ) , NewN ) ; SwitchEQNEToPLMI = true ; } else if ( ! Subtarget -> hasV6T2Ops ( ) ) { NewN = EmitShift ( <STR_LIT> , X , <NUM_LIT> - Range -> first ) ; NewN = EmitShift ( <STR_LIT> , SDValue ( NewN , <NUM_LIT> ) , Range -> second + ( <NUM_LIT> - Range -> first ) ) ; ReplaceNode ( And . getNode ( )


<s> void <ISA_LIT>DAGToDAGISel :: SelectCMPZ ( SDNode * N , bool & SwitchEQNEToPLMI ) { assert ( N -> getOpcode ( ) == <STR_LIT> ) ; SwitchEQNEToPLMI = false ; if ( ! Subtarget -> isThumb ( ) ) return ; SDValue And = N -> getOperand ( <NUM_LIT> ) ; if ( ! And -> hasOneUse ( ) ) return ; SDValue Zero = N -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Zero ) || ! cast < ConstantSDNode > ( Zero ) -> isNullValue ( ) || And -> getOpcode ( ) != <STR_LIT> ) return ; SDValue X = And . getOperand ( <NUM_LIT> ) ; auto C = dyn_cast < ConstantSDNode > ( And . getOperand ( <NUM_LIT> ) ) ; if ( ! C || ! X -> hasOneUse ( ) ) return ; auto Range = getContiguousRangeOfSetBits ( C -> getAPIntValue ( ) ) ; if ( ! Range ) return ; SDNode * NewN ; SDLoc dl ( N ) ; auto EmitShift = [ & ] ( unsigned Opc , SDValue Src , unsigned Imm )


<s> case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; assert ( NumVecs == <NUM_LIT> && <STR_LIT> ) ; break ; } EVT ResTy ; if ( NumVecs == <NUM_LIT> ) ResTy = VT ; else { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ; } std :: vector < EVT > ResTys ; ResTys . push_back ( ResTy ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDNode * VLd ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT , NumVecs ) ; if ( ( NumVecs <= <NUM_LIT> ) && ! IsImmUpdate ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs > <NUM_LIT> && ! isVLDfixed ( Opc ) ) || ! IsImmUpdate ) Ops . push_back ( IsImmUpdate ? Reg0 : Inc ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLd = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; } else { EVT AddrTy = MemAddr . getValueType ( ) ; SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , ResTy ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , Reg0 , ImplDef , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTy , AddrTy , <STR_LIT> , OpsA ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; Ops . push_back ( SDValue ( VLdA , <NUM_LIT> ) ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; assert ( isa < ConstantSDNode > ( Inc .


<s> unsigned NumBytes = NumVecs * VT . getScalarSizeInBits ( ) / <NUM_LIT> ; if ( Alignment > NumBytes ) Alignment = NumBytes ; if ( Alignment < <NUM_LIT> && Alignment < NumBytes ) Alignment = <NUM_LIT> ; Alignment = ( Alignment & - Alignment ) ; if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; } Align = CurDAG -> getTargetConstant ( Alignment , dl , <STR_LIT> ) ; unsigned Opc ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = DOpcodes [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = QOpcodes [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = DOpcodes [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = QOpcodes [ <NUM_LIT> ] ; break ; case <STR_LIT> : case <STR_LIT> : Opc = DOpcodes [ <NUM_LIT> ] ; break ; case <STR_LIT> : case <STR_LIT> : Opc = QOpcodes [ <NUM_LIT> ] ; break ; } SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT . getVectorElementType ( ) , NumVecs ) ; if ( NumVecs <= <NUM_LIT> && ! IsImmUpdate ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ! IsImmUpdate ) Ops . push_back ( Inc ) ; else if ( NumVecs > <NUM_LIT> ) Ops . push_back ( Reg0 ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; std :: vector < EVT > ResTys ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDNode * VLdDup = CurDAG -> getMachineNode ( Opc ,


<s> MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; unsigned Lane = cast < ConstantSDNode > ( N -> getOperand ( Vec0Idx + NumVecs ) ) -> getZExtValue ( ) ; EVT VT = N -> getOperand ( Vec0Idx ) . getValueType ( ) ; bool is64BitVector = VT . is64BitVector ( ) ; unsigned Alignment = <NUM_LIT> ; if ( NumVecs != <NUM_LIT> ) { Alignment = cast < ConstantSDNode > ( Align ) -> getZExtValue ( ) ; unsigned NumBytes = NumVecs * VT . getScalarSizeInBits ( ) / <NUM_LIT> ; if ( Alignment > NumBytes ) Alignment = NumBytes ; if ( Alignment < <NUM_LIT> && Alignment < NumBytes ) Alignment = <NUM_LIT> ; Alignment = ( Alignment & - Alignment ) ; if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; } Align = CurDAG -> getTargetConstant ( Alignment , dl , <STR_LIT> ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } std :: vector < EVT > ResTys ; if ( IsLoad ) { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT . getVectorElementType ( ) , NumVecs ) ; Ops . push_back ( IsImmUpdate ? Reg0 : Inc ) ; } SDValue SuperReg


<s> else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } } else { SDValue Q0 = N -> getOperand ( Vec0Idx ) ; SDValue Q1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQRegPairNode ( <STR_LIT> , Q0 , Q1 ) , <NUM_LIT> ) ; } unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT , NumVecs ) ; if ( NumVecs <= <NUM_LIT> && ! IsImmUpdate ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ! IsImmUpdate ) Ops . push_back ( Inc ) ; else if ( NumVecs > <NUM_LIT> && ! isVSTfixed ( Opc ) ) Ops . push_back ( Reg0 ) ; } Ops . push_back ( SrcReg ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; SDNode * VSt = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; cast < MachineSDNode > ( VSt ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; ReplaceNode ( N , VSt ) ; return ; } SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue RegSeq = SDValue ( createQuadQRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , Reg0 , RegSeq , Pred , Reg0 , Chain } ; SDNode * VStA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , MemAddr . getValueType ( ) , <STR_LIT> , OpsA ) ; cast < MachineSDNode > ( VStA ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; Chain = SDValue ( VStA , <NUM_LIT> ) ; Ops . push_back ( SDValue ( VStA , <NUM_LIT> ) ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; assert ( isa < ConstantSDNode > ( Inc . getNode (


<s> unsigned LSB = Srl_imm ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( ( LSB + Width + <NUM_LIT> ) == N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ) { if ( Subtarget -> isThumb ( ) ) { Opc = isSigned ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( LSB , dl , <STR_LIT> ) , getAL ( CurDAG , dl ) , Reg0 , Reg0 } ; CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , Ops ) ; return true ; } <STR_LIT> ShOpcVal = <STR_LIT> ( <STR_LIT> ) ; SDValue ShOpc = CurDAG -> getTargetConstant ( <STR_LIT> ( ShOpcVal , LSB ) , dl , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , ShOpc , getAL ( CurDAG , dl ) , Reg0 , Reg0 } ; CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops ) ; return true ; } SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( LSB , dl , <STR_LIT> ) , CurDAG -> getTargetConstant ( Width , dl , <STR_LIT> ) , getAL ( CurDAG , dl ) , Reg0 } ; CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , Ops ) ; return true ; } } return false ; } unsigned Shl_imm = <NUM_LIT> ; if ( isOpcWithIntImmediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , Shl_imm ) ) { assert ( Shl_imm > <NUM_LIT> && Shl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Srl_imm = <NUM_LIT> ; if ( isInt32Immediate ( N -> getOperand ( <NUM_LIT> ) , Srl_imm ) ) { assert ( Srl_imm > <NUM_LIT> && Srl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Width = <NUM_LIT> - Srl_imm - <NUM_LIT> ; int LSB = Srl_imm


<s> if ( <STR_LIT> ( Val ) != - <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( ~ Val ) != - <NUM_LIT> ) return <NUM_LIT> ; if ( Subtarget -> hasV6T2Ops ( ) && Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return <NUM_LIT> ; } if ( Subtarget -> useMovt ( )


<s> Base = N . getOperand ( <NUM_LIT> ) ; int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; if ( MFI . getObjectAlignment ( FI ) < <NUM_LIT> ) MFI . setObjectAlignment ( FI , <NUM_LIT> ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; OffImm = CurDAG -> getTargetConstant ( RHSC , SDLoc ( N ) , <STR_LIT> ) ; return true


<s> unsigned NumBytes = NumVecs * VT . getScalarSizeInBits ( ) / <NUM_LIT> ; if ( Alignment > NumBytes ) Alignment = NumBytes ; if ( Alignment < <NUM_LIT> && Alignment < NumBytes ) Alignment = <NUM_LIT> ; Alignment = ( Alignment & - Alignment ) ; if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; } Align = CurDAG -> getTargetConstant ( Alignment , dl , <STR_LIT> ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; EVT ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ; std :: vector < EVT > ResTys ; ResTys . push_back ( ResTy ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDNode * VLdDup ; if ( is64BitVector || NumVecs == <NUM_LIT> ) { SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; unsigned Opc = is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT . getVectorElementType ( ) , NumVecs ) ; if ( NumVecs <= <NUM_LIT> && ! IsImmUpdate ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ! IsImmUpdate ) Ops . push_back ( Inc ) ; else if ( NumVecs > <NUM_LIT> ) Ops . push_back ( Reg0 ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLdDup = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; } else if ( NumVecs == <NUM_LIT> ) { const SDValue OpsA [ ] = { MemAddr , Align , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTys , OpsA ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; const SDValue OpsB [ ] = { MemAddr , Align , Pred , Reg0 , Chain } ; VLdDup = CurDAG -> getMachineNode ( QOpcodes1 [ OpcodeIndex ] , dl


<s> ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT . getVectorElementType ( ) , NumVecs ) ; Ops . push_back ( IsImmUpdate ? Reg0 : Inc ) ; } SDValue SuperReg ; SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) { if ( is64BitVector ) SuperReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; } else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( is64BitVector ) SuperReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQuadQRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } Ops . push_back ( SuperReg ) ; Ops . push_back ( getI32Imm ( Lane , dl ) ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes [ OpcodeIndex ] ) ; SDNode * VLdLn = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( VLdLn ) , { MemOp } ) ; if ( ! IsLoad ) { ReplaceNode ( N , VLdLn ) ; return ; } SuperReg = SDValue (


<s> unsigned Op ; SDVTList VTs = CurDAG -> getVTList ( AN -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; if ( VT == <STR_LIT> ) Op = Op8 ; else if ( VT == <STR_LIT> ) Op = Op16 ; else if ( VT == <STR_LIT> ) Op = Op32 ; else if ( VT == <STR_LIT> ) { Op = Op64 ; VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; } else llvm_unreachable ( <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < AN -> getNumOperands ( ) ; ++ i ) Ops . push_back ( AN -> getOperand ( i ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( AN -> getOrdering ( ) , <STR_LIT> ) ) ; Ops . push_back ( AN -> getOperand ( <NUM_LIT> ) ) ; return CurDAG -> SelectNodeTo ( Node , Op , VTs , & Ops [ <NUM_LIT> ] , Ops . size (


<s> SDValue T1 = CurDAG -> getCopyToReg ( Sub1 , dl , Reg1 , Sub1 , T0 . getValue ( <NUM_LIT> ) ) ; std :: vector < SDValue > Ops ( GU -> op_begin ( ) , GU -> op_end ( ) - <NUM_LIT> ) ; Ops . push_back ( T1 . getValue ( <NUM_LIT> ) ) ; CurDAG -> UpdateNodeOperands ( GU , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; GU = T1 . getNode ( ) ; } else { SDValue Chain = AsmNodeOperands [ InlineAsm :: Op_InputChain ] ; SDValue T0 = CurDAG -> getCopyFromReg ( Chain , dl , Reg0 , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ; SDValue T1 = CurDAG -> getCopyFromReg ( Chain , dl , Reg1 , <STR_LIT> , T0 . getValue ( <NUM_LIT> ) ) ; SDValue Pair = SDValue ( createGPRPairNode ( <STR_LIT> , T0 , T1 ) , <NUM_LIT> ) ; unsigned GPVR = MRI . createVirtualRegister ( & <STR_LIT> ) ; PairedReg = CurDAG -> getRegister ( GPVR , <STR_LIT> ) ; Chain = CurDAG -> getCopyToReg ( T1 , dl , GPVR , Pair , T1 . getValue ( <NUM_LIT> ) ) ; AsmNodeOperands [ InlineAsm :: Op_InputChain ] = Chain ; Glue = Chain . getValue ( <NUM_LIT> ) ; } Changed = true ; if ( PairedReg . getNode ( ) ) { OpChanged [ OpChanged . size ( ) - <NUM_LIT> ] = true ; Flag = InlineAsm :: getFlagWord ( Kind , <NUM_LIT> ) ; if ( IsTiedToChangedOp ) Flag = InlineAsm :: getFlagWordForMatchingOp ( Flag , DefIdx ) ; else Flag = InlineAsm :: getFlagWordForRegClass ( Flag , <STR_LIT> ) ; AsmNodeOperands [ AsmNodeOperands . size ( ) - <NUM_LIT> ] = CurDAG -> getTargetConstant ( Flag , <STR_LIT> ) ; AsmNodeOperands . push_back ( PairedReg ) ; i += <NUM_LIT> ; } } if ( Glue . getNode ( ) )


<s> if ( SYSmvalue == - <NUM_LIT> ) return - <NUM_LIT> ; if ( ! Subtarget -> hasV7Ops ( ) && SYSmvalue >= <NUM_LIT> && SYSmvalue <= <NUM_LIT> ) return - <NUM_LIT> ; if ( Subtarget -> has8MSecExt ( ) && Flags . lower ( ) == <STR_LIT> ) { Flags = <STR_LIT> ; SYSmvalue |= <NUM_LIT> ; } if ( ! Subtarget -> has8MSecExt ( ) && ( SYSmvalue == <NUM_LIT> || SYSmvalue == <NUM_LIT> || SYSmvalue > <NUM_LIT> ) ) return - <NUM_LIT> ; if ( ! Subtarget -> hasV8MMainlineOps ( ) && ( SYSmvalue == <NUM_LIT> || SYSmvalue == <NUM_LIT> || SYSmvalue == <NUM_LIT> || SYSmvalue == <NUM_LIT> ) ) return - <NUM_LIT> ; if ( IsRead ) { if ( Flags . empty ( ) ) return SYSmvalue ; else return - <NUM_LIT> ; } int Mask = getMClassFlagsMask ( Flags ) ; if ( ( SYSmvalue < <NUM_LIT> && Mask == - <NUM_LIT> ) || ( SYSmvalue > <NUM_LIT> && ! Flags . empty ( ) ) ) return - <NUM_LIT> ; if ( ! Subtarget -> hasDSP ( ) && ( Mask


<s> if ( IsRead ) { if ( Flags . empty ( ) ) return SYSmvalue ; else return - <NUM_LIT> ; } int Mask = getMClassFlagsMask ( Flags ) ; if ( ( SYSmvalue < <NUM_LIT> && Mask == - <NUM_LIT> ) || ( SYSmvalue > <NUM_LIT> && ! Flags . empty ( ) ) ) return - <NUM_LIT> ; if ( ! Subtarget -> hasDSP ( ) && ( Mask & <NUM_LIT> ) ) return - <NUM_LIT> ; return SYSmvalue | Mask <<


<s> return StringSwitch < int > ( RegString . lower ( ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) .

Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ;


<s> return StringSwitch < int > ( RegString . lower ( ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case

( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ;


<s> Base = N . getOperand ( <NUM_LIT> ) ; OffReg = N . getOperand ( <NUM_LIT> ) ; <STR_LIT> ShOpcVal = <STR_LIT> ( OffReg . getOpcode ( ) ) ; if ( ShOpcVal != <STR_LIT> ) { ShOpcVal = <STR_LIT> ( Base . getOpcode ( ) ) ; if ( ShOpcVal == <STR_LIT> ) std :: swap ( Base , OffReg ) ; } if ( ShOpcVal == <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( OffReg . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( ShAmt < <NUM_LIT> && isShifterOpProfitable ( OffReg , ShOpcVal , ShAmt ) ) OffReg = OffReg . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; } } } if ( OffReg . getOpcode ( ) == <STR_LIT> && N . hasOneUse ( ) ) { unsigned PowerOfTwo = <NUM_LIT> ; SDValue NewMulConst ; if ( canExtractShiftFromMul ( OffReg , <NUM_LIT> , PowerOfTwo , NewMulConst ) ) { replaceDAGValue ( OffReg . getOperand ( <NUM_LIT> ) , NewMulConst ) ; ShAmt = PowerOfTwo ; } } ShImm = CurDAG -> getTargetConstant ( ShAmt , SDLoc ( N


<s> unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ; } std :: vector < EVT > ResTys ; ResTys . push_back ( ResTy ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDNode * VLd ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( ( NumVecs <= <NUM_LIT> ) && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs > <NUM_LIT> && ! isVLDfixed ( Opc ) ) || ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLd = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; } else { EVT AddrTy = MemAddr . getValueType ( ) ; SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , ResTy ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , Reg0 , ImplDef , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTy , AddrTy , <STR_LIT> , OpsA ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; Ops . push_back ( SDValue ( VLdA , <NUM_LIT> ) ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; assert ( isa < ConstantSDNode > ( Inc . getNode ( ) ) && <STR_LIT> ) ; ( void ) Inc ; Ops . push_back ( Reg0 )


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; assert ( NumVecs == <NUM_LIT> && <STR_LIT> ) ; break ; } EVT ResTy ; if ( NumVecs == <NUM_LIT> ) ResTy = VT ; else { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ; } std :: vector < EVT > ResTys ; ResTys . push_back ( ResTy ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDNode * VLd ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( ( NumVecs <= <NUM_LIT> ) && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs > <NUM_LIT> && ! isVLDfixed ( Opc ) ) || ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLd = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; }


<s> if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Opcode == <STR_LIT> && ! Subtarget -> hasFP<ISA_LIT>v8 ( ) ) return false ; Ops = { getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , <STR_LIT> , Ops ) ) ; return true ; } if ( Subtarget -> isMClass ( ) ) { StringRef Flags = <STR_LIT> , Reg = SpecialReg ; if ( Reg . endswith ( <STR_LIT> ) ) { Flags = <STR_LIT> ; Reg = Reg . drop_back ( <NUM_LIT> ) ; } int SYSmValue = getMClassRegisterMask ( Reg , Flags , true , Subtarget ) ; if ( SYSmValue == - <NUM_LIT> ) return false ; SDValue Ops [ ] = { CurDAG -> getTargetConstant ( SYSmValue , DL , <STR_LIT> ) , getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , Ops ) ) ; return true ; } if ( SpecialReg == <STR_LIT> || SpecialReg == <STR_LIT> ) { Ops = { getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( IsThumb2 ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , Ops ) ) ; return true ; } if ( SpecialReg == <STR_LIT> ) { Ops = { getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( IsThumb2 ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , Ops ) ) ; return true


<s> return true ; } unsigned Opcode = StringSwitch < unsigned > ( SpecialReg ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Opcode ) { if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Opcode == <STR_LIT> && ! Subtarget -> hasFP<ISA_LIT>v8 ( ) ) return false ; Ops = { getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , <STR_LIT> , Ops ) ) ; return true ; } if ( Subtarget -> isMClass ( ) ) { StringRef Flags = <STR_LIT> , Reg = SpecialReg ; if ( Reg . endswith ( <STR_LIT> ) ) { Flags = <STR_LIT> ; Reg = Reg . drop_back ( <NUM_LIT> ) ; } int SYSmValue = getMClassRegisterMask ( Reg , Flags , true , Subtarget ) ; if ( SYSmValue == - <NUM_LIT> ) return false ; SDValue Ops [ ] = { CurDAG -> getTargetConstant ( SYSmValue , DL , <STR_LIT> ) , getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , Ops ) ) ; return true ; } if ( SpecialReg == <STR_LIT> || SpecialReg == <STR_LIT> ) { Ops = { getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( IsThumb2 ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , Ops ) ) ; return true ; } if ( SpecialReg == <STR_LIT> ) { Ops = { getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N


<s> if ( Subtarget -> hasV6T2Ops ( ) && Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( ~ Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return <NUM_LIT> ; } else { if ( <STR_LIT> ( Val ) != - <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( ~ Val ) != - <NUM_LIT> ) return <NUM_LIT> ; if ( Subtarget -> hasV6T2Ops ( ) && Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return <NUM_LIT> ; } if ( Subtarget -> useMovt ( * MF ) ) return


<s> unsigned <ISA_LIT>DAGToDAGISel :: ConstantMaterializationCost ( unsigned Val ) const { if ( Subtarget -> isThumb ( ) ) { if ( Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( Subtarget -> hasV6T2Ops ( ) && Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( ~ Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return <NUM_LIT> ; }


<s> int Mask = getMClassFlagsMask ( Flags , Subtarget -> hasDSP ( ) ) ; if ( ( SYSmvalue < <NUM_LIT> && Mask == - <NUM_LIT> ) || ( SYSmvalue > <NUM_LIT> && ! Flags . empty ( ) ) ) return - <NUM_LIT> ; if ( ! Subtarget -> hasDSP ( ) && ( Mask & <NUM_LIT> ) ) return - <NUM_LIT> ; if ( SYSmvalue < <NUM_LIT> ) return SYSmvalue | Mask


<s> if ( ! Subtarget -> has8MSecExt ( ) && ( SYSmvalue == <NUM_LIT> || SYSmvalue == <NUM_LIT> || SYSmvalue > <NUM_LIT> ) ) return - <NUM_LIT> ; if ( ! Subtarget -> hasV8MMainlineOps ( ) && ( SYSmvalue == <NUM_LIT> || SYSmvalue == <NUM_LIT> || SYSmvalue == <NUM_LIT> || SYSmvalue == <NUM_LIT> ) ) return - <NUM_LIT> ; if ( IsRead ) { if ( Flags . empty ( ) ) return SYSmvalue ; else return - <NUM_LIT> ; } int Mask = getMClassFlagsMask ( Flags , Subtarget -> hasDSP (


<s> } ConstantSDNode * SRLSrc1 = dyn_cast < ConstantSDNode > ( SRL . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * SHLSrc1 = dyn_cast < ConstantSDNode > ( SHL . getOperand ( <NUM_LIT> ) ) ; if ( ! SRLSrc1 || ! SHLSrc1 || SRLSrc1 -> getZExtValue ( ) != <NUM_LIT> || SHLSrc1 -> getZExtValue ( ) != <NUM_LIT> ) return false ; if ( ( SRL . getOperand ( <NUM_LIT> ) . getNode ( ) != SHL . getOperand ( <NUM_LIT> ) . getNode ( ) ) || SRL . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return false ; SDNode * SMULLOHI = SRL . getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( SRL . getOperand ( <NUM_LIT> ) != SDValue ( SMULLOHI , <NUM_LIT> ) || SHL . getOperand ( <NUM_LIT> ) != SDValue ( SMULLOHI , <NUM_LIT> ) ) return false ; if ( SearchSignedMulShort ( SMULLOHI -> getOperand ( <NUM_LIT> ) , Opc , Src1 , Accumulate ) ) { Src0 = SMULLOHI -> getOperand ( <NUM_LIT> ) ; } else if ( SearchSignedMulShort ( SMULLOHI -> getOperand ( <NUM_LIT> ) , Opc , Src1 , Accumulate


<s> SDValue SRL = OR . getOperand ( <NUM_LIT> ) ; SDValue SHL = OR . getOperand ( <NUM_LIT> ) ; if ( SRL . getOpcode ( ) != <STR_LIT> || SHL . getOpcode ( ) != <STR_LIT> ) { SRL = OR . getOperand ( <NUM_LIT> ) ; SHL = OR . getOperand ( <NUM_LIT> ) ; if ( SRL . getOpcode ( ) != <STR_LIT> || SHL . getOpcode ( ) != <STR_LIT> ) return false ; } ConstantSDNode * SRLSrc1 = dyn_cast < ConstantSDNode > ( SRL . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * SHLSrc1 = dyn_cast < ConstantSDNode > ( SHL . getOperand ( <NUM_LIT> ) ) ; if ( ! SRLSrc1 || ! SHLSrc1 || SRLSrc1 -> getZExtValue ( ) != <NUM_LIT> || SHLSrc1 -> getZExtValue ( ) != <NUM_LIT> ) return false ; if ( ( SRL . getOperand ( <NUM_LIT> ) . getNode ( ) != SHL . getOperand ( <NUM_LIT> ) . getNode ( ) ) || SRL . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return false ; SDNode * SMULLOHI = SRL . getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( SRL . getOperand ( <NUM_LIT> ) != SDValue ( SMULLOHI , <NUM_LIT> ) || SHL . getOperand ( <NUM_LIT> ) != SDValue ( SMULLOHI , <NUM_LIT> ) ) return false ; if ( SearchSignedMulShort ( SMULLOHI -> getOperand ( <NUM_LIT> ) , Opc , Src1 , Accumulate ) ) { Src0 = SMULLOHI -> getOperand ( <NUM_LIT> ) ; } else if ( SearchSignedMulShort ( SMULLOHI -> getOperand ( <NUM_LIT> ) , Opc , Src1 , Accumulate ) ) { Src0 = SMULLOHI -> getOperand (


<s> if ( ! SRASrc1 || SRASrc1 -> getZExtValue ( ) != <NUM_LIT> ) return false ; SDValue Op0 = SignExt . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { SDValue SHL = Op0 ; ConstantSDNode * SHLSrc1 = dyn_cast < ConstantSDNode > ( SHL . getOperand ( <NUM_LIT> ) ) ; if ( ! SHLSrc1 || SHLSrc1 -> getZExtValue ( ) != <NUM_LIT> ) return false ; * Opc = Accumulate ? <STR_LIT> :


<s> ReplaceNode ( N , createDRegPairNode ( VT , N -> getOperand ( <NUM_LIT> ) , N ->


<s> if ( ! VT . is128BitVector ( ) || N -> getNumOperands ( ) != <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; ReplaceNode ( N , createDRegPairNode ( VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand (


<s> } else if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; } else { Base = N ; } OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } int RHSC


<s> } else if ( SearchSignedMulLong ( Src1 , & Opc , A , B , true ) ) { Acc = Src0 ; } else { return false ; } if ( Opc == <NUM_LIT> ) return false ; SDValue Ops [ ] = { A , B , Acc , getAL ( CurDAG , dl ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) } ; CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , <STR_LIT> , Ops ) ; return true ; } else if ( N -> getOpcode ( ) == <STR_LIT> && SearchSignedMulLong ( SDValue ( N , <NUM_LIT> ) , & Opc , A , B , false ) ) { if ( Opc == <NUM_LIT> ) return false ; SDValue Ops [ ] = { A , B , getAL ( CurDAG , dl ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) } ; CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> ,


<s> bool <ISA_LIT>DAGToDAGISel :: tryT2IndexedLoad ( SDNode * N ) { LoadSDNode * LD = cast < LoadSDNode > ( N ) ; <STR_LIT> AM = LD -> getAddressingMode ( ) ; if ( AM == <STR_LIT> ) return false ; EVT LoadedVT = LD -> getMemoryVT ( ) ; bool isSExtLd = LD -> getExtensionType ( ) == <STR_LIT> ; SDValue Offset ; bool isPre = ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ; unsigned Opcode = <NUM_LIT> ; bool Match = false ; if ( SelectT2AddrModeImm8Offset ( N , LD -> getOffset ( ) , Offset ) ) { switch ( LoadedVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : if ( isSExtLd ) Opcode =


<s> if ( OptLevel == CodeGenOpt :: None ) return true ; if ( ! CheckVMLxHazard ) return true ; if ( ! Subtarget -> isCortexA7 ( ) && ! Subtarget -> isCortexA8 ( ) && ! Subtarget -> isCortexA9 ( ) && ! Subtarget -> isSwift ( ) ) return true ; if ( ! N -> hasOneUse ( ) ) return false ; SDNode * Use = * N -> use_begin ( ) ; if ( Use -> getOpcode ( ) == <STR_LIT> ) return true ; if ( Use -> isMachineOpcode ( ) ) { const <ISA_LIT>BaseInstrInfo * TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( CurDAG -> getTarget ( ) . getInstrInfo ( ) ) ; const MCInstrDesc & MCID = TII -> get ( Use ->


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; return


<s> SelectAddrMode2Worker ( Op , N , Base


<s> bool SelectAddrMode2Base ( SDNode * Op , SDValue N , SDValue & Base , SDValue & Offset , SDValue & Opc ) { return SelectAddrMode2Worker ( Op , N , Base , Offset , Opc )


<s> } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { Base = N ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub


<s> if ( ! restrict_addressing_modes_for_nacl ) { if ( N . getOpcode ( ) == <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { Base = N ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC ) , <STR_LIT> ) ; return true ; } if (


<s> Match = true ; } else if ( LoadedVT == <STR_LIT> && ! isPre && SelectAddrMode2OffsetImm ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Opcode = <STR_LIT> ; Match = true ; } else if ( LoadedVT == <STR_LIT> && SelectAddrMode2OffsetReg ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Opcode = isPre ? <STR_LIT> : <STR_LIT> ; Match = true ; } else if ( LoadedVT == <STR_LIT> && SelectAddrMode3Offset ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = ( LD -> getExtensionType ( ) == <STR_LIT> ) ? ( isPre ? <STR_LIT> : <STR_LIT> ) : ( isPre ? <STR_LIT> : <STR_LIT> ) ; } else if ( LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) { if ( LD -> getExtensionType ( ) == <STR_LIT> ) { if ( SelectAddrMode3Offset ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } } else { if ( isPre && SelectAddrMode2OffsetImmPre ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = <STR_LIT> ; } else if ( ! isPre && SelectAddrMode2OffsetImm ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = <STR_LIT> ; } else if ( SelectAddrMode2OffsetReg ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } } } if ( Match ) { if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ; SDValue Ops [ ] = { Base , AMOpc , getAL ( CurDAG ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , Chain } ; return CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , <STR_LIT> , <STR_LIT> , <STR_LIT> , Ops ) ; } else { SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ; SDValue Ops [ ] = { Base , Offset , AMOpc , getAL ( CurDAG ) , CurDAG -> getRegister


<s> bool Changed = false ; unsigned NumOps = N -> getNumOperands ( ) ; SDLoc dl ( N ) ; SDValue Glue = N -> getGluedNode ( ) ? N -> getOperand ( NumOps - <NUM_LIT> ) : SDValue ( nullptr , <NUM_LIT> ) ; SmallVector < bool , <NUM_LIT> > OpChanged ; for ( unsigned i = <NUM_LIT> , e = N -> getGluedNode ( ) ? NumOps - <NUM_LIT> : NumOps ; i < e ; ++ i ) { SDValue op = N -> getOperand ( i ) ; AsmNodeOperands . push_back ( op ) ; if ( i < InlineAsm :: Op_FirstOperand ) continue ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( i ) ) ) { Flag = C -> getZExtValue ( ) ; Kind = InlineAsm :: getKind ( Flag ) ; } else continue ; if ( Kind == InlineAsm :: Kind_Imm ) { SDValue op = N -> getOperand ( ++ i ) ; AsmNodeOperands . push_back ( op ) ; continue ; } unsigned NumRegs = InlineAsm :: getNumOperandRegisters ( Flag ) ; if ( NumRegs ) OpChanged . push_back ( false ) ; unsigned DefIdx = <NUM_LIT> ; bool IsTiedToChangedOp = false ; if ( Changed && InlineAsm :: isUseOperandTiedToDef ( Flag , DefIdx ) ) IsTiedToChangedOp = OpChanged [ DefIdx ] ; if ( Kind != InlineAsm :: Kind_RegUse && Kind != InlineAsm :: Kind_RegDef && Kind != InlineAsm :: Kind_RegDefEarlyClobber ) continue ; unsigned RC ; bool HasRC = InlineAsm :: hasRegClassConstraint ( Flag , RC ) ; if ( ( ! IsTiedToChangedOp && ( ! HasRC || RC != <STR_LIT> ) ) || NumRegs != <NUM_LIT> ) continue ; assert ( ( i + <NUM_LIT> < NumOps ) && <STR_LIT> ) ; SDValue V0 = N -> getOperand ( i +


<s> return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { if ( SelectT2AddrModeImm8 ( N , Base , OffImm ) ) return false ; int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeImm5S ( SDValue N , unsigned Scale , SDValue & Base , SDValue & OffImm ) { if ( Scale == <NUM_LIT> ) { SDValue TmpBase , TmpOffImm ; if ( SelectThumbAddrModeSP ( N , TmpBase , TmpOffImm ) ) return false ; if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand


<s> case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDValue SuperReg ; unsigned Opc = Opcodes [ OpcodeIndex ] ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( Inc ) ; else if ( NumVecs > <NUM_LIT> ) Ops . push_back ( Reg0 ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; std :: vector < EVT > ResTys ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; if ( isUpdating ) ResTys . push_back (


<s> EVT VT = N -> getOperand ( Vec0Idx ) . getValueType ( ) ; bool is64BitVector = VT . is64BitVector ( ) ; unsigned Alignment = <NUM_LIT> ; if ( NumVecs != <NUM_LIT> ) { Alignment = cast < ConstantSDNode > ( Align ) -> getZExtValue ( ) ; unsigned NumBytes = NumVecs * VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( Alignment > NumBytes ) Alignment = NumBytes ; if ( Alignment < <NUM_LIT> && Alignment < NumBytes ) Alignment = <NUM_LIT> ; Alignment = ( Alignment & - Alignment ) ; if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; } Align = CurDAG -> getTargetConstant ( Alignment , <STR_LIT> ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } std :: vector < EVT > ResTys ; if ( IsLoad ) { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister (


<s> if ( IsLoad ) { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } SDValue SuperReg ; SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) { if ( is64BitVector ) SuperReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; } else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( is64BitVector ) SuperReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQuadQRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } Ops . push_back ( SuperReg ) ; Ops . push_back ( getI32Imm ( Lane ) ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes [ OpcodeIndex ] ) ; SDNode * VLdLn = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; cast < MachineSDNode > ( VLdLn ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; if ( ! IsLoad ) return VLdLn ; SuperReg = SDValue ( VLdLn ,


<s> SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { SDValue SrcReg ; if ( NumVecs == <NUM_LIT> ) { SrcReg = N -> getOperand ( Vec0Idx ) ; } else if ( is64BitVector ) { SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) SrcReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } } else { SDValue Q0 = N -> getOperand ( Vec0Idx ) ; SDValue Q1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQRegPairNode ( <STR_LIT> , Q0 , Q1 ) , <NUM_LIT> ) ; } unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( NumVecs <= <NUM_LIT> && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( Inc ) ; else if ( NumVecs > <NUM_LIT> && ! isVSTfixed ( Opc ) ) Ops . push_back (