<s> DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , MFI . getObjectSize ( FI ) , Align ) ; if ( RC == <STR_LIT> ) RC = <STR_LIT> ; if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( RC == <STR_LIT> || RC == <STR_LIT> || RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else { assert ( ( RC == <STR_LIT> || RC == <STR_LIT> || RC == <STR_LIT> ) && <STR_LIT> ) ; if ( Align >= <NUM_LIT> && ( getRegisterInfo ( ) . canRealignStack ( MF ) ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; }


<s> } else if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else { assert ( ( RC == <STR_LIT> || RC == <STR_LIT> || RC == <STR_LIT> ) && <STR_LIT> ) ; if ( Align >= <NUM_LIT> && ( getRegisterInfo ( ) . canRealignStack ( MF ) ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; }


<s> int CPI1 = MO1 . getIndex ( ) ; const MachineConstantPoolEntry & MCPE0 = MCP -> getConstants ( ) [ CPI0 ] ; const MachineConstantPoolEntry & MCPE1 = MCP -> getConstants ( ) [ CPI1 ] ; <ISA_LIT>ConstantPoolValue * ACPV0 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE0 . Val . MachineCPVal ) ; <ISA_LIT>ConstantPoolValue * ACPV1 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE1 . Val . MachineCPVal ) ; return ACPV0 -> hasSameValue


<s> if ( MI1 -> getOpcode ( ) != Opcode ) return false ; if ( MI0 -> getNumOperands ( ) != MI1 -> getNumOperands ( ) ) return false ; const MachineOperand & MO0 = MI0 -> getOperand ( <NUM_LIT> ) ; const MachineOperand & MO1 = MI1 -> getOperand ( <NUM_LIT> ) ; if ( MO0 . getOffset ( ) != MO1 . getOffset ( ) ) return false ; const MachineFunction * MF = MI0 -> getParent ( ) -> getParent ( ) ; const MachineConstantPool * MCP = MF -> getConstantPool ( ) ; int CPI0 = MO0 . getIndex ( ) ; int CPI1 = MO1 . getIndex (


<s> MachineInstrBuilder MIB = BuildMI ( MBB , I , Orig -> getDebugLoc ( ) , get ( Opcode ) , DestReg ) . addConstantPoolIndex ( CPI ) . addImm ( PCLabelId ) ; ( * MIB ) . setMemRefs ( Orig -> memoperands_begin ( ) , Orig -> memoperands_end ( ) ) ; break ; } } MachineInstr * NewMI = prior ( I ) ; NewMI -> getOperand ( <NUM_LIT> ) . setSubReg (


<s> unsigned <ISA_LIT>BaseInstrInfo :: RemoveBranch ( MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent


<s> case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; break ; } Offset += InstrOffs * Scale ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( Offset < <NUM_LIT> ) { Offset = - Offset ; isSub = true ; } if ( NumBits > <NUM_LIT> ) { MachineOperand & ImmOp = MI . getOperand ( ImmIdx ) ; int ImmedOffset = Offset / Scale ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( unsigned ) Offset <= Mask * Scale ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; if ( isSub ) ImmedOffset |= <NUM_LIT> << NumBits ; ImmOp . ChangeToImmediate ( ImmedOffset ) ; Offset = <NUM_LIT> ; return true ; } ImmedOffset = ImmedOffset & Mask ; if ( isSub ) ImmedOffset |= <NUM_LIT> << NumBits ; ImmOp . ChangeToImmediate ( ImmedOffset ) ; Offset &= ~ ( Mask * Scale ) ; } } Offset = ( isSub ) ? -


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , MFI . getObjectSize ( FI ) , Align ) ; if ( RC == <STR_LIT> ) RC = <STR_LIT> ; if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( RC == <STR_LIT> || RC == <STR_LIT> || RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else { assert ( ( RC == <STR_LIT> || RC == <STR_LIT> ) && <STR_LIT> ) ; if ( Align >= <NUM_LIT> && ( getRegisterInfo ( ) . canRealignStack ( MF


<s> storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , MFI . getObjectSize ( FI ) , Align ) ; if ( RC == <STR_LIT> ) RC = <STR_LIT> ; if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( RC == <STR_LIT> || RC == <STR_LIT> || RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( RC


<s> SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = ~ <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; CmpValue =


<s> default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = ~ <NUM_LIT> ; CmpValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = ~ <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; CmpValue =


<s> unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? <STR_LIT> : <STR_LIT> : isThumb ? Subtarget . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ; if ( isThumb && ! Call -> getOperand ( FuncOp ) . isReg ( ) ) MIB . add ( predOps ( <STR_LIT> ) ) ; Call -> eraseFromParent ( ) ; } auto IsNonTailCall = [ ] ( MachineInstr & MI ) { return MI . isCall ( ) && ! MI . isReturn ( ) ; } ; if ( std :: any_of ( MBB . instr_begin ( ) , MBB . instr_end ( ) , IsNonTailCall ) ) { MachineBasicBlock :: iterator It = MBB . begin ( ) ; MachineBasicBlock :: iterator Et = MBB . end ( ) ; if ( OF . FrameConstructionID == MachineOutlinerTailCall || OF . FrameConstructionID == MachineOutlinerThunk ) Et = std :: prev ( MBB . end ( ) ) ; if ( ! MBB . isLiveIn ( <STR_LIT> ) ) MBB . addLiveIn ( <STR_LIT> ) ; saveLROnStack ( MBB , It ) ; unsigned StackAlignment = Subtarget . getStackAlignment ( ) . value ( ) ; const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const MCRegisterInfo * MRI = STI . getRegisterInfo (


<s> ScheduleHazardRecognizer * <ISA_LIT>BaseInstrInfo :: CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAG * DAG ) const { if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2Base ( ) ) return new <ISA_LIT>HazardRecognizer ( II


<s> CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAG * DAG ) const { if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2Base ( ) ) return new <ISA_LIT>HazardRecognizer (


<s> SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; switch ( UseOpc ) { default : break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; } break ; case <STR_LIT> : case <STR_LIT> : { if ( UseOpc == <STR_LIT> && Commute ) return false ; const bool ToSP = DefMI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ; const unsigned t2ADD = ToSP ? <STR_LIT> : <STR_LIT> ; const unsigned t2SUB = ToSP ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( ImmVal ) ) NewUseOpc = UseOpc == <STR_LIT> ? t2ADD : t2SUB ; else if ( <STR_LIT> ( - ImmVal ) ) { ImmVal = - ImmVal ; NewUseOpc = UseOpc == <STR_LIT> ? t2SUB : t2ADD ; } else return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; break ; } case <STR_LIT> : case <STR_LIT> : if ( ! <STR_LIT> ( ImmVal ) ) return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; switch ( UseOpc ) { default : break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; } break ; } } } unsigned OpIdx = Commute ? <NUM_LIT> : <NUM_LIT> ; Register Reg1 = UseMI . getOperand ( OpIdx ) . getReg ( ) ; bool isKill = UseMI . getOperand ( OpIdx ) . isKill ( ) ; const TargetRegisterClass * TRC = MRI -> getRegClass ( Reg ) ; Register NewReg = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( NewUseOpc ) , NewReg ) . addReg ( Reg1 , getKillRegState ( isKill ) ) . addImm ( SOImmValV1 ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; UseMI . setDesc ( get ( NewUseOpc ) ) ; UseMI . getOperand ( <NUM_LIT> ) . setReg ( NewReg


<s> bool <ISA_LIT>BaseInstrInfo :: FoldImmediate ( MachineInstr & UseMI , MachineInstr & DefMI , Register Reg , MachineRegisterInfo * MRI ) const { unsigned DefOpc = DefMI . getOpcode ( ) ; if ( DefOpc != <STR_LIT> && DefOpc != <STR_LIT> ) return false ; if ( ! DefMI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; if ( ! MRI -> hasOneNonDBGUse ( Reg ) ) return false ; const MCInstrDesc & DefMCID = DefMI . getDesc ( ) ; if ( DefMCID . hasOptionalDef ( ) ) { unsigned NumOps = DefMCID . getNumOperands ( ) ; const MachineOperand & MO = DefMI . getOperand ( NumOps - <NUM_LIT> ) ; if ( MO . getReg ( ) == <STR_LIT> && ! MO . isDead ( ) ) return false ; } const MCInstrDesc & UseMCID = UseMI . getDesc ( ) ; if ( UseMCID . hasOptionalDef ( ) ) { unsigned NumOps = UseMCID . getNumOperands ( ) ; if ( UseMI . getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; } unsigned UseOpc = UseMI . getOpcode ( ) ; unsigned NewUseOpc = <NUM_LIT> ; uint32_t ImmVal = ( uint32_t ) DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; uint32_t SOImmValV1 = <NUM_LIT> , SOImmValV2 = <NUM_LIT> ; bool Commute = false ; switch ( UseOpc ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Commute = UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) != Reg ; switch ( UseOpc ) { default : break ; case <STR_LIT>


<s> if ( MI . isDebugInstr ( ) || MI . isIndirectDebugValue ( ) ) return outliner :: InstrType :: Invisible ; if ( MI . isKill ( ) || MI . isImplicitDef ( ) ) return outliner :: InstrType :: Invisible ; unsigned Opc = MI . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) return outliner :: InstrType :: Illegal ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) return outliner :: InstrType :: Illegal ; const MCInstrDesc & MCID = MI . getDesc ( ) ; uint64_t MIFlags = MCID . TSFlags ; if ( ( MIFlags & <STR_LIT> ) == <STR_LIT> ) return outliner :: InstrType :: Illegal ; if ( MI . isTerminator ( ) ) { if ( isPredicated ( MI ) ) return outliner :: InstrType :: Illegal ; if ( MI . getParent ( ) -> succ_empty ( ) ) return outliner :: InstrType :: Legal ; return outliner :: InstrType :: Illegal ; } for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return outliner :: InstrType :: Illegal ; } if ( MI . readsRegister ( <STR_LIT> , TRI ) || MI . readsRegister ( <STR_LIT> , TRI ) ) return outliner :: InstrType :: Illegal ; if ( MI . isCall ( ) ) { const Function * Callee = nullptr ; for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isGlobal ( ) ) { Callee = dyn_cast < Function > ( MOP . getGlobal ( ) ) ; break ; } } if ( Callee && ( Callee -> getName ( ) == <STR_LIT> || Callee -> getName ( ) == <STR_LIT> || Callee -> getName ( ) == <STR_LIT> ) ) return outliner :: InstrType :: Illegal ; auto UnknownCallOutlineType = outliner :: InstrType :: Illegal ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) UnknownCallOutlineType = outliner :: InstrType :: LegalTerminator ; if ( ! Callee )


<s> MachineBasicBlock :: iterator <ISA_LIT>BaseInstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , const outliner :: Candidate & C ) const { MachineInstrBuilder MIB ; MachineBasicBlock :: iterator CallPt ; unsigned Opc ; bool isThumb = Subtarget . isThumb ( ) ; if ( C . CallConstructionID == MachineOutlinerTailCall ) { Opc = isThumb ? Subtarget . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; if ( isThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; It = MBB . insert ( It , MIB ) ; return It ; } Opc = isThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder CallMIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) ; if ( isThumb ) CallMIB . add ( predOps ( <STR_LIT> ) ) ; CallMIB . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; if ( C . CallConstructionID == MachineOutlinerNoLRSave || C . CallConstructionID == MachineOutlinerThunk ) { It = MBB . insert ( It , CallMIB ) ; return It ; } if ( C . CallConstructionID == MachineOutlinerRegSave ) { unsigned Reg = findRegisterToSaveLRTo ( C ) ; assert ( Reg != <NUM_LIT> && <STR_LIT> ) ; copyPhysReg ( MBB , It , DebugLoc ( ) , Reg , <STR_LIT> , true ) ; CallPt = MBB . insert ( It , CallMIB ) ; copyPhysReg ( MBB , It , DebugLoc ( ) , <STR_LIT> , Reg , true ) ; It -- ; return CallPt ; } saveLROnStack ( MBB , It )


<s> const auto & Op = MI . getOperand ( i ) ; if ( Op . isReg ( ) && Op .


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const Align Alignment = MFI . getObjectAlign ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , Alignment ) ; switch ( TRI -> getSpillSize ( * RC ) ) { case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineInstrBuilder MIB ; if ( Subtarget . hasV5TEOps ( ) ) { MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; }


<s> MachineInstrBuilder MIB = BuildMI ( MBB , It , DebugLoc ( ) , get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; if ( ! Subtarget . isThumb ( ) ) MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Subtarget . getStackAlignment ( ) . value ( ) ) . add


<s> if ( isPredicated ( MI ) ) return true ; MachineBasicBlock :: const_iterator Next = & MI ; ++ Next ; Register SrcReg , SrcReg2 ; int CmpMask , CmpValue ; bool IsThumb1 ; if ( Next != MI . getParent ( ) -> end ( ) && analyzeCompare ( * Next , SrcReg , SrcReg2 , CmpMask , CmpValue ) && isRedundantFlagInstr ( & * Next , SrcReg , SrcReg2 , CmpValue , & MI , IsThumb1 ) ) return false ; return


<s> if ( isPredicated ( MI ) ) return true ; MachineBasicBlock :: const_iterator Next = & MI ; ++ Next ; Register SrcReg , SrcReg2 ; int CmpMask , CmpValue ; bool IsThumb1


<s> } if ( MI . getOpcode ( ) == <STR_LIT> && ! Subtarget . hasV6Ops ( ) ) { if ( ! <STR_LIT> . contains ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) && ! <STR_LIT> . contains ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { ErrInfo = <STR_LIT> ; return false ; } } if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI


<s> if ( ! MLxEntryMap . insert ( std :: make_pair ( <ISA_LIT>_MLxTable [ i ] . MLxOpc , i ) ) . second ) assert ( false && <STR_LIT> ) ; MLxHazardOpcodes . insert ( <ISA_LIT>_MLxTable [ i ] . AddSubOpc


<s> bool GPRDest = <STR_LIT> . contains ( DestReg ) ; bool GPRSrc = <STR_LIT> . contains ( SrcReg ) ; if ( GPRDest && GPRSrc ) { AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ) ) ; return ; } bool SPRDest = <STR_LIT> . contains ( DestReg ) ; bool SPRSrc = <STR_LIT> . contains ( SrcReg ) ; unsigned Opc ; if ( SPRDest && SPRSrc ) Opc = <STR_LIT> ; else if ( GPRDest && SPRSrc ) Opc = <STR_LIT> ; else if ( SPRDest && GPRSrc ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get


<s> const TargetInstrDesc & TID = MI -> getDesc ( ) ; if ( ! TID . getImplicitDefs ( ) && ! TID . hasOptionalDef ( ) ) return false ; bool Found = false ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> ) { Pred . push_back ( MO ) ; Found =


<s> bool Found = false ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . getReg ( ) ==


<s> if ( ! Node -> isMachineOpcode ( ) ) return <NUM_LIT> ; if ( ! ItinData || ItinData -> isEmpty ( ) ) return <NUM_LIT> ; unsigned Opcode = Node -> getMachineOpcode ( ) ; switch ( Opcode ) { default : return ItinData -> getStageLatency ( get ( Opcode ) . getSchedClass ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> } break ; } case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : { switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned EntrySize = ( Opc == <STR_LIT> ) ? <NUM_LIT> : ( ( Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned NumOps = TID . getNumOperands ( ) ; MachineOperand JTOP = MI -> getOperand ( NumOps - ( TID . isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOP . getIndex ( ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; assert ( MJTI != <NUM_LIT> ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; assert ( JTI < JT . size ( ) ) ; unsigned InstSize = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned NumEntries = getNumJTEntries ( JT , JTI ) ; if ( Opc == <STR_LIT> && ( NumEntries & <NUM_LIT> ) ) ++ NumEntries ; return NumEntries * EntrySize


<s> DefCycle = RegNo / <NUM_LIT> ; if ( DefCycle < <NUM_LIT> ) DefCycle = <NUM_LIT> ; DefCycle += <NUM_LIT> ; } else if ( Subtarget . isCortexA9 ( ) ) { DefCycle = ( RegNo / <NUM_LIT> ) ; if ( ( RegNo % <NUM_LIT> ) || DefAlign < <NUM_LIT> ) ++ DefCycle ; DefCycle += <NUM_LIT> ; } else { DefCycle = RegNo + <NUM_LIT> ; } return DefCycle


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumRegs = MI -> getNumOperands ( ) - Desc . getNumOperands ( ) ; return ( NumRegs / <NUM_LIT> ) + ( NumRegs % <NUM_LIT> ) + <NUM_LIT> ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumRegs = MI -> getNumOperands ( ) - Desc . getNumOperands ( ) + <NUM_LIT> ; if ( Subtarget . isCortexA8 ( ) ) { if ( NumRegs < <NUM_LIT> ) return <NUM_LIT> ; UOps = ( NumRegs / <NUM_LIT> ) ; if ( NumRegs % <NUM_LIT> ) ++ UOps ; return UOps ; } else if ( Subtarget . isCortexA9 ( ) ) { UOps = ( NumRegs


<s> if ( isZeroCost ( DefTID . Opcode ) ) return <NUM_LIT> ; if ( ! ItinData || ItinData -> isEmpty ( ) ) return DefTID . mayLoad ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( ! UseNode -> isMachineOpcode ( ) ) { int Latency = ItinData -> getOperandCycle ( DefTID . getSchedClass ( ) , DefIdx ) ; if ( Subtarget . isCortexA9 ( ) ) return Latency <= <NUM_LIT> ? <NUM_LIT> : Latency - <NUM_LIT> ; else return Latency <= <NUM_LIT> ? <NUM_LIT> : Latency - <NUM_LIT> ; } const TargetInstrDesc & UseTID = get ( UseNode -> getMachineOpcode ( ) ) ; const MachineSDNode * DefMN = dyn_cast < MachineSDNode > ( DefNode ) ; unsigned DefAlign = ! DefMN -> memoperands_empty ( ) ? ( * DefMN -> memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; const MachineSDNode * UseMN = dyn_cast < MachineSDNode > ( UseNode ) ; unsigned UseAlign = ! UseMN -> memoperands_empty ( ) ? ( * UseMN -> memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; int Latency = getOperandLatency ( ItinData , DefTID , DefIdx , DefAlign , UseTID , UseIdx , UseAlign ) ; if ( Latency > <NUM_LIT> && ( Subtarget . isCortexA8 ( ) || Subtarget . isCortexA9 ( ) ) ) { switch ( DefTID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned ShOpVal = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned ShImm = <STR_LIT> ( ShOpVal ) ; if ( ShImm == <NUM_LIT> || ( ShImm == <NUM_LIT> && <STR_LIT> ( ShOpVal ) == <STR_LIT> ) ) -- Latency ; break ; } case <STR_LIT> : case <STR_LIT>


<s> int <ISA_LIT>BaseInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , SDNode * DefNode , unsigned DefIdx , SDNode * UseNode , unsigned UseIdx ) const { if ( ! DefNode -> isMachineOpcode ( ) ) return <NUM_LIT> ; const TargetInstrDesc & DefTID = get ( DefNode -> getMachineOpcode ( ) ) ; if ( isZeroCost ( DefTID . Opcode ) ) return <NUM_LIT> ; if ( ! ItinData || ItinData -> isEmpty ( ) ) return DefTID . mayLoad ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( ! UseNode -> isMachineOpcode ( ) ) { int Latency = ItinData -> getOperandCycle ( DefTID . getSchedClass ( ) , DefIdx ) ; if ( Subtarget . isCortexA9 ( ) ) return Latency <= <NUM_LIT> ? <NUM_LIT> : Latency - <NUM_LIT> ; else return Latency <= <NUM_LIT> ? <NUM_LIT> : Latency - <NUM_LIT> ; } const TargetInstrDesc & UseTID = get ( UseNode -> getMachineOpcode ( ) ) ; const MachineSDNode * DefMN = dyn_cast < MachineSDNode > ( DefNode ) ; unsigned DefAlign = ! DefMN -> memoperands_empty ( ) ? ( * DefMN -> memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; const MachineSDNode * UseMN = dyn_cast < MachineSDNode > ( UseNode ) ; unsigned UseAlign = ! UseMN -> memoperands_empty ( ) ? ( * UseMN -> memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; int Latency = getOperandLatency ( ItinData , DefTID , DefIdx , DefAlign , UseTID , UseIdx , UseAlign ) ; if ( Latency > <NUM_LIT> && ( Subtarget . isCortexA8 ( ) || Subtarget . isCortexA9 ( ) ) ) { switch ( DefTID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned ShOpVal = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned ShImm = <STR_LIT> ( ShOpVal ) ; if ( ShImm == <NUM_LIT> || ( ShImm == <NUM_LIT> && <STR_LIT> ( ShOpVal ) == <STR_LIT> ) ) -- Latency ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned ShAmt = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( ShAmt == <NUM_LIT> || ShAmt == <NUM_LIT> ) -- Latency ; break ; } } } return Latency


<s> if ( RegNo <= <NUM_LIT> ) return ItinData -> getOperandCycle ( UseClass , UseIdx ) ; int UseCycle ; if ( Subtarget . isCortexA8 ( ) ) { UseCycle = RegNo / <NUM_LIT> ; if ( UseCycle < <NUM_LIT> ) UseCycle = <NUM_LIT> ; UseCycle += <NUM_LIT> ; } else if ( Subtarget . isCortexA9 ( ) ) { UseCycle = ( RegNo / <NUM_LIT>


<s> int <ISA_LIT>BaseInstrInfo :: getVSTMUseCycle ( const InstrItineraryData * ItinData , const TargetInstrDesc & UseTID , unsigned UseClass , unsigned UseIdx , unsigned UseAlign ) const { int RegNo = ( int ) ( UseIdx + <NUM_LIT> ) - UseTID . getNumOperands ( ) + <NUM_LIT> ; if ( RegNo <= <NUM_LIT> ) return ItinData -> getOperandCycle ( UseClass , UseIdx ) ; int UseCycle ; if ( Subtarget . isCortexA8 ( )


<s> if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; return <NUM_LIT> ; } BuildMI ( & MBB , DL , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] .


<s> case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; } return <NUM_LIT>


<s> if ( ( TID . TSFlags & <STR_LIT> ) == <STR_LIT> ) { <ISA_LIT>FunctionInfo * AFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; return AFI -> isThumb2Function ( ) ; } return


<s> virtual bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , const BranchProbability & Probability ) const { return NumCycles ==


<s> virtual bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , const BranchProbability & Probability


<s> if ( CmpMask != ~ <NUM_LIT> ) { if ( ! isSuitableForMask ( MI , SrcReg , CmpMask , false ) ) { MI = <NUM_LIT> ; for ( MachineRegisterInfo :: use_iterator UI = MRI -> use_begin ( SrcReg ) , UE = MRI -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getParent ( ) != CmpInstr -> getParent ( ) ) continue ; MachineInstr * PotentialAND = & * UI ; if ( ! isSuitableForMask ( PotentialAND , SrcReg , CmpMask , true ) ) continue ; MI = PotentialAND ; break ; } if ( ! MI ) return false ; } } if ( MI -> getParent ( ) != CmpInstr -> getParent ( ) ) return false ; MachineBasicBlock :: const_iterator I = CmpInstr , E = MI , B = MI -> getParent ( ) -> begin ( ) ; if ( I == B ) return false ; -- I ; for ( ; I != E ; -- I ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( ! MO . isReg ( ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) return false ; } if ( I == B ) return false ; } switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> MachineBasicBlock :: const_iterator I = CmpInstr , E = MI , B = MI -> getParent ( ) -> begin ( ) ; if ( I == B ) return false ; -- I ; for ( ; I != E ; -- I ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( ! MO . isReg ( ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) return false ; } if ( I == B ) return false ; } switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MI -> getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDef ( true ) ; CmpInstr -> eraseFromParent (


<s> break ; } case <STR_LIT> : case <STR_LIT> : { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CPI = Orig -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , Orig -> getDebugLoc ( ) , get ( Opcode ) , DestReg ) . addConstantPoolIndex ( CPI ) . addImm ( PCLabelId ) ; ( * MIB ) . setMemRefs ( Orig -> memoperands_begin ( ) , Orig


<s> unsigned RotAmt = <STR_LIT> ( Offset ) ; unsigned ThisImmVal = Offset & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; Offset &= ~ ThisImmVal ; assert ( <STR_LIT> ( ThisImmVal ) != - <NUM_LIT> && <STR_LIT> ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( ThisImmVal ) ; } else { unsigned ImmIdx = <NUM_LIT> ; int InstrOffs = <NUM_LIT> ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; switch ( AddrMode ) { case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; NumBits = <NUM_LIT> ; break ; } case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; } case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : return false ; case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; break ; } Offset += InstrOffs * Scale ; assert ( ( Offset & ( Scale - <NUM_LIT>


<s> if ( ! MI ) return nullptr ; MI -> getOperand ( MI -> findFirstPredOperandIdx ( ) ) . setImm ( <STR_LIT> ( CC ) ) ; return MI ; } } return TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI ,


<s> case <STR_LIT> : { unsigned PredReg = <NUM_LIT> ; <STR_LIT> CC = getInstrPredicate ( * MI , PredReg ) ; if ( CC == <STR_LIT> || PredReg != <STR_LIT> ) return nullptr ; MI = TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI


<s> unsigned DefOpc = DefMI -> getOpcode ( ) ; if ( DefOpc != <STR_LIT> && DefOpc != <STR_LIT> ) return false ; if ( ! DefMI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; if ( ! MRI -> hasOneNonDBGUse ( Reg ) ) return false ; const MCInstrDesc & DefMCID = DefMI -> getDesc ( ) ; if ( DefMCID . hasOptionalDef ( ) ) { unsigned NumOps = DefMCID . getNumOperands ( ) ; const MachineOperand & MO = DefMI -> getOperand ( NumOps - <NUM_LIT> ) ; if ( MO . getReg ( ) == <STR_LIT> && ! MO . isDead ( ) ) return false ; } const MCInstrDesc & UseMCID = UseMI -> getDesc ( ) ; if ( UseMCID . hasOptionalDef ( ) ) { unsigned NumOps = UseMCID . getNumOperands ( ) ; if ( UseMI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; } unsigned UseOpc = UseMI -> getOpcode ( ) ; unsigned NewUseOpc = <NUM_LIT> ; uint32_t ImmVal = ( uint32_t ) DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; uint32_t SOImmValV1 = <NUM_LIT> , SOImmValV2 = <NUM_LIT> ; bool Commute = false ; switch ( UseOpc ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Commute = UseMI -> getOperand ( <NUM_LIT> ) . getReg ( ) != Reg ; switch ( UseOpc ) { default : break ; case <STR_LIT> : case <STR_LIT> :


<s> unsigned Class = Desc . getSchedClass ( ) ; int ItinUOps = ItinData -> getNumMicroOps ( Class ) ; if ( ItinUOps >= <NUM_LIT> ) { if ( Subtarget . isSwift ( ) && ( Desc . mayLoad ( ) || Desc . mayStore ( ) ) ) return getNumMicroOpsSwiftLdSt ( ItinData , MI ) ; return ItinUOps ; } unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumRegs = MI -> getNumOperands ( ) - Desc . getNumOperands ( ) ; return ( NumRegs / <NUM_LIT> ) + ( NumRegs % <NUM_LIT> ) + <NUM_LIT> ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumRegs = MI -> getNumOperands ( ) - Desc . getNumOperands ( ) + <NUM_LIT> ; if ( Subtarget . isSwift ( ) ) { int UOps = <NUM_LIT> + NumRegs ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( MI1 -> getOpcode ( ) != Opcode ) return false ; if ( MI0 -> getNumOperands ( ) != MI1 -> getNumOperands ( ) ) return false ; unsigned Addr0 = MI0 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Addr1 = MI1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Addr0 != Addr1 ) { if ( ! MRI || ! TargetRegisterInfo :: isVirtualRegister ( Addr0 ) || ! TargetRegisterInfo :: isVirtualRegister ( Addr1 ) ) return false ; MachineInstr * Def0 = MRI -> getVRegDef ( Addr0 ) ; MachineInstr * Def1 = MRI -> getVRegDef ( Addr1 ) ; if ( ! produceSameValue ( Def0 , Def1 , MRI ) ) return false ; } for ( unsigned i = <NUM_LIT> , e = MI0 -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO0 = MI0 -> getOperand ( i ) ; const MachineOperand & MO1 = MI1 -> getOperand ( i ) ; if ( ! MO0 . isIdenticalTo ( MO1 ) ) return false ; } return true


<s> if ( ImplicitSReg != <NUM_LIT> ) MIB . addReg ( ImplicitSReg , RegState :: Implicit ) ; break ; } case <STR_LIT> : { if ( Domain != ExeNEON ) break ; DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstLane = <NUM_LIT> , SrcLane = <NUM_LIT> , DDst , DSrc ; DDst = getCorrespondingDRegAndLane ( TRI , DstReg , DstLane ) ; DSrc = getCorrespondingDRegAndLane ( TRI , SrcReg , SrcLane ) ; unsigned ImplicitSReg ; if ( ! getImplicitSPRUseForDPRUse ( TRI , MI , DSrc , SrcLane , ImplicitSReg ) ) break ; for ( unsigned i = MI -> getDesc ( ) . getNumOperands ( ) ; i ; -- i ) MI -> RemoveOperand ( i - <NUM_LIT> ) ; if ( DSrc == DDst ) { MI -> setDesc ( get ( <STR_LIT> ) ) ; MIB . addReg ( DDst , RegState :: Define ) . addReg ( DDst , getUndefRegState ( ! MI -> readsRegister ( DDst , TRI ) ) ) . addImm ( SrcLane ) ; AddDefaultPred ( MIB ) ; MIB . addReg ( DstReg , RegState :: Implicit | RegState :: Define ) ; MIB . addReg ( SrcReg , RegState :: Implicit ) ; if ( ImplicitSReg != <NUM_LIT> ) MIB . addReg ( ImplicitSReg , RegState :: Implicit ) ; break ; } MachineInstrBuilder NewMIB ; NewMIB = BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DDst ) ; unsigned CurReg = SrcLane == <NUM_LIT> && DstLane == <NUM_LIT> ? DSrc : DDst ; bool CurUndef = ! MI -> readsRegister ( CurReg , TRI ) ; NewMIB . addReg ( CurReg , getUndefRegState ( CurUndef ) ) ; CurReg = SrcLane == <NUM_LIT> && DstLane == <NUM_LIT> ? DSrc : DDst ; CurUndef = ! MI -> readsRegister ( CurReg , TRI ) ; NewMIB . addReg ( CurReg , getUndefRegState ( CurUndef ) ) ; NewMIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( NewMIB ) ; if ( SrcLane == DstLane ) NewMIB . addReg ( SrcReg , RegState :: Implicit ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MIB . addReg ( DDst , RegState


<s> if ( ! MI ) return nullptr ; if ( ! isPredicable ( * MI ) ) return nullptr ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isFI ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return nullptr ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isTied ( ) ) return nullptr ; if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) return nullptr ; if ( MO . isDef ( ) && ! MO . isDead ( ) ) return nullptr ; } bool DontMoveAcrossStores = true ; if ( ! MI -> isSafeToMove ( nullptr , DontMoveAcrossStores ) ) return nullptr ; return


<s> Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; Spacing = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) && ! Subtarget . hasFP64 ( ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( SrcReg == <STR_LIT> ) { copyFromCPSR ( MBB , I , DestReg , KillSrc , Subtarget ) ; return ; } else if ( DestReg == <STR_LIT> ) { copyToCPSR ( MBB , I , SrcReg , KillSrc , Subtarget ) ; return ; } else if ( DestReg == <STR_LIT> ) { assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps ( <STR_LIT> ) ) ; return ; } else if ( SrcReg == <STR_LIT> ) { assert ( <STR_LIT> . contains ( DestReg ) ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps ( <STR_LIT> ) ) ; return ; } else if ( DestReg == <STR_LIT> ) { assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps ( <STR_LIT> ) ) ; return ; } else if ( SrcReg == <STR_LIT> ) { assert ( <STR_LIT> . contains ( DestReg ) ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps ( <STR_LIT> ) ) ; return ; } assert ( Opc && <STR_LIT> ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; MachineInstrBuilder Mov ; if ( TRI -> regsOverlap ( SrcReg , TRI -> getSubReg ( DestReg , BeginIdx ) ) ) { BeginIdx = BeginIdx + ( ( SubRegs - <NUM_LIT> ) * Spacing ) ; Spacing = - Spacing ; } SmallSet < unsigned , <NUM_LIT> > DstRegs ; for ( unsigned i = <NUM_LIT> ; i != SubRegs ; ++ i ) { Register Dst = TRI -> getSubReg ( DestReg , BeginIdx + i * Spacing


<s> void <ISA_LIT>BaseInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { bool GPRDest = <STR_LIT> . contains ( DestReg ) ; bool GPRSrc = <STR_LIT> . contains ( SrcReg ) ; if ( GPRDest && GPRSrc ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; return ; } bool SPRDest = <STR_LIT> . contains ( DestReg ) ; bool SPRSrc = <STR_LIT> . contains ( SrcReg ) ; unsigned Opc = <NUM_LIT> ; if ( SPRDest && SPRSrc ) Opc = <STR_LIT> ; else if ( GPRDest && SPRSrc ) Opc = <STR_LIT> ; else if ( SPRDest && GPRSrc ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) && Subtarget . hasFP64 ( ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = Subtarget . hasNEON ( ) ? <STR_LIT> : <STR_LIT> ; if ( Opc ) { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) ; MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; if ( Opc == <STR_LIT> ) addUnpredicatedMveVpredROp ( MIB , DestReg ) ; else MIB . add ( predOps ( <STR_LIT> ) ) ; return ; } unsigned BeginIdx = <NUM_LIT> ; unsigned SubRegs = <NUM_LIT> ; int Spacing = <NUM_LIT> ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = Subtarget . hasNEON ( ) ? <STR_LIT> : <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = Subtarget . hasNEON ( ) ? <STR_LIT> : <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg ,


<s> while ( CmpMI != Br -> getParent ( ) -> begin ( ) ) { -- CmpMI ; if ( CmpMI -> modifiesRegister ( <STR_LIT> , TRI ) ) break ; if ( CmpMI -> readsRegister ( <STR_LIT> , TRI ) ) break ; } if ( CmpMI -> getOpcode ( ) != <STR_LIT> && CmpMI -> getOpcode ( ) != <STR_LIT> ) return nullptr ; Register Reg = CmpMI -> getOperand ( <NUM_LIT> )


<s> if ( <STR_LIT> ( ImmVal ) ) NewUseOpc = UseOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> ( - ImmVal ) ) { ImmVal = - ImmVal ; NewUseOpc = UseOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! <STR_LIT> ( ImmVal ) ) return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; switch ( UseOpc ) { default : break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; } break ; case <STR_LIT> : case <STR_LIT> : if ( UseOpc == <STR_LIT> && Commute ) return false ; if ( <STR_LIT> ( ImmVal ) ) NewUseOpc = UseOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> ( - ImmVal ) ) { ImmVal = - ImmVal ; NewUseOpc = UseOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! <STR_LIT> ( ImmVal ) ) return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; switch ( UseOpc ) { default : break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; } break ; } } } unsigned OpIdx = Commute ? <NUM_LIT> : <NUM_LIT> ; Register Reg1 = UseMI . getOperand ( OpIdx ) . getReg ( ) ; bool isKill = UseMI . getOperand ( OpIdx ) . isKill (


<s> if ( Subtarget -> isThumb ( ) ) { if ( Val <= <NUM_LIT> ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( Subtarget -> hasV6T2Ops ( ) && ( Val <= <NUM_LIT> || <STR_LIT> ( Val ) != - <NUM_LIT> || <STR_LIT> ( ~ Val ) != - <NUM_LIT> ) ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( Val <= <NUM_LIT> ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( ~ Val <= <NUM_LIT> ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; } else { if ( <STR_LIT> ( Val ) != - <NUM_LIT> ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( <STR_LIT> ( ~ Val ) != - <NUM_LIT> ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( Subtarget -> hasV6T2Ops ( ) && Val <= <NUM_LIT> ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; } if ( Subtarget -> useMovt ( ) ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; return ForCodesize ? <NUM_LIT> :


<s> unsigned <ISA_LIT>BaseInstrInfo :: extraSizeToPredicateInstructions ( const MachineFunction & MF , unsigned NumInsts ) const { return Subtarget . isThumb2 ( ) ? divideCeil ( NumInsts , <NUM_LIT> )


<s> int Threshold = <NUM_LIT> + Adj ; return Latency <= Threshold ? <NUM_LIT> : Latency - Adj ; } const MCInstrDesc & UseMCID = get ( UseNode -> getMachineOpcode ( ) ) ; auto * DefMN = cast < MachineSDNode > ( DefNode ) ; unsigned DefAlign = ! DefMN -> memoperands_empty ( ) ? ( * DefMN -> memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; auto * UseMN = cast < MachineSDNode > ( UseNode ) ; unsigned UseAlign = ! UseMN -> memoperands_empty ( ) ? ( * UseMN -> memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; int Latency = getOperandLatency ( ItinData , DefMCID , DefIdx , DefAlign , UseMCID , UseIdx , UseAlign ) ; if ( Latency > <NUM_LIT> && ( Subtarget . isCortexA8 ( ) || Subtarget . isLikeA9 ( ) || Subtarget . isCortexA7 ( ) ) ) { switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned ShOpVal = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned ShImm = <STR_LIT> ( ShOpVal ) ; if ( ShImm == <NUM_LIT> || ( ShImm == <NUM_LIT> && <STR_LIT> ( ShOpVal ) == <STR_LIT> ) ) -- Latency ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned ShAmt = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( ShAmt == <NUM_LIT> || ShAmt == <NUM_LIT> ) -- Latency ; break ; } } } else if ( DefIdx == <NUM_LIT> && Latency > <NUM_LIT> && Subtarget . isSwift ( ) ) { switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned ShOpVal = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned ShImm = <STR_LIT> ( ShOpVal ) ; if ( ShImm == <NUM_LIT> || ( ( ShImm == <NUM_LIT> || ShImm == <NUM_LIT> || ShImm == <NUM_LIT> ) && <STR_LIT> ( ShOpVal ) == <STR_LIT> ) ) Latency -= <NUM_LIT> ; else if ( ShImm == <NUM_LIT> && <STR_LIT> ( ShOpVal ) == <STR_LIT> ) -- Latency ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Latency -= <NUM_LIT> ; break ; } } if ( DefAlign < <NUM_LIT> && Subtarget . checkVLDnAccessAlignment ( ) ) switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> } } MachineBasicBlock :: iterator I = CmpInstr , E = MI , B = CmpInstr . getParent ( ) -> begin ( ) ; if ( I == B ) return false ; MachineInstr * SubAdd = nullptr ; if ( SrcReg2 != <NUM_LIT> ) MI = nullptr ; else if ( MI -> getParent ( ) != CmpInstr . getParent ( ) || CmpValue != <NUM_LIT> ) { if ( CmpInstr . getOpcode ( ) == <STR_LIT> || CmpInstr . getOpcode ( ) == <STR_LIT> || CmpInstr . getOpcode ( ) == <STR_LIT> ) MI = nullptr ; else return false ; } bool IsThumb1 = false ; if ( MI && ! isOptimizeCompareCandidate ( MI , IsThumb1 ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; if ( MI && IsThumb1 ) { -- I ; if ( I != E && ! MI -> readsRegister ( <STR_LIT> , TRI ) ) { bool CanReorder = true ; for ( ; I != E ; -- I ) { if ( I -> getOpcode ( ) != <STR_LIT> ) { CanReorder = false ; break ; } } if ( CanReorder ) { MI = MI -> removeFromParent ( ) ; E = CmpInstr ; CmpInstr . getParent ( ) -> insert ( E , MI ) ; } } I = CmpInstr ; E = MI ; } bool SubAddIsThumb1 = false ; do { const MachineInstr & Instr = * -- I ; if ( isRedundantFlagInstr ( & CmpInstr , SrcReg , SrcReg2 , CmpValue , & Instr , SubAddIsThumb1 ) ) { SubAdd = & * I ; break ; } if ( I == E ) break ; if ( Instr . modifiesRegister ( <STR_LIT> , TRI ) || Instr . readsRegister ( <STR_LIT> , TRI ) ) return false ; if ( I == B ) { return false ; } } while ( true ) ; if ( ! MI && ! SubAdd ) return false ; if ( SubAdd ) { MI = SubAdd ; IsThumb1 = SubAddIsThumb1 ; } if ( isPredicated ( * MI ) ) return false ; SmallVector < std :: pair < MachineOperand * , <STR_LIT> > , <NUM_LIT> > OperandsToUpdate ; bool isSafe = false ; I = CmpInstr ; E = CmpInstr . getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++


<s> unsigned FuncOp = isThumb ? <NUM_LIT> : <NUM_LIT> ; unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? <STR_LIT> : <STR_LIT> : isThumb ? Subtarget . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ; if ( isThumb && ! Call -> getOperand ( FuncOp ) . isReg ( ) ) MIB . add ( predOps ( <STR_LIT> ) ) ; Call -> eraseFromParent ( ) ; return ; } BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Subtarget . getReturnOpcode ( ) ) ) . add ( predOps (


<s> outliner :: OutlinedFunction <ISA_LIT>BaseInstrInfo :: getOutliningCandidateInfo ( std :: vector < outliner :: Candidate > & RepeatedSequenceLocs ) const { outliner :: Candidate & FirstCand = RepeatedSequenceLocs [ <NUM_LIT> ] ; unsigned SequenceSize = std :: accumulate ( FirstCand . front ( ) , std :: next ( FirstCand . back ( ) ) , <NUM_LIT> , [ this ] ( unsigned Sum , const MachineInstr & MI ) { return Sum + getInstSizeInBytes ( MI ) ; } ) ; unsigned FlagsSetInAll = <NUM_LIT> ; const TargetRegisterInfo & TRI = getRegisterInfo ( ) ; std :: for_each ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , [ & FlagsSetInAll ] ( outliner :: Candidate & C ) { FlagsSetInAll &= C . Flags ; } ) ; auto CantGuaranteeValueAcrossCall = [ & TRI ] ( outliner :: Candidate & C ) { if ( C . Flags & UnsafeRegsDead ) return false ; C . initLRU ( TRI ) ; LiveRegUnits LRU = C . LRU ; return ( ! LRU . available ( <STR_LIT> ) || ! LRU . available ( <STR_LIT> ) ) ; } ; if ( ! ( FlagsSetInAll & UnsafeRegsDead ) ) { RepeatedSequenceLocs . erase ( std :: remove_if ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , CantGuaranteeValueAcrossCall ) , RepeatedSequenceLocs . end ( ) ) ; if ( RepeatedSequenceLocs . size ( ) < <NUM_LIT> ) return outliner :: OutlinedFunction ( ) ; } unsigned LastInstrOpcode = RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> getOpcode ( ) ; auto SetCandidateCallInfo = [ & RepeatedSequenceLocs ] ( unsigned CallID , unsigned NumBytesForCall ) { for ( outliner :: Candidate & C : RepeatedSequenceLocs ) C . setCallInfo ( CallID , NumBytesForCall ) ; } ; OutlinerCosts Costs ( Subtarget ) ; unsigned FrameID = <NUM_LIT> ; unsigned NumBytesToCreateFrame = <NUM_LIT> ; if ( RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> isTerminator ( ) ) { FrameID = MachineOutlinerTailCall ; NumBytesToCreateFrame = Costs . FrameTailCall ; SetCandidateCallInfo ( MachineOutlinerTailCall , Costs . CallTailCall ) ; } else if ( LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> ) { FrameID = MachineOutlinerThunk ; NumBytesToCreateFrame = Costs . FrameThunk ; SetCandidateCallInfo ( MachineOutlinerThunk , Costs . CallThunk ) ; } else { unsigned NumBytesNoStackCalls = <NUM_LIT> ; std :: vector < outliner :: Candidate > CandidatesWithoutStackFixups ; for ( outliner :: Candidate & C : RepeatedSequenceLocs ) { C . initLRU ( TRI ) ; if ( C . LRU . available ( <STR_LIT> ) ) { FrameID = MachineOutlinerNoLRSave ; NumBytesNoStackCalls += Costs


<s> } Opc = isThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder CallMIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) ; if ( isThumb ) CallMIB . add ( predOps ( <STR_LIT> ) ) ; CallMIB . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; if ( C . CallConstructionID == MachineOutlinerRegSave ) { unsigned Reg = findRegisterToSaveLRTo ( C ) ; assert ( Reg != <NUM_LIT> && <STR_LIT> ) ; if ( ! MBB . isLiveIn ( <STR_LIT> )


<s> auto IsNonTailCall = [ ] ( MachineInstr & MI ) { return MI . isCall ( ) && ! MI . isReturn ( ) ; } ; if ( llvm :: any_of ( MBB . instrs ( ) , IsNonTailCall ) ) { MachineBasicBlock :: iterator It = MBB . begin ( ) ; MachineBasicBlock :: iterator Et = MBB . end ( ) ; if ( OF . FrameConstructionID == MachineOutlinerTailCall || OF . FrameConstructionID == MachineOutlinerThunk ) Et = std :: prev ( MBB . end ( ) ) ; if ( ! MBB . isLiveIn ( <STR_LIT> ) ) MBB . addLiveIn ( <STR_LIT> ) ; bool Auth = OF . Candidates . front ( ) . getMF ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> shouldSignReturnAddress ( true ) ; saveLROnStack ( MBB , It , true , Auth ) ; assert ( OF . FrameConstructionID !=


<s> if ( ! MRI . hasOneNonDBGUse ( Reg ) ) return nullptr ; MachineInstr * MI = MRI . getVRegDef ( Reg ) ; if ( ! MI ) return nullptr ; if ( ! isPredicable ( * MI ) ) return nullptr ; for ( const MachineOperand & MO : llvm :: drop_begin ( MI -> operands ( ) , <NUM_LIT> ) ) { if ( MO . isFI ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return nullptr ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isTied ( ) ) return nullptr ; if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) return nullptr ; if ( MO . isDef ( ) && ! MO . isDead


<s> for ( const MachineOperand & MO : MI . operands ( ) ) { bool ClobbersCPSR = MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ; bool IsCPSR = MO . isReg ( ) && MO . isDef ( ) && MO . getReg (


<s> } } else { const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; bool IsIndirect = Subtarget . isGVIndirectSymbol ( GV ) ; unsigned TargetFlags = <STR_LIT> ; if ( Subtarget . isTargetMachO ( ) ) { TargetFlags |= <STR_LIT> ; } else if ( Subtarget . isTargetCOFF ( ) ) { if ( GV -> hasDLLImportStorageClass ( ) ) TargetFlags |= <STR_LIT> ; else if ( IsIndirect ) TargetFlags |= <STR_LIT> ; } else if ( Subtarget . isGVInGOT ( GV ) ) { TargetFlags |= <STR_LIT> ; } BuildMI ( MBB , MI , DL , get ( LoadImmOpc ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , TargetFlags ) ; if ( IsIndirect ) { MIB = BuildMI ( MBB , MI , DL , get ( LoadOpc ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm


<s> Register SrcRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || ! SrcRegD ) return false ; if ( ! MI . definesRegister ( DstRegD , TRI ) || MI . readsRegister ( DstRegD , TRI ) ) return false ; if ( MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; MachineInstrBuilder MIB ( * MI . getParent ( ) -> getParent ( ) , MI ) ; int ImpDefIdx = MI . findRegisterDefOperandIdx ( DstRegD ) ; if ( ImpDefIdx != - <NUM_LIT> ) MI . RemoveOperand ( ImpDefIdx ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( DstRegD ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( SrcRegD ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; MIB . addReg ( SrcRegS , RegState


<s> if ( C . CallConstructionID == MachineOutlinerNoLRSave || C . CallConstructionID == MachineOutlinerThunk ) { It = MBB . insert ( It , CallMIB ) ; return It ; } const <ISA_LIT>FunctionInfo & AFI = * C . getMF ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( C . CallConstructionID == MachineOutlinerRegSave ) { unsigned Reg = findRegisterToSaveLRTo ( C ) ; assert ( Reg != <NUM_LIT> && <STR_LIT> ) ; copyPhysReg ( MBB , It , DebugLoc ( ) , Reg , <STR_LIT> , true ) ; if ( ! AFI . isLRSpilled ( ) ) emitCFIForLRSaveToReg ( MBB , It , Reg ) ; CallPt = MBB . insert ( It , CallMIB ) ; copyPhysReg ( MBB , It , DebugLoc ( ) , <STR_LIT> , Reg , true ) ; if ( ! AFI . isLRSpilled ( ) ) emitCFIForLRRestoreFromReg (


<s> if ( CFn . hasFnAttribute ( <STR_LIT> ) ) F . addFnAttr ( CFn . getFnAttribute ( <STR_LIT> ) ) ; <ISA_LIT>GenInstrInfo :: mergeOutliningCandidateAttributes ( F , Candidates


<s> bool Invert = ! DefMI ; if ( ! DefMI ) DefMI = canFoldIntoMOVCC ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; if ( ! DefMI ) return nullptr ; MachineOperand FalseReg = MI . getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; MachineOperand TrueReg = MI . getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * FalseClass = MRI . getRegClass ( FalseReg . getReg ( ) ) ; const TargetRegisterClass * TrueClass = MRI . getRegClass ( TrueReg . getReg ( ) ) ; if ( ! MRI . constrainRegClass ( DestReg , FalseClass ) ) return nullptr ; if ( ! MRI . constrainRegClass ( DestReg , TrueClass ) ) return nullptr ; MachineInstrBuilder NewMI = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . add ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( <STR_LIT> ( <STR_LIT> ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . add ( MI . getOperand ( <NUM_LIT> ) ) ; if ( NewMI -> hasOptionalDef ( ) ) NewMI . add ( condCodeOp ( ) ) ; FalseReg . setImplicit


<s> MachineInstr * <ISA_LIT>BaseInstrInfo :: optimizeSelect ( MachineInstr & MI , SmallPtrSetImpl < MachineInstr * > & SeenMIs , bool PreferFalse ) const { assert ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MachineInstr * DefMI = canFoldIntoMOVCC ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; bool Invert = ! DefMI ; if ( ! DefMI ) DefMI = canFoldIntoMOVCC ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; if ( ! DefMI ) return nullptr ; MachineOperand FalseReg = MI . getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; MachineOperand TrueReg = MI . getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * FalseClass = MRI . getRegClass ( FalseReg . getReg ( ) ) ; const TargetRegisterClass * TrueClass = MRI . getRegClass ( TrueReg . getReg ( ) ) ; if ( ! MRI . constrainRegClass ( DestReg , FalseClass ) ) return nullptr ; if ( ! MRI . constrainRegClass ( DestReg , TrueClass ) ) return nullptr ; MachineInstrBuilder NewMI = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . add ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( <STR_LIT> ( <STR_LIT> ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . add ( MI . getOperand ( <NUM_LIT> ) ) ; if ( NewMI -> hasOptionalDef ( ) ) NewMI . add ( condCodeOp ( ) ) ; FalseReg . setImplicit ( ) ; NewMI . add ( FalseReg ) ; NewMI -> tieOperands ( <NUM_LIT> , NewMI -> getNumOperands ( ) - <NUM_LIT> ) ; SeenMIs . insert ( NewMI ) ; SeenMIs . erase ( DefMI ) ; if ( DefMI -> getParent ( ) != MI .

getParent ( ) ) NewMI -> clearKillInfo ( ) ;


<s> if ( MI0 . getNumOperands ( ) != MI1 . getNumOperands ( ) ) return false ; const MachineOperand & MO0 = MI0 . getOperand ( <NUM_LIT> ) ; const MachineOperand & MO1 = MI1 . getOperand ( <NUM_LIT> ) ; if ( MO0 . getOffset ( ) != MO1 . getOffset ( ) ) return false ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return MO0 . getGlobal ( ) == MO1 . getGlobal ( ) ; const MachineFunction * MF = MI0 . getParent ( ) -> getParent ( ) ; const MachineConstantPool * MCP = MF -> getConstantPool ( ) ; int CPI0 = MO0 . getIndex ( ) ; int CPI1 = MO1 . getIndex ( ) ; const MachineConstantPoolEntry & MCPE0 = MCP -> getConstants ( ) [ CPI0 ] ; const MachineConstantPoolEntry & MCPE1 = MCP -> getConstants ( ) [ CPI1 ] ; bool is<ISA_LIT>CP0 = MCPE0 . isMachineConstantPoolEntry ( ) ; bool is<ISA_LIT>CP1 = MCPE1 . isMachineConstantPoolEntry ( ) ; if ( is<ISA_LIT>CP0 && is<ISA_LIT>CP1 ) { <ISA_LIT>ConstantPoolValue * ACPV0 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE0 . Val . MachineCPVal ) ; <ISA_LIT>ConstantPoolValue * ACPV1 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE1 . Val . MachineCPVal ) ; return ACPV0 -> hasSameValue ( ACPV1 ) ; } else if ( ! is<ISA_LIT>CP0 && ! is<ISA_LIT>CP1 ) { return MCPE0 . Val . ConstVal == MCPE1 . Val . ConstVal ; } return false ; } else if ( Opcode == <STR_LIT> ) { if ( MI1 . getOpcode ( ) != Opcode ) return false ; if ( MI0 . getNumOperands ( ) != MI1 . getNumOperands ( ) ) return false ; Register Addr0 = MI0 . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Addr1 = MI1 . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Addr0 != Addr1


<s> } else { unsigned Opc = Subtarget . isThumb ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , It , DebugLoc ( ) , get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; if ( ! Subtarget . isThumb ( ) ) MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Subtarget . getStackAlignment ( ) . value ( ) ) . add ( predOps ( <STR_LIT> ) ) . setMIFlags ( MachineInstr :: FrameDestroy ) ; } if ( CFI ) { MachineFunction & MF = * MBB . getParent ( ) ; const MCRegisterInfo * MRI = Subtarget . getRegisterInfo ( ) ; unsigned DwarfLR = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; int64_t StackPosEntry = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , <NUM_LIT> ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( StackPosEntry ) . setMIFlags ( MachineInstr :: FrameDestroy ) ; int64_t LRPosEntry = MF . addFrameInst ( MCCFIInstruction :: createRestore


<s> assert ( ( IsT1PushPop || ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; if ( NumBytes % ( IsVFPPushPop ? <NUM_LIT> : <NUM_LIT> ) != <NUM_LIT> ) return false ; int RegListIdx = IsT1PushPop ? <NUM_LIT> : <NUM_LIT> ; unsigned RegsNeeded ; const TargetRegisterClass * RegClass ; if ( IsVFPPushPop ) { RegsNeeded = NumBytes / <NUM_LIT> ; RegClass = & <STR_LIT> ; } else { RegsNeeded = NumBytes / <NUM_LIT> ; RegClass = & <STR_LIT> ; } SmallVector < MachineOperand , <NUM_LIT> > RegList ; unsigned FirstRegEnc = - <NUM_LIT> ; const TargetRegisterInfo * TRI = MF . getRegInfo ( ) . getTargetRegisterInfo ( ) ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx ; -- i ) { MachineOperand & MO = MI -> getOperand ( i ) ; RegList . push_back ( MO ) ; if ( MO . isReg ( ) && ! MO . isImplicit ( ) && TRI -> getEncodingValue ( MO . getReg ( ) ) < FirstRegEnc ) FirstRegEnc = TRI -> getEncodingValue ( MO . getReg ( ) ) ; } const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( int CurRegEnc = FirstRegEnc - <NUM_LIT> ; CurRegEnc >= <NUM_LIT> && RegsNeeded ; -- CurRegEnc ) { unsigned CurReg = RegClass -> getRegister ( CurRegEnc ) ; if ( IsT1PushPop && CurRegEnc > TRI -> getEncodingValue ( <STR_LIT> ) ) continue ; if ( ! IsPop ) { RegList . push_back ( MachineOperand :: CreateReg ( CurReg , false , false , false , false , true ) ) ; -- RegsNeeded ; continue ; } if ( isCalleeSavedRegister ( CurReg , CSRegs ) || MI -> getParent ( ) -> computeRegisterLiveness ( TRI , CurReg , MI ) != MachineBasicBlock :: LQR_Dead ) { if ( IsVFPPushPop ) return


<s> int Sign = <NUM_LIT> ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> ) Sign = - <NUM_LIT> ; else if ( Opcode != <STR_LIT> ) return None ; if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return None ; Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) * Sign ; return DestSourcePair { MI . getOperand ( <NUM_LIT> ) , MI . getOperand


<s> if ( RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> isTerminator ( ) ) { FrameID = MachineOutlinerTailCall ; NumBytesToCreateFrame = Costs . FrameTailCall ; SetCandidateCallInfo ( MachineOutlinerTailCall , Costs . CallTailCall ) ; } else if ( LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> ) { FrameID = MachineOutlinerThunk ; NumBytesToCreateFrame = Costs . FrameThunk ; SetCandidateCallInfo ( MachineOutlinerThunk , Costs . CallThunk ) ; } else { unsigned NumBytesNoStackCalls = <NUM_LIT> ; std :: vector < outliner :: Candidate > CandidatesWithoutStackFixups ; for ( outliner :: Candidate & C : RepeatedSequenceLocs ) { C . initLRU ( TRI ) ; const auto Last = C . getMBB ( ) -> rbegin ( ) ; const bool LRIsAvailable = C . getMBB ( ) -> isReturnBlock ( ) && ! Last -> isCall ( ) ? isLRAvailable ( TRI , Last , ( MachineBasicBlock :: reverse_iterator ) C . front ( ) ) : C . LRU . available ( <STR_LIT> ) ; if ( LRIsAvailable ) { FrameID = MachineOutlinerNoLRSave ; NumBytesNoStackCalls += Costs . CallNoLRSave ; C . setCallInfo ( MachineOutlinerNoLRSave , Costs . CallNoLRSave ) ; CandidatesWithoutStackFixups . push_back ( C ) ; } else if ( findRegisterToSaveLRTo ( C ) ) { FrameID = MachineOutlinerRegSave ; NumBytesNoStackCalls += Costs . CallRegSave ; C . setCallInfo ( MachineOutlinerRegSave , Costs . CallRegSave ) ; CandidatesWithoutStackFixups . push_back ( C ) ; } else if ( C . UsedInSequence . available ( <STR_LIT> ) ) { NumBytesNoStackCalls += Costs . CallDefault ; C . setCallInfo ( MachineOutlinerDefault , Costs . CallDefault ) ; SetCandidateCallInfo ( MachineOutlinerDefault , Costs . CallDefault ) ; CandidatesWithoutStackFixups . push_back ( C ) ; } else return outliner :: OutlinedFunction


<s> if ( I == MBB . begin ( ) ) return false ; -- I ; } MachineInstr * LastInst = I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( isIndirectBranchOpcode ( LastOpc ) ) return true ; if ( ! isUnpredicatedTerminator ( I ) ) return false ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( -- I ) ) { if ( isUncondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isCondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( AllowModify && isUncondBranchOpcode ( LastOpc ) ) { while ( isUncondBranchOpcode ( SecondLastOpc )


<s> switch ( RC -> getSize ( ) ) { case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB .

addReg ( DestReg , RegState :: ImplicitDefine ) ;


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT>


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return


<s> switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> :


<s> static inline bool isLoopStart ( MachineInstr & MI


<s> return MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode


<s> static inline bool isVCTP ( MachineInstr * MI ) { switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return false


<s> if ( ! MI ) return NULL ; MI -> getOperand ( MI -> findFirstPredOperandIdx ( ) ) . setImm ( <STR_LIT> ( CC ) ) ; return MI ; } } return TargetInstrInfoImpl :: commuteInstruction (


<s> else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; if ( Opc ) { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) ; MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; if ( Opc == <STR_LIT> ) MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; AddDefaultPred ( MIB ) ; return ; } unsigned BeginIdx = <NUM_LIT> ; unsigned SubRegs = <NUM_LIT> ; int Spacing = <NUM_LIT> ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> , Spacing = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> , Spacing = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> , Spacing = <NUM_LIT> ; assert ( Opc && <STR_LIT> ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; MachineInstrBuilder Mov ; if ( TRI -> regsOverlap ( SrcReg , TRI -> getSubReg ( DestReg , BeginIdx ) ) ) { BeginIdx = BeginIdx + ( ( SubRegs - <NUM_LIT> ) * Spacing ) ; Spacing = - Spacing ; } SmallSet < unsigned , <NUM_LIT> > DstRegs ; for ( unsigned i = <NUM_LIT> ; i != SubRegs ; ++ i ) { unsigned Dst = TRI -> getSubReg ( DestReg , BeginIdx + i *


<s> Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; } else if ( I -> isReturn ( ) ) { CantAnalyze = true ; } else { return true ; } if ( ! isPredicated ( * I ) && ( isUncondBranchOpcode ( I -> getOpcode ( ) ) || isIndirectBranchOpcode ( I -> getOpcode ( ) ) || isJumpTableBranchOpcode ( I -> getOpcode ( ) ) || I -> isReturn ( ) ) ) { Cond . clear ( ) ; FBB = nullptr ; if ( AllowModify ) { MachineBasicBlock :: iterator DI = std :: next ( I ) ; while ( DI != MBB . instr_end ( ) ) { MachineInstr & InstToDelete = * DI ; ++ DI ; if ( isSpeculationBarrierEndBBOpcode ( InstToDelete . getOpcode ( ) ) ) continue ; InstToDelete . eraseFromParent ( ) ; } } } if ( CantAnalyze


<s> bool isThumb = Subtarget . isThumb ( ) ; unsigned FuncOp = isThumb ? <NUM_LIT> : <NUM_LIT> ; unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? <STR_LIT> : <STR_LIT> : isThumb ? Subtarget . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ; if ( isThumb && ! Call -> getOperand ( FuncOp ) . isReg ( ) ) MIB . add ( predOps ( <STR_LIT> ) ) ; Call -> eraseFromParent ( ) ; } auto IsNonTailCall = [ ] ( MachineInstr & MI ) { return MI . isCall ( ) && ! MI . isReturn ( ) ; } ; if ( llvm :: any_of ( MBB . instrs ( ) , IsNonTailCall ) ) { MachineBasicBlock :: iterator It = MBB . begin ( ) ; MachineBasicBlock :: iterator Et = MBB . end


<s> unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? <STR_LIT> : <STR_LIT> : isThumb ? Subtarget . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ; if ( isThumb && ! Call -> getOperand ( FuncOp ) . isReg ( ) ) MIB . add ( predOps ( <STR_LIT> ) ) ; Call -> eraseFromParent ( ) ; } auto IsNonTailCall = [ ] ( MachineInstr & MI ) { return MI . isCall ( ) && ! MI . isReturn ( ) ; } ; if ( llvm :: any_of ( MBB . instrs ( ) , IsNonTailCall ) ) { MachineBasicBlock :: iterator It = MBB . begin ( ) ; MachineBasicBlock :: iterator Et = MBB . end


<s> if ( C . CallConstructionID == MachineOutlinerTailCall ) { Opc = isThumb ? Subtarget . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; if ( isThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; It = MBB . insert ( It , MIB ) ; return It ; } Opc = isThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder CallMIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) ; if ( isThumb ) CallMIB . add ( predOps ( <STR_LIT> ) ) ; CallMIB . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; if ( C . CallConstructionID == MachineOutlinerNoLRSave || C . CallConstructionID == MachineOutlinerThunk ) { It = MBB . insert ( It , CallMIB ) ; return It


<s> -- I ; } if ( ! isUnpredicatedTerminator ( I ) ) return false ; MachineInstr * LastInst = I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( -- I ) ) { if ( isUncondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isCondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true


<s> DebugLoc dl ; <ISA_LIT>FunctionInfo * AFI = MBB . getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; int BOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : ( AFI -> isThumb2Function ( ) ? <STR_LIT> : <STR_LIT> ) ; int BccOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : ( AFI -> isThumb2Function ( ) ? <STR_LIT> : <STR_LIT> ) ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( FBB ==


<s> void <ISA_LIT>BaseInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , MFI . getObjectSize ( FI ) , Align ) ; if ( RC == <STR_LIT> ) RC = <STR_LIT> ; if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( RC == <STR_LIT> || RC == <STR_LIT> || RC


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , MFI . getObjectSize ( FI ) , Align ) ; if ( RC == <STR_LIT> ) RC = <STR_LIT> ; if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( RC == <STR_LIT> || RC == <STR_LIT> || RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else { assert ( ( RC == <STR_LIT> || RC == <STR_LIT> ) && <STR_LIT> ) ; if ( Align >= <NUM_LIT> && ( getRegisterInfo ( ) . canRealignStack (


<s> DebugLoc dl = MI -> getDebugLoc ( ) ; MachineBasicBlock * BB = MI -> getParent ( ) ; MachineInstrBuilder LDM , STM ; if ( isThumb1 || ! MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) { MachineOperand LDWb ( MI -> getOperand ( <NUM_LIT> ) ) ; LDM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ) ) . add ( LDWb ) ; } else { LDM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) ; } if ( isThumb1 || ! MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) { MachineOperand STWb ( MI -> getOperand ( <NUM_LIT> ) ) ; STM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ) ) . add ( STWb ) ; } else { STM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) ; } MachineOperand LDBase ( MI -> getOperand ( <NUM_LIT> ) ) ; LDM . add ( LDBase ) . add ( predOps ( <STR_LIT> ) ) ; MachineOperand STBase ( MI -> getOperand (


<s> { MO_GOT , <STR_LIT> } , { MO_SBREL , <STR_LIT> } , { MO_DLLIMPORT , <STR_LIT> } , { MO_SECREL , <STR_LIT> } , { MO_NONLAZY , <STR_LIT> } } ; return makeArrayRef ( TargetFlags )


<s> bool <ISA_LIT>BaseInstrInfo :: isCopyInstr ( const MachineInstr & MI , const MachineOperand * & Src , const MachineOperand * & Dest ) const { if ( ! MI . isMoveReg ( ) || ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) != MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; Dest = & MI . getOperand ( <NUM_LIT> ) ; Src = & MI . getOperand ( <NUM_LIT>


<s> bool <ISA_LIT>BaseInstrInfo :: isCopyInstr ( const MachineInstr & MI , const MachineOperand * & Src , const MachineOperand * & Dest ) const { if ( ! MI . isMoveReg ( ) || ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) != MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; Dest = & MI . getOperand ( <NUM_LIT> ) ; Src = & MI . getOperand ( <NUM_LIT> ) ; return


<s> switch ( AddrMode ) { case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) ; case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) && Imm % <NUM_LIT> == <NUM_LIT> ; case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) && Imm % <NUM_LIT> == <NUM_LIT> ; case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) ; case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) *


<s> unsigned Reg = MO . getReg ( ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) && <STR_LIT> ) ; unsigned DReg = Reg ; if ( <STR_LIT> . contains ( Reg ) ) { DReg = <STR_LIT> + ( Reg - <STR_LIT> ) / <NUM_LIT> ; assert ( TRI -> isSuperRegister ( Reg , DReg ) && <STR_LIT> ) ; } assert ( <STR_LIT> . contains ( DReg ) && <STR_LIT> ) ; assert ( MI . definesRegister ( DReg , TRI ) && <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) , DReg ) .

addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ;


<s> MachineInstrBuilder MIB = BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( Opc ) , DestReg ) ; if ( Subtarget . isMClass ( ) ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Implicit | getKillRegState


<s> if ( Subtarget . isMClass ( ) ) MIB . addImm ( <NUM_LIT> ) ; else MIB . addImm ( <NUM_LIT> ) ; MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps (

<STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) ;


<s> const unsigned Mask = <STR_LIT> ; return std :: make_pair ( TF &


<s> switch ( I -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CPI = I -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; I -> getOperand ( <NUM_LIT> ) . setIndex ( CPI ) ; I -> getOperand ( <NUM_LIT> ) . setImm ( PCLabelId ) ; break ; } } if ( ! I -> isBundledWithSucc ( ) )


<s> if ( ACPV -> isGlobalValue ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getGV ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> , ACPV -> getModifier ( ) , ACPV -> mustAddCurrentAddress ( ) ) ; else if ( ACPV -> isExtSymbol ( ) ) NewCPV = <ISA_LIT>ConstantPoolSymbol :: Create ( MF . getFunction ( ) . getContext ( ) , cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) , PCLabelId , <NUM_LIT> ) ; else if ( ACPV -> isBlockAddress ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getBlockAddress ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isLSDA ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( & MF . getFunction ( ) , PCLabelId ,


<s> if ( NumBytes == <NUM_LIT> && DestReg != BaseReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . add ( predOps ( Pred , PredReg ) ) . add ( condCodeOp ( ) ) . setMIFlags ( MIFlags ) ; return ; } bool isSub = NumBytes < <NUM_LIT> ; if ( isSub ) NumBytes = - NumBytes ; while ( NumBytes ) { unsigned RotAmt = <STR_LIT> ( NumBytes ) ; unsigned ThisVal = NumBytes & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; assert ( ThisVal && <STR_LIT> ) ; NumBytes &= ~ ThisVal


<s> void <ISA_LIT>BaseInstrInfo :: expandLoadStackGuardBase ( MachineBasicBlock :: iterator MI , unsigned LoadImmOpc , unsigned LoadOpc ) const { assert ( ! Subtarget . isROPI ( ) && ! Subtarget . isRWPI ( ) && <STR_LIT> ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; MachineInstrBuilder MIB ; BuildMI ( MBB , MI , DL , get ( LoadImmOpc ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; if ( Subtarget . isGVIndirectSymbol ( GV ) ) { MIB = BuildMI ( MBB , MI , DL , get ( LoadOpc ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( * MBB . getParent ( ) ) , Flags , <NUM_LIT> , <NUM_LIT> ) ; MIB . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } MIB = BuildMI ( MBB , MI , DL


<s> } else { STM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) ; } MachineOperand LDBase ( MI -> getOperand ( <NUM_LIT> ) ) ; LDM . add ( LDBase ) . add ( predOps ( <STR_LIT> ) ) ; MachineOperand STBase ( MI -> getOperand ( <NUM_LIT> ) ) ; STM . add ( STBase ) . add ( predOps ( <STR_LIT> ) ) ; const TargetRegisterInfo & TRI = getRegisterInfo ( ) ; SmallVector < unsigned , <NUM_LIT> > ScratchRegs ; for ( unsigned I = <NUM_LIT> ; I < MI -> getNumOperands ( ) ; ++ I ) ScratchRegs . push_back ( MI -> getOperand ( I ) . getReg ( ) ) ; llvm :: sort ( ScratchRegs , [ & TRI ] ( const unsigned & Reg1 , const unsigned & Reg2 ) -> bool { return TRI . getEncodingValue ( Reg1 ) < TRI . getEncodingValue ( Reg2 ) ; } ) ; for ( const auto & Reg


<s> expandLoadStackGuard ( MI ) ; MI . getParent ( ) -> erase ( MI ) ; return true ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { expandMEMCPY ( MI ) ; return true ; } if ( ! MI . isCopy ( ) || Subtarget . dontWidenVMOVS ( ) || Subtarget . isFPOnlySP ( ) ) return false ; unsigned DstRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || ! SrcRegD ) return false ; if ( ! MI . definesRegister ( DstRegD , TRI ) || MI . readsRegister ( DstRegD , TRI ) ) return false ; if ( MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; MachineInstrBuilder MIB ( * MI . getParent ( ) -> getParent ( ) , MI ) ; int ImpDefIdx = MI . findRegisterDefOperandIdx


<s> case <STR_LIT> : { Commute = UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) != Reg ; switch ( UseOpc ) { default : break ; case <STR_LIT> : case <STR_LIT> : if ( UseOpc == <STR_LIT> && Commute ) return false ; if ( <STR_LIT> ( ImmVal ) ) NewUseOpc = UseOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> ( - ImmVal ) ) { ImmVal = - ImmVal ; NewUseOpc = UseOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! <STR_LIT> ( ImmVal ) ) return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; switch ( UseOpc ) { default : break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; } break ; case <STR_LIT> : case <STR_LIT> : if ( UseOpc == <STR_LIT> && Commute ) return false ; if ( <STR_LIT> ( ImmVal ) ) NewUseOpc = UseOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> ( - ImmVal ) ) { ImmVal = - ImmVal ; NewUseOpc = UseOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! <STR_LIT> ( ImmVal ) ) return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; switch ( UseOpc ) { default : break ; case <STR_LIT> : NewUseOpc =


<s> bool <ISA_LIT>BaseInstrInfo :: getExtractSubregLikeInputs ( const MachineInstr & MI , unsigned DefIdx , RegSubRegPairAndIdx & InputReg ) const { assert ( DefIdx < MI . getDesc ( ) . getNumDefs ( ) && <STR_LIT> ) ; assert ( MI . isExtractSubregLike ( ) && <STR_LIT> ) ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : const MachineOperand & MOReg = MI . getOperand ( <NUM_LIT> ) ; if ( MOReg . isUndef ( ) ) return false ; InputReg . Reg = MOReg . getReg ( ) ; InputReg . SubReg = MOReg . getSubReg ( ) ; InputReg . SubIdx = DefIdx == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; return


<s> const MachineOperand & MOInsertedReg = MI . getOperand ( <NUM_LIT> ) ; if ( MOInsertedReg . isUndef ( ) ) return false ; const MachineOperand & MOIndex = MI . getOperand ( <NUM_LIT> ) ; BaseReg . Reg = MOBaseReg . getReg ( ) ; BaseReg . SubReg = MOBaseReg . getSubReg ( ) ; InsertedReg . Reg = MOInsertedReg . getReg ( ) ; InsertedReg . SubReg = MOInsertedReg . getSubReg ( ) ; InsertedReg . SubIdx = MOIndex . getImm (


<s> unsigned Size = <NUM_LIT> ; MachineBasicBlock :: const_instr_iterator I = MI . getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI . getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) { assert ( ! I -> isBundle


<s> unsigned <ISA_LIT>BaseInstrInfo :: getLDMVariableDefsSize ( const MachineInstr & MI ) const { return MI . getNumOperands ( ) + <NUM_LIT> - MI . getDesc ( ) . getNumOperands


<s> if ( MF -> getFunction ( ) . hasFnAttribute ( Attribute :: OptimizeForSize ) ) -- Latency ; } return Latency ; } if ( DefMO . isImplicit ( ) || UseMI . getOperand ( UseIdx ) . isImplicit ( ) ) return - <NUM_LIT> ; unsigned DefAlign = DefMI . hasOneMemOperand ( ) ? ( * DefMI . memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; unsigned UseAlign = UseMI . hasOneMemOperand ( ) ? ( * UseMI . memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; int Latency = getOperandLatency ( ItinData , DefMCID , DefIdx , DefAlign , UseMCID , UseIdx , UseAlign ) ; if ( Latency < <NUM_LIT> ) return Latency ; int Adj = DefAdj +


<s> unsigned <ISA_LIT>BaseInstrInfo :: getPredicationCost ( const MachineInstr & MI ) const { if ( MI . isCopyLike ( ) || MI . isInsertSubreg ( ) || MI . isRegSequence ( ) ||

MI . isImplicitDef ( ) ) return <NUM_LIT> ;


<s> if ( MI . isBundle ( ) ) return <NUM_LIT> ; const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( MCID . isCall ( ) || ( MCID . hasImplicitDefOfPhysReg ( <STR_LIT> ) && ! Subtarget . cheapPredicableCPSRDef ( ) ) ) { return


<s> assert ( DefIdx < MI . getDesc ( ) . getNumDefs ( ) && <STR_LIT> ) ; assert ( MI . isRegSequenceLike ( ) && <STR_LIT> ) ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : const MachineOperand * MOReg = & MI . getOperand ( <NUM_LIT> ) ; if ( ! MOReg -> isUndef ( ) ) InputRegs . push_back ( RegSubRegPairAndIdx ( MOReg -> getReg ( ) , MOReg -> getSubReg ( ) , <STR_LIT> ) ) ; MOReg = & MI . getOperand ( <NUM_LIT> ) ; if ( ! MOReg -> isUndef ( ) ) InputRegs . push_back ( RegSubRegPairAndIdx ( MOReg -> getReg ( ) , MOReg -> getSubReg ( ) , <STR_LIT> ) ) ; return


<s> bool <ISA_LIT>BaseInstrInfo :: getRegSequenceLikeInputs ( const MachineInstr & MI , unsigned DefIdx , SmallVectorImpl < RegSubRegPairAndIdx > & InputRegs ) const { assert ( DefIdx < MI . getDesc ( ) . getNumDefs ( ) && <STR_LIT> ) ; assert ( MI . isRegSequenceLike ( ) && <STR_LIT> ) ; switch ( MI .


<s> using namespace <ISA_LIT>II ; static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_COFFSTUB , <STR_LIT> } , { MO_GOT , <STR_LIT> } , { MO_SBREL , <STR_LIT> } , { MO_DLLIMPORT , <STR_LIT> } , { MO_SECREL , <STR_LIT>


<s> bool <ISA_LIT>BaseInstrInfo :: isAddrMode3OpImm ( const MachineInstr & MI , unsigned Op ) const { const MachineOperand & Offset = MI .


<s> bool <ISA_LIT>BaseInstrInfo :: isAddrMode3OpMinusReg ( const MachineInstr & MI , unsigned Op ) const { const MachineOperand & Offset = MI . getOperand ( Op + <NUM_LIT> ) ; const MachineOperand & Opc = MI . getOperand ( Op + <NUM_LIT> ) ; assert ( Opc . isImm ( ) ) ; assert ( Offset . isReg ( ) ) ; int64_t OpcImm = Opc . getImm ( ) ; bool isSub = <STR_LIT> ( OpcImm ) == <STR_LIT> ; return ( isSub && Offset . getReg ( )


<s> bool <ISA_LIT>BaseInstrInfo :: isAm2ScaledReg ( const MachineInstr & MI , unsigned Op ) const { unsigned OffImm = MI . getOperand ( Op + <NUM_LIT> )


<s> bool <ISA_LIT>BaseInstrInfo :: isCopyInstrImpl ( const MachineInstr & MI , const MachineOperand * & Src , const MachineOperand * & Dest ) const { if ( ! MI . isMoveReg ( ) || ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) != MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; Dest = & MI . getOperand ( <NUM_LIT> ) ; Src = & MI .


<s> bool <ISA_LIT>BaseInstrInfo :: isCPSRDefined ( const MachineInstr & MI ) { for ( const auto & MO : MI . operands ( ) ) if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT>

&& MO . isDef ( ) && ! MO . isDead ( ) ) return true ;


<s> for ( const auto & MO : MI . operands ( ) ) if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> && MO . isDef ( ) && ! MO . isDead ( ) ) return true ; return


<s> default : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> unsigned OffImm = Opc . getImm ( ) ; return <STR_LIT> ( OffImm )