<s> const MachineOperand & Opc = MI . getOperand ( Op + <NUM_LIT> ) ; unsigned OffImm = Opc . getImm ( ) ; bool isAdd = <STR_LIT> ( OffImm ) == <STR_LIT> ; unsigned Amt = <STR_LIT> ( OffImm ) ; <STR_LIT> ShiftOpc = <STR_LIT> ( OffImm ) ; if ( ShiftOpc == <STR_LIT>


<s> const MachineOperand & Opc = MI . getOperand ( Op + <NUM_LIT> ) ; unsigned OffImm = Opc . getImm ( ) ; bool isAdd = <STR_LIT> (


<s> bool <ISA_LIT>BaseInstrInfo :: isLdstSoMinusReg ( const MachineInstr & MI , unsigned Op ) const { unsigned OffImm = MI . getOperand ( Op + <NUM_LIT> ) . getImm ( ) ; return <STR_LIT> ( OffImm


<s> unsigned <ISA_LIT>BaseInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { SmallVector < const MachineMemOperand * , <NUM_LIT> > Accesses ; if ( MI . mayLoad ( ) && hasLoadFromStackSlot ( MI , Accesses ) ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ; return true ; } return false


<s> SmallVector < const MachineMemOperand * , <NUM_LIT> > Accesses ; if ( MI . mayLoad ( ) && hasLoadFromStackSlot ( MI , Accesses ) ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) ->


<s> bool <ISA_LIT>BaseInstrInfo :: isPredicable ( const MachineInstr & MI ) const { if ( ! MI . isPredicable ( ) ) return false ; if ( MI . isBundle ( ) ) return false ; if ( ! isEligibleForITBlock ( & MI ) ) return false ; const <ISA_LIT>FunctionInfo * AFI = MI . getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) return false ; if ( AFI -> isThumb2Function ( ) ) { if ( getSubtarget ( ) . restrictIT ( ) ) return


<s> TUnpredCycles = TCycles + NotTakenBranchCost ; FUnpredCycles = TakenBranchCost ; } else { TUnpredCycles = TCycles + TakenBranchCost ; FUnpredCycles = FCycles + NotTakenBranchCost ; PredCost -= <NUM_LIT> * ScalingUpFactor ; } unsigned TUnpredCost = Probability . scale ( TUnpredCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FUnpredCycles * ScalingUpFactor ) ; UnpredCost = TUnpredCost + FUnpredCost ; if ( Subtarget . isThumb2 ( ) && TCycles + FCycles > <NUM_LIT> ) { PredCost += ( ( TCycles + FCycles - <NUM_LIT> ) / <NUM_LIT> ) * ScalingUpFactor ; } } else { unsigned TUnpredCost = Probability . scale


<s> if ( ( CmpI -> getOpcode ( ) == <STR_LIT> || CmpI -> getOpcode ( ) == <STR_LIT> ) && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && ( ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) || ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && OI

-> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ) ) return true ;


<s> if ( ( CmpI -> getOpcode ( ) == <STR_LIT> || CmpI -> getOpcode ( ) == <STR_LIT> ) && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && ( ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) || ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ) ) return true ; if ( ( CmpI -> getOpcode ( ) == <STR_LIT> || CmpI -> getOpcode ( ) == <STR_LIT> ) && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT>

) . getImm ( ) == ImmValue ) return true ;


<s> MachineBasicBlock :: const_iterator I = MI ; while ( ++ I != MBB -> end ( ) && I -> isDebugInstr ( ) ) ; if ( I != MBB -> end ( ) && I -> getOpcode ( ) == <STR_LIT> ) return true ; if ( ! MI . isCall ( ) && MI . definesRegister ( <STR_LIT> ) ) return true ; return false


<s> if ( MI . isDebugInstr ( ) ) return false ; if ( MI . isTerminator ( ) || MI . isPosition ( ) ) return true ; MachineBasicBlock :: const_iterator I = MI ; while ( ++ I != MBB -> end ( ) && I


<s> if ( MI . mayStore ( ) && hasStoreToStackSlot ( MI , Accesses ) ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ; return true


<s> break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . add ( predOps ( <STR_LIT> ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . add ( predOps ( <STR_LIT> ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; } else llvm_unreachable ( <STR_LIT>


<s> assert ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MachineInstr * DefMI = canFoldIntoMOVCC ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; bool Invert = ! DefMI ; if ( ! DefMI ) DefMI = canFoldIntoMOVCC ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; if ( ! DefMI ) return nullptr ; MachineOperand FalseReg = MI . getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * PreviousClass = MRI . getRegClass ( FalseReg . getReg ( ) ) ; if ( ! MRI . constrainRegClass ( DestReg , PreviousClass ) ) return nullptr ; MachineInstrBuilder NewMI = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . add ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( <STR_LIT> ( <STR_LIT> ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . add ( MI . getOperand ( <NUM_LIT> ) ) ; if ( NewMI -> hasOptionalDef ( ) ) NewMI . add ( condCodeOp ( ) ) ; FalseReg . setImplicit ( ) ; NewMI . add ( FalseReg ) ; NewMI -> tieOperands ( <NUM_LIT> , NewMI -> getNumOperands ( ) - <NUM_LIT> ) ; SeenMIs . insert ( NewMI


<s> if ( I == MBB . end ( ) ) return <NUM_LIT> ; if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( )


<s> if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end (


<s> MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . RemoveOperand ( FrameRegIdx + <NUM_LIT> ) ; Offset = <NUM_LIT> ; return true ; } else if ( Offset < <NUM_LIT> ) { Offset = - Offset ; isSub = true ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; } if ( <STR_LIT> ( Offset ) != - <NUM_LIT> ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; Offset = <NUM_LIT> ; return true ; } unsigned RotAmt = <STR_LIT> ( Offset ) ; unsigned ThisImmVal = Offset & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; Offset &= ~ ThisImmVal ; assert ( <STR_LIT> ( ThisImmVal ) != - <NUM_LIT> && <STR_LIT> ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( ThisImmVal ) ; } else { unsigned ImmIdx = <NUM_LIT> ; int InstrOffs = <NUM_LIT> ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; switch ( AddrMode ) { case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : return false ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx


<s> ++ Next ; unsigned SrcReg , SrcReg2 ; int CmpMask , CmpValue ; if ( Next != MI . getParent ( ) -> end ( ) && analyzeCompare ( * Next , SrcReg , SrcReg2 ,

CmpMask , CmpValue ) && isRedundantFlagInstr ( & * Next , SrcReg , SrcReg2 , CmpValue , & MI ) ) return false ;


<s> AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { BuildMI ( MBB , I , DebugLoc ( ) , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else { BuildMI ( MBB , I , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { BuildMI ( MBB , I , DebugLoc ( ) , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else { MachineInstrBuilder MIB = BuildMI ( MBB , I , DebugLoc ( ) , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . add ( predOps ( <STR_LIT> ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { BuildMI ( MBB , I , DebugLoc ( ) , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else { MachineInstrBuilder MIB = BuildMI ( MBB , I , DebugLoc ( ) , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . add ( predOps ( <STR_LIT> ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg ,


<s> const MachineSDNode * DefMN = dyn_cast < MachineSDNode > ( DefNode ) ; unsigned DefAlign = ! DefMN -> memoperands_empty ( ) ? ( * DefMN -> memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; const MachineSDNode * UseMN = dyn_cast < MachineSDNode > ( UseNode ) ; unsigned UseAlign = ! UseMN -> memoperands_empty ( ) ? ( * UseMN -> memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; int Latency = getOperandLatency ( ItinData , DefMCID , DefIdx , DefAlign , UseMCID , UseIdx , UseAlign ) ; if ( Latency > <NUM_LIT> && ( Subtarget . isCortexA8 ( ) || Subtarget . isCortexA9 ( ) ) ) { switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned ShOpVal = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned ShImm = <STR_LIT> ( ShOpVal ) ; if ( ShImm == <NUM_LIT> || ( ShImm == <NUM_LIT> && <STR_LIT> ( ShOpVal ) == <STR_LIT> ) ) -- Latency ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned ShAmt = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( ShAmt == <NUM_LIT> || ShAmt == <NUM_LIT> ) -- Latency ; break ; } } } if ( DefAlign < <NUM_LIT> && Subtarget . isCortexA9 ( ) ) switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return Opc == <STR_LIT> || Opc == <STR_LIT> ||


<s> bool isPredicated ( const MachineInstr * MI ) const { int PIdx = MI ->


<s> int PIdx = MI -> findFirstPredOperandIdx ( ) ; return PIdx != - <NUM_LIT> && MI -> getOperand ( PIdx


<s> bool <ISA_LIT>BaseInstrInfo :: isAddImmediate ( const MachineInstr & MI , const MachineOperand * & Destination , const MachineOperand * & Source , int64_t & Offset ) const { int Sign = <NUM_LIT> ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> ) Sign = - <NUM_LIT> ; else if ( Opcode != <STR_LIT> ) return false ; if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isImm


<s> if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; Destination = & MI . getOperand ( <NUM_LIT> ) ; Source = & MI . getOperand ( <NUM_LIT> ) ; Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) * Sign ; return


<s> return { { MachineOperand :: CreateImm ( static_cast < int64_t > ( Pred ) ) , MachineOperand :: CreateReg ( PredReg


<s> return { { MachineOperand :: CreateImm ( static_cast < int64_t > ( Pred ) ) , MachineOperand

:: CreateReg ( PredReg , <NUM_LIT> ) } } ;


<s> return ( IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID ==

<STR_LIT> || IntrinsicID == <STR_LIT> ) ;


<s> inline bool isLegalAddressImm ( unsigned Opcode , int Imm , const TargetInstrInfo * TII ) { const MCInstrDesc & Desc = TII -> get ( Opcode ) ; unsigned AddrMode = ( Desc . TSFlags & <STR_LIT> ) ; switch ( AddrMode ) { case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT>


<s> default : break ; case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg


<s> FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; } return


<s> TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isUncondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } if ( isJumpTableBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return true ; } return true


<s> } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) { return true ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { return true ; } else if ( Opc == <STR_LIT>


<s> if ( DestRC != SrcRC ) { if ( ( ( DestRC == <STR_LIT> ) && ( SrcRC == <STR_LIT> ) ) || ( ( SrcRC == <STR_LIT> ) && ( DestRC == <STR_LIT> ) ) ) { } else { return false ; } } if ( DestRC == <STR_LIT> ) { AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ) ; } else if ( DestRC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; } else if ( ( DestRC == <STR_LIT> ) || ( DestRC == <STR_LIT> ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) .


<s> return false ; } } if ( DestRC == <STR_LIT> ) { AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ) ; } else if ( DestRC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; } else if ( ( DestRC == <STR_LIT> ) || ( DestRC == <STR_LIT> ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; } else if ( DestRC ==


<s> int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( PIdx == - <NUM_LIT> ) { PredReg = <NUM_LIT> ; return <STR_LIT> ; } PredReg = MI -> getOperand ( PIdx + <NUM_LIT>


<s> unsigned <ISA_LIT>BaseInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT>


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; } else if ( RC == <STR_LIT> || RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ) ; } else if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ) ; } else


<s> void <ISA_LIT>BaseInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; } else if ( RC == <STR_LIT> || RC == <STR_LIT>


<s> virtual bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCyles

, float Probability , float Confidence ) const {


<s> unsigned SrcRegS = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || ! SrcRegD ) return false ; if ( ! MI -> definesRegister ( DstRegD , TRI ) || MI -> readsRegister ( DstRegD , TRI ) ) return false ; if ( MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MachineInstrBuilder MIB ( * MI -> getParent ( ) -> getParent ( ) , MI ) ; int ImpDefIdx = MI -> findRegisterDefOperandIdx ( DstRegD ) ; if ( ImpDefIdx != - <NUM_LIT> )


<s> MI -> setDesc ( get ( <STR_LIT> ) ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( DstRegD ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( SrcRegD ) ; AddDefaultPred ( MIB ) ; MI -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; MIB . addReg ( SrcRegS , RegState :: Implicit ) ; if ( MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) { MI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; MI -> addRegisterKilled ( SrcRegS , TRI , true ) ; } DEBUG ( dbgs ( ) << <STR_LIT> << *


<s> FUnpredCycles = FCycles + NotTakenBranchCost ; } unsigned TUnpredCost = Probability . scale ( TUnpredCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FUnpredCycles * ScalingUpFactor ) ; UnpredCost = TUnpredCost + FUnpredCost ; if ( Subtarget . isThumb2 ( ) && TCycles + FCycles > <NUM_LIT> ) { PredCost += ( ( TCycles + FCycles - <NUM_LIT> ) / <NUM_LIT> ) * ScalingUpFactor ; } } else { unsigned TUnpredCost = Probability . scale ( TCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FCycles * ScalingUpFactor ) ; UnpredCost = TUnpredCost


<s> bool <ISA_LIT>BaseInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TBB , unsigned TCycles , unsigned TExtra , MachineBasicBlock & FBB , unsigned FCycles , unsigned FExtra , BranchProbability Probability ) const { if ( ! TCycles ) return false ; const unsigned ScalingUpFactor = <NUM_LIT> ; unsigned PredCost = ( TCycles + FCycles + TExtra + FExtra ) * ScalingUpFactor ; unsigned UnpredCost ; if ( ! Subtarget . hasBranchPredictor ( ) ) { unsigned NotTakenBranchCost = <NUM_LIT>


<s> case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) && Imm % <NUM_LIT> == <NUM_LIT> ; case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) && Imm % <NUM_LIT> == <NUM_LIT> ; case <STR_LIT>


<s> bool isUnspillableTerminatorImpl ( const MachineInstr * MI


<s> static inline bool isLowOverheadTerminatorOpcode ( int Opc ) { return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ||


<s> bool isUnspillableTerminatorImpl ( const MachineInstr * MI ) const override { return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI ->


<s> switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpValue = MI -> getOperand ( <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; } return


<s> } if ( Load1 -> getOperand ( <NUM_LIT> ) != Load2 -> getOperand ( <NUM_LIT> ) || Load1 -> getOperand ( <NUM_LIT> ) != Load2 -> getOperand ( <NUM_LIT> ) ) return false ; if ( Load1 -> getOperand ( <NUM_LIT> ) != Load2 -> getOperand ( <NUM_LIT> ) ) return false ; if ( isa < ConstantSDNode > ( Load1 -> getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( Load2 -> getOperand ( <NUM_LIT> ) ) ) { Offset1 = cast < ConstantSDNode > ( Load1 -> getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; Offset2 = cast < ConstantSDNode > ( Load2 -> getOperand ( <NUM_LIT> )


<s> bool <ISA_LIT>BaseInstrInfo :: ConvertToSetZeroFlag ( MachineInstr * MI , MachineInstr * CmpInstr ) const { if ( MI -> getParent ( ) != CmpInstr -> getParent ( ) ) return false ; MachineBasicBlock :: const_iterator I = CmpInstr , E = MI , B = MI -> getParent ( ) -> begin ( ) ; -- I ; for ( ; I != E ; -- I ) { const MachineInstr & Instr =


<s> MachineInstr * MemMI = NULL ; unsigned AddrMode = ( TSFlags & <STR_LIT> ) ; const TargetInstrDesc & TID = MI -> getDesc ( ) ; unsigned NumOps = TID . getNumOperands ( ) ; bool isLoad = ! TID . mayStore ( ) ; const MachineOperand & WB = isLoad ? MI -> getOperand ( <NUM_LIT> ) : MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & Base = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & Offset = MI -> getOperand ( NumOps - <NUM_LIT> ) ; unsigned WBReg = WB . getReg ( ) ; unsigned BaseReg = Base . getReg ( ) ; unsigned OffReg = Offset . getReg ( ) ; unsigned OffImm = MI -> getOperand ( NumOps - <NUM_LIT> ) . getImm ( ) ; <STR_LIT> Pred = ( <STR_LIT> ) MI -> getOperand ( NumOps - <NUM_LIT> ) . getImm ( ) ; switch ( AddrMode ) { default : assert ( false && <STR_LIT> ) ; return NULL ; case <STR_LIT> : { bool isSub = <STR_LIT> ( OffImm ) == <STR_LIT> ; unsigned Amt = <STR_LIT> ( OffImm ) ; if ( OffReg == <NUM_LIT> ) { if ( <STR_LIT> ( Amt ) == - <NUM_LIT> ) return NULL ; UpdateMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isSub ? <STR_LIT> : <STR_LIT> ) , WBReg ) . addReg ( BaseReg ) . addImm ( Amt ) . addImm ( Pred ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } else if ( Amt != <NUM_LIT> ) { <STR_LIT> ShOpc = <STR_LIT> ( OffImm ) ; unsigned SOOpc = <STR_LIT> ( ShOpc , Amt ) ; UpdateMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isSub ? <STR_LIT> : <STR_LIT> ) , WBReg ) . addReg ( BaseReg ) . addReg ( OffReg ) . addReg ( <NUM_LIT> ) . addImm ( SOOpc ) . addImm ( Pred ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } else UpdateMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isSub ? <STR_LIT> : <STR_LIT> ) , WBReg ) . addReg ( BaseReg ) . addReg ( OffReg ) . addImm ( Pred ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; break ; } case <STR_LIT> : { bool isSub = <STR_LIT> ( OffImm ) == <STR_LIT> ; unsigned Amt = <STR_LIT> ( OffImm ) ; if ( OffReg == <NUM_LIT> ) UpdateMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isSub ? <STR_LIT> : <STR_LIT> ) , WBReg ) . addReg ( BaseReg ) . addImm ( Amt ) . addImm ( Pred )


<s> unsigned PCLabelId = AFI -> createConstPoolEntryUId ( ) ; <ISA_LIT>ConstantPoolValue * NewCPV = <NUM_LIT> ; if ( ACPV -> isGlobalValue ( ) ) NewCPV = new <ISA_LIT>ConstantPoolValue ( ACPV -> getGV ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isExtSymbol ( ) ) NewCPV = new <ISA_LIT>ConstantPoolValue ( MF . getFunction ( ) -> getContext ( ) , ACPV -> getSymbol ( ) , PCLabelId , <NUM_LIT> ) ; else if ( ACPV -> isBlockAddress ( ) ) NewCPV = new <ISA_LIT>ConstantPoolValue ( ACPV -> getBlockAddress ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isLSDA ( ) ) NewCPV = new <ISA_LIT>ConstantPoolValue ( MF . getFunction ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; CPI = MCP -> getConstantPoolIndex ( NewCPV ,


<s> bool <ISA_LIT>BaseInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumT , MachineBasicBlock & FMBB ,


<s> isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumT , MachineBasicBlock & FMBB , unsigned


<s> MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; AddDefaultPred ( MIB . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <STR_LIT> ( <STR_LIT> ) ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; } break ; case <STR_LIT> : { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <STR_LIT> ( <STR_LIT> ) ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; break ; } default : llvm_unreachable ( <STR_LIT>


<s> if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] .


<s> case <STR_LIT> : AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <STR_LIT> ( <STR_LIT> ) ) . addMemOperand ( MMO ) ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; AddDefaultPred ( MIB . addMemOperand ( MMO ) ) ; } else { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <STR_LIT> ( <STR_LIT> ) ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT>


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , MFI . getObjectSize ( FI ) , Align ) ; if ( RC == <STR_LIT> || RC == <STR_LIT> || RC == <STR_LIT> ) RC = <STR_LIT> ; switch ( RC -> getID ( ) ) { case <STR_LIT> : AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; break ; case <STR_LIT> : AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <STR_LIT> ( <STR_LIT> ) ) . addMemOperand ( MMO ) ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState (


<s> if ( ! MI . isMoveReg ( ) || ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) != MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; Dest = MI . getOperand ( <NUM_LIT> ) ; Src = MI . getOperand


<s> bool <ISA_LIT>BaseInstrInfo :: isCopyInstr ( const MachineInstr & MI , MachineOperand & Src , MachineOperand & Dest ) const { if ( ! MI . isMoveReg ( ) || ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand (

<NUM_LIT> ) . getReg ( ) != MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ;


<s> unsigned Reg = DefMO . getReg ( ) ; const MCInstrDesc * DefMCID = & DefMI -> getDesc ( ) ; const MCInstrDesc * UseMCID = & UseMI -> getDesc ( ) ; unsigned DefAdj = <NUM_LIT> ; if ( DefMI -> isBundle ( ) ) { DefMI = getBundledDefMI ( & getRegisterInfo ( ) , DefMI , Reg , DefIdx , DefAdj ) ; DefMCID = & DefMI -> getDesc ( ) ; } if ( DefMI -> isCopyLike ( ) || DefMI -> isInsertSubreg ( ) || DefMI -> isRegSequence ( ) || DefMI -> isImplicitDef ( ) ) { return <NUM_LIT> ; } unsigned UseAdj = <NUM_LIT> ; if ( UseMI -> isBundle ( ) ) { unsigned NewUseIdx ; const MachineInstr * NewUseMI = getBundledUseMI ( & getRegisterInfo ( ) , UseMI , Reg , NewUseIdx , UseAdj ) ; if ( ! NewUseMI ) return - <NUM_LIT> ; UseMI = NewUseMI ; UseIdx = NewUseIdx ; UseMCID = & UseMI -> getDesc ( ) ; } if ( Reg == <STR_LIT> ) { if ( DefMI -> getOpcode ( ) == <STR_LIT> ) { return Subtarget . isCortexA9 ( ) ? <NUM_LIT> : <NUM_LIT> ; } if ( UseMI -> isBranch ( ) ) return <NUM_LIT> ; unsigned Latency = getInstrLatency ( ItinData , DefMI ) ; if ( Latency > <NUM_LIT> && Subtarget . isThumb2 ( ) ) { const MachineFunction * MF = DefMI -> getParent ( ) -> getParent ( ) ; if ( MF -> getFunction ( ) -> hasFnAttr ( Attribute :: OptimizeForSize ) )


<s> unsigned Reg = DefMI -> getOperand ( DefIdx ) . getReg ( ) ; if ( DepMI -> readsRegister ( Reg , & getRegisterInfo ( ) ) || ! isPredicated ( DepMI ) ) return <NUM_LIT> ; return getInstrLatency ( ItinData ,


<s> if ( DepMI -> readsRegister ( Reg , & getRegisterInfo ( ) ) || ! isPredicated ( DepMI )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SmallVector < std :: pair < MachineOperand * , <STR_LIT> > , <NUM_LIT> > OperandsToUpdate ; bool isSafe = false ; I = CmpInstr ; E = CmpInstr -> getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } <STR_LIT> CC = ( <STR_LIT> ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; if ( Sub ) { <STR_LIT> NewCC = getSwappedCondition ( CC ) ; if ( NewCC == <STR_LIT> ) return false ; if ( SrcReg2 != <NUM_LIT> && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) OperandsToUpdate . push_back ( std :: make_pair ( & ( ( * I ) . getOperand ( IO - <NUM_LIT> ) ) , NewCC ) ) ; } else switch ( CC ) { default : isSafe = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } } } if ( ! isSafe && ! Sub ) return


<s> AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT>


<s> switch ( RC -> getSize ( ) / <NUM_LIT> ) { case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; }


<s> Create ( MF . getFunction ( ) . getContext ( ) , cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) , PCLabelId , <NUM_LIT> , ACPV -> getModifier ( ) ) ; else if ( ACPV -> isBlockAddress ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getBlockAddress ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isLSDA ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( & MF . getFunction ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isMachineBasicBlock ( ) ) NewCPV = <ISA_LIT>ConstantPoolMBB :: Create ( MF . getFunction ( ) . getContext ( ) , cast < <ISA_LIT>ConstantPoolMBB > ( ACPV ) -> getMBB ( ) , PCLabelId , <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; CPI = MCP -> getConstantPoolIndex ( NewCPV , MCPE . getAlignment ( ) ) ; return PCLabelId


<s> bool isThumb = Subtarget . isThumb ( ) ; unsigned FuncOp = isThumb ? <NUM_LIT> : <NUM_LIT> ; unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? <STR_LIT> : <STR_LIT> : isThumb ? Subtarget . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add


<s> unsigned LastInstrOpcode = RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> getOpcode ( ) ; auto SetCandidateCallInfo = [ & RepeatedSequenceLocs ] ( unsigned CallID , unsigned NumBytesForCall ) { for ( outliner :: Candidate & C : RepeatedSequenceLocs ) C . setCallInfo ( CallID , NumBytesForCall ) ; } ; auto Costs = std :: make_unique < OutlinerCosts > ( Subtarget ) ; unsigned FrameID = <NUM_LIT> ; unsigned NumBytesToCreateFrame = <NUM_LIT> ; if ( RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> isTerminator ( ) ) { FrameID = MachineOutlinerTailCall ; NumBytesToCreateFrame = Costs -> FrameTailCall ; SetCandidateCallInfo ( MachineOutlinerTailCall , Costs -> CallTailCall ) ; } else if ( LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> ) { FrameID = MachineOutlinerThunk ; NumBytesToCreateFrame = Costs ->


<s> Opc = isThumb ? Subtarget . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; if ( isThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; It = MBB . insert ( It , MIB ) ; return It ; } Opc = isThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder CallMIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) ; if ( isThumb ) CallMIB . add ( predOps ( <STR_LIT> ) ) ; CallMIB . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; It = MBB . insert ( It , CallMIB ) ; return It


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SmallVector < std :: pair < MachineOperand * , <STR_LIT> > , <NUM_LIT> > OperandsToUpdate ; bool isSafe = false ; I = CmpInstr ; E = CmpInstr -> getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } <STR_LIT> CC = ( <STR_LIT> ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; if ( Sub ) { <STR_LIT> NewCC = getSwappedCondition ( CC ) ; if ( NewCC == <STR_LIT> ) return false ; if ( SrcReg2 != <NUM_LIT> && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) OperandsToUpdate . push_back ( std :: make_pair ( & ( ( * I ) . getOperand ( IO - <NUM_LIT> ) ) , NewCC ) ) ; } else switch ( CC ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } } } if ( ! isSafe ) { MachineBasicBlock * MBB = CmpInstr -> getParent ( ) ; for ( MachineBasicBlock :: succ_iterator SI = MBB -> succ_begin ( ) , SE = MBB -> succ_end ( ) ; SI != SE ; ++ SI ) if ( ( * SI ) -> isLiveIn ( <STR_LIT> ) ) return false ; } MI -> getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDef ( true ) ; CmpInstr -> eraseFromParent ( ) ; for ( unsigned i = <NUM_LIT> , e = OperandsToUpdate . size ( ) ; i < e ; i ++ ) OperandsToUpdate [ i ] . first -> setImm ( OperandsToUpdate [ i ] . second ) ; return


<s> CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II ) const { if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2 ( ) ) return ( ScheduleHazardRecognizer * ) new <ISA_LIT>HazardRecognizer ( II , * this , getRegisterInfo ( ) , Subtarget ) ; return TargetInstrInfoImpl :: CreateTargetPostRAHazardRecognizer ( II


<s> MachineOperand LDWb ( MI -> getOperand ( <NUM_LIT> ) ) ; LDM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ) ) . add ( LDWb ) ; } else { LDM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) ; } if ( isThumb1 || ! MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) { MachineOperand STWb ( MI -> getOperand ( <NUM_LIT> ) ) ; STM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ) ) . add ( STWb ) ; } else { STM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) ; } MachineOperand LDBase ( MI -> getOperand ( <NUM_LIT> ) ) ; LDM . add ( LDBase ) . add ( predOps ( <STR_LIT> ) ) ; MachineOperand STBase ( MI -> getOperand ( <NUM_LIT> ) ) ; STM . add ( STBase ) . add ( predOps ( <STR_LIT> ) ) ; const TargetRegisterInfo & TRI = getRegisterInfo ( ) ; SmallVector < unsigned , <NUM_LIT>


<s> const <ISA_LIT>BaseInstrInfo * TII = Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineBasicBlock * BB = MI -> getParent ( ) ; MachineInstrBuilder LDM , STM ; if ( isThumb1 || ! MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) { MachineOperand LDWb ( MI -> getOperand ( <NUM_LIT> ) ) ; LDM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ) ) . add ( LDWb ) ; } else { LDM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) ; } if ( isThumb1 || ! MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) { MachineOperand STWb ( MI -> getOperand ( <NUM_LIT> ) ) ; STM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ) ) . add ( STWb ) ; } else { STM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) ; } MachineOperand LDBase ( MI -> getOperand ( <NUM_LIT> ) ) ; LDM . add ( LDBase ) . add ( predOps ( <STR_LIT> ) ) ; MachineOperand STBase ( MI -> getOperand ( <NUM_LIT> ) ) ; STM . add ( STBase ) . add ( predOps (


<s> MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; MachineInstrBuilder MIB ; BuildMI ( MBB , MI , DL , get ( LoadImmOpc ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; if ( Subtarget . isGVIndirectSymbol ( GV ) ) { MIB = BuildMI ( MBB , MI , DL , get ( LoadOpc ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill


<s> if ( isPredicated ( MI ) ) return outliner :: InstrType :: Illegal ; if ( MI . getParent ( ) -> succ_empty ( ) ) return outliner :: InstrType :: Legal ; return outliner :: InstrType :: Illegal ; } for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return outliner :: InstrType :: Illegal ; } if ( MI . readsRegister ( <STR_LIT> , TRI ) || MI . readsRegister ( <STR_LIT> , TRI ) ) return outliner :: InstrType :: Illegal ; if ( MI . isCall ( ) ) { const Function * Callee = nullptr ; for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isGlobal ( ) ) { Callee = dyn_cast < Function > ( MOP . getGlobal ( ) ) ; break ; } } if ( Callee && ( Callee -> getName ( ) == <STR_LIT> || Callee -> getName ( ) == <STR_LIT> || Callee -> getName ( ) == <STR_LIT> ) ) return outliner :: InstrType :: Illegal ; auto UnknownCallOutlineType = outliner :: InstrType :: Illegal ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) UnknownCallOutlineType = outliner :: InstrType :: LegalTerminator ; if ( ! Callee


<s> if ( NumBytes % ( IsVFPPushPop ? <NUM_LIT> : <NUM_LIT> ) != <NUM_LIT> ) return false ; int RegListIdx = IsT1PushPop ? <NUM_LIT> : <NUM_LIT> ; unsigned FirstReg = MI -> getOperand ( RegListIdx ) . getReg ( ) ; unsigned RD0Reg , RegsNeeded ; if ( IsVFPPushPop ) { RD0Reg = <STR_LIT> ; RegsNeeded = NumBytes / <NUM_LIT> ; } else { RD0Reg = <STR_LIT> ; RegsNeeded = NumBytes / <NUM_LIT> ; } SmallVector < MachineOperand , <NUM_LIT> > RegList ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx ; -- i ) RegList . push_back ( MI -> getOperand ( i ) ) ; const TargetRegisterInfo * TRI = MF . getRegInfo ( ) . getTargetRegisterInfo ( ) ; const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( unsigned CurReg = FirstReg - <NUM_LIT> ; CurReg >= RD0Reg && RegsNeeded ; -- CurReg ) { if ( ! IsPop ) { RegList . push_back ( MachineOperand :: CreateReg ( CurReg , false , false , false , false , true ) ) ; -- RegsNeeded


<s> assert ( ! FBB && <STR_LIT> ) ; FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; } else if ( I -> isReturn ( ) ) { CantAnalyze = true ; } else if ( I -> getOpcode ( ) == <STR_LIT> && MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . enableMachinePipeliner ( ) ) { if ( ! Cond . empty ( ) ) return true ; FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( I -> getOpcode ( ) ) ) ; Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } else { return true ; } if ( ! isPredicated ( * I ) && ( isUncondBranchOpcode ( I -> getOpcode ( ) ) || isIndirectBranchOpcode ( I -> getOpcode ( ) ) || isJumpTableBranchOpcode ( I -> getOpcode ( ) ) || I -> isReturn ( ) ) ) { Cond . clear ( ) ; FBB = nullptr ; if ( AllowModify


<s> BuildMI ( & MBB , LoopDec -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( LoopDec -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <NUM_LIT> ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; Cond . push_back ( MachineOperand :: CreateImm ( <STR_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( <STR_LIT> ,


<s> if ( ImpDefIdx != - <NUM_LIT> ) MI . removeOperand ( ImpDefIdx ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( DstRegD ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( SrcRegD ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; MIB . addReg ( SrcRegS , RegState :: Implicit ) ; if ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) { MI . getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; MI . addRegisterKilled ( SrcRegS , TRI , true ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; return true


<s> Register SrcRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || ! SrcRegD ) return false ; if ( ! MI . definesRegister ( DstRegD , TRI ) || MI . readsRegister ( DstRegD , TRI ) ) return false ; if ( MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; MachineInstrBuilder MIB ( * MI . getParent ( ) -> getParent ( ) ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : case <STR_LIT> : { unsigned Size = getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MAI ) ; if ( ! MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) )


<s> } if ( SomeMFI . shouldSignReturnAddress ( true ) ) { Costs . CallDefault += <NUM_LIT> ; Costs . SaveRestoreLROnStack += <NUM_LIT> ; } unsigned FrameID = MachineOutlinerDefault ; unsigned NumBytesToCreateFrame = Costs . FrameDefault ; if ( RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> isTerminator ( ) ) { FrameID = MachineOutlinerTailCall ; NumBytesToCreateFrame = Costs . FrameTailCall ; SetCandidateCallInfo ( MachineOutlinerTailCall , Costs . CallTailCall ) ; } else if ( LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> ) { FrameID = MachineOutlinerThunk ; NumBytesToCreateFrame = Costs . FrameThunk ; SetCandidateCallInfo ( MachineOutlinerThunk , Costs . CallThunk ) ; } else { unsigned NumBytesNoStackCalls = <NUM_LIT> ; std :: vector < outliner :: Candidate > CandidatesWithoutStackFixups ; for ( outliner :: Candidate & C : RepeatedSequenceLocs ) { const auto Last = C . getMBB ( ) -> rbegin ( ) ; const bool LRIsAvailable = C . getMBB ( ) -> isReturnBlock ( ) && ! Last -> isCall ( ) ? isLRAvailable ( TRI , Last , ( MachineBasicBlock :: reverse_iterator ) C . front ( ) ) : C . isAvailableAcrossAndOutOfSeq ( <STR_LIT> , TRI ) ; if ( LRIsAvailable ) { FrameID = MachineOutlinerNoLRSave ; NumBytesNoStackCalls += Costs . CallNoLRSave ; C . setCallInfo ( MachineOutlinerNoLRSave , Costs . CallNoLRSave ) ; CandidatesWithoutStackFixups . push_back ( C ) ; } else if ( findRegisterToSaveLRTo ( C ) ) { FrameID = MachineOutlinerRegSave ; NumBytesNoStackCalls += Costs . CallRegSave ; C . setCallInfo ( MachineOutlinerRegSave , Costs . CallRegSave ) ; CandidatesWithoutStackFixups . push_back ( C ) ; } else if ( C . isAvailableInsideSeq ( <STR_LIT> , TRI ) ) { NumBytesNoStackCalls += Costs . CallDefault ; C . setCallInfo ( MachineOutlinerDefault , Costs . CallDefault ) ; CandidatesWithoutStackFixups . push_back ( C ) ; } else NumBytesNoStackCalls += SequenceSize ; } if ( NumBytesNoStackCalls <= RepeatedSequenceLocs . size ( ) * Costs . CallDefault ) { RepeatedSequenceLocs =


<s> assert ( ! BytesAdded && <STR_LIT> ) ; <ISA_LIT>FunctionInfo * AFI = MBB . getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; int BOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : ( AFI -> isThumb2Function ( ) ? <STR_LIT> : <STR_LIT> ) ; int BccOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : ( AFI -> isThumb2Function ( ) ? <STR_LIT> : <STR_LIT> ) ; bool isThumb = AFI -> isThumbFunction ( ) || AFI -> isThumb2Function ( ) ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( ! FBB ) { if ( Cond . empty ( ) ) { if ( isThumb ) BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) . add ( predOps ( <STR_LIT> ) ) ; else BuildMI ( & MBB , DL , get ( BOpc


<s> if ( C . CallConstructionID == MachineOutlinerNoLRSave || C . CallConstructionID == MachineOutlinerThunk ) { It = MBB . insert ( It , CallMIB ) ; return It ; } const <ISA_LIT>FunctionInfo & AFI = * C . getMF ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( C . CallConstructionID == MachineOutlinerRegSave ) { unsigned Reg = findRegisterToSaveLRTo ( C ) ; assert ( Reg != <NUM_LIT> && <STR_LIT> ) ; copyPhysReg ( MBB , It , DebugLoc ( ) , Reg , <STR_LIT> , true ) ; if ( ! AFI . isLRSpilled ( ) ) emitCFIForLRSaveToReg ( MBB , It , Reg ) ; CallPt = MBB . insert ( It , CallMIB ) ; copyPhysReg ( MBB , It , DebugLoc ( ) , <STR_LIT> , Reg , true ) ; if ( ! AFI . isLRSpilled ( ) ) emitCFIForLRRestoreFromReg ( MBB , It ) ; It -- ; return CallPt ; } if ( ! MBB . isLiveIn ( <STR_LIT> ) ) MBB . addLiveIn ( <STR_LIT> ) ; bool Auth = ! AFI . isLRSpilled ( ) && AFI . shouldSignReturnAddress ( true ) ; saveLROnStack ( MBB , It , ! AFI . isLRSpilled ( ) , Auth ) ; CallPt = MBB . insert ( It , CallMIB ) ; restoreLRFromStack ( MBB , It , ! AFI . isLRSpilled ( ) , Auth ) ; It -- ; return


<s> assert ( ! BytesRemoved && <STR_LIT> ) ; MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return <NUM_LIT> ; if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) && I -> getOpcode ( ) != <STR_LIT> ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! isCondBranchOpcode ( I -> getOpcode ( ) ) && I -> getOpcode ( ) != <STR_LIT> ) return <NUM_LIT> ; I -> eraseFromParent (


<s> bool <ISA_LIT>BaseInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { if ( Cond . size ( ) == <NUM_LIT> ) { <STR_LIT> CC = ( <STR_LIT> ) ( int ) Cond [ <NUM_LIT> ] . getImm ( ) ; Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ( CC ) ) ; return false ; } return true


<s> bool <ISA_LIT>BaseInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { if ( Cond . size ( ) == <NUM_LIT> ) { <STR_LIT> CC = ( <STR_LIT> ) ( int ) Cond [ <NUM_LIT> ] . getImm ( ) ; Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ( CC ) ) ; return false


<s> bool shouldIgnoreForPipelining ( const MachineInstr * MI ) const override { return MI == EndLoop || MI


<s> return false ; } } if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { for ( const MachineOperand & MO : llvm :: drop_begin ( MI . operands ( ) , <NUM_LIT> ) ) { if ( MO . isImplicit ( ) || ! MO . isReg ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( Reg < <STR_LIT> || Reg > <STR_LIT> ) { if ( ! ( MI . getOpcode ( ) == <STR_LIT> && Reg == <STR_LIT> ) && ! ( MI . getOpcode ( ) == <STR_LIT> && Reg == <STR_LIT> ) ) { ErrInfo = <STR_LIT> ; return false ; } } } } if ( MI . getOpcode ( ) == <STR_LIT> ) { assert ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) ; if ( ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) || MI . getOperand ( <NUM_LIT> ) . getImm ( ) != MI . getOperand ( <NUM_LIT> ) . getImm ( ) + <NUM_LIT> ) { ErrInfo = <STR_LIT> ; return false ; } } <STR_LIT> AddrMode = ( <STR_LIT> ) ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) ; switch ( AddrMode ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { uint32_t Imm = <NUM_LIT> ; for ( auto Op : MI . operands ( ) ) { if ( Op . isImm ( ) ) { Imm = Op . getImm (


<s> if ( ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) || ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == <STR_LIT> ) ) { const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( MCID . TSFlags & <STR_LIT> && MO . isDead


<s> } if ( HasStmts && CanReorder ) { MI = MI -> removeFromParent ( ) ; E = CmpInstr ; CmpInstr . getParent ( ) -> insert ( E , MI ) ; } I = CmpInstr ; E = MI ; } const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; do { const MachineInstr & Instr = * -- I ; if ( isRedundantFlagInstr ( & CmpInstr , SrcReg , SrcReg2 , CmpValue , & Instr ) ) { SubAdd = & * I ; break ; } if ( I == E ) break ; if ( Instr . modifiesRegister ( <STR_LIT> , TRI ) || Instr . readsRegister ( <STR_LIT> , TRI ) ) return false ; } while ( I != B ) ; if ( ! MI && ! SubAdd ) return false ; if ( SubAdd ) { MI = SubAdd ; IsThumb1 = false ; } if ( isPredicated ( * MI ) ) return false ; SmallVector < std :: pair < MachineOperand * , <STR_LIT> > , <NUM_LIT> > OperandsToUpdate ; bool isSafe = false ; I = CmpInstr ; E = CmpInstr . getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } <STR_LIT> CC ; bool IsInstrVSel = true ; switch ( Instr . getOpcode ( ) ) { default : IsInstrVSel = false ; CC = ( <STR_LIT> ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; } if ( SubAdd ) { unsigned Opc = SubAdd -> getOpcode ( ) ; bool IsSub = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( ! IsSub || ( SrcReg2 != <NUM_LIT> && SubAdd -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && SubAdd -> getOperand ( <NUM_LIT> ) . getReg ( )


<s> return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc

== <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> static inline bool isVPTOpcode ( int Opc ) { return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc

== <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> else if ( Opcode != <STR_LIT> ) return None ; if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return None ; Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) * Sign ; return RegImmPair { MI . getOperand ( <NUM_LIT> ) . getReg


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> ) { Pred . push_back ( MO ) ; Found = true ; } } return Found


<s> if ( I -> getOpcode ( ) != <STR_LIT> ) Latency += getInstrLatency ( ItinData , I , PredCost ) ; } return Latency ; } const MCInstrDesc & MCID = MI -> getDesc ( ) ; unsigned Class = MCID . getSchedClass ( ) ; unsigned UOps = ItinData -> Itineraries [ Class ] . NumMicroOps ; if ( PredCost && MCID . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) * PredCost = <NUM_LIT> ; if ( UOps ) return ItinData


<s> } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned ShAmt = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( ShAmt == <NUM_LIT> || ShAmt == <NUM_LIT> ) -- Latency ; break ; } } } if ( DefAlign < <NUM_LIT> && Subtarget . isCortexA9 ( ) ) switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> bool <ISA_LIT>BaseInstrInfo :: isSchedulingBoundary ( const MachineInstr * MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI -> isDebugValue ( ) ) return false ; if ( MI -> isTerminator ( ) || MI -> isLabel ( ) ) return true ; MachineBasicBlock :: const_iterator I = MI ; while ( ++ I != MBB -> end ( ) && I ->


<s> AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB . addReg ( DestReg , RegState :: Define | RegState :: Implicit ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState ::


<s> MachineInstr * PotentialAND = & * UI ; if ( ! isSuitableForMask ( PotentialAND , SrcReg , CmpMask , true ) ) continue ; MI = PotentialAND ; break ; } if ( ! MI ) return false ; } } if ( MI -> getParent ( ) != CmpInstr -> getParent ( ) ) return false ; MachineBasicBlock :: iterator I = CmpInstr , E = MI , B = MI -> getParent ( ) -> begin ( ) ; if ( I == B ) return false ; -- I ; for ( ; I != E ; -- I ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( ! MO . isReg ( ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) return false ; } if ( I == B ) return false ; } switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool isSafe = false ; I = CmpInstr ; E = MI -> getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } <STR_LIT> CC = ( <STR_LIT> ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; switch ( CC ) { default : isSafe = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg ,


<s> MachineBasicBlock * Pred = * MBB . pred_begin ( ) ; if ( ! Pred -> empty ( ) ) { MachineInstr * LastMI = & * Pred -> rbegin ( ) ; if ( LastMI -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator CmpMI = LastMI ; if ( CmpMI != Pred -> begin ( ) ) { -- CmpMI ; if ( CmpMI -> getOpcode ( ) == <STR_LIT> || CmpMI -> getOpcode ( ) == <STR_LIT> ) { unsigned Reg = CmpMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> P = getInstrPredicate ( CmpMI , PredReg ) ; if ( P == <STR_LIT> && CmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && is<ISA_LIT>LowRegister ( Reg ) ) return false ; } } } } } unsigned UnpredCost = Probability . getNumerator ( ) * NumCycles ; UnpredCost /= Probability .


<s> unsigned Scale = <NUM_LIT> ; switch ( AddrMode ) { case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : return false ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } Offset += InstrOffs


<s> if ( I == MBB . begin ( ) ) return false ; -- I ; while ( isPredicated ( * I ) || I -> isTerminator ( ) || I -> isDebugValue ( ) ) { bool CantAnalyze = false ; while ( I -> isDebugValue ( ) || ! I -> isTerminator ( ) ) { if ( I == MBB . begin ( ) ) return false ; -- I ; } if ( isIndirectBranchOpcode ( I -> getOpcode ( ) ) || isJumpTableBranchOpcode ( I -> getOpcode ( ) ) ) { CantAnalyze = true ; } else if ( isUncondBranchOpcode ( I -> getOpcode ( ) ) ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB


<s> assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( ! FBB ) { if ( Cond . empty ( ) ) { if ( isThumb ) BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else BuildMI ( & MBB , DL , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addOperand ( Cond [ <NUM_LIT> ] ) ; return <NUM_LIT> ; } BuildMI ( & MBB , DL , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addOperand ( Cond [ <NUM_LIT> ] ) ; if ( isThumb ) BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( FBB ) . addImm (


<s> MachineInstrBuilder MIB ; BuildMI ( MBB , MI , DL , get ( LoadImmOpc ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; if ( Subtarget . isGVIndirectSymbol ( GV ) ) { MIB = BuildMI ( MBB , MI , DL , get ( LoadOpc ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( * MBB . getParent ( ) ) , Flags , <NUM_LIT> , <NUM_LIT> ) ; MIB . addMemOperand ( MMO )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SmallVector < std :: pair < MachineOperand * , <STR_LIT> > , <NUM_LIT> > OperandsToUpdate ; bool isSafe = false ; I = CmpInstr ; E = CmpInstr . getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } <STR_LIT> CC ; bool IsInstrVSel = true ; switch ( Instr . getOpcode ( ) ) { default : IsInstrVSel = false ; CC = ( <STR_LIT> ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; } if ( Sub ) { <STR_LIT> NewCC = getSwappedCondition ( CC ) ; if ( NewCC == <STR_LIT> ) return false ; if ( SrcReg2 != <NUM_LIT> && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) { if ( IsInstrVSel ) return false ; OperandsToUpdate . push_back ( std :: make_pair ( & ( ( * I ) . getOperand ( IO - <NUM_LIT> ) ) , NewCC ) ) ; } } else { switch ( CC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> unsigned RegsNeeded ; const TargetRegisterClass * RegClass ; if ( IsVFPPushPop ) { RegsNeeded = NumBytes / <NUM_LIT> ; RegClass = & <STR_LIT> ; } else { RegsNeeded = NumBytes / <NUM_LIT> ; RegClass = & <STR_LIT> ; } SmallVector < MachineOperand , <NUM_LIT> > RegList ; unsigned FirstRegEnc = - <NUM_LIT> ; const TargetRegisterInfo * TRI = MF . getRegInfo ( ) . getTargetRegisterInfo ( ) ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx ; -- i ) { MachineOperand & MO = MI -> getOperand ( i ) ; RegList . push_back ( MO ) ; if ( MO . isReg ( ) && TRI -> getEncodingValue ( MO . getReg ( ) ) < FirstRegEnc ) FirstRegEnc = TRI -> getEncodingValue ( MO . getReg ( ) ) ; } const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( int CurRegEnc = FirstRegEnc - <NUM_LIT> ; CurRegEnc >= <NUM_LIT> && RegsNeeded ; -- CurRegEnc ) { unsigned CurReg = RegClass -> getRegister ( CurRegEnc ) ; if ( ! IsPop ) { RegList . push_back ( MachineOperand :: CreateReg ( CurReg , false , false , false , false , true ) ) ; --


<s> Create ( MF . getFunction ( ) -> getContext ( ) , cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) , PCLabelId , <NUM_LIT> ) ; else if ( ACPV -> isBlockAddress ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getBlockAddress ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isLSDA ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isMachineBasicBlock ( ) ) NewCPV = <ISA_LIT>ConstantPoolMBB :: Create ( MF . getFunction ( ) -> getContext ( ) , cast < <ISA_LIT>ConstantPoolMBB > ( ACPV

) -> getMBB ( ) , PCLabelId , <NUM_LIT> ) ;


<s> for ( MCSubRegIterator Subreg ( Reg , TRI , true ) ; Subreg . isValid ( ) ; ++ Subreg ) if ( MI -> getParent ( ) -> computeRegisterLiveness ( TRI , * Subreg , MI ) !=

MachineBasicBlock :: LQR_Dead ) return true ;


<s> if ( ! IsPush && ! IsPop ) return false ; bool IsVFPPushPop = MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ; bool IsT1PushPop = MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ; assert ( ( IsT1PushPop || ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; if ( NumBytes % ( IsVFPPushPop ? <NUM_LIT> : <NUM_LIT> ) != <NUM_LIT> ) return false ; int RegListIdx = IsT1PushPop ? <NUM_LIT> : <NUM_LIT> ; unsigned FirstReg = MI -> getOperand ( RegListIdx ) . getReg ( ) ; unsigned RD0Reg , RegsNeeded ; if ( IsVFPPushPop ) { RD0Reg = <STR_LIT> ; RegsNeeded = NumBytes / <NUM_LIT> ; } else { RD0Reg = <STR_LIT> ; RegsNeeded = NumBytes / <NUM_LIT> ; } SmallVector < MachineOperand , <NUM_LIT> > RegList ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx ; -- i ) RegList . push_back ( MI -> getOperand ( i ) ) ; const TargetRegisterInfo * TRI = MF . getRegInfo ( ) . getTargetRegisterInfo ( ) ; const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( unsigned CurReg = FirstReg - <NUM_LIT> ; CurReg >= RD0Reg && RegsNeeded ; -- CurReg ) { if ( ! IsPop ) { RegList . push_back ( MachineOperand :: CreateReg ( CurReg , false , false , false , false , true ) ) ; -- RegsNeeded ; continue ; } if ( isCalleeSavedRegister ( CurReg , CSRegs ) || isAnySubRegLive ( CurReg , TRI , MI ) ) { if ( IsVFPPushPop ) return false ; else continue ; } RegList . push_back ( MachineOperand :: CreateReg ( CurReg , true , false , false , true ) ) ; -- RegsNeeded ; } if ( RegsNeeded > <NUM_LIT> ) return false ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx ; -- i ) MI -> RemoveOperand ( i ) ; MachineInstrBuilder MIB ( MF , &


<s> bool <ISA_LIT>BaseRegisterInfo :: cannotEliminateFrame ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI


<s> if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI


<s> const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; if ( ! TargetRegisterInfo :: canRealignStack (


<s> MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) . add ( predOps ( Pred

, PredReg ) ) . setMIFlags ( MIFlags ) ;


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx

) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) . add ( predOps ( Pred , PredReg ) ) . setMIFlags ( MIFlags ) ;


<s> bool UseSplitPush = STI . splitFramePushPop ( * MF ) ; const MCPhysReg * RegList = STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : ( UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList ) ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( <STR_LIT> ) ) { if ( STI . isMClass ( ) ) { return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ) { return


<s> } } if ( STI . isTargetDarwin ( ) && STI . getTargetLowering ( ) -> supportSwiftError ( ) && F -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_iOS_SwiftError_SaveList ; if ( STI . isTargetDarwin ( ) && F -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS ) return MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> isSplitCSR (


<s> assert ( MF && <STR_LIT> ) ; if ( MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getInfo < <ISA_LIT>FunctionInfo >

( ) -> isSplitCSR ( ) ) return CSR_iOS_CXX_TLS_ViaCopy_SaveList ;


<s> const uint32_t * <ISA_LIT>BaseRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( CC == CallingConv :: GHC ) return


<s> if ( STI . isTargetDarwin ( ) && STI . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_iOS_SwiftError_RegMask ; if ( STI . isTargetDarwin ( ) && CC == CallingConv :: CXX_FAST_TLS ) return


<s> static unsigned getFramePointerReg ( const


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; if ( TFI -> hasFP ( MF )


<s> for ( MCSuperRegIterator Supers ( Reg , RI ) ; Supers . isValid ( ) ; ++ Supers ) if ( <STR_LIT> .

contains ( * Supers ) ) return RI -> getSubReg ( * Supers , Odd ? <STR_LIT> : <STR_LIT> ) ;


<s> if ( TargetRegisterInfo :: isPhysicalRegister ( Paired ) ) { PairedPhys = Paired ; } else if ( VRM && VRM -> hasPhys ( Paired ) ) { PairedPhys = getPairedGPR ( VRM -> getPhys ( Paired ) , Odd , this ) ; } if ( PairedPhys && is_contained ( Order , PairedPhys ) ) Hints . push_back ( PairedPhys ) ; for ( unsigned I = <NUM_LIT> , E = Order . size ( ) ; I != E ; ++ I ) { unsigned Reg = Order [ I ] ; if ( Reg == PairedPhys || ( getEncodingValue ( Reg ) & <NUM_LIT> ) != Odd ) continue ; unsigned Paired = getPairedGPR ( Reg , ! Odd , this


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! STI . useSoftFloat ( ) && STI . hasVFP2 ( ) && ! STI . isThumb1Only ( ) ) return CSR_NoRegs_RegMask ; else return


<s> const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; if ( needsStackRealignment ( MF ) && ! TFI -> hasReservedCallFrame ( MF ) ) return true ; if ( AFI -> isThumbFunction ( ) && MFI . hasVarSizedObjects ( ) ) { if ( AFI -> isThumb2Function ( ) && MFI . getLocalFrameSize ( ) < <NUM_LIT> ) return


<s> static inline bool is<ISA_LIT>Area2Register ( unsigned Reg , bool isIOS ) { using namespace


<s> bool <ISA_LIT>BaseRegisterInfo :: isFrameOffsetLegal ( const MachineInstr * MI , unsigned BaseReg , int64_t Offset ) const { const MCInstrDesc & Desc = MI -> getDesc ( ) ; unsigned AddrMode = ( Desc . TSFlags & <STR_LIT> ) ; unsigned i = <NUM_LIT> ; while ( ! MI -> getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI -> getNumOperands ( ) && <STR_LIT> ) ; } if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) return Offset == <NUM_LIT> ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool isSigned = true ; switch ( AddrMode ) { case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; if ( Offset < <NUM_LIT> ) { NumBits = <NUM_LIT> ; Offset = - Offset ; } else { NumBits = <NUM_LIT> ; } break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT>


<s> ( AFI -> isThumb1OnlyFunction ( ) ? <STR_LIT> : <STR_LIT> ) ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo (


<s> break ; default : return false ; } MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int64_t FPOffset = Offset - <NUM_LIT> ; if ( ! AFI -> isThumbFunction ( ) || ! AFI -> isThumb1OnlyFunction ( ) ) FPOffset -= <NUM_LIT> ; Offset += MFI . getLocalFrameSize ( ) ; Offset += <NUM_LIT> ; unsigned StackAlign = TFI -> getStackAlignment ( ) ; if ( TFI -> hasFP ( MF ) && ! ( ( MFI . getLocalFrameMaxAlign

( ) > StackAlign ) && canRealignStack ( MF ) ) ) {


<s> const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; if ( ! DstSubReg ) return true ; if ( getRegSizeInBits ( * NewRC ) < <NUM_LIT> && getRegSizeInBits ( * DstRC ) < <NUM_LIT> && getRegSizeInBits ( * SrcRC ) < <NUM_LIT> ) return true ; auto NewRCWeight = MRI . getTargetRegisterInfo ( ) -> getRegClassWeight ( NewRC ) ; auto SrcRCWeight = MRI . getTargetRegisterInfo ( ) -> getRegClassWeight ( SrcRC ) ; auto DstRCWeight = MRI . getTargetRegisterInfo ( ) -> getRegClassWeight ( DstRC ) ; if ( SrcRCWeight . RegWeight > NewRCWeight . RegWeight ) return true ; if ( DstRCWeight . RegWeight > NewRCWeight . RegWeight ) return true ; auto AFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; auto It = AFI -> getCoalescedWeight ( MBB ) ; DEBUG ( dbgs ( ) << <STR_LIT> << It -> second << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NewRCWeight . RegWeight << <STR_LIT> ) ; unsigned SizeMultiplier = MBB -> size ( )


<s> trackLivenessAfterRegAlloc ( const MachineFunction & MF


<s> MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; std :: pair < unsigned , unsigned > Hint = MRI -> getRegAllocationHint ( Reg ) ; if ( ( Hint . first == ( unsigned ) <STR_LIT> || Hint . first == ( unsigned ) <STR_LIT>

) && TargetRegisterInfo :: isVirtualRegister ( Hint . second ) ) {


<s> if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; if ( ! MRI -> canReserveReg ( getFramePointerReg ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ) ) ) return false ; if ( TFI -> hasReservedCallFrame ( MF


<s> Register <ISA_LIT>BaseRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; if ( TFI -> hasFP ( MF


<s> const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; if ( TFI -> hasFP ( MF )


<s> const TargetRegisterClass * <ISA_LIT>BaseRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Super ; case <STR_LIT> : case <STR_LIT> : case


<s> do { switch ( Super -> getID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Super ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasNEON ( )


<s> markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , getFramePointerReg ( STI ) ) ; if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , BasePtr ) ; if ( STI . isR9Reserved ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( ! STI . hasD32 ( ) ) { static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ; for ( unsigned R = <NUM_LIT> ; R < <NUM_LIT> ; ++ R ) markSuperRegs ( Reserved , <STR_LIT> + R ) ; } const TargetRegisterClass & RC


<s> if ( AFI -> isThumb2Function ( ) && MFI . hasVarSizedObjects ( ) && MFI . getLocalFrameSize ( ) >= <NUM_LIT> ) return true ; if ( AFI -> isThumb1OnlyFunction ( ) && ! TFI -> hasReservedCallFrame ( MF ) ) return true ; return


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( )


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , <STR_LIT>


<s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , <NUM_LIT> , this , MF ) ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ; if ( ! AFI -> isThumb1OnlyFunction ( ) ) MIB . add ( predOps ( <STR_LIT>


<s> return MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || needsStackRealignment (


<s> return ( RealignStack && ! AFI -> isThumb1OnlyFunction ( ) && ! MFI -> hasVarSizedObjects


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; return ( RealignStack && ! AFI -> isThumb1OnlyFunction ( ) && !


<s> bool <ISA_LIT>BaseRegisterInfo :: canSimplifyCallFramePseudos ( MachineFunction & MF ) const { return hasReservedCallFrame ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects (


<s> canSimplifyCallFramePseudos ( MachineFunction & MF ) const { return hasReservedCallFrame ( MF ) || MF . getFrameInfo ( )


<s> int PIdx = Old -> findFirstPredOperandIdx ( ) ; <STR_LIT> Pred = ( PIdx == - <NUM_LIT> ) ? <STR_LIT> : ( <STR_LIT> ) Old -> getOperand ( PIdx ) . getImm ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { unsigned PredReg = Old -> getOperand ( <NUM_LIT> ) . getReg ( ) ; emitSPUpdate ( is<ISA_LIT> , MBB , I , dl , TII , - Amount , Pred , PredReg ) ; } else { unsigned PredReg = Old -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; emitSPUpdate ( is<ISA_LIT> , MBB , I , dl ,


<s> unsigned PredReg = ( PIdx == - <NUM_LIT> ) ? <NUM_LIT> : MI . getOperand ( PIdx + <NUM_LIT> ) . getReg ( ) ; if ( Offset == <NUM_LIT> ) MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false , false , false ) ; else { ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; if ( Value ) { Value -> first = FrameReg ; Value -> second = Offset ; } if ( ! AFI -> isThumbFunction ( ) ) emit<ISA_LIT>RegPlusImmediate ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , Pred , PredReg , TII ) ; else { assert ( AFI -> isThumb2Function ( ) ) ; emitT2RegPlusImmediate ( MBB , II , MI . getDebugLoc ( ) , ScratchReg ,


<s> unsigned <ISA_LIT>BaseRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , FrameIndexValue * Value , RegScavenger * RS ) const { unsigned i = <NUM_LIT> ; MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; unsigned FrameReg ; int Offset = getFrameIndexReference ( MF , FrameIndex , FrameReg ) ; if ( FrameReg != <STR_LIT> ) SPAdj = <NUM_LIT> ; Offset += SPAdj ; bool Done = false ; if ( ! AFI -> isThumbFunction ( ) ) Done = rewrite<ISA_LIT>FrameIndex ( MI , i , FrameReg , Offset , TII ) ; else { assert ( AFI -> isThumb2Function ( ) ) ; Done = rewriteT2FrameIndex ( MI , i , FrameReg , Offset , TII ) ; } if ( Done ) return <NUM_LIT> ; assert ( ( Offset || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned ScratchReg = <NUM_LIT> ; int PIdx = MI . findFirstPredOperandIdx ( ) ; <STR_LIT> Pred = ( PIdx == - <NUM_LIT> ) ? <STR_LIT> : ( <STR_LIT> ) MI . getOperand ( PIdx ) . getImm ( ) ; unsigned PredReg = ( PIdx == - <NUM_LIT> ) ? <NUM_LIT> : MI . getOperand ( PIdx + <NUM_LIT> ) . getReg ( ) ; if ( Offset == <NUM_LIT> ) MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false , false , false ) ; else { ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; if ( Value ) { Value -> first = FrameReg ; Value -> second = Offset ; } if ( ! AFI -> isThumbFunction ( ) ) emit<ISA_LIT>RegPlusImmediate ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , Pred , PredReg , TII ) ; else { assert ( AFI -> isThumb2Function (


<s> bool HasFP = hasFP ( MF ) ; if ( ( STI . isTargetDarwin ( ) && NumBytes ) || HasFP ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( HasFP || AFI -> getGPRCalleeSavedArea2Size ( ) || AFI -> getDPRCalleeSavedAreaSize ( ) || AFI -> getDPRCalleeSavedAreaOffset ( ) ) { if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ; } } } else if ( NumBytes ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , STI ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , AFI -> getDPRCalleeSavedAreaSize ( ) ) ; movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <STR_LIT> , <NUM_LIT> , STI ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl ,

TII , AFI -> getGPRCalleeSavedArea2Size ( ) ) ;