<s> static void checkNumAlignedDPRCS2Regs ( MachineFunction & MF ) { MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> setNumAlignedDPRCS2Regs ( <NUM_LIT> ) ; if ( ! SpillAlignedNEONRegs ) return ; if ( MF . getFunction ( ) -> getFnAttributes ( ) . hasNakedAttr ( ) ) return ; if ( ! MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasNEON ( ) ) return ; if ( MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) >= <NUM_LIT> ) return ; const <ISA_LIT>BaseRegisterInfo * RegInfo = static_cast < const <ISA_LIT>BaseRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; if ( ! RegInfo -> canRealignStack ( MF ) ) return ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned NumSpills


<s> if ( MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: Naked ) ) return ; if ( ! static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) . hasNEON ( ) ) return ; if ( MF . getSubtarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) >= <NUM_LIT> ) return ; if ( ! static_cast < const <ISA_LIT>BaseRegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) -> canRealignStack ( MF ) ) return ; MachineRegisterInfo & MRI = MF . getRegInfo


<s> AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } } else if ( NumBytes && ! tryFoldSPUpdateIntoPushPop ( STI , MF , MBBI , NumBytes ) ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; if ( AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getDPRCalleeSavedGapSize ( ) ) { assert ( AFI -> getDPRCalleeSavedGapSize ( ) == <NUM_LIT> && <STR_LIT> ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , AFI -> getDPRCalleeSavedGapSize ( ) ) ; } if ( AFI -> getGPRCalleeSavedArea2Size ( ) ) MBBI


<s> -- MBBI ; } while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , TII , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( ArgRegsSaveSize + AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedGapSize ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } } else if ( NumBytes && ! tryFoldSPUpdateIntoPushPop ( STI , MF , MBBI , NumBytes ) ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; if ( AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getDPRCalleeSavedGapSize ( ) ) { assert ( AFI -> getDPRCalleeSavedGapSize ( ) == <NUM_LIT> && <STR_LIT> ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , AFI -> getDPRCalleeSavedGapSize ( ) ) ; } if ( AFI -> getGPRCalleeSavedArea2Size ( ) ) MBBI ++ ; if ( AFI -> getGPRCalleeSavedArea1Size (


<s> LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; DeleteRet = true ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) { MIB . copyImplicitOps ( & * MI ) ; MI -> eraseFromParent ( ) ; } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT> ] = <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) , Regs [ <NUM_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; if ( LdrOpc == <STR_LIT> || LdrOpc == <STR_LIT> ) { MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ) ; } else MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB )


<s> SmallSet < MachineBasicBlock * , <NUM_LIT> > RestoreBlocks ; if ( MFI . getSavePoint ( ) ) { SaveBlocks . insert ( MFI . getSavePoint ( ) ) ; RestoreBlocks . insert ( MFI . getRestorePoint ( ) ) ; } else { SaveBlocks . insert ( & MF . front ( ) ) ; for ( MachineBasicBlock & MBB : MF ) if ( MBB . isReturnBlock ( ) ) RestoreBlocks . insert ( & MBB ) ; } SmallVector < MachineBasicBlock * , <NUM_LIT> > WorkList ; SmallSet < MachineBasicBlock * , <NUM_LIT> > VisitedBlocks ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MF . front ( ) . getName ( ) << <STR_LIT> ) ; WorkList . push_back ( & MF . front ( ) ) ; for ( MachineBasicBlock & MBB : MF ) { if ( MBB . isReturnBlock ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getName ( ) << <STR_LIT> ) ; WorkList . push_back ( & MBB ) ; } } auto CheckOutsideInst = [ & UnsaveableRegs , TRI ] ( MachineInstr & MI ) { for ( Register Reg : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) { if ( MI . modifiesRegister ( Reg , TRI ) ) { UnsaveableRegs . set ( Reg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TRI -> getName ( Reg ) << <STR_LIT> << MI << <STR_LIT> ) ; } } } ; while ( ! WorkList . empty ( ) ) { MachineBasicBlock * MBB = WorkList . pop_back_val ( ) ; if ( VisitedBlocks . count ( MBB ) ) continue ; VisitedBlocks . insert ( MBB ) ; bool IsSave = SaveBlocks . count ( MBB ) ; bool IsRestore = RestoreBlocks . count ( MBB ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getName ( ) << <STR_LIT> << IsSave << <STR_LIT> << IsRestore << <STR_LIT> ) ; if ( IsRestore ) { LivePhysRegs LPR ( * TRI ) ; LPR . addLiveOuts ( * MBB ) ; for ( auto & Term : reverse ( MBB -> terminators ( ) ) ) { LPR . stepBackward ( Term ) ; CheckOutsideInst ( Term


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; int D8SpillFI = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) if ( CSI [ i ] . getReg ( ) == <STR_LIT> ) { D8SpillFI = CSI [ i ] . getFrameIdx ( ) ; break ; } bool isThumb = AFI -> isThumbFunction ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; unsigned Opc = isThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addFrameIndex ( D8SpillFI ) . addImm ( <NUM_LIT> ) ) ) ; unsigned NextReg = <STR_LIT> ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } unsigned R4BaseReg = NextReg ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -=


<s> AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } unsigned R4BaseReg = NextReg ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg += <NUM_LIT>


<s> unsigned Opc = isThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> * NumAlignedDPRCS2Regs ) ) ) ; Opc = isThumb ? <STR_LIT> : <STR_LIT> ; unsigned MaxAlign = MF . getFrameInfo ( ) -> getMaxAlignment ( ) ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( MaxAlign - <NUM_LIT> ) ) ) ; Opc = isThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MIB = AddDefaultPred ( MIB ) ; if ( ! isThumb ) AddDefaultCC ( MIB ) ; unsigned NextReg = <STR_LIT> ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } unsigned R4BaseReg = NextReg ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } if ( NumAlignedDPRCS2Regs ) { MBB . addLiveIn ( NextReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( NextReg ) . addReg ( <STR_LIT> ) . addImm ( ( NextReg - R4BaseReg ) * <NUM_LIT> ) ) ; } llvm :: prior ( MI ) -> addRegisterKilled ( <STR_LIT> ,


<s> unsigned Opc = isThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> * NumAlignedDPRCS2Regs ) ) ) ; Opc = isThumb ? <STR_LIT> : <STR_LIT> ; unsigned MaxAlign = MF . getFrameInfo ( ) -> getMaxAlignment ( ) ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( MaxAlign - <NUM_LIT> ) ) ) ; Opc = isThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MIB = AddDefaultPred ( MIB ) ; if ( ! isThumb ) AddDefaultCC ( MIB ) ; unsigned NextReg = <STR_LIT> ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } unsigned R4BaseReg = NextReg ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) ) ; NextReg +=


<s> if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { for ( int i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( ! isCalleeSavedRegister ( MI -> getOperand ( i ) . getReg ( ) , CSRegs ) ) return false ; return true ; } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && isCalleeSavedRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , CSRegs ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return true ; return false


<s> else if ( AFI -> isDPRCalleeSavedAreaFrame ( FI ) ) return Offset - AFI -> getDPRCalleeSavedAreaOffset ( ) ; if ( RegInfo -> needsStackRealignment ( MF ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; if ( isFixed ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; Offset = FPOffset ; } else if ( MFI -> hasVarSizedObjects ( ) ) { assert ( RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; FrameReg = RegInfo -> getBaseRegister ( ) ; } return Offset ; } if ( hasFP ( MF ) && AFI -> hasStackFrame ( ) ) { if ( isFixed || ( MFI -> hasVarSizedObjects ( ) && ! RegInfo -> hasBasePointer ( MF ) ) ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset


<s> DebugLoc dl = I -> getDebugLoc ( ) ; unsigned Opc = I -> getOpcode ( ) ; bool IsDestroy = Opc == TII . getCallFrameDestroyOpcode ( ) ; unsigned CalleePopAmount = IsDestroy ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; int PIdx = I -> findFirstPredOperandIdx ( ) ; <STR_LIT> Pred = ( PIdx == - <NUM_LIT> ) ? <STR_LIT> : ( <STR_LIT> ) I -> getOperand ( PIdx ) . getImm ( ) ; unsigned PredReg = TII . getFramePred ( * I ) ; if ( ! hasReservedCallFrame ( MF ) ) { if ( IsDestroy && CalleePopAmount != <NUM_LIT> ) return MBB . erase ( I ) ; unsigned Amount = TII . getFrameSize ( * I ) ; if ( Amount != <NUM_LIT> ) { Amount = alignSPAdjust ( Amount ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { emitSPUpdate ( is<ISA_LIT> , MBB , I , dl , TII , - Amount , MachineInstr :: NoFlags , Pred , PredReg ) ; } else { assert ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; emitSPUpdate ( is<ISA_LIT> , MBB , I , dl , TII , Amount , MachineInstr :: NoFlags , Pred , PredReg ) ; } } } else if ( CalleePopAmount != <NUM_LIT> ) { emitSPUpdate ( is<ISA_LIT> , MBB , I , dl , TII , - CalleePopAmount , MachineInstr :: NoFlags ,


<s> if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII , MachineInstr :: FrameDestroy ) ; else { assert ( ! MFI . getPristineRegs ( MF ) . test ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII , MachineInstr :: FrameDestroy ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . add ( predOps ( <STR_LIT> ) ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } } else if ( NumBytes && ! tryFoldSPUpdateIntoPushPop ( STI , MF , & * MBBI , NumBytes ) ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes , MachineInstr :: FrameDestroy ) ; if ( MBBI != MBB . end ( ) && AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getDPRCalleeSavedGapSize ( ) ) { assert ( AFI -> getDPRCalleeSavedGapSize ( ) == <NUM_LIT> && <STR_LIT> ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , AFI -> getDPRCalleeSavedGapSize ( ) , MachineInstr :: FrameDestroy ) ; } if ( AFI -> getGPRCalleeSavedArea2Size ( ) )


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; assert ( MBBI -> isReturn ( ) && <STR_LIT> ) ; unsigned RetOpcode = MBBI -> getOpcode ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; bool is<ISA_LIT> = ! AFI -> isThumbFunction ( ) ; unsigned Align = MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned ArgRegsSaveSize = AFI -> getArgRegsSaveSize ( Align ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( MF . getFunction ( ) -> getCallingConv ( ) == CallingConv :: GHC ) return ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; } else { const uint16_t * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , TII , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned

) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ;


<s> if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) { MIB . copyImplicitOps ( & * MI ) ; MI -> eraseFromParent ( ) ; } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT> ] = <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) , Regs [ <NUM_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; if ( LdrOpc == <STR_LIT> || LdrOpc ==


<s> if ( ArgRegsSaveSize ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - ArgRegsSaveSize , MachineInstr :: FrameSetup ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - NumBytes , MachineInstr :: FrameSetup ) ; return ; } for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; int FI = CSI [ i ] . getFrameIdx ( ) ; switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; GPRCS1Size += <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetIOS ( ) ) GPRCS2Size += <NUM_LIT> ; else GPRCS1Size += <NUM_LIT> ; break ; default : if ( Reg == <STR_LIT> ) D8SpillFI = FI ; if ( Reg < <STR_LIT> || Reg >= <STR_LIT> + AFI -> getNumAlignedDPRCS2Regs ( ) ) DPRCSSize += <NUM_LIT> ; } } if ( GPRCS1Size > <NUM_LIT> ) MBBI ++ ; bool HasFP = hasFP ( MF ) ; unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; if ( HasFP ) AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI ) + NumBytes ) ; AFI -> setGPRCalleeSavedArea1Offset ( GPRCS1Offset ) ; AFI -> setGPRCalleeSavedArea2Offset ( GPRCS2Offset ) ; AFI -> setDPRCalleeSavedAreaOffset ( DPRCSOffset ) ; if ( HasFP ) { int FramePtrOffset = MFI -> getObjectOffset ( FramePtrSpillFI ) + GPRCS1Size ; emitRegPlusImmediate ( ! AFI -> isThumbFunction ( ) , MBB , MBBI , dl , TII , FramePtr , <STR_LIT> , FramePtrOffset , MachineInstr :: FrameSetup ) ; } if ( GPRCS2Size > <NUM_LIT> ) MBBI ++ ; if ( DPRCSSize > <NUM_LIT> ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getNumAlignedDPRCS2Regs ( ) > <NUM_LIT> ) { MBBI = skipAlignedDPRCS2Spills ( MBBI , AFI


<s> unsigned TargetAlign = getStackAlignment ( ) ; if ( TargetAlign == <NUM_LIT> && ( NumGPRSpills & <NUM_LIT> ) ) { if ( CS1Spilled && ! UnspilledCS1GPRs . empty ( ) ) { for ( unsigned i = <NUM_LIT> , e = UnspilledCS1GPRs . size ( ) ; i != e ; ++ i ) { unsigned Reg = UnspilledCS1GPRs [ i ] ; if ( ! AFI -> isThumb1OnlyFunction ( ) || is<ISA_LIT>LowRegister ( Reg ) || Reg == <STR_LIT> ) { MRI . setPhysRegUsed ( Reg ) ; if ( ! MRI . isReserved ( Reg ) ) ExtraCSSpill = true ; break ; } } } else if ( ! UnspilledCS2GPRs . empty ( ) && ! AFI -> isThumb1OnlyFunction ( ) ) { unsigned Reg = UnspilledCS2GPRs . front ( ) ; MRI . setPhysRegUsed ( Reg ) ; if ( ! MRI . isReserved ( Reg ) ) ExtraCSSpill = true ; } } if ( BigStack && ! ExtraCSSpill ) { unsigned NumExtras = TargetAlign / <NUM_LIT> ; SmallVector < unsigned , <NUM_LIT> > Extras ; while ( NumExtras && ! UnspilledCS1GPRs . empty ( ) ) { unsigned Reg = UnspilledCS1GPRs . back ( ) ; UnspilledCS1GPRs . pop_back ( ) ; if ( ! MRI . isReserved ( Reg ) && ( ! AFI -> isThumb1OnlyFunction ( ) || is<ISA_LIT>LowRegister ( Reg ) || Reg == <STR_LIT> ) ) { Extras . push_back ( Reg ) ; NumExtras -- ; } } if ( ! AFI -> isThumb1OnlyFunction ( ) ) { while ( NumExtras && ! UnspilledCS2GPRs . empty ( ) ) { unsigned Reg = UnspilledCS2GPRs . back ( ) ; UnspilledCS2GPRs . pop_back ( ) ; if ( ! MRI . isReserved ( Reg ) ) { Extras . push_back ( Reg ) ; NumExtras -- ; } } } if ( Extras . size ( ) && NumExtras == <NUM_LIT> ) { for ( unsigned i = <NUM_LIT> , e = Extras . size ( ) ; i != e ; ++ i ) { MRI . setPhysRegUsed ( Extras [ i ] ) ; } } else if ( ! AFI -> isThumb1OnlyFunction ( ) ) { const TargetRegisterClass * RC


<s> fixTCReturn ( MF , MBB ) ; return ; } if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes - ArgRegsSaveSize != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes - ArgRegsSaveSize ) ; } else { const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; if ( MBBI != MBB . begin ( ) ) { do { -- MBBI ; } while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , TII , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( ArgRegsSaveSize + AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedGapSize ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } }


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; bool is<ISA_LIT> = ! AFI -> isThumbFunction ( ) ; unsigned ArgRegsSaveSize = AFI -> getArgRegsSaveSize ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( MF . getFunction ( ) -> getCallingConv ( ) == CallingConv :: GHC ) { fixTCReturn ( MF , MBB ) ; return ; } if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes - ArgRegsSaveSize != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes - ArgRegsSaveSize ) ; } else { const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; if ( MBBI != MBB . begin ( ) ) { do { -- MBBI ; } while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , TII , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( ArgRegsSaveSize + AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedGapSize ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else { assert ( ! MFI -> getPristineRegs ( MF ) . test ( <STR_LIT> )


<s> AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> * NumAlignedDPRCS2Regs ) ) ) ; Opc = isThumb ? <STR_LIT> : <STR_LIT> ; unsigned MaxAlign = MF . getFrameInfo ( ) -> getMaxAlignment ( ) ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( MaxAlign - <NUM_LIT> ) ) ) ; Opc = isThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MIB = AddDefaultPred ( MIB ) ; if ( ! isThumb ) AddDefaultCC ( MIB ) ; unsigned NextReg = <STR_LIT> ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } unsigned R4BaseReg = NextReg ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT>


<s> MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getGPRCalleeSavedArea2Size ( ) ) MBBI ++ ; if ( AFI -> getGPRCalleeSavedArea1Size ( ) ) MBBI ++ ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; if ( RetOpcode == <STR_LIT> ) { unsigned TCOpcode = STI . isThumb ( ) ? ( STI . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( TCOpcode ) ) ; if ( JumpTarget . isGlobal ( ) ) MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) , JumpTarget . getTargetFlags ( ) ) ; else { assert ( JumpTarget . isSymbol ( ) ) ; MIB . addExternalSymbol ( JumpTarget . getSymbolName ( ) , JumpTarget . getTargetFlags ( ) ) ; } if ( STI . isThumb ( ) ) MIB . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; } else if ( RetOpcode == <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } MachineInstr * NewMI = std :: prev ( MBBI ) ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) NewMI -> addOperand ( MBBI -> getOperand ( i ) ) ; MBB . erase (


<s> void <ISA_LIT>FrameLowering :: emitPopInst ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , unsigned LdmOpc , unsigned LdrOpc , bool isVarArg , bool NoGap , bool ( * Func ) ( unsigned , bool ) ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned RetOpcode = MI -> getOpcode ( ) ; bool isTailCall = ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) ; SmallVector < unsigned , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; bool DeleteRet = false ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . isTargetDarwin ( ) ) ) continue ; if ( Reg == <STR_LIT> && ! isTailCall && !


<s> unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; unsigned GPRCS1Size = <NUM_LIT> , GPRCS2Size = <NUM_LIT> , DPRCSSize = <NUM_LIT> ; int FramePtrSpillFI = <NUM_LIT> ; if ( MF . getFunction ( ) -> getCallingConv ( ) == CallingConv :: GHC ) return ; if ( VARegSaveSize ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - VARegSaveSize , MachineInstr :: FrameSetup ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - NumBytes , MachineInstr :: FrameSetup ) ; return ; } for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; int FI = CSI [ i ] . getFrameIdx ( ) ; switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetDarwin ( ) ) { AFI -> addGPRCalleeSavedArea2Frame ( FI ) ; GPRCS2Size += <NUM_LIT> ; } else { AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; } break ; default : AFI -> addDPRCalleeSavedAreaFrame ( FI ) ; DPRCSSize += <NUM_LIT> ; } } if ( GPRCS1Size > <NUM_LIT> ) MBBI ++ ; bool HasFP = hasFP ( MF ) ; if ( HasFP ) { unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( ADDriOpc ) , FramePtr ) . addFrameIndex ( FramePtrSpillFI ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; AddDefaultCC ( AddDefaultPred ( MIB ) ) ; } if ( GPRCS2Size > <NUM_LIT> ) MBBI ++ ; unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset =


<s> } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || StrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( StmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . setMIFlags ( MIFlags ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] . first , getKillRegState ( Regs [ i ] . second ) ) ; } else if ( Regs . size ( ) == <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( StrOpc ) , <STR_LIT> ) . addReg ( Regs [ <NUM_LIT> ] . first , getKillRegState ( Regs [ <NUM_LIT> ] . second ) ) . addReg ( <STR_LIT> ) . setMIFlags ( MIFlags ) . addImm ( - <NUM_LIT> ) ; AddDefaultPred ( MIB


<s> unsigned PushOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; unsigned PushOneOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; unsigned FltOpc = <STR_LIT> ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & is<ISA_LIT>Area1Register , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc ,

false , & is<ISA_LIT>Area2Register , MachineInstr :: FrameSetup ) ;


<s> SmallVector < unsigned , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; bool DeleteRet = false ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . isTargetIOS ( ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; if ( Reg == <STR_LIT> && ! isTailCall && ! isVarArg && ! isInterrupt && STI . hasV5TOps ( ) && ! STI . isTargetNaCl ( ) ) { Reg = <STR_LIT> ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; DeleteRet = true ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) { MIB . copyImplicitOps ( &


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned RetOpcode = MI -> getOpcode ( ) ; bool isTailCall = ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) ; bool isInterrupt = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; SmallVector < unsigned , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; bool DeleteRet = false ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . isTargetDarwin ( ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; if ( Reg == <STR_LIT> && ! isTailCall && ! isVarArg && ! isInterrupt && STI . hasV5TOps ( ) && ! STI . isTargetNaCl ( ) ) { Reg = <STR_LIT> ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; DeleteRet = true ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if (


<s> int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; } else { const unsigned * CSRegs = RegInfo -> getCalleeSavedRegs ( ) ; if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , TII , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } } else if ( NumBytes ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; if ( AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getGPRCalleeSavedArea2Size ( ) ) MBBI ++ ; if ( AFI -> getGPRCalleeSavedArea1Size ( )


<s> const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; bool is<ISA_LIT> = ! AFI -> isThumbFunction ( ) ; unsigned VARegSaveSize = AFI -> getVarArgsRegSaveSize ( ) ; unsigned NumBytes = MFI -> getStackSize ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; unsigned GPRCS1Size = <NUM_LIT> , GPRCS2Size = <NUM_LIT> , DPRCSSize = <NUM_LIT> ; int FramePtrSpillFI = <NUM_LIT> ; if ( VARegSaveSize ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - VARegSaveSize , MachineInstr :: FrameSetup ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - NumBytes , MachineInstr :: FrameSetup ) ; return ; } for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; int FI = CSI [ i ] . getFrameIdx ( ) ; switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetDarwin ( ) ) { AFI -> addGPRCalleeSavedArea2Frame ( FI ) ; GPRCS2Size += <NUM_LIT> ; } else { AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; } break ; default : AFI -> addDPRCalleeSavedAreaFrame ( FI ) ; DPRCSSize += <NUM_LIT> ; } } if ( GPRCS1Size > <NUM_LIT> ) MBBI ++ ; bool HasFP = hasFP ( MF ) ; if ( HasFP ) { unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( ADDriOpc ) , FramePtr ) . addFrameIndex ( FramePtrSpillFI ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; AddDefaultCC ( AddDefaultPred ( MIB ) ) ; } if ( GPRCS2Size > <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetDarwin ( ) ) { AFI -> addGPRCalleeSavedArea2Frame ( FI ) ; GPRCS2Size += <NUM_LIT> ; } else { AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; } break ; default : AFI -> addDPRCalleeSavedAreaFrame ( FI ) ; DPRCSSize += <NUM_LIT> ; } } if ( GPRCS1Size > <NUM_LIT> ) MBBI ++ ; bool HasFP = hasFP ( MF ) ; if ( HasFP ) { unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( ADDriOpc ) , FramePtr ) . addFrameIndex ( FramePtrSpillFI ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; AddDefaultCC ( AddDefaultPred ( MIB ) ) ; } if ( GPRCS2Size > <NUM_LIT> ) MBBI ++ ; unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; if ( HasFP ) AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI ) + NumBytes ) ; AFI -> setGPRCalleeSavedArea1Offset ( GPRCS1Offset ) ; AFI -> setGPRCalleeSavedArea2Offset ( GPRCS2Offset ) ; AFI -> setDPRCalleeSavedAreaOffset ( DPRCSOffset ) ; if ( DPRCSSize > <NUM_LIT> ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } NumBytes = DPRCSOffset ; if ( NumBytes ) { emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - NumBytes , MachineInstr :: FrameSetup ) ; if ( HasFP && is<ISA_LIT> ) AFI -> setShouldRestoreSPFromFP ( true ) ; } if ( STI . isTargetELF ( ) && hasFP ( MF ) ) MFI -> setOffsetAdjustment ( MFI -> getOffsetAdjustment ( ) - AFI -> getFramePtrSpillOffset ( ) ) ; AFI -> setGPRCalleeSavedArea1Size ( GPRCS1Size ) ; AFI -> setGPRCalleeSavedArea2Size ( GPRCS2Size ) ; AFI -> setDPRCalleeSavedAreaSize ( DPRCSSize ) ; if ( RegInfo -> needsStackRealignment ( MF ) ) { unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; assert ( ! AFI -> isThumb1OnlyFunction (


<s> } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet && MI != MBB . end ( ) ) { MIB . copyImplicitOps ( * MI ) ; MI -> eraseFromParent ( ) ; } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT> ] = <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) , Regs [ <NUM_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; if ( LdrOpc == <STR_LIT> || LdrOpc == <STR_LIT> ) { MIB . addReg (


<s> LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet && MI != MBB . end ( ) ) { MIB . copyImplicitOps ( * MI ) ; MI -> eraseFromParent ( ) ; } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT> ] = <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) , Regs [ <NUM_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; if ( LdrOpc == <STR_LIT> || LdrOpc ==


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned RetOpcode = MI -> getOpcode ( ) ; bool isTailCall = ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) ; bool isInterrupt = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; SmallVector < unsigned , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; bool DeleteRet = false ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . isTargetDarwin ( ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; if ( Reg == <STR_LIT> && ! isTailCall && ! isVarArg && ! isInterrupt && STI . hasV5TOps ( ) && ! STI . isTargetNaCl ( ) ) { Reg = <STR_LIT> ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; DeleteRet = true ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) { MIB . copyImplicitOps ( & * MI ) ; MI -> eraseFromParent ( ) ; } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> )


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned RetOpcode = MI -> getOpcode ( ) ; bool isTailCall = ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) ; bool isInterrupt = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; SmallVector < unsigned , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; bool DeleteRet = false ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . isTargetDarwin ( ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; if ( Reg == <STR_LIT> && ! isTailCall && ! isVarArg && ! isInterrupt && STI . hasV5TOps ( ) && ! STI . isTargetNaCl ( ) ) { Reg = <STR_LIT> ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; DeleteRet = true ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) { MIB . copyImplicitOps ( & * MI ) ; MI -> eraseFromParent ( ) ; } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT>


<s> else { assert ( ! MFI -> getPristineRegs ( MF ) . test ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } } else if ( NumBytes && ! tryFoldSPUpdateIntoPushPop ( STI , MF , & * MBBI , NumBytes ) ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; if ( AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getDPRCalleeSavedGapSize ( )


<s> unsigned FnSize = <NUM_LIT> ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) FnSize += TII . GetInstSizeInBytes ( MI ) ; } return


<s> AddDefaultPred ( BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg0 ) . addReg ( ScratchReg0 ) . addImm ( <NUM_LIT> * TlsOffset ) ) . addReg ( <NUM_LIT> ) ; AddDefaultPred ( BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg0 ) . addReg ( ScratchReg0 ) . addImm ( <NUM_LIT> ) ) ; AddDefaultPred ( BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( ScratchReg0 ) . addReg ( ScratchReg1 ) ) ; BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( postStackMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; AddDefaultPred ( BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg0 ) . addImm ( AlignedStackSize ) ) . addReg ( <NUM_LIT> ) ; AddDefaultPred ( BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg1 ) . addImm ( AlignTo<ISA_LIT>Constant ( <ISA_LIT>FI -> getArgumentStackSize ( ) ) ) ) . addReg ( <NUM_LIT> ) ; AddDefaultPred ( BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ; BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) ; AddDefaultPred ( BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ; AddDefaultPred ( BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ) . addReg ( ScratchReg0 ) . addReg ( ScratchReg1 ) ; AddDefaultPred ( BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) . addReg ( <NUM_LIT> ) ; AddDefaultPred ( BuildMI ( postStackMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ) . addReg ( ScratchReg0 ) . addReg ( ScratchReg1 ) ; postStackMBB -> addSuccessor ( & prologueMBB ) ; allocMBB -> addSuccessor ( postStackMBB ) ; checkMBB -> addSuccessor ( postStackMBB


<s> MFI . setObjectAlignment ( FI , DNum % <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( DNum == <NUM_LIT> ) MFI . setObjectAlignment ( FI , MFI . getMaxAlignment ( ) ) ; } bool isThumb = AFI -> isThumbFunction ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; AFI -> setShouldRestoreSPFromFP ( true ) ; unsigned Opc = isThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> * NumAlignedDPRCS2Regs ) ) ) ; unsigned MaxAlign = MF . getFrameInfo ( ) -> getMaxAlignment ( ) ; emitAligningInstructions ( MF , AFI , TII , MBB , MI , DL , <STR_LIT> , MaxAlign , true ) ; Opc = isThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MIB = AddDefaultPred ( MIB ) ; if ( ! isThumb ) AddDefaultCC ( MIB ) ; unsigned NextReg = <STR_LIT> ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) ) ; NextReg +=


<s> LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet && MI != MBB . end ( ) ) { MIB . copyImplicitOps ( & * MI ) ; MI -> eraseFromParent ( ) ; } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT> ] = <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) , Regs [ <NUM_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; if ( LdrOpc == <STR_LIT> || LdrOpc == <STR_LIT> ) { MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ) ; } else MIB . addImm


<s> DeleteRet = true ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; } else LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet && MI != MBB . end ( ) ) { MIB . copyImplicitOps ( & * MI ) ; MI -> eraseFromParent ( ) ; } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT>


<s> if ( I -> getName ( ) . startswith ( <STR_LIT> ) || I -> getName ( ) . startswith ( <STR_LIT> ) ) continue ; if ( TD -> getTypeAllocSize ( I -> getType ( ) -> getElementType ( ) ) < MaxOffset ) { const TargetLoweringObjectFile & TLOF = TLI -> getObjFileLowering ( ) ; if ( TLOF . getKindForGlobal ( I , TLI -> getTargetMachine ( ) ) . isBSSLocal ( ) ) BSSGlobals . push_back ( I ) ; else if ( I -> isConstant ( ) ) ConstGlobals . push_back ( I ) ; else Globals . push_back ( I ) ; } } if ( Globals . size ( ) > <NUM_LIT> ) Changed |= doMerge ( Globals , M , false ) ; if ( BSSGlobals . size ( ) > <NUM_LIT> ) Changed |= doMerge ( BSSGlobals , M , false ) ; return


<s> bool <ISA_LIT>GlobalMerge :: runOnFunction ( Function & F


<s> bool <ISA_LIT>GlobalMerge :: runOnFunction ( Function & F ) { return


<s> bool Changed = false ; for ( Module :: global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) { if ( ! I -> hasLocalLinkage ( ) || I -> isThreadLocal ( ) || I -> hasSection ( ) ) continue ; unsigned Alignment = I -> getAlignment ( ) ; Type * Ty = I -> getType ( ) -> getElementType ( ) ; if ( Alignment > TD -> getABITypeAlignment ( Ty ) ) continue ; if ( I -> getName ( ) . startswith ( <STR_LIT> ) || I -> getName ( ) . startswith ( <STR_LIT> ) ) continue ; if ( TD -> getTypeAllocSize ( Ty ) < MaxOffset ) { const TargetLoweringObjectFile & TLOF = TLI -> getObjFileLowering ( ) ; if ( TLOF . getKindForGlobal ( I , TLI -> getTargetMachine ( ) ) . isBSSLocal ( ) ) BSSGlobals . push_back ( I ) ; else if ( I -> isConstant ( ) ) ConstGlobals . push_back ( I ) ; else Globals . push_back ( I ) ; } } if ( Globals . size ( ) > <NUM_LIT> ) Changed |= doMerge ( Globals , M , false ) ; if ( BSSGlobals . size ( ) > <NUM_LIT> ) Changed |= doMerge


<s> size_t j = <NUM_LIT> ; uint64_t MergedSize = <NUM_LIT> ; std :: vector < Type * > Tys ; std :: vector < Constant * > Inits ; for ( j = i ; j != e ; ++ j ) { Type * Ty = Globals [ j ] -> getType ( ) -> getElementType ( ) ; MergedSize += TD -> getTypeAllocSize ( Ty ) ; if ( MergedSize > MaxOffset ) { break ; } Tys . push_back ( Ty ) ; Inits . push_back ( Globals [ j ] -> getInitializer ( ) ) ; } StructType * MergedTy = StructType :: get ( M . getContext ( ) , Tys ) ; Constant * MergedInit = ConstantStruct :: get ( MergedTy , Inits ) ; GlobalVariable * MergedGV = new GlobalVariable ( M , MergedTy , isConst , GlobalValue :: InternalLinkage , MergedInit , <STR_LIT> ) ; for ( size_t k = i ; k < j ; ++ k ) { Constant * Idx [ <NUM_LIT> ] = { ConstantInt :: get ( Int32Ty , <NUM_LIT> ) , ConstantInt :: get ( Int32Ty , k - i ) } ; Constant * GEP = ConstantExpr :: getInBoundsGetElementPtr ( MergedGV , Idx ) ; Globals [ k ] -> replaceAllUsesWith


<s> FunctionPass * llvm :: create<ISA_LIT>GlobalMergePass ( const TargetLowering


<s> FunctionPass * llvm :: create<ISA_LIT>GlobalMergePass ( const TargetLowering *


<s> std :: stable_sort ( Globals . begin ( ) , Globals . end ( ) , GlobalCmp ( TD ) ) ; const Type * Int32Ty = Type :: getInt32Ty ( M . getContext ( ) ) ; for ( size_t i = <NUM_LIT> , e = Globals . size ( ) ; i != e ; ) { size_t j = <NUM_LIT> ; uint64_t MergedSize = <NUM_LIT> ; std :: vector < const Type * > Tys ; std :: vector < Constant * > Inits ; for ( j = i ; MergedSize < MaxOffset && j != e ; ++ j ) { const Type * Ty = Globals [ j ] -> getType ( ) -> getElementType ( ) ; Tys . push_back ( Ty ) ; Inits . push_back ( Globals [ j ] -> getInitializer ( ) ) ; MergedSize += TD -> getTypeAllocSize ( Ty ) ; } StructType * MergedTy = StructType :: get ( M . getContext ( ) , Tys ) ; Constant * MergedInit = ConstantStruct :: get ( MergedTy , Inits ) ; GlobalVariable * MergedGV = new GlobalVariable ( M , MergedTy , isConst , GlobalValue :: InternalLinkage , MergedInit , <STR_LIT> ) ; for ( size_t k = i ; k < j ; ++ k ) { SmallVector < Constant * , <NUM_LIT> > Idx ; Idx . push_back ( ConstantInt :: get ( Int32Ty , <NUM_LIT> ) ) ; Idx . push_back ( ConstantInt :: get ( Int32Ty , k - i ) ) ; Constant * GEP = ConstantExpr :: getInBoundsGetElementPtr ( MergedGV , & Idx [ <NUM_LIT> ] , Idx . size ( ) ) ; Globals [ k ] -> replaceAllUsesWith ( GEP ) ; Globals [ k ] -> eraseFromParent ( ) ; } i = j ; } return true


<s> const Type * Int32Ty = Type :: getInt32Ty ( M . getContext ( ) ) ; for ( size_t i = <NUM_LIT> , e = Globals . size ( ) ; i != e ; ) { size_t j = <NUM_LIT> ; uint64_t MergedSize = <NUM_LIT> ; std :: vector < const Type * > Tys ; std :: vector < Constant * > Inits ; for ( j = i ; MergedSize < MaxOffset && j != e ; ++ j ) { const Type * Ty = Globals [ j ] -> getType ( ) -> getElementType ( ) ; Tys . push_back ( Ty ) ; Inits . push_back ( Globals [ j ] -> getInitializer ( ) ) ; MergedSize += TD -> getTypeAllocSize ( Ty ) ; } StructType * MergedTy = StructType :: get ( M . getContext ( ) , Tys ) ; Constant * MergedInit = ConstantStruct :: get ( MergedTy , Inits ) ; GlobalVariable * MergedGV = new GlobalVariable ( M , MergedTy , isConst , GlobalValue :: InternalLinkage , MergedInit , <STR_LIT> ) ; for ( size_t k = i ; k < j ; ++ k ) { SmallVector < Constant * , <NUM_LIT> > Idx ; Idx . push_back ( ConstantInt :: get ( Int32Ty , <NUM_LIT> )


<s> AU . setPreservesCFG ( ) ; FunctionPass :: getAnalysisUsage


<s> AU . setPreservesCFG ( ) ; FunctionPass :: getAnalysisUsage (


<s> const char * getPassName ( ) const { return


<s> bool <ISA_LIT>GlobalMerge :: runOnFunction ( Function & F ) { return false


<s> uint64_t flags ( ) const { return llvm :: ELF


<s> void <ISA_LIT>GOT :: applyGOT0 ( uint64_t pAddress ) { llvm :: cast < <ISA_LIT>GOTEntry > ( * ( m_SectionData -> getFragmentList ( ) . begin (


<s> void <ISA_LIT>GOT :: applyGOTPLT ( uint64_t pPLTBase ) { if ( m_pGOTPLTFront == NULL ) return ; SectionData :: iterator entry ( m_pGOTPLTFront


<s> for ( unsigned int i = <NUM_LIT> ; i < <ISA_LIT>GOT0Num ; ++ i ) new <ISA_LIT>GOTEntry ( <NUM_LIT>


<s> <ISA_LIT>GOTEntry * <ISA_LIT>GOT :: createGOT ( ) { <ISA_LIT>GOTEntry * entry = new <ISA_LIT>GOTEntry ( <NUM_LIT> , NULL ) ; m_GOT . push_back (


<s> <ISA_LIT>GOTEntry * entry = new <ISA_LIT>GOTEntry ( <NUM_LIT> , NULL ) ; m_GOTPLT . push_back ( entry ) ; return entry


<s> uint64_t result = <NUM_LIT> ; for ( iterator it = begin ( ) , ie = end ( ) ; it != ie ; ++ it , ++ buffer ) { got = & ( llvm :: cast < <ISA_LIT>GOTEntry > ( ( * it ) ) ) ; * buffer = static_cast < uint32_t > ( got -> getValue ( ) ) ; result += <STR_LIT> ; } return result


<s> uint32_t * buffer = reinterpret_cast < uint32_t * > ( pRegion . begin ( ) ) ; <ISA_LIT>GOTEntry * got = NULL ; uint64_t result = <NUM_LIT> ; for ( iterator it = begin ( ) , ie = end ( ) ; it != ie ; ++ it , ++ buffer ) { got = & ( llvm :: cast < <ISA_LIT>GOTEntry > ( ( * it ) ) ) ; * buffer = static_cast < uint32_t > ( got -> getValue ( ) ) ; result += <STR_LIT> ; } return


<s> SectionData :: FragmentListType & frag_list = m_SectionData -> getFragmentList ( ) ; SectionData :: iterator frag , fragEnd = m_SectionData -> end ( ) ; for ( frag = m_SectionData -> begin ( ) ; frag != fragEnd ; ++ frag ) { frag -> setOffset ( offset ) ; offset += frag -> size ( ) ; } if ( ! m_GOTPLT . empty ( ) ) { m_pGOTPLTFront = m_GOTPLT . front ( ) ; entry_iterator it , end = m_GOTPLT . end ( ) ; for ( it = m_GOTPLT . begin ( ) ; it != end ; ++ it ) { <ISA_LIT>GOTEntry * entry = * it ; frag_list . push_back ( entry ) ; entry -> setParent ( m_SectionData ) ; entry -> setOffset ( offset ) ; offset += entry -> size ( ) ; } } m_GOTPLT . clear ( ) ; if ( ! m_GOT . empty ( ) ) { m_pGOTFront = m_GOT . front ( ) ; entry_iterator it , end = m_GOT . end ( ) ; for ( it = m_GOT . begin ( ) ; it != end ; ++


<s> frag -> setOffset ( offset ) ; offset += frag -> size ( ) ; } if ( ! m_GOTPLT . empty ( ) ) { m_pGOTPLTFront = m_GOTPLT . front ( ) ; entry_iterator it , end = m_GOTPLT . end ( ) ; for ( it = m_GOTPLT . begin ( ) ; it != end ; ++ it ) { <ISA_LIT>GOTEntry * entry = * it ; frag_list . push_back ( entry ) ; entry -> setParent ( m_SectionData ) ; entry -> setOffset ( offset ) ; offset += entry -> size ( ) ; } } m_GOTPLT . clear ( ) ; if ( ! m_GOT . empty ( ) ) { m_pGOTFront = m_GOT . front ( ) ; entry_iterator it , end = m_GOT


<s> bool <ISA_LIT>GOT :: hasGOT1 ( ) const { return ( ( ! m_GOT . empty ( ) ) || ( ! m_GOTPLT . empty


<s> void <ISA_LIT>HazardRecognizer :: AdvanceCycle ( ) { if ( FpMLxStalls && -- FpMLxStalls == <NUM_LIT> ) LastMI = nullptr ; ScoreboardHazardRecognizer :: AdvanceCycle (


<s> if ( FpMLxStalls && -- FpMLxStalls == <NUM_LIT>


<s> if ( ( Domain & <STR_LIT> ) || ( Domain & <STR_LIT> ) ) return MI -> readsRegister ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , & TRI ) ; return


<s> FpMLxStalls = <NUM_LIT> ; ScoreboardHazardRecognizer :: Reset (


<s> void <ISA_LIT>HazardRecognizer :: AdvanceCycle ( ) { if ( Stalls && -- Stalls == <NUM_LIT> ) LastMI = <NUM_LIT> ; ScoreboardHazardRecognizer :: AdvanceCycle


<s> unsigned Mask = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned NumTZ = CountTrailingZeros_32 ( Mask ) ; assert ( NumTZ <= <NUM_LIT> && <STR_LIT> ) ; ITBlockSize = <NUM_LIT> - NumTZ ; MachineBasicBlock :: iterator I = MI ; for ( unsigned i = <NUM_LIT> ; i < ITBlockSize ; ++ i ) { do { ++ I ; } while ( I -> isDebugValue ( ) ) ; ITBlockMIs [ ITBlockSize - <NUM_LIT> - i ] = & * I ; } } if ( ! MI -> isDebugValue ( ) ) { LastMI = MI ; Stalls = <NUM_LIT> ; } ScoreboardHazardRecognizer :: EmitInstruction (


<s> unsigned Opcode = MI -> getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return false ; } else if ( Domain == <STR_LIT> ) { if ( MI -> getDesc ( ) . mayStore ( ) || MI -> getDesc ( ) . mayLoad ( ) ) return false ; } else return false


<s> Stalls = <NUM_LIT> ; ITBlockSize = <NUM_LIT>


<s> void <ISA_LIT>HazardRecognizer :: AdvanceCycle ( ) { if ( FpMLxStalls && -- FpMLxStalls == <NUM_LIT> ) LastMI = <NUM_LIT> ; ScoreboardHazardRecognizer :: AdvanceCycle


<s> LastMI = <NUM_LIT> ; FpMLxStalls = <NUM_LIT> ; ScoreboardHazardRecognizer :: Reset


<s> <ISA_LIT>HazardRecognizer ( const InstrItineraryData * ItinData , const <ISA_LIT>BaseInstrInfo & tii , const <ISA_LIT>BaseRegisterInfo & tri

, const <ISA_LIT>Subtarget & sti , const ScheduleDAG * DAG ) :


<s> <ISA_LIT>HazardRecognizer ( const InstrItineraryData * ItinData , const <ISA_LIT>BaseInstrInfo & tii , const <ISA_LIT>BaseRegisterInfo

& tri , const <ISA_LIT>Subtarget & sti , const ScheduleDAG * DAG ) :


<s> if ( ! LastMI -> isBarrier ( ) && ! ( TII . getSubtarget ( ) . hasMuxedUnits ( ) && LastMI -> mayLoadOrStore ( ) ) && ( LastMCID . TSFlags & <STR_LIT> ) == <STR_LIT> ) { MachineBasicBlock :: iterator I = LastMI ; if ( I != LastMI -> getParent ( ) -> begin ( ) ) { I = std :: prev ( I ) ; DefMI = & * I ; } } if ( TII . isFpMLxInstruction ( DefMI -> getOpcode ( ) ) && ( TII . canCauseFpMLxStall ( MI -> getOpcode ( ) ) || hasRAWHazard ( DefMI , MI , TII . getRegisterInfo ( ) ) ) ) { if ( FpMLxStalls == <NUM_LIT> ) FpMLxStalls = <NUM_LIT> ; return


<s> void <ISA_LIT>BankConflictHazardRecognizer :: AdvanceCycle ( ) { Accesses . clear


<s> void <ISA_LIT>BankConflictHazardRecognizer :: EmitInstruction ( SUnit * SU ) { MachineInstr & MI = * SU -> getInstr ( ) ; if ( ! MI . mayLoad ( ) || MI . mayStore ( ) || MI . getNumMemOperands ( ) != <NUM_LIT> ) return ; auto MO = * MI . memoperands ( ) . begin ( ) ; uint64_t Size1 = MO -> getSize ( ) ; if ( Size1 > <NUM_LIT> )


<s> if ( ! MI . mayLoad ( ) || MI . mayStore ( ) || MI . getNumMemOperands ( ) != <NUM_LIT> ) return ; auto MO = * MI . memoperands ( ) . begin ( ) ; uint64_t Size1 = MO ->


<s> return false ; case <STR_LIT> : BaseOp = & MI . getOperand ( <NUM_LIT> ) ; Offset = ( IndexMode == <STR_LIT> ) ? <NUM_LIT> : ( IndexMode == <STR_LIT> || IndexMode == <STR_LIT> ) ? MI . getOperand ( <NUM_LIT> ) . getImm ( ) : MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; case <STR_LIT> : BaseOp = & MI . getOperand ( <NUM_LIT> ) ; Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; case <STR_LIT> : BaseOp = & MI . getOperand ( <NUM_LIT> ) ; Offset = ( IndexMode == <STR_LIT> ) ? <NUM_LIT> : ( IndexMode == <STR_LIT> || IndexMode == <STR_LIT> ) ? MI . getOperand ( <NUM_LIT> ) . getImm ( ) : MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; case <STR_LIT> : case <STR_LIT>


<s> void <ISA_LIT>BankConflictHazardRecognizer :: RecedeCycle ( ) { Accesses . clear (


<s> const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF -> getSubtarget ( ) . getInstrInfo ( ) ) ; if ( ! LastMI -> isBarrier ( ) && ! ( TII . getSubtarget ( ) . isLikeA9 ( ) && LastMI -> mayLoadOrStore ( ) ) && ( LastMCID . TSFlags & <STR_LIT> ) == <STR_LIT> ) { MachineBasicBlock :: iterator I = LastMI ; if ( I != LastMI -> getParent ( ) -> begin


<s> if ( ITBlockSize ) { -- ITBlockSize ; } else if ( Opcode == <STR_LIT> ) { unsigned Mask = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned NumTZ = CountTrailingZeros_32 ( Mask ) ; assert ( NumTZ <= <NUM_LIT> && <STR_LIT> ) ; ITBlockSize = <NUM_LIT> - NumTZ ; MachineBasicBlock :: iterator I = MI ; for ( unsigned i = <NUM_LIT> ; i < ITBlockSize ; ++ i ) { do { ++ I ; } while ( I -> isDebugValue (


<s> unsigned Domain = TID . TSFlags & <STR_LIT> ; if ( TID . mayStore ( ) ) return false ; unsigned Opcode = TID . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode ==


<s> unsigned Domain = TID . TSFlags & <STR_LIT> ; if ( TID . mayStore ( ) ) return false ; unsigned Opcode = TID . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return false ; if ( ( Domain & <STR_LIT> ) || ( Domain & <STR_LIT> ) ) return MI -> readsRegister ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , & TRI ) ; return


<s> void <ISA_LIT>HazardRecognizer :: Reset ( ) { LastMI =


<s> void <ISA_LIT>HazardRecognizer :: Reset ( ) { LastMI = <NUM_LIT> ; FpMLxStalls = <NUM_LIT> ; ITBlockSize =


<s> ScheduleHazardRecognizer :: HazardType <ISA_LIT>HazardRecognizer :: getHazardType ( SUnit * SU , int Stalls ) { assert ( Stalls == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * MI = SU -> getInstr ( ) ; if ( ! MI -> isDebugValue ( ) ) { const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( LastMI && ( MCID . TSFlags & <STR_LIT> ) != <STR_LIT> ) { MachineInstr * DefMI = LastMI ; const MCInstrDesc & LastMCID = LastMI -> getDesc ( ) ; const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF -> getSubtarget ( ) . getInstrInfo ( ) ) ; if ( ! LastMI -> isBarrier ( ) && ! ( TII . getSubtarget ( ) . isLikeA9 ( ) && ( LastMI -> mayLoad ( ) || LastMI -> mayStore ( ) ) ) && ( LastMCID . TSFlags & <STR_LIT> ) == <STR_LIT> ) { MachineBasicBlock :: iterator I = LastMI ; if ( I != LastMI -> getParent ( ) -> begin ( ) ) { I = std :: prev ( I ) ; DefMI = & * I ; } } if ( TII . isFpMLxInstruction ( DefMI -> getOpcode ( ) ) && ( TII . canCauseFpMLxStall ( MI -> getOpcode ( ) ) || hasRAWHazard ( DefMI , MI , TII . getRegisterInfo ( ) ) ) ) { if ( FpMLxStalls == <NUM_LIT> ) FpMLxStalls


<s> ScheduleHazardRecognizer :: HazardType <ISA_LIT>HazardRecognizer :: getHazardType ( SUnit * SU , int Stalls ) { assert ( Stalls == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * MI = SU -> getInstr ( ) ; if ( ! MI -> isDebugValue ( ) ) { const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( LastMI && ( MCID . TSFlags & <STR_LIT> ) != <STR_LIT> ) { MachineInstr * DefMI = LastMI ; const MCInstrDesc & LastMCID = LastMI -> getDesc (


<s> if ( ! LastMI -> isBarrier ( ) && ! ( TII . getSubtarget ( ) . isLikeA9 ( ) && ( LastMI -> mayLoad ( ) || LastMI -> mayStore ( ) ) ) && ( LastMCID . TSFlags & <STR_LIT> ) == <STR_LIT> ) { MachineBasicBlock :: iterator I = LastMI ; if ( I != LastMI -> getParent ( ) -> begin ( ) ) { I = std :: prev ( I ) ; DefMI = & * I ; } } if ( TII . isFpMLxInstruction ( DefMI -> getOpcode ( ) ) && ( TII . canCauseFpMLxStall ( MI -> getOpcode ( ) ) || hasRAWHazard ( DefMI , MI , TII .


<s> const TargetMachine & TM = MI -> getParent ( ) -> getParent ( ) -> getTarget ( ) ; const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( TM . getInstrInfo ( ) ) ; if ( ! LastMI -> isBarrier ( ) && ! ( TII . getSubtarget ( ) . isLikeA9 ( ) && ( LastMI -> mayLoad ( ) || LastMI -> mayStore ( ) ) ) && ( LastMCID . TSFlags & <STR_LIT> ) == <STR_LIT> ) { MachineBasicBlock :: iterator I = LastMI ; if ( I != LastMI -> getParent ( ) -> begin ( ) ) { I = llvm :: prior ( I ) ; DefMI = & * I ; } } if ( TII . isFpMLxInstruction ( DefMI -> getOpcode ( ) ) && ( TII . canCauseFpMLxStall ( MI -> getOpcode ( ) ) || hasRAWHazard ( DefMI , MI , TII . getRegisterInfo ( ) ) ) ) { if ( FpMLxStalls == <NUM_LIT> ) FpMLxStalls = <NUM_LIT> ; return Hazard


<s> <ISA_LIT>BankConflictHazardRecognizer :: <ISA_LIT>BankConflictHazardRecognizer ( const ScheduleDAG * DAG , int64_t CPUBankMask , bool CPUAssumeITCMConflict ) : MF ( DAG -> MF ) , DL ( DAG -> MF . getDataLayout ( ) ) , DataMask ( DataBankMask . getNumOccurrences ( ) ? int64_t ( DataBankMask

) : CPUBankMask ) , AssumeITCMBankConflict ( AssumeITCMConflict . getNumOccurrences ( ) ? AssumeITCMConflict : CPUAssumeITCMConflict ) {


<s> ScoreboardHazardRecognizer ( ItinData ) , TII ( tii ) , TRI ( tri ) , STI ( sti ) , LastMI ( <NUM_LIT> ) , ITBlockSize


<s> <ISA_LIT>HazardRecognizer ( const InstrItineraryData * ItinData , const <ISA_LIT>BaseInstrInfo & tii , const <ISA_LIT>BaseRegisterInfo & tri , const <ISA_LIT>Subtarget & sti , const ScheduleDAG * DAG ) : ScoreboardHazardRecognizer ( ItinData , DAG , <STR_LIT> ) , TII ( tii ) , TRI ( tri ) , STI


<s> if ( ! MI -> isDebugValue ( ) ) { LastMI = MI ; FpMLxStalls = <NUM_LIT> ; } ScoreboardHazardRecognizer :: EmitInstruction (


<s> void <ISA_LIT>HazardRecognizer :: EmitInstruction ( SUnit * SU ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( ! MI -> isDebugValue ( ) ) { LastMI = MI ; FpMLxStalls = <NUM_LIT> ; } ScoreboardHazardRecognizer :: EmitInstruction (


<s> void <ISA_LIT>InstPrinter :: printAddrMode2OffsetOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; if ( ! MO1 . getReg ( ) ) { unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; O << markup ( <STR_LIT> ) << '#' << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << ImmOffs << markup ( <STR_LIT> ) ; return ; } O << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) ; printRegName ( O , MO1 .


<s> const MCOperand & MO1 = MI -> getOperand ( Op ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op , O ) ; return ; } const MCOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; unsigned IdxMode = <STR_LIT> ( MO3 . getImm ( ) ) ; assert ( IdxMode != <STR_LIT> &&


<s> } unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; O << markup ( <STR_LIT> ) << '#' << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) )


<s> printOperand ( MI , OpNum , O ) ; return ; } O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; unsigned Op = <STR_LIT> ( MO2 . getImm ( ) ) ; if ( AlwaysPrintImm0 || ImmOffs || Op


<s> unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; unsigned Op = <STR_LIT> ( MO2 . getImm ( ) ) ; if ( AlwaysPrintImm0 || ImmOffs || Op == <STR_LIT> ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << ImmOffs * <NUM_LIT> << markup ( <STR_LIT> ) ; } O << <STR_LIT> << markup (


<s> O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( )


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; O << markup ( <STR_LIT> )


<s> O << <STR_LIT> ; printRegName ( O , MO2 . getReg ( ) ) ; O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << markup (

<STR_LIT> ) << <STR_LIT> << markup ( <STR_LIT> ) ;


<s> int32_t OffImm = ( int32_t ) MO . getImm ( ) << scale ; O << markup ( <STR_LIT> ) ; if ( OffImm == INT32_MIN ) O << <STR_LIT> ; else if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm ; else O << <STR_LIT> <<


<s> printRegName ( O , MO1 . getReg ( ) ) ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( MO3 . getImm ( ) ) ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << <STR_LIT> ( MO3 . getImm ( ) ) << markup ( <STR_LIT> ) ; } O << <STR_LIT> << markup ( <STR_LIT> ) ; return ; } O << <STR_LIT> ; O << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) ; printRegName ( O , MO2 . getReg ( ) ) ; printRegImmShift ( O , <STR_LIT> ( MO3 . getImm ( ) ) , <STR_LIT> ( MO3


<s> uint32_t v = ~ MO . getImm ( ) ; int32_t lsb = countTrailingZeros ( v ) ; int32_t width = ( <NUM_LIT> - countLeadingZeros ( v ) ) - lsb ; assert ( MO . isImm ( ) && <STR_LIT> ) ; O << markup ( <STR_LIT> ) << '#' << lsb << markup ( <STR_LIT> ) << <STR_LIT> <<

markup ( <STR_LIT> ) << '#' << width << markup ( <STR_LIT> ) ;


<s> O << <STR_LIT> << MI -> getOperand ( OpNum )


<s> O << <STR_LIT> << MI -> getOperand ( OpNum


<s> void <ISA_LIT>InstPrinter :: printCPSIFlag ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNum ) ; unsigned IFlags = Op . getImm ( ) ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( IFlags & ( <NUM_LIT> << i ) ) O << <STR_LIT> ( <NUM_LIT> << i ) ; if ( IFlags == <NUM_LIT> ) O


<s> void <ISA_LIT>InstPrinter :: printCPSIMod ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand


<s> void <ISA_LIT>InstPrinter :: printCPSIMod ( const MCInst * MI , unsigned OpNum ,


<s> O << markup ( <STR_LIT> ) << <STR_LIT> << <NUM_LIT> - MI -> getOperand ( OpNum ) . getImm ( ) << markup


<s> O << markup ( <STR_LIT> ) << <STR_LIT> << <NUM_LIT> - MI -> getOperand

( OpNum ) . getImm ( ) << markup ( <STR_LIT> ) ;


<s> void <ISA_LIT>InstPrinter :: printFBits32 ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << markup ( <STR_LIT> ) << <STR_LIT> << <NUM_LIT> - MI -> getOperand ( OpNum ) . getImm ( ) << markup (


<s> void <ISA_LIT>InstPrinter :: printFPImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; O << markup ( <STR_LIT> ) << '#' << <STR_LIT> ( MO . getImm ( )


<s> void <ISA_LIT>InstPrinter :: printGPRPairOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { unsigned Reg = MI -> getOperand ( OpNum ) . getReg


<s> void <ISA_LIT>InstPrinter :: printImmPlusOneOperand ( const MCInst * MI ,


<s> void <ISA_LIT>InstPrinter :: printInstSyncBOption ( const MCInst * MI , unsigned OpNum , raw_ostream


<s> unsigned val = MI -> getOperand ( OpNum ) . getImm ( ) ; O << <STR_LIT> ( val


<s> void <ISA_LIT>InstPrinter :: printLdStmModeOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { <STR_LIT> Mode = <STR_LIT> ( MI -> getOperand ( OpNum ) . getImm ( ) ) ; O << <STR_LIT> (


<s> void <ISA_LIT>InstPrinter :: printLdStmModeOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { <STR_LIT> Mode = <STR_LIT> ( MI -> getOperand ( OpNum ) . getImm (


<s> void <ISA_LIT>InstPrinter :: printMandatoryPredicateOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum ) . getImm ( ) ; O << <ISA_LIT>CondCodeToString ( CC )


<s> <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum )


<s> case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; } } if ( ! SpecRegRBit && ( Mask == <NUM_LIT> || Mask == <NUM_LIT> || Mask == <NUM_LIT> ) ) { O << <STR_LIT> ; switch ( Mask ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } } if ( SpecRegRBit ) O << <STR_LIT> ; else O << <STR_LIT> ; if ( Mask ) { O << '_' ; if ( Mask & <NUM_LIT> )


<s> void <ISA_LIT>InstPrinter :: printNoHashImmediate ( const MCInst * MI , unsigned OpNum


<s> switch ( Expr -> getKind ( ) ) { case MCExpr :: Binary : O << '#' << * Expr ; break ; case MCExpr :: Constant : { const MCConstantExpr * Constant = cast < MCConstantExpr > ( Expr ) ; int64_t TargetAddress ; if ( ! Constant -> EvaluateAsAbsolute ( TargetAddress ) ) { O << '#' << * Expr ; } else { O <<


<s> void <ISA_LIT>InstPrinter :: printPCLabel ( const MCInst * MI , unsigned OpNum , raw_ostream &


<s> void <ISA_LIT>InstPrinter :: printPCLabel ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { llvm_unreachable ( <STR_LIT>


<s> unsigned Imm = MI -> getOperand ( OpNum ) . getImm ( ) ; if ( Imm == <NUM_LIT> ) return ; assert ( Imm > <NUM_LIT> && Imm < <NUM_LIT> && <STR_LIT> ) ; O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << Imm << markup


<s> unsigned Imm = MI -> getOperand ( OpNum ) . getImm ( ) ; if ( Imm ==


<s> O << markup ( <STR_LIT> ) << '#' << ( ( Imm & <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) << ( Imm


<s> const MCOperand & MO = MI -> getOperand ( OpNum ) ; unsigned Imm = MO . getImm ( ) ; O << markup ( <STR_LIT> ) << '#' << ( ( Imm & <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) << ( Imm


<s> void <ISA_LIT>InstPrinter :: printPostIdxRegOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << ( MO2 . getImm ( )


<s> assert ( ! ( ShOpc == <STR_LIT> && ! ShImm ) && <STR_LIT> ) ; O << getShiftOpcStr ( ShOpc ) ; if ( ShOpc != <STR_LIT> ) { O <<


<s> void <ISA_LIT>InstPrinter :: printRegisterList ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> ; for ( unsigned i = OpNum , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i != OpNum ) O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( i ) . getReg (


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS


<s> void <ISA_LIT>InstPrinter :: printSBitModifierOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { if ( MI -> getOperand ( OpNum ) . getReg ( ) ) { assert ( MI -> getOperand ( OpNum ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; O <<


<s> void <ISA_LIT>InstPrinter :: printSetendOperand ( const MCInst * MI , unsigned OpNum


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum


<s>
const
MCOperand
&
MO2
=
MI
->
getOperand
(
OpNum
+
<NUM_LIT>
)
;
const
MCOperand
&
MO3
=
MI
->
getOperand
(
OpNum
+
<NUM_LIT>
)
;
printRegName
(
O
,
MO1
.
getReg
(
)
)
;
<STR_LIT>
ShOpc
=
<STR_LIT>
(
MO3
.
getImm
(
)
)
;
O
<<
<STR_LIT>
<<
<STR_LIT>
(
ShOpc
)
;
if
(
ShOpc
==
<STR_LIT>
)
return
;
O
<<
' '
;
printRegName
(
O
,
MO2


<s> int32_t OffImm = ( int32_t ) MO1 . getImm ( ) ; O << <STR_LIT> << markup ( <STR_LIT> ) ; if ( OffImm == INT32_MIN ) O << <STR_LIT> ; else if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm ; else O << <STR_LIT> << OffImm ; O << markup ( <STR_LIT> )


<s> void <ISA_LIT>InstPrinter :: printT2AddrModeImm8Operand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; bool isSub = OffImm < <NUM_LIT> ; if ( OffImm == INT32_MIN ) OffImm = <NUM_LIT> ; if ( isSub ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << - OffImm << markup ( <STR_LIT> ) ; } else if ( AlwaysPrintImm0 || OffImm > <NUM_LIT> ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << OffImm << markup


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; int32_t OffImm = ( int32_t ) MO1 . getImm ( ) ; assert ( ( ( OffImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; O << <STR_LIT> << markup


<s> int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; bool isSub = OffImm < <NUM_LIT> ; assert ( ( ( OffImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( OffImm == INT32_MIN ) OffImm = <NUM_LIT> ; if ( isSub ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << - OffImm << markup ( <STR_LIT> ) ; } else if ( AlwaysPrintImm0 || OffImm > <NUM_LIT>


<s> printRegName ( O , MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; bool isSub = OffImm < <NUM_LIT> ; assert ( ( ( OffImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( OffImm == INT32_MIN ) OffImm = <NUM_LIT> ; if ( isSub ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << - OffImm << markup ( <STR_LIT> ) ; } else if ( AlwaysPrintImm0 || OffImm > <NUM_LIT> ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << OffImm <<


<s> void <ISA_LIT>InstPrinter :: printT2SOOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; unsigned Reg = MO1


<s> printThumbAddrModeImm5SOperand ( MI , Op , O ,


<s> void <ISA_LIT>InstPrinter :: printThumbAddrModeImm5S2Operand ( const MCInst * MI , unsigned Op , raw_ostream &


<s> void <ISA_LIT>InstPrinter :: printThumbAddrModeImm5SOperand ( const MCInst * MI , unsigned Op , raw_ostream & O , unsigned Scale ) { const MCOperand & MO1 = MI -> getOperand ( Op ) ; const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op , O ) ; return ; } O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; if ( unsigned ImmOffs = MO2 . getImm ( ) ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( ImmOffs * Scale ) << markup ( <STR_LIT> ) ; } O << <STR_LIT> << markup ( <STR_LIT>


<s> } O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; if ( unsigned RegNum = MO2 . getReg ( ) ) { O << <STR_LIT> ; printRegName ( O , RegNum ) ; } O << <STR_LIT> << markup ( <STR_LIT> )


<s> for ( unsigned Pos = <NUM_LIT> , e = NumTZ ; Pos > e ; -- Pos ) { bool T = ( ( Mask >> Pos ) & <NUM_LIT> ) == CondBit0 ; if ( T ) O << 't' ; else O <<


<s> void <ISA_LIT>InstPrinter :: printThumbITMask ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { unsigned Mask = MI -> getOperand ( OpNum ) . getImm ( ) ; unsigned Firstcond = MI -> getOperand ( OpNum - <NUM_LIT> ) . getImm ( ) ; unsigned CondBit0 = Firstcond & <NUM_LIT> ; unsigned NumTZ = countTrailingZeros ( Mask ) ; assert ( NumTZ <= <NUM_LIT> && <STR_LIT> ) ; for ( unsigned Pos = <NUM_LIT> , e = NumTZ ; Pos > e ; --


<s> O << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( ( Imm == <NUM_LIT> ? <NUM_LIT> : Imm


<s> void <ISA_LIT>InstPrinter :: printVectorIndex ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << MI -> getOperand ( OpNum ) . getImm ( ) <<


<s> void <ISA_LIT>InstPrinter :: printVectorListFour ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) .


<s> printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O <<


<s> O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) +


<s> void <ISA_LIT>InstPrinter :: printVectorListOne ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O <<


<s> O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum


<s> O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg


<s> O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O <<


<s> O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O <<


<s> O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) .


<s> printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( )


<s> O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) .


<s> void <ISA_LIT>InstPrinter :: printVectorListTwo ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; unsigned Reg0 = MRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , Reg0 ) ; O << <STR_LIT> ; printRegName ( O , Reg1 ) ; O <<


<s> void <ISA_LIT>InstPrinter :: printVectorListTwoAllLanes ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; unsigned Reg0 = MRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , Reg0 ) ; O <<


<s> void <ISA_LIT>InstPrinter :: printVectorListTwoSpaced ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; unsigned Reg0 = MRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , Reg0 ) ; O << <STR_LIT> ; printRegName ( O , Reg1 ) ; O <<


<s> unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , Reg0 ) ; O << <STR_LIT>


<s> if ( imm == <NUM_LIT> ) return <NUM_LIT> ; return imm


<s> static unsigned translateShiftImm ( unsigned imm ) { assert ( ( imm & ~ <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; if ( imm == <NUM_LIT> )


<s> } if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getNumOperands ( ) > <NUM_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; if ( Opcode == <STR_LIT> ) O << <STR_LIT> ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( Opcode == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; O << <STR_LIT> ; printAnnotation ( O , Annot ) ; return ; } if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( Opcode == <STR_LIT> ) { bool Writeback = true ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( unsigned i = <NUM_LIT> ; i < MI -> getNumOperands ( ) ; ++ i ) { if ( MI -> getOperand ( i ) . getReg ( ) == BaseReg ) Writeback = false ; } O << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegName ( O , BaseReg ) ; if ( Writeback ) O << <STR_LIT> ; O << <STR_LIT> ; printRegisterList ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { const MCRegisterClass & MRC = MRI . getRegClass ( <STR_LIT> ) ; bool isStore = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; unsigned Reg = MI -> getOperand ( isStore ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; if ( MRC . contains ( Reg


<s> void <ISA_LIT>InstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { unsigned Reg = Op . getReg ( ) ; printRegName ( O , Reg ) ; } else if ( Op . isImm ( ) ) { O << markup ( <STR_LIT> ) << '#' << formatImm ( Op . getImm ( ) ) << markup ( <STR_LIT> ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( Op . getExpr ( ) ) ; int64_t Address ; if ( BranchTarget && BranchTarget -> EvaluateAsAbsolute ( Address ) ) { O << <STR_LIT>


<s> unsigned IdxMode = <STR_LIT> ( MO3 . getImm ( ) ) ; if ( IdxMode == <STR_LIT> ) { printAM3PostIndexOp ( MI , Op , O ) ; return ; } printAM3PreOrOffsetIndexOp ( MI , Op ,


<s> printRegName ( O , MO1 . getReg ( ) ) ; unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; unsigned Op = <STR_LIT> ( MO2 . getImm ( ) ) ; if ( ImmOffs || Op == <STR_LIT> ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << ImmOffs * <NUM_LIT> << markup ( <STR_LIT> ) ; } O << <STR_LIT> << markup (


<s> const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; if ( MO2 . getImm ( )


<s> if ( MO2 . getReg ( ) ) { O << <STR_LIT> << getAddrOpcStr ( <STR_LIT> ( MO3 . getImm ( ) ) ) ; printRegName ( O , MO2 . getReg ( ) ) ; O << ']' << markup ( <STR_LIT> ) ; return ; } unsigned ImmOffs = <STR_LIT> ( MO3 . getImm ( ) ) ; <STR_LIT> op = <STR_LIT> ( MO3 . getImm ( ) ) ; if ( ImmOffs || ( op == <STR_LIT> ) ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << <STR_LIT>

( op ) << ImmOffs << markup ( <STR_LIT> ) ;


<s> void <ISA_LIT>InstPrinter :: printImmPlusOneOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { unsigned Imm = MI -> getOperand ( OpNum )


<s> O << markup ( <STR_LIT> ) << <STR_LIT> << Imm +


<s> const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; if ( MO2 . getImm


<s> O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << MO2 . getImm ( ) * <NUM_LIT> << markup ( <STR_LIT> ) ; } O << <STR_LIT> << markup


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; int32_t OffImm = ( int32_t ) MO1 . getImm (


<s> void <ISA_LIT>InstPrinter :: printT2AddrModeImm8Operand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; if ( OffImm != <NUM_LIT> ) O << <STR_LIT> ; if ( OffImm != <NUM_LIT> && UseMarkup ) O << <STR_LIT> ; if ( OffImm == INT32_MIN ) O << <STR_LIT> ; else if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm ; else if ( OffImm > <NUM_LIT> ) O << <STR_LIT> << OffImm ; if ( OffImm != <NUM_LIT> && UseMarkup ) O << <STR_LIT> ; O << <STR_LIT> << markup ( <STR_LIT>


<s> assert ( ( ( OffImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( OffImm != <NUM_LIT> ) O << <STR_LIT> ; if ( OffImm != <NUM_LIT> && UseMarkup ) O << <STR_LIT> ; if ( OffImm == INT32_MIN ) O << <STR_LIT> ; else if ( OffImm < <NUM_LIT> ) O << <STR_LIT>


<s> int32_t OffImm = ( int32_t ) MO1 . getImm ( ) ; assert ( ( ( OffImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( OffImm != <NUM_LIT> ) O << <STR_LIT> ; if ( OffImm != <NUM_LIT> && UseMarkup


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , OpNum , O ) ; return ; } O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; assert ( ( ( OffImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( OffImm != <NUM_LIT> ) O << <STR_LIT> ; if ( OffImm != <NUM_LIT> && UseMarkup )


<s> if ( OffImm != <NUM_LIT> && UseMarkup ) O << <STR_LIT> ; if ( OffImm == INT32_MIN ) O << <STR_LIT> ; else if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm ; else if ( OffImm > <NUM_LIT> ) O << <STR_LIT> << OffImm ; if ( OffImm != <NUM_LIT> && UseMarkup ) O << <STR_LIT> ; O << <STR_LIT> << markup ( <STR_LIT>


<s> printOperand ( MI , Op , O ) ; return ; } O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; if ( unsigned ImmOffs = MO2 . getImm (


<s> assert ( NumTZ <= <NUM_LIT> && <STR_LIT> ) ; for ( unsigned Pos = <NUM_LIT> , e = NumTZ ; Pos > e ; -- Pos ) { bool T = ( ( Mask >> Pos ) & <NUM_LIT> ) == CondBit0 ; if ( T ) O <<


<s> void <ISA_LIT>InstPrinter :: printThumbS4ImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << markup ( <STR_LIT> ) << <STR_LIT> << MI -> getOperand ( OpNum )

. getImm ( ) * <NUM_LIT> << markup ( <STR_LIT> ) ;


<s> printPredicateOperand ( MI , <NUM_LIT> , O ) ; if ( Opcode == <STR_LIT> ) O << <STR_LIT> ; printAnnotation ( O , Annot ) ; return ; } if ( Opcode == <STR_LIT> ) { const MCOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; const MCOperand & MO1 = MI -> getOperand ( <NUM_LIT> ) ; const MCOperand & MO2 = MI -> getOperand ( <NUM_LIT> ) ; const MCOperand & MO3 = MI -> getOperand ( <NUM_LIT> ) ; O << '\t' << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) ; printSBitModifierOperand ( MI , <NUM_LIT> , O ) ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegName ( O , Dst . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MO2 . getReg ( ) ) ; assert ( <STR_LIT> ( MO3 . getImm ( ) ) == <NUM_LIT> ) ; printAnnotation ( O , Annot ) ; return ; } if ( Opcode == <STR_LIT> ) { const MCOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; const MCOperand & MO1 = MI -> getOperand ( <NUM_LIT> ) ; const MCOperand & MO2 = MI -> getOperand ( <NUM_LIT> ) ; O << '\t' << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) ; printSBitModifierOperand ( MI , <NUM_LIT> , O ) ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegName ( O , Dst . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; if ( <STR_LIT> ( MO2 . getImm ( ) ) == <STR_LIT> ) { printAnnotation ( O , Annot ) ; return ; } O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << translateShiftImm ( <STR_LIT> ( MO2 . getImm ( ) ) ) << markup ( <STR_LIT> ) ; printAnnotation ( O , Annot ) ; return ; } if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getNumOperands ( ) > <NUM_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; if ( Opcode == <STR_LIT> ) O << <STR_LIT> ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( Opcode == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == - <NUM_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT>


<s> if ( <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << <STR_LIT> ( MO3 . getImm ( ) ) ; O << <STR_LIT> ; return ; } O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << getRegisterName ( MO2 . getReg ( ) ) ; if ( unsigned ShImm = <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm (


<s> const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; if ( MO1 . getReg ( ) ) { O << ( char ) <STR_LIT> ( MO2 . getImm ( ) ) << getRegisterName ( MO1 . getReg ( ) ) ; return ; } unsigned ImmOffs = <STR_LIT> ( MO2 .


<s> void <ISA_LIT>InstPrinter :: printAddrMode3Operand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; const MCOperand & MO3 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << '[' << getRegisterName ( MO1 . getReg ( ) ) ; if ( MO2 . getReg ( )


<s> O << '[' << getRegisterName ( MO1 . getReg ( ) ) ; if ( MO2 . getReg ( ) ) { O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << getRegisterName ( MO2 . getReg ( ) ) << ']' ; return ; } if ( unsigned ImmOffs = <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm