<s> MachineInstr & MI = * MBBI ; DebugLoc DL = MI . getDebugLoc ( ) ; const MachineOperand & Dest = MI . getOperand ( <NUM_LIT> ) ; Register TempReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( ! MI . getOperand ( <NUM_LIT> ) . isUndef ( ) && <STR_LIT> ) ; Register AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register DesiredReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register NewReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( IsThumb ) { assert ( STI -> hasV8MBaselineOps ( ) && <STR_LIT> ) ; assert ( ( UxtOp == <NUM_LIT> || UxtOp == <STR_LIT> || UxtOp == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( UxtOp == <NUM_LIT> || <STR_LIT> . contains ( DesiredReg ) ) && <STR_LIT> ) ; } MachineFunction * MF = MBB . getParent ( ) ; auto LoadCmpBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto StoreBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto DoneBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , LoadCmpBB ) ; MF -> insert ( ++ LoadCmpBB -> getIterator ( ) , StoreBB ) ; MF -> insert ( ++ StoreBB -> getIterator ( ) , DoneBB ) ; if (


<s> MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( NewOpc ) ) ; unsigned Flags = getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) | getDefRegState ( MI . getOperand ( <NUM_LIT> ) . isDef ( ) ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MIB . add ( MI . getOperand ( <NUM_LIT> ) ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; MIB . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , Flags ) ; MIB . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , Flags ) ; MIB . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , Flags ) ; MIB . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , Flags ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { MIB . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , Flags ) ; MIB . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , Flags ) ; MIB . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , Flags ) ; MIB . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , Flags ) ; } if ( NewOpc == <STR_LIT> ) MIB . addReg ( SrcReg , RegState


<s> SubRegIndex = <STR_LIT> ; } Register SubReg = TRI -> getSubReg ( DstReg , SubRegIndex ) ; unsigned DstRegPair = TRI -> getMatchingSuperReg ( SubReg , <STR_LIT> , & <STR_LIT> ) ; MIB . addReg ( DstRegPair , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } else { unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } if ( TableEntry -> isUpdating ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) { const MachineOperand & AM6Offset = MI . getOperand ( OpIdx ++ ) ; if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { assert ( AM6Offset . getReg ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; } else { MIB . add ( AM6Offset ) ; } } unsigned SrcOpIdx = <NUM_LIT> ; if ( ! IsVLD2DUP ) { if ( RegSpc == EvenDblSpc || RegSpc == OddDblSpc || RegSpc == SingleLowSpc || RegSpc == SingleHighQSpc || RegSpc == SingleHighTSpc ) SrcOpIdx = OpIdx ++ ; } MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( SrcOpIdx != <NUM_LIT> ) { MachineOperand MO = MI . getOperand ( SrcOpIdx ) ; MO . setImplicit ( true ) ; MIB . add ( MO


<s> auto I = llvm :: lower_bound ( NEONLdStTable , Opcode ) ; if ( I != std :: end ( NEONLdStTable ) && I -> PseudoOpc == Opcode ) return I ; return


<s> if ( ! STI -> hasV6T2Ops ( ) && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) { assert ( ! STI -> isTargetWindows ( ) && <STR_LIT> ) ; LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; unsigned ImmVal = ( unsigned ) MO . getImm ( ) ; unsigned SOImmValV1 = <STR_LIT> ( ImmVal ) ; unsigned SOImmValV2 = <STR_LIT> ( ImmVal ) ; LO16 = LO16 . addImm ( SOImmValV1 ) ; HI16 = HI16 . addImm ( SOImmValV2 ) ; LO16 . cloneMemRefs ( MI ) ; HI16 . cloneMemRefs ( MI ) ; LO16 . addImm ( Pred ) . addReg ( PredReg ) . add ( condCodeOp ( ) ) ; HI16 . addImm ( Pred ) . addReg ( PredReg ) . add ( condCodeOp ( ) ) ; if ( isCC ) LO16 . add ( makeImplicit ( MI . getOperand ( <NUM_LIT> ) ) ) ; TransferImpOps ( MI , LO16 , HI16 ) ; MI . eraseFromParent ( ) ; return ; } unsigned LO16Opc = <NUM_LIT> ; unsigned HI16Opc = <NUM_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } else { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( LO16Opc ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( HI16Opc ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { const char * ES = MO . getSymbolName ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ; HI16 = HI16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ; break ; } default : { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF


<s> if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { assert ( AM6Offset . getReg ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; } else { MIB . add ( AM6Offset ) ; } } unsigned SrcOpIdx = <NUM_LIT> ; if ( TableEntry -> RealOpc != <STR_LIT> && TableEntry -> RealOpc != <STR_LIT> && TableEntry -> RealOpc != <STR_LIT> ) { if ( RegSpc == EvenDblSpc || RegSpc == OddDblSpc || RegSpc == SingleLowSpc || RegSpc == SingleHighQSpc || RegSpc == SingleHighTSpc ) SrcOpIdx = OpIdx ++ ; } MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( SrcOpIdx != <NUM_LIT> ) { MachineOperand MO = MI . getOperand ( SrcOpIdx ) ; MO . setImplicit ( true ) ; MIB . add ( MO ) ; } MIB . addReg ( DstReg , RegState ::

ImplicitDefine | getDeadRegState ( DstIsDead ) ) ;


<s> if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } if ( TableEntry -> isUpdating ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) { const MachineOperand & AM6Offset = MI . getOperand ( OpIdx ++ ) ; if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { assert ( AM6Offset . getReg ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; }


<s> } } bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; bool SrcIsUndef = MI . getOperand ( OpIdx ) . isUndef ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , getUndefRegState ( SrcIsUndef ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( SrcIsKill && ! SrcIsUndef ) MIB -> addRegisterKilled ( SrcReg , TRI , true ) ; else if ( ! SrcIsUndef ) MIB . addReg ( SrcReg , RegState :: Implicit ) ; TransferImpOps ( MI , MIB , MIB ) ; MIB . cloneMemRefs


<s> MachineOperand VdSrc ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( VdSrc ) ; } bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , SingleSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 ) ; MachineOperand VmSrc ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( VmSrc ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addReg ( SrcReg , RegState :: Implicit | getKillRegState ( SrcIsKill ) ) ; TransferImpOps ( MI , MIB , MIB


<s> AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) Modified |= ExpandMBB ( MBB ) ; if ( Verify<ISA_LIT>Pseudo ) MF . verify ( this , <STR_LIT> ) ; return Modified


<s> void <ISA_LIT>ExpandPseudo :: TransferImpOps ( MachineInstr & OldMI , MachineInstrBuilder & UseMI , MachineInstrBuilder & DefMI ) { const MCInstrDesc & Desc = OldMI . getDesc ( ) ; for ( const MachineOperand & MO : llvm :: drop_begin ( OldMI . operands ( ) , Desc . getNumOperands ( ) ) ) { assert ( MO . isReg ( ) && MO .


<s> llvm :: drop_begin ( OldMI . operands ( ) , Desc . getNumOperands ( ) ) ) { assert ( MO . isReg ( ) && MO . getReg ( ) ) ; if ( MO . isUse ( ) ) UseMI . add ( MO ) ; else DefMI . add


<s> DebugLoc DL = MI . getDebugLoc ( ) ; MachineOperand & Dest = MI . getOperand ( <NUM_LIT> ) ; unsigned TempReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( ! MI . getOperand ( <NUM_LIT> ) . isUndef ( ) && <STR_LIT> ) ; unsigned AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DesiredReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand New = MI . getOperand ( <NUM_LIT> ) ; New . setIsKill ( false ) ; unsigned DestLo = TRI -> getSubReg ( Dest . getReg ( ) , <STR_LIT> ) ; unsigned DestHi = TRI -> getSubReg ( Dest . getReg ( ) , <STR_LIT> ) ; unsigned DesiredLo = TRI -> getSubReg ( DesiredReg , <STR_LIT> ) ; unsigned DesiredHi = TRI -> getSubReg ( DesiredReg , <STR_LIT> ) ; MachineFunction * MF = MBB . getParent ( ) ; auto LoadCmpBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto StoreBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto DoneBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , LoadCmpBB ) ; MF -> insert ( ++ LoadCmpBB -> getIterator ( ) , StoreBB ) ; MF -> insert ( ++ StoreBB -> getIterator ( ) , DoneBB ) ; unsigned LDREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( LDREXD ) ) ; addExclusiveRegPair ( MIB , Dest , RegState :: Define , IsThumb , TRI ) ; MIB . addReg ( AddrReg ) . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestLo , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredLo ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestHi , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredHi ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT>


<s> HI16 . addImm ( Pred ) . addReg ( PredReg ) . add ( condCodeOp ( ) ) ; if ( isCC ) LO16 . add ( makeImplicit ( MI . getOperand ( <NUM_LIT> ) ) ) ; TransferImpOps ( MI , LO16 , HI16 ) ; MI . eraseFromParent ( ) ; return ; } unsigned LO16Opc = <NUM_LIT> ; unsigned HI16Opc = <NUM_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } else { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( LO16Opc ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( HI16Opc ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { const char * ES = MO . getSymbolName ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ; HI16 = HI16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ; break ; } default : { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; break ; } } LO16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; HI16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; LO16 . addImm ( Pred ) . addReg ( PredReg ) ; HI16 . addImm ( Pred ) . addReg ( PredReg ) ; if ( RequiresBundling ) finalizeBundle ( MBB , LO16 -> getIterator ( ) , MBBI -> getIterator ( ) ) ; if ( isCC ) LO16 . add ( makeImplicit ( MI . getOperand ( <NUM_LIT> ) ) ) ; TransferImpOps ( MI , LO16 ,


<s> if ( RegSpc == SingleSpc ) { D0 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D2 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D3 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; } else if ( RegSpc == EvenDblSpc ) { D0 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D2 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D3 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; } else { assert ( RegSpc == OddDblSpc && <STR_LIT> ) ; D0 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D2 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D3 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; } MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( hasWriteBack ) { bool WBIsDead = MI . getOperand ( OpIdx ) . isDead ( ) ; unsigned WBReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; MIB . addReg ( WBReg , RegState :: Define | getDeadRegState ( WBIsDead ) ) ; } bool AddrIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; MIB . addReg ( MI . getOperand ( OpIdx ++ ) . getReg ( ) , getKillRegState ( AddrIsKill ) ) ; MIB . addImm ( MI . getOperand ( OpIdx ++ ) . getImm ( ) ) ; if ( hasWriteBack ) { bool OffsetIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; MIB . addReg ( MI . getOperand ( OpIdx ++ ) . getReg ( ) , getKillRegState ( OffsetIsKill ) ) ; } MIB = AddDefaultPred ( MIB


<s> bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ; return


<s> bool <ISA_LIT>ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getTarget ( ) . getInstrInfo ( ) ; TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end (


<s> void <ISA_LIT>ExpandPseudo :: TransferImpOps ( MachineInstr & OldMI , MachineInstrBuilder & UseMI , MachineInstrBuilder & DefMI ) { const TargetInstrDesc & Desc = OldMI . getDesc ( ) ; for ( unsigned i = Desc . getNumOperands ( )


<s> unsigned RegElts = TableEntry -> RegElts ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TableEntry -> RealOpc ) ) ; unsigned OpIdx = <NUM_LIT> ; unsigned Lane = MI . getOperand ( MI . getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) . getImm ( ) ; assert ( RegSpc != OddDblSpc && <STR_LIT> ) ; if ( RegSpc == EvenDblSpc && Lane >= RegElts ) { RegSpc = OddDblSpc ; Lane -= RegElts ; } assert ( Lane < RegElts && <STR_LIT> ) ; unsigned D0 = <NUM_LIT> , D1 = <NUM_LIT> , D2 = <NUM_LIT> , D3 = <NUM_LIT> ; unsigned DstReg = <NUM_LIT> ; bool DstIsDead = false ; if ( TableEntry -> IsLoad ) { DstIsDead = MI . getOperand ( OpIdx ) . isDead ( ) ; DstReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } if ( TableEntry -> isUpdating ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MachineOperand MO = MI . getOperand ( OpIdx ++ ) ; if ( ! TableEntry -> IsLoad ) GetDSubRegs ( MO . getReg ( ) , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; unsigned SrcFlags = ( getUndefRegState ( MO . isUndef ( ) ) | getKillRegState ( MO . isKill ( ) ) ) ; MIB . addReg ( D0 , SrcFlags ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D1 , SrcFlags ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , SrcFlags ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , SrcFlags ) ; MIB . addImm ( Lane ) ; OpIdx +=


<s> } assert ( Lane < RegElts && <STR_LIT> ) ; unsigned D0 = <NUM_LIT> , D1 = <NUM_LIT> , D2 = <NUM_LIT> , D3 = <NUM_LIT> ; unsigned DstReg = <NUM_LIT> ; bool DstIsDead = false ; if ( TableEntry -> IsLoad ) { DstIsDead = MI . getOperand ( OpIdx ) . isDead ( ) ; DstReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } if ( TableEntry -> isUpdating ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MachineOperand MO = MI . getOperand ( OpIdx ++ ) ; if ( ! TableEntry -> IsLoad ) GetDSubRegs ( MO . getReg ( ) , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; unsigned SrcFlags = ( getUndefRegState ( MO . isUndef ( ) ) | getKillRegState ( MO . isKill ( ) ) ) ; MIB . addReg ( D0 , SrcFlags ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D1 ,


<s> MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; bool SrcIsUndef = MI . getOperand ( OpIdx ) . isUndef ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , getUndefRegState


<s> void <ISA_LIT>ExpandPseudo :: CMSESaveClearFPRegs ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc & DL , const LivePhysRegs & LiveRegs , SmallVectorImpl < unsigned > & ScratchRegs ) { if ( STI -> hasV8_1MMainlineOps ( ) ) CMSESaveClearFPRegsV81 (


<s> MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> HasWriteBack ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MachineOperand MO = MI . getOperand ( OpIdx ++ ) ; if ( ! TableEntry -> IsLoad ) GetDSubRegs ( MO . getReg ( ) , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; unsigned SrcFlags = ( getUndefRegState ( MO . isUndef ( ) ) | getKillRegState ( MO . isKill ( ) ) ) ; MIB . addReg ( D0 , SrcFlags ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D1 , SrcFlags ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , SrcFlags ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , SrcFlags ) ; MIB . addImm ( Lane ) ; OpIdx += <NUM_LIT> ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand (


<s> void <ISA_LIT>ExpandPseudo :: ExpandVLD ( MachineBasicBlock :: iterator & MBBI ) { MachineInstr & MI = * MBBI ; MachineBasicBlock & MBB = * MI . getParent ( ) ; const NEONLdStTableEntry * TableEntry = LookupNEONLdSt ( MI . getOpcode ( ) ) ; assert ( TableEntry && TableEntry -> IsLoad && <STR_LIT> ) ; NEONRegSpacing RegSpc = TableEntry -> RegSpacing ; unsigned NumRegs = TableEntry -> NumRegs ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TableEntry -> RealOpc ) ) ; unsigned OpIdx = <NUM_LIT> ; bool DstIsDead = MI . getOperand ( OpIdx ) . isDead ( ) ; unsigned DstReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( TableEntry -> HasWriteBack ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> HasWriteBack ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; unsigned SrcOpIdx = <NUM_LIT> ; if ( RegSpc == EvenDblSpc || RegSpc == OddDblSpc ) SrcOpIdx = OpIdx ++ ; MIB . addOperand ( MI . getOperand ( OpIdx ++


<s> const NEONLdStTableEntry * TableEntry = LookupNEONLdSt ( MI . getOpcode ( ) ) ; assert ( TableEntry && ! TableEntry -> IsLoad && <STR_LIT> ) ; NEONRegSpacing RegSpc = TableEntry -> RegSpacing ; unsigned NumRegs = TableEntry -> NumRegs ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TableEntry -> RealOpc ) ) ; unsigned OpIdx = <NUM_LIT> ; if ( TableEntry -> HasWriteBack ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> HasWriteBack ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 ) . addReg ( D1 ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 ) ; MIB . addOperand ( MI . getOperand ( OpIdx


<s> unsigned OpIdx = <NUM_LIT> ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( IsExt ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , SingleSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 ) . addReg ( D1 ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 ) ; MIB . addOperand ( MI . getOperand (


<s> MIB . addReg ( D0 ) . addReg ( D1 ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( SrcIsKill ) ( * MIB ) . addRegisterKilled ( SrcReg , TRI


<s> TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; STI = & MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ; return Modified


<s> TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; STI = & MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |=


<s> } } } bool returnsFPReg = ( ! NonclearedFPRegs . empty ( ) || ! ClearedFPRegs . empty ( ) ) ; if ( returnsFPReg ) assert ( STI -> hasFPRegs ( ) && <STR_LIT> ) ; for ( unsigned Reg : NonclearedFPRegs ) { if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Reg ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Reg ) . addReg ( <STR_LIT> ) . addImm ( Reg - <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } MachineInstrBuilder VLLDM = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; if ( STI -> fixCMSE_CVE_2021_35465 ( ) ) { auto Bundler = MIBundleBuilder ( MBB , VLLDM ) ; Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Define ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ) ; Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ) ; Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; if ( STI -> hasFPRegs ( ) ) Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Undef ) . add ( predOps ( <STR_LIT> ) ) ) ; else Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addImm ( InlineAsm :: Extra_HasSideEffects ) ) ; finalizeBundle ( MBB , Bundler . begin ( ) , Bundler . end ( ) ) ; } for ( const auto & Regs : ClearedFPRegs ) { unsigned Reg , SaveReg1 , SaveReg2 ; std :: tie ( Reg , SaveReg1


<s> unsigned Reg , SaveReg1 , SaveReg2 ; std :: tie ( Reg , SaveReg1 , SaveReg2 ) = Regs ; if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( SaveReg1 ) . addReg ( SaveReg2 ) . add ( predOps ( <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( SaveReg1 ) . add ( predOps ( <STR_LIT> ) ) ; } for ( unsigned Reg : NonclearedFPRegs ) { if ( <STR_LIT> . contains ( Reg ) ) { if ( STI -> isLittle ( ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else { unsigned SReg0 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SReg0 ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SReg0 + <NUM_LIT> ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> + <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } } else if ( <STR_LIT> . contains ( Reg ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( Reg - <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } } if ( passesFPReg ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SpareReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SpareReg ) . addReg ( SpareReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add


<s> if ( ! Op . isReg ( ) ) continue ; Register Reg = Op . getReg ( ) ; if ( ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg >= <STR_LIT>


<s> if ( ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) ) DefFP = true ; continue ; } if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { int R = Reg - <STR_LIT> ; ClearRegs . reset ( R * <NUM_LIT> , ( R + <NUM_LIT> ) * <NUM_LIT> ) ; } else if ( Reg >= <STR_LIT> && Reg


<s> BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( Dest . getReg ( ) , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredReg ) . add ( predOps ( <STR_LIT> ) ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; MIB = BuildMI ( StoreBB , DL , TII -> get ( StrexOp ) , TempReg ) . addReg ( NewReg ) . addReg ( AddrReg ) ; if ( StrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( TempReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB


<s> unsigned NumRegs = TableEntry -> NumRegs ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TableEntry -> RealOpc ) ) ; unsigned OpIdx = <NUM_LIT> ; bool DstIsDead = MI . getOperand ( OpIdx ) . isDead ( ) ; unsigned DstReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { unsigned SubRegIndex ; if ( RegSpc == EvenDblSpc ) { SubRegIndex = <STR_LIT> ; } else { assert ( RegSpc == OddDblSpc && <STR_LIT> ) ; SubRegIndex = <STR_LIT> ; } unsigned SubReg = TRI -> getSubReg ( DstReg , SubRegIndex ) ; unsigned DstRegPair = TRI -> getMatchingSuperReg ( SubReg , <STR_LIT> , & <STR_LIT> ) ; MIB . addReg ( DstRegPair , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } else { unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } if ( TableEntry -> isUpdating ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) { const MachineOperand & AM6Offset = MI . getOperand ( OpIdx ++ ) ; if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { assert ( AM6Offset . getReg ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; } else { MIB . add ( AM6Offset ) ; } } unsigned SrcOpIdx = <NUM_LIT> ; if ( TableEntry -> RealOpc != <STR_LIT> && TableEntry -> RealOpc != <STR_LIT> && TableEntry -> RealOpc != <STR_LIT> ) { if ( RegSpc == EvenDblSpc || RegSpc == OddDblSpc || RegSpc == SingleLowSpc || RegSpc == SingleHighQSpc || RegSpc == SingleHighTSpc ) SrcOpIdx = OpIdx ++ ; } MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( SrcOpIdx


<s> MachineInstr & MI = * MBBI ; MachineBasicBlock & MBB = * MI . getParent ( ) ; const NEONLdStTableEntry * TableEntry = LookupNEONLdSt ( MI . getOpcode ( ) ) ; assert ( TableEntry && ! TableEntry -> IsLoad && <STR_LIT> ) ; NEONRegSpacing RegSpc = ( NEONRegSpacing ) TableEntry -> RegSpacing ; unsigned NumRegs = TableEntry -> NumRegs ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TableEntry -> RealOpc ) ) ; unsigned OpIdx = <NUM_LIT> ; if ( TableEntry -> isUpdating ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) { const MachineOperand & AM6Offset = MI . getOperand ( OpIdx ++ ) ; if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { assert ( AM6Offset . getReg ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; } else { MIB . add ( AM6Offset ) ; } } bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; bool SrcIsUndef = MI . getOperand ( OpIdx ) . isUndef ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , getUndefRegState (


<s> if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { assert ( AM6Offset . getReg ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; } else { MIB . add ( AM6Offset ) ; } } bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; bool SrcIsUndef = MI . getOperand ( OpIdx ) . isUndef ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , getUndefRegState


<s> if ( STI -> hasV8_1MMainlineOps ( ) ) CMSERestoreFPRegsV81 ( MBB , MBBI , DL , AvailableRegs ) ; else CMSERestoreFPRegsV8 ( MBB , MBBI ,


<s> void <ISA_LIT>ExpandPseudo :: CMSERestoreFPRegs ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc & DL , SmallVectorImpl < unsigned > & AvailableRegs ) { if ( STI -> hasV8_1MMainlineOps ( ) ) CMSERestoreFPRegsV81 ( MBB , MBBI , DL


<s> if ( <STR_LIT> . contains ( Reg ) ) { if ( AvailableRegs . size ( ) >= <NUM_LIT> ) { unsigned SaveReg2 = AvailableRegs . pop_back_val ( ) ; unsigned SaveReg1 = AvailableRegs . pop_back_val ( ) ; ClearedFPRegs . emplace_back ( Reg , SaveReg1 , SaveReg2 ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( SaveReg1 , RegState :: Define ) . addReg ( SaveReg2 , RegState :: Define ) . addReg ( Reg ) . add ( predOps ( <STR_LIT> ) ) ; } else { NonclearedFPRegs . push_back ( Reg ) ; } } else if ( <STR_LIT> . contains ( Reg ) ) { if ( AvailableRegs . size ( ) >= <NUM_LIT> ) { unsigned SaveReg = AvailableRegs . pop_back_val ( ) ; ClearedFPRegs . emplace_back ( Reg , SaveReg , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SaveReg ) . addReg ( Reg ) . add ( predOps ( <STR_LIT> ) ) ; } else { NonclearedFPRegs . push_back ( Reg ) ; } } } } for ( unsigned Reg : NonclearedFPRegs ) { if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm (

Reg - <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ;


<s> if ( STI -> hasV8_1MMainlineOps ( ) ) CMSESaveClearFPRegsV81


<s> MachineInstrBuilder VPUSH = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; for ( int Reg = <STR_LIT> ; Reg <= <STR_LIT> ; ++ Reg ) VPUSH . addReg ( Reg ) ; ( void ) CMSEClearFPRegsV81 ( MBB , MBBI , ClearRegs ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> )


<s> bool DefFP = determineFPRegsToClear ( * MBBI , ClearRegs ) ; if ( ! DefFP && ClearRegs . count ( ) == ClearRegs . size ( ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( CMSE_FP_SAVE_SIZE >> <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else { MachineInstrBuilder VPUSH = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps


<s> auto DoneBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , LoadCmpBB ) ; MF -> insert ( ++ LoadCmpBB -> getIterator ( ) , StoreBB ) ; MF -> insert ( ++ StoreBB -> getIterator ( ) , DoneBB ) ; if ( UxtOp ) { MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( UxtOp ) , Desired . getReg ( ) ) . addReg ( Desired . getReg ( ) , RegState :: Kill ) ; if ( ! IsThumb ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; } LoadCmpBB -> addLiveIn ( Addr . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( Dest . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( Desired . getReg ( ) ) ; addPostLoopLiveIns ( LoadCmpBB , LiveRegs ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( LdrexOp ) , Dest . getReg ( ) ) ; MIB . addReg ( Addr . getReg ( ) ) ; if ( LdrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( Dest . getReg ( ) , getKillRegState ( Dest . isDead ( ) ) ) . add ( Desired ) . add ( predOps ( <STR_LIT> ) ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; StoreBB -> addLiveIn ( Addr .


<s> MIB . addReg ( Addr . getReg ( ) ) . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestLo , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredLo , getKillRegState ( Desired . isDead ( ) ) ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestHi , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredHi , getKillRegState ( Desired . isDead ( ) ) ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; StoreBB -> addLiveIn ( Addr . getReg ( ) ) ; StoreBB -> addLiveIn ( New . getReg ( ) ) ; addPostLoopLiveIns ( StoreBB , LiveRegs ) ; unsigned STREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( StoreBB , DL , TII -> get ( STREXD ) , StatusReg ) ; addExclusiveRegPair ( MIB , New , <NUM_LIT> , IsThumb , TRI ) ; MIB . add ( Addr ) . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( StatusReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( &


<s> MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned PC_ID = AFI -> createPICLabelUId ( ) ; MachineInstrBuilder PicADD = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( NotThumb ? <STR_LIT> : <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) . addImm ( PC_ID ) . addImm ( Pred ) . addReg ( PredReg ) ; ( void ) PicADD ; LO16 = LO16 . addImm (


<s> MachineInstrBuilder PicADD = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( NotThumb ? <STR_LIT> : <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) . addImm ( PC_ID ) . addImm (


<s> } const bool ShouldUseMOV16PIC = FlagSfiDisableCP && IsRelocPIC && ( MO . isCPI ( ) || MO . isJTI ( ) || MO . isGlobal ( ) ) ; if ( ShouldUseMOV16PIC ) { if ( isThumb2 ) llvm_unreachable ( <STR_LIT> ) ; LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( LO16Opc ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( HI16Opc ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , RegState :: Kill ) ; if ( MO . isImm ( ) ) { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; } else if ( MO . isGlobal ( ) ) { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; } else if ( MO . isCPI ( ) ) { int i = MO . getIndex ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addConstantPoolIndex ( i , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addConstantPoolIndex ( i , MO . getOffset ( ) , TF | <STR_LIT> ) ; } else if ( MO . isJTI ( ) ) { unsigned TF = MO . getTargetFlags


<s> TRI = TM . getRegisterInfo ( ) ; STI = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; IsRelocPIC = MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ; if ( Verify<ISA_LIT>Pseudo ) MF . verify ( this


<s> bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ; if ( Verify<ISA_LIT>Pseudo ) MF . verify ( this , <STR_LIT>


<s> AddDefaultPred ( MIB ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestLo , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredLo , getKillRegState ( Desired . isDead ( ) ) ) ) ; unsigned SBCrr = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( SBCrr ) ) . addReg ( StatusReg , RegState :: Define | RegState :: Dead ) . addReg ( DestHi , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredHi , getKillRegState ( Desired . isDead ( ) ) ) ; AddDefaultPred ( MIB ) ; MIB . addReg ( <STR_LIT> , RegState :: Kill ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; StoreBB -> addLiveIn ( Addr . getReg ( ) ) ; StoreBB -> addLiveIn ( New . getReg ( ) ) ; addPostLoopLiveIns ( StoreBB , LiveRegs ) ; unsigned STREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( StoreBB , DL , TII -> get ( STREXD ) , StatusReg ) ; addExclusiveRegPair ( MIB , New , <NUM_LIT> , IsThumb , TRI ) ; MIB . addOperand ( Addr ) ; AddDefaultPred ( MIB ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( StatusReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; addPostLoopLiveIns ( DoneBB , LiveRegs ) ; MBB . addSuccessor ( LoadCmpBB ) ; NextMBBI = MBB . end ( ) ; MI . eraseFromParent (


<s> unsigned DesiredHi = TRI -> getSubReg ( Desired . getReg ( ) , <STR_LIT> ) ; LivePhysRegs LiveRegs ( & TII -> getRegisterInfo ( ) ) ; LiveRegs . addLiveOuts ( MBB ) ; for ( auto I = std :: prev ( MBB . end ( ) ) ; I != MBBI ; -- I ) LiveRegs . stepBackward ( * I ) ; MachineFunction * MF = MBB . getParent ( ) ; auto LoadCmpBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto StoreBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto DoneBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , LoadCmpBB ) ; MF -> insert ( ++ LoadCmpBB -> getIterator ( ) , StoreBB ) ; MF -> insert ( ++ StoreBB -> getIterator ( ) , DoneBB ) ; LoadCmpBB -> addLiveIn ( Addr . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( Dest . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( Desired . getReg ( ) ) ; addPostLoopLiveIns ( LoadCmpBB , LiveRegs ) ; unsigned LDREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( LDREXD ) ) ; addExclusiveRegPair ( MIB , Dest , RegState :: Define , IsThumb , TRI ) ; MIB . addReg ( Addr . getReg ( ) ) ; AddDefaultPred ( MIB ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestLo , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredLo , getKillRegState ( Desired . isDead ( ) ) ) ) ; unsigned SBCrr = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( SBCrr ) ) . addReg ( StatusReg , RegState :: Define | RegState :: Dead ) . addReg ( DestHi , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredHi , getKillRegState ( Desired . isDead ( ) ) ) ; AddDefaultPred ( MIB ) ; MIB . addReg ( <STR_LIT> , RegState :: Kill ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor


<s> case MachineOperand :: MO_TargetIndex : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_BlockAddress : return true ; case MachineOperand :: MO_RegisterMask : case MachineOperand :: MO_RegisterLiveOut : return false ; case MachineOperand :: MO_Metadata : case MachineOperand :: MO_MCSymbol : return true ; case MachineOperand ::


<s> BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addDef ( <STR_LIT> , RegState :: Dead ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else { BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; } } MachineInstrBuilder MIB ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( LdrexOp ) , Dest . getReg ( ) ) ; MIB . addReg ( AddrReg ) ; if ( LdrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( Dest . getReg ( ) , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredReg ) . add ( predOps ( <STR_LIT> ) ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; MIB = BuildMI ( StoreBB , DL , TII -> get ( StrexOp ) , StatusReg ) . addReg ( NewReg ) . addReg ( AddrReg ) ; if ( StrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( StatusReg , getKillRegState ( StatusDead ) ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( &


<s> LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; unsigned STREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( StoreBB , DL , TII -> get ( STREXD ) , StatusReg ) ; addExclusiveRegPair ( MIB , New , <NUM_LIT> , IsThumb , TRI ) ; MIB . addReg ( AddrReg ) . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( StatusReg , getKillRegState ( StatusDead ) ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoadCmpBB ) ; NextMBBI = MBB . end ( ) ; MI . eraseFromParent ( ) ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; LivePhysRegs LiveRegs ; computeLiveIns ( LiveRegs , MRI , * DoneBB ) ; computeLiveIns ( LiveRegs , MRI , * StoreBB ) ; computeLiveIns ( LiveRegs , MRI , * LoadCmpBB ) ; StoreBB -> clearLiveIns (


<s> void <ISA_LIT>ExpandPseudo :: ExpandLaneOp ( MachineBasicBlock :: iterator & MBBI ) { MachineInstr & MI = * MBBI ; MachineBasicBlock & MBB = * MI . getParent ( ) ; const NEONLdStTableEntry * TableEntry = LookupNEONLdSt ( MI . getOpcode ( ) ) ; assert ( TableEntry && <STR_LIT> ) ; NEONRegSpacing RegSpc = TableEntry -> RegSpacing ; unsigned NumRegs = TableEntry -> NumRegs ; unsigned RegElts = TableEntry -> RegElts ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TableEntry -> RealOpc ) ) ; unsigned OpIdx = <NUM_LIT> ; unsigned Lane = MI . getOperand ( MI . getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) . getImm ( ) ; assert ( RegSpc != OddDblSpc && <STR_LIT> ) ; if ( RegSpc == EvenDblSpc && Lane >= RegElts ) { RegSpc = OddDblSpc ; Lane -= RegElts ; } assert ( Lane < RegElts && <STR_LIT> ) ; unsigned D0 = <NUM_LIT> , D1 = <NUM_LIT> , D2 = <NUM_LIT> , D3 = <NUM_LIT> ; unsigned DstReg = <NUM_LIT> ; bool DstIsDead =


<s> HI16Opc = <STR_LIT> ; } LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( LO16Opc ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( HI16Opc ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; if ( MO . isImm ( ) ) { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; } ( * LO16 ) . setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; ( * HI16 ) . setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; LO16 . addImm ( Pred ) . addReg ( PredReg ) ; HI16 . addImm ( Pred ) . addReg ( PredReg ) ; TransferImpOps ( MI , LO16 , HI16


<s> const TargetMachine & TM = MF . getTarget ( ) ; TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( TM . getInstrInfo ( ) ) ; TRI = TM . getRegisterInfo ( ) ; STI = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF


<s> bool <ISA_LIT>ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; TRI = TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; STI = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool Modified = false


<s> MIB . add ( VdSrc ) ; } bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , SingleSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 ) ; MachineOperand VmSrc ( MI . getOperand ( OpIdx ++ ) ) ; VmSrc . setIsRenamable ( false ) ; MIB . add ( VmSrc ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addReg ( SrcReg , RegState :: Implicit |


<s> case MachineOperand :: MO_MachineBasicBlock : return true ; case MachineOperand :: MO_FrameIndex : return false ; case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_TargetIndex : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_BlockAddress : return true ; case MachineOperand :: MO_RegisterMask : case MachineOperand :: MO_RegisterLiveOut : return false ; case MachineOperand :: MO_Metadata : case MachineOperand :: MO_MCSymbol : return true ; case MachineOperand :: MO_CFIIndex : return false ; case MachineOperand :: MO_IntrinsicID : case MachineOperand :: MO_Predicate : case MachineOperand :: MO_Placeholder


<s> return false ; case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_TargetIndex : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_BlockAddress : return true ; case MachineOperand :: MO_RegisterMask : case MachineOperand ::


<s> unsigned HI16Opc = <NUM_LIT> ; bool isThumb2 = ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; if ( isThumb2 ) { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } else { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } const bool ShouldUseMOV16PIC = ! STI -> useConstIslands ( ) && IsRelocPIC && ( MO . isCPI ( ) || MO . isJTI ( ) || MO . isGlobal ( ) ) ; if ( ShouldUseMOV16PIC ) { if ( isThumb2 ) llvm_unreachable ( <STR_LIT> ) ; LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( LO16Opc ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( HI16Opc ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , RegState :: Kill ) ; if ( MO . isImm ( ) ) { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; } else if ( MO . isGlobal ( ) ) { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; } else if ( MO . isCPI ( ) ) { int i = MO . getIndex ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addConstantPoolIndex ( i , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addConstantPoolIndex ( i , MO . getOffset ( ) , TF | <STR_LIT> ) ; } else if ( MO . isJTI ( ) ) { unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addJumpTableIndex ( MO . getIndex ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addJumpTableIndex ( MO . getIndex ( ) , TF | <STR_LIT> ) ; } else { assert ( <NUM_LIT>


<s> LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; } else if ( MO . isGlobal ( ) ) { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; } else if ( MO . isCPI ( ) ) { int i = MO . getIndex ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addConstantPoolIndex ( i , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addConstantPoolIndex ( i , MO . getOffset ( ) , TF | <STR_LIT> ) ; } else if ( MO . isJTI ( ) ) { unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addJumpTableIndex ( MO . getIndex ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addJumpTableIndex ( MO . getIndex ( ) , TF | <STR_LIT> ) ; } else { assert ( <NUM_LIT> && <STR_LIT> ) ; } if ( ShouldUseMOV16PIC ) { AddPICADD_MOVi16_PICID ( MI , MBB , MBBI , ! isThumb2 , PredReg , Pred , DstReg , DstIsDead , LO16 , HI16 ) ; } LO16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; HI16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; LO16 . addImm ( Pred ) . addReg ( PredReg ) ; HI16 . addImm ( Pred )


<s> HI16Opc = <STR_LIT> ; } LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( LO16Opc ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( HI16Opc ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , RegState :: Kill ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { const char * ES = MO . getSymbolName ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ; HI16 = HI16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ; break ; } default : { if ( MO . isGlobal ( ) ) { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; } else if ( MO . isCPI ( ) ) { int i = MO . getIndex ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addConstantPoolIndex ( i , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addConstantPoolIndex ( i , MO . getOffset ( ) , TF |


<s> AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; IsRelocPIC = MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ; if ( Verify<ISA_LIT>Pseudo ) MF . verify ( this , <STR_LIT> ) ; return Modified


<s> MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI != E ) { MachineInstr & MI = * MBBI ; MachineBasicBlock :: iterator NMBBI = llvm :: next ( MBBI ) ; unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned NewLdOpc = ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) { MachineInstr * NewMI = AddDefaultPred ( BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( NewLdOpc ) , DstReg ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ) ; NewMI -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , getDefRegState ( true ) ) . addReg ( DstReg ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; } MI . eraseFromParent ( ) ; Modified = true ; break ; } case <STR_LIT> : { unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) { const MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; MachineInstrBuilder LO16 , HI16 ; LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ,


<s> bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( *


<s> GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( TableEntry -> HasWriteBack ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> HasWriteBack ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; unsigned SrcOpIdx = <NUM_LIT> ; if ( RegSpc == EvenDblSpc || RegSpc == OddDblSpc ) SrcOpIdx = OpIdx ++ ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand (


<s> NEONRegSpacing RegSpc = TableEntry -> RegSpacing ; unsigned NumRegs = TableEntry -> NumRegs ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TableEntry -> RealOpc ) ) ; unsigned OpIdx = <NUM_LIT> ; bool DstIsDead = MI . getOperand ( OpIdx ) . isDead ( ) ; unsigned DstReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( TableEntry -> HasWriteBack ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> HasWriteBack ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; unsigned SrcOpIdx = <NUM_LIT> ; if ( RegSpc == EvenDblSpc || RegSpc == OddDblSpc ) SrcOpIdx = OpIdx ++ ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( SrcOpIdx != <NUM_LIT> ) { MachineOperand MO = MI . getOperand ( SrcOpIdx ) ; MO . setImplicit (


<s> void <ISA_LIT>ExpandPseudo :: ExpandVST ( MachineBasicBlock :: iterator & MBBI ) { MachineInstr & MI = * MBBI ; MachineBasicBlock & MBB = * MI . getParent ( ) ; const NEONLdStTableEntry * TableEntry = LookupNEONLdSt ( MI . getOpcode ( ) ) ; assert ( TableEntry && ! TableEntry -> IsLoad && <STR_LIT> ) ; NEONRegSpacing RegSpc = TableEntry -> RegSpacing ; unsigned NumRegs = TableEntry -> NumRegs ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TableEntry -> RealOpc ) ) ; unsigned OpIdx =


<s> } case <STR_LIT> : { unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) { const MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; MachineInstrBuilder LO16 , HI16 ; LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , getDefRegState ( true ) ) . addReg ( DstReg ) ; if ( MO . isImm ( ) ) { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; } AddDefaultPred ( LO16 ) ; AddDefaultPred ( HI16 ) ; } MI . eraseFromParent ( ) ; Modified = true ; } } MBBI = NMBBI ; } return Modified


<s> NewMI -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , getDefRegState ( true ) ) . addReg ( DstReg ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; } MI . eraseFromParent ( ) ; Modified = true ; break ; } case <STR_LIT> : { unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) { const MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; MachineInstrBuilder LO16 , HI16 ; LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , getDefRegState ( true ) ) . addReg ( DstReg ) ; if ( MO . isImm ( ) ) { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; } AddDefaultPred ( LO16 ) ; AddDefaultPred ( HI16 ) ; } MI . eraseFromParent ( ) ; Modified = true ; } } MBBI = NMBBI ; } return Modified


<s> bool <ISA_LIT>ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( TM . getInstrInfo ( ) ) ; TRI = TM . getRegisterInfo ( ) ; STI = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB (


<s> const MachineInstrBuilder & <ISA_LIT>FastISel :: AddOptionalDefs ( const MachineInstrBuilder & MIB ) { MachineInstr * MI = & * MIB ; if ( TII . isPredicable ( MI ) || is<ISA_LIT>NEONPred ( MI ) ) AddDefaultPred ( MIB ) ; bool CPSR = false ; if ( DefinesOptionalPredicate ( MI , & CPSR ) ) { if ( CPSR )


<s> const MachineInstrBuilder & <ISA_LIT>FastISel :: AddOptionalDefs ( const MachineInstrBuilder & MIB ) { MachineInstr * MI = & * MIB ; if ( TII . isPredicable ( MI ) || is<ISA_LIT>NEONPred ( MI ) ) AddDefaultPred ( MIB ) ; bool CPSR = false ; if ( DefinesOptionalPredicate ( MI , & CPSR ) ) { if ( CPSR ) AddDefaultT1CC ( MIB ) ; else AddDefaultCC ( MIB ) ; } return MIB


<s> for ( User :: const_op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { const Value * Op = * i ; if ( StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = TD . getStructLayout ( STy ) ; unsigned Idx = cast < ConstantInt > ( Op ) -> getZExtValue ( ) ; TmpOffset += SL -> getElementOffset ( Idx ) ; } else { uint64_t S = TD . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { TmpOffset += CI -> getSExtValue ( ) * S ; break ; } if ( isa < AddOperator > ( Op ) && ( ! isa < Instruction > ( Op ) || FuncInfo . MBBMap [ cast < Instruction > ( Op ) -> getParent ( ) ] == FuncInfo . MBB ) && isa < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ) { ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; TmpOffset += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } goto unsupported_gep


<s> CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : isICmp = false ; CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : needsExt = true ; case <STR_LIT> : if ( isThumb2 ) { if ( ! UseImm ) CmpOpc = <STR_LIT> ; else CmpOpc = isNegativeImm ? <STR_LIT> : <STR_LIT> ; } else { if ( ! UseImm ) CmpOpc = <STR_LIT> ; else CmpOpc = isNegativeImm ? <STR_LIT> : <STR_LIT> ; } break ; } unsigned SrcReg1 = getRegForValue ( Src1Value ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = <NUM_LIT> ; if ( ! UseImm ) { SrcReg2 = getRegForValue ( Src2Value ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } if ( needsExt ) { SrcReg1 = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg1 , <STR_LIT> , isZExt ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; if ( ! UseImm ) { SrcReg2 = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg2 , <STR_LIT> , isZExt ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } } if ( ! UseImm ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CmpOpc ) ) . addReg ( SrcReg1 ) . addReg ( SrcReg2 ) ) ; } else { MachineInstrBuilder MIB ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CmpOpc ) ) . addReg ( SrcReg1 ) ; if ( isICmp ) MIB . addImm ( Imm ) ; AddOptionalDefs ( MIB ) ; } if ( Ty -> isFloatTy ( ) || Ty -> isDoubleTy ( ) ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) ) ) ; return


<s> case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; } RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { needVMOV = true ; VT = <STR_LIT> ; Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) return false ; Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT , useAM3 ) ; if ( allocReg ) ResultReg = createResultReg ( RC ) ; assert ( ResultReg > <NUM_LIT> && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL


<s> bool IsThreadLocal = GVar && GVar -> isThreadLocal ( ) ; if ( ! Subtarget -> isTargetDarwin ( ) && IsThreadLocal ) return <NUM_LIT> ; if ( Subtarget -> useMovt ( ) && Subtarget -> isTargetDarwin ( ) == ( RelocM != Reloc :: Static ) ) { unsigned Opc ; switch ( RelocM ) { case Reloc :: PIC_ : Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case Reloc :: DynamicNoPIC : Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; default : Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; } AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addGlobalAddress ( GV ) ) ; } else { unsigned Align = TD . getPrefTypeAlignment ( GV -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( GV -> getType ( ) ) ; } if ( Subtarget -> isTargetELF ( ) && RelocM == Reloc :: PIC_ ) return <ISA_LIT>LowerPICELF ( GV , Align , VT ) ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , Id


<s> } break ; case <STR_LIT> : case <STR_LIT> : needsLowering = ( ( Addr . Offset & <NUM_LIT> ) != Addr . Offset ) ; break ; } if ( needsLowering && Addr . BaseType == Address :: FrameIndexBase ) { const TargetRegisterClass * RC = isThumb2 ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( Addr . Base . FI ) . addImm ( <NUM_LIT> ) ) ; Addr . Base .


<s> switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! useAM3 ) { needsLowering = ( ( Addr . Offset & <NUM_LIT> ) != Addr . Offset ) ; if ( needsLowering && isThumb2 ) needsLowering = ! ( Subtarget -> hasV6T2Ops ( ) && Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> ) ; } else { needsLowering = ( Addr . Offset > <NUM_LIT> || Addr . Offset < - <NUM_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : needsLowering = ( ( Addr . Offset & <NUM_LIT> ) != Addr . Offset ) ; break ; } if ( needsLowering && Addr . BaseType == Address :: FrameIndexBase ) { const TargetRegisterClass * RC = isThumb2 ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; unsigned Opc = isThumb2 ? <STR_LIT>


<s> const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool UseFastISel = false ; UseFastISel |= Subtarget -> isTargetIOS ( ) && ! Subtarget -> isThumb1Only ( ) ; UseFastISel |= Subtarget -> isTargetLinux ( ) && ! Subtarget -> isThumb ( ) ; UseFastISel |= Subtarget -> isTargetNaCl ( ) && ! Subtarget -> isThumb ( ) ; if ( UseFastISel


<s> bool UseFastISel = false ; UseFastISel |= Subtarget -> isTargetIOS ( ) && ! Subtarget -> isThumb1Only ( ) ; UseFastISel |= Subtarget -> isTargetLinux ( ) && ! Subtarget -> isThumb ( ) ; UseFastISel |= Subtarget -> isTargetNaCl ( ) && ! Subtarget -> isThumb ( ) ; if ( UseFastISel ) { TM . Options .


<s> unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL


<s> unsigned <ISA_LIT>FastISel :: FastEmitInst_extractsubreg ( MVT RetVT , unsigned Op0 , bool Op0IsKill , uint32_t Idx ) { unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( RetVT ) ) ; assert ( TargetRegisterInfo :: isVirtualRegister ( Op0


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addImm ( Imm ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ; } return


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY )

, ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ;


<s> const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) ,

ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ;


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addFPImm ( FPImm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ; } return ResultReg


<s> if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addImm ( Imm ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ; } return ResultReg


<s> if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) . addReg ( Op2 , Op2IsKill * RegState :: Kill ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) . addReg ( Op2 , Op2IsKill * RegState :: Kill ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY

) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ;


<s> const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) . addReg (

Op2 , Op2IsKill * RegState :: Kill ) ) ;


<s> UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UpdateValueMap ( I , ResultReg ) ; } else { assert ( RVLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; MVT CopyVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; if ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) CopyVT = <STR_LIT> ; const TargetRegisterClass * DstRC = TLI . getRegClassFor ( CopyVT ) ; unsigned ResultReg = createResultReg ( DstRC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg


<s> if ( ! LCREVT . isSimple ( ) ) return <NUM_LIT> ; GlobalValue * GV = new GlobalVariable ( Type :: getInt32Ty ( * Context )

, false , GlobalValue :: ExternalLinkage , <NUM_LIT> , Name ) ;


<s> NumBytes = CCInfo . getNextStackOffset ( ) ; unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( AdjStackDown ) ) . addImm ( NumBytes ) ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; unsigned Arg = ArgRegs [ VA . getValNo ( ) ] ; MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; assert ( ( ! ArgVT . isVector ( ) && ArgVT . getSizeInBits ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , false ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , true ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: BCvt : { unsigned BC = FastEmit_r ( ArgVT , VA . getLocVT ( ) , <STR_LIT> , Arg , false ) ; assert ( BC != <NUM_LIT> &&


<s> break ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; } unsigned Op1 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1 == <NUM_LIT> ) return false ; unsigned Op2 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2 == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT . SimpleTy ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addReg ( Op1


<s> } unsigned SrcReg1 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) ,

ResultReg ) . addReg ( SrcReg1 ) . addReg ( SrcReg2 ) ) ;


<s> } <STR_LIT> <ISA_LIT>Pred = getComparePred ( Predicate ) ; if ( <ISA_LIT>Pred == <STR_LIT> ) return false ; if ( ! <ISA_LIT>EmitCmp ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , CI -> isUnsigned ( ) ) ) return false ; unsigned BrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( BrOpc ) ) . addMBB ( TBB ) . addImm ( <ISA_LIT>Pred ) . addReg ( <STR_LIT> ) ; FastEmitBranch ( FBB , DL ) ; FuncInfo . MBB -> addSuccessor ( TBB ) ; return true ; } } else if ( TruncInst * TI = dyn_cast < TruncInst > ( BI -> getCondition ( ) ) ) { MVT SourceVT ; if ( TI -> hasOneUse ( ) && TI -> getParent ( ) == I -> getParent ( ) && ( isLoadTypeLegal ( TI -> getOperand ( <NUM_LIT> ) -> getType ( ) , SourceVT ) ) ) { unsigned TstOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned OpReg = getRegForValue ( TI -> getOperand ( <NUM_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TstOpc ) ) . addReg ( OpReg ) . addImm ( <NUM_LIT> ) ) ; unsigned CCMode = <STR_LIT> ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; CCMode = <STR_LIT> ; } unsigned BrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( BrOpc ) ) . addMBB ( TBB ) . addImm ( CCMode ) . addReg ( <STR_LIT> ) ; FastEmitBranch ( FBB , DL ) ; FuncInfo . MBB -> addSuccessor ( TBB ) ; return true ; } } else if ( const ConstantInt * CI = dyn_cast < ConstantInt


<s> unsigned DestReg = createResultReg ( RC ) ; Constant * Zero = ConstantInt :: get ( Type :: getInt32Ty ( * Context ) , <NUM_LIT> ) ; unsigned ZeroReg = TargetMaterializeConstant ( Zero ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( MovCCOpc ) , DestReg ) . addReg ( ZeroReg ) . addImm ( <NUM_LIT> ) . addImm ( <ISA_LIT>Pred ) . addReg ( <STR_LIT> ) ; UpdateValueMap ( I ,


<s> unsigned Result = createResultReg ( & <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , Result ) . addReg ( Op ) ) ; UpdateValueMap ( I , Result ) ; return true


<s> if ( ! Subtarget -> hasVFP2 ( ) ) return false ; Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! I -> getType ( ) -> isDoubleTy ( ) || ! V -> getType ( ) -> isFloatTy ( ) ) return false ; unsigned Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT> ) return false ; unsigned Result = createResultReg ( & <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , Result ) . addReg ( Op ) ) ; UpdateValueMap ( I , Result ) ; return


<s> unsigned Op = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op == <NUM_LIT> ) return false ; unsigned Opc ; Type * OpTy = I -> getOperand ( <NUM_LIT> ) -> getType ( ) ; if ( OpTy -> isFloatTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else if ( OpTy -> isDoubleTy ( ) ) Opc


<s> unsigned Opc ; Type * OpTy = I -> getOperand ( <NUM_LIT> ) -> getType ( ) ; if ( OpTy -> isFloatTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else if ( OpTy -> isDoubleTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addReg ( Op ) ) ; unsigned IntReg = <ISA_LIT>MoveToIntReg ( DstVT , ResultReg ) ; if ( IntReg == <NUM_LIT> )


<s> if ( ! Subtarget -> hasVFP2 ( ) ) return false ; Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! ( I -> getType ( ) -> isFloatTy ( ) && V -> getType ( ) -> isDoubleTy ( ) ) ) return false ; unsigned Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT> ) return false ; unsigned Result = createResultReg ( & <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , Result ) . addReg ( Op ) ) ; UpdateValueMap ( I ,


<s> bool <ISA_LIT>FastISel :: SelectFPTrunc ( const Instruction * I ) { if ( ! Subtarget -> hasVFP2 ( ) ) return false ; Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! ( I -> getType ( ) -> isFloatTy ( ) && V -> getType ( ) -> isDoubleTy ( ) ) ) return false ; unsigned Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT> ) return false ; unsigned Result = createResultReg ( & <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , Result ) . addReg ( Op ) ) ; UpdateValueMap ( I , Result ) ; return


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) ) . addReg ( AddrReg ) ) ; const IndirectBrInst * IB = cast < IndirectBrInst


<s> unsigned AddrReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( AddrReg == <NUM_LIT> ) return false ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) ) . addReg ( AddrReg ) ) ; const IndirectBrInst * IB = cast < IndirectBrInst > ( I ) ; for ( unsigned i = <NUM_LIT> , e = IB -> getNumSuccessors ( ) ; i != e ; ++ i ) FuncInfo . MBB -> addSuccessor ( FuncInfo . MBBMap [ IB -> getSuccessor ( i ) ] ) ; return


<s> unsigned SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { SrcReg = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg , <STR_LIT> , ! isSigned ) ; if ( SrcReg == <NUM_LIT> ) return false ; } unsigned FP = <ISA_LIT>MoveToFPReg ( <STR_LIT> , SrcReg ) ; if ( FP == <NUM_LIT> ) return false ; unsigned Opc ; if ( Ty -> isFloatTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else if ( Ty -> isDoubleTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else return


<s> CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; assert ( DestVT == <STR_LIT> && <STR_LIT> ) ; if ( Outs [ <NUM_LIT> ] . Flags . isZExt ( ) || Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) { SrcReg = <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ) ; if ( SrcReg ==


<s> unsigned MovCCOpc ; const TargetRegisterClass * RC ; if ( ! UseImm ) { RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; MovCCOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; } else { RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; if ( ! isNegativeImm ) MovCCOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; else MovCCOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; } unsigned ResultReg = createResultReg ( RC ) ; if ( ! UseImm ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( MovCCOpc ) , ResultReg ) . addReg ( Op2Reg ) . addReg ( Op1Reg ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; else BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( MovCCOpc ) , ResultReg ) . addReg ( Op1Reg ) . addImm ( Imm ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; UpdateValueMap ( I , ResultReg


<s> int Offset = Addr . Offset ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * FuncInfo . MF , FI , Offset ) , Flags , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; MIB . addFrameIndex ( FI ) ; if ( useAM3 ) { int Imm = ( Addr . Offset < <NUM_LIT> ) ? ( <NUM_LIT> | - Addr . Offset ) : Addr . Offset ; MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Imm ) ; } else { MIB . addImm ( Addr . Offset ) ; } MIB . addMemOperand ( MMO ) ; } else { MIB . addReg ( Addr . Base . Reg ) ; if (


<s> bool CPSR = false ; if ( DefinesOptionalPredicate ( MI , & CPSR ) ) MIB . add ( CPSR ? t1CondCodeOp


<s> if ( Imm < <NUM_LIT> && Imm != ( int ) <NUM_LIT> ) { isNegativeImm = true ; Imm = - Imm ; } UseImm = isThumb2 ? ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) : ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) ; } } else if ( const ConstantFP * ConstFP = dyn_cast < ConstantFP > ( Src2Value ) ) { if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) if ( ConstFP -> isZero ( ) && ! ConstFP -> isNegative ( ) ) UseImm = true ; } unsigned CmpOpc ; bool isICmp = true ; bool needsExt = false ; switch ( SrcVT . SimpleTy ) { default : return false ; case <STR_LIT> : isICmp = false ; if ( isEquality ) CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; else CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : isICmp = false ; if ( isEquality ) CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; else CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : needsExt = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( isThumb2 ) { if ( ! UseImm ) CmpOpc = <STR_LIT> ; else CmpOpc = isNegativeImm ? <STR_LIT> : <STR_LIT> ; } else { if ( ! UseImm ) CmpOpc = <STR_LIT> ; else CmpOpc = isNegativeImm ? <STR_LIT> : <STR_LIT> ; } break ; } unsigned SrcReg1 = getRegForValue ( Src1Value ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = <NUM_LIT> ; if ( ! UseImm ) { SrcReg2 = getRegForValue ( Src2Value ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } if ( needsExt ) { SrcReg1 = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg1 , <STR_LIT> , isZExt ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; if ( ! UseImm ) { SrcReg2 = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg2 , <STR_LIT> , isZExt ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } } const MCInstrDesc & II = TII . get ( CmpOpc ) ; SrcReg1 = constrainOperandRegClass ( II , SrcReg1 , <NUM_LIT> ) ; if ( ! UseImm ) { SrcReg2 = constrainOperandRegClass ( II , SrcReg2 , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( SrcReg1 ) . addReg ( SrcReg2 ) ) ; } else { MachineInstrBuilder MIB ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( SrcReg1 ) ; if ( isICmp ) MIB . addImm ( Imm ) ; AddOptionalDefs ( MIB


<s> SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; Args . reserve ( I -> getNumOperands ( ) ) ; ArgRegs . reserve ( I -> getNumOperands ( ) ) ; ArgVTs . reserve ( I -> getNumOperands ( ) ) ; ArgFlags . reserve ( I -> getNumOperands ( ) ) ; for ( Value * Op : I -> operands ( ) ) { unsigned Arg = getRegForValue ( Op ) ; if ( Arg == <NUM_LIT> ) return false ; Type * ArgTy = Op -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) ) return false ; <STR_LIT> Flags ; unsigned OriginalAlignment = DL . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( Op ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , false ) ) return false ; unsigned CalleeReg = <NUM_LIT> ; if ( Subtarget -> genLongCalls ( ) ) { CalleeReg = getLibcallReg ( TLI . getLibcallName ( Call ) ) ; if ( CalleeReg == <NUM_LIT> ) return false ; } unsigned CallOpc = <ISA_LIT>SelectCallOp ( Subtarget -> genLongCalls ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CallOpc ) ) ; if ( isThumb2 ) MIB . add ( predOps ( <STR_LIT> ) ) ; if ( Subtarget -> genLongCalls ( ) ) MIB . addReg ( CalleeReg ) ; else MIB . addExternalSymbol ( TLI . getLibcallName (


<s> unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , false ) ) return false ; unsigned CalleeReg = <NUM_LIT> ; if ( Subtarget -> genLongCalls ( ) ) { CalleeReg = getLibcallReg ( TLI . getLibcallName ( Call ) ) ; if ( CalleeReg == <NUM_LIT> ) return false ; } unsigned CallOpc = <ISA_LIT>SelectCallOp ( Subtarget -> genLongCalls ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CallOpc ) ) ; if ( isThumb2 ) MIB . add ( predOps ( <STR_LIT> ) ) ; if ( Subtarget -> genLongCalls ( ) ) MIB . addReg ( CalleeReg ) ; else MIB . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ; for ( unsigned R : RegArgs ) MIB . addReg ( R , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( * FuncInfo . MF , CC ) ) ; SmallVector < unsigned , <NUM_LIT> > UsedRegs ; if ( ! FinishCall ( RetVT , UsedRegs , I , CC , NumBytes , false ) ) return false ; static_cast < MachineInstr * > ( MIB ) -> setPhysRegsDeadExcept (


<s> RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; } RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { needVMOV = true ; VT = <STR_LIT> ; Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) return false ; Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT , useAM3 ) ; if ( allocReg ) ResultReg = createResultReg ( RC ) ; assert ( ResultReg > <NUM_LIT> &&


<s> LLVM_FALLTHROUGH ; } case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else { StrOpc = <STR_LIT> ; } break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else { StrOpc = <STR_LIT> ; useAM3 = true ; } break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; }


<s> explicit <ISA_LIT>FastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) : FastISel ( funcInfo , libInfo ) , Subtarget ( & static_cast < const <ISA_LIT>Subtarget & > ( funcInfo . MF -> getSubtarget ( ) ) ) , M ( const_cast < Module & > ( * funcInfo . Fn -> getParent ( ) ) ) , TM ( funcInfo . MF -> getTarget ( ) ) , TII (

* Subtarget -> getInstrInfo ( ) ) , TLI ( * Subtarget -> getTargetLowering ( ) ) {


<s> unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( CI -> getZExtValue ( ) ) ) ; return ImmReg ; } if ( VT == <STR_LIT> && Subtarget -> hasV6T2Ops ( ) && CI -> isNegative ( ) ) { unsigned Imm = ( unsigned ) ~ ( CI -> getSExtValue ( ) ) ; bool UseImm = isThumb2 ? ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) : ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) ; if ( UseImm ) { unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( Imm ) ) ; return ImmReg ; } } unsigned ResultReg = <NUM_LIT> ; if ( Subtarget -> useMovt ( * FuncInfo . MF ) ) ResultReg = fastEmit_i ( VT , VT , <STR_LIT> , CI -> getZExtValue ( ) ) ; if ( ResultReg ) return ResultReg ; if ( VT != <STR_LIT> ) return <NUM_LIT> ; unsigned Align = DL . getPrefTypeAlignment ( C -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = DL . getTypeAllocSize ( C -> getType ( ) ) ; } unsigned Idx = MCP . getConstantPoolIndex ( C , Align ) ; ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; if ( isThumb2 ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII .

get ( <STR_LIT> ) , ResultReg ) . addConstantPoolIndex ( Idx ) ) ;