<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetOptions & Options ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , <ISA_LIT>ProcClass ( None ) , stackAlignment ( <NUM_LIT> ) ,

CPUString ( CPU ) , TargetTriple ( TT ) , Options ( Options ) , TargetABI ( <ISA_LIT>_ABI_APCS ) {


<s> HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; HasCRC = false ; AllowsUnalignedMem = false ; Thumb2DSP =


<s> InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( ( TargetTriple . getTriple ( ) . find ( <STR_LIT> ) != std :: string :: npos ) || ( isTargetIOS ( ) && isMClass ( ) ) ) TargetABI = <ISA_LIT>_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; UseMovt = hasV6T2Ops ( ) && ArmUseMOVT ; if ( ! isTargetIOS ( ) ) { IsR9Reserved = ReserveR9 ; } else { IsR9Reserved = ReserveR9 | ! HasV6Ops ; SupportsTailCall = ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; switch ( Align ) { case DefaultAlign : AllowsUnalignedMem = ( ( hasV7Ops ( ) && ( isTargetLinux ( ) || isTargetNaCl ( ) ) ) || ( hasV6Ops ( ) && isTargetDarwin ( ) ) ) ; break ; case StrictAlign : AllowsUnalignedMem = false ; break ; case NoStrictAlign : AllowsUnalignedMem = true ; break ; } switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ? true


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , stackAlignment ( <NUM_LIT> ) , CPUString ( CPU ) , TargetTriple ( TT ) , TargetABI ( <ISA_LIT>_ABI_APCS ) { initializeEnvironment ( )


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , stackAlignment ( <NUM_LIT> ) , CPUString ( CPU ) , TargetTriple ( TT ) , TargetABI ( <ISA_LIT>_ABI_APCS ) { initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU ,


<s> CriticalPathRCs . clear ( ) ; CriticalPathRCs . push_back ( & <STR_LIT> ) ; return PostRAScheduler && OptLevel >=


<s> bool <ISA_LIT>Subtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo :: ANTIDEP_CRITICAL ; CriticalPathRCs . clear ( ) ; CriticalPathRCs . push_back ( & <STR_LIT> ) ; return PostRAScheduler && OptLevel >= CodeGenOpt


<s> bool isDecl = GV -> hasAvailableExternallyLinkage ( ) ; if ( GV -> isDeclaration ( ) && ! GV -> isMaterializable ( ) ) isDecl = true ; if ( ! isTargetDarwin ( ) ) { if ( GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( )


<s> if ( isTargetELF ( ) && TM . isPositionIndependent ( ) && ! TM . shouldAssumeDSOLocal ( * GV -> getParent


<s> bool <ISA_LIT>Subtarget :: useStride4VFPs ( const MachineFunction & MF ) const { return isTargetWatchABI ( ) || ( isSwift ( ) && ! MF . getFunction ( )


<s> return isTargetWatchABI ( ) || ( isSwift ( ) && ! MF . getFunction


<s> CPUString = ParseSubtargetFeatures ( FS , CPUString ) ; if ( CPUString == <STR_LIT> && ( FS . empty ( ) || FS == <STR_LIT> ) ) <ISA_LIT>ArchVersion = V4T ; unsigned Len = TT . length ( ) ; unsigned Idx = <NUM_LIT> ; if ( Len >= <NUM_LIT> && TT . substr ( <NUM_LIT> , <NUM_LIT> ) == <STR_LIT> ) Idx = <NUM_LIT> ; else if ( Len >= <NUM_LIT> && TT . substr ( <NUM_LIT> , <NUM_LIT> ) == <STR_LIT> ) { IsThumb = true ; if ( Len >= <NUM_LIT> && TT [ <NUM_LIT> ] == 'v' ) Idx = <NUM_LIT> ; } if ( Idx ) { unsigned SubVer = TT [ Idx ] ; if ( SubVer >= '7' && SubVer <= '9' ) { <ISA_LIT>ArchVersion = V7A ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 'm' ) <ISA_LIT>ArchVersion = V7M ; } else if ( SubVer == '6' ) { <ISA_LIT>ArchVersion = V6 ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == '2' ) <ISA_LIT>ArchVersion = V6T2 ; } else if ( SubVer == '5' ) { <ISA_LIT>ArchVersion = V5T ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == 'e' ) <ISA_LIT>ArchVersion = V5TE ; } else if ( SubVer == '4' ) { if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' ) <ISA_LIT>ArchVersion = V4T ; else <ISA_LIT>ArchVersion = V4 ; } } if ( <ISA_LIT>ArchVersion >= V6T2 ) ThumbMode = Thumb2 ; else if ( ThumbMode >= Thumb2 ) <ISA_LIT>ArchVersion = V6T2 ; if ( Len >= <NUM_LIT> ) { if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) TargetType = isDarwin ; } if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) TargetABI = <ISA_LIT>_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetDarwin ( ) ) IsR9Reserved = ReserveR9 | ( <ISA_LIT>ArchVersion < V6 ) ; if ( ! isThumb ( ) ||

hasThumb2 ( ) ) PostRAScheduler = true ;


<s> if ( RelocM == Reloc :: Static ) return false ; bool isDecl = GV -> isDeclarationForLinker ( ) ; if ( ! isTargetMachO ( ) ) { if ( GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ) return false ; return true ; } else { if ( RelocM == Reloc :: PIC_ ) { if ( ! isDecl && ! GV -> isWeakForLinker ( ) ) return false ; if ( ! GV -> hasHiddenVisibility ( ) ) return true ; if ( isDecl || GV -> hasCommonLinkage ( ) ) return true ; return false ; } else { if ( ! isDecl && ! GV -> isWeakForLinker


<s> if ( RelocM == Reloc :: Static ) return false ; bool isDecl = GV -> isDeclarationForLinker ( ) ; if ( ! isTargetMachO ( ) ) { if ( GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ) return false ; return true ; }


<s> bool <ISA_LIT>Subtarget :: hasSinCos ( ) const { return getTargetTriple ( ) . isiOS ( ) && ! getTargetTriple ( ) . isOSVersionLT (


<s> bool <ISA_LIT>Subtarget :: isAAPCS_ABI ( ) const { assert ( TM . TargetABI != <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_UNKNOWN ) ; return TM . TargetABI ==


<s> const CallLowering * <ISA_LIT>Subtarget :: getCallLowering ( )


<s> const RegisterBankInfo * <ISA_LIT>Subtarget :: getRegBankInfo ( ) const { assert ( GISel && <STR_LIT> ) ; return GISel -> getRegBankInfo (


<s> void <ISA_LIT>Subtarget :: initializeEnvironment ( ) { UseSjLjEH = isTargetDarwin ( ) &&


<s> assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; if ( genExecuteOnly ( ) ) assert ( hasV8MBaselineOps ( ) && ! NoMovt && <STR_LIT> ) ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = <NUM_LIT> ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue


<s> HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; No<ISA_LIT> = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon =


<s> HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; HasCRC = false ; HasZeroCycleZeroing = false ; AllowsUnalignedMem = false ; Thumb2DSP =


<s> void <ISA_LIT>Subtarget :: initSubtargetFeatures ( StringRef CPU , StringRef FS ) { if ( CPUString . empty ( ) ) { if ( isTargetDarwin ( ) && TargetTriple . getArchName ( ) . endswith ( <STR_LIT> ) ) CPUString = <STR_LIT> ; else CPUString = <STR_LIT> ; } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple . getTriple ( ) , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) ) stackAlignment = <NUM_LIT> ; UseMovt = hasV6T2Ops ( ) && ArmUseMOVT ; if ( isTargetMachO ( ) ) { IsR9Reserved = ReserveR9 || ! HasV6Ops ; SupportsTailCall = ! isTargetIOS ( ) || ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } else { IsR9Reserved = ReserveR9 ; SupportsTailCall = ! isThumb1Only ( ) ; } if ( Align == DefaultAlign ) { AllowsUnalignedMem = ( hasV7Ops ( ) && ( isTargetLinux ( ) || isTargetNaCl ( ) || isTargetNetBSD ( )

) ) || ( hasV6Ops ( ) && ( isTargetMachO ( ) || isTargetNetBSD ( ) ) ) ;


<s> bool <ISA_LIT>Subtarget :: useMovt ( const


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetOptions & Options ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , <ISA_LIT>ProcClass ( None ) , stackAlignment ( <NUM_LIT> ) , CPUString ( CPU ) , TargetTriple ( TT ) , Options ( Options ) , TargetABI ( <ISA_LIT>_ABI_UNKNOWN ) { initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU


<s> HasV5TEOps = false ; HasV6Ops = false ; HasV6MOps = false ; HasV6T2Ops = false ; HasV7Ops = false ; HasV8Ops = false ; HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; MinSize = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false


<s> void <ISA_LIT>Subtarget :: resetSubtargetFeatures ( StringRef CPU , StringRef FS ) { if ( CPUString . empty ( ) ) { if ( isTargetIOS ( ) && TargetTriple . getArchName ( ) . endswith ( <STR_LIT> ) ) CPUString = <STR_LIT> ; else CPUString = <STR_LIT> ; } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple . getTriple ( ) , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + <STR_LIT> + FS . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( TargetABI == <ISA_LIT>_ABI_UNKNOWN ) { switch ( TargetTriple . getEnvironment ( ) ) { case Triple :: Android : case Triple :: EABI : case Triple :: EABIHF : case Triple :: GNUEABI : case Triple :: GNUEABIHF : TargetABI = <ISA_LIT>_ABI_AAPCS ; break ; default : if ( ( isTargetIOS ( ) && isMClass ( ) ) || ( TargetTriple . isOSBinFormatMachO ( ) && TargetTriple . getOS ( ) == Triple :: UnknownOS ) ) TargetABI = <ISA_LIT>_ABI_AAPCS ; else TargetABI = <ISA_LIT>_ABI_APCS ; break ; } } if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) ) stackAlignment = <NUM_LIT> ; UseMovt = hasV6T2Ops ( ) && ArmUseMOVT ; if ( isTargetMachO ( ) ) { IsR9Reserved = ReserveR9 | ! HasV6Ops ; SupportsTailCall = ! isTargetIOS ( ) || ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } else { IsR9Reserved = ReserveR9 ; SupportsTailCall = ! isThumb1Only ( ) ; } if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; switch ( Align ) { case DefaultAlign : AllowsUnalignedMem = ( hasV7Ops ( ) && ( isTargetLinux ( ) || isTargetNaCl ( ) || isTargetNetBSD ( ) ) ) || ( hasV6Ops ( ) && ( isTargetMachO ( ) || isTargetNetBSD ( ) ) ) ; break ; case StrictAlign : AllowsUnalignedMem = false ; break ; case NoStrictAlign : AllowsUnalignedMem = true ; break ; } switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ? true : false ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } uint64_t Bits = getFeatureBits (


<s> return TM . getRelocationModel ( ) == Reloc ::


<s> if ( CPUString . empty ( ) ) { CPUString = <STR_LIT> ; if ( isTargetDarwin ( ) ) { StringRef ArchName = TargetTriple . getArchName ( ) ; unsigned ArchKind = <STR_LIT> ( ArchName ) ; if ( ArchKind == <STR_LIT> ) CPUString = <STR_LIT> ; else if ( ArchKind == <STR_LIT> ) CPUString = <STR_LIT> ; } } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; if ( genExecuteOnly ( ) ) assert ( hasV8MBaselineOps ( ) && ! NoMovt && <STR_LIT> ) ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = <NUM_LIT> ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT


<s> unsigned getMaxInlineSizeThreshold ( ) const { return isThumb ( ) ? <NUM_LIT>


<s> if ( Len >= <NUM_LIT> && TT . substr ( <NUM_LIT> , <NUM_LIT> ) == <STR_LIT> ) Idx = <NUM_LIT> ; else if ( Len >= <NUM_LIT> && TT . substr ( <NUM_LIT> , <NUM_LIT> ) == <STR_LIT> ) { IsThumb = true ; if ( Len >= <NUM_LIT> && TT [ <NUM_LIT> ] == 'v' ) Idx = <NUM_LIT> ; } if ( Idx ) { unsigned SubVer = TT [ Idx ] ; if ( SubVer >= '7' && SubVer <= '9' ) { <ISA_LIT>ArchVersion = V7A ; <ISA_LIT>ArchFeature = <STR_LIT> ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 'm' ) { <ISA_LIT>ArchVersion = V7M ; <ISA_LIT>ArchFeature = <STR_LIT> ; } } else if ( SubVer == '6' ) { <ISA_LIT>ArchVersion = V6 ; <ISA_LIT>ArchFeature = <STR_LIT> ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == '2' ) { <ISA_LIT>ArchVersion = V6T2 ; <ISA_LIT>ArchFeature = <STR_LIT> ; } } else if ( SubVer == '5' ) { <ISA_LIT>ArchVersion = V5T ; <ISA_LIT>ArchFeature = <STR_LIT> ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == 'e' ) { <ISA_LIT>ArchVersion = V5TE ; <ISA_LIT>ArchFeature =


<s> } else if ( SubVer == '6' ) { <ISA_LIT>ArchVersion = V6 ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == '2' ) <ISA_LIT>ArchVersion = V6T2 ; } else if ( SubVer == '5' ) { <ISA_LIT>ArchVersion = V5T ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == 'e' ) <ISA_LIT>ArchVersion = V5TE ; } if ( <ISA_LIT>ArchVersion >= V6T2 ) ThumbMode = Thumb2 ; } } if ( <ISA_LIT>ArchVersion < V6T2 && ThumbMode >= Thumb2 ) <ISA_LIT>ArchVersion = V6T2 ; if ( Len >= <NUM_LIT> ) { if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) TargetType = isDarwin ; } if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) TargetABI = <ISA_LIT>_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetDarwin ( ) ) IsR9Reserved = ReserveR9 | ( <ISA_LIT>ArchVersion <


<s> if ( GV -> hasHiddenVisibility ( ) && ( ! isDecl && !

GV -> hasCommonLinkage ( ) ) ) return false ;


<s> bool isDecl = GV -> isDeclaration ( ) || GV -> hasAvailableExternallyLinkage ( ) ; if ( GV -> hasHiddenVisibility ( ) && ( ! isDecl && ! GV -> hasCommonLinkage ( ) ) ) return false ; return ! isStatic && ( isDecl || GV


<s> return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . getEnvironment ( ) == Triple ::

GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: Android ) && ! isTargetDarwin ( ) ;


<s> return TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( )


<s> return TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF ||

TargetTriple . getEnvironment ( ) == Triple :: EABIHF ;


<s> Ret += DataLayout :: getManglingComponent ( ST . getTargetTriple ( ) ) ; Ret += <STR_LIT> ; if ( ! ST . isAPCS_ABI ( ) ) Ret += <STR_LIT> ; if ( ST . isAPCS_ABI ( ) ) Ret += <STR_LIT> ; if ( ST . isAPCS_ABI ( ) ) Ret += <STR_LIT> ; else Ret +=


<s> if ( CPUString . empty ( ) ) CPUString = <STR_LIT> ; std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TT , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + <STR_LIT> + FS ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; if ( ! HasV6T2Ops && hasThumb2 ( ) ) HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( ( TT . find ( <STR_LIT> ) != std :: string :: npos ) || ( isTargetIOS ( ) && isMClass ( ) ) ) TargetABI = <ISA_LIT>_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( ! isTargetIOS ( ) ) UseMovt = hasV6T2Ops ( ) ; else { IsR9Reserved = ReserveR9 | !


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>BaseTargetMachine & TM , bool IsLittle , bool MinSize ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , UseMulOps ( UseFusedMulOps ) , CPUString ( CPU ) , OptMinSize ( MinSize ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo

( * this ) : ! isThumb ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new <ISA_LIT>InstrInfo ( * this ) : ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) {


<s> bool <ISA_LIT>Subtarget :: enablePostRAMachineScheduler ( ) const { if ( ! enableMachineScheduler ( ) ) return


<s> bool <ISA_LIT>Subtarget :: enableSubRegLiveness ( ) const { return EnableSubRegLiveness


<s> } SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) && ! hasMinSize ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) )


<s> HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; IsMClass = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved =


<s> HasVFPv4 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseInlineJumpTables = ! NoInlineJumpTables ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; IsMClass = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS =


<s> if ( ! HasV6T2Ops && hasThumb2 ( ) ) HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( ( TargetTriple . getTriple ( ) . find ( <STR_LIT> ) != std :: string :: npos ) || ( isTargetIOS ( ) && isMClass ( ) ) ) TargetABI = <ISA_LIT>_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( ! isTargetIOS ( ) ) UseMovt = hasV6T2Ops ( ) ; else { IsR9Reserved = ReserveR9 | ! HasV6Ops ; UseMovt = DarwinUseMOVT && hasV6T2Ops ( ) ; SupportsTailCall = ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } if ( isTargetNaCl ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) && ! useConstPool ( ) ) UseMovt = true ; if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; switch ( Align ) { case DefaultAlign : AllowsUnalignedMem = ( ( hasV7Ops ( ) && ( isTargetLinux ( ) || isTargetNaCl ( ) ) )

|| ( hasV6Ops ( ) && isTargetDarwin ( ) ) ) ;


<s> return getSchedModel ( ) . hasInstrSchedModel


<s> bool <ISA_LIT>Subtarget :: enableMachinePipeliner ( ) const { return getSchedModel ( ) . hasInstrSchedModel ( )


<s> if ( EnableSubRegLiveness . getNumOccurrences ( ) ) return EnableSubRegLiveness ; return hasMVEIntegerOps (


<s> if ( EnableSubRegLiveness . getNumOccurrences ( ) ) return EnableSubRegLiveness ; return hasMVEIntegerOps


<s> NoMovt = false ; assert ( hasV8MBaselineOps ( ) && <STR_LIT> ) ; } SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; SupportsTailCall = ! isThumb1Only ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = false ; break ; case RestrictedIT : RestrictIT = true ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) HasNEONForFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; if ( MVEVectorCostFactor == <NUM_LIT> ) MVEVectorCostFactor = <NUM_LIT> ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9 : LdStMultipleTiming = DoubleIssueCheckUnalignedAccess ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case CortexA12 : break ; case CortexA15 : MaxInterleaveFactor = <NUM_LIT> ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; PartialUpdateClearance = <NUM_LIT> ; break ; case CortexA17 : case CortexA32 : case CortexA35 : case CortexA53 : case CortexA55 : case CortexA57 : case CortexA72 : case CortexA73 : case CortexA75 : case CortexA76 : case CortexA77 : case CortexA78 : case CortexA78C : case CortexA710 : case CortexR4 : case CortexR4F : case CortexR5 : case CortexR7 : case CortexM3 : case CortexM7 : case CortexR52 : case CortexX1 : case CortexX1C : break ; case Exynos : LdStMultipleTiming = SingleIssuePlusExtras ; MaxInterleaveFactor = <NUM_LIT> ; if ( ! isThumb ( ) ) PrefLoopLogAlignment = <NUM_LIT> ; break ; case Kryo : break ; case Krait : PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case NeoverseN1 : case NeoverseN2 : case NeoverseV1 : break ; case Swift : MaxInterleaveFactor = <NUM_LIT>


<s> else if ( AK == <STR_LIT> :: <ISA_LIT>V7K ) CPUString = <STR_LIT> ; } } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = std :: string ( FS ) ; } ParseSubtargetFeatures ( CPUString , CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; if ( genExecuteOnly ( ) ) { NoMovt = false ; assert ( hasV8MBaselineOps ( ) && <STR_LIT> ) ; } SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; SupportsTailCall = ! isThumb1Only ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = false ; break ; case RestrictedIT : RestrictIT = true ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) HasNEONForFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; if ( MVEVectorCostFactor == <NUM_LIT> ) MVEVectorCostFactor = <NUM_LIT> ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9


<s> bool <ISA_LIT>Subtarget :: useDFAforSMS ( ) const { return false


<s> if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; if ( MVEVectorCostFactor == <NUM_LIT> ) MVEVectorCostFactor = <NUM_LIT> ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9 : LdStMultipleTiming = DoubleIssueCheckUnalignedAccess ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case CortexA12 : break ; case CortexA15 : MaxInterleaveFactor = <NUM_LIT> ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; PartialUpdateClearance = <NUM_LIT> ; break ; case CortexA17


<s> bool hasVFP2Base ( ) const { return hasVFPv2SP (


<s> bool hasVFP3Base ( ) const { return hasVFPv3D16SP (


<s> bool isTargetDriverKit ( ) const { return TargetTriple . isDriverKit


<s> bool <ISA_LIT>Subtarget :: GVIsIndirectSymbol ( GlobalValue * GV , Reloc :: Model RelocM ) const { if ( RelocM == Reloc :: Static ) return false ; bool isDecl = GV -> isDeclaration ( ) && ! GV -> isMaterializable ( ) ; if ( ! isTargetDarwin ( ) ) { if ( GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ) return false ; return true ; }


<s> void <ISA_LIT>Subtarget :: initSubtargetFeatures ( StringRef CPU , StringRef FS ) { if ( CPUString . empty ( ) ) { if ( isTargetDarwin ( ) && TargetTriple . getArchName ( ) . endswith ( <STR_LIT> ) ) CPUString = <STR_LIT> ; else CPUString = <STR_LIT> ; } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; SchedModel = getSchedModelForCPU ( CPUString


<s> return isSwift ( ) && ! MF . getFunction ( ) -> optForMinSize (


<s> if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; SupportsTailCall = ! isThumb1Only ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) && ! hasMinSize ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; if ( MVEVectorCostFactor == <NUM_LIT> ) MVEVectorCostFactor = <NUM_LIT> ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9 : LdStMultipleTiming = DoubleIssueCheckUnalignedAccess ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case CortexA12 : break ; case CortexA15 : MaxInterleaveFactor = <NUM_LIT> ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; PartialUpdateClearance = <NUM_LIT> ; break ; case CortexA17 : case CortexA32 : case CortexA35 : case CortexA53 : case CortexA55 : case CortexA57 : case CortexA72 : case CortexA73 : case CortexA75 : case CortexA76 : case CortexA77 : case CortexA78 : case CortexA78C : case CortexR4 : case CortexR4F : case CortexR5 : case CortexR7 : case CortexM3 : case CortexM7 : case CortexR52 : case CortexX1 : break ; case Exynos : LdStMultipleTiming = SingleIssuePlusExtras ; MaxInterleaveFactor = <NUM_LIT> ; if ( ! isThumb ( ) ) PrefLoopLogAlignment = <NUM_LIT> ; break ; case Kryo : break ; case Krait : PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case NeoverseN1 : case NeoverseN2 : case NeoverseV1 : break ; case Swift : MaxInterleaveFactor = <NUM_LIT> ; LdStMultipleTiming = SingleIssuePlusExtras ; PreISelOperandLatencyAdjustment =


<s> const RegisterBankInfo * getRegBankInfo


<s> const RegisterBankInfo * getRegBankInfo ( ) const override { return RegBankInfo . get


<s> if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; if ( genExecuteOnly ( ) ) assert ( hasV8MBaselineOps ( ) && ! NoMovt && <STR_LIT> ) ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = <NUM_LIT> ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ; break ; case RestrictedIT


<s> bool <ISA_LIT>Subtarget :: enableAtomicExpand ( ) const { return hasAnyDataBarrier ( ) && ( ! isThumb (


<s> return hasAnyDataBarrier ( ) && ( ! isThumb (


<s> bool <ISA_LIT>Subtarget :: GVIsIndirectSymbol ( const GlobalValue * GV , Reloc :: Model RelocM ) const { if ( ! shouldAssumeDSOLocal ( RelocM , TargetTriple , * GV -> getParent ( ) , GV ) ) return true ; if ( isTargetDarwin ( ) && RelocM == Reloc :: PIC_ && ( GV -> isDeclarationForLinker ( ) || GV -> hasCommonLinkage ( ) ) ) return true ; return


<s> HasV5TEOps = false ; HasV6Ops = false ; HasV6MOps = false ; HasV6KOps = false ; HasV6T2Ops = false ; HasV7Ops = false ; HasV8Ops = false ; HasV8_1aOps = false ; HasV8_2aOps = false ; HasV8MBaselineOps = false ; HasV8MMainlineOps = false ; HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; UseSoftFloat = false ; HasThumb2 = false ; No<ISA_LIT> = false ; ReserveR9 = false ; NoMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasFullFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; Has8MSecExt = false ; HasCrypto = false ; HasCRC = false ; HasZeroCycleZeroing = false ; StrictAlign = false ; HasDSP = false ; UseNaClTrap = false ; GenLongCalls =


<s> bool <ISA_LIT>Subtarget :: useMovt ( const MachineFunction


<s> bool useConstPool ( ) const { return !


<s> HasThumb2 = false ; No<ISA_LIT> = false ; ReserveR9 = false ; NoMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool IsLittle , const TargetOptions & Options ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , <ISA_LIT>ProcClass ( None ) , stackAlignment ( <NUM_LIT> ) , CPUString ( CPU )

, IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( Options ) , TargetABI ( <ISA_LIT>_ABI_UNKNOWN ) {


<s> No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; HasCRC = false ; HasZeroCycleZeroing =


<s> IsThumb = true ; if ( Len >= <NUM_LIT> && TT [ <NUM_LIT> ] == 'v' ) Idx = <NUM_LIT> ; } if ( Idx ) { unsigned SubVer = TT [ Idx ] ; if ( SubVer > '4' && SubVer <= '9' ) { if ( SubVer >= '6' ) <ISA_LIT>ArchVersion = V6 ; else if ( SubVer == '5' ) { <ISA_LIT>ArchVersion = V5T ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == 'e' ) <ISA_LIT>ArchVersion = V5TE ; } } } if ( Len >= <NUM_LIT> ) { if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) TargetType = isDarwin ; } else if ( TT . empty ( ) ) { TargetType =


<s> std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple . getTriple ( ) , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + <STR_LIT> + FS . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; if ( ! HasV6T2Ops && hasThumb2 ( ) ) HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6MOps = HasV6T2Ops = true ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( ( TargetTriple . getTriple ( ) . find ( <STR_LIT> ) != std :: string :: npos ) || ( isTargetIOS ( ) && isMClass ( ) ) ) TargetABI = <ISA_LIT>_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; UseMovt = hasV6T2Ops ( ) && ArmUseMOVT ; if ( ! isTargetIOS ( ) ) { IsR9Reserved = ReserveR9


<s> HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; UseSoftFloat = false ; HasThumb2 = false ; No<ISA_LIT> = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; HasCRC = false ; HasZeroCycleZeroing = false ; AllowsUnalignedMem = false ; Thumb2DSP =


<s> bool <ISA_LIT>Subtarget :: enablePostRAScheduler ( )


<s> HasV5TEOps = false ; HasV6Ops = false ; HasV6MOps = false ; HasV6KOps = false ; HasV6T2Ops = false ; HasV7Ops = false ; HasV8Ops = false ; HasV8_1aOps = false ; HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; UseSoftFloat = false ; HasThumb2 = false ; No<ISA_LIT> = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; HasCRC = false ; HasZeroCycleZeroing = false ; AllowsUnalignedMem =


<s> HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; UseSoftFloat = false ; HasThumb2 = false ; No<ISA_LIT> = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack =


<s> if ( isTargetNaCl ( ) ) stackAlignment = <NUM_LIT> ; UseMovt = hasV6T2Ops ( ) && ArmUseMOVT ; if ( isTargetMachO ( ) ) { IsR9Reserved = ReserveR9 || ! HasV6Ops ; SupportsTailCall = ! isTargetIOS ( ) || ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } else { IsR9Reserved = ReserveR9 ; SupportsTailCall = ! isThumb1Only ( ) ; } if ( Align == DefaultAlign ) { AllowsUnalignedMem = ( hasV7Ops ( ) && ( isTargetLinux ( ) || isTargetNaCl ( ) || isTargetNetBSD ( ) ) ) || ( hasV6Ops ( ) && ( isTargetMachO ( ) || isTargetNetBSD ( ) ) ) ; } else { AllowsUnalignedMem = ! ( Align == StrictAlign ) ; } if ( isV6M ( ) ) AllowsUnalignedMem = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( )

) ) UseNEONForSinglePrecisionFP = true ;


<s> bool <ISA_LIT>Subtarget :: useStride4VFPs ( const MachineFunction & MF )


<s> return isTargetWatchABI ( ) || ( isSwift ( ) && ! MF . getFunction ( )


<s> ParseSubtargetFeatures ( CPUString , CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; if ( genExecuteOnly ( ) ) { NoMovt = false ; assert ( hasV8MBaselineOps ( ) && <STR_LIT> ) ; } SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; SupportsTailCall = ! isThumb1Only ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) && ! hasMinSize ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; if ( MVEVectorCostFactor == <NUM_LIT> ) MVEVectorCostFactor = <NUM_LIT> ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9 : LdStMultipleTiming = DoubleIssueCheckUnalignedAccess ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case CortexA12 : break ; case CortexA15 : MaxInterleaveFactor = <NUM_LIT> ; PreISelOperandLatencyAdjustment =


<s> if ( isTargetDarwin ( ) && TargetTriple . getArchName ( ) . endswith ( <STR_LIT> ) ) CPUString = <STR_LIT> ; else CPUString = <STR_LIT> ; } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple . getTriple ( ) , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) ) stackAlignment = <NUM_LIT> ; UseMovt = hasV6T2Ops ( ) && ArmUseMOVT ; if ( isTargetMachO ( ) ) { IsR9Reserved = ReserveR9 || ! HasV6Ops ; SupportsTailCall = ! isTargetIOS ( ) || ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } else { IsR9Reserved = ReserveR9 ; SupportsTailCall = ! isThumb1Only ( ) ; } if ( Align == DefaultAlign ) { AllowsUnalignedMem = ( hasV7Ops ( ) && ( isTargetLinux ( ) || isTargetNaCl ( ) || isTargetNetBSD ( ) ) ) || ( hasV6Ops ( ) && ( isTargetMachO ( ) || isTargetNetBSD ( ) ) ) ; } else { AllowsUnalignedMem = ! ( Align == StrictAlign ) ; } if ( isV6M ( ) ) AllowsUnalignedMem = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } uint64_t Bits = getFeatureBits (


<s> if ( isTargetDarwin ( ) && TM . isPositionIndependent ( ) && ( GV -> isDeclarationForLinker ( ) || GV -> hasCommonLinkage ( ) ) ) return true ; return false


<s> bool <ISA_LIT>Subtarget :: isGVIndirectSymbol ( const GlobalValue * GV ) const { if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( )


<s> } } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; if ( genExecuteOnly ( ) ) { NoMovt = false ; assert ( hasV8MBaselineOps ( ) && <STR_LIT> ) ; } SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = <NUM_LIT> ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9 : LdStMultipleTiming = DoubleIssueCheckUnalignedAccess ; PreISelOperandLatencyAdjustment = <NUM_LIT>


<s> void <ISA_LIT>Subtarget :: initializeEnvironment ( ) { HasV4TOps = false ; HasV5TOps = false ; HasV5TEOps = false ; HasV6Ops = false ; HasV6MOps = false ; HasV6KOps = false ; HasV6T2Ops = false ; HasV7Ops = false ; HasV8Ops = false ; HasV8_1aOps = false ; HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; UseSoftFloat = false ; HasThumb2 = false ; No<ISA_LIT> = false ; ReserveR9 = false ; NoMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false


<s> UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; UseSoftFloat = false ; HasThumb2 = false ; No<ISA_LIT> = false ; ReserveR9 = false ; NoMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false


<s> HasV8Ops = false ; HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; AllowsUnalignedMem = false ; Thumb2DSP = false ; UseNaClTrap =


<s> IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto =


<s> UseInlineJumpTables = ! NoInlineJumpTables ; UseConstIslands = true ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; HasCRC = false ; AllowsUnalignedMem =


<s> if ( CPUString . empty ( ) ) { if ( isTargetIOS ( ) && TargetTriple . getArchName ( ) . endswith ( <STR_LIT> ) ) CPUString = <STR_LIT> ; else CPUString = <STR_LIT> ; } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple . getTriple ( ) , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + <STR_LIT> + FS . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; if ( ! HasV6T2Ops && hasThumb2 ( ) ) HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6MOps = HasV6T2Ops = true ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( ( TargetTriple . getTriple ( ) . find ( <STR_LIT> ) != std :: string :: npos ) || ( isTargetIOS ( ) && isMClass ( ) ) ) TargetABI = <ISA_LIT>_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) ) stackAlignment = <NUM_LIT> ; UseMovt = hasV6T2Ops ( ) && ArmUseMOVT ; if ( ! isTargetIOS ( ) ) { IsR9Reserved =


<s> if ( CPUString . empty ( ) ) CPUString = <STR_LIT> ; std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TT ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + <STR_LIT> + FS ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; if ( ! HasV6T2Ops && hasThumb2 ( ) ) HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; computeIssueWidth ( ) ; if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) TargetABI = <ISA_LIT>_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( ! isTargetDarwin ( ) ) UseMovt = hasV6T2Ops ( ) ; else { IsR9Reserved = ReserveR9 | ! HasV6Ops ; UseMovt = DarwinUseMOVT && hasV6T2Ops ( ) ; const Triple & T = getTargetTriple ( ) ; SupportsTailCall = T . getOS ( ) == Triple :: IOS && ! T . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; if ( ! StrictAlign && hasV6Ops ( ) && isTargetDarwin ( ) )


<s> HasV6MOps = false ; HasV6KOps = false ; HasV6T2Ops = false ; HasV7Ops = false ; HasV8Ops = false ; HasV8_1aOps = false ; HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseInlineJumpTables = ! NoInlineJumpTables ; UseConstIslands = true ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; No<ISA_LIT> = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack =


<s> HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; No<ISA_LIT> = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension =


<s> if ( SubVer >= '7' && SubVer <= '9' ) { <ISA_LIT>ArchVersion = V7A ; } else if ( SubVer == '6' ) { <ISA_LIT>ArchVersion = V6 ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == '2' ) <ISA_LIT>ArchVersion = V6T2 ; } else if ( SubVer == '5' ) { <ISA_LIT>ArchVersion = V5T ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == 'e' ) <ISA_LIT>ArchVersion = V5TE ; } else if ( SubVer == '4' ) { if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' ) <ISA_LIT>ArchVersion = V4T ; else <ISA_LIT>ArchVersion = V4 ; } } if ( <ISA_LIT>ArchVersion >= V6T2 ) ThumbMode = Thumb2 ; else if ( ThumbMode >= Thumb2 ) <ISA_LIT>ArchVersion =


<s> <STR_LIT> AK = <STR_LIT> ( ArchName ) ; if ( AK == <STR_LIT> :: <ISA_LIT>V7S ) CPUString = <STR_LIT> ; else if ( AK == <STR_LIT> :: <ISA_LIT>V7K ) CPUString = <STR_LIT> ; } } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = std :: string ( FS ) ; } ParseSubtargetFeatures ( CPUString , CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; if ( genExecuteOnly ( ) ) { NoMovt = false ; assert ( hasV8MBaselineOps ( ) && <STR_LIT> ) ; } SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) && ! hasMinSize ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; if ( MVEVectorCostFactor == <NUM_LIT> ) MVEVectorCostFactor = <NUM_LIT> ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9 : LdStMultipleTiming = DoubleIssueCheckUnalignedAccess ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case CortexA12 : break ; case CortexA15 : MaxInterleaveFactor = <NUM_LIT> ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; PartialUpdateClearance = <NUM_LIT> ; break ; case CortexA17 : case CortexA32 : case CortexA35 : case CortexA53 : case CortexA55 : case CortexA57 : case CortexA72 : case CortexA73 : case CortexA75 : case CortexA76 : case CortexA77 : case CortexA78 : case CortexR4 : case CortexR4F : case CortexR5 : case CortexR7 : case CortexM3


<s> return TargetTriple . getOS ( ) == Triple


<s> std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = std :: string ( FS ) ; } ParseSubtargetFeatures ( CPUString , CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; if ( genExecuteOnly ( ) ) { NoMovt = false ; assert ( hasV8MBaselineOps ( ) && <STR_LIT> ) ; } SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) && ! hasMinSize ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; if ( MVEVectorCostFactor == <NUM_LIT> ) MVEVectorCostFactor = <NUM_LIT> ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9 : LdStMultipleTiming = DoubleIssueCheckUnalignedAccess ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case CortexA12 : break ; case CortexA15 : MaxInterleaveFactor = <NUM_LIT> ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; PartialUpdateClearance = <NUM_LIT> ; break ; case CortexA17 : case CortexA32 : case CortexA35 : case CortexA53 : case CortexA55 : case CortexA57 : case CortexA72 : case CortexA73 : case CortexA75 : case CortexA76 : case CortexA77 : case CortexA78 : case CortexR4 : case CortexR4F : case CortexR5 : case CortexR7 : case CortexM3 : case CortexR52 : case CortexX1 : break ; case Exynos : LdStMultipleTiming = SingleIssuePlusExtras ; MaxInterleaveFactor = <NUM_LIT> ; if ( ! isThumb ( ) ) PrefLoopLogAlignment = <NUM_LIT> ; break ; case Kryo : break ; case Krait : PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case NeoverseN1


<s> <STR_LIT> AK = <STR_LIT> ( ArchName ) ; if ( AK == <STR_LIT> :: <ISA_LIT>V7S ) CPUString = <STR_LIT> ; else if ( AK == <STR_LIT> :: <ISA_LIT>V7K ) CPUString = <STR_LIT> ; } } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = std :: string ( FS ) ; } ParseSubtargetFeatures ( CPUString , CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; if ( genExecuteOnly ( ) ) { NoMovt = false ; assert ( hasV8MBaselineOps ( ) && <STR_LIT> ) ; } SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) && ! hasMinSize ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; if ( MVEVectorCostFactor == <NUM_LIT> ) MVEVectorCostFactor = <NUM_LIT> ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9 : LdStMultipleTiming = DoubleIssueCheckUnalignedAccess ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case CortexA12 : break ; case CortexA15 : MaxInterleaveFactor = <NUM_LIT> ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; PartialUpdateClearance = <NUM_LIT> ; break ; case CortexA17 : case CortexA32 : case CortexA35 : case CortexA53 : case CortexA55 : case CortexA57 : case CortexA72 : case CortexA73 : case CortexA75 : case CortexA76 : case CortexA77 : case CortexA78 : case CortexR4 : case CortexR4F : case CortexR5 : case CortexR7 : case CortexM3 : case CortexR52 : case CortexX1 : break ; case Exynos : LdStMultipleTiming = SingleIssuePlusExtras ; MaxInterleaveFactor = <NUM_LIT> ; if ( ! isThumb ( ) ) PrefLoopLogAlignment = <NUM_LIT> ; break ; case Kryo : break ; case Krait : PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case NeoverseN1 : break ; case Swift : MaxInterleaveFactor = <NUM_LIT> ; LdStMultipleTiming = SingleIssuePlusExtras ; PreISelOperandLatencyAdjustment =


<s> SlowFPBrcc = false ; InThumbMode = false ; UseSoftFloat = false ; HasThumb2 = false ; No<ISA_LIT> = false ; ReserveR9 = false ; NoMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasFullFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRetAddrStack = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; Has8MSecExt = false ; HasCrypto = false ; HasCRC = false ; HasRAS = false


<s> HasV6Ops = false ; HasV6MOps = false ; HasV6T2Ops = false ; HasV7Ops = false ; HasV8Ops = false ; HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseInlineJumpTables = ! NoInlineJumpTables ; UseConstIslands = true ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false


<s> case DefaultIT : RestrictIT = hasV8Ops ( ) && ! hasMinSize ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; if ( MVEVectorCostFactor == <NUM_LIT> ) MVEVectorCostFactor = <NUM_LIT> ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9 : LdStMultipleTiming = DoubleIssueCheckUnalignedAccess ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case CortexA12 : break ; case CortexA15 : MaxInterleaveFactor = <NUM_LIT> ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; PartialUpdateClearance = <NUM_LIT> ; break ; case CortexA17 : case CortexA32 : case CortexA35 : case CortexA53 : case CortexA55 : case CortexA57 : case CortexA72 : case CortexA73 : case CortexA75 : case CortexA76 : case CortexA77 : case CortexA78 : case CortexA78C : case CortexA710 : case CortexR4 : case CortexR4F : case CortexR5 : case CortexR7 : case CortexM3 : case CortexM7 : case CortexR52 : case CortexX1 : break ; case Exynos : LdStMultipleTiming = SingleIssuePlusExtras ; MaxInterleaveFactor = <NUM_LIT> ; if ( ! isThumb ( ) ) PrefLoopLogAlignment = <NUM_LIT> ; break ; case Kryo : break ; case Krait : PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case NeoverseN1 : case NeoverseN2 : case NeoverseV1 : break ; case Swift : MaxInterleaveFactor = <NUM_LIT> ; LdStMultipleTiming =


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>BaseTargetMachine & TM , bool IsLittle , bool MinSize ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , UseMulOps ( UseFusedMulOps ) , ReservedGPRegisters ( <STR_LIT> . getNumRegs ( ) ) , CPUString ( CPU ) , OptMinSize ( MinSize ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new <ISA_LIT>InstrInfo ( * this ) : ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) { CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo


<s> break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) || ( isTargetMachO ( ) && ! HasV6Ops ) ) ReservedGPRegisters . set ( <NUM_LIT> ) ; const int restFP = ( useR7AsFramePointer ( ) ) ? <NUM_LIT> : <NUM_LIT> ; if ( isGPRegisterReserved ( restFP ) ) report_fatal_error ( <STR_LIT> + std :: to_string ( restFP ) + <STR_LIT> ) ; if ( MVEVectorCostFactor == <NUM_LIT> ) MVEVectorCostFactor = <NUM_LIT> ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9 : LdStMultipleTiming = DoubleIssueCheckUnalignedAccess ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case CortexA12 : break ; case CortexA15 : MaxInterleaveFactor = <NUM_LIT> ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; PartialUpdateClearance = <NUM_LIT> ; break ; case CortexA17 : case CortexA32 : case CortexA35 : case CortexA53 : case CortexA55 : case CortexA57 : case CortexA72 : case CortexA73 : case CortexA75 : case CortexA76 : case CortexR4 : case CortexR4F : case CortexR5 : case CortexR7 : case CortexM3 : case CortexR52 : break ; case Exynos : LdStMultipleTiming = SingleIssuePlusExtras ; MaxInterleaveFactor = <NUM_LIT> ; if ( ! isThumb ( ) ) PrefLoopLogAlignment = <NUM_LIT> ; break ; case Kryo : break ; case Krait : PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case NeoverseN1 : break ; case Swift : MaxInterleaveFactor = <NUM_LIT> ; LdStMultipleTiming = SingleIssuePlusExtras ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; PartialUpdateClearance =


<s> HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; IsMClass = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; AllowsUnalignedMem = false ; Thumb2DSP = false ; UseNaClTrap = false ; UnsafeFPMath = false


<s> void <ISA_LIT>Subtarget :: initializeEnvironment ( ) { HasV4TOps = false ; HasV5TOps = false ; HasV5TEOps = false ; HasV6Ops = false ; HasV6T2Ops = false ; HasV7Ops = false ; HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; IsMClass = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide =


<s> bool <ISA_LIT>Subtarget :: enableAtomicExpand ( )


<s> bool <ISA_LIT>Subtarget :: enableMachineScheduler (


<s> if ( disablePostRAScheduler ( ) ) return false ; return ! isThumb1Only


<s> const LegalizerInfo * <ISA_LIT>Subtarget :: getLegalizerInfo ( )


<s> unsigned getPrefLoopAlignment ( ) const


<s> const RegisterBankInfo * <ISA_LIT>Subtarget :: getRegBankInfo ( ) const { return RegBankInfo . get (


<s> if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = <NUM_LIT> ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9


<s> if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = <NUM_LIT> ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9 : LdStMultipleTiming = DoubleIssueCheckUnalignedAccess ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case CortexA12 : break ; case CortexA15 : MaxInterleaveFactor = <NUM_LIT> ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; PartialUpdateClearance = <NUM_LIT> ; break ; case CortexA17 : case CortexA32 : case CortexA35 : case CortexA53 : case CortexA55 : case CortexA57 : case CortexA72 : case CortexA73 : case CortexA75 : case CortexR4 : case CortexR4F : case CortexR5 : case CortexR7 : case CortexM3 : case CortexR52 : break ; case Exynos : LdStMultipleTiming = SingleIssuePlusExtras ; MaxInterleaveFactor = <NUM_LIT> ; if ( ! isThumb ( ) ) PrefLoopAlignment = <NUM_LIT> ; break ; case Kryo : break ; case Krait : PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case Swift : MaxInterleaveFactor =


<s> bool <ISA_LIT>Subtarget :: isAAPCS_ABI ( ) const { assert ( TM . TargetABI

!= <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_UNKNOWN ) ;


<s> bool <ISA_LIT>Subtarget :: isGVIndirectSymbol ( const GlobalValue * GV ) const { if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV )


<s> return TM . getRelocationModel ( ) == Reloc :: RWPI || TM .

getRelocationModel ( ) == Reloc :: ROPI_RWPI ;


<s> return TM . getRelocationModel ( ) == Reloc :: RWPI ||

TM . getRelocationModel ( ) == Reloc :: ROPI_RWPI ;


<s> bool <ISA_LIT>Subtarget :: isXRaySupported ( )


<s> bool useAA ( ) const override { return


<s> bool useAA ( ) const override { return UseAA


<s> return TM . Options . EnableFastISel && ( ( isTargetMachO ( ) && ! isThumb1Only ( ) ) || ( isTargetLinux ( ) && ! isThumb

( ) ) || ( isTargetNaCl ( ) && ! isThumb ( ) ) ) ;


<s> bool <ISA_LIT>Subtarget :: useStride4VFPs ( const MachineFunction & MF


<s> NeedsSet = false ; HasLEB128 = true ; AbsoluteDebugSectionOffsets = true ; CStringSection = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; SetDirective = <STR_LIT> ; DwarfRequiresFrameSection = false ; DwarfAbbrevSection = <STR_LIT> ; DwarfInfoSection = <STR_LIT> ; DwarfLineSection = <STR_LIT> ; DwarfFrameSection = <STR_LIT> ; DwarfPubNamesSection = <STR_LIT> ; DwarfPubTypesSection = <STR_LIT> ; DwarfStrSection = <STR_LIT> ; DwarfLocSection = <STR_LIT> ; DwarfARangesSection = <STR_LIT> ; DwarfRangesSection =


<s> CStringSection = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; SetDirective = <STR_LIT> ; DwarfRequiresFrameSection = false ; DwarfAbbrevSection = <STR_LIT> ; DwarfInfoSection = <STR_LIT> ; DwarfLineSection = <STR_LIT> ; DwarfFrameSection = <STR_LIT> ; DwarfPubNamesSection = <STR_LIT> ; DwarfPubTypesSection = <STR_LIT> ; DwarfStrSection = <STR_LIT> ; DwarfLocSection = <STR_LIT> ; DwarfARangesSection = <STR_LIT> ; DwarfRangesSection =


<s> BaseTAI :: ConstantPoolSection = <STR_LIT> ; BaseTAI :: COMMDirectiveTakesAlignment = false ; BaseTAI :: InlineAsmStart = <STR_LIT> ; BaseTAI :: InlineAsmEnd = <STR_LIT> ; BaseTAI :: LCOMMDirective =


<s> unsigned count = <NUM_LIT> ; while ( * p && isspace ( * p ) && * p != '\n' ) p ++ ; count ++ ; while ( * p && * p != '\n' && strncmp ( p , BaseTAI :: CommentString , strlen ( BaseTAI :: CommentString ) ) != <NUM_LIT> ) { if ( * p == ',' ) count


<s> unsigned count = <NUM_LIT> ; while ( * p && isspace ( * p ) && * p != '\n' ) p ++ ; count ++ ; while ( * p && * p != '\n' && strncmp ( p , BaseTAI :: CommentString , strlen ( BaseTAI :: CommentString ) ) != <NUM_LIT> ) { if ( * p == ',' )


<s> Data64bitsDirective = <NUM_LIT> ; CommentString = <STR_LIT> ; COMMDirectiveTakesAlignment = false ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: SjLj ; AbsoluteEHSectionOffsets = false


<s> CommentString = <STR_LIT> ; COMMDirectiveTakesAlignment = false ; NeedsSet = false ; HasLEB128 = true ; AbsoluteDebugSectionOffsets = true ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; SetDirective = <STR_LIT> ; LCOMMDirective = <STR_LIT> ; DwarfRequiresFrameSection = false ; SupportsDebugInformation = true


<s> HasLEB128 = true ; AbsoluteDebugSectionOffsets = true ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; SetDirective = <STR_LIT> ; LCOMMDirective = <STR_LIT> ; DwarfRequiresFrameSection = false


<s> static Target The<ISA_LIT>BETarget ; return


<s> static Target The<ISA_LIT>BETarget ; return The<ISA_LIT>BETarget


<s> Target & llvm :: getTheThumbBETarget ( ) { static Target TheThumbBETarget ; return TheThumbBETarget


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: arm , true > X ( getThe<ISA_LIT>LETarget ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: armeb , true > Y ( getThe<ISA_LIT>BETarget ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: thumb , true > A ( getTheThumbLETarget


<s> RegisterTarget < Triple :: armeb , true > Y ( getThe<ISA_LIT>BETarget ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: thumb , true > A ( getTheThumbLETarget ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: thumbeb , true > B ( getTheThumbBETarget ( ) , <STR_LIT> , <STR_LIT> ,


<s> RegisterTarget < Triple :: arm , true > X ( getThe<ISA_LIT>LETarget ( ) , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: armeb , true > Y ( getThe<ISA_LIT>BETarget ( ) , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: thumb , true > A ( getTheThumbLETarget ( ) , <STR_LIT> ,


<s> RegisterTarget < Triple :: arm , true > X ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT>


<s> void MCLDInitialize<ISA_LIT>LDTargetInfo ( ) { mcld :: RegisterTarget < llvm :: Triple :: arm > X


<s> mcld :: RegisterTarget < llvm :: Triple :: thumb


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ,


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel


<s> addPass ( createUnpackMachineBundles ( [ this ] ( const Function & F ) { return this -> TM -> getSubtarget < <ISA_LIT>Subtarget > (


<s> addPass ( createExecutionDependencyFixPass ( & <STR_LIT> ) ) ; } addPass ( create<ISA_LIT>ExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createThumb2SizeReductionPass ( [ this ]


<s> Ret += <STR_LIT> ; if ( ABI != <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_APCS ) Ret += <STR_LIT> ; if ( ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_APCS ) Ret += <STR_LIT> ; if ( ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_APCS ) Ret += <STR_LIT> ; else if ( ABI != <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS16 ) Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( TT . isOSNaCl ( ) || ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS16 ) Ret += <STR_LIT> ; else if ( ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS )


<s> Ret += DataLayout :: getManglingComponent ( TT ) ; Ret += <STR_LIT> ; if ( ABI != <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_APCS ) Ret += <STR_LIT> ; if ( ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_APCS ) Ret += <STR_LIT> ; if ( ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_APCS ) Ret += <STR_LIT> ; else if ( ABI != <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS16 ) Ret += <STR_LIT> ; Ret +=


<s> TargetPassConfig * <ISA_LIT>BaseTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( this ,


<s> static std :: unique_ptr < TargetLoweringObjectFile > createTLOF ( const Triple & TT ) { if ( TT . isOSBinFormatMachO ( ) ) return make_unique < TargetLoweringObjectFileMachO > ( ) ; if ( TT . isOSWindows ( ) ) return make_unique < TargetLoweringObjectFileCOFF > ( ) ; return make_unique < <ISA_LIT>ElfTargetObjectFile > ( )


<s> std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . hasFnAttribute ( <STR_LIT> ) && F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( SoftFloat ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; auto & I = SubtargetMap [ CPU +


<s> TargetIRAnalysis <ISA_LIT>BaseTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( const Function & F ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ; } )


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>LETargetMachine > X ( The<ISA_LIT>LETarget ) ; RegisterTargetMachine < <ISA_LIT>BETargetMachine > Y ( The<ISA_LIT>BETarget ) ; RegisterTargetMachine < ThumbLETargetMachine > A ( TheThumbLETarget


<s> RegisterTargetMachine < <ISA_LIT>BETargetMachine > Y ( The<ISA_LIT>BETarget ) ; RegisterTargetMachine < ThumbLETargetMachine > A ( TheThumbLETarget


<s> ThumbTargetMachine :: ThumbTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) :

<ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , isLittle ) {


<s> ThumbTargetMachine :: ThumbTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , isLittle ) { initAsmInfo ( )


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( )


<s> PM . add ( createBasicTargetTransformInfoPass ( getTargetLowering ( ) ) ) ; PM . add ( create<ISA_LIT>TargetTransformInfoPass ( this )


<s> const <ISA_LIT>Subtarget * Subtarget = & get<ISA_LIT>Subtarget ( ) ; if ( Subtarget -> isTargetELF ( ) && ! Subtarget -> isThumb1Only ( ) && TM -> Options . EnableFastISel )

addPass ( create<ISA_LIT>GlobalBaseRegPass ( ) ) ;


<s> bool <ISA_LIT>PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge ) addPass ( createGlobalMergePass ( TM -> getTargetLowering (


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge ) addPass ( createGlobalMergePass ( TM -> getTargetLowering ( ) ) ) ; return


addPass ( createThumb2ITBlockPass ( ) ) ;


<s> <ISA_LIT>BaseTargetMachine :: <ISA_LIT>BaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS ) , JITInfo ( ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) { if ( Options . FloatABIType == FloatABI :: Default ) this

-> Options . FloatABIType = FloatABI :: Soft ;


<s> std :: string ( <STR_LIT> <STR_LIT> ) ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( * this , Subtarget ) { if ( ! Subtarget . has<ISA_LIT>Ops ( ) ) report_fatal_error ( <STR_LIT> + Subtarget . getCPUString ( ) + <STR_LIT>


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , Options , RM ,

CM , OL ) , InstrInfo ( Subtarget ) , DL ( Subtarget . isAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> ) :


<s> return * get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl (


<s> RegisterTargetMachine < ThumbTargetMachine >


<s> RegisterTargetMachine < ThumbTargetMachine > Y (


<s> ThumbTargetMachine :: ThumbTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , InstrInfo ( Subtarget . hasThumb2 ( ) ? ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( Subtarget ) ) : ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( Subtarget ) ) ) , DL ( Subtarget . isAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) : Subtarget . isAAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) : std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget . hasThumb2

( ) ? new <ISA_LIT>FrameLowering ( * this , Subtarget ) : ( <ISA_LIT>FrameLowering * ) new Thumb1FrameLowering ( * this , Subtarget ) ) {


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( <NUM_LIT> , false , false , true , true , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( create<ISA_LIT>ParallelDSPPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass


<s> addPass ( createBreakFalseDeps ( ) ) ; } addPass ( create<ISA_LIT>ExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createThumb2SizeReductionPass ( [ this ] ( const Function & F ) { return this -> TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) . restrictIT ( ) ; } ) ) ; addPass ( createIfConverter ( [ ] ( const MachineFunction & MF ) { return ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb1Only ( ) ; } ) ) ; } addPass ( createMVEVPTBlockPass ( ) ) ; addPass ( createThumb2ITBlockPass ( )


<s> std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( SoftFloat ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; std :: string Key = CPU + FS ; if ( F . hasMinSize ( ) ) Key += <STR_LIT> ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this , isLittle , F . hasMinSize ( ) ) ; if ( ! I -> isThumb ( ) && ! I -> has<ISA_LIT>Ops ( ) ) F . getContext ( ) . emitError ( <STR_LIT> + F . getName ( ) + <STR_LIT> <STR_LIT> ) ; } return I .


<s> const <ISA_LIT>Subtarget * <ISA_LIT>BaseTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( <STR_LIT> ) ; Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) .


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( <NUM_LIT> , false , false , true , true , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( create<ISA_LIT>ParallelDSPPass (


<s> <ISA_LIT>BaseTargetMachine :: <ISA_LIT>BaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) { if ( isTargetHardFloat ( ) ) this -> Options . FloatABIType = FloatABI :: Hard ; else this -> Options . FloatABIType = FloatABI :: Soft ; } if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF ) && ! ( TargetTriple . isOSWindows ( ) || TargetTriple . isOSDarwin ( ) ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI :: EABI5 ; } if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } setSupportsDebugEntryValues ( true ) ; initAsmInfo ( )


<s> return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb2 ( ) ; } ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None

) addPass ( create<ISA_LIT>OptimizeBarriersPass ( ) ) ;


<s> addPass ( create<ISA_LIT>LowOverheadLoopsPass ( ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardLongjmpPass


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createMVEVPTOptimisationsPass ( )


<s> std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( SoftFloat ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; std :: string Key = CPU + FS ; if ( F . hasMinSize ( ) ) Key


<s> auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this , isLittle , F . hasMinSize ( ) ) ; if ( ! I -> isThumb ( ) && ! I -> has<ISA_LIT>Ops ( ) ) F . getContext ( ) . emitError (

<STR_LIT> + F . getName ( ) + <STR_LIT> <STR_LIT> ) ;


<s> } addPass ( create<ISA_LIT>ExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createThumb2SizeReductionPass ( [ this ] ( const Function & F ) { return this -> TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) . hasMinSize ( ) || this -> TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) . restrictIT ( ) ; } ) ) ; addPass ( createIfConverter ( [ ] (


<s> <ISA_LIT>BaseTargetMachine :: <ISA_LIT>BaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options

, RM , CM , OL ) , Subtarget ( TT , CPU , FS , Options ) , JITInfo ( ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) {


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , InstrInfo ( Subtarget ) , DL ( Subtarget . isAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> ) : Subtarget . isAAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> ) : std :: string ( <STR_LIT> <STR_LIT> ) ) , TLInfo ( * this ) , TSInfo ( * this


<s> Subtarget . isAAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) : std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget . hasThumb2 ( ) ? new <ISA_LIT>FrameLowering ( Subtarget ) : ( <ISA_LIT>FrameLowering * ) new Thumb1FrameLowering ( Subtarget ) ) { initAsmInfo (


<s> <ISA_LIT>BaseTargetMachine :: <ISA_LIT>BaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , CM , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , Subtarget ( TT , CPU , FS , * this , isLittle ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ; if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( Subtarget . isTargetGNUAEABI ( ) || Subtarget . isTargetMuslAEABI ( ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI ::


<s> if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ; if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( Subtarget . isTargetGNUAEABI ( ) || Subtarget . isTargetMuslAEABI ( ) ) this

-> Options . EABIVersion = EABI :: GNU ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , isLittle ) { initAsmInfo ( ) ; if ( ! Subtarget . has<ISA_LIT>Ops ( ) ) report_fatal_error ( <STR_LIT> + Subtarget . getCPUString


<s> if ( * RM == Reloc :: DynamicNoPIC && ! TT . isOSDarwin ( ) ) return Reloc :: Static ; return * RM


<s> const <ISA_LIT>Subtarget * <ISA_LIT>BaseTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( <STR_LIT> ) ; Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( )


<s> Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( SoftFloat ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; <ISA_LIT>GISelActualAccessor * GISel = new <ISA_LIT>GISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * I -> getTargetLowering (


<s> RegisterTargetMachine < <ISA_LIT>LETargetMachine > X ( getThe<ISA_LIT>LETarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>BETargetMachine > Y ( getThe<ISA_LIT>BETarget ( ) ) ; RegisterTargetMachine < ThumbLETargetMachine > A (


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { PM . add ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; return false


<s> if ( getOptLevel ( ) != CodeGenOpt :: None && ! get<ISA_LIT>Subtarget ( ) . isThumb1Only ( )


PM . add ( createThumb2ITBlockPass ( ) ) ;


<s> Subtarget . isAAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> ) : std :: string ( <STR_LIT> <STR_LIT> ) ) , ELFWriterInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) { if ( ! Subtarget . has<ISA_LIT>Ops ( ) ) report_fatal_error ( <STR_LIT> + Subtarget . getCPUString (


<s> Subtarget . isAAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> ) : std :: string ( <STR_LIT> <STR_LIT> ) ) , ELFWriterInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) { if ( ! Subtarget . has<ISA_LIT>Ops ( ) ) report_fatal_error ( <STR_LIT> +

Subtarget . getCPUString ( ) + <STR_LIT> <STR_LIT> ) ;


<s> ThumbTargetMachine :: ThumbTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , InstrInfo ( Subtarget . hasThumb2 ( ) ? ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( Subtarget ) ) : ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( Subtarget ) ) ) , DataLayout ( Subtarget . isAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) : Subtarget . isAAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) : std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) ) , ELFWriterInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) ,

FrameLowering ( Subtarget . hasThumb2 ( ) ? new <ISA_LIT>FrameLowering ( Subtarget ) : ( <ISA_LIT>FrameLowering * ) new Thumb1FrameLowering ( Subtarget ) ) {


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( <NUM_LIT> , false , false , true , true , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; addPass ( createMVEGatherScatterLoweringPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass (


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>OptimizeBarriersPass ( ) ) ; addPass ( create<ISA_LIT>ConstantIslandPass ( ) ) ; addPass ( create<ISA_LIT>LowOverheadLoopsPass ( )


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( createUnpackMachineBundles ( [ ] ( const MachineFunction & MF ) { return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb2 ( ) ; } )


<s> addPass ( createIfConverter ( [ ] ( const MachineFunction & MF ) { return ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb1Only ( ) ; } ) ) ; } addPass ( createMVEVPTBlockPass ( ) ) ; addPass ( createThumb2ITBlockPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & PostMachineSchedulerID )


<s> printAndVerify ( <STR_LIT> ) ; } if ( get<ISA_LIT>Subtarget ( ) . hasNEON ( ) ) PM . add ( createExecutionDependencyFixPass ( & <STR_LIT> ) ) ; } PM . add ( create<ISA_LIT>ExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( ! get<ISA_LIT>Subtarget ( ) . isThumb1Only ( )


<s> virtual const <ISA_LIT>FrameInfo * getFrameInfo (


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const override { return &


<s> virtual <ISA_LIT>TargetLowering * getTargetLowering ( ) const { return const_cast < <ISA_LIT>TargetLowering * > ( &


<s> static void registerAsmPrinter ( AsmPrinterCtorFn F


<s> if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( - <NUM_LIT> , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass (


<s> if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( - <NUM_LIT> , [ this ] ( const Function & F ) { const auto & ST = this -> TM

-> getSubtarget < <ISA_LIT>Subtarget > ( F ) ;


<s> if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ; if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( Subtarget . isTargetGNUAEABI ( ) || Subtarget . isTargetMuslAEABI ( ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI :: EABI5 ; } initAsmInfo ( ) ; if ( ! Subtarget . isThumb ( ) && ! Subtarget . has<ISA_LIT>Ops ( ) ) report_fatal_error ( <STR_LIT> + Subtarget . getCPUString (


<s> if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( Subtarget . isTargetGNUAEABI ( ) || Subtarget . isTargetMuslAEABI ( ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI :: EABI5 ; } initAsmInfo ( ) ; if ( ! Subtarget . isThumb ( ) && ! Subtarget . has<ISA_LIT>Ops ( ) ) report_fatal_error ( <STR_LIT> +


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { ScheduleDAGMILive * DAG = createGenericSchedLive ( C ) ; return DAG