<s> bool <ISA_LIT>CallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , CallingConv :: ID CallConv , const MachineOperand & Callee , const ArgInfo & OrigRet , ArrayRef < ArgInfo > OrigArgs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; const auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; const auto & DL = MF . getDataLayout ( ) ; const auto & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( STI . genLongCalls ( ) ) return false ; auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; bool isDirect = ! Callee . isReg ( ) ; auto CallOpcode = isDirect ? <STR_LIT> : STI . hasV5TOps ( ) ? <STR_LIT> : STI . hasV4TOps ( ) ? <STR_LIT> : <STR_LIT> ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpcode ) . add ( Callee ) . addRegMask ( TRI -> getCallPreservedMask ( MF , CallConv ) ) ; if ( Callee . isReg ( ) ) { auto CalleeReg = Callee . getReg ( ) ; if ( CalleeReg && ! TRI -> isPhysicalRegister ( CalleeReg ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB . getInstr ( ) , MIB -> getDesc ( ) , Callee , <NUM_LIT> ) ) ; } SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; for ( auto Arg : OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( ! Arg . IsFixed ) return false ; if ( Arg . Flags . isByVal ( ) ) return false ; SmallVector < unsigned , <NUM_LIT> > Regs ; splitToValueTypes ( Arg , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { Regs . push_back (


<s> auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasByValOrInAllocaAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; SmallVector < unsigned , <NUM_LIT> > SplitRegs ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + AttributeList :: FirstArgIndex , DL


<s> auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasByValOrInAllocaAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; SmallVector < unsigned , <NUM_LIT> > SplitRegs


<s> auto const & ST = MIRBuilder . getMF ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned Opcode = ST . getReturnOpcode ( ) ; auto Ret = MIRBuilder . buildInstrNoInsert ( Opcode ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! lowerReturnVal ( MIRBuilder , Val , VReg , Ret ) ) return false ; MIRBuilder . insertInstr ( Ret ) ; return true


<s> auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; if ( ! isSupportedType ( DL , TLI , Val -> getType ( ) ) ) return false ; SmallVector < ArgInfo , <NUM_LIT> > SplitVTs ; SmallVector < unsigned , <NUM_LIT> > Regs ; ArgInfo RetInfo ( VReg , Val -> getType ( ) ) ; setArgFlags ( RetInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( RetInfo , SplitVTs , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { Regs . push_back ( Reg ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> ) MIRBuilder . buildUnmerge ( Regs , VReg ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret , AssignFn ) ; return handleAssignments ( MIRBuilder , SplitVTs , RetHandler


<s> void assignValueToAddress ( Register ValVReg , Register Addr , LLT MemTy , MachinePointerInfo & MPO , CCValAssign & VA ) override { if ( VA . getLocInfo ( ) == CCValAssign :: SExt || VA . getLocInfo ( ) == CCValAssign :: ZExt ) { MemTy = LLT :: scalar ( <NUM_LIT> ) ; assert ( MRI . getType ( ValVReg ) . isScalar ( ) && <STR_LIT> ) ; auto LoadVReg = buildLoad ( LLT :: scalar ( <NUM_LIT> ) , Addr , MemTy , MPO ) ; MIRBuilder . buildTrunc ( ValVReg , LoadVReg ) ; } else


<s> MachineInstrBuilder buildLoad ( const DstOp & Res , Register Addr , LLT MemTy , MachinePointerInfo & MPO ) { MachineFunction & MF = MIRBuilder . getMF (


<s> MachineInstrBuilder buildLoad ( const DstOp & Res , Register Addr , LLT MemTy , MachinePointerInfo & MPO ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , MemTy , inferAlignFromPtrInfo ( MF , MPO ) ) ; return MIRBuilder . buildLoad ( Res , Addr


<s> if ( isDirect ) return STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ; if ( STI . isThumb ( ) ) return gettBLXrOpcode ( MF ) ; if ( STI . hasV5TOps ( ) ) return getBLXOpcode ( MF ) ; if ( STI . hasV4TOps ( ) ) return <STR_LIT> ; return


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO , <STR_LIT> Flags ) override { assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; const bool IsImmutable = ! Flags . isByVal (


<s> int FI = MFI . CreateFixedObject ( Size , Offset , IsImmutable ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; return MIRBuilder . buildFrameIndex ( LLT :: pointer ( MPO . getAddrSpace ( )

, <NUM_LIT> ) , FI ) . getReg ( <NUM_LIT> ) ;


<s> auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpcode ) ; bool IsThumb = STI . isThumb ( ) ; if ( IsThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; MIB . add ( Info . Callee ) ; if ( ! IsDirect ) { auto CalleeReg = Info . Callee . getReg ( ) ; if ( CalleeReg && ! Register :: isPhysicalRegister ( CalleeReg ) ) { unsigned CalleeIdx = IsThumb ? <NUM_LIT> : <NUM_LIT> ; MIB -> getOperand ( CalleeIdx ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB . getInstr ( ) , MIB -> getDesc ( ) , Info . Callee , CalleeIdx ) ) ; } } MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , Info . CallConv ) ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; for ( auto Arg : Info . OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( Arg . Flags [ <NUM_LIT> ] . isByVal ( ) ) return false ; splitToValueTypes ( Arg , ArgInfos , DL , Info . CallConv ) ; } auto ArgAssignFn = TLI . CCAssignFnForCall ( Info . CallConv , Info . IsVarArg ) ; OutgoingValueAssigner ArgAssigner ( ArgAssignFn ) ; <ISA_LIT>OutgoingValueHandler ArgHandler ( MIRBuilder , MRI , MIB ) ; if ( ! determineAndHandleAssignments ( ArgHandler , ArgAssigner , ArgInfos , MIRBuilder , Info . CallConv , Info . IsVarArg ) ) return false ; MIRBuilder . insertInstr (


<s> if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; const auto & DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasPassPointeeByValueCopyAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; OutgoingValueAssigner ArgAssigner ( AssignFn ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgInfos ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) , Idx ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , DL , F . getCallingConv ( ) ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr (


<s> unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) , Idx ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , DL , F . getCallingConv ( ) ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; if ( ! determineAndHandleAssignments ( ArgHandler , ArgAssigner , SplitArgInfos , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ) return false ; MIRBuilder . setMBB ( MBB


<s> assert ( ! Val == VRegs . empty ( ) && <STR_LIT> ) ; auto const & ST = MIRBuilder . getMF ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned Opcode = ST . getReturnOpcode ( ) ; auto Ret = MIRBuilder . buildInstrNoInsert ( Opcode ) .


<s> bool <ISA_LIT>CallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs , FunctionLoweringInfo & FLI ) const { assert ( ! Val == VRegs . empty ( ) && <STR_LIT> ) ; auto const & ST = MIRBuilder . getMF ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned Opcode = ST . getReturnOpcode ( ) ; auto Ret = MIRBuilder . buildInstrNoInsert ( Opcode ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! lowerReturnVal ( MIRBuilder , Val , VRegs , Ret ) ) return false ; MIRBuilder . insertInstr (


<s> setArgFlags ( OrigRetInfo , AttributeList :: ReturnIndex , DL , F ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitRetInfos ; splitToValueTypes ( OrigRetInfo , SplitRetInfos , DL , F . getCallingConv ( ) ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; OutgoingValueAssigner RetAssigner ( AssignFn ) ; <ISA_LIT>OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret ) ; return determineAndHandleAssignments ( RetHandler , RetAssigner , SplitRetInfos , MIRBuilder , F . getCallingConv ( )


<s> Register NewRegs [ ] = { MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) , MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) } ; assignValueToReg ( NewRegs [ <NUM_LIT> ] , VA . getLocReg ( ) , VA ) ; assignValueToReg ( NewRegs [ <NUM_LIT> ] , NextVA . getLocReg ( ) , NextVA ) ; bool IsLittle = MIRBuilder . getMF ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . isLittle ( ) ; if ( ! IsLittle ) std :: swap ( NewRegs [ <NUM_LIT> ] , NewRegs [ <NUM_LIT> ] ) ; MIRBuilder . buildMerge ( Arg . Regs [ <NUM_LIT> ] ,


<s> uint64_t ValSize = VA . getValVT ( ) . getFixedSizeInBits ( ) ; uint64_t LocSize = VA . getLocVT ( ) . getFixedSizeInBits ( ) ; assert ( ValSize <= <NUM_LIT> && <STR_LIT> ) ; assert ( LocSize <= <NUM_LIT> && <STR_LIT> ) ; markPhysRegUsed ( PhysReg ) ; if ( ValSize == LocSize ) { MIRBuilder . buildCopy ( ValVReg , PhysReg ) ; } else { assert ( ValSize <


<s> const auto & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( STI . genLongCalls ( ) ) return false ; if ( STI . isThumb1Only ( ) ) return false ; auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; bool IsDirect = ! Info . Callee . isReg ( ) ; auto CallOpcode = getCallOpcode ( MF , STI , IsDirect ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpcode ) ; bool IsThumb = STI . isThumb ( ) ; if ( IsThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; MIB . add ( Info . Callee ) ; if ( ! IsDirect ) { auto CalleeReg = Info . Callee . getReg ( ) ; if ( CalleeReg && ! Register :: isPhysicalRegister ( CalleeReg ) ) { unsigned CalleeIdx = IsThumb ? <NUM_LIT> : <NUM_LIT> ; MIB -> getOperand ( CalleeIdx ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB . getInstr ( ) , MIB -> getDesc ( ) , Info . Callee , CalleeIdx ) ) ; } } MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , Info . CallConv ) ) ; SmallVector < ArgInfo , <NUM_LIT>


<s> SmallVector < ArgInfo , <NUM_LIT> > SplitArgInfos ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , MF , [ & ] ( Register Reg ) { llvm_unreachable ( <STR_LIT> ) ; } ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgInfos , ArgHandler ) ) return false ; MIRBuilder . setMBB ( MBB


<s> EVT VT = TLI . getValueType ( DL , T , true ) ; if ( ! VT . isSimple ( ) || VT . isVector ( ) ) return false ; unsigned VTSize = VT . getSimpleVT (


<s> splitToValueTypes ( Arg , ArgInfos , DL , MRI ) ; } auto ArgAssignFn = TLI . CCAssignFnForCall ( CallConv , false ) ; OutgoingValueHandler ArgHandler ( MIRBuilder , MRI , MIB , ArgAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( ! OrigRet . Ty -> isVoidTy ( ) ) { if ( ! isSupportedType ( DL , TLI , OrigRet . Ty ) ) return false ; ArgInfos . clear ( ) ; splitToValueTypes ( OrigRet , ArgInfos , DL , MRI ) ; auto RetAssignFn = TLI . CCAssignFnForReturn ( CallConv , false ) ; CallReturnHandler RetHandler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder ,

ArgInfos , RetHandler ) ) return false ;


<s> auto & MF = MIRBuilder . getMF ( ) ; auto DL = MF . getDataLayout ( ) ; auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb ( ) ) return false ; if ( Subtarget -> useSoftFloat ( ) || ! Subtarget -> hasVFP2 ( ) ) return false ; auto & Args = F . getArgumentList ( ) ; for ( auto & Arg : Args ) if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : Args ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + <NUM_LIT> , DL , F ) ; splitToValueTypes ( AInfo , ArgInfos , DL , MF . getRegInfo ( ) ) ; Idx ++ ; } FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; return handleAssignments ( MIRBuilder , ArgInfos


<s> auto DL = MF . getDataLayout ( ) ; auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; if ( ! isSupportedType ( DL , TLI , Val -> getType ( ) ) ) return false ; SmallVector < ArgInfo , <NUM_LIT> > SplitVTs ; ArgInfo RetInfo ( VReg , Val -> getType


<s> bool IsDirect = ! Info . Callee . isReg ( ) ; auto CallOpcode = getCallOpcode ( STI , IsDirect ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpcode ) ; bool IsThumb = STI . isThumb ( ) ; if ( IsThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; MIB . add ( Info . Callee ) ; if ( ! IsDirect ) { auto CalleeReg = Info . Callee . getReg ( ) ; if ( CalleeReg && ! Register :: isPhysicalRegister ( CalleeReg ) ) { unsigned CalleeIdx = IsThumb ? <NUM_LIT> : <NUM_LIT> ; MIB -> getOperand ( CalleeIdx ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB . getInstr ( ) , MIB -> getDesc ( ) , Info . Callee , CalleeIdx ) ) ; } } MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , Info . CallConv ) ) ; bool IsVarArg = false ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; for ( auto Arg : Info . OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( ! Arg . IsFixed ) IsVarArg = true ; if ( Arg . Flags [ <NUM_LIT> ] . isByVal ( ) ) return false ; splitToValueTypes ( Arg , ArgInfos , MF ) ; } auto ArgAssignFn = TLI . CCAssignFnForCall ( Info . CallConv , IsVarArg ) ; <ISA_LIT>OutgoingValueHandler ArgHandler ( MIRBuilder , MRI


<s> FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgInfos ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , MF ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( *


<s> CCValAssign NextVA = VAs [ <NUM_LIT> ] ; assert ( NextVA . needsCustom ( ) && <STR_LIT> ) ; assert ( NextVA . getValVT ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( VA . getValNo ( ) == NextVA . getValNo ( ) && <STR_LIT> ) ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; assert ( NextVA . isRegLoc ( ) && <STR_LIT> ) ; Register NewRegs [ ] = { MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) , MRI . createGenericVirtualRegister (


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt || VA . getLocInfo ( ) == CCValAssign :: ZExt ) { Size = <NUM_LIT> ; assert ( MRI . getType ( ValVReg ) . isScalar ( ) && <STR_LIT> ) ; auto LoadVReg = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; buildLoad ( LoadVReg , Addr , Size , <NUM_LIT> , MPO ) ; MIRBuilder . buildTrunc ( ValVReg , LoadVReg ) ; }


<s> assert ( MRI . getType ( ValVReg ) . isScalar ( ) && <STR_LIT> ) ; auto LoadVReg = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; buildLoad ( LoadVReg , Addr , Size , <NUM_LIT> , MPO ) ; MIRBuilder . buildTrunc ( ValVReg , LoadVReg )


<s> auto LocSize = VA . getLocVT ( ) . getSizeInBits ( ) ; assert ( ValSize <= <NUM_LIT> && <STR_LIT> ) ; assert ( LocSize <= <NUM_LIT> && <STR_LIT> ) ; markPhysRegUsed ( PhysReg ) ; if ( ValSize == LocSize ) { MIRBuilder . buildCopy ( ValVReg , PhysReg ) ; } else { assert ( ValSize < LocSize && <STR_LIT> ) ; auto PhysRegToVReg = MRI . createGenericVirtualRegister ( LLT :: scalar ( LocSize ) ) ; MIRBuilder . buildCopy ( PhysRegToVReg , PhysReg ) ; MIRBuilder . buildTrunc ( ValVReg ,


<s> auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , Size , Alignment ) ; MIRBuilder . buildLoad ( Val , Addr


<s> assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , true ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( LLT :: pointer (

MPO . getAddrSpace ( ) , <NUM_LIT> ) ) ;


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset ,


<s> const auto & DL = MF . getDataLayout ( ) ; const auto & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( STI . genLongCalls ( ) ) return false ; if ( STI . isThumb1Only ( ) ) return false ; auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; bool IsDirect = ! Callee . isReg ( ) ; auto CallOpcode = getCallOpcode ( STI , IsDirect ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpcode ) ; bool IsThumb = STI . isThumb ( ) ; if ( IsThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; MIB . add ( Callee ) ; if ( ! IsDirect ) { auto CalleeReg = Callee . getReg ( ) ; if ( CalleeReg && ! TRI -> isPhysicalRegister ( CalleeReg ) ) { unsigned CalleeIdx = IsThumb ? <NUM_LIT> : <NUM_LIT> ; MIB -> getOperand ( CalleeIdx ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB . getInstr ( ) , MIB -> getDesc ( ) , Callee , CalleeIdx ) ) ; } } MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , CallConv )


<s> } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgInfos ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos ,


<s> for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , MF ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgInfos , ArgHandler ) ) return false ; MIRBuilder . setMBB


<s> auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , Size , Alignment ) ; return MIRBuilder . buildLoad ( Res ,


<s> assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt || VA . getLocInfo ( ) == CCValAssign :: ZExt ) { Size = <NUM_LIT> ; assert ( MRI . getType ( ValVReg ) . isScalar ( ) && <STR_LIT> ) ; auto LoadVReg = buildLoad ( LLT :: scalar ( <NUM_LIT> ) , Addr , Size


<s> MachineInstrBuilder buildLoad ( const DstOp & Res , Register Addr , uint64_t Size , unsigned Alignment , MachinePointerInfo & MPO ) { auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , Size , Alignment ) ; return MIRBuilder . buildLoad ( Res , Addr


<s> assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , true ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; Register AddrReg = MRI . createGenericVirtualRegister ( LLT :: pointer (


<s> ComputeValueVTs ( TLI , DL , OrigArg . Ty , SplitVTs , nullptr , nullptr , <NUM_LIT> ) ; assert ( OrigArg . Regs . size ( ) == SplitVTs . size ( ) && <STR_LIT> ) ; if ( SplitVTs . size ( ) == <NUM_LIT> ) { auto Flags = OrigArg . Flags [ <NUM_LIT> ] ; unsigned OriginalAlignment = DL . getABITypeAlignment ( OrigArg . Ty ) ; Flags . setOrigAlign ( OriginalAlignment ) ; SplitArgs . emplace_back ( OrigArg . Regs [ <NUM_LIT> ] , SplitVTs [ <NUM_LIT> ] . getTypeForEVT ( Ctx ) , Flags , OrigArg . IsFixed ) ; return ; } for ( unsigned i = <NUM_LIT> , e = SplitVTs . size ( ) ; i != e ; ++ i ) { EVT SplitVT = SplitVTs [ i ]


<s> auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; bool isDirect = ! Callee . isReg ( ) ; auto CallOpcode = isDirect ? <STR_LIT> : STI . hasV5TOps ( ) ? <STR_LIT> : STI . hasV4TOps ( ) ? <STR_LIT> : <STR_LIT> ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpcode ) . add ( Callee ) . addRegMask ( TRI -> getCallPreservedMask ( MF , CallConv ) ) ; if ( Callee . isReg ( ) ) { auto CalleeReg = Callee . getReg ( ) ; if ( CalleeReg && ! TRI -> isPhysicalRegister ( CalleeReg ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB . getInstr ( ) , MIB -> getDesc ( ) , CalleeReg , <NUM_LIT> ) ) ; } SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; for ( auto Arg : OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( ! Arg . IsFixed ) return false ; SmallVector < unsigned , <NUM_LIT> > Regs ; splitToValueTypes ( Arg , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { Regs . push_back ( Reg ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> ) MIRBuilder . buildUnmerge ( Regs , Arg . Reg ) ; } auto ArgAssignFn = TLI . CCAssignFnForCall ( CallConv , false ) ; OutgoingValueHandler ArgHandler ( MIRBuilder , MRI , MIB , ArgAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( ! OrigRet . Ty -> isVoidTy ( ) ) { if ( ! isSupportedType ( DL , TLI , OrigRet . Ty ) ) return false ; ArgInfos . clear ( ) ; SmallVector < unsigned , <NUM_LIT> > SplitRegs ; splitToValueTypes ( OrigRet , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { SplitRegs . push_back ( Reg ) ; } ) ; auto RetAssignFn = TLI . CCAssignFnForReturn ( CallConv , false ) ; CallReturnHandler RetHandler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , RetHandler )


<s> if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; SmallVector < unsigned , <NUM_LIT> > SplitRegs ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg


<s> SmallVector < ArgInfo , <NUM_LIT> > SplitVTs ; SmallVector < unsigned , <NUM_LIT> > Regs ; ArgInfo RetInfo ( VReg , Val -> getType ( ) ) ; setArgFlags ( RetInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( RetInfo , SplitVTs , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { Regs . push_back ( Reg ) ; }


<s> const DataLayout & DL = MF . getDataLayout ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const Function * F = MF . getFunction ( ) ; SmallVector < EVT , <NUM_LIT> > SplitVTs ; SmallVector < uint64_t , <NUM_LIT> > Offsets ; ComputeValueVTs ( TLI , DL , OrigArg . Ty , SplitVTs , & Offsets , <NUM_LIT> ) ; if ( SplitVTs . size ( ) == <NUM_LIT> ) { auto Flags = OrigArg . Flags ; unsigned OriginalAlignment = DL . getABITypeAlignment ( OrigArg . Ty ) ; Flags . setOrigAlign ( OriginalAlignment ) ; SplitArgs . emplace_back ( OrigArg . Reg , SplitVTs [ <NUM_LIT> ] . getTypeForEVT ( Ctx ) , Flags , OrigArg . IsFixed ) ; return ; } unsigned FirstRegIdx = SplitArgs .


<s> ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , DL , F . getCallingConv ( ) ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; if ( ! determineAndHandleAssignments ( ArgHandler , ArgAssigner , SplitArgInfos , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ) return false ; MIRBuilder . setMBB ( MBB


<s> } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; OutgoingValueAssigner ArgAssigner ( AssignFn ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgInfos ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , DL , F . getCallingConv ( ) ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( *


<s> if ( ! isSupportedType ( DL , TLI , Val -> getType ( ) ) ) return false ; ArgInfo OrigRetInfo ( VRegs , Val -> getType ( ) ) ; setArgFlags ( OrigRetInfo , AttributeList :: ReturnIndex , DL , F ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitRetInfos ; splitToValueTypes ( OrigRetInfo , SplitRetInfos , DL , F . getCallingConv ( ) ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; OutgoingValueAssigner RetAssigner ( AssignFn ) ; <ISA_LIT>OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret ) ; return determineAndHandleAssignments ( RetHandler , RetAssigner , SplitRetInfos , MIRBuilder , F . getCallingConv ( ) ,


<s> if ( ! Val ) return true ; auto & MF = MIRBuilder . getMF ( ) ; const auto & F = MF . getFunction ( ) ; const auto & DL = MF . getDataLayout ( ) ; auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; if ( ! isSupportedType ( DL , TLI , Val -> getType ( ) ) ) return false ; ArgInfo OrigRetInfo ( VRegs , Val -> getType ( ) ) ; setArgFlags ( OrigRetInfo , AttributeList :: ReturnIndex , DL ,


<s> auto ArgAssignFn = TLI . CCAssignFnForCall ( Info . CallConv , IsVarArg ) ; <ISA_LIT>OutgoingValueHandler ArgHandler ( MIRBuilder , MRI , MIB , ArgAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) { if ( ! isSupportedType ( DL , TLI , Info . OrigRet . Ty ) ) return false ; ArgInfos . clear ( ) ; splitToValueTypes ( Info . OrigRet , ArgInfos , MF ) ; auto RetAssignFn = TLI . CCAssignFnForReturn ( Info . CallConv , IsVarArg ) ; CallReturnHandler RetHandler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , RetHandler ) ) return false ; } CallSeqStart . addImm ( ArgHandler . StackSize ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; MIRBuilder . buildInstr ( <STR_LIT> ) . addImm ( ArgHandler . StackSize ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; return true


<s> auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasPassPointeeByValueCopyAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo ,


<s> MIRBuilder . buildConstant ( OffsetReg , Offset ) ; Register AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildPtrAdd ( AddrReg , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MIRBuilder


<s> const auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; const auto & DL = MF . getDataLayout ( ) ; const auto & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( STI . genLongCalls ( ) ) return false ; if ( STI . isThumb1Only ( ) ) return false ; auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; bool IsDirect = ! Callee . isReg ( ) ; auto CallOpcode = getCallOpcode ( STI , IsDirect ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpcode ) ; bool IsThumb = STI . isThumb ( ) ; if ( IsThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; MIB . add ( Callee ) ; if ( ! IsDirect ) { auto CalleeReg = Callee . getReg ( ) ; if ( CalleeReg && ! TRI -> isPhysicalRegister ( CalleeReg ) ) { unsigned CalleeIdx = IsThumb ? <NUM_LIT> : <NUM_LIT> ; MIB -> getOperand ( CalleeIdx ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB . getInstr ( ) , MIB -> getDesc ( ) , Callee , CalleeIdx ) ) ; } } MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , CallConv ) ) ; bool IsVarArg = false ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; for ( auto Arg : OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( ! Arg . IsFixed ) IsVarArg = true ; if ( Arg . Flags . isByVal ( ) ) return false ; SmallVector < unsigned , <NUM_LIT> > Regs ; splitToValueTypes ( Arg , ArgInfos , MF , [ & ] ( unsigned Reg ) { Regs . push_back ( Reg ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> ) MIRBuilder . buildUnmerge


<s> auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasByValOrInAllocaAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; SmallVector < unsigned , <NUM_LIT> > SplitRegs ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType


<s> bool <ISA_LIT>CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasByValOrInAllocaAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; SmallVector < unsigned ,


<s> bool <ISA_LIT>CallLowering :: lowerReturnVal ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < unsigned > VRegs , MachineInstrBuilder & Ret ) const { if ( ! Val ) return true ; auto & MF = MIRBuilder . getMF ( ) ; const auto & F = MF . getFunction ( ) ; auto DL = MF . getDataLayout ( ) ; auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; if ( ! isSupportedType ( DL , TLI , Val -> getType ( ) ) ) return false ; SmallVector < EVT , <NUM_LIT> > SplitEVTs ; ComputeValueVTs ( TLI , DL , Val -> getType ( ) , SplitEVTs ) ; assert ( VRegs . size ( ) == SplitEVTs . size ( ) && <STR_LIT>


<s> assert ( NextVA . isRegLoc ( ) && <STR_LIT> ) ; unsigned NewRegs [ ] = { MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) , MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) } ; MIRBuilder . buildExtract ( NewRegs [ <NUM_LIT> ] , Arg . Reg , <NUM_LIT> ) ; MIRBuilder . buildExtract ( NewRegs [ <NUM_LIT> ] , Arg . Reg , <NUM_LIT> ) ; bool IsLittle = MIRBuilder . getMF ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . isLittle ( ) ; if ( ! IsLittle ) std :: swap ( NewRegs [ <NUM_LIT>


<s> auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( <STR_LIT> ) . add ( Callee ) . addRegMask ( TRI -> getCallPreservedMask ( MF , CallConv ) ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; for ( auto Arg : OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( ! Arg . IsFixed ) return false ; splitToValueTypes ( Arg , ArgInfos , DL , MRI ) ; } auto ArgAssignFn = TLI . CCAssignFnForCall ( CallConv , false ) ; OutgoingValueHandler ArgHandler ( MIRBuilder , MRI , MIB , ArgAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( ! OrigRet . Ty -> isVoidTy ( ) ) { if ( ! isSupportedType ( DL , TLI , OrigRet . Ty ) ) return false ; ArgInfos . clear ( ) ; splitToValueTypes ( OrigRet , ArgInfos , DL , MRI ) ; auto RetAssignFn = TLI . CCAssignFnForReturn ( CallConv , false ) ; CallReturnHandler RetHandler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , RetHandler ) ) return


<s> auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb ( ) ) return false ; for ( auto & Arg : F . args ( ) ) if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + <NUM_LIT> , DL , F ) ; splitToValueTypes ( AInfo , ArgInfos , DL , MF . getRegInfo


<s> auto & MF = MIRBuilder . getMF ( ) ; const auto & F = * MF . getFunction ( ) ; auto DL = MF . getDataLayout ( ) ; auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; if ( ! isSupportedType ( DL , TLI , Val -> getType ( ) ) ) return false ; SmallVector < ArgInfo , <NUM_LIT> > SplitVTs ; ArgInfo RetInfo ( VReg , Val -> getType ( ) ) ; setArgFlags ( RetInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( RetInfo , SplitVTs , DL , MF . getRegInfo ( ) ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv (


<s> auto DL = MF . getDataLayout ( ) ; auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb ( ) ) return false ; for ( auto & Arg : F . args ( ) ) if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; SmallVector < unsigned , <NUM_LIT> > SplitRegs ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; SplitRegs . clear ( )


<s> for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + <NUM_LIT> , DL , F ) ; splitToValueTypes ( AInfo , ArgInfos , DL , MF . getRegInfo ( ) ) ; Idx ++ ; } FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; return handleAssignments ( MIRBuilder , ArgInfos ,


<s> for ( auto & Arg : F . args ( ) ) if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + <NUM_LIT> , DL , F ) ; splitToValueTypes ( AInfo , ArgInfos , DL , MF .


<s> assert ( VA . needsCustom ( ) && <STR_LIT> ) ; assert ( VA . getValVT ( ) == <STR_LIT> && <STR_LIT> ) ; CCValAssign NextVA = VAs [ <NUM_LIT> ] ; assert ( NextVA . needsCustom ( ) && <STR_LIT> ) ; assert ( NextVA . getValVT ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( VA . getValNo ( ) == NextVA . getValNo ( ) && <STR_LIT> ) ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; assert ( NextVA . isRegLoc ( ) && <STR_LIT> ) ; unsigned NewRegs [ ] = { MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) , MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) } ; assignValueToReg ( NewRegs [ <NUM_LIT> ] , VA . getLocReg ( ) , VA ) ; assignValueToReg ( NewRegs [ <NUM_LIT> ] , NextVA . getLocReg ( ) , NextVA ) ; bool IsLittle = MIRBuilder . getMF ( ) . getSubtarget < <ISA_LIT>Subtarget


<s> assignValueToReg ( NewRegs [ <NUM_LIT> ] , NextVA . getLocReg ( ) , NextVA ) ; bool IsLittle = MIRBuilder . getMF ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . isLittle ( ) ; if ( ! IsLittle ) std :: swap ( NewRegs [ <NUM_LIT> ] , NewRegs [ <NUM_LIT> ] ) ; MIRBuilder . buildSequence ( Arg . Reg , NewRegs , { <NUM_LIT> , <NUM_LIT> } ) ; return


<s> auto DL = MF . getDataLayout ( ) ; auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; if ( ! isSupportedType ( DL , TLI , Val -> getType ( ) ) ) return false ; SmallVector < ArgInfo , <NUM_LIT> > SplitVTs ; ArgInfo RetInfo ( VReg , Val -> getType ( ) ) ; setArgFlags ( RetInfo , AttributeSet :: ReturnIndex , DL , F ) ; splitToValueTypes ( RetInfo , SplitVTs , DL , MF . getRegInfo ( ) ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) , F . isVarArg


<s> bool <ISA_LIT>CallLowering :: lowerReturnVal ( MachineIRBuilder & MIRBuilder , const Value * Val , unsigned VReg , MachineInstrBuilder & Ret ) const { if ( ! Val ) return true ; auto & MF = MIRBuilder . getMF ( ) ; const auto & F = * MF . getFunction ( ) ; auto DL = MF . getDataLayout ( ) ; auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; if ( ! isSupportedType ( DL , TLI , Val -> getType ( ) ) ) return false ; SmallVector < ArgInfo , <NUM_LIT> > SplitVTs ; ArgInfo RetInfo ( VReg , Val -> getType ( ) ) ; setArgFlags ( RetInfo , AttributeSet :: ReturnIndex , DL , F ) ; splitToValueTypes ( RetInfo , SplitVTs , DL , MF . getRegInfo ( ) ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FuncReturnHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret ,


<s> const auto & DL = MF . getDataLayout ( ) ; const auto & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( STI . genLongCalls ( ) ) return false ; if ( STI . isThumb1Only ( ) ) return false ; auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; bool IsDirect = ! Info . Callee . isReg ( ) ; auto CallOpcode = getCallOpcode ( MF , STI , IsDirect ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpcode ) ; bool IsThumb = STI . isThumb ( ) ; if ( IsThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; MIB . add ( Info . Callee ) ; if ( ! IsDirect ) { auto CalleeReg = Info . Callee . getReg ( ) ; if ( CalleeReg && ! Register :: isPhysicalRegister ( CalleeReg ) ) { unsigned CalleeIdx = IsThumb ? <NUM_LIT> : <NUM_LIT> ; MIB -> getOperand ( CalleeIdx ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB . getInstr ( ) , MIB -> getDesc ( ) , Info . Callee , CalleeIdx ) ) ; } } MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , Info . CallConv ) ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; for ( auto Arg : Info . OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( Arg . Flags [ <NUM_LIT> ] . isByVal ( ) ) return false ; splitToValueTypes ( Arg , ArgInfos , MF ) ; } auto ArgAssignFn = TLI . CCAssignFnForCall ( Info . CallConv , Info . IsVarArg ) ; <ISA_LIT>OutgoingValueHandler ArgHandler ( MIRBuilder , MRI , MIB , ArgAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ) return false ; MIRBuilder . insertInstr ( MIB


<s> auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; bool isDirect = ! Callee . isReg ( ) ; auto CallOpcode = isDirect ? <STR_LIT> : STI . hasV5TOps ( ) ? <STR_LIT> : STI . hasV4TOps ( ) ? <STR_LIT> : <STR_LIT> ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpcode ) . add ( Callee ) . addRegMask ( TRI -> getCallPreservedMask ( MF , CallConv ) ) ; if ( Callee . isReg ( ) ) { auto CalleeReg = Callee . getReg ( ) ; if ( CalleeReg && ! TRI -> isPhysicalRegister ( CalleeReg ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB . getInstr ( ) , MIB -> getDesc ( ) , CalleeReg , <NUM_LIT> ) ) ; } SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; for ( auto Arg : OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( ! Arg . IsFixed ) return false ; if ( Arg . Flags . isByVal ( ) ) return false ; SmallVector < unsigned , <NUM_LIT> > Regs ; splitToValueTypes ( Arg , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { Regs . push_back ( Reg ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> ) MIRBuilder . buildUnmerge ( Regs , Arg . Reg ) ; } auto ArgAssignFn = TLI . CCAssignFnForCall ( CallConv , false ) ; OutgoingValueHandler ArgHandler ( MIRBuilder , MRI , MIB , ArgAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( ! OrigRet . Ty -> isVoidTy ( ) ) { if ( ! isSupportedType ( DL , TLI , OrigRet . Ty ) ) return false ; ArgInfos . clear ( ) ; SmallVector < unsigned , <NUM_LIT> > SplitRegs ; splitToValueTypes ( OrigRet , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { SplitRegs . push_back ( Reg ) ; }


<s> if ( Callee . isReg ( ) ) { auto CalleeReg = Callee . getReg ( ) ; if ( CalleeReg && ! TRI -> isPhysicalRegister ( CalleeReg ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB . getInstr ( ) , MIB -> getDesc ( ) , CalleeReg , <NUM_LIT> ) ) ; } SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; for ( auto Arg : OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( ! Arg . IsFixed ) return false ; if ( Arg . Flags . isByVal ( ) ) return false ; SmallVector < unsigned , <NUM_LIT> > Regs ; splitToValueTypes ( Arg , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { Regs . push_back ( Reg ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> ) MIRBuilder . buildUnmerge ( Regs , Arg . Reg ) ; } auto ArgAssignFn = TLI . CCAssignFnForCall ( CallConv , false ) ; OutgoingValueHandler ArgHandler ( MIRBuilder , MRI ,


<s> static bool isSupportedType ( const DataLayout & DL , const <ISA_LIT>TargetLowering & TLI , Type * T ) { EVT VT = TLI . getValueType ( DL , T , true ) ; if ( ! VT . isSimple ( ) || VT . isVector ( ) || ! ( VT . isInteger ( ) || VT . isFloatingPoint ( ) ) ) return false ; unsigned VTSize = VT . getSimpleVT ( )


<s> unsigned VTSize = VT . getSimpleVT ( ) . getSizeInBits ( ) ; if ( VTSize == <NUM_LIT> ) return VT . isFloatingPoint ( ) ; return VTSize == <NUM_LIT> || VTSize == <NUM_LIT> || VTSize == <NUM_LIT>


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt || VA . getLocInfo ( ) == CCValAssign :: ZExt ) { Size = <NUM_LIT> ; assert ( MRI . getType ( ValVReg ) . isScalar ( )


<s> markPhysRegUsed ( PhysReg ) ; if ( ValSize == LocSize ) { MIRBuilder . buildCopy ( ValVReg , PhysReg ) ; } else { assert ( ValSize < LocSize && <STR_LIT> ) ; auto PhysRegToVReg = MIRBuilder . buildCopy ( LLT :: scalar ( LocSize ) , PhysReg ) ; MIRBuilder . buildTrunc ( ValVReg


<s> assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; assert ( VA . getLocReg ( ) == PhysReg && <STR_LIT> ) ; auto ValSize = VA . getValVT ( ) . getSizeInBits ( ) ; auto LocSize = VA . getLocVT ( ) . getSizeInBits ( ) ; assert ( ValSize <=


<s> auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , Size , inferAlignFromPtrInfo ( MF , MPO ) ) ; return MIRBuilder . buildLoad ( Res ,


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; auto & MFI = MIRBuilder . getMF


<s> MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; return MIRBuilder . buildFrameIndex ( LLT :: pointer ( MPO . getAddrSpace ( ) , <NUM_LIT>


<s> bool isIncomingArgumentHandler ( ) const override { return true


<s> if ( T -> isStructTy ( ) ) { auto StructT = cast < StructType > ( T ) ; for ( unsigned i = <NUM_LIT> , e = StructT -> getNumElements ( ) ; i != e ; ++ i ) if ( StructT -> getElementType ( i ) != StructT -> getElementType ( <NUM_LIT> ) ) return false ; return isSupportedType ( DL , TLI , StructT -> getElementType ( <NUM_LIT> ) ) ; } EVT VT = TLI . getValueType ( DL , T , true ) ; if ( ! VT . isSimple ( ) || VT . isVector ( ) || ! ( VT . isInteger ( ) || VT . isFloatingPoint ( ) ) ) return false ; unsigned VTSize = VT . getSimpleVT ( ) . getSizeInBits ( ) ; if ( VTSize == <NUM_LIT> ) return VT .


<s> const auto & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( STI . genLongCalls ( ) ) return false ; if ( STI . isThumb1Only ( ) ) return false ; auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; bool IsDirect = ! Info . Callee . isReg ( ) ; auto CallOpcode = getCallOpcode ( STI , IsDirect ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpcode ) ; bool IsThumb = STI . isThumb ( ) ; if ( IsThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; MIB . add ( Info . Callee ) ; if ( ! IsDirect ) { auto CalleeReg = Info . Callee . getReg ( ) ; if ( CalleeReg && ! Register :: isPhysicalRegister ( CalleeReg ) ) { unsigned CalleeIdx = IsThumb ? <NUM_LIT> : <NUM_LIT> ; MIB -> getOperand ( CalleeIdx ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB . getInstr ( ) , MIB -> getDesc ( ) , Info


<s> auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasPassPointeeByValueAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgInfos ; unsigned Idx


<s> auto const & ST = MIRBuilder . getMF ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned Opcode = ST . getReturnOpcode ( ) ; auto Ret = MIRBuilder . buildInstrNoInsert ( Opcode ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! lowerReturnVal ( MIRBuilder , Val , VRegs , Ret ) ) return false ; MIRBuilder . insertInstr (


<s> auto const & ST = MIRBuilder . getMF ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned Opcode = ST . getReturnOpcode ( ) ; auto Ret = MIRBuilder . buildInstrNoInsert ( Opcode ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! lowerReturnVal ( MIRBuilder , Val , VRegs , Ret ) ) return false ; MIRBuilder . insertInstr ( Ret ) ; return true


<s> auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; if ( ! isSupportedType ( DL , TLI , Val -> getType ( ) ) ) return false ; ArgInfo OrigRetInfo ( VRegs , Val -> getType ( ) ) ; setArgFlags ( OrigRetInfo , AttributeList :: ReturnIndex , DL , F ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitRetInfos ; splitToValueTypes ( OrigRetInfo , SplitRetInfos , MF ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) ,


<s> assert ( ACPV -> isGlobalValue ( ) && <STR_LIT> ) ; const GlobalValue * GV = ACPV -> getGV ( ) ; if ( GV ) { Reloc :: Model RelocM = TM . getRelocationModel ( ) ; emitGlobalAddress ( GV , <STR_LIT> , isa < Function > ( GV ) , Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) , ( intptr_t ) ACPV ) ; } else { emitExternalSymbolAddress ( ACPV -> getSymbol ( ) , <STR_LIT> ) ; } emitWordLE ( <NUM_LIT> ) ; } else { const Constant * CV = MCPE . Val . ConstVal ; DEBUG ( { errs ( ) << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> ; if ( const Function * F = dyn_cast < Function > ( CV ) ) errs ( ) << F -> getName ( ) ; else errs ( ) << * CV ; errs ( ) << '\n' ; } ) ; if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( CV ) ) { emitGlobalAddress ( GV , <STR_LIT> , isa < Function > ( GV ) , false ) ; emitWordLE ( <NUM_LIT> ) ; } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( CV ) ) { uint32_t Val = uint32_t ( * CI -> getValue ( ) . getRawData ( ) ) ; emitWordLE ( Val ) ; } else if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( CV ) ) { if ( CFP -> getType ( ) -> isFloatTy ( ) ) emitWordLE ( CFP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ) ; else if ( CFP -> getType ( ) -> isDoubleTy ( ) ) emitDWordLE ( CFP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ) ; else { llvm_unreachable ( <STR_LIT>


<s> JTI -> addConstantPoolEntryAddr ( CPI , MCE . getCurrentPCValue ( ) ) ; if ( MCPE . isMachineConstantPoolEntry ( ) ) { <ISA_LIT>ConstantPoolValue * ACPV = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE . Val . MachineCPVal ) ; DEBUG ( errs ( ) << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> << * ACPV << '\n' ) ; assert ( ACPV -> isGlobalValue ( ) && <STR_LIT> ) ; const GlobalValue * GV = ACPV -> getGV ( ) ; if ( GV ) { Reloc :: Model RelocM = TM . getRelocationModel ( ) ; emitGlobalAddress ( GV , <STR_LIT> , isa < Function > ( GV ) , Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) , ( intptr_t ) ACPV ) ; } else { emitExternalSymbolAddress ( ACPV -> getSymbol ( ) , <STR_LIT> ) ; } emitWordLE ( <NUM_LIT> ) ; } else { const Constant * CV = MCPE . Val . ConstVal ; DEBUG ( { errs ( ) << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> ; if ( const Function * F = dyn_cast < Function > ( CV ) ) errs ( ) << F -> getName ( ) ; else errs ( ) << * CV ; errs ( ) << '\n' ; } ) ; if ( const GlobalValue * GV = dyn_cast < GlobalValue >


<s> Binary |= getAddrModeSBit ( MI , TID ) ; unsigned NumDefs = TID . getNumDefs ( ) ; unsigned OpIdx = <NUM_LIT> ; if ( NumDefs ) Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; else if ( ImplicitRd ) Binary |= ( get<ISA_LIT>RegisterNumbering ( ImplicitRd ) << <STR_LIT> ) ; if ( TID . Opcode == <STR_LIT> ) { unsigned Lo16 = getMovi32Value ( MI , MI . getOperand ( OpIdx ) , <STR_LIT> ) ; Binary |= Lo16 & <NUM_LIT> ; Binary |= ( ( Lo16 >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( TID . Opcode == <STR_LIT> ) { unsigned Hi16 = ( getMovi32Value ( MI , MI . getOperand ( OpIdx ) , <STR_LIT> ) >> <NUM_LIT> ) ; Binary |= Hi16 & <NUM_LIT> ; Binary |= ( ( Hi16 >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( ( TID . Opcode == <STR_LIT> ) || ( TID . Opcode == <STR_LIT> ) ) { uint32_t v = ~ MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int32_t lsb = CountTrailingZeros_32 ( v ) ; int32_t msb = ( <NUM_LIT> - CountLeadingZeros_32 ( v ) ) - <NUM_LIT> ; Binary |= ( msb & <NUM_LIT> ) << <NUM_LIT> ; Binary |= ( lsb & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary


<s> case <STR_LIT> : emitLoadStoreInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitMiscLoadStoreInstruction ( MI ) ; break ; case <STR_LIT> : emitLoadStoreMultipleInstruction ( MI ) ; break ; case <STR_LIT> : emitMulFrmInstruction ( MI ) ; break ; case <STR_LIT> : emitExtendInstruction ( MI ) ; break ; case <STR_LIT> : emitMiscArithInstruction ( MI ) ; break ; case <STR_LIT> : emitSaturateInstruction ( MI ) ; break ; case <STR_LIT> : emitBranchInstruction ( MI ) ; break ; case <STR_LIT> : emitMiscBranchInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitVFPArithInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : emitVFPConversionInstruction ( MI ) ; break ; case <STR_LIT> : emitVFPLoadStoreInstruction ( MI )


<s> const TargetInstrDesc & TID = MI . getDesc ( ) ; unsigned Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getAddrModeSBit ( MI , TID ) ; Binary |= getMachineOpValue ( MI , <NUM_LIT> ) << <STR_LIT> ; Binary |= get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) << <STR_LIT> ; Binary |= <NUM_LIT> << <STR_LIT> ; emitJumpTableAddress ( MI . getOperand ( <NUM_LIT> ) . getIndex ( ) , <STR_LIT> ) ; emitWordLE ( Binary )


<s> const TargetInstrDesc & TID = MI . getDesc ( ) ; unsigned Form = TID . TSFlags & <STR_LIT> ; bool IsPrePost = ( TID . TSFlags & <STR_LIT> ) != <NUM_LIT> ; unsigned Binary = getBinaryCodeForInstr ( MI ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { emitWordLE ( Binary ) ; return ; } Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; bool Skipped = false ; if ( IsPrePost && Form == <STR_LIT> ) { ++ OpIdx ; Skipped = true ; } if ( ImplicitRd ) Binary |= ( get<ISA_LIT>RegisterNumbering ( ImplicitRd ) << <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ImplicitRn ) Binary |= ( get<ISA_LIT>RegisterNumbering ( ImplicitRn ) << <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ! Skipped && TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; const MachineOperand & MO2 = MI . getOperand ( OpIdx ) ; unsigned AM2Opc = ( ImplicitRn == <STR_LIT> ) ? <NUM_LIT> : MI . getOperand ( OpIdx + <NUM_LIT> ) . getImm ( ) ; Binary |= ( ( <STR_LIT> ( AM2Opc ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <STR_LIT> ) ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( AM2Opc ) ) Binary |= <STR_LIT> ( AM2Opc ) ; emitWordLE ( Binary ) ; return ; } Binary |= <NUM_LIT> << <STR_LIT> ; assert ( TargetRegisterInfo :: isPhysicalRegister ( MO2 . getReg ( ) ) ) ; Binary |= get<ISA_LIT>RegisterNumbering ( MO2 . getReg ( ) ) ; if ( unsigned ShImm = <STR_LIT> ( AM2Opc ) ) { Binary |= getShiftOp (


<s> Binary |= getMachineOpValue ( MI , MO ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) ; unsigned ShiftAmt = MI . getOperand ( OpIdx ) . getImm ( ) ; if ( TID . Opcode == <STR_LIT> ) { assert ( ShiftAmt != <NUM_LIT> && <STR_LIT> ) ; if ( ShiftAmt == <NUM_LIT> ) ShiftAmt = <NUM_LIT> ; } assert ( ShiftAmt < <NUM_LIT> && <STR_LIT> ) ; Binary |= ShiftAmt


<s> Binary |= getMachineOpValue ( MI , MO ) ; emitWordLE ( Binary ) ; return ; } Binary |= getMachineOpValue ( MI , MO ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) ; unsigned ShiftAmt = MI . getOperand ( OpIdx ) . getImm ( ) ; if ( TID . Opcode == <STR_LIT> ) { assert ( ShiftAmt != <NUM_LIT> && <STR_LIT> ) ; if ( ShiftAmt == <NUM_LIT> ) ShiftAmt = <NUM_LIT> ; } assert ( ShiftAmt < <NUM_LIT> && <STR_LIT>


<s> if ( TID . Opcode == <STR_LIT> || TID . Opcode == <STR_LIT> ) { emitDataProcessingInstruction ( MI , <STR_LIT> ) ; unsigned JTIndex = ( TID . Opcode == <STR_LIT> ) ? MI . getOperand ( <NUM_LIT> ) . getIndex ( ) : MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; emitInlineJumpTable ( JTIndex ) ; return ; } else if ( TID . Opcode


<s> Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; bool Skipped = false ; if ( IsPrePost && Form == <STR_LIT> ) { ++ OpIdx ; Skipped = true ; } Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( TID . Opcode == <STR_LIT> || TID . Opcode == <STR_LIT> ) ++ OpIdx ; if ( ImplicitRn ) Binary |= ( get<ISA_LIT>RegisterNumbering ( ImplicitRn ) << <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ! Skipped && TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO )


<s> void <ISA_LIT>CodeEmitter :: emitNEON2RegInstruction ( const MachineInstr & MI ) { const TargetInstrDesc & TID = MI . getDesc ( ) ; unsigned Binary = getBinaryCodeForInstr ( MI


<s> unsigned Binary = getBinaryCodeForInstr ( MI ) ; unsigned OpIdx = <NUM_LIT> ; Binary |= encodeNEONRd ( MI , OpIdx ++ ) ; if ( TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; Binary |= encodeNEONRn ( MI


<s> RegT = get<ISA_LIT>RegisterNumbering ( RegT ) ; Binary |= ( RegT << <STR_LIT> ) ; Binary |= encodeNEONRn ( MI , <NUM_LIT> ) ; emitWordLE ( Binary


<s> void <ISA_LIT>CodeEmitter :: emitNEONDupInstruction ( const MachineInstr & MI ) { unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= ( IsThumb ? <STR_LIT> : II -> getPredicate ( & MI ) ) << <STR_LIT> ; unsigned RegT = MI . getOperand ( <NUM_LIT> ) . getReg


<s> if ( ( Binary & ( <NUM_LIT> << <NUM_LIT> ) ) != <NUM_LIT> ) LaneShift = <NUM_LIT> ; else if ( ( Binary & ( <NUM_LIT> << <NUM_LIT> ) ) != <NUM_LIT> ) LaneShift = <NUM_LIT> ; else LaneShift = <NUM_LIT> ; unsigned Lane = MI . getOperand ( LnOpIdx ) . getImm ( ) << LaneShift ; unsigned Opc1 = Lane >> <NUM_LIT> ; unsigned Opc2 = Lane & <NUM_LIT> ; assert ( ( Opc1 & <NUM_LIT> ) ==


<s> unsigned LaneShift ; if ( ( Binary & ( <NUM_LIT> << <NUM_LIT> ) ) != <NUM_LIT> ) LaneShift = <NUM_LIT> ; else if ( ( Binary & ( <NUM_LIT> << <NUM_LIT> ) ) != <NUM_LIT> ) LaneShift = <NUM_LIT> ; else LaneShift = <NUM_LIT> ; unsigned Lane = MI . getOperand ( LnOpIdx ) . getImm ( ) << LaneShift ; unsigned Opc1 = Lane >> <NUM_LIT> ; unsigned Opc2 = Lane & <NUM_LIT> ; assert ( ( Opc1 & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Binary |= ( Opc1 << <NUM_LIT> ) ; Binary |= ( Opc2 << <NUM_LIT> ) ; emitWordLE (


<s> } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { addPCLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; emitLoadStoreInstruction ( MI , <NUM_LIT> , <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { addPCLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; emitMiscLoadStoreInstruction ( MI , <STR_LIT> ) ; break ; } case <STR_LIT> : if ( Subtarget -> hasV6T2Ops ( ) ) emitMOVi32immInstruction ( MI ) ; else emitMOVi2piecesInstruction ( MI ) ; break ; case <STR_LIT> : emitLEApcrelJTInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : emitPseudoMoveInstruction ( MI )


<s> assert ( ( Pos < <NUM_LIT> || ( Pos < <NUM_LIT> && TID . Opcode != <STR_LIT> && TID . Opcode != <STR_LIT> ) ) && <STR_LIT> ) ; Binary |= Pos << <NUM_LIT> ; Binary |= getMachineOpValue ( MI , <NUM_LIT> ) ; if ( TID . getNumOperands ( ) == <NUM_LIT> ) { unsigned ShiftOp = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; <STR_LIT> Opc = <STR_LIT> ( ShiftOp ) ; if ( Opc == <STR_LIT> ) Binary


<s> if ( IsUpdating ) ++ OpIdx ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; <STR_LIT> Mode = <STR_LIT> ( MI . getOpcode ( ) ) ; Binary |= getAddrModeUPBits ( <STR_LIT> ( Mode ) ) ; if ( IsUpdating ) Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= encodeVFPRd ( MI , OpIdx + <NUM_LIT> ) ; unsigned NumRegs = <NUM_LIT> ; for ( unsigned i = OpIdx + <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isImplicit ( ) ) break ; ++ NumRegs ; } if ( Binary & <NUM_LIT> ) Binary |= NumRegs * <NUM_LIT> ; else Binary |= NumRegs


<s> static unsigned encodeNEONRd ( const MachineInstr & MI , unsigned OpIdx ) { unsigned RegD = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary = <NUM_LIT> ; RegD = get<ISA_LIT>RegisterNumbering ( RegD ) ; Binary |= ( RegD & <NUM_LIT> ) << <STR_LIT> ; Binary |= ( ( RegD >> <NUM_LIT> ) & <NUM_LIT>


<s> Binary |= ( RegM & <NUM_LIT> ) ; Binary |= ( ( RegM >> <NUM_LIT> ) & <NUM_LIT> ) << <STR_LIT> ; return Binary


<s> RegN = get<ISA_LIT>RegisterNumbering ( RegN ) ; Binary |= ( RegN & <NUM_LIT> ) << <STR_LIT> ; Binary |= ( ( RegN >> <NUM_LIT> ) &


<s> static unsigned encodeNEONRn ( const MachineInstr & MI , unsigned OpIdx ) { unsigned RegN = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary = <NUM_LIT> ; RegN = get<ISA_LIT>RegisterNumbering ( RegN ) ; Binary |= ( RegN &


<s> unsigned RegD = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary = <NUM_LIT> ; bool isSPVFP = <STR_LIT> -> contains ( RegD ) ; RegD = get<ISA_LIT>RegisterNumbering ( RegD ) ; if ( ! isSPVFP ) Binary |= RegD << <STR_LIT> ; else { Binary |= ( ( RegD & <NUM_LIT> ) >> <NUM_LIT> ) << <STR_LIT> ; Binary |= ( RegD & <NUM_LIT> ) << <STR_LIT> ; } return Binary


<s> unsigned RegM = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary = <NUM_LIT> ; bool isSPVFP = <STR_LIT> -> contains ( RegM ) ; RegM = get<ISA_LIT>RegisterNumbering ( RegM ) ; if ( ! isSPVFP ) Binary |= RegM ; else { Binary |= ( ( RegM & <NUM_LIT> ) >> <NUM_LIT>


<s> static unsigned encodeVFPRn ( const MachineInstr & MI , unsigned OpIdx ) { unsigned RegN = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary =


<s> const MachineOperand & MO = MI . getOperand ( Op ) ; const MachineOperand & MO1 = MI . getOperand ( Op + <NUM_LIT> ) ; if ( ! MO . isReg ( ) ) { emitConstPoolAddress ( MO . getIndex ( ) ,


<s> } unsigned Reg = get<ISA_LIT>RegisterNumbering ( MO . getReg ( ) ) ; int32_t Imm12 = MO1 . getImm ( ) ; uint32_t Binary ; Binary = Imm12 & <NUM_LIT> ; if ( Imm12 >= <NUM_LIT> ) Binary |= ( <NUM_LIT> << <NUM_LIT> ) ; Binary |= ( Reg << <NUM_LIT>


<s> unsigned getImmMinusOneOpValue ( const MachineInstr &


<s> unsigned getImmMinusOneOpValue ( const MachineInstr & MI , unsigned Op


<s> do { DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB ) { MCE . StartMachineBasicBlock ( MBB ) ; for ( MachineBasicBlock :: const_iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) emitInstruction ( * I ) ; } } while ( MCE . finishFunction ( MF ) ) ; return


<s> unsigned VFPThumb2PostEncoder ( const MachineInstr & MI , unsigned Val ) const { return <NUM_LIT>


<s> void Emitter < CodeEmitter > :: addPCLabel ( unsigned LabelID ) { DOUT << <STR_LIT> << LabelID << <STR_LIT> << ( void

* ) MCE . getCurrentPCValue ( ) << '\n' ;


<s> DOUT << <STR_LIT> << LabelID << <STR_LIT> << ( void *


<s> FunctionPass * llvm :: create<ISA_LIT>CodeEmitterPass ( <ISA_LIT>BaseTargetMachine & TM , MachineCodeEmitter &


<s> FunctionPass * llvm :: create<ISA_LIT>CodeEmitterPass ( <ISA_LIT>BaseTargetMachine & TM , MachineCodeEmitter & MCE ) { return new Emitter < MachineCodeEmitter > ( TM ,


<s> FunctionPass * llvm :: create<ISA_LIT>JITCodeEmitterPass ( <ISA_LIT>BaseTargetMachine & TM , JITCodeEmitter & JCE ) { return new Emitter < JITCodeEmitter > (


<s> return new Emitter < JITCodeEmitter >


<s> return new Emitter < ObjectCodeEmitter >


<s> return new Emitter < ObjectCodeEmitter > ( TM ,


<s> } unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI


<s> void Emitter < CodeEmitter > :: emitConstPoolAddress ( unsigned CPI , unsigned Reloc ) { MCE . addRelocation ( MachineRelocation :: getConstPool ( MCE . getCurrentPCOffset ( ) , Reloc , CPI ,


<s> if ( MCPE . isMachineConstantPoolEntry ( ) ) { <ISA_LIT>ConstantPoolValue * ACPV = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE . Val . MachineCPVal ) ; DOUT << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> << * ACPV << '\n' ; GlobalValue * GV = ACPV -> getGV ( ) ; if ( GV ) { Reloc :: Model RelocM = TM . getRelocationModel ( ) ; emitGlobalAddress ( GV , <STR_LIT> , isa < Function > ( GV ) , Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) , ( intptr_t ) ACPV ) ; } else { emitExternalSymbolAddress ( ACPV -> getSymbol ( ) , <STR_LIT> ) ; } emitWordLE ( <NUM_LIT> ) ; } else { Constant * CV = MCPE . Val . ConstVal ; DEBUG ( { errs ( ) << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> ; if ( const Function * F = dyn_cast < Function > ( CV ) ) errs ( ) << F -> getName ( ) ; else errs ( ) << * CV ; errs ( ) << '\n' ; } ) ; if ( GlobalValue * GV = dyn_cast < GlobalValue > ( CV ) ) { emitGlobalAddress ( GV , <STR_LIT> , isa < Function > ( GV ) , false ) ; emitWordLE ( <NUM_LIT> ) ; } else if ( const ConstantInt * CI = dyn_cast


<s> if ( GV ) { Reloc :: Model RelocM = TM . getRelocationModel ( ) ; emitGlobalAddress ( GV , <STR_LIT> , isa < Function > ( GV ) , Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) , ( intptr_t ) ACPV ) ; } else { emitExternalSymbolAddress ( ACPV -> getSymbol ( ) , <STR_LIT> ) ; } emitWordLE ( <NUM_LIT> ) ; } else { Constant * CV = MCPE . Val . ConstVal ; DEBUG ( { errs ( ) << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> ; if ( const Function * F = dyn_cast < Function > ( CV ) ) errs ( ) << F -> getName ( ) ; else errs ( ) << * CV ; errs ( ) << '\n' ; } ) ; if ( GlobalValue * GV = dyn_cast < GlobalValue > ( CV ) ) { emitGlobalAddress ( GV , <STR_LIT> , isa < Function > ( GV ) , false ) ; emitWordLE ( <NUM_LIT> ) ; } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( CV ) ) { uint32_t Val = * ( uint32_t * ) CI -> getValue ( ) . getRawData ( ) ; emitWordLE ( Val ) ; } else if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( CV ) ) { if ( CFP -> getType ( ) == Type :: getFloatTy ( CFP -> getContext ( ) ) ) emitWordLE ( CFP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ) ; else if ( CFP -> getType ( ) == Type :: getDoubleTy ( CFP -> getContext ( ) ) ) emitDWordLE ( CFP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ) ; else { llvm_unreachable (


<s> DOUT << <STR_LIT> << std :: hex << std :: setw ( <NUM_LIT> ) << std :: setfill ( '0' ) << ( unsigned ) ( Binary >> <NUM_LIT>


<s> } else { Binary |= getMachineOpValue ( MI , MO1 ) ; } if ( MI . getOperand ( OpIdx ) . isImm ( ) && ! TID . OpInfo [ OpIdx ] . isPredicate ( ) && ! TID .

OpInfo [ OpIdx ] . isOptionalDef ( ) ) Binary |= ( getMachineOpValue ( MI , OpIdx ) / <NUM_LIT> ) << <STR_LIT> ;


<s> void Emitter < CodeEmitter > :: emitExternalSymbolAddress ( const char * ES


<s> MachineRelocation MR = Indirect ? MachineRelocation :: getIndirectSymbol ( MCE . getCurrentPCOffset ( ) , Reloc , GV , ACPV , NeedStub ) : MachineRelocation :: getGV ( MCE . getCurrentPCOffset ( ) , Reloc


<s> const std :: vector < MachineBasicBlock * > & MBBs = ( * MJTEs ) [ JTIndex ] . MBBs ; for ( unsigned i = <NUM_LIT> , e = MBBs . size ( ) ; i != e ; ++ i ) { if ( IsPIC ) emitMachineBasicBlock ( MBBs [ i ] , <STR_LIT> , JTBase ) ; else emitMachineBasicBlock ( MBBs [ i ] , <STR_LIT> ) ; emitWordLE (


<s> case <STR_LIT> : emitLoadStoreInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitMiscLoadStoreInstruction ( MI ) ; break ; case <STR_LIT> : emitLoadStoreMultipleInstruction ( MI ) ; break ; case <STR_LIT> : emitMulFrmInstruction ( MI ) ; break ; case <STR_LIT> : emitExtendInstruction ( MI ) ; break ; case <STR_LIT> : emitMiscArithInstruction ( MI ) ; break ; case <STR_LIT> : emitBranchInstruction ( MI ) ; break ; case <STR_LIT> : emitMiscBranchInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitVFPArithInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : emitVFPConversionInstruction ( MI ) ; break ; case <STR_LIT>


<s> void Emitter < CodeEmitter > :: emitLEApcrelJTInstruction ( const MachineInstr & MI ) { const TargetInstrDesc & TID = MI . getDesc ( ) ; unsigned Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getAddrModeSBit ( MI ,


<s> Binary |= getAddrModeUPBits ( <STR_LIT> ( MO . getImm ( ) ) ) ; if ( <STR_LIT> ( MO . getImm ( ) ) ) Binary |= <NUM_LIT> << <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand (


<s> void Emitter < CodeEmitter > :: emitMachineBasicBlock ( MachineBasicBlock * BB


<s> void Emitter < CodeEmitter > :: emitMachineBasicBlock ( MachineBasicBlock * BB , unsigned Reloc


<s> void Emitter < CodeEmitter > :: emitMiscInstruction ( const MachineInstr & MI ) { unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; emitWordLE (


<s> ++ OpIdx ; Skipped = true ; } Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( TID . Opcode == <STR_LIT> || TID . Opcode == <STR_LIT> ) ++ OpIdx ; if ( ImplicitRn ) Binary |= ( <ISA_LIT>RegisterInfo :: getRegisterNumbering ( ImplicitRn ) << <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ! Skipped && TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; const MachineOperand & MO2 = MI . getOperand ( OpIdx ) ; unsigned AM3Opc = ( ImplicitRn == <STR_LIT> ) ? <NUM_LIT> : MI . getOperand ( OpIdx + <NUM_LIT> ) . getImm ( ) ; Binary |= ( ( <STR_LIT> ( AM3Opc ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <STR_LIT> ) ; if ( MO2 . getReg


<s> else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ! Skipped && TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; const MachineOperand & MO2 = MI . getOperand ( OpIdx ) ; unsigned AM3Opc = ( ImplicitRn == <STR_LIT> ) ? <NUM_LIT> : MI . getOperand ( OpIdx + <NUM_LIT> ) . getImm ( ) ; Binary |= ( ( <STR_LIT> ( AM3Opc ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <STR_LIT> ) ; if ( MO2 . getReg ( ) ) { Binary |= <ISA_LIT>RegisterInfo :: getRegisterNumbering ( MO2 . getReg ( ) ) ; emitWordLE ( Binary


<s> unsigned V2 = <STR_LIT> ( MO1 . getImm ( ) ) ; unsigned Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , MO0 ) << <STR_LIT> ; Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= getMachineSoImmOpValue ( V1 ) ; emitWordLE ( Binary ) ; Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , MO0 ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , MO0 ) << <STR_LIT> ; Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= getMachineSoImmOpValue ( V2 ) ; emitWordLE ( Binary


<s> void Emitter < CodeEmitter > :: emitMulFrmInstruction ( const MachineInstr & MI ) { const TargetInstrDesc & TID = MI . getDesc ( ) ; unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getAddrModeSBit ( MI , TID ) ; unsigned OpIdx = <NUM_LIT> ; if ( TID . getNumDefs ( ) == <NUM_LIT> ) Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI


<s> unsigned OpIdx = <NUM_LIT> ; if ( TID . getNumDefs ( ) == <NUM_LIT> ) Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( TID . getNumOperands ( ) > OpIdx && ! TID . OpInfo [ OpIdx ] . isPredicate ( ) && ! TID . OpInfo [ OpIdx ] . isOptionalDef ( ) ) Binary |= getMachineOpValue ( MI , OpIdx ) << <STR_LIT> ; emitWordLE ( Binary )


<s> void Emitter < CodeEmitter > :: emitPseudoInstruction ( const MachineInstr & MI ) { unsigned Opcode = MI . getDesc ( ) . Opcode ; switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case TargetInstrInfo :: INLINEASM : { if ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) [ <NUM_LIT> ] ) { llvm_report_error ( <STR_LIT> ) ; } break ; } case TargetInstrInfo :: DBG_LABEL : case TargetInstrInfo :: EH_LABEL : MCE . emitLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case TargetInstrInfo :: IMPLICIT_DEF : case TargetInstrInfo :: DECLARE : case <STR_LIT> : break ; case <STR_LIT> : emitConstPoolInstruction (


<s> const TargetInstrDesc & TID = MI . getDesc ( ) ; unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; assert ( ( Binary & <STR_LIT> ) == <NUM_LIT> && ( Binary & <STR_LIT> ) == <NUM_LIT> && ( Binary & <STR_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Binary |= encodeVFPRd ( MI , OpIdx ++ ) ; if ( TID . getOperandConstraint ( OpIdx , TOI ::


<s> unsigned OpIdx = <NUM_LIT> ; Binary |= encodeVFPRd ( MI , OpIdx ++ ) ; const MachineOperand & Base = MI . getOperand ( OpIdx ++ ) ; Binary |= getMachineOpValue ( MI , Base ) << <STR_LIT> ; if ( Base . isReg ( ) ) { const MachineOperand & Offset = MI . getOperand ( OpIdx ) ; if ( unsigned ImmOffs = <STR_LIT> ( Offset . getImm ( ) ) ) { if ( <STR_LIT> ( Offset . getImm ( ) ) == <STR_LIT> ) Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= ImmOffs ; emitWordLE ( Binary )


<s> const MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; Binary |= getAddrModeUPBits ( <STR_LIT> ( MO . getImm ( ) ) ) ; if ( <STR_LIT> ( MO . getImm ( ) ) ) Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= encodeVFPRd ( MI , <NUM_LIT> ) ; unsigned NumRegs = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isImplicit ( )


<s> const MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; Binary |= getAddrModeUPBits ( <STR_LIT> ( MO . getImm ( ) ) ) ; if ( <STR_LIT> ( MO . getImm ( ) ) ) Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= encodeVFPRd ( MI , <NUM_LIT> ) ; unsigned NumRegs = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i !=


<s> DOUT << <STR_LIT> << std :: hex << std :: setw ( <NUM_LIT> ) <<

std :: setfill ( '0' ) << Binary << std :: dec << <STR_LIT> ;


<s> unsigned Emitter < CodeEmitter > :: getMachineSoImmOpValue ( unsigned SoImm ) { int SoImmVal = <STR_LIT> ( SoImm ) ; assert ( SoImmVal != - <NUM_LIT> && <STR_LIT> ) ; unsigned Binary = ( <STR_LIT> ( ( unsigned ) SoImmVal ) >> <NUM_LIT> ) << <STR_LIT> ; Binary |= <STR_LIT> ( ( unsigned ) SoImmVal ) ; return


<s> unsigned Binary = getMachineOpValue ( MI , MO ) ; const MachineOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; const MachineOperand & MO2 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; <STR_LIT> SOpc = <STR_LIT> ( MO2 . getImm ( ) ) ; unsigned SBits = <NUM_LIT> ; unsigned Rs = MO1 . getReg ( ) ; if ( Rs ) { switch ( SOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; } } else { switch ( SOpc ) { default : llvm_unreachable ( <STR_LIT> )


<s> switch ( <STR_LIT> ( Imm ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; } return


<s> unsigned Emitter < CodeEmitter > :: getShiftOp ( unsigned Imm ) const { switch ( <STR_LIT> ( Imm ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; } return <NUM_LIT>


<s> if ( MCID . Opcode == <STR_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } unsigned Binary = getBinaryCodeForInstr (


<s> } ) ; if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( CV ) ) { emitGlobalAddress ( GV , <STR_LIT> , isa < Function > ( GV ) , false ) ; emitWordLE ( <NUM_LIT> ) ; } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( CV ) ) { uint32_t Val = uint32_t ( * CI -> getValue ( ) . getRawData ( ) ) ; emitWordLE ( Val ) ; } else if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( CV ) ) { if ( CFP -> getType ( ) -> isFloatTy ( ) ) emitWordLE ( CFP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ) ; else if ( CFP -> getType ( ) -> isDoubleTy ( ) ) emitDWordLE ( CFP -> getValueAPF ( ) . bitcastToAPInt


<s> } else { const Constant * CV = MCPE . Val . ConstVal ; DEBUG ( { errs ( ) << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> ; if ( const Function * F = dyn_cast < Function > ( CV ) ) errs ( ) << F -> getName ( ) ; else errs ( ) << * CV ; errs ( ) << '\n' ; } ) ; if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( CV ) ) { emitGlobalAddress ( GV , <STR_LIT> , isa < Function > ( GV ) , false ) ; emitWordLE ( <NUM_LIT> ) ; } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( CV ) ) { uint32_t Val = uint32_t ( * CI ->


<s> unsigned OpIdx = <NUM_LIT> ; if ( NumDefs ) Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; else if ( ImplicitRd ) Binary |= ( get<ISA_LIT>RegisterNumbering ( ImplicitRd ) << <STR_LIT> ) ; if ( MCID . Opcode == <STR_LIT> ) { unsigned Lo16 = getMovi32Value ( MI , MI . getOperand ( OpIdx ) , <STR_LIT> ) ; Binary |= Lo16 & <NUM_LIT> ; Binary |= ( ( Lo16 >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( MCID . Opcode == <STR_LIT> ) { unsigned Hi16 = ( getMovi32Value ( MI , MI . getOperand ( OpIdx ) , <STR_LIT> ) >> <NUM_LIT> ) ; Binary |= Hi16 & <NUM_LIT> ; Binary |= ( ( Hi16 >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( ( MCID . Opcode == <STR_LIT> ) || ( MCID . Opcode == <STR_LIT> ) ) { uint32_t v = ~ MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int32_t lsb = CountTrailingZeros_32 ( v ) ; int32_t msb = ( <NUM_LIT> - CountLeadingZeros_32 ( v ) ) - <NUM_LIT> ; Binary |= ( msb & <NUM_LIT> ) << <NUM_LIT> ; Binary |= ( lsb & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( ( MCID . Opcode == <STR_LIT> ) || ( MCID . Opcode == <STR_LIT> ) ) { Binary |= getMachineOpValue ( MI , OpIdx ++ ) ; uint32_t lsb = MI . getOperand ( OpIdx ++ ) . getImm ( ) ; uint32_t widthm1 = MI . getOperand ( OpIdx ++ ) . getImm ( ) - <NUM_LIT> ; Binary |= ( widthm1 & <NUM_LIT> ) << <NUM_LIT> ; Binary |= ( lsb & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } if ( MCID . getOperandConstraint ( OpIdx , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; bool isUnary = MCID . TSFlags & <STR_LIT> ; if ( ! isUnary ) { if ( ImplicitRn ) Binary |= ( get<ISA_LIT>RegisterNumbering ( ImplicitRn ) << <STR_LIT> ) ; else { Binary |= getMachineOpValue ( MI , OpIdx ) << <STR_LIT> ; ++ OpIdx


<s> } case <STR_LIT> : if ( MI . getOpcode ( ) == <STR_LIT> ) { emitLEApcrelJTInstruction ( MI ) ; break ; } llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : emitPseudoInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitDataProcessingInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitLoadStoreInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitMiscLoadStoreInstruction ( MI ) ; break ; case <STR_LIT> : emitLoadStoreMultipleInstruction ( MI ) ; break ; case <STR_LIT> : emitMulFrmInstruction ( MI ) ; break ; case <STR_LIT> : emitExtendInstruction ( MI ) ; break ; case <STR_LIT> : emitMiscArithInstruction ( MI ) ; break ; case <STR_LIT> : emitSaturateInstruction ( MI ) ; break ; case <STR_LIT> : emitBranchInstruction ( MI ) ; break ; case <STR_LIT> : emitMiscBranchInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitVFPArithInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : emitVFPConversionInstruction ( MI ) ; break ; case <STR_LIT>


<s> void <ISA_LIT>CodeEmitter :: emitLEApcrelJTInstruction ( const MachineInstr & MI ) { const MCInstrDesc & MCID = MI . getDesc ( ) ; unsigned Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getAddrModeSBit ( MI , MCID ) ; Binary |= getMachineOpValue ( MI , <NUM_LIT> ) << <STR_LIT> ; Binary |= get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) << <STR_LIT> ; Binary |= <NUM_LIT> <<


<s> void <ISA_LIT>CodeEmitter :: emitLEApcrelJTInstruction ( const MachineInstr & MI ) { const MCInstrDesc & MCID = MI . getDesc ( ) ; unsigned Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getAddrModeSBit ( MI , MCID ) ; Binary |= getMachineOpValue ( MI


<s> const MCInstrDesc & MCID = MI . getDesc ( ) ; bool IsUpdating = ( MCID . TSFlags & <STR_LIT> ) != <NUM_LIT> ; unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; if ( IsUpdating ) ++ OpIdx ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; <STR_LIT> Mode = <STR_LIT> ( MI . getOpcode ( ) ) ; Binary |= getAddrModeUPBits ( <STR_LIT> ( Mode ) ) ; if ( IsUpdating ) Binary |= <NUM_LIT> << <STR_LIT> ; for ( unsigned i = OpIdx + <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isImplicit ( ) ) break ; unsigned RegNum = get<ISA_LIT>RegisterNumbering ( MO . getReg


<s> if ( MCID . Opcode == <STR_LIT> || MCID . Opcode == <STR_LIT> ) ++ OpIdx ; if ( ImplicitRn ) Binary |= ( get<ISA_LIT>RegisterNumbering ( ImplicitRn ) << <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ! Skipped && MCID . getOperandConstraint ( OpIdx , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; const MachineOperand & MO2 = MI . getOperand ( OpIdx ) ; unsigned AM3Opc = ( ImplicitRn == <STR_LIT> ) ? <NUM_LIT> : MI . getOperand ( OpIdx + <NUM_LIT> ) . getImm ( ) ; Binary |= ( ( <STR_LIT> ( AM3Opc ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <STR_LIT> ) ; if ( MO2 . getReg ( ) ) { Binary |= get<ISA_LIT>RegisterNumbering ( MO2 . getReg ( ) ) ; emitWordLE ( Binary ) ; return ; } Binary |= <NUM_LIT> << <STR_LIT> ; if ( unsigned ImmOffs =


<s> Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; assert ( ( Binary & <STR_LIT> ) == <NUM_LIT> && ( Binary & <STR_LIT> ) == <NUM_LIT> && ( Binary & <STR_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Binary |= encodeVFPRd ( MI , OpIdx ++ ) ; if ( MCID . getOperandConstraint ( OpIdx , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; if ( ( MCID . TSFlags & <STR_LIT> ) == <STR_LIT> ) Binary |= encodeVFPRn ( MI , OpIdx ++ ) ; if ( OpIdx == MCID . getNumOperands ( ) || MCID . OpInfo [ OpIdx ] . isPredicate ( ) || MCID . OpInfo [ OpIdx ] . isOptionalDef ( ) ) { emitWordLE ( Binary )


<s> unsigned getHiLo16ImmOpValue ( const MachineInstr & MI , unsigned Op ) const { return <NUM_LIT>


<s> unsigned getHiLo16ImmOpValue ( const MachineInstr & MI ,


<s> if ( MO . isReg ( ) ) return get<ISA_LIT>RegisterNumbering ( MO . getReg ( ) ) ; else if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; else if ( MO . isGlobal ( ) ) emitGlobalAddress ( MO . getGlobal ( ) , <STR_LIT> , true , false ) ; else if ( MO . isSymbol ( ) ) emitExternalSymbolAddress ( MO . getSymbolName ( ) , <STR_LIT> ) ; else if ( MO . isCPI ( ) ) { const MCInstrDesc & MCID = MI


<s> case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; } } else { switch ( SOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; } } Binary |= SBits << <NUM_LIT> ; if ( SOpc == <STR_LIT> ) return Binary ; if ( Rs ) { assert ( <STR_LIT> ( MO2 . getImm ( ) ) == <NUM_LIT> ) ; return Binary | ( get<ISA_LIT>RegisterNumbering ( Rs ) << <STR_LIT>


<s> bool <ISA_LIT>CodeEmitter :: runOnMachineFunction ( MachineFunction & MF ) { assert ( ( MF . getTarget ( ) . getRelocationModel ( ) != Reloc :: Default || MF . getTarget ( ) . getRelocationModel ( ) != Reloc :: Static ) && <STR_LIT> ) ; JTI = ( ( <ISA_LIT>BaseTargetMachine & ) MF . getTarget ( ) ) . getJITInfo ( ) ; II = ( const <ISA_LIT>BaseInstrInfo * ) MF . getTarget ( ) . getInstrInfo ( ) ; TD = MF . getTarget ( ) . getTargetData ( ) ; Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MCPEs = & MF . getConstantPool ( ) -> getConstants ( ) ; MJTEs = <NUM_LIT> ; if ( MF . getJumpTableInfo ( ) ) MJTEs = & MF . getJumpTableInfo ( ) -> getJumpTables ( ) ; IsPIC = TM . getRelocationModel ( ) == Reloc :: PIC_ ; IsThumb = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) ; JTI -> Initialize ( MF , IsPIC ) ; MMI = & getAnalysis < MachineModuleInfo > ( ) ; MCE . setModuleInfo ( MMI ) ; do { DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF )


<s> Skipped = true ; } if ( ImplicitRd ) Binary |= ( II -> getRegisterInfo ( ) . getEncodingValue ( ImplicitRd ) << <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ImplicitRn ) Binary |= ( II -> getRegisterInfo ( ) . getEncodingValue ( ImplicitRn ) << <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ! Skipped && MCID . getOperandConstraint ( OpIdx , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; const MachineOperand & MO2 = MI . getOperand ( OpIdx ) ; unsigned AM2Opc = ( ImplicitRn == <STR_LIT> ) ? <NUM_LIT> : MI . getOperand ( OpIdx + <NUM_LIT> ) . getImm ( ) ; Binary |= ( ( <STR_LIT> ( AM2Opc ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <STR_LIT> ) ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( AM2Opc ) ) Binary |=


<s> const MCInstrDesc & MCID = MI . getDesc ( ) ; bool IsUpdating = ( MCID . TSFlags & <STR_LIT> ) != <NUM_LIT> ; unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; if ( IsUpdating ) ++ OpIdx ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; <STR_LIT> Mode = <STR_LIT> ( MI . getOpcode ( ) ) ; Binary |= getAddrModeUPBits ( <STR_LIT> ( Mode ) ) ; if ( IsUpdating ) Binary |= <NUM_LIT> << <STR_LIT> ; for ( unsigned i = OpIdx + <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isImplicit ( ) ) break ; unsigned RegNum = II -> getRegisterInfo ( ) . getEncodingValue ( MO . getReg ( ) ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) && RegNum < <NUM_LIT> ) ; Binary |= <NUM_LIT>


<s> void <ISA_LIT>CodeEmitter :: emitLoadStoreMultipleInstruction ( const MachineInstr & MI ) { const MCInstrDesc & MCID = MI . getDesc ( ) ; bool IsUpdating = ( MCID . TSFlags & <STR_LIT> ) != <NUM_LIT> ; unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; if ( IsUpdating ) ++ OpIdx ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; <STR_LIT> Mode = <STR_LIT> ( MI .


<s> bool isSPVFP = <STR_LIT> . contains ( RegD ) ; RegD = II -> getRegisterInfo ( ) . getEncodingValue ( RegD ) ; if ( ! isSPVFP ) Binary |= RegD


<s> unsigned <ISA_LIT>CodeEmitter :: encodeVFPRm ( const MachineInstr & MI , unsigned OpIdx ) const { unsigned RegM = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary = <NUM_LIT> ; bool isSPVFP = <STR_LIT> . contains ( RegM ) ; RegM = II -> getRegisterInfo (


<s> unsigned RegN = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary = <NUM_LIT> ; bool isSPVFP = <STR_LIT> . contains ( RegN ) ; RegN = II -> getRegisterInfo ( ) . getEncodingValue ( RegN ) ; if ( ! isSPVFP ) Binary |= RegN << <STR_LIT> ; else { Binary |= ( ( RegN & <NUM_LIT> ) >> <NUM_LIT> ) << <STR_LIT> ; Binary |= ( RegN & <NUM_LIT> ) << <STR_LIT> ; } return Binary


<s> emitConstPoolAddress ( MO . getIndex ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } unsigned Reg = II -> getRegisterInfo ( ) . getEncodingValue ( MO . getReg ( ) ) ; int32_t Imm12 = MO1 . getImm ( ) ; if ( Imm12 == INT32_MIN ) Imm12 = <NUM_LIT> ; bool isAdd = true ; if ( Imm12 < <NUM_LIT> ) { Imm12 =


<s> if ( ! MO . isReg ( ) ) { emitConstPoolAddress ( MO . getIndex ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } unsigned Reg = II -> getRegisterInfo ( ) . getEncodingValue ( MO . getReg ( ) ) ; int32_t Imm12 = MO1 . getImm ( ) ; if ( Imm12 == INT32_MIN ) Imm12 = <NUM_LIT> ; bool isAdd = true ; if ( Imm12 < <NUM_LIT> ) { Imm12 = - Imm12


<s> unsigned <ISA_LIT>CodeEmitter :: getMachineOpValue ( const MachineInstr & MI , const MachineOperand & MO ) const { if ( MO . isReg ( ) ) return II -> getRegisterInfo ( ) . getEncodingValue ( MO . getReg ( ) ) ; else if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; else if ( MO . isGlobal ( ) ) emitGlobalAddress ( MO . getGlobal ( )


<s> if ( MO . isReg ( ) ) return II -> getRegisterInfo ( ) . getEncodingValue ( MO . getReg ( ) ) ; else if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; else if ( MO . isGlobal ( ) ) emitGlobalAddress ( MO . getGlobal ( ) , <STR_LIT> , true , false ) ; else if ( MO . isSymbol ( ) ) emitExternalSymbolAddress ( MO . getSymbolName ( ) , <STR_LIT> ) ; else if ( MO . isCPI ( ) ) { const MCInstrDesc & MCID = MI . getDesc ( ) ; unsigned Reloc = ( ( MCID . TSFlags & <STR_LIT> ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; emitConstPoolAddress ( MO . getIndex ( ) , Reloc ) ; } else if ( MO . isJTI ( ) ) emitJumpTableAddress ( MO . getIndex ( ) , <STR_LIT> ) ; else if ( MO . isMBB ( ) ) emitMachineBasicBlock ( MO . getMBB ( ) , <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT>


<s> JTI = ( ( <ISA_LIT>BaseTargetMachine & ) MF . getTarget ( ) ) . getJITInfo ( ) ; II = ( const <ISA_LIT>BaseInstrInfo * ) MF . getTarget ( ) . getInstrInfo ( ) ; TD = MF . getTarget ( ) . getTargetData ( ) ; Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MCPEs = & MF . getConstantPool ( ) -> getConstants ( ) ; MJTEs = <NUM_LIT> ; if ( MF . getJumpTableInfo ( ) ) MJTEs = &

MF . getJumpTableInfo ( ) -> getJumpTables ( ) ;


<s> return ; } else if ( MCID . Opcode == <STR_LIT> ) { unsigned Hi16 = ( getMovi32Value ( MI , MI . getOperand ( OpIdx ) , <STR_LIT> ) >> <NUM_LIT> ) ; Binary |= Hi16 & <NUM_LIT> ; Binary |= ( ( Hi16 >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( ( MCID . Opcode == <STR_LIT> ) || ( MCID . Opcode == <STR_LIT> ) ) { uint32_t v = ~ MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int32_t lsb = countTrailingZeros ( v ) ; int32_t msb = ( <NUM_LIT> - countLeadingZeros ( v ) ) - <NUM_LIT> ; Binary |= ( msb & <NUM_LIT> ) << <NUM_LIT> ; Binary |= ( lsb & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( ( MCID . Opcode == <STR_LIT> ) || ( MCID . Opcode == <STR_LIT> ) ) { Binary |= getMachineOpValue ( MI , OpIdx ++ ) ; uint32_t lsb = MI . getOperand ( OpIdx ++ ) . getImm ( ) ; uint32_t widthm1 = MI . getOperand ( OpIdx ++ ) . getImm ( ) - <NUM_LIT> ; Binary |= ( widthm1 & <NUM_LIT> ) << <NUM_LIT> ; Binary |= ( lsb & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } if ( MCID . getOperandConstraint ( OpIdx , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; bool isUnary = MCID . TSFlags & <STR_LIT> ; if ( ! isUnary ) { if ( ImplicitRn ) Binary |= ( II -> getRegisterInfo ( ) . getEncodingValue ( ImplicitRn ) << <STR_LIT> ) ; else { Binary |= getMachineOpValue ( MI , OpIdx ) << <STR_LIT> ; ++ OpIdx ; } } const MachineOperand & MO = MI . getOperand ( OpIdx ) ; if ( ( MCID . TSFlags & <STR_LIT> ) == <STR_LIT> ) { emitWordLE ( Binary | getMachineSoRegOpValue ( MI , MCID


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineModuleInfo > (


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> MJTEs = nullptr ; if ( MF . getJumpTableInfo ( ) ) MJTEs = & MF . getJumpTableInfo ( ) -> getJumpTables ( ) ; IsPIC = TM . getRelocationModel ( ) == Reloc :: PIC_ ; IsThumb = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) ; JTI -> Initialize ( MF , IsPIC ) ; MMI = & getAnalysis < MachineModuleInfo > ( ) ; MCE . setModuleInfo ( MMI ) ; do { DEBUG ( errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF


<s> II = ( const <ISA_LIT>BaseInstrInfo * ) MF . getTarget ( ) . getInstrInfo ( ) ; TD = MF . getTarget ( ) . getDataLayout ( ) ; Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MCPEs = & MF . getConstantPool ( ) -> getConstants ( ) ; MJTEs = <NUM_LIT> ; if ( MF . getJumpTableInfo ( ) ) MJTEs = & MF . getJumpTableInfo ( ) -> getJumpTables ( ) ; IsPIC = TM . getRelocationModel ( ) == Reloc :: PIC_ ; IsThumb = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) ; JTI -> Initialize ( MF , IsPIC ) ; MMI = & getAnalysis < MachineModuleInfo > ( ) ; MCE . setModuleInfo ( MMI ) ; do { DEBUG ( errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB ) { MCE . StartMachineBasicBlock ( MBB ) ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I


<s> MachineRelocation MR = Indirect ? MachineRelocation :: getIndirectSymbol ( MCE . getCurrentPCOffset ( ) , Reloc , GV , ACPV , MayNeedFarStub ) : MachineRelocation :: getGV ( MCE . getCurrentPCOffset ( ) , Reloc , GV , ACPV , MayNeedFarStub ) ; MCE . addRelocation ( MR )


<s> if ( ImplicitRd ) Binary |= ( <ISA_LIT>RegisterInfo :: getRegisterNumbering ( ImplicitRd ) << <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ImplicitRn ) Binary |= ( <ISA_LIT>RegisterInfo :: getRegisterNumbering ( ImplicitRn ) << <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ! Skipped && TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; const MachineOperand & MO2 = MI . getOperand ( OpIdx ) ; unsigned AM2Opc = ( ImplicitRn == <STR_LIT> ) ? <NUM_LIT> : MI . getOperand


<s> Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , <NUM_LIT> ) << <STR_LIT> ; const MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; Binary |= getAddrModeUPBits ( <STR_LIT> ( MO . getImm ( ) ) ) ; if ( <STR_LIT> ( MO . getImm ( ) ) ) Binary |= <NUM_LIT> << <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isImplicit ( ) ) break ; unsigned RegNum = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( MO . getReg ( ) ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) && RegNum < <NUM_LIT> ) ; Binary |= <NUM_LIT> <<


<s> void <ISA_LIT>CodeEmitter :: emitMOVi2piecesInstruction ( const MachineInstr & MI ) { const MachineOperand & MO0 = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & MO1 = MI . getOperand ( <NUM_LIT> ) ; assert ( MO1 . isImm ( ) && <STR_LIT> ( MO1 . isImm ( ) ) != - <NUM_LIT> && <STR_LIT> ) ; unsigned V1 = <STR_LIT> ( MO1 . getImm ( ) ) ; unsigned V2 = <STR_LIT> ( MO1 . getImm ( ) ) ; unsigned Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , MO0 ) << <STR_LIT> ; Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= getMachineSoImmOpValue ( V1 ) ; emitWordLE ( Binary ) ; Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , MO0 ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , MO0 ) << <STR_LIT> ; Binary |= <NUM_LIT> << <STR_LIT>


<s> break ; case <STR_LIT> : { addPCLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; emitDataProcessingInstruction ( MI , <NUM_LIT> , <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { addPCLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; emitLoadStoreInstruction ( MI , <NUM_LIT> , <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { addPCLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; emitMiscLoadStoreInstruction ( MI , <STR_LIT> ) ; break ; } case <STR_LIT> : emitMOVi2piecesInstruction ( MI