<s> if ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) || ! N -> getValueType ( <NUM_LIT> ) . isSimple ( ) || ( OpOpcode != <STR_LIT> && OpOpcode != <STR_LIT> ) ) return SDValue ( ) ; SDValue ConstVec = N -> getOperand ( <NUM_LIT> ) ; if ( ! isa < BuildVectorSDNode > ( ConstVec ) ) return SDValue ( ) ; MVT FloatTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; uint32_t FloatBits = FloatTy . getSizeInBits ( ) ; MVT IntTy = Op . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getVectorElementType ( ) ; uint32_t IntBits = IntTy . getSizeInBits ( ) ; unsigned NumLanes = Op . getValueType ( ) . getVectorNumElements ( ) ; if ( FloatBits != <NUM_LIT> || IntBits > <NUM_LIT> || NumLanes > <NUM_LIT> ) { return SDValue ( ) ; } BitVector UndefElements


<s> LoadSDNode * LD = dyn_cast < LoadSDNode > ( Op . getNode ( ) ) ; if ( LD && Op . hasOneUse ( ) && LD -> isUnindexed ( ) && LD -> getMemoryVT ( ) == N -> getValueType ( <NUM_LIT> ) . getVectorElementType ( ) ) { SDValue Ops [ ] = { LD -> getOperand ( <NUM_LIT> ) , LD -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( LD -> getAlignment ( ) , SDLoc ( N ) , <STR_LIT> ) } ; SDVTList SDTys = DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue VLDDup = DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , SDTys , Ops , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , VLDDup . getValue ( <NUM_LIT> ) ) ; return VLDDup ; } return SDValue (


<s> while ( Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getOpcode ( ) != <STR_LIT> && Op . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned EltSize = Op . getScalarValueSizeInBits ( ) ; unsigned Imm = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned EltBits ; if ( <STR_LIT> ( Imm , EltBits


<s> SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue NewLD2 = DAG . getLoad ( <STR_LIT> , DL , NewLD1 . getValue ( <NUM_LIT> ) , OffsetPtr , LD -> getPointerInfo ( ) , std :: min ( <NUM_LIT> , LD -> getAlignment ( ) / <NUM_LIT> ) , LD -> getMemOperand ( ) -> getFlags ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , NewLD2 . getValue ( <NUM_LIT> ) ) ; if ( DCI . DAG . getDataLayout ( ) . isBigEndian ( ) ) std :: swap ( NewLD1 , NewLD2 ) ; SDValue Result = DCI . CombineTo ( N , NewLD1 , NewLD2 ) ; return


<s> Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; return ; case <STR_LIT> : ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ; return ; case <STR_LIT> : case <STR_LIT> : assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; return ExpandDIV_Windows ( SDValue ( N , <NUM_LIT> ) , DAG , N -> getOpcode ( ) == <STR_LIT> , Results ) ; case <STR_LIT> : ReplaceCMP_SWAP_64Results ( N , Results , DAG ) ; return ; case <STR_LIT> : return ReplaceLongIntrinsic ( N , Results , DAG ) ; } if ( Res . getNode ( )


<s> unsigned PCAdj = ( isThumb || isThumb2 ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolMBB :: Create ( F . getContext ( ) , DispatchBB , PCLabelId , PCAdj ) ; unsigned CPI = MCP -> getConstantPoolIndex ( CPV , <NUM_LIT> ) ; const TargetRegisterClass * TRC = isThumb ? & <STR_LIT> : & <STR_LIT> ; MachineMemOperand * CPMMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( * MF ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; MachineMemOperand * FIMMOSt = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; if ( isThumb2 ) { unsigned NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addMemOperand ( CPMMO ) . add ( predOps ( <STR_LIT> ) ) ; unsigned NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; unsigned NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( NewVReg2 , RegState :: Kill ) . addImm ( PCLabelId ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( NewVReg3 , RegState :: Kill ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( FIMMOSt ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( isThumb ) { unsigned NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI )


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; bool hasAtomicRMW = ! Subtarget -> isThumb ( ) || Subtarget -> hasV8MBaselineOps ( ) ; return ( Size <= ( Subtarget -> isMClass ( ) ? <NUM_LIT> : <NUM_LIT> ) && hasAtomicRMW ) ? AtomicExpansionKind


<s> bool <ISA_LIT>TargetLowering :: shouldFoldShiftPairToMask ( const SDNode *


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FrameIndex = StoreByValRegs ( CCInfo , DAG , dl , Chain , nullptr , CCInfo . getInRegsParamsCount ( ) , CCInfo . getNextStackOffset ( ) , <NUM_LIT> ) ; AFI -> setVarArgsFrameIndex (


<s> Register DestPhiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register CurrDestReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , DestPhiReg ) . addUse ( OpDestReg ) . addMBB ( TpEntry ) . addUse ( CurrDestReg ) . addMBB ( TpLoopBody ) ; Register LoopCounterPhiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register RemainingLoopIterationsReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , LoopCounterPhiReg ) . addUse ( TotalIterationsReg ) . addMBB ( TpEntry ) . addUse ( RemainingLoopIterationsReg ) . addMBB ( TpLoopBody ) ; Register PredCounterPhiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register RemainingElementsReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , PredCounterPhiReg ) . addUse ( ElementCountReg ) . addMBB ( TpEntry ) . addUse ( RemainingElementsReg ) . addMBB ( TpLoopBody ) ; Register VccrReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , VccrReg ) . addUse ( PredCounterPhiReg ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , RemainingElementsReg ) . addUse ( PredCounterPhiReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . addReg ( <NUM_LIT> ) ; Register SrcValueReg ; if ( IsMemcpy ) { SrcValueReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) ) . addDef ( CurrSrcReg ) . addDef ( SrcValueReg ) . addReg ( SrcPhiReg ) . addImm ( <NUM_LIT> )

. addImm ( <STR_LIT> ) . addUse ( VccrReg ) ;


<s> } Register DestPhiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register CurrDestReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , DestPhiReg ) . addUse ( OpDestReg ) . addMBB ( TpEntry ) . addUse ( CurrDestReg ) . addMBB ( TpLoopBody ) ; Register LoopCounterPhiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register RemainingLoopIterationsReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , LoopCounterPhiReg ) . addUse ( TotalIterationsReg ) . addMBB ( TpEntry ) . addUse ( RemainingLoopIterationsReg ) . addMBB ( TpLoopBody ) ; Register PredCounterPhiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register RemainingElementsReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , PredCounterPhiReg ) . addUse ( ElementCountReg ) . addMBB ( TpEntry ) . addUse ( RemainingElementsReg ) . addMBB ( TpLoopBody ) ; Register VccrReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , VccrReg ) . addUse ( PredCounterPhiReg ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , RemainingElementsReg ) . addUse ( PredCounterPhiReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . addReg ( <NUM_LIT> ) ; Register SrcValueReg ; if ( IsMemcpy ) { SrcValueReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) ) . addDef ( CurrSrcReg ) . addDef ( SrcValueReg ) . addReg ( SrcPhiReg )

. addImm ( <NUM_LIT> ) . addImm ( <STR_LIT> ) . addUse ( VccrReg ) ;


<s> else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> && ( Subtarget -> hasNEON ( ) || isLegalMVEShuffleOp ( PFEntry ) ) ) return true ; } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; if ( EltSize >= <NUM_LIT> || ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || ShuffleVectorInst :: isIdentityMask ( M ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF


<s> else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> && ( Subtarget -> hasNEON ( ) || isLegalMVEShuffleOp ( PFEntry ) ) ) return true ; } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; if ( EltSize >= <NUM_LIT> || ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || ShuffleVectorInst :: isIdentityMask ( M ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask


<s> case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op ,


<s> for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ; else PFIndexes [ i ] = ShuffleMask [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> ) { if ( ST -> hasNEON ( ) ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; else if ( isLegalMVEShuffleOp ( PFEntry ) ) { unsigned LHSID = ( PFEntry >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned RHSID = ( PFEntry >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned PFEntryLHS = PerfectShuffleTable [ LHSID ] ; unsigned PFEntryRHS = PerfectShuffleTable [ RHSID ] ; if ( isLegalMVEShuffleOp ( PFEntryLHS ) && isLegalMVEShuffleOp ( PFEntryRHS ) ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; } } } if ( EltSize >= <NUM_LIT> ) { EVT EltVT = EVT :: getFloatingPointVT ( EltSize ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumElts ) ; V1 = DAG . getNode ( <STR_LIT> , dl , VecVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , VecVT , V2 ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) Ops . push_back ( DAG . getUNDEF ( EltVT ) ) ; else Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , ShuffleMask [ i ] < ( int ) NumElts ? V1 : V2 , DAG . getConstant ( ShuffleMask [ i ] & ( NumElts - <NUM_LIT> ) , dl , <STR_LIT> ) ) ) ; } SDValue Val = DAG . getNode ( <STR_LIT> , dl , VecVT , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Val ) ; } if ( ST -> hasNEON ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) && isReverseMask ( ShuffleMask , VT ) ) return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16 ( Op , DAG ) ; if ( ST -> hasNEON ( ) && VT == <STR_LIT> ) if ( SDValue NewOp = LowerVECTOR_SHUFFLEv8i8 ( Op , ShuffleMask , DAG ) ) return NewOp ; if ( ST -> hasMVEIntegerOps ( ) ) if ( SDValue NewOp = LowerVECTOR_SHUFFLEUsingMovs ( Op ,


<s> return V -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( V -> getOperand ( <NUM_LIT> ) ) && V -> getConstantOperandVal ( <NUM_LIT> ) == Lane + <NUM_LIT> ; } ) ; if ( OtherIt == Op0 -> uses ( ) . end ( ) ) return SDValue ( ) ; SDValue OtherExt ( * OtherIt , <NUM_LIT> ) ; if ( OtherExt . getValueType ( ) != <STR_LIT> ) { if ( OtherExt -> use_size ( ) != <NUM_LIT> || OtherExt -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> || OtherExt -> use_begin ( ) -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; OtherExt = SDValue ( * OtherExt -> use_begin ( ) , <NUM_LIT> ) ; } SDValue F64 = DCI . DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DCI . DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 ) , DCI . DAG . getConstant ( Ext . getConstantOperandVal ( <NUM_LIT> ) / <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue VMOVRRD = DCI . DAG . getNode ( <STR_LIT> , dl


<s> static SDValue PerformHWLoopCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * ST ) { <STR_LIT> CC ; SDValue Cond ; int Imm = <NUM_LIT> ; bool Negate = false ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Dest ; if ( N -> getOpcode ( ) == <STR_LIT> ) { CC = <STR_LIT> ; Cond = N -> getOperand ( <NUM_LIT> ) ; Dest = N -> getOperand ( <NUM_LIT> ) ; } else { assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; CC = cast < CondCodeSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> get ( ) ; Cond = N -> getOperand ( <NUM_LIT> ) ; Dest = N -> getOperand ( <NUM_LIT> ) ; if ( auto * Const = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) { if ( ! Const -> isOne ( ) && ! Const -> isNullValue ( ) ) return SDValue ( ) ; Imm = Const -> getZExtValue ( ) ; } else return SDValue ( ) ; } SDValue Int = SearchLoopIntrinsic ( Cond , CC , Imm , Negate ) ; if ( ! Int ) return SDValue ( ) ; if ( Negate ) CC = <STR_LIT> ( CC , <STR_LIT> ) ; auto IsTrueIfZero = [ ] ( <STR_LIT> CC , int Imm ) { return ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) ; } ; auto IsFalseIfZero = [ ] ( <STR_LIT> CC , int Imm ) { return ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) ; } ; assert ( ( IsTrueIfZero ( CC , Imm ) || IsFalseIfZero ( CC , Imm ) ) && <STR_LIT> ) ; SDLoc dl ( Int ) ; SelectionDAG & DAG = DCI . DAG ; SDValue Elements = Int . getOperand ( <NUM_LIT>


<s> EVT VecVT = Ext0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ! VecVT . isPow2VectorType ( ) || VecVT . getVectorNumElements ( ) == <NUM_LIT> ) return SDValue ( ) ; if ( Ext1 . getOperand ( <NUM_LIT> ) . getValueType ( ) != VecVT || VecVT . getScalarType ( ) != ScalarType || VT . getScalarSizeInBits ( ) < ScalarType . getScalarSizeInBits ( ) * <NUM_LIT> ) return SDValue ( ) ; SDLoc DL ( Mul ) ; unsigned LegalLanes = <NUM_LIT> / ( ShftAmt + <NUM_LIT> ) ; EVT LegalVecVT = <STR_LIT> ( ScalarType , LegalLanes ) ; if ( VecVT . getSizeInBits ( ) < <NUM_LIT> ) { EVT ExtVecVT = <STR_LIT> ( <STR_LIT> ( <NUM_LIT> / VecVT . getVectorNumElements ( ) ) , VecVT . getVectorNumElements ( ) ) ; SDValue Inp0 = DAG . getNode ( <STR_LIT> , DL , ExtVecVT , Ext0 . getOperand ( <NUM_LIT> ) ) ; SDValue Inp1 = DAG . getNode ( <STR_LIT> , DL , ExtVecVT , Ext1 . getOperand ( <NUM_LIT> ) ) ; Inp0 = DAG . getNode ( <STR_LIT> , DL , LegalVecVT , Inp0 ) ; Inp1 = DAG . getNode ( <STR_LIT> , DL , LegalVecVT , Inp1 ) ; SDValue VQDMULH = DAG . getNode ( <STR_LIT> , DL , LegalVecVT , Inp0 , Inp1 ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , DL , ExtVecVT , VQDMULH ) ; Trunc = DAG . getNode ( <STR_LIT> , DL , VecVT , Trunc ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Trunc ) ; } assert ( VecVT . getSizeInBits ( ) % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; unsigned NumParts = VecVT . getSizeInBits ( ) / <NUM_LIT> ; SmallVector < SDValue > Parts ; for ( unsigned I = <NUM_LIT> ; I < NumParts ; ++ I ) { SDValue Inp0 = DAG . getNode ( <STR_LIT> , DL , LegalVecVT , Ext0 . getOperand ( <NUM_LIT> ) , DAG . getVectorIdxConstant ( I * LegalLanes , DL ) ) ; SDValue Inp1 = DAG . getNode ( <STR_LIT> , DL , LegalVecVT , Ext1 . getOperand ( <NUM_LIT> ) , DAG . getVectorIdxConstant ( I * LegalLanes , DL ) ) ; SDValue VQDMULH = DAG . getNode ( <STR_LIT> , DL , LegalVecVT , Inp0 , Inp1 ) ; Parts . push_back (


<s> void <ISA_LIT>TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { SDValue Res ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : ExpandREAD_REGISTER ( N , Results , DAG ) ; break ; case <STR_LIT> : Res = ExpandBITCAST ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Res = Expand64BitShift ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerREM ( N , DAG ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerDivRem ( SDValue ( N , <NUM_LIT> ) , DAG ) ; assert ( Res . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; return ; case <STR_LIT> : case


<s> assert ( Res . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Res = LowerADDSUBSAT ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ; break ; case <STR_LIT> : ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ; return ; case <STR_LIT> : case <STR_LIT> : assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; return ExpandDIV_Windows ( SDValue ( N , <NUM_LIT> ) , DAG , N -> getOpcode ( ) == <STR_LIT> , Results ) ; case <STR_LIT> : ReplaceCMP_SWAP_64Results ( N , Results , DAG ) ; return ; case <STR_LIT> : return ReplaceLongIntrinsic ( N , Results , DAG ) ; case <STR_LIT> : lowerABS ( N , Results , DAG ) ; return ; case <STR_LIT> : LowerLOAD ( N , Results ,


<s> Negate = ! Negate ; return SearchLoopIntrinsic ( N . getOperand ( <NUM_LIT> ) , CC , Imm , Negate ) ; } case <STR_LIT> : { auto * Const = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! Const ) return SDValue ( ) ; if ( Const -> isNullValue ( ) ) Imm = <NUM_LIT> ; else if ( Const -> isOne ( ) ) Imm = <NUM_LIT> ; else return SDValue ( ) ; CC = cast < CondCodeSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> get ( ) ; return SearchLoopIntrinsic ( N -> getOperand ( <NUM_LIT> ) , CC , Imm , Negate ) ; } case <STR_LIT> : { unsigned IntOp = cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( IntOp != <STR_LIT> && IntOp != <STR_LIT> )


<s> } ; auto IsFMS = [ & ] ( Instruction * I ) { if ( match ( I -> getOperand ( <NUM_LIT> ) , m_FNeg ( m_Value ( ) ) ) || match ( I -> getOperand ( <NUM_LIT> ) , m_FNeg ( m_Value ( ) ) ) ) return true ; return false ; } ; auto IsSinker = [ & ] ( Instruction * I , int Operand ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Add : case Instruction :: Mul : case Instruction :: FAdd : case Instruction :: ICmp : case Instruction :: FCmp : return true ; case Instruction :: FMul : return ! IsFMSMul ( I ) ; case Instruction :: Sub : case Instruction :: FSub : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return Operand == <NUM_LIT> ; case Instruction :: Call : if ( auto * II = dyn_cast < IntrinsicInst > ( I ) ) { switch ( II -> getIntrinsicID ( ) ) { case <STR_LIT> : return ! IsFMS ( I ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Operand == <NUM_LIT> ; default : return false ; } } return false ; default : return false ; } } ; for ( auto OpIdx : enumerate ( I -> operands ( ) ) ) { Instruction * Op = dyn_cast < Instruction > ( OpIdx . value ( ) . get ( ) ) ; if ( ! Op || any_of ( Ops , [ & ] ( Use * U ) { return U -> get ( ) == Op ; } ) ) continue ; Instruction * Shuffle = Op ; if ( Shuffle -> getOpcode ( ) == Instruction :: BitCast ) Shuffle = dyn_cast < Instruction > ( Shuffle -> getOperand ( <NUM_LIT> ) ) ; if ( ! Shuffle || ! match ( Shuffle , m_Shuffle ( m_InsertElt ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) continue ; if ( ! IsSinker ( I , OpIdx . index ( ) ) ) continue ; for ( Use & U : Op -> uses


<s> case <STR_LIT> : { if ( Op . getResNo ( ) == <NUM_LIT> && ! Op -> hasAnyUseOfValue ( <NUM_LIT> ) && isa < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ) { unsigned ShAmt = Op -> getConstantOperandVal ( <NUM_LIT> ) ; if ( ShAmt < <NUM_LIT> && OriginalDemandedBits . isSubsetOf ( APInt :: getAllOnesValue ( <NUM_LIT> ) << ( <NUM_LIT> - ShAmt ) ) ) return TLO . CombineTo ( Op , TLO . DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , TLO . DAG . getConstant ( <NUM_LIT> - ShAmt , SDLoc ( Op ) , <STR_LIT> ) ) ) ; } break ; } } return TargetLowering :: SimplifyDemandedBitsForTargetNode ( Op , OriginalDemandedBits ,

OriginalDemandedElts , Known , TLO , Depth ) ;


<s> unsigned <ISA_LIT>TargetLowering :: getABIAlignmentForCallingConv ( Type * ArgTy , DataLayout DL ) const { if ( ! ArgTy -> isVectorTy ( ) ) return DL . getABITypeAlignment ( ArgTy ) ; return std :: min ( DL . getABITypeAlignment ( ArgTy ) , ( unsigned ) DL .


<s> if ( Subtarget -> hasNEON ( ) ) return <NUM_LIT> ; return TargetLoweringBase :: getMaxSupportedInterleaveFactor (


<s> unsigned <ISA_LIT>TargetLowering :: getMaxSupportedInterleaveFactor ( ) const { if ( Subtarget -> hasNEON ( ) ) return <NUM_LIT> ; return TargetLoweringBase :: getMaxSupportedInterleaveFactor (


<s> bool isLegal = false ; if ( VT . isVector ( ) ) isLegal = Subtarget -> hasMVEIntegerOps ( ) && getMVEIndexedAddressParts ( Ptr . getNode ( ) , VT , Align , isSEXTLoad , Subtarget -> isLittle ( ) , Base , Offset , isInc , DAG ) ; else { if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = get<ISA_LIT>IndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; } if ( ! isLegal ) return false ; AM = isInc ? <STR_LIT> :


<s> SDValue Ptr ; unsigned Align ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Align = LD -> getAlignment ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Align = ST -> getAlignment ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( VT . isVector ( ) ) isLegal = Subtarget -> hasMVEIntegerOps ( ) && getMVEIndexedAddressParts ( Ptr . getNode ( ) , VT , Align , isSEXTLoad , Subtarget -> isLittle ( ) ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> virtual bool isSelectSupported ( SelectSupportKind Kind )


<s> SDValue Mask = N -> getMask ( ) ; SDValue PassThru = N -> getPassThru ( ) ; SDLoc dl ( Op ) ; auto IsZero = [ ] ( SDValue PassThru ) { return ( <STR_LIT> ( PassThru . getNode ( ) ) || ( PassThru -> getOpcode ( ) == <STR_LIT> && isNullConstant ( PassThru -> getOperand ( <NUM_LIT> ) ) ) ) ; } ; if ( IsZero ( PassThru ) ) return Op ; SDValue ZeroVec = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue NewLoad = DAG . getMaskedLoad ( VT , dl , N -> getChain ( ) , N -> getBasePtr ( ) , Mask , ZeroVec , N -> getMemoryVT ( ) , N -> getMemOperand ( ) , N -> getExtensionType ( ) , N -> isExpandingLoad ( ) ) ; SDValue Combo = NewLoad ; if ( ! PassThru . isUndef ( ) && ( PassThru . getOpcode ( ) != <STR_LIT> || ! IsZero ( PassThru -> getOperand ( <NUM_LIT> ) ) ) ) Combo = DAG . getNode ( <STR_LIT> , dl , VT , Mask , NewLoad , PassThru ) ; return DAG . getMergeValues ( { Combo , NewLoad . getValue ( <NUM_LIT> ) } , dl


<s> SDLoc dl ( Op ) ; auto IsZero = [ ] ( SDValue PassThru ) { return ( <STR_LIT> ( PassThru . getNode ( ) ) || ( PassThru -> getOpcode ( ) == <STR_LIT> && isNullConstant ( PassThru -> getOperand ( <NUM_LIT> ) ) ) ) ; } ; if ( IsZero ( PassThru ) ) return Op ; SDValue ZeroVec = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant


<s> case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT>


<s> if ( ST -> hasNEON ( ) ) { if ( unsigned ShuffleOpc = isNEONTwoResultShuffleMask ( ShuffleMask , VT , WhichResult , isV_UNDEF ) ) { if ( isV_UNDEF ) V2 = V1 ; return DAG . getNode ( ShuffleOpc , dl , DAG . getVTList ( VT , VT ) , V1 , V2 ) . getValue ( WhichResult ) ; } } if ( ST -> hasMVEIntegerOps ( ) ) { if ( isVMOVNMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V2 , V1 , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; if ( isVMOVNMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } if ( ST -> hasNEON ( ) && V1 -> getOpcode ( ) == <STR_LIT> && V2 -> isUndef ( ) ) { SDValue SubV1 = V1 -> getOperand ( <NUM_LIT> ) ; SDValue SubV2 = V1 -> getOperand ( <NUM_LIT> ) ; EVT SubVT = SubV1 . getValueType ( ) ; assert ( llvm :: all_of ( ShuffleMask , [ & ] ( int i ) { return i < ( int ) VT . getVectorNumElements ( ) ; } ) && <STR_LIT> ) ; if ( unsigned ShuffleOpc = isNEONTwoResultShuffleMask ( ShuffleMask , SubVT , WhichResult , isV_UNDEF ) ) { if ( isV_UNDEF ) SubV2 = SubV1 ; assert ( ( WhichResult == <NUM_LIT> ) && <STR_LIT> ) ; SDValue Res = DAG . getNode ( ShuffleOpc , dl , DAG . getVTList ( SubVT , SubVT ) , SubV1 , SubV2 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res . getValue ( <NUM_LIT> ) , Res . getValue ( <NUM_LIT> ) ) ; } } } unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == <NUM_LIT> ) { unsigned PFIndexes [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ; else PFIndexes [ i ] = ShuffleMask [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry


<s> if ( VT == <STR_LIT> && ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && TLI . isTypeLegal ( Vec . getValueType ( ) ) && isa < ConstantSDNode > ( Lane ) ) { unsigned Opc = <NUM_LIT> ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; break ; } return DAG . getNode ( Opc , SDLoc ( N ) , VT


<s> SDLoc Loc ( Op ) ; RTLIB :: Libcall LC ; MakeLibCallOptions CallOptions ; SDValue Chain = IsStrict ? Op . getOperand ( <NUM_LIT> ) : SDValue ( ) ; for ( unsigned Sz = SrcSz ; Sz <= <NUM_LIT> && Sz < DstSz ; Sz *= <NUM_LIT> ) { bool Supported = ( Sz == <NUM_LIT> ? Subtarget -> hasFP16 ( ) : Subtarget -> hasFP64 ( ) ) ; MVT SrcVT = ( Sz == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; MVT DstVT = ( Sz == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; if ( Supported ) { if ( IsStrict ) { SrcVal = DAG . getNode ( <STR_LIT> , Loc , { DstVT , <STR_LIT> } , { Chain , SrcVal } ) ; Chain = SrcVal . getValue ( <NUM_LIT>


<s> EVT VT = Op . getValueType ( ) ; if ( VT . isVector ( ) ) return LowerVectorFP_TO_INT ( Op , DAG ) ; bool IsStrict = Op -> isStrictFPOpcode ( ) ; SDValue SrcVal = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; if ( isUnsupportedFloatingType ( SrcVal . getValueType ( ) ) ) { RTLIB :: Libcall LC ; if ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( SrcVal . getValueType ( ) , Op . getValueType ( ) ) ; else LC = RTLIB :: getFPTOUINT ( SrcVal . getValueType ( ) , Op . getValueType ( ) ) ; SDLoc Loc ( Op ) ; MakeLibCallOptions CallOptions ; SDValue Chain = IsStrict ? Op . getOperand ( <NUM_LIT> ) : SDValue ( ) ; SDValue Result ; std :: tie ( Result , Chain ) = makeLibCall ( DAG , LC , Op . getValueType ( ) , SrcVal , CallOptions , Loc , Chain ) ; return IsStrict ? DAG . getMergeValues ( { Result , Chain } , Loc )


<s> DAG . getTargetLoweringInfo ( ) . softenSetCCOperands ( DAG , LHS . getValueType ( ) , LHS , RHS , CC , dl , LHS , RHS ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) == <STR_LIT> ) { if ( Subtarget -> hasFP<ISA_LIT>v8Base ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { CC = <STR_LIT> ( CC , LHS . getValueType ( ) ) ; std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; if ( cast < ConstantSDNode > ( <ISA_LIT>cc ) -> getZExtValue ( ) == <STR_LIT> ) <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; if ( Subtarget -> hasFP<ISA_LIT>v8Base ( ) && ! ( isFloatingPointZero ( RHS ) && TrueVal . getValueType ( ) != <STR_LIT> ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { bool swpCmpOps = false ; bool swpVselOps = false ; checkVSELConstraints ( CC , CondCode , swpCmpOps , swpVselOps ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { if ( swpCmpOps ) std :: swap ( LHS , RHS ) ; if ( swpVselOps ) std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode


<s> SDLoc dl ( Op ) ; SDValue SatValue ; uint64_t SatConstant ; bool SatUSat ; if ( ( ( ! Subtarget -> isThumb ( ) && Subtarget -> hasV6Ops ( ) ) || Subtarget -> isThumb2 ( ) ) && isSaturatingConditional ( Op , SatValue , SatConstant , SatUSat ) ) { if ( SatUSat ) return DAG . getNode ( <STR_LIT> , dl , VT , SatValue , DAG . getConstant ( countTrailingOnes ( SatConstant ) , dl , VT ) ) ; else return DAG . getNode ( <STR_LIT> , dl , VT , SatValue , DAG . getConstant ( countTrailingOnes ( SatConstant ) , dl , VT ) ) ; } SDValue LowerSatConstant ; if ( VT == <STR_LIT> && isLowerSaturatingConditional ( Op , SatValue , LowerSatConstant ) ) { SDValue ShiftV = DAG . getNode ( <STR_LIT> , dl , VT , SatValue , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; if ( isNullConstant ( LowerSatConstant ) ) { SDValue NotShiftV = DAG . getNode ( <STR_LIT> , dl , VT , ShiftV , DAG . getAllOnesConstant ( dl , VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , SatValue , NotShiftV ) ; } else if ( isAllOnesConstant ( LowerSatConstant ) ) return DAG . getNode ( <STR_LIT> , dl , VT , SatValue , ShiftV ) ; } SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; ConstantSDNode * CFVal = dyn_cast < ConstantSDNode > ( FalseVal ) ; ConstantSDNode * CTVal = dyn_cast < ConstantSDNode > ( TrueVal ) ; if ( Subtarget -> hasV8_1MMainlineOps ( ) && CFVal && CTVal && LHS . getValueType ( ) == <STR_LIT> && RHS . getValueType ( ) == <STR_LIT> ) { unsigned TVal = CTVal -> getZExtValue ( ) ; unsigned FVal = CFVal -> getZExtValue ( ) ; unsigned Opcode = <NUM_LIT> ; if ( TVal == ~ FVal ) { Opcode = <STR_LIT> ; } else if ( TVal == ~ FVal + <NUM_LIT> ) { Opcode = <STR_LIT> ; } else if ( TVal + <NUM_LIT> == FVal ) { Opcode = <STR_LIT> ; } else if ( TVal == FVal + <NUM_LIT> ) { Opcode = <STR_LIT> ; std :: swap ( TrueVal , FalseVal ) ; std :: swap ( TVal , FVal ) ; CC = <STR_LIT> ( CC , LHS . getValueType ( ) ) ; } if ( Opcode ) { if ( Opcode != <STR_LIT> && HasLowerConstantMaterializationCost ( FVal , TVal , Subtarget ) ) { std :: swap (


<s> } MVT ElemTy = VT . getVectorElementType ( ) ; if ( ElemTy != <STR_LIT> ) setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; if ( ElemTy == <STR_LIT> ) { setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } else { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; } setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; if ( VT . isInteger ( ) ) { setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> ,


<s> KnownBits KnownRHS = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; Known . Zero &= KnownRHS . Zero ; Known . One &= KnownRHS . One ; return ; } case <STR_LIT> : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : case <STR_LIT> : { EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } } case <STR_LIT> : { Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; ConstantSDNode * CI = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; const APInt & Mask = CI -> getAPIntValue ( ) ; Known . Zero &= Mask ; Known . One &= Mask ; return ; } case <STR_LIT> : case <STR_LIT> : { const SDValue & SrcSV = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = SrcSV . getValueType ( ) ; assert ( VecVT . isVector ( ) && <STR_LIT> ) ; const unsigned NumSrcElts = VecVT . getVectorNumElements ( ) ; ConstantSDNode * Pos = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; assert ( Pos -> getAPIntValue ( ) . ult ( NumSrcElts ) && <STR_LIT> ) ; unsigned Idx = Pos -> getZExtValue ( ) ; APInt DemandedElt = APInt :: getOneBitSet ( NumSrcElts , Idx ) ; Known = DAG . computeKnownBits ( SrcSV , DemandedElt , Depth + <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; const unsigned DstSz = VT


<s> const Align ABITypeAlign = DL . getABITypeAlign ( ArgTy ) ; if ( ! ArgTy -> isVectorTy ( ) ) return ABITypeAlign ; return std :: min ( ABITypeAlign ,


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { if ( ( Op . isMemcpy ( ) || Op . isZeroMemset ( ) ) && Subtarget ->

hasNEON ( ) && ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) {


<s> const GlobalValue * GV = G -> getGlobal ( ) ; const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } LLVMContext & C = * DAG . getContext ( ) ; if ( ! CCState :: resultsCompatible ( getEffectiveCallingConv ( CalleeCC , isVarArg ) , getEffectiveCallingConv ( CallerCC , CallerF . isVarArg ( ) ) , MF , C , Ins , CCAssignFnForReturn ( CalleeCC , isVarArg ) , CCAssignFnForReturn ( CallerCC , CallerF . isVarArg ( ) ) ) ) return false ; const <ISA_LIT>BaseRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( CalleeCC != CallerCC ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } const <ISA_LIT>FunctionInfo * AFI_Caller = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI_Caller -> getArgRegsSaveSize ( ) ) return false ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs ,


<s> bool <ISA_LIT>TargetLowering :: isLegalInterleavedAccessType ( unsigned Factor , FixedVectorType * VecTy , const DataLayout & DL ) const { unsigned VecSize = DL . getTypeSizeInBits ( VecTy ) ; unsigned ElSize = DL . getTypeSizeInBits ( VecTy -> getElementType ( ) ) ; if ( ! Subtarget -> hasNEON ( ) && ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; if ( Subtarget -> hasNEON ( ) && VecTy -> getElementType ( ) -> isHalfTy ( ) ) return false ; if ( Subtarget -> hasMVEIntegerOps ( ) && Factor == <NUM_LIT> ) return false ; if ( VecTy -> getNumElements ( ) < <NUM_LIT> )


<s> if ( ! isa < ConstantSDNode > ( K1 ) || ! isa < ConstantSDNode > ( K2 ) ) return false ; int64_t Val1 = cast < ConstantSDNode > ( K1 ) -> getSExtValue ( ) ; int64_t Val2 = cast < ConstantSDNode > ( K2 ) -> getSExtValue ( ) ; int64_t PosVal = std :: max ( Val1 , Val2 ) ; int64_t NegVal = std :: min ( Val1 , Val2 ) ; if ( ! ( ( Val1 > Val2 && isLTorLE ( CC1 ) ) || ( Val1 < Val2 && isLTorLE ( CC2 ) ) ) || ! isPowerOf2_64 ( PosVal + <NUM_LIT> ) ) return false ; if ( Val1 == ~ Val2 ) Usat = false ; else if ( NegVal == <NUM_LIT> ) Usat = true ; else return false ; V = V2Tmp ; K = ( uint64_t ) PosVal


<s> OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( type == OtherModImm ) return SDValue ( ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( type == MVEVMVNModImm ) return SDValue ( ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } return SDValue ( ) ; case <NUM_LIT> : { if ( type != VMOVModImm ) return SDValue ( ) ; uint64_t BitMask = <NUM_LIT> ; uint64_t Val = <NUM_LIT> ; unsigned ImmMask = <NUM_LIT> ; Imm =


<s> break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( type == OtherModImm ) return SDValue ( ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( type == MVEVMVNModImm ) return SDValue ( ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } return SDValue ( ) ; case <NUM_LIT> : { if ( type != VMOVModImm ) return SDValue ( ) ; uint64_t BitMask = <NUM_LIT> ; uint64_t Val = <NUM_LIT> ; unsigned ImmMask = <NUM_LIT> ; Imm = <NUM_LIT> ; for ( int ByteNum = <NUM_LIT> ; ByteNum < <NUM_LIT> ; ++ ByteNum ) { if ( ( ( SplatBits | SplatUndef ) & BitMask ) == BitMask ) { Val |= BitMask ; Imm |= ImmMask ; } else if ( ( SplatBits & BitMask ) != <NUM_LIT> ) { return SDValue ( ) ; } BitMask <<= <NUM_LIT> ; ImmMask <<=


<s> Type * Tys [ ] = { VecTy , Int8Ptr } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , Int8Ptr ) ) ; Ops . push_back ( Builder . getInt32 ( LI -> getAlignment ( ) ) ) ; return Builder . CreateCall ( VldnFunc , Ops , <STR_LIT> ) ; } else { assert ( ( Factor == <NUM_LIT> || Factor == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> LoadInts = Factor == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; Type * VecEltTy = VecTy -> getElementType ( ) -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ ] = { VecTy , VecEltTy } ; Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts , Tys ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , VecEltTy ) ) ; return Builder . CreateCall ( VldnFunc , Ops , <STR_LIT> ) ; } } ; DenseMap < ShuffleVectorInst * , SmallVector < Value * , <NUM_LIT> >> SubVecs ; for ( unsigned LoadCount = <NUM_LIT> ; LoadCount < NumLoads ; ++ LoadCount ) { if ( LoadCount > <NUM_LIT> ) BaseAddr = Builder . CreateConstGEP1_32 ( VecTy -> getElementType ( ) , BaseAddr , VecTy -> getNumElements ( ) * Factor ) ; CallInst * VldN = createLoadIntrinsic ( BaseAddr ) ; for ( unsigned i = <NUM_LIT> ; i < Shuffles . size ( ) ;


<s> } assert ( isTypeLegal ( EVT :: getEVT ( VecTy ) ) && <STR_LIT> ) ; auto createLoadIntrinsic = [ & ] ( Value * BaseAddr ) { if ( Subtarget -> hasNEON ( ) ) { Type * Int8Ptr = Builder . getInt8PtrTy ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ ] = { VecTy , Int8Ptr } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , Int8Ptr ) ) ; Ops . push_back ( Builder . getInt32 ( LI -> getAlignment ( ) ) ) ; return Builder . CreateCall ( VldnFunc , Ops , <STR_LIT> ) ; } else { assert ( ( Factor == <NUM_LIT> || Factor == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> LoadInts = Factor == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; Type * VecEltTy = VecTy -> getElementType ( ) -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ ] = { VecTy , VecEltTy } ; Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts , Tys ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , VecEltTy ) ) ; return Builder . CreateCall ( VldnFunc , Ops , <STR_LIT> ) ; } } ; DenseMap < ShuffleVectorInst * , SmallVector < Value * , <NUM_LIT> >> SubVecs ; for ( unsigned LoadCount = <NUM_LIT> ; LoadCount


<s> case <STR_LIT> : return LowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , true ) ; return LowerSDIV ( Op , DAG , Subtarget ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , false ) ; return LowerUDIV ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerADDSUBCARRY ( Op , DAG ) ; case <STR_LIT> : case


<s> if ( SDValue Result = PerformADDCombineWithOperands ( N , N0 , N1 , DCI , Subtarget ) ) return Result ; return PerformADDCombineWithOperands ( N , N1 , N0


<s> for ( unsigned i = <NUM_LIT> , e = VecRed . getNumOperands ( ) ; i < e ; i ++ ) Ops . push_back ( VecRed -> getOperand ( i ) ) ; SDValue Red = DCI . DAG . getNode ( OpcodeA , dl , DCI . DAG . getVTList ( { <STR_LIT> , <STR_LIT> } ) , Ops ) ; return DCI . DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Red , SDValue ( Red . getNode ( ) , <NUM_LIT> ) ) ; } ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; return SDValue (


<s> while ( Src . getOpcode ( ) == <STR_LIT> ) Src = Src . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; if ( ( Src . getOpcode ( ) == <STR_LIT> || Src . getOpcode ( ) == <STR_LIT> || Src . getOpcode ( ) == <STR_LIT> ) && SrcVT . getScalarSizeInBits ( )

<= DstVT . getScalarSizeInBits ( ) && DAG . getDataLayout ( ) . isBigEndian ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , DstVT , Src ) ;


<s> EVT SrcVT = Src . getValueType ( ) ; if ( ( Src . getOpcode ( ) == <STR_LIT> || Src . getOpcode ( ) == <STR_LIT> || Src . getOpcode ( ) == <STR_LIT> ) && SrcVT . getScalarSizeInBits ( ) <= DstVT . getScalarSizeInBits ( ) && DAG . getDataLayout ( ) . isBigEndian ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc (


<s> SDLoc dl ( N ) ; if ( Op0 -> getOpcode ( ) == <STR_LIT> ) { SDValue X = Op0 -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && X . getValueType ( ) == <STR_LIT> ) return DCI .

DAG . getNode ( <STR_LIT> , dl , VT , X ) ;


<s> if ( VT == <STR_LIT> ) SaturateC = APInt ( <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , true ) ; else SaturateC = APInt ( <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , true ) ; APInt MinC , MaxC ; if ( ! <STR_LIT> ( Min -> getOperand ( <NUM_LIT> ) . getNode ( ) , MinC ) || MinC != SaturateC ) return false ; if ( ! <STR_LIT> ( Max -> getOperand ( <NUM_LIT> ) . getNode ( ) , MaxC ) || MaxC != ~ SaturateC ) return false ; return true ; } ; if ( IsSignedSaturate ( N , N0 . getNode ( ) ) ) { SDLoc DL ( N ) ; MVT ExtVT , HalfVT ; if ( VT == <STR_LIT> ) { HalfVT = <STR_LIT> ; ExtVT = <STR_LIT> ; } else { HalfVT = <STR_LIT> ; ExtVT = <STR_LIT> ; } SDValue VQMOVN = DAG . getNode ( <STR_LIT> , DL , HalfVT , DAG . getUNDEF ( HalfVT ) , N0 -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Bitcast = DAG . getNode ( <STR_LIT> , DL , VT , VQMOVN ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Bitcast , DAG . getValueType ( ExtVT ) ) ; } auto IsUnsignedSaturate = [ & ] ( SDNode * Min ) { if ( Min -> getOpcode ( ) != <STR_LIT> ) return false ; APInt SaturateC ; if ( VT == <STR_LIT> ) SaturateC = APInt ( <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , true ) ; else SaturateC = APInt ( <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , true ) ; APInt MinC ; if ( ! <STR_LIT> ( Min -> getOperand ( <NUM_LIT> ) . getNode ( ) , MinC ) || MinC != SaturateC ) return false ; return true ; } ; if ( IsUnsignedSaturate ( N ) ) { SDLoc DL ( N ) ; MVT HalfVT ; unsigned ExtConst ; if ( VT == <STR_LIT> ) { HalfVT = <STR_LIT> ; ExtConst = <NUM_LIT> ; } else { HalfVT = <STR_LIT> ; ExtConst = <NUM_LIT> ; } SDValue VQMOVN = DAG . getNode ( <STR_LIT> , DL , HalfVT , DAG . getUNDEF ( HalfVT ) , N0 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Bitcast = DAG . getNode ( <STR_LIT> , DL , VT ,


<s> if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( Subtarget -> hasMVEIntegerOps ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) return PerformORCombine_i1 ( N , DCI , Subtarget ) ; APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN && ( Subtarget -> hasNEON ( ) || Subtarget -> hasMVEIntegerOps ( ) ) && BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize == <NUM_LIT> || SplatBitSize == <NUM_LIT> || SplatBitSize == <NUM_LIT> || SplatBitSize == <NUM_LIT> ) { EVT VorrVT ; SDValue Val = isVMOVModifiedImm ( SplatBits . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , dl , VorrVT , VT , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VorrVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Vorr = DAG . getNode ( <STR_LIT> , dl , VorrVT , Input , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vorr ) ; } } } if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , false , DCI ) ) return Result ; if ( SDValue Result = PerformORCombineToSMULWBT ( N , DCI , Subtarget ) ) return Result ; } SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget -> hasNEON ( ) && N1 . getOpcode ( ) == <STR_LIT> && VT . isVector ( ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) { if ( N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) ) return SDValue ( ) ; APInt SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; APInt SplatBits0 , SplatBits1 ; BuildVectorSDNode * BVN0 = dyn_cast < BuildVectorSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; BuildVectorSDNode * BVN1 = dyn_cast < BuildVectorSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ; if ( BVN0 && BVN0 -> isConstantSplat ( SplatBits0 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { if ( BVN1 && BVN1 -> isConstantSplat ( SplatBits1 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { if ( SplatBits0 . getBitWidth ( ) == SplatBits1 . getBitWidth ( ) && SplatBits0 == ~ SplatBits1 ) { EVT CanonicalVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , CanonicalVT , N0 -> getOperand ( <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> ) , N1 -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Result


<s> SDValue NewN0 = DCI . DAG . getLogicalNOT ( DL , N0 , VT ) ; SDValue NewN1 = DCI . DAG . getLogicalNOT ( DL , N1 , VT ) ; SDValue And = DCI . DAG . getNode ( <STR_LIT> , DL , VT , NewN0 , NewN1 ) ; return DCI . DAG . getLogicalNOT ( DL , And ,


<s> SDValue Op = N -> getOperand ( <NUM_LIT> ) ; SDLoc dl ( N ) ; if ( Op -> getOpcode ( ) == <STR_LIT> ) { if ( Op -> getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) return Op -> getOperand ( <NUM_LIT> ) ; return DCI . DAG . getNode ( <STR_LIT> , dl , VT , Op


<s> unsigned NumElts = ToVT . getVectorNumElements ( ) ; if ( NumElts != M . size ( ) ) return false ; unsigned Off0 = rev ? NumElts : <NUM_LIT> ; unsigned Off1 = rev ? <NUM_LIT> : NumElts ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; i += <NUM_LIT> ) { if ( M [ i ] >= <NUM_LIT> && M [ i ] != ( int ) ( Off0 + i / <NUM_LIT> ) ) return false ; if ( M [ i + <NUM_LIT> ] >= <NUM_LIT> && M [ i + <NUM_LIT> ] != ( int ) ( Off1 + i / <NUM_LIT> ) ) return false ; } return true ; } ; if ( auto * Shuffle = dyn_cast < ShuffleVectorSDNode > ( Trunc -> getOperand ( <NUM_LIT> ) ) ) if ( isVMOVNOriginalMask ( Shuffle -> getMask ( ) , false ) || isVMOVNOriginalMask ( Shuffle -> getMask ( ) , true ) ) return SDValue ( ) ; LLVMContext & C = * DAG . getContext ( ) ; SDLoc DL ( St ) ; SDValue Ch = St -> getChain ( ) ; SDValue BasePtr = St -> getBasePtr ( ) ; Align Alignment = St -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = St -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = St -> getAAInfo ( ) ; EVT NewFromVT = EVT :: getVectorVT ( C , FromEltVT , NumElements ) ; EVT NewToVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , ToEltVT . getSizeInBits ( ) ) , NumElements ) ; SmallVector < SDValue , <NUM_LIT> > Stores ; for ( unsigned i = <NUM_LIT> ; i < FromVT . getVectorNumElements ( ) / NumElements ;


<s> SDLoc DL ( LD ) ; SDValue Ch = LD -> getChain ( ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; Align Alignment = LD -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = LD -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = LD -> getAAInfo ( ) ; <STR_LIT> NewExtType = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Offset = DAG . getUNDEF ( BasePtr . getValueType ( ) ) ; EVT NewFromVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , FromEltVT . getScalarSizeInBits ( ) ) , NumElements ) ; EVT NewToVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , ToEltVT . getScalarSizeInBits ( ) ) , NumElements ) ; SmallVector < SDValue , <NUM_LIT> > Loads ; SmallVector < SDValue , <NUM_LIT> > Chains ; for ( unsigned i = <NUM_LIT> ; i < FromVT . getVectorNumElements ( ) / NumElements ; i ++ ) { unsigned NewOffset = ( i * NewFromVT . getSizeInBits ( ) ) / <NUM_LIT> ; SDValue NewPtr = DAG . getObjectPtrOffset ( DL , BasePtr , TypeSize :: Fixed ( NewOffset ) ) ; SDValue NewLoad = DAG . getLoad ( <STR_LIT> , NewExtType , NewToVT , DL , Ch , NewPtr , Offset , LD -> getPointerInfo ( )

. getWithOffset ( NewOffset ) , NewFromVT , Alignment , MMOFlags , AAInfo ) ;


<s> if ( ! ToVT . isVector ( ) ) return SDValue ( ) ; assert ( FromVT . getVectorNumElements ( ) == ToVT . getVectorNumElements ( ) ) ; EVT ToEltVT = ToVT . getVectorElementType ( ) ; EVT FromEltVT = FromVT . getVectorElementType ( ) ; unsigned NumElements = <NUM_LIT> ; if ( ToEltVT == <STR_LIT> && ( FromEltVT == <STR_LIT> || FromEltVT == <STR_LIT> ) ) NumElements = <NUM_LIT> ; if ( ToEltVT == <STR_LIT> && FromEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( ToEltVT == <STR_LIT> && FromEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( NumElements == <NUM_LIT> || ( FromEltVT != <STR_LIT> && FromVT . getVectorNumElements ( ) == NumElements ) || FromVT . getVectorNumElements ( ) % NumElements != <NUM_LIT> || ! isPowerOf2_32 ( NumElements ) ) return SDValue ( ) ; LLVMContext & C = * DAG . getContext ( ) ; SDLoc DL ( LD ) ; SDValue Ch = LD -> getChain ( ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; Align Alignment = LD -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = LD -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = LD -> getAAInfo ( ) ; <STR_LIT> NewExtType = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Offset = DAG . getUNDEF (


<s> static SDValue PerformVDUPCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { SelectionDAG & DAG = DCI . DAG ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; SDLoc dl ( N ) ; if ( Subtarget -> hasMVEIntegerOps ( ) ) { if ( Op . getValueType ( ) == <STR_LIT> ) return DCI . DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ) ; else if ( Op . getValueType ( ) == <STR_LIT> ) return DCI . DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ) ; } if ( ! Subtarget -> hasNEON ( ) ) return SDValue ( ) ; LoadSDNode * LD = dyn_cast < LoadSDNode > ( Op . getNode ( ) ) ; if ( LD && Op . hasOneUse ( ) && LD -> isUnindexed ( ) && LD -> getMemoryVT ( ) == N -> getValueType ( <NUM_LIT> ) . getVectorElementType ( ) ) { SDValue Ops [ ] = { LD -> getOperand ( <NUM_LIT> ) , LD -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( LD

-> getAlignment ( ) , SDLoc ( N ) , <STR_LIT> ) } ;


<s> if ( Op -> getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) return Op -> getOperand ( <NUM_LIT> ) ; return DCI . DAG . getNode ( <STR_LIT> , dl , VT , Op -> getOperand ( <NUM_LIT> ) ) ; } return SDValue (


<s> static SDValue PerformVMOVNCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI ) { SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; unsigned IsTop = N -> getConstantOperandVal ( <NUM_LIT> ) ; if ( ( Op1 -> getOpcode ( ) == <STR_LIT> || Op1 -> getOpcode ( ) == <STR_LIT> ) && Op1 -> getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> ) return DCI . DAG . getNode ( Op1 -> getOpcode ( ) , SDLoc ( Op1 ) , N -> getValueType ( <NUM_LIT> ) , Op0 , Op1 -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; unsigned NumElts = N -> getValueType (

<NUM_LIT> ) . getVectorNumElements ( ) ;


<s> static SDValue PerformVSELECTCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return SDValue ( ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue XOR = N -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * Const = isConstOrConstSplat ( XOR -> getOperand ( <NUM_LIT> ) , false , true ) ; if ( ! Const || ! Const -> isOne ( ) ) return SDValue ( ) ; SDValue Cond = XOR -> getOperand ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; EVT Type = N -> getValueType ( <NUM_LIT>


<s> ConstantSDNode * Const = isConstOrConstSplat ( XOR -> getOperand ( <NUM_LIT> ) , false , true ) ; if ( ! Const || ! Const -> isOne ( ) ) return SDValue ( ) ; SDValue Cond = XOR -> getOperand ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; EVT Type = N -> getValueType (


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : ExpandREAD_REGISTER ( N , Results , DAG ) ; break ; case <STR_LIT> : Res = ExpandBITCAST ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Res = Expand64BitShift ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerREM ( N , DAG ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerDivRem ( SDValue ( N , <NUM_LIT> ) , DAG ) ; assert ( Res . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; return ; case <STR_LIT> : case <STR_LIT> : Res = LowerSADDSUBSAT ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ; break ; case <STR_LIT> : ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ; return ; case <STR_LIT> : case <STR_LIT> : assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; return ExpandDIV_Windows ( SDValue ( N , <NUM_LIT> ) , DAG , N -> getOpcode ( ) == <STR_LIT> , Results ) ; case <STR_LIT> : ReplaceCMP_SWAP_64Results ( N ,


<s> if ( ! I -> hasOneUse ( ) ) return false ; auto * Sub = cast < Instruction > ( * I -> users ( ) . begin ( ) ) ; return Sub -> getOpcode ( ) == Instruction :: FSub && Sub -> getOperand ( <NUM_LIT> ) == I ; } ; auto IsFMS = [ & ] ( Instruction * I ) { if ( match ( I -> getOperand ( <NUM_LIT> ) , m_FNeg ( m_Value ( ) ) ) || match ( I -> getOperand ( <NUM_LIT> ) , m_FNeg ( m_Value ( ) ) ) ) return true ; return false ; } ; auto IsSinker = [ & ] ( Instruction * I , int Operand ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Add : case Instruction :: Mul : case Instruction :: FAdd : case Instruction :: ICmp : case Instruction :: FCmp : return true ; case Instruction :: FMul : return ! IsFMSMul ( I ) ; case Instruction :: Sub : case Instruction :: FSub : case Instruction :: Shl : case Instruction :: LShr : case Instruction ::


<s> bool supportSplitCSR ( MachineFunction * MF ) const override { return MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getFunction ( ) -> hasFnAttribute ( Attribute


<s> return MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getFunction

( ) -> hasFnAttribute ( Attribute :: NoUnwind ) ;


<s> SDLoc dl ( N ) ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = Op . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; if ( SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) { if ( ! Subtarget -> hasFullFP16 ( ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Op ) ) ; } if ( SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) { if ( ! Subtarget -> hasFullFP16 ( ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Op ) ) ; } if ( ! ( SrcVT == <STR_LIT> || DstVT == <STR_LIT> ) ) return SDValue ( ) ; if ( SrcVT == <STR_LIT> && TLI . isTypeLegal ( DstVT ) ) { if ( SDValue Val = CombineVMOVDRRCandidateWithVecOp ( N , DAG ) ) return Val ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , DstVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ) ; } if ( DstVT == <STR_LIT> && TLI . isTypeLegal (


<s> assert ( Factor >= <NUM_LIT> && Factor <= getMaxSupportedInterleaveFactor ( ) && <STR_LIT> ) ; assert ( ! Shuffles . empty ( ) && <STR_LIT> ) ; assert ( Shuffles . size ( ) == Indices . size ( ) && <STR_LIT> ) ; VectorType * VecTy = Shuffles [ <NUM_LIT> ] -> getType ( ) ; Type * EltTy = VecTy -> getElementType ( ) ; const DataLayout & DL = LI -> getModule ( ) -> getDataLayout ( ) ; if ( ! isLegalInterleavedAccessType ( Factor , VecTy , DL ) ) return false ; unsigned NumLoads = getNumInterleavedAccesses ( VecTy , DL ) ; if ( EltTy -> isPointerTy ( ) ) VecTy = VectorType :: get ( DL . getIntPtrType ( EltTy ) , VecTy -> getNumElements ( ) ) ; IRBuilder < > Builder ( LI ) ; Value * BaseAddr = LI -> getPointerOperand ( ) ; if ( NumLoads > <NUM_LIT> ) { VecTy = VectorType :: get ( VecTy -> getElementType ( ) , VecTy -> getNumElements ( ) / NumLoads ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , VecTy -> getElementType ( ) -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ) ; } assert ( isTypeLegal ( EVT :: getEVT ( VecTy ) ) && <STR_LIT> ) ; auto createLoadIntrinsic = [ & ] ( Value * BaseAddr ) { if ( Subtarget -> hasNEON ( ) ) { Type * Int8Ptr = Builder . getInt8PtrTy ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ ] = { VecTy , Int8Ptr } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , Int8Ptr ) ) ; Ops . push_back ( Builder . getInt32 ( LI -> getAlignment ( ) ) ) ; return Builder . CreateCall ( VldnFunc , Ops , <STR_LIT> ) ; } else { assert ( ( Factor == <NUM_LIT> || Factor == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> LoadInts = Factor == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; Type * VecEltTy = VecTy -> getElementType ( ) -> getPointerTo ( LI


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Op . dump ( ) ) ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerWRITE_REGISTER ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SelectionDAG & DAG = DCI . DAG ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN && ( Subtarget -> hasNEON ( ) || Subtarget -> hasMVEIntegerOps ( ) ) && BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize <= <NUM_LIT> ) { EVT VbicVT ; SDValue Val = isVMOVModifiedImm ( ( ~ SplatBits ) . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , dl , VbicVT , VT , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VbicVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Vbic = DAG . getNode ( <STR_LIT> , dl , VbicVT , Input , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vbic ) ; } } } if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , true , DCI ) ) return Result ; if ( SDValue Result = PerformSHLSimplify ( N , DCI ,


<s> SDValue Src = N -> getOperand ( <NUM_LIT> ) ; while ( Src . getOpcode ( ) == <STR_LIT> ) Src = Src . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; if ( ( Src . getOpcode ( ) == <STR_LIT> || Src . getOpcode ( ) == <STR_LIT> || Src . getOpcode ( ) == <STR_LIT> ) && SrcVT . getScalarSizeInBits ( ) <= DstVT . getScalarSizeInBits ( ) && DAG . getDataLayout ( ) .

isBigEndian ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , DstVT , Src ) ;


<s> if ( ! ToVT . isVector ( ) ) return SDValue ( ) ; assert ( FromVT . getVectorNumElements ( ) == ToVT . getVectorNumElements ( ) ) ; EVT ToEltVT = ToVT . getVectorElementType ( ) ; EVT FromEltVT = FromVT . getVectorElementType ( ) ; unsigned NumElements = <NUM_LIT> ; if ( FromEltVT == <STR_LIT> && ( ToEltVT == <STR_LIT> || ToEltVT == <STR_LIT> ) ) NumElements = <NUM_LIT> ; if ( FromEltVT == <STR_LIT> && ToEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( NumElements == <NUM_LIT> || FromVT . getVectorNumElements ( ) == NumElements || FromVT . getVectorNumElements ( ) % NumElements != <NUM_LIT> ) return SDValue ( ) ; auto isVMOVNOriginalMask = [ & ] ( ArrayRef < int > M , bool rev ) { unsigned NumElts = ToVT . getVectorNumElements ( ) ; if ( NumElts != M . size ( ) || ( ToVT != <STR_LIT> && ToVT != <STR_LIT> ) ) return false ; unsigned Off0 = rev ? NumElts : <NUM_LIT> ; unsigned Off1 = rev ? <NUM_LIT> : NumElts ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; i += <NUM_LIT> ) { if ( M [ i ] >= <NUM_LIT> && M [ i ] != ( int ) ( Off0 + i / <NUM_LIT> ) ) return false ; if ( M [ i + <NUM_LIT> ] >= <NUM_LIT> && M [ i + <NUM_LIT> ]

!= ( int ) ( Off1 + i / <NUM_LIT> ) ) return false ;


<s> if ( ! LD -> isSimple ( ) || ! N0 . hasOneUse ( ) || LD -> isIndexed ( ) || LD -> getExtensionType ( ) != <STR_LIT> ) return SDValue ( ) ; EVT FromVT = LD -> getValueType ( <NUM_LIT> ) ; EVT ToVT = N -> getValueType ( <NUM_LIT> ) ; if ( ! ToVT . isVector ( ) ) return SDValue ( ) ; assert ( FromVT . getVectorNumElements ( ) == ToVT . getVectorNumElements ( ) ) ; EVT ToEltVT = ToVT . getVectorElementType ( ) ; EVT FromEltVT = FromVT . getVectorElementType ( ) ; unsigned NumElements = <NUM_LIT> ; if ( ToEltVT == <STR_LIT> && ( FromEltVT == <STR_LIT> || FromEltVT == <STR_LIT> ) ) NumElements = <NUM_LIT> ; if ( ToEltVT == <STR_LIT> && FromEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( NumElements == <NUM_LIT> || FromVT . getVectorNumElements ( ) == NumElements || FromVT . getVectorNumElements ( ) % NumElements != <NUM_LIT> || ! isPowerOf2_32 ( NumElements ) ) return SDValue ( ) ; SDLoc DL ( LD ) ; SDValue Ch = LD -> getChain ( ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; Align Alignment = LD -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = LD -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = LD -> getAAInfo ( ) ; <STR_LIT> NewExtType = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Offset = DAG . getUNDEF ( BasePtr . getValueType ( ) ) ; EVT NewFromVT = FromVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) ; EVT NewToVT = ToVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) ; unsigned NewOffset = NewFromVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue NewPtr = DAG . getObjectPtrOffset ( DL , BasePtr , NewOffset ) ; SDValue NewLoad1 = DAG . getLoad ( <STR_LIT> , NewExtType , NewToVT , DL , Ch , BasePtr , Offset , LD -> getPointerInfo ( )

, NewFromVT , Alignment . value ( ) , MMOFlags , AAInfo ) ;


<s> if ( ! LD -> isSimple ( ) || ! N0 . hasOneUse ( ) || LD -> isIndexed ( ) || LD -> getExtensionType ( ) != <STR_LIT> ) return SDValue ( ) ; EVT FromVT = LD -> getValueType ( <NUM_LIT> ) ; EVT ToVT = N -> getValueType ( <NUM_LIT> ) ; if ( ! ToVT . isVector ( ) ) return SDValue ( ) ; assert ( FromVT . getVectorNumElements ( ) == ToVT . getVectorNumElements ( ) ) ; EVT ToEltVT = ToVT . getVectorElementType ( ) ; EVT FromEltVT = FromVT . getVectorElementType ( ) ; unsigned NumElements = <NUM_LIT> ; if ( ToEltVT == <STR_LIT> && ( FromEltVT == <STR_LIT> || FromEltVT == <STR_LIT> ) ) NumElements = <NUM_LIT> ; if ( ToEltVT == <STR_LIT> && FromEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( NumElements == <NUM_LIT> || FromVT . getVectorNumElements ( ) == NumElements || FromVT . getVectorNumElements ( ) % NumElements != <NUM_LIT> || ! isPowerOf2_32 ( NumElements ) ) return SDValue ( ) ; SDLoc DL ( LD ) ; SDValue Ch = LD -> getChain ( ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; Align Alignment = LD -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = LD -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = LD -> getAAInfo ( ) ; <STR_LIT> NewExtType = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Offset = DAG . getUNDEF ( BasePtr . getValueType ( ) ) ; EVT NewFromVT = FromVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) ; EVT NewToVT = ToVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) ; unsigned NewOffset = NewFromVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue NewPtr = DAG . getObjectPtrOffset ( DL , BasePtr , NewOffset ) ; SDValue NewLoad1 = DAG . getLoad ( <STR_LIT> , NewExtType , NewToVT , DL , Ch , BasePtr , Offset , LD -> getPointerInfo ( ) , NewFromVT , Alignment . value ( ) , MMOFlags , AAInfo ) ; SDValue NewLoad2 = DAG . getLoad ( <STR_LIT> , NewExtType , NewToVT , DL , Ch , NewPtr , Offset , LD -> getPointerInfo ( ) . getWithOffset ( NewOffset ) , NewFromVT , Alignment . value ( ) , MMOFlags , AAInfo ) ; SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( NewLoad1 . getNode ( ) , <NUM_LIT> ) , SDValue ( NewLoad2 . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> )


<s> } ; auto IsVMLAV = [ & ] ( MVT RetTy , unsigned ExtendCode , ArrayRef < MVT > ExtTypes , SDValue & A , SDValue & B ) { if ( ResVT != RetTy || N0 -> getOpcode ( ) != <STR_LIT> ) return false ; SDValue ExtA = N0 -> getOperand ( <NUM_LIT> ) ; SDValue ExtB = N0 -> getOperand ( <NUM_LIT> ) ; if ( ExtA -> getOpcode ( ) != ExtendCode && ExtB -> getOpcode ( ) != ExtendCode ) return false ; A = ExtA -> getOperand ( <NUM_LIT> ) ; B = ExtB -> getOperand ( <NUM_LIT> ) ; if ( A . getValueType ( ) == B . getValueType ( ) && llvm :: any_of ( ExtTypes , [ & A ] ( MVT Ty ) { return A . getValueType ( ) == Ty ; } ) ) return true ; return false ; } ; auto Create64bitNode = [ & ] ( unsigned Opcode , ArrayRef < SDValue > Ops ) { SDValue Node = DAG . getNode ( Opcode , dl , { <STR_LIT> , <STR_LIT> } , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node , SDValue ( Node . getNode ( ) , <NUM_LIT> ) ) ; } ; if ( SDValue A = IsVADDV ( <STR_LIT> , <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) ) return DAG . getNode ( <STR_LIT> , dl , ResVT , A ) ; if ( SDValue A = IsVADDV ( <STR_LIT> , <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) ) return DAG . getNode ( <STR_LIT> , dl , ResVT , A ) ; if ( SDValue A = IsVADDV ( <STR_LIT> , <STR_LIT> , { <STR_LIT> } ) ) return Create64bitNode ( <STR_LIT> , { A } ) ; if ( SDValue A = IsVADDV ( <STR_LIT> , <STR_LIT> , { <STR_LIT> } ) ) return Create64bitNode ( <STR_LIT> , { A } ) ; SDValue A , B ; if ( IsVMLAV ( <STR_LIT> , <STR_LIT> , { <STR_LIT> , <STR_LIT> } , A , B ) ) return DAG . getNode ( <STR_LIT> , dl , ResVT , A , B ) ; if ( IsVMLAV ( <STR_LIT> , <STR_LIT> , { <STR_LIT> , <STR_LIT> } , A , B ) ) return DAG . getNode ( <STR_LIT> , dl , ResVT , A , B ) ; if ( IsVMLAV ( <STR_LIT> , <STR_LIT> , { <STR_LIT> , <STR_LIT> } , A , B )

) return Create64bitNode ( <STR_LIT> , { A , B } ) ;


<s> SDValue Copy = Op0 -> getOperand ( <NUM_LIT> ) ; if ( Copy . getValueType ( ) == <STR_LIT> && Copy -> getOpcode ( ) == <STR_LIT> ) { SDValue Ops [ ] = { Copy -> getOperand ( <NUM_LIT> ) , Copy -> getOperand ( <NUM_LIT> ) } ; SDValue NewCopy = DCI . DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Ops ) ; return NewCopy ; } } APInt DemandedMask = APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; const TargetLowering & TLI = DCI . DAG . getTargetLoweringInfo ( ) ; if ( TLI . SimplifyDemandedBits ( Op0 , DemandedMask , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; return SDValue ( )


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 -> getOpcode ( ) == <STR_LIT> ) { SDValue Copy = Op0 -> getOperand ( <NUM_LIT> ) ; if ( Copy . getValueType ( ) == <STR_LIT> && Copy -> getOpcode ( ) == <STR_LIT> ) { SDValue Ops [ ] = { Copy -> getOperand ( <NUM_LIT> ) , Copy -> getOperand ( <NUM_LIT> ) } ; SDValue NewCopy = DCI . DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Ops ) ; return NewCopy ; } } APInt DemandedMask = APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; const TargetLowering & TLI = DCI . DAG . getTargetLoweringInfo ( ) ; if ( TLI . SimplifyDemandedBits ( Op0 , DemandedMask , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; return SDValue (


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( <STR_LIT> ( N0 . getNode ( ) ) && N0 . hasOneUse ( ) ) { LoadSDNode * LN0 = cast < LoadSDNode > ( N0 ) ; SDValue Load = DCI . DAG . getExtLoad ( <STR_LIT> , SDLoc ( N ) , VT , LN0 -> getChain ( ) , LN0 -> getBasePtr ( ) , <STR_LIT> , LN0 -> getMemOperand ( ) ) ; DCI . DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; DCI . DAG . ReplaceAllUsesOfValueWith ( N0 . getValue ( <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; return


<s> if ( isThumb2 ) { Register NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addMemOperand ( CPMMO ) . add ( predOps ( <STR_LIT> ) ) ; Register NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; Register NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( NewVReg2 , RegState :: Kill ) . addImm ( PCLabelId ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( NewVReg3 , RegState :: Kill ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( FIMMOSt ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( isThumb ) { Register NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addMemOperand ( CPMMO ) . add ( predOps ( <STR_LIT> ) ) ; Register NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( PCLabelId ) ; Register NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( <STR_LIT> , RegState :: Define ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; Register NewVReg4 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg4 ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( NewVReg2 , RegState :: Kill ) . addReg ( NewVReg3 , RegState :: Kill ) . add ( predOps ( <STR_LIT> ) ) ; Register NewVReg5 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg5 ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( NewVReg4 , RegState :: Kill ) . addReg ( NewVReg5 , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addMemOperand ( FIMMOSt ) . add ( predOps ( <STR_LIT> ) ) ; }


<s> return ! IsFMSMul ( I ) ; case Instruction :: Sub : case Instruction :: FSub : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return Operand == <NUM_LIT> ; default : return false ; } } ; int Op = <NUM_LIT> ; if ( ! isa < ShuffleVectorInst > ( I -> getOperand ( Op ) ) ) Op = <NUM_LIT> ; if ( ! IsSinker ( I , Op ) ) return false ; if ( ! match ( I -> getOperand ( Op ) , m_ShuffleVector ( m_InsertElement ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) { return false ; } Instruction * Shuffle = cast < Instruction > ( I -> getOperand ( Op ) ) ; for ( Use & U : Shuffle


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> return false ; } } if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; auto IsSinker = [ ] ( Instruction * I , int Operand ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Add : case Instruction :: Mul : case Instruction :: ICmp : return true ; case Instruction :: Sub : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return Operand == <NUM_LIT> ; default : return false ; } } ; int Op = <NUM_LIT> ; if ( ! isa < ShuffleVectorInst > ( I -> getOperand ( Op ) ) ) Op = <NUM_LIT> ; if ( ! IsSinker ( I , Op ) ) return false ; if ( ! match ( I -> getOperand ( Op ) , m_ShuffleVector ( m_InsertElement ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_Zero ( ) ) ) ) { return false ; } Instruction * Shuffle = cast < Instruction > ( I -> getOperand ( Op ) ) ; for ( Use & U : Shuffle -> uses ( ) ) { Instruction * Insn = cast < Instruction > ( U . getUser ( ) ) ; if ( ! IsSinker ( Insn , U . getOperandNo ( ) ) ) return false ; } Ops . push_back ( & Shuffle -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & I -> getOperandUse


<s> while ( ! Worklist . empty ( ) ) { auto * U = Worklist . pop_back_val ( ) ; if ( isa < ConstantExpr > ( U ) ) { for ( auto * UU : U -> users ( ) ) Worklist . push_back ( UU ) ; continue ; } if ( ! isa < Instruction > ( U ) ) return


<s> if ( ! LeftShift && isMask_32 ( C1 ) ) { uint32_t C3 = countLeadingZeros ( C1 ) ; if ( C2 < C3 ) { SDValue SHL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( C3 - C2 , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SHL , DAG . getConstant ( C3 , DL , <STR_LIT> ) ) ; } } if ( LeftShift && isShiftedMask_32 ( C1 ) ) { uint32_t C3 = countLeadingZeros ( C1 ) ; if ( C2 + C3 < <NUM_LIT> && C1 == ( ( - <NUM_LIT> << ( C2 + C3 ) ) >> C3 ) ) { SDValue SHL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 -> getOperand ( <NUM_LIT>

) , DAG . getConstant ( C2 + C3 , DL , <STR_LIT> ) ) ;


<s> NumVecs = <NUM_LIT> ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; isLaneOp = true ; break ; } } else { isLaneOp = true ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = false ; isLoadOp = false ; break ; } } EVT VecTy ; if ( isLoadOp ) { VecTy = N -> getValueType ( <NUM_LIT> ) ; } else if ( isIntrinsic ) { VecTy = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) . getValueType ( ) ; } else { assert ( isStore && <STR_LIT> ) ; VecTy = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; } unsigned NumBytes = NumVecs * VecTy . getSizeInBits ( ) / <NUM_LIT> ; if ( isLaneOp ) NumBytes /= VecTy . getVectorNumElements ( ) ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ; if ( NumBytes >= <NUM_LIT> * <NUM_LIT> && ( ! CInc || CInc -> getZExtValue ( ) != NumBytes ) ) { continue ; } EVT AlignedVecTy = VecTy ; unsigned Alignment = MemN -> getAlignment


<s> BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) . addExternalSymbol ( <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; } } BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlags ( MachineInstr :: FrameSetup ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; MI . eraseFromParent (


<s> if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) GV = GA -> getBaseObject


<s> EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc dl ( Op ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; const TargetMachine & TM = getTargetMachine ( ) ; bool IsRO = isReadOnly ( GV ) ; if ( TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) && ! Subtarget -> genExecuteOnly ( ) ) if ( SDValue V = promoteToConstantPool ( GV , DAG , PtrVT , dl ) ) return V ; if ( isPositionIndependent ( ) ) { bool UseGOT_PREL = ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ; SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , UseGOT_PREL ? <STR_LIT> : <NUM_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , G ) ; if ( UseGOT_PREL ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; return Result ; } else if ( Subtarget -> isROPI ( ) && IsRO ) { SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , G ) ; return Result ; } else if ( Subtarget -> isRWPI ( ) && ! IsRO


<s> ++ NumMovwMovt ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , TargetFlags ) ) ; if ( GV -> hasDLLImportStorageClass ( ) ) Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT (