<s> unsigned Reg ; if ( ( Reg = isLoadFromStackSlot ( MI , FrameIndex ) ) ) return Reg ; SmallVector < const MachineMemOperand * , <NUM_LIT> > Accesses ; if ( hasLoadFromStackSlot ( MI , Accesses ) ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ; return <NUM_LIT> ;


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == <STR_LIT> ) { unsigned Reg ; if ( ( Reg = isLoadFromStackSlot ( MI , FrameIndex ) ) ) return Reg ; SmallVector < const MachineMemOperand * , <NUM_LIT> > Accesses ; if ( hasLoadFromStackSlot ( MI , Accesses ) ) {

FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ;


<s> if ( CmpI -> getOpcode ( ) == <STR_LIT> && OI -> getOpcode ( ) == <STR_LIT> && ( ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) || ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ) ) return true ; if ( ( ( CmpI -> getOpcode ( ) == <STR_LIT> && OI -> getOpcode ( ) == <STR_LIT> ) || ( CmpI -> getOpcode ( ) == <STR_LIT> && OI -> getOpcode ( ) == <STR_LIT> ) ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getImm ( ) == ImmValue ) return true ; return false ;


<s> if ( ( ( CmpI -> getOpcode ( ) == <STR_LIT> && OI -> getOpcode ( ) == <STR_LIT> ) || ( CmpI -> getOpcode ( ) == <STR_LIT> && OI -> getOpcode ( ) == <STR_LIT> ) ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getImm ( ) == ImmValue ) return true ;


<s> static inline bool isRMOpcode ( unsigned Opcode ) { switch ( Opcode ) { case <STR_LIT> :


<s> switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return true ; default : return false ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } return <NUM_LIT> ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RegisterInfo ( ) {


<s> DebugLoc DL ; if ( Position != MBB . end ( ) ) { DL = Position -> getDebugLoc ( ) ; } if ( ! <STR_LIT> . hasSubClassEq ( RegisterClass ) ) { llvm_unreachable ( <STR_LIT> ) ;


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator Position , unsigned DestinationRegister , int FrameIndex , const TargetRegisterClass * RegisterClass , const TargetRegisterInfo * ) const { DebugLoc DL ; if ( Position != MBB . end ( ) ) { DL = Position -> getDebugLoc ( ) ; } if ( ! <STR_LIT> . hasSubClassEq ( RegisterClass ) ) {


<s> } if ( I == B ) return false ; } if ( ! MI && ! Sub ) return false ; if ( ! MI ) MI = Sub ; if ( flagSettingOpcodeVariant ( MI -> getOpcode ( ) ) != <STR_LIT> ) { bool isSafe = false ; SmallVector < std :: pair < MachineOperand * , LPCC :: CondCode > , <NUM_LIT> > OperandsToUpdate ; I = CmpInstr ; E = CmpInstr . getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } LPCC :: CondCode CC ; CC = ( LPCC :: CondCode ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; if ( Sub ) { LPCC :: CondCode NewCC = getOppositeCondition ( CC ) ; if ( NewCC == LPCC :: ICC_T ) return false ; if ( SrcReg2 != <NUM_LIT> && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) { OperandsToUpdate . push_back ( std :: make_pair ( & ( ( * I ) . getOperand ( IO - <NUM_LIT> ) ) , NewCC ) ) ; } } else { switch ( CC ) { case LPCC :: ICC_EQ : case LPCC :: ICC_NE : case LPCC :: ICC_MI : case LPCC :: ICC_PL : case LPCC :: ICC_F : case LPCC :: ICC_T : break ; case LPCC :: ICC_CS : case LPCC :: ICC_CC : case LPCC :: ICC_VS : case LPCC :: ICC_VC :


<s> assert ( MI . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MachineInstr * DefMI = canFoldIntoSelect ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; bool Invert = ! DefMI ; if ( ! DefMI ) DefMI = canFoldIntoSelect ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! DefMI ) return nullptr ; MachineOperand FalseReg = MI . getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;

const TargetRegisterClass * PreviousClass = MRI . getRegClass ( FalseReg . getReg ( ) ) ;


<s> if ( ! MRI . constrainRegClass ( DestReg , PreviousClass ) ) return nullptr ; MachineInstrBuilder NewMI = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . add ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( getOppositeCondition ( LPCC :: CondCode ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . copyImplicitOps ( MI ) ;


<s> if ( Instruction -> isDebugInstr ( ) ) continue ; if ( Instruction -> getOpcode ( ) != <STR_LIT> && Instruction -> getOpcode ( ) != <STR_LIT> ) { break ; } Instruction -> eraseFromParent ( ) ; Instruction = MBB . end ( ) ; ++ Count ;


<s> assert ( ( Condition . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; LPCC :: CondCode BranchCond = static_cast < LPCC :: CondCode > ( Condition [ <NUM_LIT> ] . getImm ( ) ) ;

Condition [ <NUM_LIT> ] . setImm ( getOppositeCondition ( BranchCond ) ) ;


<s> if ( Position != MBB . end ( ) ) { DL = Position -> getDebugLoc ( ) ; } if ( ! <STR_LIT> . hasSubClassEq ( RegisterClass ) ) { llvm_unreachable ( <STR_LIT> ) ; }

BuildMI ( MBB , Position , DL , get ( <STR_LIT> ) ) . addReg ( SourceRegister , getKillRegState ( IsKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addImm ( LPAC :: ADD ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; } BuildMI ( MBB , Position , DL , get ( <STR_LIT> ) ) . addReg ( SourceRegister , getKillRegState ( IsKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addImm ( LPAC :: ADD ) ;


<s> if ( getMemOperandWithOffsetWidth ( MIa , BaseOpA , OffsetA , WidthA , TRI ) && getMemOperandWithOffsetWidth ( MIb , BaseOpB , OffsetB , WidthB , TRI ) ) { if ( BaseOpA -> isIdenticalTo ( * BaseOpB ) ) { int LowOffset = std :: min ( OffsetA , OffsetB ) ; int HighOffset = std :: max ( OffsetA , OffsetB ) ;

int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : unsigned Width ;

return getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset , Width , TRI ) ;


<s> if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) || MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned BaseRegA = <NUM_LIT> , BaseRegB = <NUM_LIT> ; int64_t OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; unsigned int WidthA = <NUM_LIT> , WidthB = <NUM_LIT> ; if ( getMemOpBaseRegImmOfsWidth ( MIa , BaseRegA , OffsetA , WidthA , TRI ) && getMemOpBaseRegImmOfsWidth ( MIb , BaseRegB , OffsetB , WidthB , TRI ) ) { if ( BaseRegA == BaseRegB ) { int LowOffset = std :: min ( OffsetA , OffsetB ) ; int HighOffset = std :: max ( OffsetA , OffsetB ) ; int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ;

if ( LowOffset + LowWidth <= HighOffset ) return true ;


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; break ; }

BaseReg = LdSt . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> bool <ISA_LIT>InstrInfo :: analyzeCompare ( const MachineInstr & MI , Register & SrcReg , Register & SrcReg2 , int64_t & CmpMask , int64_t & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : break ;


<s> if ( MO . isFI ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return nullptr ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isTied ( ) ) return nullptr ; if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) return nullptr ; if ( MO . isDef ( ) && ! MO . isDead ( ) ) return nullptr ; } bool DontMoveAcrossStores = true ; if ( ! MI -> isSafeToMove ( nullptr , DontMoveAcrossStores ) ) return nullptr ; return MI ;


<s> if ( MO . isFI ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return nullptr ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isTied ( ) ) return nullptr ; if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) return nullptr ;

if ( MO . isDef ( ) && ! MO . isDead ( ) ) return nullptr ;


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : const MachineOperand * BaseOp ; OffsetIsScalable = false ; if ( ! getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset , Width , TRI ) ) return false ; BaseOps . push_back ( BaseOp ) ; return true ;


<s> if ( CmpI -> getOpcode ( ) == <STR_LIT> && OI -> getOpcode ( ) == <STR_LIT> && ( ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) || ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ) ) return true ; if ( ( ( CmpI -> getOpcode ( ) == <STR_LIT> && OI -> getOpcode ( ) == <STR_LIT> ) || ( CmpI -> getOpcode ( ) == <STR_LIT> && OI -> getOpcode ( ) == <STR_LIT> ) ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getImm ( ) == ImmValue ) return true ;


<s> if ( CmpI -> getOpcode ( ) == <STR_LIT> && OI -> getOpcode ( ) == <STR_LIT> && ( ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) || ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ) ) return true ; if ( ( ( CmpI -> getOpcode ( ) == <STR_LIT> && OI -> getOpcode ( ) == <STR_LIT> ) || ( CmpI -> getOpcode ( ) == <STR_LIT> && OI -> getOpcode ( ) == <STR_LIT> ) ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getImm ( ) == ImmValue ) return true ; return false ;


<s> if ( Position != MBB . end ( ) ) { DL = Position -> getDebugLoc ( ) ; } if ( ! <STR_LIT> . hasSubClassEq ( RegisterClass ) ) { llvm_unreachable ( <STR_LIT> ) ; } BuildMI ( MBB , Position , DL , get ( <STR_LIT> ) , DestinationRegister ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addImm ( LPAC :: ADD ) ;


<s> DebugLoc DL ; if ( Position != MBB . end ( ) ) { DL = Position -> getDebugLoc ( ) ; } if ( ! <STR_LIT> . hasSubClassEq ( RegisterClass ) ) { llvm_unreachable ( <STR_LIT> ) ; }

BuildMI ( MBB , Position , DL , get ( <STR_LIT> ) , DestinationRegister ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addImm ( LPAC :: ADD ) ;


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator Position , Register SourceRegister , bool IsKill , int FrameIndex , const TargetRegisterClass * RegisterClass , const TargetRegisterInfo * ) const { DebugLoc DL ; if ( Position != MBB . end ( ) ) { DL = Position -> getDebugLoc ( ) ; }

if ( ! <STR_LIT> . hasSubClassEq ( RegisterClass ) ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : const MachineOperand * BaseOp ; unsigned Width ; OffsetIsScalable = false ; if ( ! getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset , Width , TRI ) ) return false ; BaseOps . push_back ( BaseOp ) ;


<s> CmpValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = ~ <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ;


<s> SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = Register ( ) ; CmpMask = ~ <NUM_LIT> ; CmpValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; case <STR_LIT> :


<s> else return false ; } const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; for ( -- I ; I != E ; -- I ) { const MachineInstr & Instr = * I ; if ( Instr . modifiesRegister ( <STR_LIT> , TRI ) || Instr . readsRegister ( <STR_LIT> , TRI ) ) return false ; if ( isRedundantFlagInstr ( & CmpInstr , SrcReg , SrcReg2 , CmpValue , & * I ) ) { Sub = & * I ; break ; } if ( I == B ) return false ; } if ( ! MI && ! Sub ) return false ; if ( ! MI ) MI = Sub ; if ( flagSettingOpcodeVariant ( MI -> getOpcode ( ) ) != <STR_LIT> ) { bool isSafe = false ; SmallVector < std :: pair < MachineOperand * , LPCC :: CondCode > , <NUM_LIT> > OperandsToUpdate ; I = CmpInstr ; E = CmpInstr . getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } LPCC :: CondCode CC ; CC = ( LPCC :: CondCode ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; if ( Sub ) { LPCC :: CondCode NewCC = getOppositeCondition ( CC ) ; if ( NewCC == LPCC :: ICC_T ) return false ; if ( SrcReg2 != <NUM_LIT> && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) { OperandsToUpdate . push_back ( std :: make_pair ( & ( ( * I ) . getOperand ( IO - <NUM_LIT> ) ) , NewCC ) ) ; } } else { switch ( CC ) { case LPCC :: ICC_EQ : case LPCC :: ICC_NE : case LPCC :: ICC_MI : case LPCC :: ICC_PL : case LPCC :: ICC_F : case LPCC :: ICC_T : break ; case LPCC :: ICC_CS : case LPCC :: ICC_CC : case LPCC :: ICC_VS : case LPCC :: ICC_VC : case LPCC :: ICC_HI : case LPCC :: ICC_LS : case LPCC :: ICC_GE : case LPCC :: ICC_LT :


<s> FalseBlock = nullptr ; if ( MBB . isLayoutSuccessor ( Instruction -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TrueBlock = nullptr ; Instruction -> eraseFromParent ( ) ; Instruction = MBB . end ( ) ; continue ; } TrueBlock = Instruction -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } unsigned Opcode = Instruction -> getOpcode ( ) ; if ( Opcode != <STR_LIT> ) return true ; if ( Condition . empty ( ) ) { LPCC :: CondCode BranchCond = static_cast < LPCC :: CondCode > ( Instruction -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; FalseBlock = TrueBlock ; TrueBlock = Instruction -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Condition . push_back ( MachineOperand :: CreateImm ( BranchCond ) ) ; continue ; } return true ;


<s> FalseBlock = nullptr ; if ( MBB . isLayoutSuccessor ( Instruction -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TrueBlock = nullptr ; Instruction -> eraseFromParent ( ) ; Instruction = MBB . end ( ) ; continue ; } TrueBlock = Instruction -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } unsigned Opcode = Instruction -> getOpcode ( ) ; if ( Opcode != <STR_LIT> ) return true ; if ( Condition . empty ( ) ) { LPCC :: CondCode BranchCond = static_cast < LPCC :: CondCode > ( Instruction -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; FalseBlock = TrueBlock ; TrueBlock = Instruction -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Condition . push_back ( MachineOperand :: CreateImm ( BranchCond ) ) ;


<s> bool <ISA_LIT>InstrInfo :: areMemAccessesTriviallyDisjoint ( MachineInstr * MIa , MachineInstr * MIb , AliasAnalysis * AA ) const { assert ( MIa && MIa -> mayLoadOrStore ( ) && <STR_LIT> ) ; assert ( MIb && MIb -> mayLoadOrStore ( ) && <STR_LIT> ) ; if ( MIa -> hasUnmodeledSideEffects ( ) || MIb -> hasUnmodeledSideEffects ( ) || MIa -> hasOrderedMemoryRef ( ) || MIb -> hasOrderedMemoryRef ( ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned BaseRegA = <NUM_LIT> , BaseRegB = <NUM_LIT> ; int64_t OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; unsigned int WidthA = <NUM_LIT> , WidthB = <NUM_LIT> ; if ( getMemOpBaseRegImmOfsWidth ( MIa , BaseRegA , OffsetA , WidthA , TRI ) && getMemOpBaseRegImmOfsWidth ( MIb , BaseRegB , OffsetB , WidthB , TRI ) ) {


<s> bool <ISA_LIT>InstrInfo :: areMemAccessesTriviallyDisjoint ( MachineInstr * MIa , MachineInstr * MIb , AliasAnalysis * AA ) const { assert ( MIa && MIa -> mayLoadOrStore ( ) && <STR_LIT> ) ; assert ( MIb && MIb -> mayLoadOrStore ( ) && <STR_LIT> ) ; if ( MIa -> hasUnmodeledSideEffects ( ) || MIb -> hasUnmodeledSideEffects ( ) || MIa -> hasOrderedMemoryRef ( ) || MIb -> hasOrderedMemoryRef ( ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned BaseRegA = <NUM_LIT> , BaseRegB = <NUM_LIT> ; int64_t OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; unsigned int WidthA = <NUM_LIT> , WidthB = <NUM_LIT> ; if ( getMemOpBaseRegImmOfsWidth ( MIa , BaseRegA , OffsetA , WidthA , TRI ) && getMemOpBaseRegImmOfsWidth ( MIb , BaseRegB , OffsetB , WidthB , TRI ) ) { if ( BaseRegA == BaseRegB ) { int LowOffset = std :: min ( OffsetA , OffsetB ) ; int HighOffset = std :: max ( OffsetA , OffsetB ) ; int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ; if ( LowOffset + LowWidth <= HighOffset ) return true ;


<s> BuildMI ( MBB , Position , DL , get ( <STR_LIT> ) , DestinationRegister ) . addReg ( SourceRegister , getKillRegState ( KillSource ) ) . addImm ( <NUM_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const {


<s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { return false ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : unsigned Width ; return getMemOpBaseRegImmOfsWidth ( LdSt , BaseReg , Offset , Width , TRI ) ; }


<s> if ( LdSt -> getNumOperands ( ) != <NUM_LIT> ) return false ; if ( ! LdSt -> getOperand ( <NUM_LIT> ) . isReg ( ) || ! LdSt -> getOperand ( <NUM_LIT> ) . isImm ( ) || ! ( LdSt -> getOperand ( <NUM_LIT> ) . isImm ( ) && LdSt -> getOperand ( <NUM_LIT> ) . getImm ( ) == LPAC :: ADD ) ) return false ; switch ( LdSt -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; break ; } BaseReg = LdSt -> getOperand ( <NUM_LIT> ) . getReg ( ) ;

Offset = LdSt -> getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == <STR_LIT> ) if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ;

return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> if ( MI -> getOpcode ( ) == <STR_LIT> ) if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) {

FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ;


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == <STR_LIT> ) {


<s> int64_t OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; unsigned int WidthA = <NUM_LIT> , WidthB = <NUM_LIT> ; if ( getMemOperandWithOffsetWidth ( MIa , BaseOpA , OffsetA , WidthA , TRI ) && getMemOperandWithOffsetWidth ( MIb , BaseOpB , OffsetB , WidthB , TRI ) ) { if ( BaseOpA -> isIdenticalTo ( * BaseOpB ) ) { int LowOffset = std :: min ( OffsetA , OffsetB ) ; int HighOffset = std :: max ( OffsetA , OffsetB ) ; int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ;


<s> MachineInstr * MI = MRI . getVRegDef ( Reg ) ; if ( ! MI ) return nullptr ; if ( ! MI -> isPredicable ( ) ) return nullptr ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isFI ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return nullptr ;


<s> static MachineInstr * canFoldIntoSelect ( unsigned Reg , const MachineRegisterInfo & MRI ) { if ( ! Register :: isVirtualRegister ( Reg ) ) return nullptr ; if ( ! MRI . hasOneNonDBGUse ( Reg ) ) return nullptr ; MachineInstr * MI = MRI . getVRegDef ( Reg ) ; if ( ! MI ) return nullptr ; if ( ! MI -> isPredicable ( ) ) return nullptr ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isFI ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return nullptr ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isTied ( ) ) return nullptr ; if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) return nullptr ; if ( MO . isDef ( ) && ! MO . isDead ( ) ) return nullptr ; } bool DontMoveAcrossStores = true ;

if ( ! MI -> isSafeToMove ( nullptr , DontMoveAcrossStores ) ) return nullptr ;


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator Position , const DebugLoc & DL , MCRegister DestinationRegister , MCRegister SourceRegister , bool KillSource ) const { if ( ! <STR_LIT> . contains ( DestinationRegister , SourceRegister ) ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : const MachineOperand * BaseOp ; unsigned Width ; if ( ! getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset , Width , TRI ) ) return false ; BaseOps . push_back ( BaseOp ) ;


<s> const TargetRegisterClass * PreviousClass = MRI . getRegClass ( FalseReg . getReg ( ) ) ; if ( ! MRI . constrainRegClass ( DestReg , PreviousClass ) ) return nullptr ; MachineInstrBuilder NewMI = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . add ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( getOppositeCondition ( LPCC :: CondCode ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . copyImplicitOps ( MI ) ; FalseReg . setImplicit ( ) ; NewMI . add ( FalseReg ) ; NewMI -> tieOperands ( <NUM_LIT> , NewMI -> getNumOperands ( ) - <NUM_LIT> ) ; SeenMIs . insert ( NewMI ) ; SeenMIs . erase ( DefMI ) ;

if ( DefMI -> getParent ( ) != MI . getParent ( ) ) NewMI -> clearKillInfo ( ) ;


<s> if ( ! Reg . isVirtual ( ) ) return nullptr ; if ( ! MRI . hasOneNonDBGUse ( Reg ) ) return nullptr ; MachineInstr * MI = MRI . getVRegDef ( Reg ) ; if ( ! MI ) return nullptr ; if ( ! MI -> isPredicable ( ) ) return nullptr ; for ( const MachineOperand & MO : llvm :: drop_begin ( MI -> operands ( ) , <NUM_LIT> ) ) { if ( MO . isFI ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return nullptr ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isTied ( ) ) return nullptr ; if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) return nullptr ; if ( MO . isDef ( ) && ! MO . isDead ( ) ) return nullptr ; }


<s> MachineBasicBlock :: iterator I = CmpInstr , E = MI , B = CmpInstr . getParent ( ) -> begin ( ) ; if ( I == B ) return false ; MachineInstr * Sub = nullptr ; if ( SrcReg2 != <NUM_LIT> ) MI = nullptr ; else if ( MI -> getParent ( ) != CmpInstr . getParent ( ) || CmpValue != <NUM_LIT> ) { if ( CmpInstr . getOpcode ( ) == <STR_LIT> ) MI = nullptr ; else return false ; } const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; for ( -- I ; I != E ; -- I ) { const MachineInstr & Instr = * I ; if ( Instr . modifiesRegister ( <STR_LIT> , TRI ) || Instr . readsRegister ( <STR_LIT> , TRI ) ) return false ; if ( isRedundantFlagInstr ( & CmpInstr , SrcReg , SrcReg2 , CmpValue , & * I ) ) { Sub = & * I ; break ; } if ( I == B ) return false ; } if ( ! MI && ! Sub ) return false ; if ( ! MI ) MI = Sub ; if ( flagSettingOpcodeVariant ( MI -> getOpcode ( ) ) != <STR_LIT> ) { bool isSafe = false ; SmallVector < std :: pair < MachineOperand * , LPCC :: CondCode > , <NUM_LIT> > OperandsToUpdate ; I = CmpInstr ; E = CmpInstr . getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } LPCC :: CondCode CC ; CC = ( LPCC :: CondCode ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; if ( Sub ) { LPCC :: CondCode NewCC = getOppositeCondition ( CC ) ; if ( NewCC == LPCC :: ICC_T ) return false ;

if ( SrcReg2 != <NUM_LIT> && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) {


<s> MachineInstrBuilder NewMI = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . addOperand ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( getOppositeCondition ( LPCC :: CondCode ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . copyImplicitOps ( MI ) ; FalseReg . setImplicit ( ) ; NewMI . addOperand ( FalseReg ) ; NewMI -> tieOperands ( <NUM_LIT> , NewMI -> getNumOperands ( ) - <NUM_LIT> ) ; SeenMIs . insert ( NewMI ) ; SeenMIs . erase ( DefMI ) ; if ( DefMI -> getParent ( ) != MI . getParent ( ) ) NewMI -> clearKillInfo ( ) ; DefMI -> eraseFromParent ( ) ;


<s> i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . addOperand ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( getOppositeCondition ( LPCC :: CondCode ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . copyImplicitOps ( MI ) ; FalseReg . setImplicit ( ) ; NewMI . addOperand ( FalseReg ) ; NewMI -> tieOperands ( <NUM_LIT> , NewMI -> getNumOperands ( ) - <NUM_LIT> ) ; SeenMIs . insert ( NewMI ) ; SeenMIs . erase ( DefMI ) ; if ( DefMI -> getParent ( ) != MI . getParent ( ) ) NewMI -> clearKillInfo ( ) ;


<s> if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) || MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned BaseRegA = <NUM_LIT> , BaseRegB = <NUM_LIT> ; int64_t OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; unsigned int WidthA = <NUM_LIT> , WidthB = <NUM_LIT> ; if ( getMemOpBaseRegImmOfsWidth ( MIa , BaseRegA , OffsetA , WidthA , TRI ) && getMemOpBaseRegImmOfsWidth ( MIb , BaseRegB , OffsetB , WidthB , TRI ) ) { if ( BaseRegA == BaseRegB ) {

int LowOffset = std :: min ( OffsetA , OffsetB ) ;


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isFI ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return nullptr ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isTied ( ) ) return nullptr ; if ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) return nullptr ; if ( MO . isDef ( ) && ! MO . isDead ( ) ) return nullptr ;


<s> const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isFI ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return nullptr ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isTied ( ) ) return nullptr ; if ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) return nullptr ; if ( MO . isDef ( ) && ! MO . isDead ( ) ) return nullptr ;


<s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const {


<s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { return false ;


<s> if ( ! LdSt . getOperand ( <NUM_LIT> ) . isReg ( ) || ! LdSt . getOperand ( <NUM_LIT> ) . isImm ( ) || ! ( LdSt . getOperand ( <NUM_LIT> ) . isImm ( ) && LdSt . getOperand ( <NUM_LIT> ) . getImm ( ) == LPAC :: ADD ) ) return false ; switch ( LdSt . getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; break ; } BaseReg = LdSt . getOperand ( <NUM_LIT> ) . getReg ( ) ; Offset = LdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> } assert ( ( Condition . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned ConditionalCode = Condition [ <NUM_LIT> ] . getImm ( ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TrueBlock ) . addImm ( ConditionalCode ) ;


<s> assert ( ( Condition . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned ConditionalCode = Condition [ <NUM_LIT> ] . getImm ( ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TrueBlock ) . addImm ( ConditionalCode ) ;


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) { unsigned Reg ; if ( ( Reg = isLoadFromStackSlot ( MI , FrameIndex ) ) ) return Reg ; const MachineMemOperand * Dummy ; return hasLoadFromStackSlot ( MI , Dummy , FrameIndex ) ; } return <NUM_LIT> ;


<s> if ( Position != MBB . end ( ) ) { DL = Position -> getDebugLoc ( ) ; } if ( ! <STR_LIT> . hasSubClassEq ( RegisterClass ) ) { llvm_unreachable ( <STR_LIT> ) ; }


<s> if ( isRedundantFlagInstr ( & CmpInstr , SrcReg , SrcReg2 , CmpValue , & * I ) ) { Sub = & * I ; break ; } if ( I == B ) return false ; } if ( ! MI && ! Sub ) return false ; if ( ! MI ) MI = Sub ; if ( flagSettingOpcodeVariant ( MI -> getOpcode ( ) ) != <STR_LIT> ) { bool isSafe = false ; SmallVector < std :: pair < MachineOperand * , LPCC :: CondCode > , <NUM_LIT> > OperandsToUpdate ; I = CmpInstr ; E = CmpInstr . getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } LPCC :: CondCode CC ; CC = ( LPCC :: CondCode ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; if ( Sub ) { LPCC :: CondCode NewCC = getOppositeCondition ( CC ) ; if ( NewCC == LPCC :: ICC_T ) return false ; if ( SrcReg2 != <NUM_LIT> && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) {

OperandsToUpdate . push_back ( std :: make_pair ( & ( ( * I ) . getOperand ( IO - <NUM_LIT> ) ) , NewCC ) ) ;


<s> for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . addOperand ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( getOppositeCondition ( LPCC :: CondCode ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . copyImplicitOps ( MI ) ; FalseReg . setImplicit ( ) ; NewMI . addOperand ( FalseReg ) ; NewMI -> tieOperands ( <NUM_LIT> , NewMI -> getNumOperands ( ) - <NUM_LIT> ) ; SeenMIs . insert ( NewMI ) ; SeenMIs . erase ( DefMI ) ; if ( DefMI -> getParent ( ) != MI . getParent ( ) ) NewMI -> clearKillInfo ( ) ; DefMI -> eraseFromParent ( ) ;


<s> unsigned Count = <NUM_LIT> ; while ( Instruction != MBB . begin ( ) ) { -- Instruction ; if ( Instruction -> isDebugValue ( ) ) continue ; if ( Instruction -> getOpcode ( ) != <STR_LIT> && Instruction -> getOpcode ( ) != <STR_LIT> ) { break ; } Instruction -> eraseFromParent ( ) ; Instruction = MBB . end ( ) ; ++ Count ; } return Count ;


<s> LPCC :: CondCode BranchCond = static_cast < LPCC :: CondCode > ( Condition [ <NUM_LIT> ] . getImm ( ) ) ; Condition [ <NUM_LIT> ] . setImm ( getOppositeCondition ( BranchCond ) ) ; return false ;


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator Position , unsigned SourceRegister , bool IsKill , int FrameIndex , const TargetRegisterClass * RegisterClass , const TargetRegisterInfo * RegisterInfo ) const { DebugLoc DL ; if ( Position != MBB . end ( ) ) { DL = Position -> getDebugLoc ( ) ; } if ( ! <STR_LIT> . hasSubClassEq ( RegisterClass ) ) { llvm_unreachable ( <STR_LIT> ) ; } BuildMI ( MBB , Position , DL , get ( <STR_LIT> ) ) . addReg ( SourceRegister , getKillRegState ( IsKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addImm ( LPAC :: ADD ) ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ;


<s> if ( Node -> hasOneUse ( ) ) { CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI , Imm ) ; return ; } ReplaceNode ( Node , CurDAG -> getMachineNode ( Opc , DL , VT , TFI , Imm ) ) ;


<s> return ; } EVT VT = Node -> getValueType ( <NUM_LIT> ) ; switch ( Opcode ) { case <STR_LIT> : if ( VT == <STR_LIT> ) { ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ; if ( ConstNode -> isZero ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , <STR_LIT> ) ; return ReplaceNode ( Node , New . getNode ( ) ) ; } if ( ConstNode -> isAllOnes ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , <STR_LIT> ) ; return ReplaceNode ( Node , New . getNode ( ) ) ; } }


<s> EVT VT = Node -> getValueType ( <NUM_LIT> ) ; switch ( Opcode ) { case <STR_LIT> : if ( VT == <STR_LIT> ) { ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ; if ( ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , <STR_LIT> ) ; return ReplaceNode ( Node , New . getNode ( ) ) ; } if ( ConstNode -> isAllOnesValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , <STR_LIT> ) ; return ReplaceNode ( Node , New . getNode ( ) ) ; } }


<s> ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ; if ( ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , <STR_LIT> ) ; return ReplaceNode ( Node , New . getNode ( ) ) ; } if ( ConstNode -> isAllOnesValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , <STR_LIT> ) ; return ReplaceNode ( Node , New . getNode ( ) ) ; } } break ; case <STR_LIT> : selectFrameIndex ( Node ) ; return ; default : break ;


<s> return CurDAG -> getTargetConstant ( Imm , DL , <STR_LIT> ) ;


<s> inline SDValue getI32Imm ( unsigned Imm , SDLoc DL ) {

return CurDAG -> getTargetConstant ( Imm , DL , <STR_LIT> ) ;


<s> bool canBeRepresentedAsSls ( const ConstantSDNode & CN ) { return isInt < <NUM_LIT> > ( CN . getSExtValue ( ) ) && ( ( CN . getSExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> inline SDValue getI32Imm ( unsigned Imm , const SDLoc & DL ) { return CurDAG -> getTargetConstant ( Imm , DL , <STR_LIT> ) ;


<s> const char * getPassName ( ) const override {


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TargetMachine ) : SelectionDAGISel ( TargetMachine ) {


<s> bool runOnMachineFunction ( MachineFunction & MF ) override {

return SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> void <ISA_LIT>DAGToDAGISel :: Select ( SDNode * Node ) { unsigned Opcode = Node -> getOpcode ( ) ; DEBUG ( errs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; if ( Node -> isMachineOpcode ( ) ) { DEBUG ( errs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; return ; } switch ( Opcode ) {


<s> bool <ISA_LIT>DAGToDAGISel :: selectAddrRi ( SDValue Addr , SDValue & Base , SDValue & Offset , SDValue & AluOp ) { return selectAddrRiSpls ( Addr , Base , Offset , AluOp , true ) ;


<s> return selectAddrRiSpls ( Addr , Base , Offset , AluOp , true ) ;


<s> int16_t Imm = CN -> getSExtValue ( ) ; Offset = CurDAG -> getTargetConstant ( Imm , DL , CN -> getValueType ( <NUM_LIT> ) ) ; Base = CurDAG -> getRegister ( <STR_LIT> , CN -> getValueType ( <NUM_LIT> ) ) ; AluOp = CurDAG -> getTargetConstant ( LPAC :: ADD , DL , <STR_LIT> ) ; return true ; } if ( canBeRepresentedAsSls ( * CN ) ) return false ; } else { if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { int16_t Imm = CN -> getSExtValue ( ) ; Offset = CurDAG -> getTargetConstant ( Imm , DL , CN -> getValueType ( <NUM_LIT> ) ) ; Base = CurDAG -> getRegister ( <STR_LIT> , CN -> getValueType ( <NUM_LIT> ) ) ; AluOp = CurDAG -> getTargetConstant ( LPAC :: ADD , DL , <STR_LIT> ) ; return true ; } } } if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; AluOp = CurDAG -> getTargetConstant ( LPAC :: ADD , DL , <STR_LIT> ) ; return true ; } if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; <STR_LIT> AluOperator = static_cast < <STR_LIT> > ( Addr . getOpcode ( ) ) ; if ( AluOperator == <STR_LIT> ) { AluOp = CurDAG -> getTargetConstant ( LPAC :: ADD , DL , <STR_LIT> ) ; if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) if ( ( RiMode && isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) || ( ! RiMode && isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; } else {

Base = Addr . getOperand ( <NUM_LIT> ) ;


<s> <STR_LIT> AluOperator = static_cast < <STR_LIT> > ( Addr . getOpcode ( ) ) ; LPAC :: AluCode AluCode = LPAC :: isdTo<ISA_LIT>AluCode ( AluOperator ) ; if ( AluCode != LPAC :: UNKNOWN ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) return false ; if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; R1 = Addr . getOperand ( <NUM_LIT> ) ;


<s> } if ( Addr . getOpcode ( ) == <STR_LIT> && Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Offset = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; return true ;


<s> return true ; } } if ( Addr . getOpcode ( ) == <STR_LIT> && Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Offset = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: selectAddrSpls ( SDValue Addr , SDValue & Base , SDValue & Offset , SDValue & AluOp ) { return selectAddrRiSpls ( Addr , Base , Offset , AluOp , false ) ;


<s> int FI = dyn_cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ;


<s> SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; int FI = dyn_cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; unsigned Opc = <STR_LIT> ; if ( Node -> hasOneUse ( ) ) { CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI , Imm ) ; return ; } ReplaceNode ( Node , CurDAG -> getMachineNode ( Opc , DL , VT , TFI , Imm ) ) ;


<s> return true ; case InlineAsm :: Constraint_m : if ( ! selectAddrRr ( Op , Op0 , Op1 , AluOp ) && ! selectAddrRi ( Op , Op0 , Op1 , AluOp ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( AluOp ) ;


<s> DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , Known , Depth + <NUM_LIT> ) ; DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , Known2 , Depth + <NUM_LIT> ) ; Known . Zero &= Known2 . Zero ;


<s> void <ISA_LIT>TargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { unsigned BitWidth = Known . getBitWidth ( ) ; switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : Known = KnownBits ( BitWidth ) ; Known . Zero . setBits ( <NUM_LIT> , BitWidth ) ; break ; case <STR_LIT> : KnownBits Known2 ; DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , Known , Depth + <NUM_LIT> ) ; DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , Known2 , Depth + <NUM_LIT> ) ; Known . Zero &= Known2 . Zero ; Known . One &= Known2 . One ; break ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; } setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setMinFunctionAlignment ( <NUM_LIT> ) ; setPrefFunctionAlignment ( <NUM_LIT> ) ; setJumpIsExpensive ( true ) ; setMinimumJumpTableEntries ( <NUM_LIT> ) ; for ( int I = <NUM_LIT> ; I < RTLIB :: UNKNOWN_LIBCALL ; ++ I ) { setLibcallCallingConv ( static_cast < RTLIB :: Libcall > ( I ) , CallingConv :: Fast ) ; } MaxStoresPerMemset = <NUM_LIT> ; MaxStoresPerMemsetOptSize = <NUM_LIT> ; MaxStoresPerMemcpy = <NUM_LIT> ; MaxStoresPerMemcpyOptSize = <NUM_LIT> ; MaxStoresPerMemmove = <NUM_LIT> ; MaxStoresPerMemmoveOptSize = <NUM_LIT> ;

setBooleanContents ( ZeroOrOneBooleanContent ) ;


<s> uint8_t OpFlagHi = <STR_LIT> ; uint8_t OpFlagLo = <STR_LIT> ; SDValue Hi = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) , Offset , OpFlagHi ) ; SDValue Lo = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) , Offset , OpFlagLo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , Lo ) ;


<s> Known = DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; Known2 = DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; Known . Zero &= Known2 . Zero ; Known . One &= Known2 . One ; break ;


<s> default : break ; case <STR_LIT> : Known = KnownBits ( BitWidth ) ; Known . Zero . setBits ( <NUM_LIT> , BitWidth ) ; break ; case <STR_LIT> : KnownBits Known2 ; Known = DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; Known2 = DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; Known . Zero &= Known2 . Zero ; Known . One &= Known2 . One ; break ; }


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ;


<s> return ; case 'J' : case 'O' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) == <NUM_LIT> ) { Result = DAG . getTargetConstant ( <NUM_LIT> , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'K' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'L' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } }


<s> for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : { Register VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; break ; } default : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << RegVT . getEVTString ( ) << <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > <NUM_LIT> ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; } int FI = MFI . CreateFixedObject ( ObjSize , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; InVals . push_back ( DAG . getLoad ( VA . getLocVT ( ) , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ) ; } } if ( MF . getFunction ( ) . hasStructRetAttr ( ) ) { Register Reg = <ISA_LIT>MFI -> getSRetReturnReg ( ) ; if ( ! Reg ) { Reg = MF . getRegInfo ( ) . createVirtualRegister ( getRegClassFor ( <STR_LIT> ) ) ; <ISA_LIT>MFI -> setSRetReturnReg ( Reg ) ; } SDValue Copy = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , Reg , InVals [ <NUM_LIT> ] ) ; Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Copy , Chain ) ; } if ( IsVarArg ) { int FI = MFI . CreateFixedObject ( <NUM_LIT> , CCInfo . getNextStackOffset ( ) , true ) ; <ISA_LIT>MFI -> setVarArgsFrameIndex ( FI ) ; } return Chain ;


<s> Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasStructRetAttr ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Register Reg = <ISA_LIT>MFI -> getSRetReturnReg ( ) ; assert ( Reg && <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( <STR_LIT> , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasStructRetAttr ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Register Reg = <ISA_LIT>MFI -> getSRetReturnReg ( ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) {

SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ;


<s> Register <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , EVT , const MachineFunction & ) const { Register Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ;


<s> CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; break ; } default : DEBUG ( dbgs ( ) << <STR_LIT> << RegVT . getEVTString ( ) << <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > <NUM_LIT> ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; } int FI = MFI . CreateFixedObject ( ObjSize , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ;

InVals . push_back ( DAG . getLoad ( VA . getLocVT ( ) , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ) ;


<s> default : DEBUG ( dbgs ( ) << <STR_LIT> << RegVT . getEVTString ( ) << <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > <NUM_LIT> ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; } int FI = MFI . CreateFixedObject ( ObjSize , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; InVals . push_back ( DAG . getLoad ( VA . getLocVT ( ) , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ) ; } } if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { unsigned Reg = <ISA_LIT>MFI -> getSRetReturnReg ( ) ; if ( ! Reg ) { Reg = MF . getRegInfo ( ) . createVirtualRegister ( getRegClassFor ( <STR_LIT> ) ) ; <ISA_LIT>MFI -> setSRetReturnReg ( Reg ) ; } SDValue Copy = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , Reg , InVals [ <NUM_LIT> ] ) ; Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Copy , Chain ) ; } if ( IsVarArg ) { int FI = MFI . CreateFixedObject ( <NUM_LIT> , CCInfo . getNextStackOffset ( ) , true ) ; <ISA_LIT>MFI -> setVarArgsFrameIndex ( FI ) ; } return Chain ;


<s> if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ;


<s> else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ;


<s> unsigned <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , EVT , SelectionDAG & ) const { unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ; report_fatal_error ( <STR_LIT> ) ;


<s> unsigned <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , EVT , SelectionDAG & ) const {

unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'O' : if ( isa < ConstantInt > ( CallOperandVal ) ) Weight = CW_Constant ; break ; default : Weight = TargetLowering :: getSingleConstraintMatchWeight ( Info , Constraint ) ;


<s> case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'O' : if ( isa < ConstantInt > ( CallOperandVal ) ) Weight = CW_Constant ; break ; default : Weight = TargetLowering :: getSingleConstraintMatchWeight ( Info , Constraint ) ; break ;


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> default : return false ; case <STR_LIT> : { CC = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDValue N2 = N -> getOperand ( <NUM_LIT> ) ; if ( isZeroOrAllOnes ( N1 , AllOnes ) ) { Invert = false ; OtherOp = N2 ; return true ; } if ( isZeroOrAllOnes ( N2 , AllOnes ) ) { Invert = true ; OtherOp = N1 ; return true ; } return false ; } case <STR_LIT> : { if ( AllOnes ) return false ; CC = N -> getOperand ( <NUM_LIT> ) ; if ( CC . getValueType ( ) != <STR_LIT> ) return false ; SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; OtherOp = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; Invert = true ; return true ; } case <STR_LIT> : { CC = N -> getOperand ( <NUM_LIT> ) ; if ( CC . getValueType ( ) != <STR_LIT> ) return false ; SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; Invert = ! AllOnes ;

if ( AllOnes ) OtherOp = DAG . getConstant ( <NUM_LIT> , dl , VT ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ;


<s> } return ; case 'K' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'L' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'M' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { int64_t Val = C -> getSExtValue ( ) ; if ( ( isInt < <NUM_LIT> > ( Val ) ) && ( ( Val & <NUM_LIT> ) == <NUM_LIT> ) ) { Result = DAG . getTargetConstant ( Val , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'N' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) {


<s> case 'L' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'M' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { int64_t Val = C -> getSExtValue ( ) ; if ( ( isInt < <NUM_LIT> > ( Val ) ) && ( ( Val & <NUM_LIT> ) == <NUM_LIT> ) ) { Result = DAG . getTargetConstant ( Val , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'N' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { int64_t Val = C -> getSExtValue ( ) ; if ( ( Val >= - <NUM_LIT> ) && ( Val <= <NUM_LIT> ) ) { Result = DAG . getTargetConstant ( Val , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; default : break ; } if ( Result . getNode ( ) ) { Ops . push_back ( Result ) ; return ; }

TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ;


<s> SDLoc & DL = CLI . DL ; SmallVectorImpl < <STR_LIT> > & Outs = CLI . Outs ; SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ; SmallVectorImpl < <STR_LIT> > & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & IsTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool IsVarArg = CLI . IsVarArg ;


<s> SelectionDAG & DAG = CLI . DAG ; SDLoc & DL = CLI . DL ; SmallVectorImpl < <STR_LIT> > & Outs = CLI . Outs ; SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ; SmallVectorImpl < <STR_LIT> > & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & IsTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool IsVarArg = CLI . IsVarArg ; IsTailCall = false ; switch ( CallConv ) { case CallingConv :: Fast : case CallingConv :: C : return LowerCCCCallTo ( Chain , Callee , CallConv , IsVarArg , IsTailCall , Outs , OutVals , Ins , DL , DAG , InVals ) ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > <NUM_LIT> ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; } int FI = MFI -> CreateFixedObject ( ObjSize , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; InVals . push_back ( DAG . getLoad ( VA . getLocVT ( ) , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ) ; } } if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { unsigned Reg = <ISA_LIT>MFI -> getSRetReturnReg ( ) ; if ( ! Reg ) { Reg = MF . getRegInfo ( ) . createVirtualRegister ( getRegClassFor ( <STR_LIT> ) ) ; <ISA_LIT>MFI -> setSRetReturnReg ( Reg ) ; } SDValue Copy = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , Reg , InVals [ <NUM_LIT> ] ) ; Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Copy , Chain ) ; } if ( IsVarArg ) { int FI = MFI -> CreateFixedObject ( <NUM_LIT> , CCInfo . getNextStackOffset ( ) , true ) ; <ISA_LIT>MFI -> setVarArgsFrameIndex ( FI ) ; } return Chain ;


<s> case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( Flags . isByVal ( ) ) Arg = ByValArgs [ J ++ ] ; if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( StackPtr . getNode ( ) == <NUM_LIT> ) StackPtr = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue PtrOff = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) , DL ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo ( ) ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ArrayRef < SDValue > ( & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ) ; SDValue InFlag ; for ( unsigned I = <NUM_LIT> , E = RegsToPass . size ( ) ; I != E ; ++ I ) { Chain = DAG . getCopyToReg ( Chain , DL , RegsToPass [ I ] . first , RegsToPass [ I ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } uint8_t OpFlag = <STR_LIT> ; if ( G ) { Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , DL , getPointerTy ( DAG . getDataLayout ( ) ) , <NUM_LIT> , OpFlag ) ; } else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , getPointerTy ( DAG . getDataLayout ( ) ) , OpFlag ) ; } SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ;


<s> SDLoc DL ( Op ) ; ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; const Constant * C = N -> getConstVal ( ) ; const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * > ( getTargetMachine ( ) . getObjFileLowering ( ) ) ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Small || TLOF -> isConstantInSmallSection ( DAG . getDataLayout ( ) , C ) ) { SDValue Small = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) , N -> getOffset ( ) , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Small ) ) ; } else { uint8_t OpFlagHi = <STR_LIT> ; uint8_t OpFlagLo = <STR_LIT> ; SDValue Hi = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) , N -> getOffset ( ) , OpFlagHi ) ;

SDValue Lo = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) , N -> getOffset ( ) , OpFlagLo ) ;


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; unsigned SPReg = getStackPointerRegisterToSaveRestore ( ) ; SDValue StackPointer = DAG . getCopyFromReg ( Chain , DL , SPReg , <STR_LIT> ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , StackPointer , Size ) ; SDValue ArgAdjust = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Sub ) ; SDValue CopyChain = DAG . getCopyToReg ( Chain , DL , SPReg , Sub ) ; SDValue Ops [ <NUM_LIT> ] = { ArgAdjust , CopyChain } ; return DAG . getMergeValues ( Ops , DL ) ;


<s> switch ( CallConv ) { case CallingConv :: C : case CallingConv :: Fast :

return LowerCCCArguments ( Chain , CallConv , IsVarArg , Ins , DL , DAG , InVals ) ;


<s> } else { uint8_t OpFlagHi = <STR_LIT> ; uint8_t OpFlagLo = <STR_LIT> ; SDValue Hi = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) , Offset , OpFlagHi ) ; SDValue Lo = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) , Offset , OpFlagLo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ;


<s> case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCE ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> case <STR_LIT> : return LowerSETCCE ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; default :


<s> SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; const unsigned Offset = - <NUM_LIT> ;

SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , DL ) ) ;


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Carry = Op . getOperand ( <NUM_LIT> ) ; SDValue Cond = Op . getOperand ( <NUM_LIT> ) ;


<s> unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ;


<s> unsigned <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , EVT VT , SelectionDAG & DAG ) const { unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ;


<s> } return LPCC :: ICC_GT ; case <STR_LIT> : return LPCC :: ICC_UGT ; case <STR_LIT> : if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ) if ( RHSC -> getZExtValue ( ) == <NUM_LIT> ) return LPCC :: ICC_MI ; return LPCC :: ICC_LT ; case <STR_LIT> : return LPCC :: ICC_ULT ; case <STR_LIT> : if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ) if ( RHSC -> getZExtValue ( ) == <NUM_LIT> ) { RHS = DAG . getConstant ( <NUM_LIT> , DL , RHS . getValueType ( ) ) ; return LPCC :: ICC_MI ; } return LPCC :: ICC_LE ; case <STR_LIT> : return LPCC :: ICC_ULE ; case <STR_LIT> : if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ) if ( RHSC -> getZExtValue ( ) == <NUM_LIT> ) return LPCC :: ICC_PL ; return LPCC :: ICC_GE ; case <STR_LIT> : return LPCC :: ICC_UGE ; case <STR_LIT> : return LPCC :: ICC_NE ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; } setMinFunctionAlignment ( <NUM_LIT> ) ;

setPrefFunctionAlignment ( <NUM_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerBR_CC ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ;

SDValue Dest = Op . getOperand ( <NUM_LIT> ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT>32 ) ; for ( unsigned I = <NUM_LIT> ; I != RVLocs . size ( ) ; ++ I ) { Chain = DAG . getCopyFromReg ( Chain , DL , RVLocs [ I ] . getLocReg ( ) , RVLocs [ I ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ;

InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ;


<s> CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>32_Fast ) ; } else { CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>32 ) ; } for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; break ; } default : DEBUG ( dbgs ( ) << <STR_LIT> << RegVT . getEVTString ( ) << <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; }


<s> case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( Flags . isByVal ( ) ) Arg = ByValArgs [ J ++ ] ; if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( StackPtr . getNode ( ) == <NUM_LIT> ) StackPtr = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue PtrOff = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) , DL ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ArrayRef < SDValue > ( & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ) ; SDValue InFlag ; for ( unsigned I = <NUM_LIT> , E = RegsToPass . size ( ) ; I != E ; ++ I ) { Chain = DAG . getCopyToReg ( Chain , DL , RegsToPass [ I ] . first , RegsToPass [ I ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } uint8_t OpFlag = <STR_LIT> ; if ( G ) { Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , DL , getPointerTy ( DAG . getDataLayout ( ) ) , <NUM_LIT> , OpFlag ) ;

} else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


<s> case CallingConv :: Fast : return LowerCCCArguments ( Chain , CallConv , IsVarArg , Ins , DL , DAG , InVals ) ; default :


<s> MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , VT ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { const unsigned Offset = - <NUM_LIT> ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , DL ) ) ;

FrameAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , VT ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { const unsigned Offset = - <NUM_LIT> ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , DL ) ) ;


<s> CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>32 ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;

unsigned Reg = <ISA_LIT>MFI -> getSRetReturnReg ( ) ;


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MFI -> setReturnAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) {


<s> SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; const unsigned Offset = - <NUM_LIT> ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , DL ) ) ; return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> SDLoc DL ( Op ) ; LPCC :: CondCode CC = IntCondCCodeToICC ( Cond , DL , LHS , RHS , DAG ) ; SDValue TargetCC = DAG . getConstant ( CC , DL , <STR_LIT> ) ; SDValue Flag = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , RHS , TargetCC ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , VTs , TrueV , FalseV , TargetCC , Flag ) ;


<s> SDValue TargetCC = DAG . getConstant ( CC , DL , <STR_LIT> ) ; SDValue Flag = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , RHS , TargetCC ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ;


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; LPCC :: CondCode CC = IntCondCCodeToICC ( Cond , DL , LHS , RHS , DAG ) ; SDValue TargetCC = DAG . getConstant ( CC , DL , <STR_LIT> ) ; SDValue Flag = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , RHS , TargetCC ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , TargetCC , Flag ) ;


<s> SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; LPCC :: CondCode CC = IntCondCCodeToICC ( Cond , DL , LHS , RHS , DAG ) ; SDValue TargetCC = DAG . getConstant ( CC , DL , <STR_LIT> ) ;

SDValue Flag = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , RHS , TargetCC ) ;


SDValue Flag = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , RHS , Carry ) ;


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Carry = Op . getOperand ( <NUM_LIT> ) ; SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; LPCC :: CondCode CC = IntCondCCodeToICC ( Cond , DL , LHS , RHS , DAG ) ; SDValue TargetCC = DAG . getConstant ( CC , DL , <STR_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerVASTART ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ;


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; if ( CallConv == CallingConv :: Fast ) { CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>32_Fast ) ; } else { CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>32 ) ; } for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; break ; } default : DEBUG ( dbgs ( ) << <STR_LIT> << RegVT . getEVTString ( ) << <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > <NUM_LIT> ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; } int FI = MFI . CreateFixedObject ( ObjSize , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; InVals . push_back ( DAG . getLoad ( VA . getLocVT ( ) , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ) ; } } if ( MF . getFunction ( ) . hasStructRetAttr ( ) ) { unsigned Reg = <ISA_LIT>MFI -> getSRetReturnReg ( ) ;


<s> if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; break ; } default : DEBUG ( dbgs ( ) << <STR_LIT> << RegVT . getEVTString ( ) << <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > <NUM_LIT> ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; } int FI = MFI -> CreateFixedObject ( ObjSize , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; InVals . push_back ( DAG . getLoad ( VA . getLocVT ( ) , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) , false , false , false , <NUM_LIT> ) ) ; } } if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { unsigned Reg = <ISA_LIT>MFI -> getSRetReturnReg ( ) ; if ( ! Reg ) { Reg = MF . getRegInfo ( ) . createVirtualRegister ( getRegClassFor ( <STR_LIT> ) ) ; <ISA_LIT>MFI -> setSRetReturnReg ( Reg ) ; } SDValue Copy = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , Reg , InVals [ <NUM_LIT> ] ) ; Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Copy , Chain ) ; }


<s> llvm_unreachable ( <STR_LIT> ) ; } if ( Flags . isByVal ( ) ) Arg = ByValArgs [ J ++ ] ; if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( StackPtr . getNode ( ) == nullptr ) StackPtr = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue PtrOff = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) , DL ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo ( ) ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ArrayRef < SDValue > ( & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ) ; SDValue InFlag ; for ( unsigned I = <NUM_LIT> , E = RegsToPass . size ( ) ; I != E ; ++ I ) { Chain = DAG . getCopyToReg ( Chain , DL , RegsToPass [ I ] . first , RegsToPass [ I ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } uint8_t OpFlag = <STR_LIT> ; if ( G ) { Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , DL , getPointerTy ( DAG . getDataLayout ( ) ) , <NUM_LIT> , OpFlag ) ; } else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , getPointerTy ( DAG . getDataLayout ( ) ) , OpFlag ) ; } SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ;

const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallConv ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ;

return CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT>32 ) ;


<s> CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ;


<s> return CC_<ISA_LIT>32 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ;

else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ;


<s> } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ;


<s> static SDValue combineSelectAndUse ( SDNode * N , SDValue Slct , SDValue OtherOp , TargetLowering :: DAGCombinerInfo & DCI , bool AllOnes ) { SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue NonConstantVal ; SDValue CCOp ; bool SwapSelectOps ; if ( ! isConditionalZeroOrAllOnes ( Slct . getNode ( ) , AllOnes , CCOp , SwapSelectOps , NonConstantVal , DAG ) ) return SDValue ( ) ; SDValue TrueVal = OtherOp ; SDValue FalseVal = DAG . getNode ( N -> getOpcode ( ) , SDLoc ( N ) , VT , OtherOp , NonConstantVal ) ; if ( SwapSelectOps ) std :: swap ( TrueVal , FalseVal ) ;

return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , CCOp , TrueVal , FalseVal ) ;


<s> SDValue NonConstantVal ; SDValue CCOp ; bool SwapSelectOps ; if ( ! isConditionalZeroOrAllOnes ( Slct . getNode ( ) , AllOnes , CCOp , SwapSelectOps , NonConstantVal , DAG ) ) return SDValue ( ) ; SDValue TrueVal = OtherOp ; SDValue FalseVal = DAG . getNode ( N -> getOpcode ( ) , SDLoc ( N ) , VT , OtherOp , NonConstantVal ) ; if ( SwapSelectOps ) std :: swap ( TrueVal , FalseVal ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , CCOp , TrueVal , FalseVal ) ;


<s> if ( N1 . getNode ( ) -> hasOneUse ( ) ) if ( SDValue Result = combineSelectAndUse ( N , N1 , N0 , DCI , AllOnes ) ) return Result ;


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . getNode ( ) -> hasOneUse ( ) ) if ( SDValue Result = combineSelectAndUse ( N , N0 , N1 , DCI , AllOnes ) ) return Result ; if ( N1 . getNode ( ) -> hasOneUse ( ) ) if ( SDValue Result = combineSelectAndUse ( N , N1 , N0 , DCI , AllOnes ) ) return Result ;


<s> std :: pair < unsigned , const TargetRegisterClass * > <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) switch ( Constraint [ <NUM_LIT> ] ) { case 'r' :

return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ;


<s> std :: pair < unsigned , const TargetRegisterClass * > <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; default : break ; }

return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ;


<s> Register <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , LLT , const MachineFunction & ) const {

Register Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> case 'L' : case 'M' : case 'N' : case 'O' : if ( isa < ConstantInt > ( CallOperandVal ) ) Weight = CW_Constant ; break ; default : Weight = TargetLowering :: getSingleConstraintMatchWeight ( Info , Constraint ) ; break ; } return Weight ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : return nullptr ;


<s> case <STR_LIT> : return LPCC :: ICC_EQ ; case <STR_LIT> : if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ) if ( RHSC -> getZExtValue ( ) == <NUM_LIT> ) { RHS = DAG . getConstant ( <NUM_LIT> , DL , RHS . getValueType ( ) ) ; return LPCC :: ICC_PL ; } return LPCC :: ICC_GT ; case <STR_LIT> : return LPCC :: ICC_UGT ; case <STR_LIT> : if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ) if ( RHSC -> getZExtValue ( ) == <NUM_LIT> ) return LPCC :: ICC_MI ; return LPCC :: ICC_LT ; case <STR_LIT> : return LPCC :: ICC_ULT ; case <STR_LIT> : if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ) if ( RHSC -> getZExtValue ( ) == <NUM_LIT> ) { RHS = DAG . getConstant ( <NUM_LIT> , DL , RHS . getValueType ( ) ) ; return LPCC :: ICC_MI ; } return LPCC :: ICC_LE ; case <STR_LIT> : return LPCC :: ICC_ULE ; case <STR_LIT> : if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ) if ( RHSC -> getZExtValue ( ) == <NUM_LIT> ) return LPCC :: ICC_PL ; return LPCC :: ICC_GE ; case <STR_LIT> : return LPCC :: ICC_UGE ; case <STR_LIT> : return LPCC :: ICC_NE ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> return AllOnes ? isAllOnesConstant ( N ) : isNullConstant ( N ) ;


<s> if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isInt < <NUM_LIT> > ( C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'J' : case 'O' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) == <NUM_LIT> ) { Result = DAG . getTargetConstant ( <NUM_LIT> , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'K' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) {

if ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) {


<s> if ( isInt < <NUM_LIT> > ( C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'J' : case 'O' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) == <NUM_LIT> ) { Result = DAG . getTargetConstant ( <NUM_LIT> , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'K' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'L' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( C ) , Op . getValueType ( ) ) ;


<s> Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , Lo ) ; return Result ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; uint8_t OpFlagHi = <STR_LIT> ;


<s> SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; LPCC :: CondCode CC = IntCondCCodeToICC ( Cond , DL , RHS , DAG ) ; SDValue TargetCC = DAG . getConstant ( CC , DL , <STR_LIT> ) ; SDValue Flag = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , RHS , TargetCC ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Chain , Dest , TargetCC , Flag ) ;


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; LPCC :: CondCode CC = IntCondCCodeToICC ( Cond , DL , RHS , DAG ) ; SDValue TargetCC = DAG . getConstant ( CC , DL , <STR_LIT> ) ; SDValue Flag = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , RHS , TargetCC ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Chain , Dest , TargetCC , Flag ) ;


<s> SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & IsTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool IsVarArg = CLI . IsVarArg ; IsTailCall = false ; switch ( CallConv ) { case CallingConv :: Fast : case CallingConv :: C :

return LowerCCCCallTo ( Chain , Callee , CallConv , IsVarArg , IsTailCall , Outs , OutVals , Ins , DL , DAG , InVals ) ;


<s> default : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << RegVT . getEVTString ( ) << <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > <NUM_LIT> ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; } int FI = MFI . CreateFixedObject ( ObjSize , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; InVals . push_back ( DAG . getLoad ( VA . getLocVT ( ) , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ) ; } } if ( MF . getFunction ( ) . hasStructRetAttr ( ) ) { unsigned Reg = <ISA_LIT>MFI -> getSRetReturnReg ( ) ; if ( ! Reg ) { Reg = MF . getRegInfo ( ) . createVirtualRegister ( getRegClassFor ( <STR_LIT> ) ) ; <ISA_LIT>MFI -> setSRetReturnReg ( Reg ) ; } SDValue Copy = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , Reg , InVals [ <NUM_LIT> ] ) ;

Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Copy , Chain ) ;