<s> auto foundIt = CpuTable . find ( CPUString ) ; if ( foundIt != CpuTable . end ( ) ) <ISA_LIT>ArchVersion = foundIt -> second ; else llvm_unreachable ( <STR_LIT> ) ; UseHVXOps = false ; UseHVXDblOps = false ; UseLongCalls = false ; ParseSubtargetFeatures ( CPUString , FS ) ; if ( Enable<ISA_LIT>HVX . getPosition ( ) ) UseHVXOps = Enable<ISA_LIT>HVX ;

if ( Enable<ISA_LIT>HVXDouble . getPosition ( ) ) UseHVXDblOps = Enable<ISA_LIT>HVXDouble ;


<s> MachineInstr & SrcInst = * Src -> getInstr ( ) ; MachineInstr & DstInst = * Dst -> getInstr ( ) ; if ( Dst -> isBoundaryNode ( ) ) return false ; if ( SrcInst . isPHI ( ) || DstInst . isPHI ( ) ) return false ; SUnit * Best = nullptr ; SUnit * DstBest = nullptr ; SUnit * SrcBest = getZeroLatency ( Dst , Dst -> Preds ) ; if ( SrcBest == nullptr || Src -> NodeNum >= SrcBest -> NodeNum ) { DstBest = getZeroLatency ( Src , Src -> Succs ) ; if ( DstBest == nullptr || Dst -> NodeNum <= DstBest -> NodeNum ) Best = Dst ; } if ( Best != Dst ) return false ; if ( Src == SrcBest && Dst == DstBest ) return true ; if ( SrcBest != nullptr ) changeLatency ( SrcBest , SrcBest -> Succs , Dst , <NUM_LIT> ) ;

if ( DstBest != nullptr ) changeLatency ( Src , Src -> Succs , DstBest , <NUM_LIT> ) ;


<s> <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ArchVersion ( V2 ) , CPUString ( CPU . str ( ) ) { ParseSubtargetFeatures ( CPU , FS ) ; switch ( <ISA_LIT>ArchVersion ) { case <ISA_LIT>Subtarget :: V2 : break ; case <ISA_LIT>Subtarget :: V3 : EnableV3 = true ; break ; case <ISA_LIT>Subtarget :: V4 : break ; case <ISA_LIT>Subtarget :: V5 : break ; default : llvm_unreachable ( <STR_LIT> ) ; } InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( EnableMemOps ) UseMemOps = true ; else UseMemOps = false ; if ( EnableIEEERndNear ) ModeIEEERndNear = true ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , OptLevel ( TM . getOptLevel ( ) ) , CPUString ( std :: string ( <ISA_LIT>_MC :: select<ISA_LIT>CPU ( CPU ) ) ) , TargetTriple ( TT ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , RegInfo ( getHwMode ( ) ) , TLInfo ( TM , * this ) , InstrItins ( getInstrItineraryForCPU ( CPUString ) ) { <ISA_LIT>_MC :: addArchSubtarget ( this , FS ) ; assert ( InstrItins . Itineraries != nullptr && <STR_LIT> ) ;


<s> UseHVX64BOps = false ; UseAudioOps = false ; UseLongCalls = false ; UseBSBScheduling = hasV60Ops ( ) && EnableBSBSched ; ParseSubtargetFeatures ( CPUString , FS ) ; if ( OverrideLongCalls . getPosition ( ) ) UseLongCalls = OverrideLongCalls ; if ( isTinyCore ( ) ) { if ( ! EnableBSBSched . getPosition ( ) ) UseBSBScheduling = false ; } FeatureBitset Features = getFeatureBits ( ) ;

if ( <ISA_LIT>DisableDuplex ) setFeatureBits ( Features . reset ( <STR_LIT> ) ) ;


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { if ( CPUString . empty ( ) ) CPUString = <STR_LIT> ; if ( CPUString == <STR_LIT> ) { <ISA_LIT>ArchVersion = V2 ; } else if ( CPUString == <STR_LIT> ) { EnableV3 = true ; <ISA_LIT>ArchVersion = V3 ; } else if ( CPUString == <STR_LIT> ) { <ISA_LIT>ArchVersion = V4 ; } else if ( CPUString == <STR_LIT> ) { <ISA_LIT>ArchVersion = V5 ; } else { llvm_unreachable ( <STR_LIT> ) ;


<s> const <ISA_LIT>InstrInfo * QII = getInstrInfo ( ) ; SmallSet < SUnit * , <NUM_LIT> > ExclSrc ; SmallSet < SUnit * , <NUM_LIT> > ExclDst ; if ( QII -> canExecuteInBundle ( * SrcInst , * DstInst ) && isBestZeroLatency ( Src , Dst , QII , ExclSrc , ExclDst ) ) { Dep . setLatency ( <NUM_LIT> ) ; return ; } if ( ! hasV60Ops ( ) ) return ; if ( DstInst -> isCopy ( ) ) Dep . setLatency ( <NUM_LIT> ) ; if ( ( DstInst -> isRegSequence ( ) || DstInst -> isCopy ( ) ) && Dst -> NumSuccs == <NUM_LIT> ) { Register DReg = DstInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DDst = Dst -> Succs [ <NUM_LIT> ] . getSUnit ( ) -> getInstr ( ) ; unsigned UseIdx = - <NUM_LIT> ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < DDst -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DDst -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . getReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DReg ) { UseIdx = OpNum ; break ;


<s> T . setSUnit ( Src ) ; auto F = std :: find ( Dst -> Preds . begin ( ) , Dst -> Preds . end ( ) , T ) ;

assert ( F != Dst -> Preds . end ( ) ) ;


<s> T . setSUnit ( Src ) ; auto F = std :: find ( Dst -> Preds . begin ( ) , Dst -> Preds . end ( ) , T ) ; assert ( F != Dst -> Preds . end ( ) ) ; F -> setLatency ( Lat ) ; }


<s> const DataLayout * getDataLayout ( ) const { return & DL ;


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const { return & FrameLowering ;


<s> const <ISA_LIT>ArchEnum & get<ISA_LIT>ArchVersion ( ) const {


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const { return & InstrInfo ;


<s> const InstrItineraryData & getInstrItineraryData ( ) const { return InstrItins ;


<s> return & InstrInfo . getRegisterInfo ( ) ;


<s> const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const { return & TSInfo ;


<s> bool hasV2TOps ( ) const { return <ISA_LIT>ArchVersion >= V2 ;


<s> bool hasV2TOpsOnly ( ) const { return <ISA_LIT>ArchVersion == V2 ;


<s> bool hasV5TOps ( ) const { return <ISA_LIT>ArchVersion >= V5 ;


<s> bool hasV5TOpsOnly ( ) const { return <ISA_LIT>ArchVersion == V5 ;


<s> if ( Ty . isVector ( ) ) Ty = Ty . getVectorElementType ( ) ; if ( IncludeBool && Ty == <STR_LIT> ) return true ; ArrayRef < MVT > ElemTypes = getHVXElementTypes ( ) ; return llvm :: find ( ElemTypes , Ty ) != ElemTypes . end ( ) ;


<s> if ( ! useHVXOps ( ) ) return false ; if ( Ty . isVector ( ) ) Ty = Ty . getVectorElementType ( ) ; if ( IncludeBool && Ty == <STR_LIT> ) return true ; ArrayRef < MVT > ElemTypes = getHVXElementTypes ( ) ; return llvm :: find ( ElemTypes , Ty ) != ElemTypes . end ( ) ;


<s> if ( ! IncludeBool && ElemTy == <STR_LIT> ) return false ; unsigned HwLen = getVectorLength ( ) ; unsigned NumElems = VecTy . getVectorNumElements ( ) ; ArrayRef < MVT > ElemTypes = getHVXElementTypes ( ) ; if ( IncludeBool && ElemTy == <STR_LIT> ) { for ( MVT T : ElemTypes ) if ( NumElems * T . getSizeInBits ( ) == <NUM_LIT> * HwLen ) return true ; return false ;


<s> bool isSubtargetV2 ( ) const { return <ISA_LIT>ArchVersion == V2 ;


<s> if ( isHVXVectorType ( Ty . getSimpleVT ( ) , IncludeBool ) ) return true ; auto Action = getTargetLowering ( ) -> getPreferredVectorAction ( Ty . getSimpleVT ( ) ) ; return Action == TargetLoweringBase :: TypeWidenVector ;


<s> if ( ! VecTy -> isVectorTy ( ) || isa < ScalableVectorType > ( VecTy ) ) return false ; if ( ! cast < VectorType > ( VecTy ) -> getElementType ( ) -> isIntegerTy ( ) ) return false ; EVT Ty = EVT :: getEVT ( VecTy , false ) ; if ( ! Ty . isSimple ( ) || Ty . getSizeInBits ( ) <= <NUM_LIT> ) return false ; if ( isHVXVectorType ( Ty . getSimpleVT ( ) , IncludeBool ) ) return true ; auto Action = getTargetLowering ( ) -> getPreferredVectorAction ( Ty . getSimpleVT ( ) ) ;

return Action == TargetLoweringBase :: TypeWidenVector ;


<s> bool modeIEEERndNear ( ) const { return ModeIEEERndNear ;


<s> const MachineOperand & MO = DstI -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DepR ) { int Latency = ( InstrInfo . getOperandLatency ( & InstrItins , * SrcI , DefIdx , * DstI , OpNum ) ) ; Latency = std :: max ( Latency , <NUM_LIT> ) ; I . setLatency ( Latency ) ; updateLatency ( * SrcI , * DstI , I ) ; } } T . setSUnit ( Src ) ; auto F = std :: find ( Dst -> Preds . begin ( ) , Dst -> Preds . end ( ) , T ) ; assert ( F != Dst -> Preds . end ( ) ) ; F -> setLatency ( I . getLatency ( ) ) ;


<s> if ( ! hasV60Ops ( ) ) return ; auto & QII = static_cast < const <ISA_LIT>InstrInfo & > ( * getInstrInfo ( ) ) ; if ( QII . isHVXVec ( SrcInst ) || useBSBScheduling ( ) ) Dep . setLatency ( ( Dep . getLatency ( ) + <NUM_LIT> ) >> <NUM_LIT> ) ;


<s> return ; } if ( ! hasV60Ops ( ) ) return ; auto & QII = static_cast < const <ISA_LIT>InstrInfo & > ( * getInstrInfo ( ) ) ; if ( QII . isHVXVec ( SrcInst ) || useBSBScheduling ( ) ) Dep . setLatency ( ( Dep . getLatency ( ) + <NUM_LIT> ) >> <NUM_LIT> ) ;


<s> if ( ! hasV60Ops ( ) ) return ; if ( DstInst -> isCopy ( ) ) Dep . setLatency ( <NUM_LIT> ) ; if ( ( DstInst -> isRegSequence ( ) || DstInst -> isCopy ( ) ) && Dst -> NumSuccs == <NUM_LIT> ) { unsigned DReg = DstInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DDst = Dst -> Succs [ <NUM_LIT> ] . getSUnit ( ) -> getInstr ( ) ; unsigned UseIdx = - <NUM_LIT> ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < DDst -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DDst -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . getReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DReg ) { UseIdx = OpNum ; break ; }


<s> SmallSet < SUnit * , <NUM_LIT> > ExclSrc ; SmallSet < SUnit * , <NUM_LIT> > ExclDst ; if ( QII -> canExecuteInBundle ( * SrcInst , * DstInst ) && isBestZeroLatency ( Src , Dst , QII , ExclSrc , ExclDst ) ) { Dep . setLatency ( <NUM_LIT> ) ; return ; } if ( ! hasV60Ops ( ) ) return ; if ( DstInst -> isCopy ( ) ) Dep . setLatency ( <NUM_LIT> ) ; if ( ( DstInst -> isRegSequence ( ) || DstInst -> isCopy ( ) ) && Dst -> NumSuccs == <NUM_LIT> ) { unsigned DReg = DstInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DDst = Dst -> Succs [ <NUM_LIT> ] . getSUnit ( ) -> getInstr ( ) ; unsigned UseIdx = - <NUM_LIT> ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < DDst -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DDst -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . getReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DReg ) { UseIdx = OpNum ; break ; } } int DLatency = ( InstrInfo . getOperandLatency ( & InstrItins , * SrcInst , <NUM_LIT> , * DDst , UseIdx ) ) ; DLatency = std :: max ( DLatency , <NUM_LIT> ) ; Dep . setLatency ( ( unsigned ) DLatency ) ; } ExclSrc . clear ( ) ;


auto FoundIt = CpuTable . find ( CPUString ) ;


<s> } else { llvm_unreachable ( <STR_LIT> ) ; } ParseSubtargetFeatures ( CPUString , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( EnableMemOps ) UseMemOps = true ; else UseMemOps = false ; if ( EnableIEEERndNear ) ModeIEEERndNear = true ; else ModeIEEERndNear = false ;


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { static std :: map < StringRef , <STR_LIT> > CpuTable { { <STR_LIT> , <STR_LIT> :: V4 } , { <STR_LIT> , <STR_LIT> :: V5 } , { <STR_LIT> , <STR_LIT> :: V55 } , { <STR_LIT> , <STR_LIT> :: V60 } , { <STR_LIT> , <STR_LIT> :: V62 } , { <STR_LIT> , <STR_LIT> :: V65 } , } ; auto FoundIt = CpuTable . find ( CPUString ) ; if ( FoundIt != CpuTable . end ( ) ) <ISA_LIT>ArchVersion = FoundIt -> second ; else llvm_unreachable ( <STR_LIT> ) ; UseHVX128BOps = false ; UseHVX64BOps = false ; UseLongCalls = false ; UseMemOps = DisableMemOps ? false : EnableMemOps ; ModeIEEERndNear = EnableIEEERndNear ; UseBSBScheduling = hasV60TOps ( ) && EnableBSBSched ; ParseSubtargetFeatures ( CPUString , FS ) ; if ( OverrideLongCalls . getPosition ( ) ) UseLongCalls = OverrideLongCalls ; FeatureBitset Features = getFeatureBits ( ) ; if ( <ISA_LIT>DisableDuplex ) setFeatureBits ( Features . set ( <STR_LIT> , false ) ) ;

setFeatureBits ( <ISA_LIT>_MC :: completeHVXFeatures ( Features ) ) ;


<s> UseMemOps = DisableMemOps ? false : EnableMemOps ; ModeIEEERndNear = EnableIEEERndNear ; UseBSBScheduling = hasV60TOps ( ) && EnableBSBSched ; ParseSubtargetFeatures ( CPUString , FS ) ; if ( OverrideLongCalls . getPosition ( ) ) UseLongCalls = OverrideLongCalls ; FeatureBitset Features = getFeatureBits ( ) ; if ( <ISA_LIT>DisableDuplex ) setFeatureBits ( Features . set ( <STR_LIT> , false ) ) ; setFeatureBits ( <ISA_LIT>_MC :: completeHVXFeatures ( Features ) ) ;


<s> unsigned NumElems = VecTy . getVectorNumElements ( ) ; ArrayRef < MVT > ElemTypes = getHVXElementTypes ( ) ; if ( IncludeBool && ElemTy == <STR_LIT> ) { for ( MVT T : ElemTypes ) if ( NumElems * T . getSizeInBits ( ) == <NUM_LIT> * HwLen ) return true ; return false ; } unsigned VecWidth = VecTy . getSizeInBits ( ) ; if ( VecWidth != <NUM_LIT> * HwLen && VecWidth != <NUM_LIT> * HwLen ) return false ; return llvm :: any_of ( ElemTypes , [ ElemTy ] ( MVT T ) { return ElemTy == T ; } ) ;


<s> unsigned VecWidth = VecTy . getSizeInBits ( ) ; return VecWidth == <NUM_LIT> * getVectorLength ( ) || VecWidth == <NUM_LIT> * getVectorLength ( ) ;


<s> bool isHVXVectorType ( MVT VecTy ) const { if ( ! VecTy . isVector ( ) || ! useHVXOps ( ) ) return false ; unsigned ElemWidth = VecTy . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ElemWidth < <NUM_LIT> || ElemWidth > <NUM_LIT> ) return false ; unsigned VecWidth = VecTy . getSizeInBits ( ) ; return VecWidth == <NUM_LIT> * getVectorLength ( ) || VecWidth == <NUM_LIT> * getVectorLength ( ) ;


<s> if ( MO . isReg ( ) ) { Register MOReg = MO . getReg ( ) ; if ( DepR . isVirtual ( ) ) { IsSameOrSubReg = ( MOReg == DepR ) ; } else { IsSameOrSubReg = getRegisterInfo ( ) -> isSubRegisterEq ( DepR , MOReg ) ; } if ( MO . isDef ( ) && IsSameOrSubReg ) DefIdx = OpNum ; } } assert ( DefIdx >= <NUM_LIT> && <STR_LIT> ) ; MachineInstr * DstI = Dst -> getInstr ( ) ; SDep T = I ;

for ( unsigned OpNum = <NUM_LIT> ; OpNum < DstI -> getNumOperands ( ) ; OpNum ++ ) {


<s> IsSameOrSubReg = getRegisterInfo ( ) -> isSubRegisterEq ( DepR , MOReg ) ; } if ( MO . isDef ( ) && IsSameOrSubReg ) DefIdx = OpNum ; } } assert ( DefIdx >= <NUM_LIT> && <STR_LIT> ) ; MachineInstr * DstI = Dst -> getInstr ( ) ; SDep T = I ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < DstI -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DstI -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DepR ) { int Latency = ( InstrInfo . getOperandLatency ( & InstrItins , * SrcI , DefIdx , * DstI , OpNum ) ) ; Latency = std :: max ( Latency , <NUM_LIT> ) ; I . setLatency ( Latency ) ; updateLatency ( * SrcI , * DstI , I ) ; } }


<s> if ( ! hasV60Ops ( ) ) return ; if ( DstInst -> isCopy ( ) ) Dep . setLatency ( <NUM_LIT> ) ; if ( ( DstInst -> isRegSequence ( ) || DstInst -> isCopy ( ) ) && Dst -> NumSuccs == <NUM_LIT> ) { Register DReg = DstInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DDst = Dst -> Succs [ <NUM_LIT> ] . getSUnit ( ) -> getInstr ( ) ; unsigned UseIdx = - <NUM_LIT> ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < DDst -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DDst -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . getReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DReg ) { UseIdx = OpNum ; break ; } } int DLatency = ( InstrInfo . getOperandLatency ( & InstrItins , * SrcInst , <NUM_LIT> , * DDst , UseIdx ) ) ;

DLatency = std :: max ( DLatency , <NUM_LIT> ) ;


<s> } if ( ! hasV60Ops ( ) ) return ; if ( DstInst -> isCopy ( ) ) Dep . setLatency ( <NUM_LIT> ) ; if ( ( DstInst -> isRegSequence ( ) || DstInst -> isCopy ( ) ) && Dst -> NumSuccs == <NUM_LIT> ) { Register DReg = DstInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DDst = Dst -> Succs [ <NUM_LIT> ] . getSUnit ( ) -> getInstr ( ) ; unsigned UseIdx = - <NUM_LIT> ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < DDst -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DDst -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . getReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DReg ) {


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { static std :: map < StringRef , <STR_LIT> > CpuTable { { <STR_LIT> , <STR_LIT> :: V4 } , { <STR_LIT> , <STR_LIT> :: V5 } , { <STR_LIT> , <STR_LIT> :: V55 } , { <STR_LIT> , <STR_LIT> :: V60 } , { <STR_LIT> , <STR_LIT> :: V62 } , } ; auto FoundIt = CpuTable . find ( CPUString ) ; if ( FoundIt != CpuTable . end ( ) ) <ISA_LIT>ArchVersion = FoundIt -> second ; else llvm_unreachable ( <STR_LIT> ) ; UseHVX128BOps = false ; UseHVX64BOps = false ; UseLongCalls = false ; UseMemOps = DisableMemOps ? false : EnableMemOps ; ModeIEEERndNear = EnableIEEERndNear ; UseBSBScheduling = hasV60TOps ( ) && EnableBSBSched ; ParseSubtargetFeatures ( CPUString , FS ) ; if ( OverrideLongCalls . getPosition ( ) ) UseLongCalls = OverrideLongCalls ;


<s> case <ISA_LIT>Subtarget :: V3 : EnableV3 = true ; break ; case <ISA_LIT>Subtarget :: V4 : break ; default : llvm_unreachable ( <STR_LIT> ) ; }

InstrItins = getInstrItineraryForCPU ( CPUString ) ;


<s> case <ISA_LIT>Subtarget :: V2 : break ; case <ISA_LIT>Subtarget :: V3 : EnableV3 = true ; break ; case <ISA_LIT>Subtarget :: V4 : break ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , CPUString ( CPU ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( ) { InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( DisableMemOps ) UseMemOps = false ; else if ( EnableMemOps ) UseMemOps = true ; else UseMemOps = false ;

if ( EnableIEEERndNear ) ModeIEEERndNear = true ;


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { if ( CPUString . empty ( ) ) CPUString = <STR_LIT> ; if ( CPUString == <STR_LIT> ) { <ISA_LIT>ArchVersion = V4 ;


<s> if ( ! VecTy . isVector ( ) || ! useHVXOps ( ) || VecTy . isScalableVector ( ) ) return false ; MVT ElemTy = VecTy . getVectorElementType ( ) ; if ( ! IncludeBool && ElemTy == <STR_LIT> ) return false ; unsigned HwLen = getVectorLength ( ) ; unsigned NumElems = VecTy . getVectorNumElements ( ) ; ArrayRef < MVT > ElemTypes = getHVXElementTypes ( ) ; if ( IncludeBool && ElemTy == <STR_LIT> ) { if ( <NUM_LIT> * HwLen == NumElems ) return true ;

for ( MVT T : ElemTypes ) if ( NumElems * T . getSizeInBits ( ) == <NUM_LIT> * HwLen ) return true ;


<s> unsigned HwLen = getVectorLength ( ) ; unsigned NumElems = VecTy . getVectorNumElements ( ) ; ArrayRef < MVT > ElemTypes = getHVXElementTypes ( ) ; if ( IncludeBool && ElemTy == <STR_LIT> ) { if ( <NUM_LIT> * HwLen == NumElems ) return true ; for ( MVT T : ElemTypes ) if ( NumElems * T . getSizeInBits ( ) == <NUM_LIT> * HwLen ) return true ; return false ;


<s> const DataLayout * getDataLayout ( ) const override { return & DL ;


<s> llvm_unreachable ( <STR_LIT> ) ; } ParseSubtargetFeatures ( CPUString , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( DisableMemOps ) UseMemOps = false ; else if ( EnableMemOps ) UseMemOps = true ; else UseMemOps = false ;


<s> ParseSubtargetFeatures ( CPUString , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( DisableMemOps ) UseMemOps = false ; else if ( EnableMemOps ) UseMemOps = true ; else UseMemOps = false ; if ( EnableIEEERndNear ) ModeIEEERndNear = true ; else ModeIEEERndNear = false ;


<s> { <STR_LIT> , <STR_LIT> :: V60 } , { <STR_LIT> , <STR_LIT> :: V4 } , { <STR_LIT> , <STR_LIT> :: V5 } , { <STR_LIT> , <STR_LIT> :: V55 } , { <STR_LIT> , <STR_LIT> :: V60 } , { <STR_LIT> , <STR_LIT> :: V62 } , { <STR_LIT> , <STR_LIT> :: V65 } , } ; auto FoundIt = CpuTable . find ( CPUString ) ; if ( FoundIt != CpuTable . end ( ) ) <ISA_LIT>ArchVersion = FoundIt -> second ; else llvm_unreachable ( <STR_LIT> ) ; UseHVX128BOps = false ; UseHVX64BOps = false ; UseLongCalls = false ; UseBSBScheduling = hasV60Ops ( ) && EnableBSBSched ; ParseSubtargetFeatures ( CPUString , FS ) ;

if ( OverrideLongCalls . getPosition ( ) ) UseLongCalls = OverrideLongCalls ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( StringRef TT , StringRef CPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , CPUString ( CPU . str ( ) ) , DL ( <STR_LIT> ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM ) , TSInfo ( DL ) , FrameLowering ( ) { InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( DisableMemOps ) UseMemOps = false ; else if ( EnableMemOps ) UseMemOps = true ; else UseMemOps = false ; if ( EnableIEEERndNear ) ModeIEEERndNear = true ; else ModeIEEERndNear = false ;


<s> if ( ( DstInst -> isRegSequence ( ) || DstInst -> isCopy ( ) ) && Dst -> NumSuccs == <NUM_LIT> ) { Register DReg = DstInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DDst = Dst -> Succs [ <NUM_LIT> ] . getSUnit ( ) -> getInstr ( ) ; unsigned UseIdx = - <NUM_LIT> ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < DDst -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DDst -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . getReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DReg ) { UseIdx = OpNum ; break ; } } int DLatency = ( InstrInfo . getOperandLatency ( & InstrItins , * SrcInst , <NUM_LIT> , * DDst , UseIdx ) ) ; DLatency = std :: max ( DLatency , <NUM_LIT> ) ; Dep . setLatency ( ( unsigned ) DLatency ) ; } ExclSrc . clear ( ) ; ExclDst . clear ( ) ; if ( EnableDotCurSched && QII -> isToBeScheduledASAP ( * SrcInst , * DstInst ) && isBestZeroLatency ( Src , Dst , QII , ExclSrc , ExclDst ) ) {


<s> MachineInstr * DDst = Dst -> Succs [ <NUM_LIT> ] . getSUnit ( ) -> getInstr ( ) ; unsigned UseIdx = - <NUM_LIT> ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < DDst -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DDst -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . getReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DReg ) { UseIdx = OpNum ; break ; } } int DLatency = ( InstrInfo . getOperandLatency ( & InstrItins , * SrcInst , <NUM_LIT> , * DDst , UseIdx ) ) ; DLatency = std :: max ( DLatency , <NUM_LIT> ) ; Dep . setLatency ( ( unsigned ) DLatency ) ; } ExclSrc . clear ( ) ; ExclDst . clear ( ) ; if ( EnableDotCurSched && QII -> isToBeScheduledASAP ( * SrcInst , * DstInst ) && isBestZeroLatency ( Src , Dst , QII , ExclSrc , ExclDst ) ) { Dep . setLatency ( <NUM_LIT> ) ; return ; }

updateLatency ( * SrcInst , * DstInst , Dep ) ;


<s> static std :: map < StringRef , <STR_LIT> > CpuTable { { <STR_LIT> , <STR_LIT> :: V60 } , { <STR_LIT> , <STR_LIT> :: V5 } , { <STR_LIT> , <STR_LIT> :: V55 } , { <STR_LIT> , <STR_LIT> :: V60 } , { <STR_LIT> , <STR_LIT> :: V62 } , { <STR_LIT> , <STR_LIT> :: V65 } , { <STR_LIT> , <STR_LIT> :: V66 } , } ; auto FoundIt = CpuTable . find ( CPUString ) ; if ( FoundIt != CpuTable . end ( ) ) <ISA_LIT>ArchVersion = FoundIt -> second ; else llvm_unreachable ( <STR_LIT> ) ; UseHVX128BOps = false ; UseHVX64BOps = false ; UseLongCalls = false ; UseBSBScheduling = hasV60Ops ( ) && EnableBSBSched ; ParseSubtargetFeatures ( CPUString , FS ) ; if ( OverrideLongCalls . getPosition ( ) ) UseLongCalls = OverrideLongCalls ; FeatureBitset Features = getFeatureBits ( ) ; if ( <ISA_LIT>DisableDuplex ) setFeatureBits ( Features . reset ( <STR_LIT> ) ) ;


<s> InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( DisableMemOps ) UseMemOps = false ; else if ( EnableMemOps ) UseMemOps = true ; else UseMemOps = false ; if ( EnableIEEERndNear ) ModeIEEERndNear = true ; else ModeIEEERndNear = false ;


<s> static std :: map < StringRef , <STR_LIT> > CpuTable { { <STR_LIT> , <STR_LIT> :: V60 } , { <STR_LIT> , <STR_LIT> :: V5 } , { <STR_LIT> , <STR_LIT> :: V55 } , { <STR_LIT> , <STR_LIT> :: V60 } , { <STR_LIT> , <STR_LIT> :: V62 } , { <STR_LIT> , <STR_LIT> :: V65 } , } ; auto FoundIt = CpuTable . find ( CPUString ) ; if ( FoundIt != CpuTable . end ( ) ) <ISA_LIT>ArchVersion = FoundIt -> second ; else llvm_unreachable ( <STR_LIT> ) ; UseHVX128BOps = false ; UseHVX64BOps = false ; UseLongCalls = false ; UseBSBScheduling = hasV60Ops ( ) && EnableBSBSched ; ParseSubtargetFeatures ( CPUString , FS ) ; if ( OverrideLongCalls . getPosition ( ) ) UseLongCalls = OverrideLongCalls ;

FeatureBitset Features = getFeatureBits ( ) ;


<s> if ( Op . isReg ( ) && Dep . getReg ( ) != Op . getReg ( ) ) return ; } if ( useBSBScheduling ( ) && SrcInst -> isPHI ( ) ) { changePhiLatency ( SrcInst , Dst , Dep ) ; return ; } if ( DstInst -> isRegSequence ( ) && Dst -> NumSuccs == <NUM_LIT> ) DstInst = Dst -> Succs [ <NUM_LIT> ] . getSUnit ( ) -> getInstr ( ) ; if ( EnableDotCurSched && QII -> isToBeScheduledASAP ( SrcInst , DstInst ) && isBestZeroLatency ( Src , Dst , QII ) ) { Dep . setLatency ( <NUM_LIT> ) ; return ; }

updateLatency ( SrcInst , DstInst , Dep ) ;


<s> for ( auto & I : Deps ) { if ( I . getSUnit ( ) != Dst ) continue ; I . setLatency ( Lat ) ; SUnit * UpdateDst = I . getSUnit ( ) ; updateLatency ( SrcI , UpdateDst -> getInstr ( ) , I ) ;

for ( auto & PI : UpdateDst -> Preds ) {


<s> I . setLatency ( Lat ) ; SUnit * UpdateDst = I . getSUnit ( ) ; updateLatency ( SrcI , UpdateDst -> getInstr ( ) , I ) ; for ( auto & PI : UpdateDst -> Preds ) { if ( PI . getSUnit ( ) != Src || ! PI . isAssignedRegDep ( ) ) continue ; PI . setLatency ( Lat ) ;

updateLatency ( SrcI , UpdateDst -> getInstr ( ) , PI ) ;


<s> void <ISA_LIT>Subtarget :: changePhiLatency ( MachineInstr * SrcInst , SUnit * Dst , SDep & Dep ) const { if ( ! SrcInst -> isPHI ( ) || Dst -> NumPreds == <NUM_LIT> || Dep . getLatency ( ) != <NUM_LIT> ) return ; for ( const SDep & PI : Dst -> Preds ) { if ( PI . getLatency ( ) != <NUM_LIT> ) continue ; Dep . setLatency ( <NUM_LIT> ) ; break ;


<s> for ( const SDep & PI : Dst -> Preds ) {

if ( PI . getLatency ( ) != <NUM_LIT> ) continue ;


<s> MachineInstr * DstInst = Dst -> getInstr ( ) ; if ( SrcInst -> isPHI ( ) || DstInst -> isPHI ( ) ) return false ; SUnit * Best = nullptr ; SUnit * DstBest = nullptr ; SUnit * SrcBest = getZeroLatency ( Dst , Dst -> Preds ) ; if ( SrcBest == nullptr || Src -> NodeNum >= SrcBest -> NodeNum ) { DstBest = getZeroLatency ( Src , Src -> Succs ) ; if ( DstBest == nullptr || Dst -> NodeNum <= DstBest -> NodeNum ) Best = Dst ; } if ( Best != Dst ) return false ; if ( Src == SrcBest && Dst == DstBest ) return true ; if ( SrcBest != nullptr ) changeLatency ( SrcBest , SrcBest -> Succs , Dst , <NUM_LIT> ) ;

if ( DstBest != nullptr ) changeLatency ( Src , Src -> Succs , DstBest , <NUM_LIT> ) ;


<s> } else if ( EnableTCLatencySched ) {

if ( QII . isTC1 ( SrcInst ) || QII . isTC2 ( SrcInst ) ) if ( ! QII . isTC1 ( DstInst ) && ! QII . isTC2 ( DstInst ) ) Dep . setLatency ( Dep . getLatency ( ) + <NUM_LIT> ) ;


<s> if ( QII . isTC1 ( SrcInst ) || QII . isTC2 ( SrcInst ) ) if ( ! QII . isTC1 ( DstInst ) && ! QII . isTC2 ( DstInst ) ) Dep . setLatency ( Dep . getLatency ( ) + <NUM_LIT> ) ; }


<s> UseAudioOps = false ; UseLongCalls = false ; SubtargetFeatures Features ( FS ) ; auto IsQFloatFS = [ ] ( StringRef F ) { return F == <STR_LIT> || F == <STR_LIT> ; } ; if ( ! llvm :: count_if ( Features . getFeatures ( ) , IsQFloatFS ) ) { auto getHvxVersion = [ & Features ] ( StringRef FS ) -> StringRef { for ( StringRef F : llvm :: reverse ( Features . getFeatures ( ) ) ) { if ( F . startswith ( <STR_LIT> ) ) return F ; } for ( StringRef F : llvm :: reverse ( Features . getFeatures ( ) ) ) { if ( F == <STR_LIT> ) return StringRef ( ) ; if ( F . startswith ( <STR_LIT> ) || F == <STR_LIT> ) return F . take_front ( <NUM_LIT> ) ; } return StringRef ( ) ; } ; bool AddQFloat = false ; StringRef HvxVer = getHvxVersion ( FS ) ; if ( HvxVer . startswith ( <STR_LIT> ) ) { int Ver = <NUM_LIT> ; if ( ! HvxVer . drop_front ( <NUM_LIT> ) . consumeInteger ( <NUM_LIT> , Ver ) && Ver >= <NUM_LIT> ) AddQFloat = true ; } else if ( HvxVer == <STR_LIT> ) { if ( hasV68Ops ( ) ) AddQFloat = true ; } if ( AddQFloat ) Features . AddFeature ( <STR_LIT> ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , OptLevel ( TM . getOptLevel ( ) ) , CPUString ( <ISA_LIT>_MC :: select<ISA_LIT>CPU ( CPU ) ) , TargetTriple ( TT ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , RegInfo ( getHwMode ( ) ) , TLInfo ( TM , * this ) , InstrItins ( getInstrItineraryForCPU ( CPUString ) ) { <ISA_LIT>_MC :: addArchSubtarget ( this , FS ) ; assert ( InstrItins . Itineraries != nullptr && <STR_LIT> ) ;


<s> ArrayRef < MVT > ElemTypes = getHVXElementTypes ( ) ;

return llvm :: find ( ElemTypes , Ty ) != ElemTypes . end ( ) ;


<s> bool isHVXElementType ( MVT Ty , bool IncludeBool = false ) const { if ( ! useHVXOps ( ) ) return false ; if ( Ty . isVector ( ) ) Ty = Ty . getVectorElementType ( ) ; if ( IncludeBool && Ty == <STR_LIT> ) return true ;

ArrayRef < MVT > ElemTypes = getHVXElementTypes ( ) ;


<s> if ( Dep . getReg ( ) != SrcInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return ; } else if ( QII -> isPostIncrement ( * DstInst ) && Dep . getKind ( ) == SDep :: Anti ) { if ( DstInst -> mayStore ( ) ) return ; if ( Dep . getReg ( ) != DstInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return ; } else if ( QII -> isPostIncrement ( * DstInst ) && DstInst -> mayStore ( ) && Dep . isAssignedRegDep ( ) ) { MachineOperand & Op = DstInst -> getOperand ( DstInst -> getNumOperands ( ) - <NUM_LIT> ) ; if ( Op . isReg ( ) && Dep . getReg ( ) != Op . getReg ( ) ) return ; } if ( useBSBScheduling ( ) && SrcInst -> isPHI ( ) ) { changePhiLatency ( * SrcInst , Dst , Dep ) ; return ; } if ( DstInst -> isRegSequence ( ) && Dst -> NumSuccs == <NUM_LIT> ) DstInst = Dst -> Succs [ <NUM_LIT> ] . getSUnit ( ) -> getInstr ( ) ;

if ( EnableDotCurSched && QII -> isToBeScheduledASAP ( * SrcInst , * DstInst ) && isBestZeroLatency ( Src , Dst , QII ) ) {


<s> for ( auto & I : Deps ) { if ( I . getSUnit ( ) != Dst ) continue ; I . setLatency ( Lat ) ; SUnit * UpdateDst = I . getSUnit ( ) ; updateLatency ( SrcI , * UpdateDst -> getInstr ( ) , I ) ; for ( auto & PI : UpdateDst -> Preds ) { if ( PI . getSUnit ( ) != Src || ! PI . isAssignedRegDep ( ) ) continue ; PI . setLatency ( Lat ) ; updateLatency ( SrcI , * UpdateDst -> getInstr ( ) , PI ) ; }


<s> void <ISA_LIT>Subtarget :: changeLatency ( SUnit * Src , SmallVector < SDep , <NUM_LIT> > & Deps , SUnit * Dst , unsigned Lat ) const { MachineInstr & SrcI = * Src -> getInstr ( ) ; for ( auto & I : Deps ) { if ( I . getSUnit ( ) != Dst ) continue ; I . setLatency ( Lat ) ; SUnit * UpdateDst = I . getSUnit ( ) ; updateLatency ( SrcI , * UpdateDst -> getInstr ( ) , I ) ; for ( auto & PI : UpdateDst -> Preds ) { if ( PI . getSUnit ( ) != Src || ! PI . isAssignedRegDep ( ) ) continue ; PI . setLatency ( Lat ) ; updateLatency ( SrcI , * UpdateDst -> getInstr ( ) , PI ) ;


<s> for ( const SDep & PI : Dst -> Preds ) { if ( PI . getLatency ( ) != <NUM_LIT> ) continue ;


<s> const <ISA_LIT>ArchEnum & get<ISA_LIT>ArchVersion ( ) const { return <ISA_LIT>ArchVersion ;


<s> Mutations . push_back ( make_unique < <ISA_LIT>Subtarget :: <ISA_LIT>DAGMutation > ( ) ) ;


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ;


<s> unsigned getSmallDataThreshold ( ) const { return <ISA_LIT>_SMALL_DATA_THRESHOLD ;


<s> unsigned getSmallDataThreshold ( ) const {


<s> return get<ISA_LIT>ArchVersion ( ) >= V55 ;


<s> bool hasV55TOpsOnly ( ) const { return get<ISA_LIT>ArchVersion ( ) == V55 ;


<s> return get<ISA_LIT>ArchVersion ( ) == V55 ;


<s> return get<ISA_LIT>ArchVersion ( ) >= V5 ;


<s> return get<ISA_LIT>ArchVersion ( ) == V5 ;


<s> bool hasV60TOps ( ) const { return get<ISA_LIT>ArchVersion ( ) >= V60 ;


<s> return get<ISA_LIT>ArchVersion ( ) == V60 ;


<s> static std :: map < StringRef , <ISA_LIT>ArchEnum > CpuTable { { <STR_LIT> , V4 } , { <STR_LIT> , V5 } , { <STR_LIT> , V55 } , { <STR_LIT> , V60 } , } ; auto foundIt = CpuTable . find ( CPUString ) ; if ( foundIt != CpuTable . end ( ) ) <ISA_LIT>ArchVersion = foundIt -> second ;


<s> CPUString = <STR_LIT> ( getTargetTriple ( ) , CPU ) ; static std :: map < StringRef , <ISA_LIT>ArchEnum > CpuTable { { <STR_LIT> , V4 } , { <STR_LIT> , V5 } , { <STR_LIT> , V55 } , { <STR_LIT> , V60 } , } ; auto foundIt = CpuTable . find ( CPUString ) ;

if ( foundIt != CpuTable . end ( ) ) <ISA_LIT>ArchVersion = foundIt -> second ;


<s> if ( SrcInst . isPHI ( ) || DstInst . isPHI ( ) ) return false ; SUnit * Best = nullptr ; SUnit * DstBest = nullptr ; SUnit * SrcBest = getZeroLatency ( Dst , Dst -> Preds ) ; if ( SrcBest == nullptr || Src -> NodeNum >= SrcBest -> NodeNum ) { DstBest = getZeroLatency ( Src , Src -> Succs ) ; if ( DstBest == nullptr || Dst -> NodeNum <= DstBest -> NodeNum ) Best = Dst ; } if ( Best != Dst ) return false ; if ( Src == SrcBest && Dst == DstBest ) return true ;

if ( SrcBest != nullptr ) changeLatency ( SrcBest , SrcBest -> Succs , Dst , <NUM_LIT> ) ;


<s> } else if ( EnableTCLatencySched ) { if ( QII . isTC1 ( SrcInst ) || QII . isTC2 ( SrcInst ) ) if ( ! QII . isTC1 ( DstInst ) && ! QII . isTC2 ( DstInst ) ) Dep . setLatency ( Dep . getLatency ( ) + <NUM_LIT> ) ; }


<s> return UseHVXOps && ! UseHVXDblOps ;


<s> static Target The<ISA_LIT>Target ; return The<ISA_LIT>Target ;


<s> RegisterTarget < Triple :: hexagon , false > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) {

RegisterTarget < Triple :: hexagon , false > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


RegisterTarget < Triple :: hexagon , true > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> void MCLDInitialize<ISA_LIT>LDTargetInfo ( ) { mcld :: RegisterTarget < llvm :: Triple :: hexagon > X ( The<ISA_LIT>Target , <STR_LIT> ) ;


RegisterTarget < Triple :: hexagon , false > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> ) ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetInfo ( ) {


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: hexagon , false > X ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT> ) ;


<s> void <ISA_LIT>PassConfig :: addPostRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) if ( ! Disable<ISA_LIT>CFGOpt ) addPass ( create<ISA_LIT>CFGOptimizer ( ) , false ) ;


<s> if ( ! NoOpt ) addPass ( create<ISA_LIT>NewValueJump ( ) , false ) ; addPass ( create<ISA_LIT>ExpandPredSpillCode ( ) , false ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) , false ) ; if ( EnableGenMux ) addPass ( create<ISA_LIT>GenMux ( ) , false ) ;

addPass ( create<ISA_LIT>Packetizer ( ) , false ) ;


<s> if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) , false ) ; if ( EnableGenMux ) addPass ( create<ISA_LIT>GenMux ( ) , false ) ; addPass ( create<ISA_LIT>Packetizer ( ) , false ) ; } addPass ( create<ISA_LIT>CallFrameInformation ( ) , false ) ;


<s> if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>HardwareLoops ( ) , false ) ;


<s> Pass * Exp = create<ISA_LIT>ExpandCondsets ( ) ; insertPass ( & RegisterCoalescerID , IdentifyingPassPtr ( Exp ) ) ; } }


<s> Pass * Exp = create<ISA_LIT>ExpandCondsets ( ) ; insertPass ( & RegisterCoalescerID , IdentifyingPassPtr ( Exp ) ) ;


<s> if ( EnableBitSimplify ) addPass ( create<ISA_LIT>BitSimplify ( ) , false ) ; addPass ( create<ISA_LIT>Peephole ( ) ) ; printAndVerify ( <STR_LIT> ) ; if ( EnableGenInsert ) addPass ( create<ISA_LIT>GenInsert ( ) , false ) ; if ( EnableEarlyIf ) addPass ( create<ISA_LIT>EarlyIfConversion ( ) , false ) ; }


<s> if ( ! NoOpt ) { if ( EnableGenPred ) addPass ( create<ISA_LIT>GenPredicate ( ) , false ) ; if ( EnableLoopResched ) addPass ( create<ISA_LIT>LoopRescheduling ( ) , false ) ; if ( ! DisableHSDR ) addPass ( create<ISA_LIT>SplitDoubleRegs ( ) ) ; if ( EnableBitSimplify ) addPass ( create<ISA_LIT>BitSimplify ( ) , false ) ; addPass ( create<ISA_LIT>Peephole ( ) ) ; printAndVerify ( <STR_LIT> ) ; if ( EnableGenInsert ) addPass ( create<ISA_LIT>GenInsert ( ) , false ) ; if ( EnableEarlyIf ) addPass ( create<ISA_LIT>EarlyIfConversion ( ) , false ) ; }


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; addPass ( createAtomicExpandPass ( TM ) ) ;


<s> void <ISA_LIT>PassConfig :: addPostRegAlloc ( ) {

if ( getOptLevel ( ) != CodeGenOpt :: None ) {


<s> void <ISA_LIT>PassConfig :: addPostRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableRDFOpt ) addPass ( create<ISA_LIT>RDFOpt ( ) ) ; if ( ! Disable<ISA_LIT>CFGOpt ) addPass ( create<ISA_LIT>CFGOptimizer ( ) , false ) ;

if ( ! DisableAModeOpt ) addPass ( create<ISA_LIT>OptAddrMode ( ) , false ) ;


<s> if ( ! NoOpt ) addPass ( create<ISA_LIT>NewValueJump ( ) , false ) ; addPass ( create<ISA_LIT>BranchRelaxation ( ) , false ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) , false ) ; if ( EnableGenMux ) addPass ( create<ISA_LIT>GenMux ( ) , false ) ;


<s> if ( ! NoOpt ) addPass ( create<ISA_LIT>NewValueJump ( ) , false ) ; addPass ( create<ISA_LIT>BranchRelaxation ( ) , false ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) , false ) ;

if ( EnableGenMux ) addPass ( create<ISA_LIT>GenMux ( ) , false ) ;


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableExpandCondsets ) { Pass * Exp = create<ISA_LIT>ExpandCondsets ( ) ; insertPass ( & RegisterCoalescerID , IdentifyingPassPtr ( Exp ) ) ; }

if ( ! DisableStoreWidening ) addPass ( create<ISA_LIT>StoreWidening ( ) , false ) ;


<s> addPass ( create<ISA_LIT>CopyToCombine ( ) , false ) ;

if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID , false ) ;


<s> void <ISA_LIT>PassConfig :: addPreSched2 ( ) { addPass ( create<ISA_LIT>CopyToCombine ( ) , false ) ;


<s> return new VLIWMachineScheduler ( C , make_unique < ConvergingVLIWScheduler > ( ) ) ;


<s> static Reloc :: Model getEffectiveRelocModel ( Optional < Reloc :: Model > RM ) {

if ( ! RM . hasValue ( ) ) return Reloc :: Static ;


<s> return getTM < <ISA_LIT>TargetMachine > ( ) ;


<s> <ISA_LIT>TargetObjectFile * getObjFileLowering ( ) const override { return static_cast < <ISA_LIT>TargetObjectFile * > ( TLOF . get ( ) ) ;


<s> return static_cast < <ISA_LIT>TargetObjectFile * > ( TLOF . get ( ) ) ;


<s> auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this ) ; }


<s> return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ; } ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> void LLVMInitialize<ISA_LIT>Target ( ) {

RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target ) ;


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target ) ;


<s> <ISA_LIT>TargetMachine :: ~ <ISA_LIT>TargetMachine ( ) {


<s> virtual const <ISA_LIT>FrameLowering * getFrameLowering ( ) const {


<s> virtual const <ISA_LIT>InstrInfo * getInstrInfo ( ) const { return & InstrInfo ;


<s> virtual const InstrItineraryData * getInstrItineraryData ( ) const {


<s> virtual const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ;


<s> virtual const ScalarTargetTransformInfo * getScalarTargetTransformInfo ( ) const {


<s> virtual const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const {


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const {


<s> addPass ( create<ISA_LIT>Packetizer ( NoOpt ) , false ) ; if ( EnableVectorPrint ) addPass ( create<ISA_LIT>VectorPrint ( ) , false ) ;

addPass ( create<ISA_LIT>CallFrameInformation ( ) , false ) ;


<s> addPass ( create<ISA_LIT>BranchRelaxation ( ) ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) ) ; if ( EnableGenMux ) addPass ( create<ISA_LIT>GenMux ( ) ) ; } addPass ( create<ISA_LIT>Packetizer ( NoOpt ) , false ) ; if ( EnableVectorPrint ) addPass ( create<ISA_LIT>VectorPrint ( ) , false ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , <STR_LIT> <STR_LIT> <STR_LIT> , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , ( <ISA_LIT>NoOpt ? CodeGenOpt :: None : OL ) ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) { initialize<ISA_LIT>ExpandCondsetsPass ( * PassRegistry :: getPassRegistry ( ) ) ; initAsmInfo ( ) ;


<s> addPass ( createDeadCodeEliminationPass ( ) ) ; } addPass ( createAtomicExpandPass ( ) ) ; if ( ! NoOpt ) {

if ( EnableInitialCFGCleanup ) addPass ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . forwardSwitchCondToPhi ( true ) . convertSwitchToLookupTable ( true ) . needCanonicalLoops ( false ) . hoistCommonInsts ( true ) . sinkCommonInsts ( true ) ) ) ;


<s> TargetPassConfig :: addIRPasses ( ) ; bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) { if ( EnableInstSimplify ) addPass ( createInstSimplifyLegacyPass ( ) ) ; addPass ( createDeadCodeEliminationPass ( ) ) ; } addPass ( createAtomicExpandPass ( ) ) ; if ( ! NoOpt ) { if ( EnableInitialCFGCleanup ) addPass ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . forwardSwitchCondToPhi ( true ) . convertSwitchToLookupTable ( true ) . needCanonicalLoops ( false ) . hoistCommonInsts ( true ) . sinkCommonInsts ( true ) ) ) ; if ( EnableLoopPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ;

if ( EnableVectorCombine ) addPass ( create<ISA_LIT>VectorCombineLegacyPass ( ) ) ;


<s> bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( create<ISA_LIT>NewValueJump ( ) ) ; addPass ( create<ISA_LIT>BranchRelaxation ( ) ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) ) ; if ( EnableGenMux ) addPass ( create<ISA_LIT>GenMux ( ) ) ; }

addPass ( create<ISA_LIT>Packetizer ( NoOpt ) ) ;


<s> PMB . addExtension ( PassManagerBuilder :: EP_LoopOptimizerEnd , [ & ] ( const PassManagerBuilder & , legacy :: PassManagerBase & PM ) {


<s> static ScheduleDAGInstrs * createVLIWMachineSched ( MachineSchedContext * C ) { ScheduleDAGMILive * DAG = new VLIWMachineScheduler ( C , std :: make_unique < <ISA_LIT>ConvergingVLIWScheduler > ( ) ) ; DAG -> addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: UsrOverflowMutation > ( ) ) ; DAG -> addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: HVXMemLatencyMutation > ( ) ) ; DAG -> addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: CallMutation > ( ) ) ; DAG -> addMutation ( createCopyConstrainDAGMutation ( DAG -> TII , DAG -> TRI ) ) ;


<s> static ScheduleDAGInstrs * createVLIWMachineSched ( MachineSchedContext * C ) { ScheduleDAGMILive * DAG = new VLIWMachineScheduler ( C , std :: make_unique < <ISA_LIT>ConvergingVLIWScheduler > ( ) ) ; DAG -> addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: UsrOverflowMutation > ( ) ) ; DAG -> addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: HVXMemLatencyMutation > ( ) ) ;

DAG -> addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: CallMutation > ( ) ) ;


<s> Attribute FSAttr = FnAttrs . getFnAttr ( <STR_LIT> ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; if ( F . getFnAttribute ( <STR_LIT> ) . getValueAsBool ( ) ) FS = FS . empty ( ) ? <STR_LIT> : <STR_LIT> + FS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this ) ; } return I . get ( ) ;


<s> PB . registerLoopOptimizerEndEPCallback ( [ = ] ( LoopPassManager & LPM , OptimizationLevel Level ) { LPM . addPass ( <ISA_LIT>VectorLoopCarriedReusePass ( ) ) ;


<s> addPass ( createAtomicExpandPass ( ) ) ; if ( ! NoOpt ) { if ( EnableLoopPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ;

if ( EnableCommGEP ) addPass ( create<ISA_LIT>CommonGEP ( ) ) ;


<s> if ( EnableGenMux ) addPass ( create<ISA_LIT>GenMux ( ) ) ; addPass ( create<ISA_LIT>Packetizer ( ) , false ) ; } if ( EnableVectorPrint ) addPass ( create<ISA_LIT>VectorPrint ( ) , false ) ; addPass ( create<ISA_LIT>CallFrameInformation ( ) , false ) ;


<s> if ( EnableExpandCondsets ) insertPass ( & RegisterCoalescerID , & <ISA_LIT>ExpandCondsetsID ) ; if ( ! DisableStoreWidening ) addPass ( create<ISA_LIT>StoreWidening ( ) ) ; if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>HardwareLoops ( ) ) ; } if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Default ) addPass ( & MachinePipelinerID ) ;


<s> void <ISA_LIT>TargetMachine :: adjustPassManager ( PassManagerBuilder & PMB ) { PMB . addExtension ( PassManagerBuilder :: EP_LateLoopOptimizations , [ & ] ( const PassManagerBuilder & , legacy :: PassManagerBase & PM ) { PM . add ( create<ISA_LIT>LoopIdiomPass ( ) ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , <STR_LIT> <STR_LIT> <STR_LIT> , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , CM , ( <ISA_LIT>NoOpt ? CodeGenOpt :: None : OL ) ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) { initialize<ISA_LIT>ExpandCondsetsPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , <STR_LIT> <STR_LIT> <STR_LIT> , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , CM , ( <ISA_LIT>NoOpt ? CodeGenOpt :: None : OL ) ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) { initialize<ISA_LIT>ExpandCondsetsPass ( * PassRegistry :: getPassRegistry ( ) ) ; initAsmInfo ( ) ;


initialize<ISA_LIT>OptAddrModePass ( PR ) ;


<s> if ( ! NoOpt ) addPass ( create<ISA_LIT>NewValueJump ( ) , false ) ; addPass ( create<ISA_LIT>ExpandPredSpillCode ( ) , false ) ; addPass ( create<ISA_LIT>SplitTFRCondSets ( ) , false ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) , false ) ; addPass ( create<ISA_LIT>Packetizer ( ) , false ) ; }


<s> bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ;

if ( ! NoOpt ) addPass ( create<ISA_LIT>NewValueJump ( ) , false ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) { if ( Disable<ISA_LIT>MISched ) disablePass ( & MachineSchedulerID ) ; else enablePass ( & MachineSchedulerID ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , DL ( <STR_LIT> ) , Subtarget ( TT , CPU , FS , * this ) {


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) { PM . add ( createConstantPropagationPass ( ) ) ; PM . add ( createLoopSimplifyPass ( ) ) ; PM . add ( createDeadCodeEliminationPass ( ) ) ; PM . add ( createConstantPropagationPass ( ) ) ;


<s> PM . add ( createLoopSimplifyPass ( ) ) ; PM . add ( createDeadCodeEliminationPass ( ) ) ; PM . add ( createConstantPropagationPass ( ) ) ;


<s> bool <ISA_LIT>PassConfig :: addPostRegAlloc ( ) {

const <ISA_LIT>TargetMachine & TM = get<ISA_LIT>TargetMachine ( ) ;


<s> bool <ISA_LIT>PassConfig :: addPostRegAlloc ( ) { const <ISA_LIT>TargetMachine & TM = get<ISA_LIT>TargetMachine ( ) ;

if ( getOptLevel ( ) != CodeGenOpt :: None ) if ( ! Disable<ISA_LIT>CFGOpt ) addPass ( create<ISA_LIT>CFGOptimizer ( TM ) ) ;


<s> bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( create<ISA_LIT>NewValueJump ( ) ) ; addPass ( create<ISA_LIT>ExpandPredSpillCode ( TM ) ) ; addPass ( create<ISA_LIT>SplitTFRCondSets ( TM ) ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) ) ; addPass ( create<ISA_LIT>Packetizer ( ) ) ; } return false ;


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>HardwareLoops ( ) ) ; return false ;


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID ) ;

if ( ! TLOF . IsSmallDataEnabled ( ) ) {


<s> virtual ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const { return createVLIWMachineSched ( C ) ;


<s> static ScheduleDAGInstrs * createVLIWMachineSched ( MachineSchedContext * C ) { return new VLIWMachineScheduler ( C , new ConvergingVLIWScheduler ( ) ) ;


<s> return new VLIWMachineScheduler ( C , new ConvergingVLIWScheduler ( ) ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DL ( <STR_LIT> ) , Subtarget ( TT , CPU , FS ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) , InstrItins ( & Subtarget . getInstrItineraryData ( ) ) { setMCUseCFI ( false ) ;


<s> PM . add ( create<ISA_LIT>RemoveExtendOps ( get<ISA_LIT>TargetMachine ( ) ) ) ;

PM . add ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> PM . add ( create<ISA_LIT>CFGOptimizer ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> PM . add ( create<ISA_LIT>ExpandPredSpillCode ( get<ISA_LIT>TargetMachine ( ) ) ) ;

PM . add ( create<ISA_LIT>SplitTFRCondSets ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> PM . add ( create<ISA_LIT>FixupHwLoops ( ) ) ; } PM . add ( create<ISA_LIT>ExpandPredSpillCode ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> PM . add ( create<ISA_LIT>HardwareLoops ( ) ) ; }


<s> bool <ISA_LIT>PassConfig :: addPreSched2 ( ) { addPass ( IfConverterID ) ;


<s> const DataLayout * getDataLayout ( ) const override { return & DL ;


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const override {


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return InstrItins ;


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override {


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DataLayout ( <STR_LIT> ) , Subtarget ( TT , CPU , FS ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) , InstrItins ( & Subtarget . getInstrItineraryData ( ) ) {


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableRDFOpt ) addPass ( create<ISA_LIT>RDFOpt ( ) ) ; if ( ! Disable<ISA_LIT>CFGOpt ) addPass ( create<ISA_LIT>CFGOptimizer ( ) , false ) ;


<s> if ( ! NoOpt ) { if ( EnableGenPred ) addPass ( create<ISA_LIT>GenPredicate ( ) , false ) ; addPass ( create<ISA_LIT>Peephole ( ) ) ; printAndVerify ( <STR_LIT> ) ; if ( EnableGenInsert ) addPass ( create<ISA_LIT>GenInsert ( ) , false ) ;

if ( EnableEarlyIf ) addPass ( create<ISA_LIT>EarlyIfConversion ( ) , false ) ;


<s> if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) , false ) ;

if ( EnableGenMux ) addPass ( create<ISA_LIT>GenMux ( ) , false ) ;


<s> bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( create<ISA_LIT>NewValueJump ( ) , false ) ;

addPass ( create<ISA_LIT>ExpandPredSpillCode ( ) , false ) ;


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>HardwareLoops ( ) , false ) ;


<s> void <ISA_LIT>PassConfig :: addPreRegAlloc ( ) {

if ( getOptLevel ( ) != CodeGenOpt :: None ) if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>HardwareLoops ( ) , false ) ;


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & ) const override {


<s> if ( ! NoOpt ) { addPass ( createConstantPropagationPass ( ) ) ; addPass ( createDeadCodeEliminationPass ( ) ) ; } addPass ( createAtomicExpandPass ( ) ) ; if ( ! NoOpt ) { if ( EnableLoopPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableCommGEP ) addPass ( create<ISA_LIT>CommonGEP ( ) ) ;

if ( EnableGenExtract ) addPass ( create<ISA_LIT>GenExtract ( ) ) ;


<s> if ( ! NoOpt ) { addPass ( createConstantPropagationPass ( ) ) ; addPass ( createDeadCodeEliminationPass ( ) ) ; } addPass ( createAtomicExpandPass ( ) ) ; if ( ! NoOpt ) { if ( EnableLoopPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ;


<s> addPass ( create<ISA_LIT>RemoveExtendOps ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ;

addPass ( create<ISA_LIT>Peephole ( ) ) ;


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>RemoveExtendOps ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>Peephole ( ) ) ; return false ;


<s> } addPass ( create<ISA_LIT>NewValueJump ( ) ) ; addPass ( create<ISA_LIT>ExpandPredSpillCode ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>SplitTFRCondSets ( get<ISA_LIT>TargetMachine ( ) ) ) ;

addPass ( create<ISA_LIT>Packetizer ( ) ) ;


addPass ( create<ISA_LIT>HardwareLoops ( ) ) ;


<s> bool <ISA_LIT>PassConfig :: addPreSched2 ( ) { addPass ( & IfConverterID ) ; return true ;


<s> bool <ISA_LIT>PassConfig :: addPreSched2 ( ) { addPass ( & IfConverterID ) ;


<s> PM . add ( createConstantPropagationPass ( ) ) ; PM . add ( createLoopSimplifyPass ( ) ) ; PM . add ( createDeadCodeEliminationPass ( ) ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DL ( <STR_LIT> <STR_LIT> <STR_LIT> ) , Subtarget ( TT , CPU , FS ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) , InstrItins ( & Subtarget . getInstrItineraryData ( ) ) , STTI ( & TLInfo ) , VTTI ( & TLInfo ) { setMCUseCFI ( false ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DL ( <STR_LIT> <STR_LIT> <STR_LIT> ) , Subtarget ( TT , CPU , FS ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) , InstrItins ( & Subtarget . getInstrItineraryData ( ) ) {


<s> TargetPassConfig :: addIRPasses ( ) ; bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) { if ( EnableInstSimplify ) addPass ( createInstSimplifyLegacyPass ( ) ) ; addPass ( createDeadCodeEliminationPass ( ) ) ; } addPass ( createAtomicExpandPass ( ) ) ; if ( ! NoOpt ) { if ( EnableInitialCFGCleanup ) addPass ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . forwardSwitchCondToPhi ( true ) . convertSwitchRangeToICmp ( true ) . convertSwitchToLookupTable ( true ) . needCanonicalLoops ( false ) . hoistCommonInsts ( true ) . sinkCommonInsts ( true ) ) ) ; if ( EnableLoopPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableVectorCombine ) addPass ( create<ISA_LIT>VectorCombineLegacyPass ( ) ) ;

if ( EnableCommGEP ) addPass ( create<ISA_LIT>CommonGEP ( ) ) ;


<s> TargetTransformInfo <ISA_LIT>TargetMachine :: getTargetTransformInfo ( const Function & F ) const {

return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ;


<s> static ScheduleDAGInstrs * createVLIWMachineSched ( MachineSchedContext * C ) { ScheduleDAGMILive * DAG = new VLIWMachineScheduler ( C , std :: make_unique < ConvergingVLIWScheduler > ( ) ) ; DAG -> addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: UsrOverflowMutation > ( ) ) ; DAG -> addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: HVXMemLatencyMutation > ( ) ) ;

DAG -> addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: CallMutation > ( ) ) ;


<s> DAG -> addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: HVXMemLatencyMutation > ( ) ) ; DAG -> addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: CallMutation > ( ) ) ;

DAG -> addMutation ( createCopyConstrainDAGMutation ( DAG -> TII , DAG -> TRI ) ) ;


<s> Attribute CPUAttr = FnAttrs . getAttribute ( AttributeList :: FunctionIndex , <STR_LIT> ) ; Attribute FSAttr = FnAttrs . getAttribute ( AttributeList :: FunctionIndex , <STR_LIT> ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; if ( F . getFnAttribute ( <STR_LIT> ) . getValueAsBool ( ) ) FS = FS . empty ( ) ? <STR_LIT> : <STR_LIT> + FS ; auto & I = SubtargetMap [ CPU + FS ] ;


<s> PB . registerLoopOptimizerEndEPCallback ( [ = ] ( LoopPassManager & LPM , PassBuilder :: OptimizationLevel Level ) { LPM . addPass ( <ISA_LIT>VectorLoopCarriedReusePass ( ) ) ;


<s> addPass ( create<ISA_LIT>ISelDag ( TM , getOptLevel ( ) ) ) ; if ( ! NoOpt ) { if ( EnableGenPred ) addPass ( create<ISA_LIT>GenPredicate ( ) , false ) ; if ( EnableLoopResched ) addPass ( create<ISA_LIT>LoopRescheduling ( ) , false ) ;

if ( ! DisableHSDR ) addPass ( create<ISA_LIT>SplitDoubleRegs ( ) ) ;


<s> if ( ! NoOpt ) { if ( EnableGenPred ) addPass ( create<ISA_LIT>GenPredicate ( ) , false ) ; if ( EnableLoopResched ) addPass ( create<ISA_LIT>LoopRescheduling ( ) , false ) ; if ( ! DisableHSDR ) addPass ( create<ISA_LIT>SplitDoubleRegs ( ) ) ;

if ( EnableBitSimplify ) addPass ( create<ISA_LIT>BitSimplify ( ) , false ) ;


<s> if ( EnableCommGEP ) addPass ( create<ISA_LIT>CommonGEP ( ) ) ; if ( EnableGenExtract ) addPass ( create<ISA_LIT>GenExtract ( ) ) ;


<s> if ( ! NoOpt ) { if ( EnableLoopPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ;


<s> if ( EnableGenMux ) addPass ( create<ISA_LIT>GenMux ( ) , false ) ; addPass ( create<ISA_LIT>Packetizer ( ) , false ) ; } if ( EnableVectorPrint ) addPass ( create<ISA_LIT>VectorPrint ( ) , false ) ; addPass ( create<ISA_LIT>CallFrameInformation ( ) , false ) ;


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID ) ; addPass ( create<ISA_LIT>SplitConst32AndConst64 ( TM ) ) ; printAndVerify ( <STR_LIT> ) ; return true ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this ) {


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo ( ) ;


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableExpandCondsets ) insertPass ( & RegisterCoalescerID , & <ISA_LIT>ExpandCondsetsID ) ; if ( ! DisableStoreWidening ) addPass ( create<ISA_LIT>StoreWidening ( ) , false ) ; if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>HardwareLoops ( ) , false ) ;


<s> if ( ! DisableStoreWidening ) addPass ( create<ISA_LIT>StoreWidening ( ) , false ) ;

if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>HardwareLoops ( ) , false ) ;


<s> void LLVMInitialize<ISA_LIT>Target ( ) {

RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> AttributeList FnAttrs = F . getAttributes ( ) ; Attribute CPUAttr = FnAttrs . getAttribute ( AttributeList :: FunctionIndex , <STR_LIT> ) ; Attribute FSAttr = FnAttrs . getAttribute ( AttributeList :: FunctionIndex , <STR_LIT> ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; if ( FnAttrs . hasFnAttribute ( <STR_LIT> ) && F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ) FS = FS . empty ( ) ? <STR_LIT> : <STR_LIT> + FS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) {


<s> } ) ; PB . registerOptimizerLastEPCallback ( [ = ] ( ModulePassManager & MPM , PassBuilder :: OptimizationLevel Level ) { LoopPassManager LPM ( DebugPassManager ) ; FunctionPassManager FPM ( DebugPassManager ) ; LPM . addPass ( <ISA_LIT>VectorLoopCarriedReusePass ( ) ) ; FPM . addPass ( createFunctionToLoopPassAdaptor ( std :: move ( LPM ) ) ) ; MPM . addPass ( createModuleToFunctionPassAdaptor ( std :: move ( FPM ) ) ) ;


<s> PB . registerLateLoopOptimizationsEPCallback ( [ = ] ( LoopPassManager & LPM , PassBuilder :: OptimizationLevel Level ) { LPM . addPass ( <ISA_LIT>LoopIdiomRecognitionPass ( ) ) ; } ) ; PB . registerOptimizerLastEPCallback ( [ = ] ( ModulePassManager & MPM , PassBuilder :: OptimizationLevel Level ) { LoopPassManager LPM ( DebugPassManager ) ; FunctionPassManager FPM ( DebugPassManager ) ; LPM . addPass ( <ISA_LIT>VectorLoopCarriedReusePass ( ) ) ; FPM . addPass ( createFunctionToLoopPassAdaptor ( std :: move ( LPM ) ) ) ;

MPM . addPass ( createModuleToFunctionPassAdaptor ( std :: move ( FPM ) ) ) ;


<s> addPass ( createDeadCodeEliminationPass ( ) ) ; } addPass ( createAtomicExpandPass ( ) ) ; if ( ! NoOpt ) {

if ( EnableInitialCFGCleanup ) addPass ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . forwardSwitchCondToPhi ( true ) . convertSwitchToLookupTable ( true ) . needCanonicalLoops ( false ) . hoistCommonInsts ( true ) . sinkCommonInsts ( true ) ) ) ;


<s> Attribute CPUAttr = FnAttrs . getAttribute ( AttributeList :: FunctionIndex , <STR_LIT> ) ; Attribute FSAttr = FnAttrs . getAttribute ( AttributeList :: FunctionIndex , <STR_LIT> ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; if ( FnAttrs . hasFnAttribute ( <STR_LIT> ) && F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ) FS = FS . empty ( ) ? <STR_LIT> : <STR_LIT> + FS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) {


<s> if ( FnAttrs . hasFnAttribute ( <STR_LIT> ) && F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ) FS = FS . empty ( ) ? <STR_LIT> : <STR_LIT> + FS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this ) ; } return I . get ( ) ;


initialize<ISA_LIT>NewValueJumpPass ( PR ) ;


initialize<ISA_LIT>OptAddrModePass ( PR ) ;


<s> if ( EnableGenPred ) addPass ( create<ISA_LIT>GenPredicate ( ) ) ; if ( EnableLoopResched ) addPass ( create<ISA_LIT>LoopRescheduling ( ) ) ; if ( ! DisableHSDR ) addPass ( create<ISA_LIT>SplitDoubleRegs ( ) ) ; if ( EnableBitSimplify ) addPass ( create<ISA_LIT>BitSimplify ( ) ) ; addPass ( create<ISA_LIT>Peephole ( ) ) ; printAndVerify ( <STR_LIT> ) ;


<s> if ( ! NoOpt ) addPass ( create<ISA_LIT>OptimizeSZextends ( ) ) ; addPass ( create<ISA_LIT>ISelDag ( TM , getOptLevel ( ) ) ) ; if ( ! NoOpt ) { if ( EnableGenPred ) addPass ( create<ISA_LIT>GenPredicate ( ) ) ; if ( EnableLoopResched ) addPass ( create<ISA_LIT>LoopRescheduling ( ) ) ; if ( ! DisableHSDR ) addPass ( create<ISA_LIT>SplitDoubleRegs ( ) ) ;

if ( EnableBitSimplify ) addPass ( create<ISA_LIT>BitSimplify ( ) ) ;


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ;

PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ;


initialize<ISA_LIT>PacketizerPass ( PR ) ;


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ; PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ;


<s> PM . add ( create<ISA_LIT>RemoveExtendOps ( * this ) ) ; PM . add ( create<ISA_LIT>ISelDag ( * this ) ) ; return false ;


<s> bool <ISA_LIT>TargetMachine :: addPostRegAlloc ( PassManagerBase & PM ) {

PM . add ( create<ISA_LIT>CFGOptimizer ( * this ) ) ;


<s> bool <ISA_LIT>TargetMachine :: addPreEmitPass ( PassManagerBase & PM ) { if ( ! DisableHardwareLoops ) { PM . add ( create<ISA_LIT>FixupHwLoops ( ) ) ; } PM . add ( create<ISA_LIT>ExpandPredSpillCode ( * this ) ) ; PM . add ( create<ISA_LIT>SplitTFRCondSets ( * this ) ) ;


<s> PM . add ( create<ISA_LIT>HardwareLoops ( ) ) ; } return false ;


<s> PM . add ( createIfConverterPass ( ) ) ; return true ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , TargetOptions Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DataLayout ( <STR_LIT> ) , Subtarget ( TT , CPU , FS ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) , InstrItins ( & Subtarget . getInstrItineraryData ( ) ) {


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , TargetOptions Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DataLayout ( <STR_LIT> ) , Subtarget ( TT , CPU , FS ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) , InstrItins ( & Subtarget . getInstrItineraryData ( ) ) { setMCUseCFI ( false ) ;


<s> PM -> add ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; PM -> add ( create<ISA_LIT>Peephole ( ) ) ; return false ;


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { PM -> add ( create<ISA_LIT>RemoveExtendOps ( get<ISA_LIT>TargetMachine ( ) ) ) ; PM -> add ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ;

PM -> add ( create<ISA_LIT>Peephole ( ) ) ;


<s> } PM -> add ( create<ISA_LIT>ExpandPredSpillCode ( get<ISA_LIT>TargetMachine ( ) ) ) ; PM -> add ( create<ISA_LIT>SplitTFRCondSets ( get<ISA_LIT>TargetMachine ( ) ) ) ; return false ;


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass ( ) { if ( ! DisableHardwareLoops ) { PM -> add ( create<ISA_LIT>FixupHwLoops ( ) ) ; } PM -> add ( create<ISA_LIT>ExpandPredSpillCode ( get<ISA_LIT>TargetMachine ( ) ) ) ;

PM -> add ( create<ISA_LIT>SplitTFRCondSets ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> PM -> add ( create<ISA_LIT>HardwareLoops ( ) ) ;


<s> std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ;

I = std :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this ) ;


<s> } ) ; PB . registerLoopOptimizerEndEPCallback ( [ = ] ( LoopPassManager & LPM , PassBuilder :: OptimizationLevel Level ) {

LPM . addPass ( <ISA_LIT>VectorLoopCarriedReusePass ( ) ) ;


<s> } ) ; PB . registerLoopOptimizerEndEPCallback ( [ = ] ( LoopPassManager & LPM , PassBuilder :: OptimizationLevel Level ) { LPM . addPass ( <ISA_LIT>VectorLoopCarriedReusePass ( ) ) ;


<s> addPass ( create<ISA_LIT>ISelDag ( TM , getOptLevel ( ) ) ) ; if ( ! NoOpt ) {

if ( EnableGenPred ) addPass ( create<ISA_LIT>GenPredicate ( ) , false ) ;


<s> if ( ! NoOpt ) addPass ( create<ISA_LIT>RemoveExtendArgs ( TM ) ) ; addPass ( create<ISA_LIT>ISelDag ( TM , getOptLevel ( ) ) ) ; if ( ! NoOpt ) { if ( EnableGenPred ) addPass ( create<ISA_LIT>GenPredicate ( ) , false ) ; addPass ( create<ISA_LIT>Peephole ( ) ) ; printAndVerify ( <STR_LIT> ) ; if ( EnableGenInsert ) addPass ( create<ISA_LIT>GenInsert ( ) , false ) ;


<s> if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) , false ) ;

addPass ( create<ISA_LIT>Packetizer ( ) , false ) ;


<s> if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) , false ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , <STR_LIT> , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) {


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> TargetIRAnalysis <ISA_LIT>TargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( Function & F ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ; } ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , <STR_LIT> , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) {


<s> bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( create<ISA_LIT>NewValueJump ( ) , false ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) , false ) ; if ( EnableGenMux ) addPass ( create<ISA_LIT>GenMux ( ) , false ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , <STR_LIT> <STR_LIT> <STR_LIT> , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) { initAsmInfo ( ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , <STR_LIT> <STR_LIT> <STR_LIT> , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) {


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) if ( ! Disable<ISA_LIT>CFGOpt ) addPass ( create<ISA_LIT>CFGOptimizer ( TM ) , false ) ;


<s> void <ISA_LIT>PassConfig :: addPostRegAlloc ( ) { const <ISA_LIT>TargetMachine & TM = get<ISA_LIT>TargetMachine ( ) ;

if ( getOptLevel ( ) != CodeGenOpt :: None ) if ( ! Disable<ISA_LIT>CFGOpt ) addPass ( create<ISA_LIT>CFGOptimizer ( TM ) , false ) ;


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { const <ISA_LIT>TargetMachine & TM = get<ISA_LIT>TargetMachine ( ) ; bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ;

if ( ! NoOpt ) addPass ( create<ISA_LIT>NewValueJump ( ) , false ) ;


<s> void <ISA_LIT>PassConfig :: addPreSched2 ( ) {

const <ISA_LIT>TargetMachine & TM = get<ISA_LIT>TargetMachine ( ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo ( ) ;


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableExpandCondsets ) { Pass * Exp = create<ISA_LIT>ExpandCondsets ( ) ;

insertPass ( & RegisterCoalescerID , IdentifyingPassPtr ( Exp ) ) ;


<s> insertPass ( & RegisterCoalescerID , IdentifyingPassPtr ( Exp ) ) ; } if ( ! DisableStoreWidening ) addPass ( create<ISA_LIT>StoreWidening ( ) , false ) ;

if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>HardwareLoops ( ) , false ) ;


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; addPass ( create<ISA_LIT>Peephole ( ) ) ; return false ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DL ( <STR_LIT> <STR_LIT> <STR_LIT> ) , Subtarget ( TT , CPU , FS ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) , InstrItins ( & Subtarget . getInstrItineraryData ( ) ) {


<s> bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( create<ISA_LIT>RemoveExtendArgs ( TM ) ) ; addPass ( create<ISA_LIT>ISelDag ( TM , getOptLevel ( ) ) ) ; if ( ! NoOpt ) { addPass ( create<ISA_LIT>Peephole ( ) ) ; printAndVerify ( <STR_LIT> ) ; }


<s> bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( create<ISA_LIT>RemoveExtendArgs ( TM ) ) ; addPass ( create<ISA_LIT>ISelDag ( TM , getOptLevel ( ) ) ) ; if ( ! NoOpt ) { addPass ( create<ISA_LIT>Peephole ( ) ) ; printAndVerify ( <STR_LIT> ) ;


initialize<ISA_LIT>SplitDoubleRegsPass ( PR ) ;


<s> LPM . addPass ( <ISA_LIT>VectorLoopCarriedReusePass ( ) ) ; FPM . addPass ( createFunctionToLoopPassAdaptor ( std :: move ( LPM ) ) ) ;

MPM . addPass ( createModuleToFunctionPassAdaptor ( std :: move ( FPM ) ) ) ;


<s> void <ISA_LIT>TargetMachine :: registerPassBuilderCallbacks ( PassBuilder & PB , bool DebugPassManager ) {

PB . registerOptimizerLastEPCallback ( [ = ] ( ModulePassManager & MPM , PassBuilder :: OptimizationLevel Level ) {


<s> if ( EnableBitSimplify ) addPass ( create<ISA_LIT>BitSimplify ( ) ) ; addPass ( create<ISA_LIT>Peephole ( ) ) ; if ( ! DisableHCP ) { addPass ( create<ISA_LIT>ConstPropagationPass ( ) ) ; addPass ( & UnreachableMachineBlockElimID ) ; } if ( EnableGenInsert ) addPass ( create<ISA_LIT>GenInsert ( ) ) ; if ( EnableEarlyIf ) addPass ( create<ISA_LIT>EarlyIfConversion ( ) ) ; }


<s> } addPass ( createAtomicExpandPass ( ) ) ; if ( ! NoOpt ) { if ( EnableInitialCFGCleanup ) addPass ( createCFGSimplificationPass ( <NUM_LIT> , true , true , false , true ) ) ; if ( EnableLoopPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableCommGEP ) addPass ( create<ISA_LIT>CommonGEP ( ) ) ;

if ( EnableGenExtract ) addPass ( create<ISA_LIT>GenExtract ( ) ) ;


<s> if ( EnableRDFOpt ) addPass ( create<ISA_LIT>RDFOpt ( ) ) ; if ( ! Disable<ISA_LIT>CFGOpt ) addPass ( create<ISA_LIT>CFGOptimizer ( ) ) ;

if ( ! DisableAModeOpt ) addPass ( create<ISA_LIT>OptAddrMode ( ) ) ;


<s> if ( EnableRDFOpt ) addPass ( create<ISA_LIT>RDFOpt ( ) ) ; if ( ! Disable<ISA_LIT>CFGOpt ) addPass ( create<ISA_LIT>CFGOptimizer ( ) ) ; if ( ! DisableAModeOpt ) addPass ( create<ISA_LIT>OptAddrMode ( ) ) ;


<s> if ( ! NoOpt ) addPass ( create<ISA_LIT>NewValueJump ( ) ) ; addPass ( create<ISA_LIT>BranchRelaxation ( ) ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) ) ; if ( EnableGenMux ) addPass ( create<ISA_LIT>GenMux ( ) ) ; } addPass ( create<ISA_LIT>GatherPacketize ( ) , false ) ; if ( ! NoOpt ) addPass ( create<ISA_LIT>Packetizer ( ) , false ) ; if ( EnableVectorPrint ) addPass ( create<ISA_LIT>VectorPrint ( ) , false ) ;

addPass ( create<ISA_LIT>CallFrameInformation ( ) , false ) ;


<s> bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( create<ISA_LIT>NewValueJump ( ) ) ; addPass ( create<ISA_LIT>BranchRelaxation ( ) ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) ) ; if ( EnableGenMux ) addPass ( create<ISA_LIT>GenMux ( ) ) ; } addPass ( create<ISA_LIT>GatherPacketize ( ) , false ) ;

if ( ! NoOpt ) addPass ( create<ISA_LIT>Packetizer ( ) , false ) ;


<s> addPass ( create<ISA_LIT>CopyToCombine ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID ) ;

addPass ( create<ISA_LIT>SplitConst32AndConst64 ( ) ) ;


<s> void <ISA_LIT>TargetMachine :: adjustPassManager ( PassManagerBuilder & PMB ) { PMB . addExtension ( PassManagerBuilder :: EP_LateLoopOptimizations , [ & ] ( const PassManagerBuilder & , legacy :: PassManagerBase & PM ) { PM . add ( create<ISA_LIT>LoopIdiomPass ( ) ) ;


<s> PMB . addExtension ( PassManagerBuilder :: EP_LateLoopOptimizations , [ & ] ( const PassManagerBuilder & , legacy :: PassManagerBase & PM ) {

PM . add ( create<ISA_LIT>LoopIdiomPass ( ) ) ;


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( * this , PM ) ;


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) {

return new <ISA_LIT>PassConfig ( * this , PM ) ;


<s> DAG -> addMutation ( make_unique < <ISA_LIT>Subtarget :: HVXMemLatencyMutation > ( ) ) ; DAG -> addMutation ( make_unique < <ISA_LIT>Subtarget :: CallMutation > ( ) ) ;

DAG -> addMutation ( createCopyConstrainDAGMutation ( DAG -> TII , DAG -> TRI ) ) ;


<s> DAG -> addMutation ( make_unique < <ISA_LIT>Subtarget :: CallMutation > ( ) ) ;


<s> const DataLayout * getDataLayout ( ) const override { return getSubtargetImpl ( ) -> getDataLayout ( ) ;


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override { return getSubtargetImpl ( ) -> getInstrInfo ( ) ;


<s> return & getSubtargetImpl ( ) -> getInstrItineraryData ( ) ;


<s> return getSubtargetImpl ( ) -> getRegisterInfo ( ) ;


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return getSubtargetImpl ( ) -> getTargetLowering ( ) ;


<s> return getSubtargetImpl ( ) -> getTargetLowering ( ) ;


<s> TargetTransformInfo <ISA_LIT>TargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , <STR_LIT> <STR_LIT> <STR_LIT> , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveCodeModel ( CM ) , ( <ISA_LIT>NoOpt ? CodeGenOpt :: None : OL ) ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) {

initialize<ISA_LIT>ExpandCondsetsPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> if ( GO -> hasSection ( ) ) { StringRef Section = GO -> getSection ( ) ; if ( Section . contains ( <STR_LIT> ) ) return getContext ( ) . getELFSection ( GO -> getSection ( ) , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_EXECINSTR ) ;

if ( Section . contains ( <STR_LIT> ) ) return getContext ( ) . getELFSection ( GO -> getSection ( ) , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ;


<s> if ( ! Bb ) continue ; auto * UserFn = Bb -> getParent ( ) ; if ( ! ReturnFn ) ReturnFn = UserFn ; else if ( ReturnFn != UserFn ) return nullptr ; } return ReturnFn ;


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; }


<s> switch ( Size ) { default : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ;


<s> SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_HEX_GPREL ) ;


<s> SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_HEX_GPREL ) ;

SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_HEX_GPREL ) ;


<s> bool IsSmall = isSmallDataSection ( GVar -> getSection ( ) ) ; LLVM_DEBUG ( dbgs ( ) << ( IsSmall ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << GVar -> getSection ( ) << '\n' ) ; return IsSmall ; } if ( ! HaveSData ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( GVar -> isConstant ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } bool IsLocal = GVar -> hasLocalLinkage ( ) ; if ( ! StaticsInSData && IsLocal ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } Type * GType = GVar -> getValueType ( ) ; if ( isa < ArrayType > ( GType ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ;


<s> bool <ISA_LIT>TargetObjectFile :: isSmallDataEnabled ( const TargetMachine & TM ) const { return SmallDataThreshold > <NUM_LIT> && ! TM . isPositionIndependent ( ) ;


<s> return Sec . contains ( <STR_LIT> ) || Sec . contains ( <STR_LIT> ) || Sec . contains ( <STR_LIT> ) ;


<s> TRACE ( ( GO -> hasPrivateLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasLocalLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasInternalLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasExternalLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasCommonLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasCommonLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( Kind . isCommon ( ) ? <STR_LIT> : <STR_LIT> ) << ( Kind . isBSS ( ) ? <STR_LIT> : <STR_LIT> ) << ( Kind . isBSSLocal ( ) ? <STR_LIT> : <STR_LIT> ) ) ;

if ( EmitLutInText && GO -> getName ( ) . startswith ( <STR_LIT> ) ) {


<s> MCSection * <ISA_LIT>TargetObjectFile :: SelectSectionForGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const { TRACE ( <STR_LIT> << GO -> getName ( ) << <STR_LIT> ) ; TRACE ( <STR_LIT> << GO -> getSection ( ) << <STR_LIT> ) ; TRACE ( ( GO -> hasPrivateLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasLocalLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasInternalLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasExternalLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasCommonLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasCommonLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( Kind . isCommon ( ) ? <STR_LIT> : <STR_LIT> ) << ( Kind . isBSS ( ) ? <STR_LIT> : <STR_LIT> ) << ( Kind . isBSSLocal ( ) ? <STR_LIT> : <STR_LIT> ) ) ; if ( EmitLutInText && GO -> getName ( ) . startswith ( <STR_LIT> ) ) { if ( const Function * Fn = getLutUsedFunction ( GO ) ) return selectSectionForLookupTable ( GO , TM , Fn ) ; } if ( isGlobalInSmallSection ( GO , TM ) ) return selectSmallSectionForGlobal ( GO , Kind , TM ) ; if ( Kind . isCommon ( ) ) { return BSSSection ; } TRACE ( <STR_LIT> ) ;

return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GO , Kind , TM ) ;


<s> MCSection * <ISA_LIT>TargetObjectFile :: selectSectionForLookupTable ( const GlobalObject * GO , const TargetMachine & TM , const Function * Fn ) const { SectionKind Kind = SectionKind :: getText ( ) ;

if ( Fn -> hasSection ( ) ) return getExplicitSectionGlobal ( Fn , Kind , TM ) ;


<s> if ( Fn -> hasSection ( ) ) return getExplicitSectionGlobal ( Fn , Kind , TM ) ; const auto * FuncObj = dyn_cast < GlobalObject > ( Fn ) ; return SelectSectionForGlobal ( FuncObj , Kind , TM ) ;


<s> if ( Section . find ( <STR_LIT> ) != StringRef :: npos ) return getContext ( ) . getELFSection ( GO -> getSection ( ) , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_EXECINSTR ) ; if ( Section . find ( <STR_LIT> ) != StringRef :: npos ) return getContext ( ) . getELFSection ( GO -> getSection ( ) , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; }

if ( isGlobalInSmallSection ( GO , TM ) ) return selectSmallSectionForGlobal ( GO , Kind , TM ) ;


<s> unsigned SmallestElement = <NUM_LIT> ; if ( ! Ty ) return <NUM_LIT> ; switch ( Ty -> getTypeID ( ) ) { case Type :: StructTyID : { const StructType * STy = cast < const StructType > ( Ty ) ; for ( auto & E : STy -> elements ( ) ) { unsigned AtomicSize = getSmallestAddressableSize ( E , GV , TM ) ; if ( AtomicSize < SmallestElement ) SmallestElement = AtomicSize ; } return ( STy -> getNumElements ( ) == <NUM_LIT> ) ? <NUM_LIT> : SmallestElement ; } case Type :: ArrayTyID : { const ArrayType * ATy = cast < const ArrayType > ( Ty ) ; return getSmallestAddressableSize ( ATy -> getElementType ( ) , GV , TM ) ; } case Type :: VectorTyID : { const VectorType * PTy = cast < const VectorType > ( Ty ) ; return getSmallestAddressableSize ( PTy -> getElementType ( ) , GV , TM ) ; } case Type :: PointerTyID : case Type :: HalfTyID : case Type :: FloatTyID : case Type :: DoubleTyID : case Type :: IntegerTyID : { const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; return DL . getTypeAllocSize ( const_cast < Type * > ( Ty ) ) ; } case Type :: FunctionTyID : case Type :: VoidTyID : case Type :: X86_FP80TyID : case Type :: FP128TyID : case Type :: PPC_FP128TyID : case Type :: LabelTyID : case Type :: MetadataTyID : case Type :: X86_MMXTyID : case Type :: TokenTyID : return <NUM_LIT> ; } return <NUM_LIT> ;


<s> void <ISA_LIT>TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_HEX_GPREL ) ;


<s> SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_HEX_GPREL ) ; SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_HEX_GPREL ) ;


<s> const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GO ) ; if ( ! GVar ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( GVar -> hasSection ( ) ) { bool IsSmall = isSmallDataSection ( GVar -> getSection ( ) ) ; DEBUG ( dbgs ( ) << ( IsSmall ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << GVar -> getSection ( ) << '\n' ) ; return IsSmall ; } if ( GVar -> isConstant ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } bool IsLocal = GVar -> hasLocalLinkage ( ) ; if ( ! StaticsInSData && IsLocal ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } Type * GType = GVar -> getType ( ) ; if ( PointerType * PT = dyn_cast < PointerType > ( GType ) ) GType = PT -> getElementType ( ) ; if ( isa < ArrayType > ( GType ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( StructType * ST = dyn_cast < StructType > ( GType ) ) { if ( ST -> isOpaque ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ;


<s> return SmallDataThreshold > <NUM_LIT> ;


<s> return Sec . find ( <STR_LIT> ) != StringRef :: npos || Sec . find ( <STR_LIT> ) != StringRef :: npos || Sec . find ( <STR_LIT> ) != StringRef :: npos ;


<s> static bool isSmallDataSection ( StringRef Sec ) { if ( Sec . equals ( <STR_LIT> ) || Sec . equals ( <STR_LIT> ) || Sec . equals ( <STR_LIT> ) ) return true ; return Sec . find ( <STR_LIT> ) != StringRef :: npos || Sec . find ( <STR_LIT> ) != StringRef :: npos || Sec . find ( <STR_LIT> ) != StringRef :: npos ;


<s> TRACE ( <STR_LIT> << GO -> getName ( ) << <STR_LIT> ) ; TRACE ( <STR_LIT> << GO -> getSection ( ) << <STR_LIT> ) ; TRACE ( ( GO -> hasPrivateLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasLocalLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasInternalLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasExternalLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasCommonLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasCommonLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( Kind . isCommon ( ) ? <STR_LIT> : <STR_LIT> ) << ( Kind . isBSS ( ) ? <STR_LIT> : <STR_LIT> ) << ( Kind . isBSSLocal ( ) ? <STR_LIT> : <STR_LIT> ) ) ; if ( isGlobalInSmallSection ( GO , TM ) ) return selectSmallSectionForGlobal ( GO , Kind , TM ) ;


<s> if ( EmitUniquedSection ) { Name . append ( <STR_LIT> ) ; Name . append ( GO -> getName ( ) ) ; } TRACE ( <STR_LIT> << Name << <STR_LIT> ) ; return getContext ( ) . getELFSection ( Name . str ( ) , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_HEX_GPREL ) ; } if ( Kind . isCommon ( ) ) { if ( NoSmallDataSorting ) return BSSSection ; Twine Name = Twine ( <STR_LIT> ) + getSectionSuffixForSize ( Size ) ; TRACE ( <STR_LIT> << Name << <STR_LIT> ) ; return getContext ( ) . getELFSection ( Name . str ( ) , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_HEX_GPREL ) ; } if ( Kind . isMergeableConst ( ) ) { TRACE ( <STR_LIT> ) ; const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GO ) ; if ( GVar -> hasSection ( ) && isSmallDataSection ( GVar -> getSection ( ) ) ) Kind = SectionKind :: getData ( ) ; } if ( Kind . isData ( ) ) { if ( NoSmallDataSorting ) { TRACE ( <STR_LIT> ) ; return SmallDataSection ; } StringRef Prefix ( <STR_LIT> ) ; SmallString < <NUM_LIT> > Name ( Prefix ) ; Name . append ( getSectionSuffixForSize ( Size ) ) ; if ( EmitUniquedSection ) { Name . append ( <STR_LIT> ) ; Name . append ( GO -> getName ( ) ) ;


<s> } return ( STy -> getNumElements ( ) == <NUM_LIT> ) ? <NUM_LIT> : SmallestElement ; } case Type :: ArrayTyID : { const ArrayType * ATy = cast < const ArrayType > ( Ty ) ; return getSmallestAddressableSize ( ATy -> getElementType ( ) , GV , TM ) ; } case Type :: FixedVectorTyID : case Type :: ScalableVectorTyID : { const VectorType * PTy = cast < const VectorType > ( Ty ) ; return getSmallestAddressableSize ( PTy -> getElementType ( ) , GV , TM ) ; } case Type :: PointerTyID : case Type :: HalfTyID : case Type :: FloatTyID : case Type :: DoubleTyID : case Type :: IntegerTyID : { const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ;

return DL . getTypeAllocSize ( const_cast < Type * > ( Ty ) ) ;


<s> unsigned SmallestElement = <NUM_LIT> ; if ( ! Ty ) return <NUM_LIT> ; switch ( Ty -> getTypeID ( ) ) { case Type :: StructTyID : { const StructType * STy = cast < const StructType > ( Ty ) ; for ( auto & E : STy -> elements ( ) ) { unsigned AtomicSize = getSmallestAddressableSize ( E , GV , TM ) ; if ( AtomicSize < SmallestElement ) SmallestElement = AtomicSize ; } return ( STy -> getNumElements ( ) == <NUM_LIT> ) ? <NUM_LIT> : SmallestElement ; } case Type :: ArrayTyID : { const ArrayType * ATy = cast < const ArrayType > ( Ty ) ; return getSmallestAddressableSize ( ATy -> getElementType ( ) , GV , TM ) ; } case Type :: FixedVectorTyID : case Type :: ScalableVectorTyID : { const VectorType * PTy = cast < const VectorType > ( Ty ) ; return getSmallestAddressableSize ( PTy -> getElementType ( ) , GV , TM ) ; } case Type :: PointerTyID : case Type :: HalfTyID : case Type :: FloatTyID : case Type :: DoubleTyID : case Type :: IntegerTyID : { const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; return DL . getTypeAllocSize ( const_cast < Type * > ( Ty ) ) ; } case Type :: FunctionTyID : case Type :: VoidTyID : case Type :: BFloatTyID : case Type :: X86_FP80TyID : case Type :: FP128TyID : case Type :: PPC_FP128TyID : case Type :: LabelTyID : case Type :: MetadataTyID : case Type :: X86_MMXTyID : case Type :: TokenTyID :


<s> TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ;

SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ;


<s> void <ISA_LIT>TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ;


if ( Kind . isBSS ( ) || Kind . isDataNoRel ( ) || Kind . isCommon ( ) ) {


<s> SelectSectionForGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler * Mang , const TargetMachine & TM ) const { if ( Kind . isBSS ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallBSSSection ; if ( Kind . isDataNoRel ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallDataSection ;

return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GV , Kind , Mang , TM ) ;


<s> if ( Kind . isDataNoRel ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GV , Kind , Mang , TM ) ;


<s> const StructType * STy = cast < const StructType > ( Ty ) ; for ( auto & E : STy -> elements ( ) ) { unsigned AtomicSize = getSmallestAddressableSize ( E , GV , TM ) ; if ( AtomicSize < SmallestElement ) SmallestElement = AtomicSize ; } return ( STy -> getNumElements ( ) == <NUM_LIT> ) ? <NUM_LIT> : SmallestElement ; } case Type :: ArrayTyID : { const ArrayType * ATy = cast < const ArrayType > ( Ty ) ; return getSmallestAddressableSize ( ATy -> getElementType ( ) , GV , TM ) ; } case Type :: FixedVectorTyID : case Type :: ScalableVectorTyID : { const VectorType * PTy = cast < const VectorType > ( Ty ) ; return getSmallestAddressableSize ( PTy -> getElementType ( ) , GV , TM ) ; } case Type :: PointerTyID : case Type :: HalfTyID : case Type :: FloatTyID : case Type :: DoubleTyID : case Type :: IntegerTyID : { const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; return DL . getTypeAllocSize ( const_cast < Type * > ( Ty ) ) ; } case Type :: FunctionTyID : case Type :: VoidTyID : case Type :: BFloatTyID : case Type :: X86_FP80TyID : case Type :: FP128TyID : case Type :: PPC_FP128TyID : case Type :: LabelTyID : case Type :: MetadataTyID : case Type :: X86_MMXTyID :


<s> const ArrayType * ATy = cast < const ArrayType > ( Ty ) ; return getSmallestAddressableSize ( ATy -> getElementType ( ) , GV , TM ) ; } case Type :: FixedVectorTyID : case Type :: ScalableVectorTyID : { const VectorType * PTy = cast < const VectorType > ( Ty ) ; return getSmallestAddressableSize ( PTy -> getElementType ( ) , GV , TM ) ; } case Type :: PointerTyID : case Type :: HalfTyID : case Type :: FloatTyID : case Type :: DoubleTyID : case Type :: IntegerTyID : { const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; return DL . getTypeAllocSize ( const_cast < Type * > ( Ty ) ) ; } case Type :: FunctionTyID : case Type :: VoidTyID : case Type :: BFloatTyID : case Type :: X86_FP80TyID : case Type :: FP128TyID : case Type :: PPC_FP128TyID : case Type :: LabelTyID :


<s> bool <ISA_LIT>TargetObjectFile :: isGlobalInSmallSection ( const GlobalObject * GO , const TargetMachine & TM ) const { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << SmallDataThreshold << <STR_LIT> << GO -> getName ( ) << <STR_LIT> ) ; const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GO ) ; if ( ! GVar ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( GVar -> hasSection ( ) ) { bool IsSmall = isSmallDataSection ( GVar -> getSection ( ) ) ; LLVM_DEBUG ( dbgs ( ) << ( IsSmall ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << GVar -> getSection ( ) << '\n' ) ; return IsSmall ; } if ( GVar -> isConstant ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } bool IsLocal = GVar -> hasLocalLinkage ( ) ; if ( ! StaticsInSData && IsLocal ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } Type * GType = GVar -> getType ( ) ; if ( PointerType * PT = dyn_cast < PointerType > ( GType ) ) GType = PT -> getElementType ( ) ; if ( isa < ArrayType > ( GType ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( StructType * ST = dyn_cast < StructType > ( GType ) ) { if ( ST -> isOpaque ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } unsigned Size = GVar -> getParent ( ) -> getDataLayout ( ) . getTypeAllocSize ( GType ) ; if ( Size == <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( Size > SmallDataThreshold ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Size << '\n' ) ; return false ;


<s> bool <ISA_LIT>TargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( Kind . isBSS ( ) || Kind . isDataNoRel ( ) || Kind . isCommon ( ) ) { Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( GV -> getParent ( ) -> getDataLayout ( ) . getTypeAllocSize ( Ty ) ) ; }


<s> const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( Kind . isBSS ( ) || Kind . isDataNoRel ( ) || Kind . isCommon ( ) ) { Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( GV -> getParent ( ) -> getDataLayout ( ) . getTypeAllocSize ( Ty ) ) ; }


<s> if ( Kind . isBSS ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallBSSSection ; if ( Kind . isDataNoRel ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallDataSection ;


<s> MCSection * <ISA_LIT>TargetObjectFile :: SelectSectionForGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler & Mang , const TargetMachine & TM ) const { if ( Kind . isBSS ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallBSSSection ;

if ( Kind . isDataNoRel ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallDataSection ;


<s> if ( Kind . isBSS ( ) || Kind . isDataNoRel ( ) || Kind . isCommon ( ) ) { Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( TM . getSubtargetImpl ( ) -> getDataLayout ( ) -> getTypeAllocSize ( Ty ) ) ;


<s> IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( Kind . isBSS ( ) || Kind . isDataNoRel ( ) || Kind . isCommon ( ) ) { Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( TM . getSubtargetImpl ( ) -> getDataLayout ( ) -> getTypeAllocSize ( Ty ) ) ;


<s> InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ;


<s> SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ;


<s> if ( PointerType * PT = dyn_cast < PointerType > ( GType ) ) GType = PT -> getElementType ( ) ; if ( isa < ArrayType > ( GType ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( StructType * ST = dyn_cast < StructType > ( GType ) ) { if ( ST -> isOpaque ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } unsigned Size = GVar -> getParent ( ) -> getDataLayout ( ) . getTypeAllocSize ( GType ) ;