<s> FunctionPass * llvm :: create<ISA_LIT>RemoveExtendOps ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>RemoveExtendArgs ( ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>RemoveExtendOps ( <ISA_LIT>TargetMachine & TM ) {

return new <ISA_LIT>RemoveExtendArgs ( ) ;


<s> AU . addPreserved < MachineFunctionAnalysis > ( ) ;

FunctionPass :: getAnalysisUsage ( AU ) ;


<s> AU . addRequired < MachineFunctionAnalysis > ( ) ; AU . addPreserved < MachineFunctionAnalysis > ( ) ;


<s> <ISA_LIT>RemoveExtendArgs ( ) : FunctionPass ( ID ) {


<s> if ( ! isa < PointerType > ( Arg -> getType ( ) ) ) { for ( Instruction :: use_iterator UI = Arg -> use_begin ( ) ; UI != Arg -> use_end ( ) ; ) { if ( isa < SExtInst > ( * UI ) ) { Instruction * Use = cast < Instruction > ( * UI ) ; SExtInst * SI = new SExtInst ( Arg , Use -> getType ( ) ) ; assert ( EVT :: getEVT ( SI -> getType ( ) ) == ( EVT :: getEVT ( Use -> getType ( ) ) ) ) ; ++ UI ; Use -> replaceAllUsesWith ( SI ) ; Instruction * First = F . getEntryBlock ( ) . begin ( ) ;


<s> AU . addPreserved < MachineFunctionAnalysis > ( ) ; AU . addPreserved ( <STR_LIT> ) ; FunctionPass :: getAnalysisUsage ( AU ) ;


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineFunctionAnalysis > ( ) ; AU . addPreserved < MachineFunctionAnalysis > ( ) ; AU . addPreserved ( <STR_LIT> ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>RemoveExtendArgs ( const <ISA_LIT>TargetMachine & TM ) {


initialize<ISA_LIT>RemoveExtendArgsPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> assert ( EVT :: getEVT ( SI -> getType ( ) ) == ( EVT :: getEVT ( I -> getType ( ) ) ) ) ; ++ UI ; I -> replaceAllUsesWith ( SI ) ; Instruction * First = F . getEntryBlock ( ) . begin ( ) ; SI -> insertBefore ( First ) ; I -> eraseFromParent ( ) ; } else {


<s> Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; const char * SpecialMemcpyName = <STR_LIT> ; const MachineFunction & MF = DAG . getMachineFunction ( ) ; bool LongCalls = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . useLongCalls ( ) ;

unsigned Flags = LongCalls ? <STR_LIT> : <NUM_LIT> ;


<s> if ( AlwaysInline || ( Align & <NUM_LIT> ) != <NUM_LIT> || ! ConstantSize ) return SDValue ( ) ; uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; if ( SizeVal < <NUM_LIT> || ( SizeVal % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = * DAG . getSubtarget ( ) . getTargetLowering ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; const char * SpecialMemcpyName = <STR_LIT> ;

const MachineFunction & MF = DAG . getMachineFunction ( ) ;


<s> Args . push_back ( Entry ) ; const char * SpecialMemcpyName = <STR_LIT> ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMCPY ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getTargetExternalSymbol ( SpecialMemcpyName , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ;


<s> uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; if ( SizeVal < <NUM_LIT> || ( SizeVal % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = * DAG . getSubtarget ( ) . getTargetLowering ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; Entry . Node = Src ;


<s> ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( AlwaysInline || ( Align & <NUM_LIT> ) != <NUM_LIT> || ! ConstantSize ) return SDValue ( ) ; uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; if ( SizeVal < <NUM_LIT> || ( SizeVal % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = * DAG . getSubtarget ( ) . getTargetLowering ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; const char * SpecialMemcpyName = <STR_LIT> ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ;

CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMCPY ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getTargetExternalSymbol ( SpecialMemcpyName , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ;


<s> Args . push_back ( Entry ) ; const char * SpecialMemcpyName = <STR_LIT> ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMCPY ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getTargetExternalSymbol ( SpecialMemcpyName , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ;

std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ;


<s> const char * SpecialMemcpyName = <STR_LIT> ; const MachineFunction & MF = DAG . getMachineFunction ( ) ; bool LongCalls = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . useLongCalls ( ) ; unsigned Flags = LongCalls ? <STR_LIT> : <NUM_LIT> ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ;

CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMCPY ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getTargetExternalSymbol ( SpecialMemcpyName , TLI . getPointerTy ( DAG . getDataLayout ( ) ) , Flags ) , std :: move ( Args ) ) . setDiscardResult ( ) ;


<s> uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; if ( SizeVal < <NUM_LIT> || ( SizeVal % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = * DAG . getSubtarget ( ) . getTargetLowering ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; const char * SpecialMemcpyName = <STR_LIT> ; const MachineFunction & MF = DAG . getMachineFunction ( ) ; bool LongCalls = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . useLongCalls ( ) ; unsigned Flags = LongCalls ? <STR_LIT> : <NUM_LIT> ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMCPY ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getTargetExternalSymbol ( SpecialMemcpyName , TLI . getPointerTy ( DAG . getDataLayout ( ) ) , Flags ) , std :: move ( Args ) ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ;


<s> <ISA_LIT>SelectionDAGInfo :: <ISA_LIT>SelectionDAGInfo ( const <ISA_LIT>TargetMachine & TM ) : TargetSelectionDAGInfo ( TM ) {


<s> if ( ConstantSize ) { uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; if ( ( SizeVal > <NUM_LIT> ) && ( ( SizeVal % <NUM_LIT> ) == <NUM_LIT> ) ) flag_aligned_memcpy = true ; }


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { flag_aligned_memcpy = false ; if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) { ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( ConstantSize ) { uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; if ( ( SizeVal > <NUM_LIT> ) && ( ( SizeVal % <NUM_LIT> ) == <NUM_LIT> ) ) flag_aligned_memcpy = true ;


<s> <ISA_LIT>SelectionDAGInfo :: <ISA_LIT>SelectionDAGInfo ( const DataLayout & DL ) : TargetSelectionDAGInfo ( & DL ) {


<s> <ISA_LIT>SelectionDAGInfo :: ~ <ISA_LIT>SelectionDAGInfo ( ) {


<s> void <ISA_LIT>Shuffler :: append ( MCInst const & ID , MCInst const * Extender , unsigned S ) { <ISA_LIT>Instr PI ( & TUL , MCII , & ID , Extender , S ) ;


<s> <ISA_LIT>Instr PI ( & TUL , MCII , & ID , Extender , S ) ;


<s> bool bid ( unsigned B ) { unsigned b = B & ~ isSold ; if ( b ) {

for ( unsigned i = <NUM_LIT> ; i < HEXAGON_PACKET_SIZE ; ++ i ) if ( b & ( <NUM_LIT> << i ) ) {


<s> unsigned allBits = makeAllBits ( b , hvxInsts [ startIdx ] . Lanes ) ; if ( ( allBits & usedUnits ) == <NUM_LIT> ) { if ( checkHVXPipes ( hvxInsts , startIdx + <NUM_LIT> , usedUnits | allBits ) ) return true ; }


<s> Bid = B ? MAX / countPopulation ( B ) : <NUM_LIT> ;


<s> <ISA_LIT>CVIResource :: <ISA_LIT>CVIResource ( TypeUnitsAndLanes * TUL , MCInstrInfo const & MCII , unsigned s , MCInst const * id ) : <ISA_LIT>Resource ( s ) { unsigned T = <ISA_LIT>MCInstrInfo :: getType ( MCII , * id ) ;


<s> <ISA_LIT>UnitAuction ( unsigned cs = <NUM_LIT> ) : isSold ( cs ) {


<s> static unsigned makeAllBits ( unsigned startBit , unsigned Lanes ) { for ( unsigned i = <NUM_LIT> ; i < Lanes ; ++ i ) startBit = ( startBit << <NUM_LIT> ) | startBit ; return startBit ;


<s> for ( unsigned i = <NUM_LIT> ; i < Lanes ; ++ i ) startBit = ( startBit << <NUM_LIT> ) | startBit ; return startBit ;


<s> void <ISA_LIT>Shuffler :: reportError ( Twine const & Msg ) { if ( ReportErrors ) { for ( auto const & I : AppliedRestrictions ) {

auto SM = Context . getSourceManager ( ) ;


<s> if ( SM ) SM -> PrintMessage ( I . first , SourceMgr :: DK_Note , I . second ) ; } Context . reportError ( Loc , Msg ) ;


<s> if ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , Inst ) . mayStore ( ) ) { unsigned Units = ISJ -> Core . getUnits ( ) ; if ( Units & <NUM_LIT> ) { AppliedRestriction = true ; AppliedRestrictions . push_back ( std :: make_pair ( Inst . getLoc ( ) , <STR_LIT> ) ) ; ISJ -> Core . setUnits ( Units & ~ <NUM_LIT> ) ; } } } if ( AppliedRestriction ) AppliedRestrictions . push_back ( std :: make_pair ( RestrictLoc , <STR_LIT> ) ) ;


<s> ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_MPY0 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = ( CPU == <STR_LIT> ) ? UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) : UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ;

( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_MPY0 , <NUM_LIT> ) ;


<s> ( * TUL ) [ <STR_LIT> ] = ( CPU == <STR_LIT> ) ? UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) : UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ;


<s> if ( Key == <NUM_LIT> || Units == <NUM_LIT> || ( SlotWeight * s >= <NUM_LIT> ) ) return Weight = <NUM_LIT> ; unsigned Ctpop = countPopulation ( Units ) ; unsigned Cttz = countTrailingZeros ( Units ) ;

Weight = ( <NUM_LIT> << ( SlotWeight * s ) ) * ( ( MaskWeight - Ctpop ) << Cttz ) ;


<s> unsigned Ctpop = countPopulation ( Units ) ; unsigned Cttz = countTrailingZeros ( Units ) ;


<s> void <ISA_LIT>Shuffler :: append ( MCInst const * ID , MCInst const * Extender , unsigned S , bool X ) { <ISA_LIT>Instr PI ( MCII , ID , Extender , S , X ) ; Packet . push_back ( PI ) ;


<s> Scores [ i ] += <ISA_LIT>Bid ( b ) ; isSold |= Scores [ i ] . isSold ( ) << i ; } return true ;


<s> if ( b ) { for ( unsigned i = <NUM_LIT> ; i < HEXAGON_PACKET_SIZE ; ++ i ) if ( b & ( <NUM_LIT> << i ) ) { Scores [ i ] += <ISA_LIT>Bid ( b ) ; isSold |= Scores [ i ] . isSold ( ) << i ;


<s> MCInst const * getExtender ( ) const {


<s> Valid = true ; setUnits ( ( * TUL ) [ T ] . first ) ; setLanes ( ( * TUL ) [ T ] . second ) ; setLoad ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , * id ) . mayLoad ( ) ) ; setStore ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , * id ) . mayStore ( ) ) ; } else { Valid = false ; setUnits ( <NUM_LIT> ) ; setLanes ( <NUM_LIT> ) ; setLoad ( false ) ; setStore ( false ) ; }


<s> <ISA_LIT>Shuffler :: <ISA_LIT>Shuffler ( MCInstrInfo const & MCII , MCSubtargetInfo const & STI ) : MCII ( MCII ) , STI ( STI ) { reset ( ) ;


<s> static bool lessCore ( const <ISA_LIT>Instr & A , const <ISA_LIT>Instr & B ) {

return ( <STR_LIT> ( A . Core , B . Core ) ) ;


<s> static bool lessCore ( const <ISA_LIT>Instr & A , const <ISA_LIT>Instr & B ) { return ( <STR_LIT> ( A . Core , B . Core ) ) ;


<s> static bool lessCVI ( const <ISA_LIT>Instr & A , const <ISA_LIT>Instr & B ) { return ( <STR_LIT> ( A . CVI , B . CVI ) ) ;


<s> static bool lessCVI ( const <ISA_LIT>Instr & A , const <ISA_LIT>Instr & B ) {

return ( <STR_LIT> ( A . CVI , B . CVI ) ) ;


<s> return ( countPopulation ( A . getUnits ( ) ) < countPopulation ( B . getUnits ( ) ) ) ;


<s> return ( A . getWeight ( ) < B . getWeight ( ) ) ;


<s> BundleFlags = <NUM_LIT> ; Error = SHUFFLE_SUCCESS ;


<s> ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_MPY0 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ;


<s> assert ( SlotWeight * s < <NUM_LIT> && <STR_LIT> ) ; Weight = ( Key << ( SlotWeight * s ) ) * ( ( MaskWeight - countPopulation ( getUnits ( ) ) ) << countTrailingZeros ( getUnits ( ) ) ) ; return ( Weight ) ;


<s> const unsigned MaskWeight = SlotWeight - <NUM_LIT> ; bool Key = ( <NUM_LIT> << s ) & getUnits ( ) ; assert ( SlotWeight * s < <NUM_LIT> && <STR_LIT> ) ; Weight = ( Key << ( SlotWeight * s ) ) * ( ( MaskWeight - countPopulation ( getUnits ( ) ) ) << countTrailingZeros ( getUnits ( ) ) ) ;


<s> } for ( iterator ISJ = begin ( ) ; ISJ != end ( ) ; ++ ISJ ) DEBUG ( dbgs ( ) . write_hex ( ISJ -> Core . getUnits ( ) ) ; dbgs ( ) << ':' << <ISA_LIT>MCInstrInfo :: getDesc ( MCII , * ISJ -> getDesc ( ) ) . getOpcode ( ) ; dbgs ( ) << '\n' ) ; DEBUG ( dbgs ( ) << '\n' ) ; return ( ! getError ( ) ) ;


<s> if ( size ( ) > <NUM_LIT> && check ( ) ) for ( unsigned nSlot = <NUM_LIT> , emptySlots = <NUM_LIT> ; nSlot < HEXAGON_PACKET_SIZE ; ++ nSlot ) { iterator ISJ , ISK ; unsigned slotSkip , slotWeight ; for ( ISJ = ISK = Packet . begin ( ) , slotSkip = slotWeight = <NUM_LIT> ; ISK != Packet . end ( ) ; ++ ISK , ++ slotSkip ) if ( slotSkip < nSlot - emptySlots ) ++ ISJ ; else slotWeight += ISK -> Core . setWeight ( HEXAGON_PACKET_SIZE - nSlot - <NUM_LIT> ) ; if ( slotWeight ) std :: sort ( ISJ , Packet . end ( ) ) ; else ++ emptySlots ; } for ( iterator ISJ = begin ( ) ; ISJ != end ( ) ; ++ ISJ ) DEBUG ( dbgs ( ) . write_hex ( ISJ -> Core . getUnits ( ) ) ; dbgs ( ) << ':' << <ISA_LIT>MCInstrInfo :: getDesc ( MCII , * ISJ -> getDesc ( ) ) . getOpcode ( ) ;


<s> permitNonSlot ( ) ; if ( ! CheckFailure ) restrictStoreLoadOrder ( Summary ) ; if ( ! CheckFailure ) restrictBranchOrder ( Summary ) ; if ( ! CheckFailure ) restrictPreferSlot3 ( Summary ) ;


<s> const <ISA_LIT>PacketSummary Summary = GetPacketSummary ( ) ;

if ( ! applySlotRestrictions ( Summary ) ) return false ;


<s> dbgs ( ) << '/' ; dbgs ( ) . write_hex ( ISJ . CVI . getUnits ( ) ) << '|' ;


<s> <ISA_LIT>CVIResource :: <ISA_LIT>CVIResource ( MCInstrInfo const & MCII , MCSubtargetInfo const & STI , unsigned s , MCInst const * id ) : <ISA_LIT>Resource ( s ) { const unsigned ItinUnits = <ISA_LIT>MCInstrInfo :: getCVIResources ( MCII , STI , * id ) ; unsigned Lanes ; const unsigned Units = <ISA_LIT>ConvertUnits ( ItinUnits , & Lanes ) ; if ( Units == <NUM_LIT> && Lanes == <NUM_LIT> ) { Valid = false ; setUnits ( <NUM_LIT> ) ; setLanes ( <NUM_LIT> ) ; setLoad ( false ) ; setStore ( false ) ; } else { Valid = true ; setUnits ( Units ) ; setLanes ( Lanes ) ; setLoad ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , * id ) . mayLoad ( ) ) ; setStore ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , * id ) . mayStore ( ) ) ;


<s> <ISA_LIT>Shuffler :: <ISA_LIT>Shuffler ( MCContext & Context , bool ReportErrors , MCInstrInfo const & MCII , MCSubtargetInfo const & STI ) : Context ( Context ) , MCII ( MCII ) , STI ( STI ) , ReportErrors ( ReportErrors ) { reset ( ) ;


<s> <ISA_LIT>Shuffler :: <ISA_LIT>Shuffler ( MCContext & Context , bool ReportErrors , MCInstrInfo const & MCII , MCSubtargetInfo const & STI ) : Context ( Context ) , MCII ( MCII ) , STI ( STI ) , ReportErrors ( ReportErrors ) {


<s> void <ISA_LIT>Shuffler :: permitNonSlot ( ) {

for ( <ISA_LIT>Instr & ISJ : insts ( ) ) {


<s> for ( <ISA_LIT>Instr & ISJ : insts ( ) ) { const bool RequiresSlot = <ISA_LIT>MCInstrInfo :: requiresSlot ( STI , * ISJ . ID ) ; if ( ! RequiresSlot ) ISJ . Core . setAllUnits ( ) ; }


<s> if ( ReportErrors ) { for ( auto const & I : AppliedRestrictions ) { auto SM = Context . getSourceManager ( ) ; if ( SM ) SM -> PrintMessage ( I . first , SourceMgr :: DK_Note , I . second ) ;


<s> { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } } ; for ( std :: pair < unsigned , unsigned > jumpSlot : jumpSlots ) {

if ( ! ( jumpSlot . first & Summary . branchInsts [ <NUM_LIT> ] -> Core . getUnits ( ) ) ) continue ;


<s> if ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , Inst ) . mayStore ( ) ) { unsigned Units = ISJ . Core . getUnits ( ) ; if ( Units & Slot1Mask ) { AppliedRestriction = true ; AppliedRestrictions . push_back ( std :: make_pair ( Inst . getLoc ( ) , <STR_LIT> ) ) ; ISJ . Core . setUnits ( Units & ~ Slot1Mask ) ; } } } if ( AppliedRestriction ) AppliedRestrictions . push_back ( std :: make_pair ( * Summary . NoSlot1StoreLoc , <STR_LIT> ) ) ;


<s> unsigned Units = ISJ . Core . getUnits ( ) ; if ( Units & Slot1Mask ) { AppliedRestriction = true ; AppliedRestrictions . push_back ( std :: make_pair ( Inst . getLoc ( ) , <STR_LIT> ) ) ; ISJ . Core . setUnits ( Units & ~ Slot1Mask ) ; } } } if ( AppliedRestriction ) AppliedRestrictions . push_back ( std :: make_pair ( * Summary . NoSlot1StoreLoc , <STR_LIT> ) ) ;


<s> void <ISA_LIT>Shuffler :: restrictPreferSlot3 ( <ISA_LIT>PacketSummary const & Summary ) { const bool HasOnlySlot3 = llvm :: any_of ( insts ( ) , [ & ] ( <ISA_LIT>Instr const & I ) { return ( I . Core . getUnits ( ) == Slot3Mask ) ; } ) ; const bool NeedsPrefSlot3Shuffle = ( Summary . branchInsts . size ( ) <= <NUM_LIT> && ! HasOnlySlot3 && Summary . pSlot3Cnt == <NUM_LIT> && Summary . PrefSlot3Inst ) ; if ( ! NeedsPrefSlot3Shuffle ) return ; <ISA_LIT>Instr * PrefSlot3Inst = * Summary . PrefSlot3Inst ; const unsigned saveUnits = PrefSlot3Inst -> Core . getUnits ( ) ; PrefSlot3Inst -> Core . setUnits ( saveUnits & Slot3Mask ) ;

const bool HasShuffledPacket = tryAuction ( Summary ) . hasValue ( ) ;


<s> void <ISA_LIT>Shuffler :: restrictPreferSlot3 ( <ISA_LIT>PacketSummary const & Summary ) { const bool HasOnlySlot3 = llvm :: any_of ( insts ( ) , [ & ] ( <ISA_LIT>Instr const & I ) { return ( I . Core . getUnits ( ) == Slot3Mask ) ; } ) ; const bool NeedsPrefSlot3Shuffle = ( Summary . branchInsts . size ( ) <= <NUM_LIT> && ! HasOnlySlot3 && Summary . pSlot3Cnt == <NUM_LIT> && Summary . PrefSlot3Inst ) ; if ( ! NeedsPrefSlot3Shuffle ) return ; <ISA_LIT>Instr * PrefSlot3Inst = * Summary . PrefSlot3Inst ; const unsigned saveUnits = PrefSlot3Inst -> Core . getUnits ( ) ; PrefSlot3Inst -> Core . setUnits ( saveUnits & Slot3Mask ) ; const bool HasShuffledPacket = tryAuction ( Summary ) . hasValue ( ) ;


<s> const unsigned Type = <ISA_LIT>MCInstrInfo :: getType ( MCII , Inst ) ; if ( Type != <STR_LIT> && Type != <STR_LIT> && Type != <STR_LIT> ) { const unsigned Units = ISJ . Core . getUnits ( ) ; if ( Units & Slot1Mask ) { AppliedRestrictions . push_back ( std :: make_pair ( Inst . getLoc ( ) , <STR_LIT> ) ) ;

AppliedRestrictions . push_back ( std :: make_pair ( * Summary . Slot1AOKLoc , <STR_LIT> <STR_LIT> ) ) ;


<s> bool <ISA_LIT>Shuffler :: restrictStoreLoadOrder ( <ISA_LIT>PacketSummary const & Summary ) { static const unsigned slotFirstLoadStore = Slot1Mask ; static const unsigned slotLastLoadStore = Slot0Mask ; unsigned slotLoadStore = slotFirstLoadStore ; for ( iterator ISJ = begin ( ) ; ISJ != end ( ) ; ++ ISJ ) { MCInst const & ID = ISJ -> getDesc ( ) ; if ( ! ISJ -> Core . getUnits ( ) ) return false ; if ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , ID ) . mayLoad ( ) ) { if ( Summary . loads == <NUM_LIT> && Summary . loads == Summary . memory && Summary . memops == <NUM_LIT> ) switch ( ID . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : ISJ -> Core . setUnits ( ISJ -> Core . getUnits ( ) & slotSingleLoad ) ; break ; } else if ( Summary . loads >= <NUM_LIT> && isMemReorderDisabled ( ) ) { if ( slotLoadStore < slotLastLoadStore ) {


<s> return false ; } bool Ok = true ; if ( size ( ) > <NUM_LIT> && ( Ok = check ( ) ) ) for ( unsigned nSlot = <NUM_LIT> , emptySlots = <NUM_LIT> ; nSlot < HEXAGON_PACKET_SIZE ; ++ nSlot ) { iterator ISJ , ISK ; unsigned slotSkip , slotWeight ; for ( ISJ = ISK = Packet . begin ( ) , slotSkip = slotWeight = <NUM_LIT> ; ISK != Packet . end ( ) ; ++ ISK , ++ slotSkip ) if ( slotSkip < nSlot - emptySlots ) ++ ISJ ; else slotWeight += ISK -> Core . setWeight ( HEXAGON_PACKET_SIZE - nSlot - <NUM_LIT> ) ; if ( slotWeight ) std :: stable_sort ( ISJ , Packet . end ( ) ) ; else ++ emptySlots ; } LLVM_DEBUG ( for ( <ISA_LIT>Instr const & ISJ : insts ( ) ) { dbgs ( ) . write_hex ( ISJ . Core . getUnits ( ) ) ; if ( ISJ . CVI . isValid ( ) ) { dbgs ( ) << '/' ; dbgs ( ) . write_hex ( ISJ . CVI . getUnits ( ) ) << '|' ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( ValidSlots ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> ;

for ( <ISA_LIT>Instr const & ISJ : insts ( PacketResult ) ) dbgs ( ) << <STR_LIT> << <ISA_LIT>MCInstrInfo :: getName ( MCII , * ISJ . ID ) << <STR_LIT> << llvm :: format_hex ( ISJ . Core . getUnits ( ) , <NUM_LIT> , true ) << <STR_LIT> ;


<s> const bool InvalidPacket = ( ( Summary . load0 > <NUM_LIT> || Summary . store0 > <NUM_LIT> || ! ValidHVXMem ) || ( Summary . duplex > <NUM_LIT> || ( Summary . duplex && Summary . memory ) ) ) ;


<s> bool <ISA_LIT>Shuffler :: ValidPacketMemoryOps ( <ISA_LIT>PacketSummary const & Summary ) const { const unsigned ZCVIloads = Summary . AllCVIloads - Summary . NonZCVIloads ; const bool ValidHVXMem = Summary . NonZCVIloads <= <NUM_LIT> && ZCVIloads <= <NUM_LIT> && Summary . CVIstores <= <NUM_LIT> ; const bool InvalidPacket = ( ( Summary . load0 > <NUM_LIT> || Summary . store0 > <NUM_LIT> || ! ValidHVXMem ) || ( Summary . duplex > <NUM_LIT> || ( Summary . duplex && Summary . memory ) ) ) ;


<s> Packet = * ShuffledPacket ; } llvm :: stable_sort ( * this , <STR_LIT> ) ; HVXInstsT hvxInsts ; hvxInsts . clear ( ) ; for ( const_iterator I = cbegin ( ) ; I != cend ( ) ; ++ I ) { struct CVIUnits inst ;

inst . Units = I -> CVI . getUnits ( ) ;


<s> bool <ISA_LIT>Shuffler :: ValidResourceUsage ( <ISA_LIT>PacketSummary const & Summary ) { Optional < <ISA_LIT>Packet > ShuffledPacket = tryAuction ( Summary ) ; if ( ! ShuffledPacket ) { reportError ( <STR_LIT> ) ; return false ; } else { Packet = * ShuffledPacket ; } llvm :: stable_sort ( * this , <STR_LIT> ) ; HVXInstsT hvxInsts ; hvxInsts . clear ( ) ; for ( const_iterator I = cbegin ( ) ; I != cend ( ) ; ++ I ) { struct CVIUnits inst ; inst . Units = I -> CVI . getUnits ( ) ; inst . Lanes = I -> CVI . getLanes ( ) ; if ( inst . Units == <NUM_LIT> ) continue ; hvxInsts . push_back ( inst ) ; } if ( hvxInsts . size ( ) > <NUM_LIT> ) { unsigned startIdx , usedUnits ; startIdx = usedUnits = <NUM_LIT> ; if ( ! checkHVXPipes ( hvxInsts , startIdx , usedUnits ) ) { reportError ( Twine ( <STR_LIT> ) ) ;


<s> static bool checkHVXPipes ( const HVXInstsT & hvxInsts , unsigned startIdx , unsigned usedUnits ) { if ( startIdx < hvxInsts . size ( ) ) { if ( ! hvxInsts [ startIdx ] . Units ) return checkHVXPipes ( hvxInsts , startIdx + <NUM_LIT> , usedUnits ) ; for ( unsigned b = <NUM_LIT> ; b <= <NUM_LIT> ; b <<= <NUM_LIT> ) { if ( ( hvxInsts [ startIdx ] . Units & b ) == <NUM_LIT> ) continue ; unsigned allBits = makeAllBits ( b , hvxInsts [ startIdx ] . Lanes ) ; if ( ( allBits & usedUnits ) == <NUM_LIT> ) { if ( checkHVXPipes ( hvxInsts , startIdx + <NUM_LIT> , usedUnits | allBits ) ) return true ; } } return false ;


<s> if ( startIdx < hvxInsts . size ( ) ) { if ( ! hvxInsts [ startIdx ] . Units ) return checkHVXPipes ( hvxInsts , startIdx + <NUM_LIT> , usedUnits ) ; for ( unsigned b = <NUM_LIT> ; b <= <NUM_LIT> ; b <<= <NUM_LIT> ) { if ( ( hvxInsts [ startIdx ] . Units & b ) == <NUM_LIT> ) continue ; unsigned allBits = makeAllBits ( b , hvxInsts [ startIdx ] . Lanes ) ; if ( ( allBits & usedUnits ) == <NUM_LIT> ) { if ( checkHVXPipes ( hvxInsts , startIdx + <NUM_LIT> , usedUnits | allBits ) ) return true ; } }


<s> unsigned subInst0Opcode = ID . getOperand ( <NUM_LIT> ) . getInst ( ) -> getOpcode ( ) ; unsigned subInst1Opcode = ID . getOperand ( <NUM_LIT> ) . getInst ( ) -> getOpcode ( ) ; Result += ! isDuplexAGroup ( subInst0Opcode ) ;

Result += ! isDuplexAGroup ( subInst1Opcode ) ;


<s> if ( Type == <STR_LIT> ) { unsigned subInst0Opcode = ID . getOperand ( <NUM_LIT> ) . getInst ( ) -> getOpcode ( ) ; unsigned subInst1Opcode = ID . getOperand ( <NUM_LIT> ) . getInst ( ) -> getOpcode ( ) ;

Result += ! isDuplexAGroup ( subInst0Opcode ) ;


<s> <ISA_LIT>Bid ( ) : Bid ( <NUM_LIT> ) {


<s> static unsigned makeAllBits ( unsigned startBit , unsigned Lanes ) { for ( unsigned i = <NUM_LIT> ; i < Lanes ; ++ i ) startBit = ( startBit << <NUM_LIT> ) | startBit ; return startBit ;


<s> const unsigned MaskWeight = SlotWeight - <NUM_LIT> ; unsigned Units = getUnits ( ) ; unsigned Key = ( ( <NUM_LIT> << s ) & Units ) != <NUM_LIT> ; if ( Key == <NUM_LIT> || Units == <NUM_LIT> || ( SlotWeight * s >= <NUM_LIT> ) ) return Weight = <NUM_LIT> ; unsigned Ctpop = countPopulation ( Units ) ; unsigned Cttz = countTrailingZeros ( Units ) ; Weight = ( <NUM_LIT> << ( SlotWeight * s ) ) * ( ( MaskWeight - Ctpop ) << Cttz ) ;


<s> else ++ emptySlots ; } for ( iterator ISJ = begin ( ) ; ISJ != end ( ) ; ++ ISJ ) DEBUG ( dbgs ( ) . write_hex ( ISJ -> Core . getUnits ( ) ) ; if ( ISJ -> CVI . isValid ( ) ) { dbgs ( ) << '/' ; dbgs ( ) . write_hex ( ISJ -> CVI . getUnits ( ) ) << '|' ; dbgs ( ) << ISJ -> CVI . getLanes ( ) ; } dbgs ( ) << ':' << <ISA_LIT>MCInstrInfo :: getDesc ( MCII , ISJ -> getDesc ( ) ) . getOpcode ( ) ; dbgs ( ) << '\n' ) ;


<s> void setUnits ( unsigned s ) { Slots = s & ~ ( - <NUM_LIT> << HEXAGON_PACKET_SIZE ) ;


<s> <ISA_LIT>UnitAuction AuctionCore ( Summary . ReservedSlotMask ) ; std :: stable_sort ( PacketResult . begin ( ) , PacketResult . end ( ) , <STR_LIT> ) ; const bool ValidSlots = llvm :: all_of ( insts ( PacketResult ) , [ & AuctionCore ] ( <ISA_LIT>Instr const & I ) { return AuctionCore . bid ( I . Core . getUnits ( ) ) ; } ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( ValidSlots ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> ;


<s> llvm :: Optional < <ISA_LIT>Shuffler :: <ISA_LIT>Packet > <ISA_LIT>Shuffler :: tryAuction ( <ISA_LIT>PacketSummary const & Summary ) const { <ISA_LIT>Packet PacketResult = Packet ; <ISA_LIT>UnitAuction AuctionCore ( Summary . ReservedSlotMask ) ; std :: stable_sort ( PacketResult . begin ( ) , PacketResult . end ( ) , <STR_LIT> ) ; const bool ValidSlots = llvm :: all_of ( insts ( PacketResult ) , [ & AuctionCore ] ( <ISA_LIT>Instr const & I ) { return AuctionCore . bid ( I . Core . getUnits ( ) ) ; } ) ;

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( ValidSlots ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> ;


<s> for ( const_iterator I = cbegin ( ) ; I != cend ( ) ; ++ I ) { struct CVIUnits inst ; inst . Units = I -> CVI . getUnits ( ) ; inst . Lanes = I -> CVI . getLanes ( ) ; if ( inst . Units == <NUM_LIT> ) continue ;


<s> reportError ( <STR_LIT> ) ; return false ; } else { Packet = * ShuffledPacket ; } std :: stable_sort ( begin ( ) , end ( ) , <STR_LIT> ) ; HVXInstsT hvxInsts ; hvxInsts . clear ( ) ; for ( const_iterator I = cbegin ( ) ; I != cend ( ) ; ++ I ) { struct CVIUnits inst ; inst . Units = I -> CVI . getUnits ( ) ; inst . Lanes = I -> CVI . getLanes ( ) ; if ( inst . Units == <NUM_LIT> ) continue ; hvxInsts . push_back ( inst ) ; } if ( hvxInsts . size ( ) > <NUM_LIT> ) { unsigned startIdx , usedUnits ; startIdx = usedUnits = <NUM_LIT> ;

if ( ! checkHVXPipes ( hvxInsts , startIdx , usedUnits ) ) {


<s> void <ISA_LIT>Shuffler :: reportError ( Twine const & Msg ) {

if ( ReportErrors ) Context . reportError ( Loc , Msg ) ;


<s> if ( ReportErrors ) Context . reportError ( Loc , Msg ) ;


<s> ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_MPY0 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = ( CPU == <STR_LIT> ) ? UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) : UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ;


<s> bool Ok = true ; if ( size ( ) > <NUM_LIT> && ( Ok = check ( ) ) ) for ( unsigned nSlot = <NUM_LIT> , emptySlots = <NUM_LIT> ; nSlot < HEXAGON_PACKET_SIZE ; ++ nSlot ) { iterator ISJ , ISK ; unsigned slotSkip , slotWeight ; for ( ISJ = ISK = Packet . begin ( ) , slotSkip = slotWeight = <NUM_LIT> ;

ISK != Packet . end ( ) ; ++ ISK , ++ slotSkip ) if ( slotSkip < nSlot - emptySlots ) ++ ISJ ;


<s> reportError ( Twine ( <STR_LIT> ) ) ; return false ; } bool Ok = true ; if ( size ( ) > <NUM_LIT> && ( Ok = check ( ) ) ) for ( unsigned nSlot = <NUM_LIT> , emptySlots = <NUM_LIT> ; nSlot < HEXAGON_PACKET_SIZE ; ++ nSlot ) { iterator ISJ , ISK ; unsigned slotSkip , slotWeight ; for ( ISJ = ISK = Packet . begin ( ) , slotSkip = slotWeight = <NUM_LIT> ; ISK != Packet . end ( ) ; ++ ISK , ++ slotSkip ) if ( slotSkip < nSlot - emptySlots ) ++ ISJ ; else slotWeight += ISK -> Core . setWeight ( HEXAGON_PACKET_SIZE - nSlot - <NUM_LIT> ) ; if ( slotWeight ) std :: sort ( ISJ , Packet . end ( ) ) ; else ++ emptySlots ;


<s> const_iterator cend ( ) const { return ( Packet . end ( ) ) ;


<s> bool HasInstWith ( InstPredicate Pred ) const { return llvm :: any_of ( insts ( ) , [ & ] ( <ISA_LIT>Instr const & I ) { MCInst const & Inst = I . getDesc ( ) ; return ( * Pred ) ( MCII , Inst ) ; } ) ;


<s> MCInst const & Inst = I . getDesc ( ) ; return ( * Pred ) ( MCII , Inst ) ; } ) ;


<s> <ISA_LIT>Bid ( ) : Bid ( <NUM_LIT> ) {


<s> const_packet_range insts ( ) const {

return make_range ( cbegin ( ) , cend ( ) ) ;


<s> void <ISA_LIT>Shuffler :: reportError ( llvm :: Twine const & Msg ) {


<s> void setAllUnits ( ) { setUnits ( ( ( <NUM_LIT> << HEXAGON_PACKET_SIZE ) - <NUM_LIT> ) ) ;


<s> if ( size ( ) > <NUM_LIT> && ( Ok = check ( ) ) ) for ( unsigned nSlot = <NUM_LIT> , emptySlots = <NUM_LIT> ; nSlot < HEXAGON_PACKET_SIZE ; ++ nSlot ) { iterator ISJ , ISK ; unsigned slotSkip , slotWeight ; for ( ISJ = ISK = Packet . begin ( ) , slotSkip = slotWeight = <NUM_LIT> ; ISK != Packet . end ( ) ; ++ ISK , ++ slotSkip ) if ( slotSkip < nSlot - emptySlots ) ++ ISJ ; else slotWeight += ISK -> Core . setWeight ( HEXAGON_PACKET_SIZE - nSlot - <NUM_LIT> ) ; if ( slotWeight ) std :: sort ( ISJ , Packet . end ( ) ) ; else ++ emptySlots ; } for ( iterator ISJ = begin ( ) ; ISJ != end ( ) ; ++ ISJ ) DEBUG ( dbgs ( ) . write_hex ( ISJ -> Core . getUnits ( ) ) ; if ( ISJ -> CVI . isValid ( ) ) { dbgs ( ) << '/' ;

dbgs ( ) . write_hex ( ISJ -> CVI . getUnits ( ) ) << '|' ;


<s> if ( slotWeight ) std :: sort ( ISJ , Packet . end ( ) ) ; else ++ emptySlots ; } for ( iterator ISJ = begin ( ) ; ISJ != end ( ) ; ++ ISJ ) DEBUG ( dbgs ( ) . write_hex ( ISJ -> Core . getUnits ( ) ) ; if ( ISJ -> CVI . isValid ( ) ) { dbgs ( ) << '/' ; dbgs ( ) . write_hex ( ISJ -> CVI . getUnits ( ) ) << '|' ; dbgs ( ) << ISJ -> CVI . getLanes ( ) ; } dbgs ( ) << ':' << <ISA_LIT>MCInstrInfo :: getDesc ( MCII , ISJ -> getDesc ( ) ) . getOpcode ( ) ; dbgs ( ) << '\n' ) ;


<s> <ISA_LIT>Instr PI ( ID , Extender , S , X ) ; Packet . push_back ( PI ) ;


<s> bool Key = ( <NUM_LIT> << s ) & getUnits ( ) ;

Weight = ( Key << ( SlotWeight * s ) ) * ( ( MaskWeight - countPopulation ( getUnits ( ) ) ) << countTrailingZeros ( getUnits ( ) ) ) ;


<s> void <ISA_LIT>Shuffler :: append ( MCInst const * ID , MCInst const * Extender , unsigned S , bool X ) { <ISA_LIT>Instr PI ( & TUL , MCII , ID , Extender , S , X ) ;


<s> reset ( ) ; <ISA_LIT>CVIResource :: SetupTUL ( & TUL , STI . getCPU ( ) ) ;


<s> ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_MPY0 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_MPY0 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ;


<s> ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ;


<s> if ( ( load0 > <NUM_LIT> || store0 > <NUM_LIT> || CVIloads > <NUM_LIT> || CVIstores > <NUM_LIT> ) || ( duplex > <NUM_LIT> || ( duplex && memory ) ) || ( solo && size ( ) > <NUM_LIT> ) || ( onlyAX && neitherAnorX > <NUM_LIT> ) || ( onlyAX && xtypeFloat ) ) { Error = SHUFFLE_ERROR_INVALID ; return false ; } if ( jump1 && jumps > <NUM_LIT> ) { Error = SHUFFLE_ERROR_BRANCHES ; return false ; } bool bOnlySlot3 = false ; for ( iterator ISJ = begin ( ) ; ISJ != end ( ) ; ++ ISJ ) { MCInst const * ID = ISJ -> getDesc ( ) ; if ( ! ISJ -> Core . getUnits ( ) ) { Error = SHUFFLE_ERROR_UNKNOWN ; return false ; } if ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , * ID ) . getOpcode ( ) != <STR_LIT> ) if ( onlyNo1 ) ISJ -> Core . setUnits ( ISJ -> Core . getUnits ( ) & ~ slotOne ) ; if ( <ISA_LIT>MCInstrInfo :: getType ( MCII , * ID ) != <STR_LIT> ) if ( onlyAin1 ) ISJ -> Core . setUnits ( ISJ -> Core . getUnits ( ) & ~ slotOne ) ; if ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , * ID ) . isBranch ( ) || <ISA_LIT>MCInstrInfo :: getDesc ( MCII , * ID ) . isCall ( ) ) if ( jumps > <NUM_LIT> ) { if ( slotJump < slotLastJump ) { Error = SHUFFLE_ERROR_BRANCHES ; return false ; } ISJ -> Core . setUnits ( ISJ -> Core . getUnits ( ) & slotJump ) ; slotJump >>= <NUM_LIT> ; } if ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , * ID ) . mayLoad ( ) ) { if ( loads == <NUM_LIT> && loads == memory ) ISJ -> Core . setUnits ( ISJ -> Core . getUnits ( ) & slotSingleLoad ) ; } if ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , * ID ) . mayStore ( ) ) { if ( ! store0 ) { if ( stores == <NUM_LIT> ) ISJ -> Core . setUnits ( ISJ -> Core . getUnits ( ) & slotSingleStore ) ; else if ( stores > <NUM_LIT> ) { if ( slotLoadStore < slotLastLoadStore ) { Error = SHUFFLE_ERROR_STORES ; return false ; } ISJ -> Core . setUnits ( ISJ -> Core . getUnits ( ) & slotLoadStore ) ; slotLoadStore >>= <NUM_LIT> ; } } if ( store1 && stores > <NUM_LIT> ) { Error = SHUFFLE_ERROR_STORES ; return false ; } } if ( ISJ -> Core . getUnits ( ) == slotThree ) bOnlySlot3 = true ; if ( ! ISJ -> Core . getUnits ( ) ) {


<s> ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = ( CPU == <STR_LIT> || CPU == <STR_LIT> || CPU == <STR_LIT> ) ? UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) : UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ;


<s> ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_MPY0 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = ( CPU == <STR_LIT> || CPU == <STR_LIT> || CPU == <STR_LIT> ) ? UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) : UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ;

( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ;


<s> bool <ISA_LIT>Shuffler :: applySlotRestrictions ( <ISA_LIT>PacketSummary const & Summary , const bool DoShuffle ) { restrictSlot1AOK ( Summary ) ; restrictNoSlot1Store ( Summary ) ; permitNonSlot ( ) ; if ( ! CheckFailure ) restrictStoreLoadOrder ( Summary ) ;

if ( ! CheckFailure ) restrictBranchOrder ( Summary ) ;


<s> if ( ! ValidPacketMemoryOps ( Summary ) ) { reportError ( <STR_LIT> ) ; return false ; }

if ( RequireShuffle ) ValidResourceUsage ( Summary ) ;


<s> if ( ! applySlotRestrictions ( Summary , RequireShuffle ) ) return false ;

if ( ! ValidPacketMemoryOps ( Summary ) ) {


<s> <ISA_LIT>Shuffler :: <ISA_LIT>Shuffler ( MCContext & Context , bool ReportErrors , MCInstrInfo const & MCII , MCSubtargetInfo const & STI ) : Context ( Context ) , BundleFlags ( ) , MCII ( MCII ) , STI ( STI ) , ReportErrors ( ReportErrors ) , CheckFailure ( ) { reset ( ) ;


<s> if ( ReportErrors ) reportResourceUsage ( Summary ) ;

reportError ( Twine ( <STR_LIT> ) + Err ) ;


<s> if ( SM ) { for ( <ISA_LIT>Instr const & I : insts ( ) ) { const unsigned Units = I . Core . getUnits ( ) ; if ( <ISA_LIT>MCInstrInfo :: requiresSlot ( STI , * I . ID ) ) { const std :: string UnitsText = Units ? SlotMaskToText ( Units ) : <STR_LIT> ; SM -> PrintMessage ( I . ID -> getLoc ( ) , SourceMgr :: DK_Note , Twine ( <STR_LIT> ) + UnitsText ) ; } else if ( ! <ISA_LIT>MCInstrInfo :: isImmext ( * I . ID ) ) SM -> PrintMessage ( I . ID -> getLoc ( ) , SourceMgr :: DK_Note , <STR_LIT> ) ; } }


<s> void <ISA_LIT>Shuffler :: restrictPreferSlot3 ( <ISA_LIT>PacketSummary const & Summary , const bool DoShuffle ) { const bool HasOnlySlot3 = llvm :: any_of ( insts ( ) , [ & ] ( <ISA_LIT>Instr const & I ) { return ( I . Core . getUnits ( ) == Slot3Mask ) ; } ) ; const bool NeedsPrefSlot3Shuffle = Summary . branchInsts . size ( ) <= <NUM_LIT> && ! HasOnlySlot3 && Summary . pSlot3Cnt == <NUM_LIT> && Summary . PrefSlot3Inst && DoShuffle ; if ( ! NeedsPrefSlot3Shuffle ) return ; <ISA_LIT>Instr * PrefSlot3Inst = * Summary . PrefSlot3Inst ; const unsigned saveUnits = PrefSlot3Inst -> Core . getUnits ( ) ; PrefSlot3Inst -> Core . setUnits ( saveUnits & Slot3Mask ) ; const bool HasShuffledPacket = tryAuction ( Summary ) . hasValue ( ) ; if ( HasShuffledPacket ) return ; PrefSlot3Inst -> Core . setUnits ( saveUnits ) ;


<s> bool <ISA_LIT>Shuffler :: shuffle ( ) { if ( size ( ) > HEXAGON_PACKET_SIZE ) { reportError ( <STR_LIT> ) ; return false ; } bool Ok = check ( ) ; if ( size ( ) > <NUM_LIT> && Ok ) for ( unsigned nSlot = <NUM_LIT> , emptySlots = <NUM_LIT> ; nSlot < HEXAGON_PACKET_SIZE ; ++ nSlot ) { iterator ISJ , ISK ; unsigned slotSkip , slotWeight ; for ( ISJ = ISK = Packet . begin ( ) , slotSkip = slotWeight = <NUM_LIT> ; ISK != Packet . end ( ) ; ++ ISK , ++ slotSkip ) if ( slotSkip < nSlot - emptySlots ) ++ ISJ ; else slotWeight += ISK -> Core . setWeight ( HEXAGON_PACKET_SIZE - nSlot - <NUM_LIT> ) ; if ( slotWeight ) std :: stable_sort ( ISJ , Packet . end ( ) ) ; else ++ emptySlots ; } LLVM_DEBUG ( for ( <ISA_LIT>Instr const & ISJ : insts ( ) ) { dbgs ( ) . write_hex ( ISJ . Core . getUnits ( ) ) ; if ( ISJ . CVI . isValid ( ) ) { dbgs ( ) << '/' ; dbgs ( ) . write_hex ( ISJ . CVI . getUnits ( ) ) << '|' ; dbgs ( ) << ISJ . CVI . getLanes ( ) ; }

dbgs ( ) << ':' << <ISA_LIT>MCInstrInfo :: getDesc ( MCII , ISJ . getDesc ( ) ) . getOpcode ( ) << '\n' ;


<s> for ( unsigned SlotNum = <NUM_LIT> ; SlotNum < HEXAGON_PACKET_SIZE ; SlotNum ++ ) if ( ( SlotMask & ( <NUM_LIT> << SlotNum ) ) != <NUM_LIT> ) Slots . push_back ( utostr ( SlotNum ) ) ; return llvm :: join ( Slots , StringRef ( <STR_LIT> ) ) ;


<s> llvm :: stable_sort ( PacketResult , <STR_LIT> ) ; const bool ValidSlots = llvm :: all_of ( insts ( PacketResult ) , [ & AuctionCore ] ( <ISA_LIT>Instr const & I ) { return AuctionCore . bid ( I . Core . getUnits ( ) ) ; } ) ;


<s> return AuctionCore . bid ( I . Core . getUnits ( ) ) ; } ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( ValidSlots ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> ; for ( <ISA_LIT>Instr const & ISJ : insts ( PacketResult ) ) dbgs ( ) << <STR_LIT> << <ISA_LIT>MCInstrInfo :: getName ( MCII , * ISJ . ID ) << <STR_LIT> << llvm :: format_hex ( ISJ . Core . getUnits ( ) , <NUM_LIT> , true ) << <STR_LIT> ; ) ; Optional < <ISA_LIT>Packet > Res ; if ( ValidSlots ) Res = PacketResult ; return Res ;


<s> Optional < <ISA_LIT>Packet > ShuffledPacket = tryAuction ( Summary ) ; if ( ! ShuffledPacket ) { reportResourceError ( Summary , <STR_LIT> ) ; return false ; } llvm :: stable_sort ( * ShuffledPacket , <STR_LIT> ) ; HVXInstsT hvxInsts ; hvxInsts . clear ( ) ; for ( const auto & I : * ShuffledPacket ) { struct CVIUnits inst ;


<s> MCInst const & getDesc ( ) const { return * ID ;


<s> unsigned getLanes ( ) const { return Lanes ;


<s> unsigned getWeight ( ) const { return ( Weight ) ;


<s> <ISA_LIT>Instr ( <ISA_LIT>CVIResource :: TypeUnitsAndLanes * T , MCInstrInfo const & MCII , MCInst const * id , MCInst const * Extender , unsigned s ) : ID ( id ) , Extender ( Extender ) , Core ( s ) , CVI ( T , MCII , s , id ) {


<s> bool isMemReorderDisabled ( ) const { return ( BundleFlags & <ISA_LIT>MCInstrInfo :: memReorderDisabledMask ) != <NUM_LIT> ;


<s> bool mayLoad ( ) const { return Load ;


<s> Slots = s & ( ( <NUM_LIT> << HEXAGON_PACKET_SIZE ) - <NUM_LIT> ) ;


<s> void setUnits ( unsigned s ) { Slots = s & ( ( <NUM_LIT> << HEXAGON_PACKET_SIZE ) - <NUM_LIT> ) ; setWeight ( s ) ;


<s> ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = ( CPU == <STR_LIT> ) ? UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) : UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ;


<s> else ++ emptySlots ; } for ( iterator ISJ = begin ( ) ; ISJ != end ( ) ; ++ ISJ ) DEBUG ( dbgs ( ) . write_hex ( ISJ -> Core . getUnits ( ) ) ; if ( ISJ -> CVI . isValid ( ) ) { dbgs ( ) << '/' ; dbgs ( ) . write_hex ( ISJ -> CVI . getUnits ( ) ) << '|' ; dbgs ( ) << ISJ -> CVI . getLanes ( ) ; } dbgs ( ) << ':' << <ISA_LIT>MCInstrInfo :: getDesc ( MCII , ISJ -> getDesc ( ) ) . getOpcode ( ) ; dbgs ( ) << '\n' ) ; DEBUG ( dbgs ( ) << '\n' ) ;


<s> <ISA_LIT>SplitConst32AndConst64 ( const <ISA_LIT>TargetMachine & TM ) : MachineFunctionPass ( ID ) , QTM ( TM ) {


<s> int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned DestLo = QTM . getRegisterInfo ( ) -> getSubReg ( DestReg , <STR_LIT> ) ; unsigned DestHi = QTM . getRegisterInfo ( ) -> getSubReg ( DestReg , <STR_LIT> ) ; int32_t LowWord = ( ImmValue & <NUM_LIT> ) ; int32_t HighWord = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestLo ) . addImm ( LowWord ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestLo ) . addImm ( LowWord ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestHi ) . addImm ( HighWord ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestHi ) . addImm ( HighWord ) ; MII = MBB -> erase ( MI ) ; continue ; } ++ MII ; } } return true ;


<s> return new <ISA_LIT>SplitConst32AndConst64 ( ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>SplitConst32AndConst64 ( ) {

return new <ISA_LIT>SplitConst32AndConst64 ( ) ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> MachineInstr & MI = * I ; ++ I ; unsigned Opc = MI . getOpcode ( ) ; if ( Opc == <STR_LIT> ) { unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t ImmValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; B . erase ( & MI ) ; } else if ( Opc == <STR_LIT> ) {


<s> const TargetRegisterInfo * TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; for ( MachineFunction :: iterator MBBb = Fn . begin ( ) , MBBe = Fn . end ( ) ; MBBb != MBBe ; ++ MBBb ) { MachineBasicBlock * MBB = & * MBBb ; MachineBasicBlock :: iterator MII = MBB -> begin ( ) ; MachineBasicBlock :: iterator MIE = MBB -> end ( ) ; while ( MII != MIE ) { MachineInstr * MI = MII ; int Opc = MI -> getOpcode ( ) ; if ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isBlockAddress ( ) ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue ; if ( Opc == <STR_LIT> ) { APFloat Val = MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; ImmValue = * Val . bitcastToAPInt ( ) . getRawData ( ) ; } else ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue ; if ( Opc == <STR_LIT> ) { APFloat Val = MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; ImmValue = * Val . bitcastToAPInt ( ) . getRawData ( ) ; } else ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned DestLo = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; unsigned DestHi = TRI -> getSubReg ( DestReg , <STR_LIT> ) ;

int32_t LowWord = ( ImmValue & <NUM_LIT> ) ;


<s> unsigned Opc = MI . getOpcode ( ) ; if ( Opc == <STR_LIT> ) { Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t ImmValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; B . erase ( & MI ) ; } else if ( Opc == <STR_LIT> ) { Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; Register DestLo = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; Register DestHi = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; int32_t LowWord = ( ImmValue & <NUM_LIT> ) ; int32_t HighWord = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestLo ) . addImm ( LowWord ) ;

BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestHi ) . addImm ( HighWord ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>SplitConst32AndConst64 ( const <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>SplitConst32AndConst64 ( TM ) ;


<s> return new <ISA_LIT>SplitConst32AndConst64 ( TM ) ;


<s> <ISA_LIT>SplitConst32AndConst64 ( const <ISA_LIT>TargetMachine & TM ) : MachineFunctionPass ( ID ) , QTM ( TM ) , QST ( * TM . getSubtargetImpl ( ) ) {


<s> int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ; continue ;


<s> BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned DestLo = QTM . getSubtargetImpl ( ) -> getRegisterInfo ( ) -> getSubReg ( DestReg , <STR_LIT> ) ; unsigned DestHi = QTM . getSubtargetImpl ( ) -> getRegisterInfo ( ) -> getSubReg ( DestReg , <STR_LIT> ) ; int32_t LowWord = ( ImmValue & <NUM_LIT> ) ; int32_t HighWord = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestLo ) . addImm ( LowWord ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestLo ) . addImm ( LowWord ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestHi ) . addImm ( HighWord ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestHi ) . addImm ( HighWord ) ; MII = MBB -> erase ( MI ) ; continue ;


<s> MachineInstr & MI = * I ; ++ I ; unsigned Opc = MI . getOpcode ( ) ; if ( Opc == <STR_LIT> ) { unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t ImmValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; B . erase ( & MI ) ; } else if ( Opc == <STR_LIT> ) { unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned DestLo = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; unsigned DestHi = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; int32_t LowWord = ( ImmValue & <NUM_LIT> ) ; int32_t HighWord = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestLo ) . addImm ( LowWord ) ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestHi ) . addImm ( HighWord ) ; B . erase ( & MI ) ;


<s> unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t ImmValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; B . erase ( & MI ) ; } else if ( Opc == <STR_LIT> ) { unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned DestLo = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; unsigned DestHi = TRI -> getSubReg ( DestReg , <STR_LIT> ) ;


<s> int64_t ImmValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned DestLo = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; unsigned DestHi = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; int32_t LowWord = ( ImmValue & <NUM_LIT> ) ; int32_t HighWord = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestLo ) . addImm ( LowWord ) ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestHi ) . addImm ( HighWord ) ; B . erase ( & MI ) ; } }


<s> if ( Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isBlockAddress ( ) ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue ; if ( Opc == <STR_LIT> ) { APFloat Val = MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; ImmValue = * Val . bitcastToAPInt ( ) . getRawData ( ) ; } else ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue ; if ( Opc == <STR_LIT> ) { APFloat Val = MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ;


<s> const TargetInstrInfo * TII = Fn . getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; for ( MachineFunction :: iterator MBBb = Fn . begin ( ) , MBBe = Fn . end ( ) ; MBBb != MBBe ; ++ MBBb ) { MachineBasicBlock * MBB = MBBb ; MachineBasicBlock :: iterator MII = MBB -> begin ( ) ; MachineBasicBlock :: iterator MIE = MBB -> end ( ) ; while ( MII != MIE ) { MachineInstr * MI = MII ; int Opc = MI -> getOpcode ( ) ; if ( Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isBlockAddress ( ) ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ;


<s> ++ I ; unsigned Opc = MI . getOpcode ( ) ; if ( Opc == <STR_LIT> ) { unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t ImmValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; B . erase ( & MI ) ; } else if ( Opc == <STR_LIT> ) { unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned DestLo = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; unsigned DestHi = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; int32_t LowWord = ( ImmValue & <NUM_LIT> ) ; int32_t HighWord = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestLo ) . addImm ( LowWord ) ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestHi ) . addImm ( HighWord ) ; B . erase ( & MI ) ;


<s> MII = MBB -> erase ( & MI ) ; continue ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { int DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue ; if ( Opc == <STR_LIT> ) { APFloat Val = MI . getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; ImmValue = * Val . bitcastToAPInt ( ) . getRawData ( ) ; } else ImmValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned DestLo = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; unsigned DestHi = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; int32_t LowWord = ( ImmValue & <NUM_LIT> ) ; int32_t HighWord = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; BuildMI ( * MBB , MII , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestLo ) . addImm ( LowWord ) ; BuildMI ( * MBB , MII , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestHi ) . addImm ( HighWord ) ; MII = MBB -> erase ( & MI ) ;


<s> const TargetRegisterInfo * TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; for ( MachineFunction :: iterator MBBb = Fn . begin ( ) , MBBe = Fn . end ( ) ; MBBb != MBBe ; ++ MBBb ) { MachineBasicBlock * MBB = & * MBBb ; MachineBasicBlock :: iterator MII = MBB -> begin ( ) ; MachineBasicBlock :: iterator MIE = MBB -> end ( ) ; while ( MII != MIE ) { MachineInstr * MI = MII ; int Opc = MI -> getOpcode ( ) ; if ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isBlockAddress ( ) ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue ; if ( Opc == <STR_LIT> ) { APFloat Val = MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; ImmValue = * Val . bitcastToAPInt ( ) . getRawData ( ) ; } else ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; MII = MBB -> erase ( MI ) ; continue ; }


<s> if ( TLOF . isSmallDataEnabled ( ) ) return true ; const TargetInstrInfo * TII = Fn . getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; for ( MachineFunction :: iterator MBBb = Fn . begin ( ) , MBBe = Fn . end ( ) ; MBBb != MBBe ; ++ MBBb ) { MachineBasicBlock * MBB = & * MBBb ; MachineBasicBlock :: iterator MII = MBB -> begin ( ) ; MachineBasicBlock :: iterator MIE = MBB -> end ( ) ; while ( MII != MIE ) { MachineInstr * MI = MII ; int Opc = MI -> getOpcode ( ) ; if ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isBlockAddress ( ) ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ;


<s> uint64_t ImmValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; B . erase ( & MI ) ; } else if ( Opc == <STR_LIT> ) { Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; Register DestLo = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; Register DestHi = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; int32_t LowWord = ( ImmValue & <NUM_LIT> ) ; int32_t HighWord = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestLo ) . addImm ( LowWord ) ;


<s> continue ; } else if ( Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned DestLo = Fn . getSubtarget ( ) . getRegisterInfo ( ) -> getSubReg ( DestReg , <STR_LIT> ) ; unsigned DestHi = Fn . getSubtarget ( ) . getRegisterInfo ( ) -> getSubReg ( DestReg , <STR_LIT> ) ; int32_t LowWord = ( ImmValue & <NUM_LIT> ) ; int32_t HighWord = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestLo ) . addImm ( LowWord ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestLo ) . addImm ( LowWord ) ;

BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestHi ) . addImm ( HighWord ) ;


<s> } else if ( Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned DestLo = Fn . getSubtarget ( ) . getRegisterInfo ( ) -> getSubReg ( DestReg , <STR_LIT> ) ; unsigned DestHi = Fn . getSubtarget ( ) . getRegisterInfo ( ) -> getSubReg ( DestReg , <STR_LIT> ) ; int32_t LowWord = ( ImmValue & <NUM_LIT> ) ; int32_t HighWord = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestLo ) . addImm ( LowWord ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestLo ) . addImm ( LowWord ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestHi ) . addImm ( HighWord ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestHi ) . addImm ( HighWord ) ; MII = MBB -> erase ( MI ) ;


<s> const TargetInstrInfo * TII = Fn . getSubtarget ( ) . getInstrInfo ( ) ; for ( MachineFunction :: iterator MBBb = Fn . begin ( ) , MBBe = Fn . end ( ) ; MBBb != MBBe ; ++ MBBb ) { MachineBasicBlock * MBB = MBBb ; MachineBasicBlock :: iterator MII = MBB -> begin ( ) ; MachineBasicBlock :: iterator MIE = MBB -> end ( ) ; while ( MII != MIE ) { MachineInstr * MI = MII ; int Opc = MI -> getOpcode ( ) ; if ( Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ; continue ; }


<s> FunctionPass * llvm :: create<ISA_LIT>SplitConst32AndConst64 ( ) {


<s> <ISA_LIT>SplitConst32AndConst64 ( ) : MachineFunctionPass ( ID ) {


<s> MachineBasicBlock * MBB = MBBb ; MachineBasicBlock :: iterator MII = MBB -> begin ( ) ; MachineBasicBlock :: iterator MIE = MBB -> end ( ) ; while ( MII != MIE ) { MachineInstr * MI = MII ; int Opc = MI -> getOpcode ( ) ; if ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isBlockAddress ( ) ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue ; if ( Opc == <STR_LIT> ) { APFloat Val = MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; ImmValue = * Val . bitcastToAPInt ( ) . getRawData ( ) ; } else ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue ; if ( Opc == <STR_LIT> ) { APFloat Val = MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; ImmValue = * Val . bitcastToAPInt ( ) . getRawData ( ) ;


<s> if ( TLOF . IsSmallDataEnabled ( ) ) return true ; const TargetInstrInfo * TII = Fn . getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; for ( MachineFunction :: iterator MBBb = Fn . begin ( ) , MBBe = Fn . end ( ) ; MBBb != MBBe ; ++ MBBb ) { MachineBasicBlock * MBB = MBBb ; MachineBasicBlock :: iterator MII = MBB -> begin ( ) ; MachineBasicBlock :: iterator MIE = MBB -> end ( ) ; while ( MII != MIE ) { MachineInstr * MI = MII ; int Opc = MI -> getOpcode ( ) ; if ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isBlockAddress ( ) ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue ; if ( Opc == <STR_LIT> ) { APFloat Val = MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; ImmValue = * Val . bitcastToAPInt ( ) . getRawData ( ) ; } else ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue ; if ( Opc == <STR_LIT> ) { APFloat Val = MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; ImmValue = * Val . bitcastToAPInt ( ) . getRawData ( ) ; } else ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned DestLo = TRI -> getSubReg ( DestReg , <STR_LIT> ) ;

unsigned DestHi = TRI -> getSubReg ( DestReg , <STR_LIT> ) ;


<s> UUPairMap :: const_iterator F = PairMap . find ( R ) ; if ( F == PairMap . end ( ) ) continue ; const UUPair & Pr = F -> second ; Register NewDR = MRI -> createVirtualRegister ( DoubleRC ) ; BuildMI ( B , MI , DL , TII -> get ( TargetOpcode :: REG_SEQUENCE ) , NewDR ) . addReg ( Pr . first ) . addImm ( <STR_LIT> ) . addReg ( Pr . second ) . addImm ( <STR_LIT> ) ;


<s> Register R = Op . getReg ( ) ; if ( ! R . isVirtual ( ) ) continue ; if ( MRI -> getRegClass ( R ) != DoubleRC || Op . getSubReg ( ) ) continue ; UUPairMap :: const_iterator F = PairMap . find ( R ) ; if ( F == PairMap . end ( ) ) continue ; const UUPair & Pr = F -> second ; Register NewDR = MRI -> createVirtualRegister ( DoubleRC ) ;

BuildMI ( B , MI , DL , TII -> get ( TargetOpcode :: REG_SEQUENCE ) , NewDR ) . addReg ( Pr . first ) . addImm ( <STR_LIT> ) . addReg ( Pr . second ) . addImm ( <STR_LIT> ) ;


<s> using LoopVector = std :: vector < MachineLoop * > ; LoopVector WorkQ ; append_range ( WorkQ , * MLI ) ; for ( unsigned i = <NUM_LIT> ; i < WorkQ . size ( ) ; ++ i ) append_range ( WorkQ , * WorkQ [ i ] ) ; USet Rs ; for ( unsigned i = <NUM_LIT> , n = WorkQ . size ( ) ; i < n ; ++ i ) { MachineLoop * L = WorkQ [ i ] ; Rs . clear ( ) ;


<s> if ( ! OkCI ) return ; if ( CmpR1 && MRI -> getRegClass ( CmpR1 ) != DoubleRC ) CmpR1 = <NUM_LIT> ; if ( CmpR2 && MRI -> getRegClass ( CmpR2 ) != DoubleRC ) CmpR2 = <NUM_LIT> ; if ( ! CmpR1 && ! CmpR2 ) return ; using UVect = std :: vector < unsigned > ; UVect DP ; for ( auto & MI : * HB ) { if ( ! MI . isPHI ( ) ) break ; const MachineOperand & MD = MI . getOperand ( <NUM_LIT> ) ; Register R = MD . getReg ( ) ; if ( MRI -> getRegClass ( R ) == DoubleRC ) DP . push_back ( R ) ; } if ( DP . empty ( ) ) return ; auto NoIndOp = [ this , CmpR1 , CmpR2 ] ( unsigned R ) -> bool { for ( auto I = MRI -> use_nodbg_begin ( R ) , E = MRI -> use_nodbg_end ( ) ; I != E ; ++ I ) { const MachineInstr * UseI = I -> getParent ( ) ; if ( UseI -> getOpcode ( ) != <STR_LIT> ) continue ; Register T = UseI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( T == CmpR1 || T == CmpR2 ) return false ; } return true ; } ; UVect :: iterator End = llvm :: remove_if ( DP , NoIndOp ) ; Rs . insert ( DP . begin ( ) , End ) ; Rs . insert ( CmpR1 ) ; Rs . insert ( CmpR2 ) ;


<s> if ( ! MI . isPHI ( ) ) break ; const MachineOperand & MD = MI . getOperand ( <NUM_LIT> ) ; Register R = MD . getReg ( ) ; if ( MRI -> getRegClass ( R ) == DoubleRC ) DP . push_back ( R ) ; } if ( DP . empty ( ) ) return ; auto NoIndOp = [ this , CmpR1 , CmpR2 ] ( unsigned R ) -> bool { for ( auto I = MRI -> use_nodbg_begin ( R ) , E = MRI -> use_nodbg_end ( ) ; I != E ; ++ I ) { const MachineInstr * UseI = I -> getParent ( ) ; if ( UseI -> getOpcode ( ) != <STR_LIT> ) continue ; Register T = UseI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( T == CmpR1 || T == CmpR2 ) return false ; } return true ; } ; UVect :: iterator End = llvm :: remove_if ( DP , NoIndOp ) ; Rs . insert ( DP . begin ( ) , End ) ; Rs . insert ( CmpR1 ) ; Rs . insert ( CmpR2 ) ; LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> << printMBBReference ( * HB ) << <STR_LIT> ; dump_partition ( dbgs ( ) , Rs , * TRI ) ;


<s> for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) ) { NewI -> addOperand ( Op ) ; continue ; } Register R = Op . getReg ( ) ; unsigned SR = Op . getSubReg ( ) ; bool isVirtReg = R . isVirtual ( ) ; bool isKill = Op . isKill ( ) ; if ( isVirtReg && MRI -> getRegClass ( R ) == DoubleRC ) { isKill = false ; UUPairMap :: const_iterator F = PairMap . find ( R ) ; if ( F == PairMap . end ( ) ) { SR = SubR ; } else { const UUPair & P = F -> second ; R = ( SubR == <STR_LIT> ) ? P . first : P . second ; SR = <NUM_LIT> ; } } auto CO = MachineOperand :: CreateReg ( R , Op . isDef ( ) , Op . isImplicit ( ) , isKill , Op . isDead ( ) , Op . isUndef ( ) , Op . isEarlyClobber ( ) , SR , Op . isDebug ( ) , Op . isInternalRead ( ) ) ; NewI -> addOperand ( CO ) ;


<s> case TargetOpcode :: PHI : case TargetOpcode :: COPY : break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) break ; return true ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) break ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s>
unsigned
R
=
Register
::
index2VirtReg
(
x
)
;
MachineInstr
*
DefI
=
MRI
->
getVRegDef
(
R
)
;
if
(
!
DefI
||
isFixedInstr
(
DefI
)
)
FixedRegs
.
set
(
x
)
;
}
UUSetMap
AssocMap
;
for
(
int
x
=
DoubleRegs
.
find_first
(
)
;
x
>=
<NUM_LIT>
;
x
=
DoubleRegs
.
find_next
(
x
)
)
{
if
(
FixedRegs
[
x
]
)
continue
;
unsigned
R
=
Register
::
index2VirtReg
(
x
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
printReg
(
R
,
TRI
)
<<
<STR_LIT>
)
;
USet
&
Asc
=
AssocMap
[
R
]
;
for
(
auto
U
=
MRI
->
use_nodbg_begin
(
R
)
,
Z
=
MRI
->
use_nodbg_end
(
)
;
U
!=
Z
;
++
U
)
{
MachineOperand
&
Op
=
*
U
;
MachineInstr
*
UseI
=
Op
.
getParent
(
)
;
if
(
isFixedInstr
(
UseI
)
)
continue
;
for
(
unsigned
i
=
<NUM_LIT>
,
n
=
UseI
->
getNumOperands
(
)
;
i
<
n
;
++
i
)
{
MachineOperand
&
MO
=
UseI
->
getOperand
(
i
)
;
if
(
&
MO
==
&
Op
||
!
MO
.
isReg
(
)
||
MO
.
getSubReg
(
)
)
continue
;
Register
T
=
MO
.
getReg
(
)
;
if
(
!
T
.
isVirtual
(
)
)
{
FixedRegs
.
set
(
x
)
;
continue
;
}
if
(
MRI
->
getRegClass
(
T
)
!=
DoubleRC
)
continue
;
unsigned
u
=
Register
::
virtReg2Index
(
T
)
;
if
(
FixedRegs
[
u
]
)
continue
;
LLVM_DEBUG
(
dbgs
(
)
<<
' '
<<
printReg
(
T
,
TRI
)
)
;
Asc
.
insert
(
T
)
;
AssocMap
[
T
]
.
insert
(
R
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
'\n'
)
;
}
UUMap
R2P
;
unsigned
NextP
=
<NUM_LIT>
;
USet
Visited
;
for
(
int
x
=
DoubleRegs
.
find_first
(
)
;
x
>=
<NUM_LIT>
;
x
=
DoubleRegs
.
find_next
(
x
)
)
{
unsigned
R
=
Register
::
index2VirtReg
(
x
)
;
if
(
Visited
.
count
(
R
)
)
continue
;
unsigned
ThisP
=
FixedRegs
[
x
]
<NUM_LIT>
:
NextP
++
;
UVect
WorkQ
;
WorkQ
.
push_back
(
R
)
;
for
(
unsigned
i
=
<NUM_LIT>
;
i
<
WorkQ
.
size
(
)
;
++
i
)
{
unsigned
T
=
WorkQ
[
i
]
;
if
(
Visited
.
count
(
T
)
)
continue
;
R2P
[
T
]
=
ThisP
;
Visited
.
insert
(
T
)
;
USet
&
Asc
=
AssocMap
[
T
]
;
append_range
(
WorkQ
,
Asc
)
;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return profit ( DefI ) ; default : break ; } return <NUM_LIT> ;


<s> void <ISA_LIT>SplitDoubleRegs :: collapseRegPairs ( MachineInstr * MI , const UUPairMap & PairMap ) { MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isUse ( ) ) continue ; unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; if ( MRI -> getRegClass ( R ) != DoubleRC || Op . getSubReg ( ) ) continue ; UUPairMap :: const_iterator F = PairMap . find ( R ) ;

if ( F == PairMap . end ( ) ) continue ;


<s> int Mask = <NUM_LIT> , Val = <NUM_LIT> ; bool OkCI = TII -> analyzeCompare ( * CmpI , CmpR1 , CmpR2 , Mask , Val ) ; if ( ! OkCI ) return ; if ( CmpR1 && MRI -> getRegClass ( CmpR1 ) != DoubleRC ) CmpR1 = <NUM_LIT> ; if ( CmpR2 && MRI -> getRegClass ( CmpR2 ) != DoubleRC ) CmpR2 = <NUM_LIT> ; if ( ! CmpR1 && ! CmpR2 ) return ; using UVect = std :: vector < unsigned > ; UVect DP ; for ( auto & MI : * HB ) { if ( ! MI . isPHI ( ) ) break ; const MachineOperand & MD = MI . getOperand ( <NUM_LIT> ) ; unsigned R = MD . getReg ( ) ; if ( MRI -> getRegClass ( R ) == DoubleRC ) DP . push_back ( R ) ; } if ( DP . empty ( ) ) return ; auto NoIndOp = [ this , CmpR1 , CmpR2 ] ( unsigned R ) -> bool {

for ( auto I = MRI -> use_nodbg_begin ( R ) , E = MRI -> use_nodbg_end ( ) ;


<s> bool isKill = Op . isKill ( ) ; if ( isVirtReg && MRI -> getRegClass ( R ) == DoubleRC ) { isKill = false ; UUPairMap :: const_iterator F = PairMap . find ( R ) ; if ( F == PairMap . end ( ) ) { SR = SubR ; } else { const UUPair & P = F -> second ; R = ( SubR == <STR_LIT> ) ? P . first : P . second ; SR = <NUM_LIT> ; } }

auto CO = MachineOperand :: CreateReg ( R , Op . isDef ( ) , Op . isImplicit ( ) , isKill , Op . isDead ( ) , Op . isUndef ( ) , Op . isEarlyClobber ( ) , SR , Op . isDebug ( ) , Op . isInternalRead ( ) ) ;


<s>
for
(
auto
I
:
Part
)
dbgs
(
)
<<
' '
<<
PrintReg
(
I
,
&
TRI
)
;
dbgs
(
)
<<
<STR_LIT>
;


<s> <ISA_LIT>SplitDoubleRegs ( ) : MachineFunctionPass ( ID ) {

initialize<ISA_LIT>SplitDoubleRegsPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> <ISA_LIT>SplitDoubleRegs ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>SplitDoubleRegsPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> MachineInstr * DefI = MRI -> getVRegDef ( DR ) ; int32_t P = profit ( DefI ) ; if ( P == std :: numeric_limits < int > :: min ( ) ) return false ; TotalP += P ; if ( isInduction ( DR , IRM ) ) TotalP -= <NUM_LIT> ; for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI -> use_nodbg_end ( ) ; U != W ; ++ U ) { MachineInstr * UseI = U -> getParent ( ) ; if ( isFixedInstr ( UseI ) ) { FixedNum ++ ; for ( auto & Op : UseI -> operands ( ) ) { if ( Op . isReg ( ) && Part . count ( Op . getReg ( ) ) ) if ( Op . getSubReg ( ) ) TotalP -= <NUM_LIT> ; } continue ; } if ( UseI -> isPHI ( ) ) { const MachineBasicBlock * PB = UseI -> getParent ( ) ;

const MachineLoop * L = MLI -> getLoopFor ( PB ) ;


<s>
using
UUMap
=
std
::
map
<
unsigned
,
unsigned
>
;
using
UVect
=
std
::
vector
<
unsigned
>
;
unsigned
NumRegs
=
MRI
->
getNumVirtRegs
(
)
;
BitVector
DoubleRegs
(
NumRegs
)
;
for
(
unsigned
i
=
<NUM_LIT>
;
i
<
NumRegs
;
++
i
)
{
unsigned
R
=
TargetRegisterInfo
::
index2VirtReg
(
i
)
;
if
(
MRI
->
getRegClass
(
R
)
==
DoubleRC
)
DoubleRegs
.
set
(
i
)
;
}
BitVector
FixedRegs
(
NumRegs
)
;
for
(
int
x
=
DoubleRegs
.
find_first
(
)
;
x
>=
<NUM_LIT>
;
x
=
DoubleRegs
.
find_next
(
x
)
)
{
unsigned
R
=
TargetRegisterInfo
::
index2VirtReg
(
x
)
;
MachineInstr
*
DefI
=
MRI
->
getVRegDef
(
R
)
;
if
(
!
DefI
||
isFixedInstr
(
DefI
)
)
FixedRegs
.
set
(
x
)
;
}
UUSetMap
AssocMap
;
for
(
int
x
=
DoubleRegs
.
find_first
(
)
;
x
>=
<NUM_LIT>
;
x
=
DoubleRegs
.
find_next
(
x
)
)
{
if
(
FixedRegs
[
x
]
)
continue
;
unsigned
R
=
TargetRegisterInfo
::
index2VirtReg
(
x
)
;
DEBUG
(
dbgs
(
)
<<
PrintReg
(
R
,
TRI
)
<<
<STR_LIT>
)
;
USet
&
Asc
=
AssocMap
[
R
]
;
for
(
auto
U
=
MRI
->
use_nodbg_begin
(
R
)
,
Z
=
MRI
->
use_nodbg_end
(
)
;
U
!=
Z
;
++
U
)
{
MachineOperand
&
Op
=
*
U
;
MachineInstr
*
UseI
=
Op
.
getParent
(
)
;
if
(
isFixedInstr
(
UseI
)
)
continue
;
for
(
unsigned
i
=
<NUM_LIT>
,
n
=
UseI
->
getNumOperands
(
)
;
i
<
n
;
++
i
)
{
MachineOperand
&
MO
=
UseI
->
getOperand
(
i
)
;
if
(
&
MO
==
&
Op
||
!
MO
.
isReg
(
)
||
MO
.
getSubReg
(
)
)
continue
;
unsigned
T
=
MO
.
getReg
(
)
;
if
(
!
TargetRegisterInfo
::
isVirtualRegister
(
T
)
)
{
FixedRegs
.
set
(
x
)
;
continue
;
}
if
(
MRI
->
getRegClass
(
T
)
!=
DoubleRC
)
continue
;
unsigned
u
=
TargetRegisterInfo
::
virtReg2Index
(
T
)
;
if
(
FixedRegs
[
u
]
)
continue
;
DEBUG
(
dbgs
(
)
<<
' '
<<
PrintReg
(
T
,
TRI
)
)
;
Asc
.
insert
(
T
)
;
AssocMap
[
T
]
.
insert
(
R
)
;
}
}
DEBUG
(
dbgs
(
)
<<
'\n'
)
;
}
UUMap
R2P
;
unsigned
NextP
=
<NUM_LIT>
;
USet
Visited
;
for
(
int
x
=
DoubleRegs
.
find_first
(
)
;
x
>=
<NUM_LIT>
;
x
=
DoubleRegs
.
find_next
(
x
)
)
{


<s> for ( const auto & Op : MI -> operands ( ) ) if ( ! Op . getSubReg ( ) ) return <NUM_LIT> ; return <NUM_LIT> ; case TargetOpcode :: COPY : if ( MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) != <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return - <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : { uint64_t D = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Lo = D & <NUM_LIT> ; unsigned Hi = D >> <NUM_LIT> ; return profitImm ( Lo , Hi ) ; } case <STR_LIT> : case <STR_LIT> : return profitImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : ImmX ++ ; LLVM_FALLTHROUGH ; case <STR_LIT> : { ImmX ++ ; int64_t V = MI -> getOperand ( ImmX ) . getImm ( ) ; if ( V == <NUM_LIT> || V == - <NUM_LIT> ) return <NUM_LIT> ; LLVM_FALLTHROUGH ; } case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : { unsigned S = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( S == <NUM_LIT> || S == <NUM_LIT> ) return <NUM_LIT> ; return - <NUM_LIT> ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : unsigned S = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( S == <NUM_LIT> || S == <NUM_LIT> ) return <NUM_LIT> ; if ( S == <NUM_LIT> ) return <NUM_LIT> ; if ( S == <NUM_LIT> ) return <NUM_LIT> ; return - <NUM_LIT> ; } return <NUM_LIT> ;


<s> for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isUse ( ) || ! Op . getSubReg ( ) ) continue ; unsigned R = Op . getReg ( ) ; UUPairMap :: const_iterator F = PairMap . find ( R ) ; if ( F == PairMap . end ( ) ) continue ; const UUPair & P = F -> second ; switch ( Op . getSubReg ( ) ) { case <STR_LIT> : Op . setReg ( P . first ) ; break ; case <STR_LIT> : Op . setReg ( P . second ) ; break ; }


<s> MachineOperand & Op3 = MI -> getOperand ( <NUM_LIT> ) ; assert ( Op0 . isReg ( ) && Op1 . isReg ( ) && Op2 . isReg ( ) && Op3 . isImm ( ) ) ; int64_t Sh64 = Op3 . getImm ( ) ; assert ( Sh64 >= <NUM_LIT> && Sh64 < <NUM_LIT> ) ; unsigned S = Sh64 ; UUPairMap :: const_iterator F = PairMap . find ( Op0 . getReg ( ) ) ; assert ( F != PairMap . end ( ) ) ; const UUPair & P = F -> second ; unsigned LoR = P . first ; unsigned HiR = P . second ; MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned RS1 = getRegState ( Op1 ) ; unsigned RS2 = getRegState ( Op2 ) ; const TargetRegisterClass * IntRC = & IntRegsRegClass ; unsigned LoSR = isub_lo ; unsigned HiSR = isub_hi ; if ( S == <NUM_LIT> ) { BuildMI ( B , MI , DL , TII -> get ( A2_or ) , LoR ) . addReg ( Op1 . getReg ( ) , RS1 & ~ RegState :: Kill , LoSR ) . addReg ( Op2 . getReg ( ) , RS2 & ~ RegState :: Kill , LoSR ) ; BuildMI ( B , MI , DL , TII -> get ( A2_or ) , HiR ) . addReg ( Op1 . getReg ( ) , RS1 , HiSR ) . addReg ( Op2 . getReg ( ) , RS2 , HiSR ) ; } else if ( S < <NUM_LIT> ) { BuildMI ( B , MI , DL , TII -> get ( S2_asl_i_r_or ) , LoR ) . addReg ( Op1 . getReg ( ) , RS1 & ~ RegState :: Kill , LoSR ) . addReg ( Op2 . getReg ( ) , RS2 & ~ RegState :: Kill , LoSR ) . addImm ( S ) ; unsigned TmpR1 = MRI -> createVirtualRegister ( IntRC ) ;

BuildMI ( B , MI , DL , TII -> get ( S2_extractu ) , TmpR1 ) . addReg ( Op2 . getReg ( ) , RS2 & ~ RegState :: Kill , LoSR ) . addImm ( S ) . addImm ( <NUM_LIT> - S ) ;


<s> case L2_loadrd_io : case L2_loadrd_pi : case S2_storerd_io : case S2_storerd_pi : splitMemRef ( MI , PairMap ) ; Split = true ; break ; case A2_tfrpi : case CONST64 : splitImmediate ( MI , PairMap ) ; Split = true ; break ; case A2_combineii : case A4_combineir : case A4_combineii : case A4_combineri : case A2_combinew : splitCombine ( MI , PairMap ) ; Split = true ; break ; case A2_sxtw : splitExt ( MI , PairMap ) ; Split = true ; break ; case S2_asl_i_p : case S2_asr_i_p : case S2_lsr_i_p : splitShift ( MI , PairMap ) ; Split = true ; break ; case S2_asl_i_p_or : splitAslOr ( MI , PairMap ) ; Split = true ; break ; default :


<s> using MISet = std :: set < MachineInstr * > ; const TargetRegisterClass * IntRC = & <STR_LIT> ; bool Changed = false ; DEBUG ( dbgs ( ) << <STR_LIT> ; dump_partition ( dbgs ( ) , Part , * TRI ) ; dbgs ( ) << '\n' ) ; UUPairMap PairMap ; MISet SplitIns ; for ( unsigned DR : Part ) { MachineInstr * DefI = MRI -> getVRegDef ( DR ) ; SplitIns . insert ( DefI ) ; for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI -> use_nodbg_end ( ) ; U != W ; ++ U ) SplitIns . insert ( U -> getParent ( ) ) ; unsigned LoR = MRI -> createVirtualRegister ( IntRC ) ; unsigned HiR = MRI -> createVirtualRegister ( IntRC ) ; DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( DR , TRI ) << <STR_LIT> << PrintReg ( HiR , TRI ) << ':' << PrintReg ( LoR , TRI ) << '\n' ) ; PairMap . insert ( std :: make_pair ( DR , UUPair ( LoR , HiR ) ) ) ; } MISet Erase ; for ( auto MI : SplitIns ) { if ( isFixedInstr ( MI ) ) { collapseRegPairs ( MI , PairMap ) ; } else { bool Done = splitInstr ( MI , PairMap ) ; if ( Done ) Erase . insert ( MI ) ; Changed |= Done ; } } for ( unsigned DR : Part ) { MISet Uses ; for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI -> use_nodbg_end ( ) ; U != W ; ++ U ) Uses . insert ( U -> getParent ( ) ) ; for ( auto M : Uses ) replaceSubregUses ( M , PairMap ) ; } for ( auto MI : Erase ) { MachineBasicBlock * B = MI -> getParent ( ) ; B -> erase ( MI ) ; }


<s> dbgs ( ) << '\n' ) ; UUPairMap PairMap ; MISet SplitIns ; for ( unsigned DR : Part ) { MachineInstr * DefI = MRI -> getVRegDef ( DR ) ; SplitIns . insert ( DefI ) ; for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI -> use_nodbg_end ( ) ; U != W ; ++ U ) SplitIns . insert ( U -> getParent ( ) ) ; unsigned LoR = MRI -> createVirtualRegister ( IntRC ) ; unsigned HiR = MRI -> createVirtualRegister ( IntRC ) ; DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( DR , TRI ) << <STR_LIT> << PrintReg ( HiR , TRI ) << ':' << PrintReg ( LoR , TRI ) << '\n' ) ; PairMap . insert ( std :: make_pair ( DR , UUPair ( LoR , HiR ) ) ) ; } MISet Erase ; for ( auto MI : SplitIns ) { if ( isFixedInstr ( MI ) ) { collapseRegPairs ( MI , PairMap ) ; } else { bool Done = splitInstr ( MI , PairMap ) ; if ( Done ) Erase . insert ( MI ) ; Changed |= Done ; } } for ( unsigned DR : Part ) {


<s> if ( DP . empty ( ) ) return ; auto NoIndOp = [ this , CmpR1 , CmpR2 ] ( unsigned R ) -> bool { for ( auto I = MRI -> use_nodbg_begin ( R ) , E = MRI -> use_nodbg_end ( ) ; I != E ; ++ I ) { const MachineInstr * UseI = I -> getParent ( ) ; if ( UseI -> getOpcode ( ) != <STR_LIT> ) continue ; unsigned T = UseI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( T == CmpR1 || T == CmpR2 ) return false ; } return true ; } ; UVect :: iterator End = llvm :: remove_if ( DP , NoIndOp ) ; Rs . insert ( DP . begin ( ) , End ) ; Rs . insert ( CmpR1 ) ; Rs . insert ( CmpR2 ) ; LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> << printMBBReference ( * HB ) << <STR_LIT> ; dump_partition ( dbgs ( ) , Rs , * TRI ) ;


<s> break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) break ; return true ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) break ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( MI -> isDebugInstr ( ) ) return false ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { default : return true ; case TargetOpcode :: PHI : case TargetOpcode :: COPY : break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) break ; return true ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) break ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> void <ISA_LIT>SplitDoubleRegs :: partitionRegisters ( UUSetMap & P2Rs ) { using UUMap = std :: map < unsigned , unsigned > ; using UVect = std :: vector < unsigned > ; unsigned NumRegs = MRI -> getNumVirtRegs ( ) ; BitVector DoubleRegs ( NumRegs ) ; for ( unsigned i = <NUM_LIT> ; i < NumRegs ; ++ i ) { unsigned R = TargetRegisterInfo :: index2VirtReg ( i ) ; if ( MRI -> getRegClass ( R ) == DoubleRC ) DoubleRegs . set ( i ) ; } BitVector FixedRegs ( NumRegs ) ; for ( int x = DoubleRegs . find_first ( ) ; x >= <NUM_LIT> ; x = DoubleRegs . find_next ( x ) ) { unsigned R = TargetRegisterInfo :: index2VirtReg ( x ) ; MachineInstr * DefI = MRI -> getVRegDef ( R ) ; if ( ! DefI || isFixedInstr ( DefI ) ) FixedRegs . set ( x ) ; } UUSetMap AssocMap ; for ( int x = DoubleRegs . find_first ( ) ; x >= <NUM_LIT> ; x = DoubleRegs . find_next ( x ) ) { if ( FixedRegs [ x ] ) continue ; unsigned R = TargetRegisterInfo :: index2VirtReg ( x ) ; LLVM_DEBUG ( dbgs ( ) << printReg ( R , TRI ) << <STR_LIT> ) ; USet & Asc = AssocMap [ R ] ; for ( auto U = MRI -> use_nodbg_begin ( R ) , Z = MRI -> use_nodbg_end ( ) ; U != Z ; ++ U ) { MachineOperand & Op = * U ; MachineInstr * UseI = Op . getParent ( ) ; if ( isFixedInstr ( UseI ) ) continue ; for ( unsigned i = <NUM_LIT> , n = UseI -> getNumOperands ( ) ; i < n ; ++ i ) { MachineOperand & MO = UseI -> getOperand ( i ) ; if ( & MO == & Op || ! MO . isReg ( ) || MO . getSubReg ( ) ) continue ; unsigned T = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( T ) ) { FixedRegs . set ( x ) ; continue ; } if ( MRI -> getRegClass ( T ) != DoubleRC ) continue ; unsigned u = TargetRegisterInfo :: virtReg2Index ( T ) ;


<s>
if
(
!
DefI
||
isFixedInstr
(
DefI
)
)
FixedRegs
.
set
(
x
)
;
}
UUSetMap
AssocMap
;
for
(
int
x
=
DoubleRegs
.
find_first
(
)
;
x
>=
<NUM_LIT>
;
x
=
DoubleRegs
.
find_next
(
x
)
)
{
if
(
FixedRegs
[
x
]
)
continue
;
unsigned
R
=
TargetRegisterInfo
::
index2VirtReg
(
x
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
printReg
(
R
,
TRI
)
<<
<STR_LIT>
)
;
USet
&
Asc
=
AssocMap
[
R
]
;
for
(
auto
U
=
MRI
->
use_nodbg_begin
(
R
)
,
Z
=
MRI
->
use_nodbg_end
(
)
;
U
!=
Z
;
++
U
)
{
MachineOperand
&
Op
=
*
U
;
MachineInstr
*
UseI
=
Op
.
getParent
(
)
;
if
(
isFixedInstr
(
UseI
)
)
continue
;
for
(
unsigned
i
=
<NUM_LIT>
,
n
=
UseI
->
getNumOperands
(
)
;
i
<
n
;
++
i
)
{
MachineOperand
&
MO
=
UseI
->
getOperand
(
i
)
;
if
(
&
MO
==
&
Op
||
!
MO
.
isReg
(
)
||
MO
.
getSubReg
(
)
)
continue
;
unsigned
T
=
MO
.
getReg
(
)
;
if
(
!
TargetRegisterInfo
::
isVirtualRegister
(
T
)
)
{
FixedRegs
.
set
(
x
)
;
continue
;
}
if
(
MRI
->
getRegClass
(
T
)
!=
DoubleRC
)
continue
;
unsigned
u
=
TargetRegisterInfo
::
virtReg2Index
(
T
)
;
if
(
FixedRegs
[
u
]
)
continue
;
LLVM_DEBUG
(
dbgs
(
)
<<
' '
<<
printReg
(
T
,
TRI
)
)
;
Asc
.
insert
(
T
)
;
AssocMap
[
T
]
.
insert
(
R
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
'\n'
)
;
}
UUMap
R2P
;
unsigned
NextP
=
<NUM_LIT>
;


<s> int32_t <ISA_LIT>SplitDoubleRegs :: profit ( unsigned Reg ) const { assert ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) ; const MachineInstr * DefI = MRI -> getVRegDef ( Reg ) ; switch ( DefI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return profit ( DefI ) ; default : break ; }


<s> createHalfInstr ( A2_and , MI , PairMap , isub_lo ) ; createHalfInstr ( A2_and , MI , PairMap , isub_hi ) ; Split = true ; break ; case A2_orp : createHalfInstr ( A2_or , MI , PairMap , isub_lo ) ; createHalfInstr ( A2_or , MI , PairMap , isub_hi ) ; Split = true ; break ; case A2_xorp : createHalfInstr ( A2_xor , MI , PairMap , isub_lo ) ; createHalfInstr ( A2_xor , MI , PairMap , isub_hi ) ; Split = true ; break ; case L2_loadrd_io : case L2_loadrd_pi : case S2_storerd_io : case S2_storerd_pi : splitMemRef ( MI , PairMap ) ; Split = true ; break ; case A2_tfrpi : case CONST64 : splitImmediate ( MI , PairMap ) ; Split = true ; break ; case A2_combineii : case A4_combineir : case A4_combineii : case A4_combineri : case A2_combinew : splitCombine ( MI , PairMap ) ; Split = true ; break ; case A2_sxtw : splitExt ( MI , PairMap ) ;


<s> collapseRegPairs ( MI , PairMap ) ; } else { bool Done = splitInstr ( MI , PairMap ) ; if ( Done ) Erase . insert ( MI ) ; Changed |= Done ; } } for ( unsigned DR : Part ) { MISet Uses ; for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI -> use_nodbg_end ( ) ; U != W ; ++ U ) Uses . insert ( U -> getParent ( ) ) ; for ( auto M : Uses ) replaceSubregUses ( M , PairMap ) ; } for ( auto MI : Erase ) { MachineBasicBlock * B = MI -> getParent ( ) ; B -> erase ( MI ) ; }


<s> dump_partition ( dbgs ( ) , Part , * TRI ) ; dbgs ( ) << '\n' ) ; UUPairMap PairMap ; MISet SplitIns ; for ( unsigned DR : Part ) { MachineInstr * DefI = MRI -> getVRegDef ( DR ) ; SplitIns . insert ( DefI ) ; for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI -> use_nodbg_end ( ) ; U != W ; ++ U ) SplitIns . insert ( U -> getParent ( ) ) ; unsigned LoR = MRI -> createVirtualRegister ( IntRC ) ; unsigned HiR = MRI -> createVirtualRegister ( IntRC ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( DR , TRI ) << <STR_LIT> << printReg ( HiR , TRI ) << ':' << printReg ( LoR , TRI ) << '\n' ) ; PairMap . insert ( std :: make_pair ( DR , UUPair ( LoR , HiR ) ) ) ; } MISet Erase ; for ( auto MI : SplitIns ) { if ( isFixedInstr ( MI ) ) { collapseRegPairs ( MI , PairMap ) ; } else { bool Done = splitInstr ( MI , PairMap ) ;