<s> switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ;

case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ;


<s> SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } unsigned Reg = MF . addLiveIn ( TRI -> getRARegister ( ) , getRegClassFor ( <STR_LIT> ) ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , Reg , VT ) ;


<s> if ( ! RetCC_<ISA_LIT>32 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! RetCC_<ISA_LIT>64 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; }


<s> SDNode * N = DAG . getMachineNode ( MachineOpc , dl , Ty , Ops ) ;


<s> bool isUndef ( SDValue Op ) const { if ( Op . isMachineOpcode ( ) ) return Op . getMachineOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ; return Op . getOpcode ( ) == <STR_LIT> ;


if ( Op . isMachineOpcode ( ) ) return Op . getMachineOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ;


<s> TypePair ty ( const VectorPair & Ops ) const { return { Ops . first . getValueType ( ) . getSimpleVT ( ) , Ops . second . getValueType ( ) . getSimpleVT ( ) } ;


<s> return { Ops . first . getValueType ( ) . getSimpleVT ( ) , Ops . second . getValueType ( ) . getSimpleVT ( ) } ;


<s> return <STR_LIT> ( Ty . getSizeInBits ( ) ) ;


<s> if ( ! Ty . isVector ( ) ) return Ty ;

return <STR_LIT> ( Ty . getSizeInBits ( ) ) ;


<s> unsigned TyWidth = Ty . getSizeInBits ( ) ; unsigned ElemWidth = ElemTy . getSizeInBits ( ) ;

assert ( ( TyWidth % ElemWidth ) == <NUM_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: allowTruncateForTailCall ( Type * Ty1 , Type * Ty2 ) const { if ( ! Ty1 -> isIntegerTy ( ) || ! Ty2 -> isIntegerTy ( ) ) return false ;

return Ty1 -> getPrimitiveSizeInBits ( ) <= <NUM_LIT> ;


<s> static bool CC_<ISA_LIT> ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { if ( ArgFlags . isByVal ( ) ) { unsigned Offset = State . AllocateStack ( ArgFlags . getByValSize ( ) , ArgFlags . getByValAlign ( ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; LocInfo = CCValAssign :: BCvt ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; LocInfo = CCValAssign :: BCvt ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! CC_<ISA_LIT>32 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! CC_<ISA_LIT>64 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { unsigned Offset = State . AllocateStack ( ArgFlags . getByValSize ( ) , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ;


<s> if ( unsigned Reg = State . AllocateReg ( RegList ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ;


<s> if ( unsigned Reg = State . AllocateReg ( <STR_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } static const MCPhysReg RegList1 [ ] = { <STR_LIT> , <STR_LIT> } ; static const MCPhysReg RegList2 [ ] = { <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList1 , RegList2 ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ;


<s> unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( ( UseHVX && UseHVXDbl ) && ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) ) { if ( unsigned Reg = State . AllocateReg ( VecLstD ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( ( UseHVX && UseHVXDbl ) && ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) ) { if ( unsigned Reg = State . AllocateReg ( VecLstS ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; }


<s> <ISA_LIT>CCState & HState = static_cast < <ISA_LIT>CCState & > ( State ) ; if ( ValNo < HState . getNumNamedVarArgParams ( ) ) { return CC_<ISA_LIT> ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ; } unsigned ofst ; if ( ArgFlags . isByVal ( ) ) { ofst = State . AllocateStack ( ArgFlags . getByValSize ( ) , ArgFlags . getByValAlign ( ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , ofst , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { ofst = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , ofst , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { ofst = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , ofst , LocVT , LocInfo ) ) ; return false ; }

if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) {


<s> return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getByValAlign ( ) , false , false , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> if ( VT . getSimpleVT ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Val ) ;


<s> static SDValue createSplat ( SelectionDAG & DAG , const SDLoc & dl , EVT VT , SDValue Val ) { if ( VT . getSimpleVT ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Val ) ; if ( VT . getSimpleVT ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Val ) ; return SDValue ( ) ;


<s> MachineFunction * MF = BB -> getParent ( ) ; auto * FuncInfo = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;

FuncInfo -> addAllocaAdjustInst ( & MI ) ;


<s> Value * <ISA_LIT>TargetLowering :: emitLoadLinked ( IRBuilder < > & Builder , Value * Addr , AtomicOrdering Ord ) const { BasicBlock * BB = Builder . GetInsertBlock ( ) ; Module * M = BB -> getParent ( ) -> getParent ( ) ; Type * Ty = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; unsigned SZ = Ty -> getPrimitiveSizeInBits ( ) ; assert ( ( SZ == <NUM_LIT> || SZ == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> IntID = ( SZ == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; Value * Fn = <STR_LIT> ( M , IntID ) ; return Builder . CreateCall ( Fn , Addr , <STR_LIT> ) ;


<s> assert ( ( SZ == <NUM_LIT> || SZ == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> IntID = ( SZ == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; Value * Fn = <STR_LIT> ( M , IntID ) ; Value * Call = Builder . CreateCall ( Fn , { Addr , Val } , <STR_LIT> ) ; Value * Cmp = Builder . CreateICmpEQ ( Call , Builder . getInt32 ( <NUM_LIT> ) , <STR_LIT> ) ; Value * Ext = Builder . CreateZExt ( Cmp , Type :: getInt32Ty ( M -> getContext ( ) ) ) ;


<s> Type * Ty = Val -> getType ( ) ; unsigned SZ = Ty -> getPrimitiveSizeInBits ( ) ; assert ( ( SZ == <NUM_LIT> || SZ == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> IntID = ( SZ == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; Value * Fn = <STR_LIT> ( M , IntID ) ; Value * Call = Builder . CreateCall ( Fn , { Addr , Val } , <STR_LIT> ) ;

Value * Cmp = Builder . CreateICmpEQ ( Call , Builder . getInt32 ( <NUM_LIT> ) , <STR_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : RRC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasV60TOps ( ) && Subtarget . useHVXOps ( ) && Subtarget . useHVXDblOps ( ) ) RRC = & <STR_LIT> ; else RRC = & <STR_LIT> ; break ; case <STR_LIT> :


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasV60TOps ( ) && Subtarget . useHVXOps ( ) && Subtarget . useHVXDblOps ( ) ) RRC = & <STR_LIT> ; else RRC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RRC = & <STR_LIT> ; break ; } return std :: make_pair ( RRC , Cost ) ;


<s> switch ( Constraint [ <NUM_LIT> ] ) { case 'q' : case 'v' : if ( Subtarget . useHVXOps ( ) ) return C_Register ;


<s> TargetLowering :: ConstraintType <ISA_LIT>TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == <NUM_LIT> ) {


<s> unsigned getExceptionPointerRegister ( const Constant * PersonalityFn ) const override {


<s> unsigned getExceptionPointerRegister ( const Constant * PersonalityFn ) const override { return <STR_LIT> ;


<s> static bool getIndexedAddressParts ( SDNode * Ptr , EVT VT , bool isSEXTLoad , SDValue & Base , SDValue & Offset , bool & isInc , SelectionDAG & DAG ) { if ( Ptr -> getOpcode ( ) != <STR_LIT> ) return false ; auto & HST = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ;


<s> if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_o ; return TargetLowering :: getInlineAsmMemConstraint ( ConstraintCode ) ;


<s> return TargetLowering :: getInlineAsmMemConstraint ( ConstraintCode ) ;


<s> unsigned getNumNamedVarArgParams ( ) const { return NumNamedVarArgParams ;


<s> SDValue <ISA_LIT>TargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { int Idx = cast < JumpTableSDNode > ( Table ) -> getIndex ( ) ; EVT VT = Table . getValueType ( ) ; SDValue T = DAG . getTargetJumpTable ( Idx , VT , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Table ) , VT , T ) ;


<s> SDValue <ISA_LIT>TargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { int Idx = cast < JumpTableSDNode > ( Table ) -> getIndex ( ) ; EVT VT = Table . getValueType ( ) ; SDValue T = DAG . getTargetJumpTable ( Idx , VT , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , SDLoc ( Table ) , VT , T ) ;


<s> } bool isInc = false ; bool isLegal = getIndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( isLegal ) { auto & HII = * Subtarget . getInstrInfo ( ) ; int32_t OffsetVal = cast < ConstantSDNode > ( Offset . getNode ( ) ) -> getSExtValue ( ) ; if ( HII . isValidAutoIncImm ( VT , OffsetVal ) ) {


<s> return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } case 'q' : switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } case 'v' : switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasV60TOps ( ) && UseHVX && UseHVXDbl ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> EVT getSetCCResultType ( const DataLayout & , LLVMContext & C , EVT VT ) const override { if ( ! VT . isVector ( ) ) return <STR_LIT> ; else return EVT :: getVectorVT ( C , <STR_LIT> , VT . getVectorNumElements ( ) ) ;


<s> else return EVT :: getVectorVT ( C , <STR_LIT> , VT . getVectorNumElements ( ) ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> <ISA_LIT>CCState ( CallingConv :: ID CC , bool isVarArg , MachineFunction & MF , SmallVectorImpl < CCValAssign > & locs , LLVMContext & C , int NumNamedVarArgParams ) : CCState ( CC , isVarArg , MF , locs , C ) , NumNamedVarArgParams ( NumNamedVarArgParams ) {


<s> for ( unsigned i = <NUM_LIT> , e = NElts ; i != e ; ++ i ) {

if ( BVN -> getOperand ( i ) != V0 ) return false ;


<s> bool CCMatch = CallerCC == CalleeCC ; if ( ! ( isa < GlobalAddressSDNode > ( Callee ) ) && ! ( isa < ExternalSymbolSDNode > ( Callee ) ) ) { return false ; } if ( ! CCMatch ) return false ; if ( isVarArg ) return false ; if ( isCalleeStructRet || isCallerStructRet ) return false ; return true ;


<s> bool CCMatch = CallerCC == CalleeCC ; if ( ! ( isa < GlobalAddressSDNode > ( Callee ) ) && ! ( isa < ExternalSymbolSDNode > ( Callee ) ) ) { return false ; } if ( ! CCMatch ) return false ; if ( isVarArg ) return false ; if ( isCalleeStructRet || isCallerStructRet ) return false ;


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { return Subtarget . hasV5TOps ( ) ;


<s> static bool IsHvxVectorType ( MVT ty ) { return ( ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> ) ;


<s> return ( ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> ) ;


<s> if ( Scale < <NUM_LIT> ) Scale = - Scale ; switch ( Scale ) { case <NUM_LIT> : break ; default : return false ; } return true ;


<s> return Imm >= - <NUM_LIT> && Imm <= <NUM_LIT> ;


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return HTM . getRelocationModel ( ) == Reloc :: Static ;


<s> bool llvm :: isPositiveHalfWord ( SDNode * N ) {

ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ;


<s> static bool isSExtFree ( SDValue N ) {

if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return true ;


<s> bool <ISA_LIT>TargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( ! VT1 . isSimple ( ) || ! VT2 . isSimple ( ) ) return false ;

return ( VT1 . getSimpleVT ( ) == <STR_LIT> ) && ( VT2 . getSimpleVT ( ) == <STR_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( ! VT1 . isSimple ( ) || ! VT2 . isSimple ( ) ) return false ; return ( VT1 . getSimpleVT ( ) == <STR_LIT> ) && ( VT2 . getSimpleVT ( ) == <STR_LIT> ) ;


<s> return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerATOMIC_FENCE ( SDValue Op , SelectionDAG & DAG ) const {


<s> Reloc :: Model RM = HTM . getRelocationModel ( ) ; if ( RM == Reloc :: Static ) { SDValue A = DAG . getTargetBlockAddress ( BA , PtrVT ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , A ) ; }

SDValue A = DAG . getTargetBlockAddress ( BA , PtrVT , <NUM_LIT> , <STR_LIT> ) ;


<s> const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDLoc dl ( Op ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; Reloc :: Model RM = HTM . getRelocationModel ( ) ; if ( RM == Reloc :: Static ) { SDValue A = DAG . getTargetBlockAddress ( BA , PtrVT ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , A ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue RetVal ; if ( RVLocs [ i ] . getValVT ( ) == <STR_LIT> ) { auto & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue FR0 = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , <STR_LIT> , InFlag ) ; unsigned PredR = MRI . createVirtualRegister ( & <STR_LIT> ) ; SDValue TPR = DAG . getCopyToReg ( FR0 . getValue ( <NUM_LIT> ) , dl , PredR , FR0 . getValue ( <NUM_LIT> ) , FR0 . getValue ( <NUM_LIT> ) ) ; RetVal = DAG . getCopyFromReg ( TPR . getValue ( <NUM_LIT> ) , dl , PredR , <STR_LIT> , TPR . getValue ( <NUM_LIT> ) ) ; } else { RetVal = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) ; } InVals . push_back ( RetVal . getValue ( <NUM_LIT> ) ) ;

Chain = RetVal . getValue ( <NUM_LIT> ) ;


<s> assert ( ( Width == <NUM_LIT> * <NUM_LIT> && Subtarget . useHVXSglOps ( ) ) || ( Width == <NUM_LIT> * <NUM_LIT> && Subtarget . useHVXDblOps ( ) ) ) ; SDValue Vec1 = Op . getOperand ( <NUM_LIT> ) ; MVT OpTy = Subtarget . useHVXSglOps ( ) ? <STR_LIT> : <STR_LIT> ; MVT ReTy = Subtarget . useHVXSglOps ( ) ? <STR_LIT> : <STR_LIT> ; SDValue B0 = DAG . getNode ( <STR_LIT> , dl , OpTy , Vec0 ) ; SDValue B1 = DAG . getNode ( <STR_LIT> , dl , OpTy , Vec1 ) ; SDValue VC = DAG . getNode ( <STR_LIT> , dl , ReTy , B1 , B0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , VC ) ; } } if ( VT . getSizeInBits ( ) != <NUM_LIT> && VT . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ; SDValue C0 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue C32 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue W = DAG . getConstant ( Width , dl , <STR_LIT> ) ; SDValue S = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , W , C32 ) ; SDValue V = C0 ;

for ( unsigned i = <NUM_LIT> , e = NElts ; i != e ; ++ i ) {


<s> EVT ValTy = Op . getValueType ( ) ; ConstantPoolSDNode * CPN = cast < ConstantPoolSDNode > ( Op ) ; unsigned Align = CPN -> getAlignment ( ) ; bool IsPositionIndependent = isPositionIndependent ( ) ; unsigned char TF = IsPositionIndependent ? <STR_LIT> : <NUM_LIT> ; SDValue T ; if ( CPN -> isMachineConstantPoolEntry ( ) ) T = DAG . getTargetConstantPool ( CPN -> getMachineCPVal ( ) , ValTy , Align , TF ) ; else T = DAG . getTargetConstantPool ( CPN -> getConstVal ( ) , ValTy , Align , TF ) ; if ( IsPositionIndependent ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , ValTy , T ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , ValTy , T ) ;


<s> if ( CPN -> isMachineConstantPoolEntry ( ) ) T = DAG . getTargetConstantPool ( CPN -> getMachineCPVal ( ) , ValTy , Align , TF ) ; else T = DAG . getTargetConstantPool ( CPN -> getConstVal ( ) , ValTy , Align , TF ) ; if ( IsPositionIndependent ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , ValTy , T ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , ValTy , T ) ;


<s> return DAG . getTargetConstant ( countPopulation ( V ) , dl , <STR_LIT> ) ; } SDValue PopOut = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InpVal ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , PopOut ) ;


<s> SDValue InpVal = Op . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( InpVal ) ) { uint64_t V = cast < ConstantSDNode > ( InpVal ) -> getZExtValue ( ) ; return DAG . getTargetConstant ( countPopulation ( V ) , dl , <STR_LIT> ) ; }

SDValue PopOut = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InpVal ) ;


<s> SDValue Align = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; ConstantSDNode * AlignConst = dyn_cast < ConstantSDNode > ( Align ) ; assert ( AlignConst && <STR_LIT> ) ; unsigned A = AlignConst -> getSExtValue ( ) ; auto & HFI = * Subtarget . getFrameLowering ( ) ;

if ( A == <NUM_LIT> ) A = HFI . getStackAlignment ( ) ;


<s> <ISA_LIT>MachineFunctionInfo * FuncInfo = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; FuncInfo -> setHasEHReturn ( ) ; unsigned OffsetReg = <STR_LIT> ; SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getRegister ( <STR_LIT> , PtrVT ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; Chain = DAG . getStore ( Chain , dl , Handler , StoreAddr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ;

Chain = DAG . getCopyToReg ( Chain , dl , OffsetReg , Offset ) ;


<s> FuncInfo -> setHasEHReturn ( ) ; unsigned OffsetReg = <STR_LIT> ; SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getRegister ( <STR_LIT> , PtrVT ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; Chain = DAG . getStore ( Chain , dl , Handler , StoreAddr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ;


<s> if ( W == <NUM_LIT> ) { unsigned Subreg = ( X == <NUM_LIT> ) ? <STR_LIT> : <NUM_LIT> ; if ( X == <NUM_LIT> ) Subreg = <STR_LIT> ; else if ( SVT == <STR_LIT> && X == <NUM_LIT> ) Subreg = <STR_LIT> ; else if ( SVT == <STR_LIT> && X == <NUM_LIT> ) Subreg = <STR_LIT> ; else if ( SVT == <STR_LIT> && X == <NUM_LIT> ) Subreg = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; N = DAG . getTargetExtractSubreg ( Subreg , dl , <STR_LIT> , Vec ) ; } else if ( VecVT . getSizeInBits ( ) == <NUM_LIT> ) { N = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } else { N = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) N = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , N ) ; } return DAG . getNode ( <STR_LIT> , dl , VT , N ) ; } SDValue Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Idx , DAG . getConstant ( EltSize , dl , <STR_LIT> ) ) ; SDValue Shifted = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Width , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Combined = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Shifted , Offset ) ; const SDValue Ops [ ] = { Vec , Combined } ;


<s> InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else if ( UseHVX && UseHVXDbl && ( ( RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> ) ) ) { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else if ( ( RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> ) ) { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else if ( UseHVX && UseHVXDbl && ( ( RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> ) ) ) { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else if ( RegVT == <STR_LIT> || RegVT == <STR_LIT> ) { assert ( <NUM_LIT> && <STR_LIT> ) ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else { assert ( <NUM_LIT> ) ; } } else if ( VA . isRegLoc ( ) && Flags . isByVal ( ) && Flags . getByValSize ( ) <= <NUM_LIT> ) { assert ( <NUM_LIT> && <STR_LIT> ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( Flags . isByVal ( ) ) { ObjSize = Flags . getByValSize ( ) ; } else { ObjSize = VA . getLocVT ( ) . getStoreSizeInBits ( ) >> <NUM_LIT> ; }

StackLocation = HEXAGON_LRFP_SIZE + VA . getLocMemOffset ( ) ;


<s> MFI . setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;

SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , HRI . getFrameRegister ( ) , VT ) ;


<s> SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , HRI . getFrameRegister ( ) , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> if ( UsePCRel ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , Offset , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA ) ; } SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Off = DAG . getConstant ( Offset , dl , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , dl , PtrVT , GOT , GA , Off ) ;


<s> case TLSModel :: LocalDynamic : return LowerToTLSGeneralDynamicModel ( GA , DAG ) ; case TLSModel :: InitialExec : return LowerToTLSInitialExecModel ( GA , DAG ) ; case TLSModel :: LocalExec : return LowerToTLSLocalExecModel ( GA , DAG ) ; }


<s> return LowerToTLSInitialExecModel ( GA , DAG ) ; case TLSModel :: LocalExec : return LowerToTLSLocalExecModel ( GA , DAG ) ; } llvm_unreachable ( <STR_LIT> ) ;


<s> EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue GOTSym = DAG . getTargetExternalSymbol ( HEXAGON_GOT_SYM_NAME , PtrVT , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , PtrVT , GOTSym ) ;


<s> EVT VT = Op . getValueType ( ) ; int VTN = VT . isVector ( ) ? VT . getVectorNumElements ( ) : <NUM_LIT> ; SDLoc dl ( Op ) ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; SDValue Val = Op . getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = Vec . getValueType ( ) ; EVT EltVT = VecVT . getVectorElementType ( ) ; int EltSize = EltVT . getSizeInBits ( ) ; SDValue Width = DAG . getConstant ( Op . getOpcode ( ) == <STR_LIT> ? EltSize : VTN * EltSize , dl , <STR_LIT> ) ; if ( ConstantSDNode * C = cast < ConstantSDNode > ( Idx ) ) { SDValue Offset = DAG . getConstant ( C -> getSExtValue ( ) * EltSize , dl , <STR_LIT> ) ; const SDValue Ops [ ] = { Vec , Val , Width , Offset } ; SDValue N ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) N = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; else N = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N ) ; } SDValue Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Idx , DAG . getConstant ( EltSize , dl , <STR_LIT> ) ) ; SDValue Shifted = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Width , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Combined = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Shifted , Offset ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && Val . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> ) { SDValue C = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; Val = DAG . getNode ( <STR_LIT> , dl , VT , C , Val ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerINTRINSIC_VOID ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( IntNo == <STR_LIT> ) { SDValue Addr = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , Addr , Zero ) ;


<s> return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , T ) ; } SDValue T = DAG . getTargetJumpTable ( Idx , VT ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , T ) ;


<s> if ( isPositionIndependent ( ) ) { SDValue T = DAG . getTargetJumpTable ( Idx , VT , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , T ) ; }

SDValue T = DAG . getTargetJumpTable ( Idx , VT ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerLOAD ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; LoadSDNode * LoadNode = cast < LoadSDNode > ( Op ) ; SDValue Chain = LoadNode -> getChain ( ) ; SDValue Ptr = Op . getOperand ( <NUM_LIT> ) ; SDValue LoweredLoad ; SDValue Result ; SDValue Base = LoadNode -> getBasePtr ( ) ; <STR_LIT> Ext = LoadNode -> getExtensionType ( ) ; unsigned Alignment = LoadNode -> getAlignment ( ) ; SDValue LoadChain ; if ( Ext == <STR_LIT> ) Ext = <STR_LIT> ; if ( VT == <STR_LIT> ) { if ( Alignment == <NUM_LIT> ) { SDValue Loads [ <NUM_LIT> ] ; Loads [ <NUM_LIT> ] = DAG . getExtLoad ( Ext , DL , <STR_LIT> , Chain , Base , LoadNode -> getPointerInfo ( ) , <STR_LIT> , LoadNode -> isVolatile ( ) , LoadNode -> isNonTemporal ( ) , LoadNode -> isInvariant ( ) , Alignment ) ; SDValue Increment = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , Base . getValueType ( ) , Base , Increment ) ; Loads [ <NUM_LIT> ] = DAG . getExtLoad ( Ext , DL , <STR_LIT> , Chain , Ptr , LoadNode -> getPointerInfo ( ) , <STR_LIT> , LoadNode -> isVolatile ( ) , LoadNode -> isNonTemporal ( ) , LoadNode -> isInvariant ( ) , Alignment ) ;

SDValue ShiftAmount = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ;


<s> unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { default : Op . getNode ( ) -> dumpr ( & DAG ) ; if ( Opc > <STR_LIT> && Opc < <STR_LIT> ) errs ( ) << <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> :

case <STR_LIT> : return LowerVECTOR_SHIFT ( Op , DAG ) ;


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Addr = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , Addr , Zero ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & dl , SelectionDAG & DAG ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ;

RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ;


<s> const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } unsigned Reg = MF . addLiveIn ( HRI . getRARegister ( ) , getRegClassFor ( <STR_LIT> ) ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , Reg , VT ) ;


<s> SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Cmp ) -> get ( ) ; EVT VT = Op . getValueType ( ) ; EVT LHSVT = LHS . getValueType ( ) ; EVT RHSVT = RHS . getValueType ( ) ; if ( LHSVT == <STR_LIT> ) { assert ( <STR_LIT> ( CC ) || <STR_LIT> ( CC ) ) ; unsigned ExtOpc = <STR_LIT> ( CC ) ? <STR_LIT> : <STR_LIT> ; SDValue LX = DAG . getNode ( ExtOpc , dl , <STR_LIT> , LHS ) ; SDValue RX = DAG . getNode ( ExtOpc , dl , <STR_LIT> , RHS ) ; SDValue SC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LX , RX , Cmp ) ; return SC ; } if ( VT . isVector ( ) ) return Op ; if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && ( RHSVT == <STR_LIT> || RHSVT == <STR_LIT> ) && ( LHSVT == <STR_LIT> || LHSVT == <STR_LIT> ) ) { ConstantSDNode * C = dyn_cast < ConstantSDNode > ( RHS ) ; if ( C && C -> getAPIntValue ( ) . isNegative ( ) ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS , Op . getOperand ( <NUM_LIT> ) ) ; } if ( isSExtFree ( LHS ) || isSExtFree ( RHS ) ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS , Op . getOperand ( <NUM_LIT> ) ) ;


<s> SDValue InFlag ; Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , Chain , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; return GetDynamicTLSAddr ( DAG , Chain , GA , & InFlag , PtrVT , <STR_LIT> , <STR_LIT> ) ;


<s> SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , PtrVT , Offset , <STR_LIT> ) ; SDValue GOT = LowerGLOBAL_OFFSET_TABLE ( TGA , DAG ) ; SDValue Sym = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA ) ;

SDValue Chain = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOT , Sym ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerToTLSInitialExecModel ( GlobalAddressSDNode * GA , SelectionDAG & DAG ) const { SDLoc dl ( GA ) ; int64_t Offset = GA -> getOffset ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue TP = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , PtrVT ) ; bool IsPositionIndependent = isPositionIndependent ( ) ; unsigned char TF = IsPositionIndependent ? <STR_LIT> : <STR_LIT> ; SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , PtrVT , Offset , TF ) ; SDValue Sym = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA ) ; if ( IsPositionIndependent ) { SDValue GOT = LowerGLOBAL_OFFSET_TABLE ( Sym , DAG ) ;

Sym = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOT , Sym ) ;


<s> auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue TP = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , PtrVT ) ; SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , PtrVT , Offset , <STR_LIT> ) ; SDValue Sym = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA ) ;

return DAG . getNode ( <STR_LIT> , dl , PtrVT , TP , Sym ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * QFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SDValue Addr = DAG . getFrameIndex ( QFI -> getVarArgsFrameIndex ( ) , <STR_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;

return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , Addr , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ;


<s> return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , Addr , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ;


<s> BuildVectorSDNode * BVN = <NUM_LIT> ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; SDValue V3 ; SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( ( BVN = dyn_cast < BuildVectorSDNode > ( V1 . getNode ( ) ) ) && isCommonSplatElement ( BVN ) ) V3 = V2 ; else if ( ( BVN = dyn_cast < BuildVectorSDNode > ( V2 . getNode ( ) ) ) && isCommonSplatElement ( BVN ) ) V3 = V1 ; else return SDValue ( ) ; SDValue CommonSplat = BVN -> getOperand ( <NUM_LIT> ) ; SDValue Result ; if ( VT . getSimpleVT ( ) == <STR_LIT> ) { switch ( Op . getOpcode ( ) ) { case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , V3 , CommonSplat ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , V3 , CommonSplat ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , V3 , CommonSplat ) ; break ; default :


<s> SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( V2 . isUndef ( ) ) V2 = V1 ; if ( SVN -> isSplat ( ) ) { int Lane = SVN -> getSplatIndex ( ) ; if ( Lane == - <NUM_LIT> ) Lane = <NUM_LIT> ; if ( Lane == <NUM_LIT> && V1 . getOpcode ( ) == <STR_LIT> ) return createSplat ( DAG , dl , VT , V1 . getOperand ( <NUM_LIT> ) ) ;

if ( Lane == <NUM_LIT> && V1 . getOpcode ( ) == <STR_LIT> && ! isa < ConstantSDNode > ( V1 . getOperand ( <NUM_LIT> ) ) ) {


<s> SDValue Op1 = Op . getOperand ( <NUM_LIT> ) , Op2 = Op . getOperand ( <NUM_LIT> ) ; EVT OpVT = Op1 . getValueType ( ) ; SDLoc DL ( Op ) ; if ( OpVT == <STR_LIT> ) { SDValue X1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op1 ) ; SDValue X2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op2 ) ; SDValue SL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , PredOp , X1 , X2 ) ; SDValue TR = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SL ) ; return TR ;


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( <STR_LIT> ) ;

if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == <STR_LIT> ) return false ;


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( <STR_LIT> ) ; if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == <STR_LIT> ) return false ;


<s> setOperationAction ( <STR_LIT> , VT , Promote ) ; AddPromotedToType ( <STR_LIT> , VT , PromotedLdStVT ) ; }


<s> LocVT = <STR_LIT> ; LocInfo = CCValAssign :: BCvt ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; LocInfo = CCValAssign :: Full ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || ( LocVT == <STR_LIT> && UseHVX && UseHVXDbl ) ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; LocInfo = CCValAssign :: Full ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; LocInfo = CCValAssign :: Full ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! RetCC_<ISA_LIT>32 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! RetCC_<ISA_LIT>64 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) {

if ( ! RetCC_<ISA_LIT>Vector ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ;


<s> static bool RetCC_<ISA_LIT>32 ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( unsigned Reg = State . AllocateReg ( <STR_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ;


<s> if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( unsigned Reg = State . AllocateReg ( <STR_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ;

State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ;


<s> return false ; } } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ;


<s> auto & MF = State . getMachineFunction ( ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool UseHVX = HST . useHVXOps ( ) ; bool UseHVXDbl = HST . useHVXDblOps ( ) ; unsigned OffSiz = <NUM_LIT> ; if ( LocVT == <STR_LIT> ) { if ( unsigned Reg = State . AllocateReg ( <STR_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; }


<s> unsigned Size = DL . getTypeStoreSize ( AI -> getCompareOperand ( ) -> getType ( ) ) ; return Size >= <NUM_LIT> && Size <= <NUM_LIT> ;


<s> const DataLayout & DL = AI -> getModule ( ) -> getDataLayout ( ) ; unsigned Size = DL . getTypeStoreSize ( AI -> getCompareOperand ( ) -> getType ( ) ) ;

return Size >= <NUM_LIT> && Size <= <NUM_LIT> ;


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const {

return LI -> getType ( ) -> getPrimitiveSizeInBits ( ) > <NUM_LIT> ? AtomicExpansionKind :: LLOnly : AtomicExpansionKind :: None ;


<s> return LI -> getType ( ) -> getPrimitiveSizeInBits ( ) > <NUM_LIT> ? AtomicExpansionKind :: LLOnly : AtomicExpansionKind :: None ;


<s> AtomicExpansionKind shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const override {


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const {

return SI -> getValueOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) > <NUM_LIT> ;


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const { return SI -> getValueOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) > <NUM_LIT> ;


<s> EVT EltVT = VT . getVectorElementType ( ) ;

int EltBits = EltVT . getSizeInBits ( ) ;


<s> if ( ( EltBits != <NUM_LIT> ) && ( EltBits != <NUM_LIT> ) ) return false ;

return TargetLowering :: shouldExpandBuildVectorWithShuffles ( VT , DefinedValues ) ;


<s> bool <ISA_LIT>TargetLowering :: allowsMemoryAccess ( LLVMContext & Context , const DataLayout & DL , EVT VT , unsigned AddrSpace , Align Alignment , MachineMemOperand :: Flags Flags , bool * Fast ) const { MVT SVT = VT . getSimpleVT ( ) ; if ( Subtarget . isHVXVectorType ( SVT , true ) ) return allowsHvxMemoryAccess ( SVT , Flags , Fast ) ; return TargetLoweringBase :: allowsMemoryAccess ( Context , DL , VT , AddrSpace , Alignment , Flags , Fast ) ;


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Alignment , MachineMemOperand :: Flags Flags , bool * Fast ) const { MVT SVT = VT . getSimpleVT ( ) ; if ( Subtarget . isHVXVectorType ( SVT , true ) ) return allowsHvxMisalignedMemoryAccesses ( SVT , Flags , Fast ) ; if ( Fast ) * Fast = false ;


<s> unsigned ValLen = ValTy . getVectorNumElements ( ) ; unsigned ResLen = ResTy . getVectorNumElements ( ) ; if ( ValLen == ResLen ) return Val ; const SDLoc & dl ( Val ) ; assert ( ValLen < ResLen ) ; assert ( ResLen % ValLen == <NUM_LIT> ) ;

SmallVector < SDValue , <NUM_LIT> > Concats = { Val } ;


<s> assert ( Elem . size ( ) == <NUM_LIT> ) ; if ( AllConst ) { uint32_t V = ( Consts [ <NUM_LIT> ] -> getZExtValue ( ) & <NUM_LIT> ) | Consts [ <NUM_LIT> ] -> getZExtValue ( ) << <NUM_LIT> ; return DAG . getBitcast ( <STR_LIT> , DAG . getConstant ( V , dl , <STR_LIT> ) ) ; } SDValue N = getInstr ( <STR_LIT> , dl , <STR_LIT> , { Elem [ <NUM_LIT> ] , Elem [ <NUM_LIT> ] } , DAG ) ; return DAG . getBitcast ( <STR_LIT> , N ) ; } if ( ElemTy == <STR_LIT> ) { if ( AllConst ) { int32_t V = ( Consts [ <NUM_LIT> ] -> getZExtValue ( ) & <NUM_LIT> ) | ( Consts [ <NUM_LIT> ] -> getZExtValue ( ) & <NUM_LIT> ) << <NUM_LIT> | ( Consts [ <NUM_LIT> ] -> getZExtValue ( ) & <NUM_LIT> ) << <NUM_LIT> | Consts [ <NUM_LIT> ] -> getZExtValue ( ) << <NUM_LIT> ; return DAG . getBitcast ( <STR_LIT> , DAG . getConstant ( V , dl , <STR_LIT> ) ) ; } bool IsSplat = true ; for ( unsigned i = First + <NUM_LIT> ; i != Num ; ++ i ) { if ( Elem [ i ] == Elem [ First ] || isUndef ( Elem [ i ] ) ) continue ; IsSplat = false ; break ; } if ( IsSplat ) { SDValue Ext = DAG . getZExtOrTrunc ( Elem [ First ] , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , Ext ) ; } assert ( Elem . size ( ) == <NUM_LIT> ) ; SDValue Vs [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { Vs [ i ] = DAG . getZExtOrTrunc ( Elem [ i ] , dl , <STR_LIT> ) ; Vs [ i ] = DAG . getZeroExtendInReg ( Vs [ i ] , dl , <STR_LIT> ) ; } SDValue S8 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue T0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { Vs [ <NUM_LIT> ] , S8 } ) ;

SDValue T1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { Vs [ <NUM_LIT> ] , S8 } ) ;


<s> MVT ElemTy = VecTy . getVectorElementType ( ) ; assert ( VecTy . getVectorNumElements ( ) == Elem . size ( ) ) ; SmallVector < ConstantInt * , <NUM_LIT> > Consts ( Elem . size ( ) ) ; bool AllConst = getBuildVectorConstInts ( Elem , VecTy , DAG , Consts ) ; unsigned First , Num = Elem . size ( ) ; for ( First = <NUM_LIT> ; First != Num ; ++ First ) { if ( ! isUndef ( Elem [ First ] ) ) break ; } if ( First == Num ) return DAG . getUNDEF ( VecTy ) ; if ( AllConst && llvm :: all_of ( Consts , [ ] ( ConstantInt * CI ) { return CI -> isZero ( ) ; } ) ) return getZero ( dl , VecTy , DAG ) ; if ( ElemTy == <STR_LIT> ) { bool IsSplat = true ; for ( unsigned i = First + <NUM_LIT> ; i != Num ; ++ i ) { if ( Elem [ i ] == Elem [ First ] || isUndef ( Elem [ i ] ) ) continue ; IsSplat = false ; break ; } if ( IsSplat ) { SDValue Ext = DAG . getZExtOrTrunc ( Elem [ First ] , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , Ext ) ; } } if ( AllConst ) { uint64_t Val = <NUM_LIT> ; unsigned W = ElemTy . getSizeInBits ( ) ; uint64_t Mask = ( ElemTy == <STR_LIT> ) ? <NUM_LIT> : ( ElemTy == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != Num ; ++ i ) Val = ( Val << W ) | ( Consts [ Num - <NUM_LIT> - i ] -> getZExtValue ( ) & Mask ) ;

SDValue V0 = DAG . getConstant ( Val , dl , <STR_LIT> ) ;


<s> for ( unsigned i = First + <NUM_LIT> ; i != Num ; ++ i ) { if ( Elem [ i ] == Elem [ First ] || isUndef ( Elem [ i ] ) ) continue ; IsSplat = false ; break ; } if ( IsSplat ) { SDValue Ext = DAG . getZExtOrTrunc ( Elem [ First ] , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , Ext ) ; } } if ( AllConst ) { uint64_t Val = <NUM_LIT> ; unsigned W = ElemTy . getSizeInBits ( ) ; uint64_t Mask = ( ElemTy == <STR_LIT> ) ? <NUM_LIT> : ( ElemTy == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != Num ; ++ i ) Val = ( Val << W ) | ( Consts [ Num - <NUM_LIT> - i ] -> getZExtValue ( ) & Mask ) ; SDValue V0 = DAG . getConstant ( Val , dl , <STR_LIT> ) ; return DAG . getBitcast ( VecTy , V0 ) ; } MVT HalfTy = <STR_LIT> ( ElemTy , Num / <NUM_LIT> ) ; SDValue L = ( ElemTy == <STR_LIT> ) ? Elem [ <NUM_LIT> ] : buildVector32 ( Elem . take_front ( Num / <NUM_LIT> ) , dl , HalfTy , DAG ) ; SDValue H = ( ElemTy == <STR_LIT> ) ? Elem [ <NUM_LIT> ] : buildVector32 ( Elem . drop_front ( Num / <NUM_LIT> ) , dl , HalfTy , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , { H , L } ) ;


<s> SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , dl , <STR_LIT> ) ;

return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getNonZeroByValAlign ( ) , false , false , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> static SDValue CreateCopyOfByValArgument ( SDValue Src , SDValue Dst , SDValue Chain , <STR_LIT> Flags , SelectionDAG & DAG , const SDLoc & dl ) { SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , dl , <STR_LIT> ) ;


<s> assert ( ( SZ == <NUM_LIT> || SZ == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> IntID = ( SZ == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; Function * Fn = <STR_LIT> ( M , IntID ) ;

PointerType * NewPtrTy = Builder . getIntNTy ( SZ ) -> getPointerTo ( PT -> getAddressSpace ( ) ) ;


<s> Type * CastTy = Builder . getIntNTy ( SZ ) ; assert ( ( SZ == <NUM_LIT> || SZ == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> IntID = ( SZ == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; Function * Fn = <STR_LIT> ( M , IntID ) ; unsigned AS = Addr -> getType ( ) -> getPointerAddressSpace ( ) ; Addr = Builder . CreateBitCast ( Addr , CastTy -> getPointerTo ( AS ) ) ; Val = Builder . CreateBitCast ( Val , CastTy ) ; Value * Call = Builder . CreateCall ( Fn , { Addr , Val } , <STR_LIT> ) ; Value * Cmp = Builder . CreateICmpEQ ( Call , Builder . getInt32 ( <NUM_LIT> ) , <STR_LIT> ) ; Value * Ext = Builder . CreateZExt ( Cmp , Type :: getInt32Ty ( M -> getContext ( ) ) ) ;


<s> Module * M = BB -> getParent ( ) -> getParent ( ) ; Type * Ty = Val -> getType ( ) ; unsigned SZ = Ty -> getPrimitiveSizeInBits ( ) ; Type * CastTy = Builder . getIntNTy ( SZ ) ; assert ( ( SZ == <NUM_LIT> || SZ == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> IntID = ( SZ == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; Function * Fn = <STR_LIT> ( M , IntID ) ; unsigned AS = Addr -> getType ( ) -> getPointerAddressSpace ( ) ;

Addr = Builder . CreateBitCast ( Addr , CastTy -> getPointerTo ( AS ) ) ;


<s> if ( Op . size ( ) >= <NUM_LIT> && Op . isAligned ( Align ( <NUM_LIT> ) ) ) return <STR_LIT> ; if ( Op . size ( ) >= <NUM_LIT> && Op . isAligned ( Align ( <NUM_LIT> ) ) ) return <STR_LIT> ;


<s> if ( Op . size ( ) >= <NUM_LIT> && Op . isAligned ( Align ( <NUM_LIT> ) ) ) return <STR_LIT> ; if ( Op . size ( ) >= <NUM_LIT> && Op . isAligned ( Align ( <NUM_LIT> ) ) ) return <STR_LIT> ; if ( Op . size ( ) >= <NUM_LIT> && Op . isAligned ( Align ( <NUM_LIT> ) ) ) return <STR_LIT> ;


<s> TargetLoweringBase :: LegalizeTypeAction <ISA_LIT>TargetLowering :: getPreferredVectorAction ( MVT VT ) const { unsigned VecLen = VT . getVectorNumElements ( ) ; MVT ElemTy = VT . getVectorElementType ( ) ; if ( VecLen == <NUM_LIT> || VT . isScalableVector ( ) ) return TargetLoweringBase :: TypeScalarizeVector ; if ( Subtarget . useHVXOps ( ) ) { unsigned Action = getPreferredHvxVectorAction ( VT ) ; if ( Action != ~ <NUM_LIT> ) return static_cast < TargetLoweringBase :: LegalizeTypeAction > ( Action ) ; } if ( ElemTy == <STR_LIT> ) return TargetLoweringBase :: TypeWidenVector ; return TargetLoweringBase :: TypeSplitVector ;


<s> TargetLoweringBase :: LegalizeTypeAction <ISA_LIT>TargetLowering :: getPreferredVectorAction ( MVT VT ) const { unsigned VecLen = VT . getVectorNumElements ( ) ; MVT ElemTy = VT . getVectorElementType ( ) ; if ( VecLen == <NUM_LIT> || VT . isScalableVector ( ) ) return TargetLoweringBase :: TypeScalarizeVector ; if ( Subtarget . useHVXOps ( ) ) { unsigned Action = getPreferredHvxVectorAction ( VT ) ; if ( Action != ~ <NUM_LIT> ) return static_cast < TargetLoweringBase :: LegalizeTypeAction > ( Action ) ;


<s> Register <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , LLT VT , const MachineFunction & ) const { Register Reg = StringSwitch < Register > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( Register ( ) ) ; if ( Reg ) return Reg ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : break ; }


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : break ; } return nullptr ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const Module & M = * I . getParent ( ) -> getParent ( ) -> getParent ( ) ; Info . opc = <STR_LIT> ; Type * VecTy = I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ; Info . memVT = <STR_LIT> ( VecTy ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = MaybeAlign ( M . getDataLayout ( ) . getTypeAllocSizeInBits ( VecTy ) / <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ;


<s> NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; const SDLoc & dl ( Op ) ; switch ( Op1 . getOpcode ( ) ) { case <STR_LIT> : if ( SDValue S = cast < BuildVectorSDNode > ( Op1 ) -> getSplatValue ( ) ) return DAG . getNode ( NewOpc , dl , ty ( Op ) , Op0 , S ) ;


<s> if ( W <= <NUM_LIT> ) return DAG . getBitcast ( Ty , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ( W ) ) ) ; return DAG . getNode ( <STR_LIT> , dl , Ty , getZero ( dl , <STR_LIT> , DAG ) ) ; } if ( Ty . isInteger ( ) ) return DAG . getConstant ( <NUM_LIT> , dl , Ty ) ; if ( Ty . isFloatingPoint ( ) ) return DAG . getConstantFP ( <NUM_LIT> , dl , Ty ) ; llvm_unreachable ( <STR_LIT> ) ;


<s> return DAG . getNode ( <STR_LIT> , dl , Ty , getZero ( dl , <STR_LIT> , DAG ) ) ; } if ( Ty . isInteger ( ) ) return DAG . getConstant ( <NUM_LIT> , dl , Ty ) ; if ( Ty . isFloatingPoint ( ) ) return DAG . getConstantFP ( <NUM_LIT> , dl , Ty ) ;


<s> return X . getValueType ( ) . isScalarInteger ( ) ;


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { return true ;


<s> Align A = DL . getABITypeAlign ( Ty ) ; if ( ! isAligned ( A , AM . BaseOffs ) ) return false ; if ( ! isInt < <NUM_LIT> > ( AM . BaseOffs >> Log2 ( A ) ) ) return false ; } if ( AM . BaseGV ) return false ; int Scale = AM . Scale ; if ( Scale < <NUM_LIT> ) Scale = - Scale ; switch ( Scale ) { case <NUM_LIT> : break ;


<s> SDValue Sc = DAG . getBitcast ( tyScalar ( InpTy ) , InpV ) ; SDValue Ext = DAG . getZExtOrTrunc ( Sc , dl , <STR_LIT> ) ; return getInstr ( <STR_LIT> , dl , ResTy , Ext , DAG ) ; } return SDValue ( ) ; }


<s> MVT ResTy = ty ( Op ) ; SDValue InpV = Op . getOperand ( <NUM_LIT> ) ; MVT InpTy = ty ( InpV ) ; assert ( ResTy . getSizeInBits ( ) == InpTy . getSizeInBits ( ) ) ; const SDLoc & dl ( Op ) ; if ( InpTy == <STR_LIT> ) { if ( ResTy == <STR_LIT> ) { SDValue Sc = DAG . getBitcast ( tyScalar ( InpTy ) , InpV ) ; SDValue Ext = DAG . getZExtOrTrunc ( Sc , dl , <STR_LIT> ) ; return getInstr ( <STR_LIT> , dl , ResTy , Ext , DAG ) ; } return SDValue ( ) ; }


<s> if ( All0 ) return DAG . getNode ( <STR_LIT> , dl , VecTy ) ; if ( All1 ) return DAG . getNode ( <STR_LIT> , dl , VecTy ) ; SDValue Rs [ <NUM_LIT> ] ; SDValue Z = getZero ( dl , <STR_LIT> , DAG ) ; unsigned Rep = <NUM_LIT> / VecTy . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { SDValue S = DAG . getConstant ( <NUM_LIT> << i , dl , <STR_LIT> ) ; Rs [ i ] = DAG . getSelect ( dl , <STR_LIT> , Ops [ i / Rep ] , S , Z ) ; } for ( ArrayRef < SDValue > A ( Rs ) ; A . size ( ) != <NUM_LIT> ; A = A . drop_back ( A . size ( ) / <NUM_LIT> ) ) { for ( unsigned i = <NUM_LIT> , e = A . size ( ) / <NUM_LIT> ; i != e ; ++ i ) Rs [ i ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Rs [ <NUM_LIT> * i ] , Rs [ <NUM_LIT> * i + <NUM_LIT> ] ) ; } return getInstr ( <STR_LIT> , dl , VecTy , { Rs [ <NUM_LIT> ] } , DAG ) ; }


<s> uint32_t C = CN -> getZExtValue ( ) ; All0 &= ( C == <NUM_LIT> ) ; All1 &= ( C == <NUM_LIT> ) ; } if ( All0 ) return DAG . getNode ( <STR_LIT> , dl , VecTy ) ; if ( All1 ) return DAG . getNode ( <STR_LIT> , dl , VecTy ) ; SDValue Rs [ <NUM_LIT> ] ; SDValue Z = getZero ( dl , <STR_LIT> , DAG ) ; unsigned Rep = <NUM_LIT> / VecTy . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { SDValue S = DAG . getConstant ( <NUM_LIT> << i , dl , <STR_LIT> ) ; Rs [ i ] = DAG . getSelect ( dl , <STR_LIT> , Ops [ i / Rep ] , S , Z ) ; } for ( ArrayRef < SDValue > A ( Rs ) ; A . size ( ) != <NUM_LIT> ; A = A . drop_back ( A . size ( ) / <NUM_LIT> ) ) { for ( unsigned i = <NUM_LIT> , e = A . size ( ) / <NUM_LIT> ; i != e ; ++ i ) Rs [ i ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Rs [ <NUM_LIT> * i ] , Rs [ <NUM_LIT> * i + <NUM_LIT> ] ) ;


<s> if ( Subtarget . useHVXOps ( ) ) CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT>_HVX ) ; else CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue RetVal ; if ( RVLocs [ i ] . getValVT ( ) == <STR_LIT> ) { auto & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue FR0 = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , <STR_LIT> , Glue ) ; Register PredR = MRI . createVirtualRegister ( & <STR_LIT> ) ; SDValue TPR = DAG . getCopyToReg ( FR0 . getValue ( <NUM_LIT> ) , dl , PredR , FR0 . getValue ( <NUM_LIT> ) , FR0 . getValue ( <NUM_LIT> ) ) ; RetVal = DAG . getCopyFromReg ( TPR . getValue ( <NUM_LIT> ) , dl , PredR , <STR_LIT> ) ; Glue = TPR . getValue ( <NUM_LIT> ) ; Chain = TPR . getValue ( <NUM_LIT> ) ;


<s> bool isVTi1Type = false ; if ( auto * CV = dyn_cast < ConstantVector > ( CPN -> getConstVal ( ) ) ) { if ( cast < VectorType > ( CV -> getType ( ) ) -> getElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { IRBuilder < > IRB ( CV -> getContext ( ) ) ; SmallVector < Constant * , <NUM_LIT> > NewConst ; unsigned VecLen = CV -> getNumOperands ( ) ; assert ( isPowerOf2_32 ( VecLen ) && <STR_LIT> ) ;

for ( unsigned i = <NUM_LIT> ; i < VecLen ; ++ i ) NewConst . push_back ( IRB . getInt8 ( CV -> getOperand ( i ) -> isZeroValue ( ) ) ) ;


<s> unsigned char TF = IsPositionIndependent ? <STR_LIT> : <NUM_LIT> ; unsigned Offset = <NUM_LIT> ; SDValue T ; if ( CPN -> isMachineConstantPoolEntry ( ) ) T = DAG . getTargetConstantPool ( CPN -> getMachineCPVal ( ) , ValTy , Alignment , Offset , TF ) ; else if ( isVTi1Type ) T = DAG . getTargetConstantPool ( CVal , ValTy , Alignment , Offset , TF ) ; else T = DAG . getTargetConstantPool ( CPN -> getConstVal ( ) , ValTy , Alignment , Offset , TF ) ; assert ( cast < ConstantPoolSDNode > ( T ) -> getTargetFlags ( ) == TF && <STR_LIT> ) ; if ( IsPositionIndependent ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , ValTy , T ) ;


<s> SDValue Align = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; ConstantSDNode * AlignConst = dyn_cast < ConstantSDNode > ( Align ) ; assert ( AlignConst && <STR_LIT> ) ; unsigned A = AlignConst -> getSExtValue ( ) ; auto & HFI = * Subtarget . getFrameLowering ( ) ;

if ( A == <NUM_LIT> ) A = HFI . getStackAlign ( ) . value ( ) ;


<s> const TargetRegisterClass * RC = getRegClassFor ( RegVT ) ; Register VReg = MRI . createVirtualRegister ( RC ) ; SDValue Copy = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getValVT ( ) == <STR_LIT> ) { assert ( RegVT . getSizeInBits ( ) <= <NUM_LIT> ) ; SDValue T = DAG . getNode ( <STR_LIT> , dl , RegVT , Copy , DAG . getConstant ( <NUM_LIT> , dl , RegVT ) ) ; Copy = DAG . getSetCC ( dl , <STR_LIT> , T , DAG . getConstant ( <NUM_LIT> , dl , RegVT ) , <STR_LIT> ) ; } else { unsigned RegSize = RegVT . getSizeInBits ( ) ; assert ( RegSize == <NUM_LIT> || RegSize == <NUM_LIT> || Subtarget . isHVXVectorType ( RegVT ) ) ; } InVals . push_back ( Copy ) ; MRI . addLiveIn ( VA . getLocReg ( ) , VReg ) ; HFL . FirstVarArgSavedReg = NextSingleReg ( * RC , VA . getLocReg ( ) ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; unsigned ObjSize = Flags . isByVal ( ) ? Flags . getByValSize ( ) : VA . getLocVT ( ) . getStoreSizeInBits ( ) / <NUM_LIT> ; int Offset = HEXAGON_LRFP_SIZE + VA . getLocMemOffset ( ) ; int FI = MFI . CreateFixedObject ( ObjSize , Offset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; if ( Flags . isByVal ( ) ) { InVals . push_back ( FIN ) ; } else { SDValue L = DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI , <NUM_LIT> ) ) ; InVals . push_back ( L ) ; } } } if ( IsVarArg && Subtarget . isEnvironmentMusl ( ) ) { for ( int i = HFL . FirstVarArgSavedReg ; i < <NUM_LIT> ; i ++ ) MRI . addLiveIn ( <STR_LIT> + i ) ; } if ( IsVarArg && Subtarget . isEnvironmentMusl ( ) ) { HMFI . setFirstNamedArgFrameIndex ( HMFI . getFirstNamedArgFrameIndex ( ) - <NUM_LIT> ) ; HMFI . setLastNamedArgFrameIndex ( - int ( MFI . getNumFixedObjects ( ) ) ) ; int NumVarArgRegs = <NUM_LIT> - HFL . FirstVarArgSavedReg ; bool RequiresPadding = ( NumVarArgRegs & <NUM_LIT> ) ; int RegSaveAreaSizePlusPadding = RequiresPadding ? ( NumVarArgRegs + <NUM_LIT> ) * <NUM_LIT> : NumVarArgRegs * <NUM_LIT> ; if ( RegSaveAreaSizePlusPadding > <NUM_LIT> ) { int RegAreaStart = HEXAGON_LRFP_SIZE + CCInfo . getNextStackOffset ( ) ;

if ( ! ( RegAreaStart % <NUM_LIT> ) ) RegAreaStart = ( RegAreaStart + <NUM_LIT> ) & - <NUM_LIT> ;


<s> case <STR_LIT> : return LowerROTL ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG ) ; case <STR_LIT> : return LowerREADCYCLECOUNTER ( Op , DAG ) ;


<s> void <ISA_LIT>TargetLowering :: LowerOperationWrapper ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const {


<s> if ( VY != <NUM_LIT> ) return SDValue ( ) ; if ( Opc == <STR_LIT> ) { SDValue Op = DAG . getNode ( <STR_LIT> , dl , VTs . VTs [ <NUM_LIT> ] , { X , Y } ) ; SDValue Ov = DAG . getSetCC ( dl , <STR_LIT> , Op , getZero ( dl , ty ( Op ) , DAG ) , <STR_LIT> ) ; return DAG . getMergeValues ( { Op , Ov } , dl ) ; } if ( Opc == <STR_LIT> ) { SDValue Op = DAG . getNode ( <STR_LIT> , dl , VTs . VTs [ <NUM_LIT> ] , { X , Y } ) ; SDValue Ov = DAG . getSetCC ( dl , <STR_LIT> , Op , DAG . getConstant ( - <NUM_LIT> , dl , ty ( Op ) ) , <STR_LIT> ) ; return DAG . getMergeValues ( { Op , Ov } , dl ) ; }


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue DestPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * DestSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;

const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;


<s> SDLoc DL ( Op ) ; return DAG . getMemcpy ( Chain , DL , DestPtr , SrcPtr , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) , Align ( <NUM_LIT> ) , false , false , false , MachinePointerInfo ( DestSV ) , MachinePointerInfo ( SrcSV ) ) ;


<s> auto & FuncInfo = * MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; auto & HFL = * Subtarget . getFrameLowering ( ) ; SDLoc DL ( Op ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; SDValue FIN = Op . getOperand ( <NUM_LIT> ) ; SDValue SavedRegAreaStartFrameIndex = DAG . getFrameIndex ( FuncInfo . getRegSavedAreaStartFrameIndex ( ) , <STR_LIT> ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( HFL . FirstVarArgSavedReg & <NUM_LIT> ) SavedRegAreaStartFrameIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getFrameIndex ( FuncInfo . getRegSavedAreaStartFrameIndex ( ) , <STR_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , SavedRegAreaStartFrameIndex , FIN , MachinePointerInfo ( SV ) ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getFrameIndex ( FuncInfo . getVarArgsFrameIndex ( ) , PtrVT ) , FIN , MachinePointerInfo ( SV , <NUM_LIT> ) ) ;


<s> MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getFrameIndex ( FuncInfo . getVarArgsFrameIndex ( ) , PtrVT ) , FIN , MachinePointerInfo ( SV , <NUM_LIT> ) ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ;


<s> assert ( ElemTy . isScalarInteger ( ) ) ; MVT WideTy = <STR_LIT> ( <STR_LIT> ( <NUM_LIT> * ElemTy . getSizeInBits ( ) ) , OpTy . getVectorNumElements ( ) ) ;

return DAG . getSExtOrTrunc ( DAG . getSelect ( dl , WideTy , PredOp , DAG . getSExtOrTrunc ( Op1 , dl , WideTy ) , DAG . getSExtOrTrunc ( Op2 , dl , WideTy ) ) , dl , OpTy ) ;


<s> } else if ( Opc == <STR_LIT> ) { SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; if ( Cond -> getOpcode ( ) == <STR_LIT> ) { SDValue C0 = Cond . getOperand ( <NUM_LIT> ) , C1 = Cond . getOperand ( <NUM_LIT> ) ; if ( C1 -> getOpcode ( ) == <STR_LIT> ) { SDValue VSel = DCI . DAG . getNode ( <STR_LIT> , dl , ty ( Op ) , C0 , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; return VSel ; } }


<s> if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { if ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { SDValue P = getInstr ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG ) ; SDValue T = DAG . getAnyExtOrTrunc ( P , dl , <STR_LIT> ) ; Results . push_back ( T ) ; }


<s> if ( isHvxOperation ( N , DAG ) ) { ReplaceHvxNodeResults ( N , Results , DAG ) ; if ( ! Results . empty ( ) ) return ; } const SDLoc & dl ( N ) ; switch ( N -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ; case <STR_LIT> : if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { if ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { SDValue P = getInstr ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG ) ; SDValue T = DAG . getAnyExtOrTrunc ( P , dl , <STR_LIT> ) ; Results . push_back ( T ) ; }


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { return AtomicExpansionKind :: LLSC ;


<s> if ( CPN -> isMachineConstantPoolEntry ( ) ) T = DAG . getTargetConstantPool ( CPN -> getMachineCPVal ( ) , ValTy , Align , TF ) ; else T = DAG . getTargetConstantPool ( CPN -> getConstVal ( ) , ValTy , Align , TF ) ; if ( RM == Reloc :: PIC_ ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , ValTy , T ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , ValTy , T ) ;


<s> SDValue T ; if ( CPN -> isMachineConstantPoolEntry ( ) ) T = DAG . getTargetConstantPool ( CPN -> getMachineCPVal ( ) , ValTy , Align , TF ) ; else T = DAG . getTargetConstantPool ( CPN -> getConstVal ( ) , ValTy , Align , TF ) ; if ( RM == Reloc :: PIC_ ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , ValTy , T ) ;


<s> SDValue Align = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; ConstantSDNode * AlignConst = dyn_cast < ConstantSDNode > ( Align ) ; assert ( AlignConst && <STR_LIT> ) ; unsigned A = AlignConst -> getSExtValue ( ) ; auto & HFI = * Subtarget . getFrameLowering ( ) ; if ( A == <NUM_LIT> ) A = HFI . getStackAlignment ( ) ; DEBUG ( { dbgs ( ) << LLVM_FUNCTION_NAME << <STR_LIT> << A << <STR_LIT> ; Size . getNode ( ) -> dump ( & DAG ) ; dbgs ( ) << <STR_LIT> ; } ) ;

SDValue AC = DAG . getConstant ( A , dl , <STR_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerDYNAMIC_STACKALLOC ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; SDValue Align = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; ConstantSDNode * AlignConst = dyn_cast < ConstantSDNode > ( Align ) ; assert ( AlignConst && <STR_LIT> ) ;

unsigned A = AlignConst -> getSExtValue ( ) ;


<s> int64_t Offset = GAN -> getOffset ( ) ; auto & HLOF = * HTM . getObjFileLowering ( ) ; Reloc :: Model RM = HTM . getRelocationModel ( ) ; if ( RM == Reloc :: Static ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , Offset ) ; if ( HLOF . isGlobalInSmallSection ( GV , HTM ) ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA ) ;


<s> EVT VT = Op . getValueType ( ) ; int Idx = cast < JumpTableSDNode > ( Op ) -> getIndex ( ) ; Reloc :: Model RM = HTM . getRelocationModel ( ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerJumpTable ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; int Idx = cast < JumpTableSDNode > ( Op ) -> getIndex ( ) ; Reloc :: Model RM = HTM . getRelocationModel ( ) ; if ( RM == Reloc :: PIC_ ) {

SDValue T = DAG . getTargetJumpTable ( Idx , VT , <STR_LIT> ) ;


<s> SDValue TP = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , PtrVT ) ; Reloc :: Model RM = HTM . getRelocationModel ( ) ; unsigned char TF = ( RM == Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , PtrVT , Offset , TF ) ; SDValue Sym = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA ) ; if ( RM == Reloc :: PIC_ ) { SDValue GOT = LowerGLOBAL_OFFSET_TABLE ( Sym , DAG ) ; Sym = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOT , Sym ) ; } SDValue LoadOffset = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Sym , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , TP , LoadOffset ) ;


<s> unsigned VecWidth = VecTy . getSizeInBits ( ) ; unsigned ValWidth = ValTy . getSizeInBits ( ) ; unsigned ElemWidth = VecTy . getVectorElementType ( ) . getSizeInBits ( ) ; assert ( ( VecWidth % ElemWidth ) == <NUM_LIT> ) ; auto * IdxN = dyn_cast < ConstantSDNode > ( IdxV ) ; if ( ElemWidth == <NUM_LIT> ) { assert ( VecWidth == VecTy . getVectorNumElements ( ) && <STR_LIT> ) ; assert ( VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> ) ; if ( IdxN ) { if ( IdxN -> isNullValue ( ) && ValTy . getSizeInBits ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VecV ) ; } if ( ValWidth == <NUM_LIT> ) { SDValue A0 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { VecV } , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , A0 , IdxV ) ; } unsigned Scale = VecWidth / ValWidth ; assert ( ty ( IdxV ) == <STR_LIT> ) ; SDValue S0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , DAG . getConstant ( <NUM_LIT> * Scale , dl , <STR_LIT> ) ) ; SDValue T0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VecV ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T0 , S0 ) ; while ( Scale > <NUM_LIT> ) { T1 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , T1 ) ; T1 = expandPredicate ( T1 , dl , DAG ) ; Scale /= <NUM_LIT> ;


<s> unsigned ValWidth = ValTy . getSizeInBits ( ) ; unsigned ElemWidth = VecTy . getVectorElementType ( ) . getSizeInBits ( ) ; assert ( ( VecWidth % ElemWidth ) == <NUM_LIT> ) ; auto * IdxN = dyn_cast < ConstantSDNode > ( IdxV ) ; if ( ElemWidth == <NUM_LIT> ) { assert ( VecWidth == VecTy . getVectorNumElements ( ) && <STR_LIT> ) ; assert ( VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> ) ; if ( IdxN ) { if ( IdxN -> isNullValue ( ) && ValTy . getSizeInBits ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VecV ) ; } if ( ValWidth == <NUM_LIT> ) { SDValue A0 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { VecV } , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , A0 , IdxV ) ; } unsigned Scale = VecWidth / ValWidth ; assert ( ty ( IdxV ) == <STR_LIT> ) ; SDValue S0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , DAG . getConstant ( <NUM_LIT> * Scale , dl , <STR_LIT> ) ) ; SDValue T0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VecV ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T0 , S0 ) ; while ( Scale > <NUM_LIT> ) { T1 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , T1 ) ; T1 = expandPredicate ( T1 , dl , DAG ) ; Scale /= <NUM_LIT> ; } return DAG . getNode ( <STR_LIT> , dl , ResTy , T1 ) ; } assert ( VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> ) ; MVT ScalarTy = tyScalar ( VecTy ) ; VecV = DAG . getBitcast ( ScalarTy , VecV ) ; SDValue WidthV = DAG . getConstant ( ValWidth , dl , <STR_LIT> ) ;


<s> EVT VT = LSN -> getMemoryVT ( ) ; if ( ! VT . isSimple ( ) ) return false ; bool IsLegalType = VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || Subtarget . isHVXVectorType ( VT . getSimpleVT ( ) ) ; if ( ! IsLegalType ) return false ; if ( Op -> getOpcode ( ) != <STR_LIT> ) return false ; Base = Op -> getOperand ( <NUM_LIT> ) ; Offset = Op -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Offset . getNode ( ) ) ) return false ; AM = <STR_LIT> ; int32_t V = cast < ConstantSDNode > ( Offset . getNode ( ) ) -> getSExtValue ( ) ; return Subtarget . getInstrInfo ( ) -> isValidAutoIncImm ( VT , V ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : break ; }


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const Module & M = * I . getParent ( ) -> getParent ( ) -> getParent ( ) ; Info . opc = <STR_LIT> ; Type * VecTy = I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ; Info . memVT = <STR_LIT> ( VecTy ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = M . getDataLayout ( ) . getTypeAllocSizeInBits ( VecTy ) / <NUM_LIT> ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; } default : break ; } return false ;


<s> case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return LowerUnalignedLoad ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVECTOR_SHIFT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ;

case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ;


<s> case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return LowerUnalignedLoad ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVECTOR_SHIFT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ;

case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ;


<s> SDLoc dl ( Op ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Cmp = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Cmp ) -> get ( ) ; EVT VT = Op . getValueType ( ) ; EVT LHSVT = LHS . getValueType ( ) ; EVT RHSVT = RHS . getValueType ( ) ; if ( LHSVT == <STR_LIT> ) { assert ( CC == <STR_LIT> || CC == <STR_LIT> || <STR_LIT> ( CC ) || <STR_LIT> ( CC ) ) ; unsigned ExtOpc = <STR_LIT> ( CC ) ? <STR_LIT> : <STR_LIT> ; SDValue LX = DAG . getNode ( ExtOpc , dl , <STR_LIT> , LHS ) ; SDValue RX = DAG . getNode ( ExtOpc , dl , <STR_LIT> , RHS ) ; SDValue SC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LX , RX , Cmp ) ; return SC ; } if ( VT . isVector ( ) ) return Op ; if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && ( RHSVT == <STR_LIT> || RHSVT == <STR_LIT> ) && ( LHSVT == <STR_LIT> || LHSVT == <STR_LIT> ) ) { ConstantSDNode * C = dyn_cast < ConstantSDNode > ( RHS ) ; if ( C && C -> getAPIntValue ( ) . isNegative ( ) ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS , Op . getOperand ( <NUM_LIT> ) ) ; }

if ( isSExtFree ( LHS ) || isSExtFree ( RHS ) ) {


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Cmp ) -> get ( ) ; EVT VT = Op . getValueType ( ) ; EVT LHSVT = LHS . getValueType ( ) ; EVT RHSVT = RHS . getValueType ( ) ; if ( LHSVT == <STR_LIT> ) { assert ( CC == <STR_LIT> || CC == <STR_LIT> || <STR_LIT> ( CC ) || <STR_LIT> ( CC ) ) ; unsigned ExtOpc = <STR_LIT> ( CC ) ? <STR_LIT> : <STR_LIT> ; SDValue LX = DAG . getNode ( ExtOpc , dl , <STR_LIT> , LHS ) ; SDValue RX = DAG . getNode ( ExtOpc , dl , <STR_LIT> , RHS ) ; SDValue SC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LX , RX , Cmp ) ; return SC ;


<s> if ( Subtarget . isHVXVectorType ( SVT , true ) ) return allowsHvxMemoryAccess ( SVT , Alignment , Flags , Fast ) ;

return TargetLoweringBase :: allowsMemoryAccess ( Context , DL , VT , AddrSpace , Alignment , Flags , Fast ) ;


<s> bool <ISA_LIT>TargetLowering :: allowsMemoryAccess ( LLVMContext & Context , const DataLayout & DL , EVT VT , unsigned AddrSpace , unsigned Alignment , MachineMemOperand :: Flags Flags , bool * Fast ) const {


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Alignment , MachineMemOperand :: Flags Flags , bool * Fast ) const { MVT SVT = VT . getSimpleVT ( ) ;

if ( Subtarget . isHVXVectorType ( SVT , true ) ) return allowsHvxMisalignedMemoryAccesses ( SVT , Alignment , Flags , Fast ) ;


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Alignment , MachineMemOperand :: Flags Flags , bool * Fast ) const { MVT SVT = VT . getSimpleVT ( ) ; if ( Subtarget . isHVXVectorType ( SVT , true ) ) return allowsHvxMisalignedMemoryAccesses ( SVT , Alignment , Flags , Fast ) ; if ( Fast ) * Fast = false ; return false ;


<s> ArrayRef < MVT > Tys = Subtarget . getHVXElementTypes ( ) ; if ( llvm :: find ( Tys , ElemTy ) != Tys . end ( ) ) { unsigned HwWidth = <NUM_LIT> * HwLen ; unsigned VecWidth = VT . getSizeInBits ( ) ; if ( VecWidth >= HwWidth / <NUM_LIT> && VecWidth < HwWidth ) return TargetLoweringBase :: TypeWidenVector ; }

if ( ElemTy == <STR_LIT> && VecLen == <NUM_LIT> * HwLen ) return TargetLoweringBase :: TypeSplitVector ;


<s> if ( VecLen == <NUM_LIT> || VT . isScalableVector ( ) ) return TargetLoweringBase :: TypeScalarizeVector ; if ( Subtarget . useHVXOps ( ) ) { unsigned HwLen = Subtarget . getVectorLength ( ) ; ArrayRef < MVT > Tys = Subtarget . getHVXElementTypes ( ) ; if ( llvm :: find ( Tys , ElemTy ) != Tys . end ( ) ) { unsigned HwWidth = <NUM_LIT> * HwLen ; unsigned VecWidth = VT . getSizeInBits ( ) ;

if ( VecWidth >= HwWidth / <NUM_LIT> && VecWidth < HwWidth ) return TargetLoweringBase :: TypeWidenVector ;


<s> switch ( ( <STR_LIT> ) Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> case <STR_LIT> : { Info . opc = <STR_LIT> ; auto & DL = I . getCalledFunction ( ) -> getParent ( ) -> getDataLayout ( ) ; auto & Cont = I . getCalledFunction ( ) -> getParent ( ) -> getContext ( ) ; Type * ElTy = I . getCalledFunction ( ) -> getReturnType ( ) -> getStructElementType ( <NUM_LIT> ) ; Info . memVT = <STR_LIT> ( ElTy ) ; llvm :: Value * BasePtrVal = I . getOperand ( <NUM_LIT> ) ; Info . ptrVal = getUnderLyingObjectForBrevLdIntr ( BasePtrVal ) ; Info . offset = <NUM_LIT> ; Info . align = MaybeAlign ( DL . getABITypeAlignment ( Info . memVT . getTypeForEVT ( Cont ) ) ) ; Info . flags = MachineMemOperand :: MOLoad ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const Module & M = * I . getParent ( ) -> getParent ( ) -> getParent ( ) ; Info . opc = <STR_LIT> ; Type * VecTy = I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ; Info . memVT = <STR_LIT> ( VecTy ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = MaybeAlign ( M . getDataLayout ( ) . getTypeAllocSizeInBits ( VecTy ) / <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; } default : break ; } return false ;


<s> } else { unsigned RegSize = RegVT . getSizeInBits ( ) ; assert ( RegSize == <NUM_LIT> || RegSize == <NUM_LIT> || Subtarget . isHVXVectorType ( RegVT ) ) ; } InVals . push_back ( Copy ) ; MRI . addLiveIn ( VA . getLocReg ( ) , VReg ) ; HFL . FirstVarArgSavedReg = NextSingleReg ( * RC , VA . getLocReg ( ) ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; unsigned ObjSize = Flags . isByVal ( ) ? Flags . getByValSize ( ) : VA . getLocVT ( ) . getStoreSizeInBits ( ) / <NUM_LIT> ; int Offset = HEXAGON_LRFP_SIZE + VA . getLocMemOffset ( ) ; int FI = MFI . CreateFixedObject ( ObjSize , Offset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; if ( Flags . isByVal ( ) ) { InVals . push_back ( FIN ) ; } else { SDValue L = DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI , <NUM_LIT> ) ) ; InVals . push_back ( L ) ; } } } if ( IsVarArg && Subtarget . isEnvironmentMusl ( ) ) { for ( int i = HFL . FirstVarArgSavedReg ; i < <NUM_LIT> ; i ++ ) MRI . addLiveIn ( <STR_LIT> + i ) ; } if ( IsVarArg && Subtarget . isEnvironmentMusl ( ) ) { HMFI . setFirstNamedArgFrameIndex ( HMFI . getFirstNamedArgFrameIndex ( ) - <NUM_LIT> ) ; HMFI . setLastNamedArgFrameIndex ( - int ( MFI . getNumFixedObjects ( ) ) ) ; int NumVarArgRegs = <NUM_LIT> - HFL . FirstVarArgSavedReg ; bool RequiresPadding = ( NumVarArgRegs & <NUM_LIT> ) ; int RegSaveAreaSizePlusPadding = RequiresPadding ? ( NumVarArgRegs + <NUM_LIT> ) * <NUM_LIT> : NumVarArgRegs * <NUM_LIT> ; if ( RegSaveAreaSizePlusPadding > <NUM_LIT> ) { int RegAreaStart = HEXAGON_LRFP_SIZE + CCInfo . getNextStackOffset ( ) ; if ( ! ( RegAreaStart % <NUM_LIT> ) ) RegAreaStart = ( RegAreaStart + <NUM_LIT> ) & - <NUM_LIT> ; int RegSaveAreaFrameIndex = MFI . CreateFixedObject ( RegSaveAreaSizePlusPadding , RegAreaStart , true ) ; HMFI . setRegSavedAreaStartFrameIndex ( RegSaveAreaFrameIndex ) ;

int Offset = RegAreaStart + RegSaveAreaSizePlusPadding ;


<s> case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return LowerLoad ( Op , DAG ) ; case <STR_LIT> : return LowerStore ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerUAddSubO ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerAddSubCarry ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVECTOR_SHIFT ( Op , DAG ) ; case <STR_LIT> : return LowerROTL ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ;

case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ;


<s> if ( ! Results . empty ( ) ) return ; } if ( N -> getOpcode ( ) != <STR_LIT> ) return TargetLowering :: LowerOperationWrapper ( N , Results , DAG ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerUnalignedLoad ( SDValue Op , SelectionDAG & DAG ) const { LoadSDNode * LN = cast < LoadSDNode > ( Op . getNode ( ) ) ; MVT LoadTy = ty ( Op ) ; unsigned NeedAlign = Subtarget . getTypeAlignment ( LoadTy ) ; unsigned HaveAlign = LN -> getAlignment ( ) ; if ( HaveAlign >= NeedAlign ) return Op ; const SDLoc & dl ( Op ) ; const DataLayout & DL = DAG . getDataLayout ( ) ; LLVMContext & Ctx = * DAG . getContext ( ) ; bool DoDefault = false ; if ( ! LN -> isUnindexed ( ) ) DoDefault = true ; if ( ! AlignLoads ) { if ( allowsMemoryAccessForAlignment ( Ctx , DL , LN -> getMemoryVT ( ) , * LN -> getMemOperand ( ) ) ) return Op ; DoDefault = true ; } if ( ! DoDefault && ( <NUM_LIT> * HaveAlign ) == NeedAlign ) { MVT PartTy = HaveAlign <= <NUM_LIT> ? <STR_LIT> ( <NUM_LIT> * HaveAlign ) : <STR_LIT> ( <STR_LIT> , HaveAlign ) ; DoDefault = allowsMemoryAccessForAlignment ( Ctx , DL , PartTy , * LN -> getMemOperand ( ) ) ; } if ( DoDefault ) { std :: pair < SDValue , SDValue > P = expandUnalignedLoad ( LN , DAG ) ; return DAG . getMergeValues ( { P . first , P . second } , dl ) ; } assert ( LoadTy . getSizeInBits ( ) == <NUM_LIT> * NeedAlign ) ; unsigned LoadLen = NeedAlign ; SDValue Base = LN -> getBasePtr ( ) ; SDValue Chain = LN -> getChain ( ) ; auto BO = getBaseAndOffset ( Base ) ; unsigned BaseOpc = BO . first . getOpcode ( ) ; if ( BaseOpc == <STR_LIT> && BO . second % LoadLen == <NUM_LIT> ) return Op ; if ( BO . second % LoadLen != <NUM_LIT> ) { BO . first = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BO . first , DAG . getConstant ( BO . second % LoadLen , dl , <STR_LIT> ) ) ; BO . second -= BO . second % LoadLen ; }

SDValue BaseNoOff = ( BaseOpc != <STR_LIT> ) ? DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BO . first , DAG . getConstant ( NeedAlign , dl , <STR_LIT> ) ) : BO . first ;


<s> return DCI . DAG . getConstant ( - <NUM_LIT> , dl , ty ( Op ) ) ; case <STR_LIT> : return getZero ( dl , ty ( Op ) , DCI . DAG ) ; default : break ; } } else if ( Opc == <STR_LIT> ) { SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; if ( Cond -> getOpcode ( ) == <STR_LIT> ) { SDValue C0 = Cond . getOperand ( <NUM_LIT> ) , C1 = Cond . getOperand ( <NUM_LIT> ) ; if ( C1 -> getOpcode ( ) == <STR_LIT> ) { SDValue VSel = DCI . DAG . getNode ( <STR_LIT> , dl , ty ( Op ) , C0 , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; return VSel ; } } } return SDValue ( ) ;


<s> case <STR_LIT> : if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDValue P = getInstr ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG ) ; SDValue T = DAG . getAnyExtOrTrunc ( P , dl , <STR_LIT> ) ; Results . push_back ( T ) ; } break ;


<s> if ( Fast ) * Fast = false ; return Subtarget . isHVXVectorType ( VT . getSimpleVT ( ) ) ;


<s> } ; if ( Size >= <NUM_LIT> && Aligned ( DstAlign , <NUM_LIT> ) && ( IsMemset || Aligned ( SrcAlign , <NUM_LIT> ) ) ) return <STR_LIT> ; if ( Size >= <NUM_LIT> && Aligned ( DstAlign , <NUM_LIT> ) && ( IsMemset || Aligned ( SrcAlign , <NUM_LIT> ) ) ) return <STR_LIT> ; if ( Size >= <NUM_LIT> && Aligned ( DstAlign , <NUM_LIT> ) && ( IsMemset || Aligned ( SrcAlign , <NUM_LIT> ) ) ) return <STR_LIT> ; return <STR_LIT> ;


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , const AttributeList & FuncAttributes ) const { auto Aligned = [ ] ( unsigned GivenA , unsigned MinA ) -> bool { return ( GivenA % MinA ) == <NUM_LIT> ; } ;

if ( Size >= <NUM_LIT> && Aligned ( DstAlign , <NUM_LIT> ) && ( IsMemset || Aligned ( SrcAlign , <NUM_LIT> ) ) ) return <STR_LIT> ;


<s> <ISA_LIT>CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) , MF . getFunction ( ) . getFunctionType ( ) -> getNumParams ( ) ) ; if ( Subtarget . useHVXOps ( ) ) CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>_HVX ) ; else CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; auto & HMFI = * MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; <STR_LIT> Flags = Ins [ i ] . Flags ; bool ByVal = Flags . isByVal ( ) ; if ( VA . isRegLoc ( ) && ByVal && Flags . getByValSize ( ) <= <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; bool InReg = VA . isRegLoc ( ) && ( ! ByVal || ( ByVal && Flags . getByValSize ( ) > <NUM_LIT> ) ) ; if ( InReg ) { MVT RegVT = VA . getLocVT ( ) ; if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) RegVT = VA . getValVT ( ) ; const TargetRegisterClass * RC = getRegClassFor ( RegVT ) ; Register VReg = MRI . createVirtualRegister ( RC ) ; SDValue Copy = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getValVT ( ) == <STR_LIT> ) { assert ( RegVT . getSizeInBits ( ) <= <NUM_LIT> ) ; SDValue T = DAG . getNode ( <STR_LIT> , dl , RegVT , Copy , DAG . getConstant ( <NUM_LIT> , dl , RegVT ) ) ; Copy = DAG . getSetCC ( dl , <STR_LIT> , T , DAG . getConstant ( <NUM_LIT> , dl , RegVT ) , <STR_LIT> ) ; } else { unsigned RegSize = RegVT . getSizeInBits ( ) ; assert ( RegSize == <NUM_LIT> || RegSize == <NUM_LIT> || Subtarget . isHVXVectorType ( RegVT ) ) ; } InVals . push_back ( Copy ) ; MRI . addLiveIn ( VA . getLocReg ( ) , VReg ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; unsigned ObjSize = Flags . isByVal ( ) ? Flags . getByValSize ( ) : VA . getLocVT ( ) . getStoreSizeInBits ( ) / <NUM_LIT> ; int Offset = HEXAGON_LRFP_SIZE + VA . getLocMemOffset ( ) ;

int FI = MFI . CreateFixedObject ( ObjSize , Offset , true ) ;