<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { assert ( <ISA_LIT>MCInstrInfo :: isBundle ( * MI ) ) ; assert ( <ISA_LIT>MCInstrInfo :: bundleSize ( * MI ) <= HEXAGON_PACKET_SIZE ) ; assert ( <ISA_LIT>MCInstrInfo :: bundleSize ( * MI ) > <NUM_LIT> ) ; HasExtender = false ; for ( auto const & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( * MI ) ) { MCInst const & MCI = * I . getInst ( ) ; if ( <ISA_LIT>MCInstrInfo :: isDuplex ( MII , MCI ) ) { printInstruction ( MCI . getOperand ( <NUM_LIT> ) . getInst ( ) , OS ) ; OS << '\v' ; HasExtender = false ; printInstruction ( MCI . getOperand ( <NUM_LIT> ) . getInst ( ) , OS ) ; } else printInstruction ( & MCI , OS ) ;

HasExtender = <ISA_LIT>MCInstrInfo :: isImmext ( MCI ) ;


<s> void <ISA_LIT>InstPrinter :: printInst ( const <ISA_LIT>MCInst * MI , raw_ostream & O , StringRef Annot ) { const char startPacket = '{' , endPacket = '}' ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { assert ( MI -> isPacketEnd ( ) && <STR_LIT> ) ; if ( MI -> isPacketBegin ( ) ) { <ISA_LIT>MCInst Nop ( <STR_LIT> ) ; StringRef NoAnnot ; Nop . setPacketBegin ( MI -> isPacketBegin ( ) ) ; printInst ( & Nop , O , NoAnnot ) ; } if ( MI -> isPacketEnd ( ) ) O << PacketPadding << endPacket ; printInstruction ( MI , O ) ; } else { if ( MI -> isPacketBegin ( ) ) O << PacketPadding << startPacket << '\n' ; printInstruction ( MI , O ) ; if ( MI -> isPacketEnd ( ) ) O << '\n' << PacketPadding << endPacket ; }


<s> assert ( MO . isExpr ( ) && <STR_LIT> ) ; printOperand ( MI , OpNo , O ) ;


<s> const MCOperand & MO = MI -> getOperand ( OpNo ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; printOperand ( MI , OpNo , O ) ;


<s> void <ISA_LIT>InstPrinter :: printJumpTable ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) const {

const MCOperand & MO = MI -> getOperand ( OpNo ) ;


<s> HasExtender = false ; printInstruction ( MCI . getOperand ( <NUM_LIT> ) . getInst ( ) , OS ) ; } else printInstruction ( & MCI , OS ) ; setExtender ( MCI ) ; OS << <STR_LIT> ; } auto Separator = <STR_LIT> ; if ( <ISA_LIT>MCInstrInfo :: isInnerLoop ( * MI ) ) { OS << Separator ; Separator = <STR_LIT> ; MCInst ME ; ME . setOpcode ( <STR_LIT> ) ; printInstruction ( & ME , OS ) ; } if ( <ISA_LIT>MCInstrInfo :: isOuterLoop ( * MI ) ) { OS << Separator ; Separator = <STR_LIT> ; MCInst ME ; ME . setOpcode ( <STR_LIT> ) ;


<s> printOperand ( MI , OpNo , O ) ; } else { printOperand ( MI , OpNo , O ) ; assert ( <STR_LIT> ) ; } O << ')' ;


<s> Nop . setOpcode ( <STR_LIT> ) ; Nop . setPacketBegin ( MI -> isPacketBegin ( ) ) ; printInst ( & Nop , O , NoAnnot ) ; } if ( MI -> isPacketEnd ( ) ) O << PacketPadding << endPacket ; printInstruction ( MI , O ) ; } else {

if ( MI -> isPacketBegin ( ) ) O << PacketPadding << startPacket << '\n' ;


<s> MCInst const & MCI = * I . getInst ( ) ; if ( <ISA_LIT>MCInstrInfo :: isDuplex ( MII , MCI ) ) { printInstruction ( MCI . getOperand ( <NUM_LIT> ) . getInst ( ) , OS ) ; OS << '\v' ; HasExtender = false ; printInstruction ( MCI . getOperand ( <NUM_LIT> ) . getInst ( ) , OS ) ; } else printInstruction ( & MCI , OS ) ;


<s> StringRef <ISA_LIT>InstPrinter :: getOpcodeName ( unsigned Opcode ) const {


<s> StringRef <ISA_LIT>InstPrinter :: getRegName ( unsigned RegNo ) const { return getRegisterName ( RegNo ) ;


<s> explicit <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) , MII ( MII ) {


<s> void <ISA_LIT>InstPrinter :: printAbsAddrOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) const {


<s> void <ISA_LIT>InstPrinter :: printCallOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) const {


<s> assert ( MI -> getOperand ( OpNo ) . isExpr ( ) && <STR_LIT> ) ; printOperand ( MI , OpNo , O ) ;


<s> if ( HMCI -> isConstExtended ( ) ) O << <STR_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printExtOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) const { const <ISA_LIT>MCInst * HMCI = static_cast < const <ISA_LIT>MCInst * > ( MI ) ; if ( HMCI -> isConstExtended ( ) ) O << <STR_LIT> ; printOperand ( MI , OpNo , O ) ;


<s> O << getRegisterName ( MO0 . getReg ( ) ) << <STR_LIT> << MO1 . getImm ( ) ;


<s> const MCOperand & MO0 = MI -> getOperand ( OpNo ) ; const MCOperand & MO1 = MI -> getOperand ( OpNo + <NUM_LIT> ) ;

O << getRegisterName ( MO0 . getReg ( ) ) << <STR_LIT> << MO1 . getImm ( ) ;


<s> void <ISA_LIT>InstPrinter :: printGlobalOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) const {

assert ( MI -> getOperand ( OpNo ) . isExpr ( ) && <STR_LIT> ) ;


<s> void <ISA_LIT>InstPrinter :: printImmOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) const {


<s> O << * MO . getExpr ( ) ; } else if ( MO . isImm ( ) ) { O << MI -> getOperand ( OpNo ) . getImm ( ) ;


<s> const char startPacket = '{' , endPacket = '}' ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { assert ( MI -> isPacketEnd ( ) && <STR_LIT> ) ; if ( MI -> isPacketStart ( ) ) { <ISA_LIT>MCInst Nop ; StringRef NoAnnot ;


<s> <ISA_LIT>MCInst Nop ; StringRef NoAnnot ; Nop . setOpcode ( <STR_LIT> ) ; Nop . setPacketStart ( MI -> isPacketStart ( ) ) ; printInst ( & Nop , O , NoAnnot ) ; } if ( MI -> isPacketEnd ( ) ) O << PacketPadding << endPacket ; printInstruction ( MI , O ) ;


<s> void <ISA_LIT>InstPrinter :: printJumpTable ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) const {


<s> void <ISA_LIT>InstPrinter :: printJumpTable ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) const { assert ( MI -> getOperand ( OpNo ) . isExpr ( ) && <STR_LIT> ) ; printOperand ( MI , OpNo , O ) ;


<s> void <ISA_LIT>InstPrinter :: printMEMriOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) const { const MCOperand & MO0 = MI -> getOperand ( OpNo ) ;

const MCOperand & MO1 = MI -> getOperand ( OpNo + <NUM_LIT> ) ;


O << getRegisterName ( MO0 . getReg ( ) ) ;


<s> O << - MI -> getOperand ( OpNo ) . getImm ( ) ;


<s> void <ISA_LIT>InstPrinter :: printNOneImmOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) const { O << - <NUM_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) const { const MCOperand & MO = MI -> getOperand ( OpNo ) ; if ( MO . isReg ( ) ) { O << getRegisterName ( MO . getReg ( ) ) ;


<s> void <ISA_LIT>InstPrinter :: printPredicateOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) const {


<s> O << '#' << ( hi ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> ; printOperand ( MI , OpNo , O ) ; O << ')' ;


<s> printSymbol ( MI , OpNo , O , true ) ;


<s> printSymbol ( MI , OpNo , O , false ) ;


<s> void printSymbolLo ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) const { printSymbol ( MI , OpNo , O , false ) ;


<s> O << MI -> getOperand ( OpNo ) . getImm ( ) ;


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return RI ;


<s> if ( isHVXVec ( MI1 ) && isHVXVec ( MI2 ) ) if ( ! isVecUsableNextPacket ( MI1 , MI2 ) ) return true ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = ~ <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = <NUM_LIT> ; break ; } switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SrcReg2 = <NUM_LIT> ; const MachineOperand & Op2 = MI . getOperand ( <NUM_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: canExecuteInBundle ( const MachineInstr & First , const MachineInstr & Second ) const { if ( Second . mayStore ( ) && First . getOpcode ( ) == <STR_LIT> ) { const MachineOperand & Op = Second . getOperand ( <NUM_LIT> ) ; if ( Op . isReg ( ) && Op . isUse ( ) && Op . getReg ( ) == <STR_LIT> ) return true ; } if ( DisableNVSchedule ) return false ; if ( mayBeNewStore ( Second ) ) { const MachineOperand & Stored = Second . getOperand ( Second . getNumOperands ( ) - <NUM_LIT> ) ; if ( ! Stored . isReg ( ) ) return false ; for ( unsigned i = <NUM_LIT> , e = First . getNumOperands ( ) ; i < e ; ++ i ) { const MachineOperand & Op = First . getOperand ( i ) ; if ( Op . isReg ( ) && Op . isDef ( ) && Op . getReg ( ) == Stored . getReg ( ) ) return true ; } }


<s> if ( Second . mayStore ( ) && First . getOpcode ( ) == <STR_LIT> ) { const MachineOperand & Op = Second . getOperand ( <NUM_LIT> ) ; if ( Op . isReg ( ) && Op . isUse ( ) && Op . getReg ( ) == <STR_LIT> ) return true ; } if ( DisableNVSchedule ) return false ; if ( mayBeNewStore ( Second ) ) { const MachineOperand & Stored = Second . getOperand ( Second . getNumOperands ( ) - <NUM_LIT> ) ; if ( ! Stored . isReg ( ) ) return false ; for ( unsigned i = <NUM_LIT> , e = First . getNumOperands ( ) ; i < e ; ++ i ) { const MachineOperand & Op = First . getOperand ( i ) ;

if ( Op . isReg ( ) && Op . isDef ( ) && Op . getReg ( ) == Stored . getReg ( ) ) return true ;


<s> return Opc >= <NUM_LIT> ? <STR_LIT> ( Opc ) : Opc ;


<s> short <ISA_LIT>InstrInfo :: changeAddrMode_io_abs ( short Opc ) const {

return Opc >= <NUM_LIT> ? <STR_LIT> ( Opc ) : Opc ;


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { unsigned LoSrc = HRI . getSubReg ( SrcReg , <STR_LIT> ) ; unsigned HiSrc = HRI . getSubReg ( SrcReg , <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( HiSrc , KillFlag ) . addReg ( LoSrc , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { llvm_unreachable ( <STR_LIT> ) ; return ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { llvm_unreachable ( <STR_LIT> ) ; return ; } dbgs ( ) << <STR_LIT> << printMBBReference ( MBB ) << <STR_LIT> << printReg ( DestReg , & HRI ) << <STR_LIT> << printReg ( SrcReg , & HRI ) << '\n' ;


<s> if ( UseDFAHazardRec ) return new <ISA_LIT>HazardRecognizer ( II , this , Subtarget ) ; return TargetInstrInfo :: CreateTargetPostRAHazardRecognizer ( II , DAG ) ;


<s> } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { TRC = & <STR_LIT> ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) {


<s> std :: pair < unsigned , unsigned > <ISA_LIT>InstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned TF ) const {

return std :: make_pair ( TF & ~ <STR_LIT> , TF & <STR_LIT> ) ;


<s> MachineOperand MO = MI . getOperand ( oper ) ; if ( MO . isReg ( ) ) { if ( ! MO . isDef ( ) ) continue ; const TargetRegisterClass * RC = HRI . getMinimalPhysRegClass ( MO . getReg ( ) ) ; if ( RC == & <STR_LIT> ) { Pred . push_back ( MO ) ; return true ; } continue ; } else if ( MO . isRegMask ( ) ) { for ( unsigned PR : <STR_LIT> ) { if ( ! MI . modifiesRegister ( PR , & HRI ) ) continue ; Pred . push_back ( MO ) ; return true ; } } }


<s> unsigned Opc = CallMI . getOpcode ( ) ;

return Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> for ( MachineBasicBlock * PB : BB -> predecessors ( ) ) { if ( ! Visited . insert ( PB ) . second ) continue ; if ( PB == BB ) continue ;

for ( auto I = PB -> instr_rbegin ( ) , E = PB -> instr_rend ( ) ; I != E ; ++ I ) {


<s> insn < <STR_LIT> ; ++ insn ) { NewMI = BuildMI ( B , I , DL , get ( insn ) ) ;

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << getName ( NewMI -> getOpcode ( ) ) << <STR_LIT> << NewMI -> getDesc ( ) . getSchedClass ( ) ) ;


<s> MachineBasicBlock :: iterator I = B . begin ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; MachineInstr * NewMI ; for ( unsigned insn = TargetOpcode :: GENERIC_OP_END + <NUM_LIT> ; insn < <STR_LIT> ; ++ insn ) {

NewMI = BuildMI ( B , I , DL , get ( insn ) ) ;


<s> unsigned <ISA_LIT>InstrInfo :: getAddrMode ( const MachineInstr & MI ) const { const uint64_t F = MI . getDesc ( ) . TSFlags ;


<s> const uint64_t F = MI . getDesc ( ) . TSFlags ;


<s> } else { const MachineOperand & OffsetOp = MI . getOperand ( OffsetPos ) ; if ( ! OffsetOp . isImm ( ) ) return nullptr ; Offset = OffsetOp . getImm ( ) ; } const MachineOperand & BaseOp = MI . getOperand ( BasePos ) ;

if ( BaseOp . getSubReg ( ) != <NUM_LIT> ) return nullptr ;


<s> } else return false ; if ( isPredicated ( MI ) ) { BasePos ++ ; OffsetPos ++ ; } if ( isPostIncrement ( MI ) ) { BasePos ++ ; OffsetPos ++ ; } if ( ! MI . getOperand ( BasePos ) . isReg ( ) || ! MI . getOperand ( OffsetPos ) . isImm ( ) ) return false ; return true ;


<s> MachineBasicBlock :: instr_iterator I = MBB . instr_end ( ) ; if ( I == MBB . instr_begin ( ) ) return Jumpers ; do { -- I ; if ( I -> isEHLabel ( ) ) return Jumpers ; } while ( I != MBB . instr_begin ( ) ) ; I = MBB . instr_end ( ) ; -- I ; while ( I -> isDebugInstr ( ) ) { if ( I == MBB . instr_begin ( ) ) return Jumpers ; -- I ;


<s> unsigned DstReg , SrcReg , Src1Reg , Src2Reg ; switch ( MI . getOpcode ( ) ) { default : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Src1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Src2Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( DstReg ) && ( <STR_LIT> == DstReg || <STR_LIT> == DstReg ) && isIntRegForSubInst ( Src1Reg ) && isIntRegForSubInst ( Src2Reg ) ) return <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( DstReg ) && ( <STR_LIT> == DstReg || <STR_LIT> == DstReg ) && isIntRegForSubInst ( SrcReg ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && ( ( isUInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) || ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == - <NUM_LIT> ) ) ) return <STR_LIT> ; break ; case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isIntRegForSubInst ( DstReg ) && isIntRegForSubInst ( SrcReg ) ) return <STR_LIT> ; break ; case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isIntRegForSubInst ( DstReg ) ) return <STR_LIT> ; break ; case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Src1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( DstReg ) && ( <STR_LIT> == DstReg || <STR_LIT> == DstReg ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && isIntRegForSubInst ( Src1Reg ) && ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) return <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Src1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Src2Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( DstReg ) && ( <STR_LIT> == DstReg || <STR_LIT> == DstReg ) && isIntRegForSubInst ( Src1Reg ) && isIntRegForSubInst ( Src2Reg ) ) return <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( DstReg ) && ( <STR_LIT> == DstReg || <STR_LIT> == DstReg ) && isIntRegForSubInst ( SrcReg ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && ( ( isUInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) || ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == - <NUM_LIT> ) ) ) return <STR_LIT> ; break ; case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isIntRegForSubInst ( DstReg ) && isIntRegForSubInst ( SrcReg ) ) return <STR_LIT> ; break ; case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isIntRegForSubInst ( DstReg ) ) return <STR_LIT> ; break ; case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> if ( ! GB . readsRegister ( DestReg ) ) return - <NUM_LIT> ; if ( DestReg != <STR_LIT> && DestReg != <STR_LIT> ) return - <NUM_LIT> ; const MachineOperand & CmpOp = GA . getOperand ( <NUM_LIT> ) ; if ( ! CmpOp . isImm ( ) ) return - <NUM_LIT> ;


<s> enum <STR_LIT> inPredSense ; inPredSense = invertPredicate ? <STR_LIT> : <STR_LIT> ; int CondOpcode = <STR_LIT> ( Opc , inPredSense ) ;

if ( CondOpcode >= <NUM_LIT> ) return CondOpcode ;


<s> int NVOpcode = <STR_LIT> ( MI . getOpcode ( ) ) ; if ( NVOpcode >= <NUM_LIT> ) return NVOpcode ; switch ( MI . getOpcode ( ) ) { default : report_fatal_error ( std :: string ( <STR_LIT> ) + std :: to_string ( MI . getOpcode ( ) ) ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> int <ISA_LIT>InstrInfo :: getDotNewOp ( const MachineInstr & MI ) const { int NVOpcode = <STR_LIT> ( MI . getOpcode ( ) ) ; if ( NVOpcode >= <NUM_LIT> ) return NVOpcode ; switch ( MI . getOpcode ( ) ) { default :

report_fatal_error ( std :: string ( <STR_LIT> ) + std :: to_string ( MI . getOpcode ( ) ) ) ;


<s> if ( NextIt == B . instr_end ( ) ) { for ( const MachineBasicBlock * SB : B . successors ( ) ) { if ( ! B . isLayoutSuccessor ( SB ) ) continue ; Taken = getEdgeProbability ( Src , SB ) < OneHalf ; break ; } } else { assert ( NextIt -> isUnconditionalBranch ( ) ) ; const MachineBasicBlock * BT = nullptr ; for ( const MachineOperand & Op : NextIt -> operands ( ) ) { if ( ! Op . isMBB ( ) ) continue ; BT = Op . getMBB ( ) ; break ; } Taken = BT && getEdgeProbability ( Src , BT ) < OneHalf ; } } } switch ( MI . getOpcode ( ) ) { case <STR_LIT> : return Taken ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return Taken ? <STR_LIT> : <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> return getDotNewPredJumpOp ( MI , MBPI ) ; } int NewOpcode = <STR_LIT> ( MI . getOpcode ( ) ) ; if ( NewOpcode >= <NUM_LIT> ) return NewOpcode ;


<s> unsigned Length = <NUM_LIT> ; for ( ; * Str ; ++ Str ) { if ( * Str == '\n' || strncmp ( Str , MAI . getSeparatorString ( ) , strlen ( MAI . getSeparatorString ( ) ) ) == <NUM_LIT> ) atInsnStart = true ; if ( atInsnStart && ! std :: isspace ( static_cast < unsigned char > ( * Str ) ) ) { Length += MAI . getMaxInstLength ( ) ; atInsnStart = false ;


<s> unsigned <ISA_LIT>InstrInfo :: getInstrLatency ( const InstrItineraryData * ItinData , const MachineInstr & MI , unsigned * PredCost ) const {

return getInstrTimingClassLatency ( ItinData , MI ) ;


<s> unsigned <ISA_LIT>InstrInfo :: getInstrTimingClassLatency ( const InstrItineraryData * ItinData , const MachineInstr & MI ) const { if ( ! ItinData ) return getInstrLatency ( ItinData , MI ) ; if ( MI . isTransient ( ) ) return <NUM_LIT> ;

return ItinData -> getStageLatency ( MI . getDesc ( ) . getSchedClass ( ) ) ;


<s> int <ISA_LIT>InstrInfo :: getMaxValue ( const MachineInstr & MI ) const { const uint64_t F = MI . getDesc ( ) . TSFlags ; unsigned isSigned = ( F >> <STR_LIT> ) & <STR_LIT> ; unsigned bits = ( F >> <STR_LIT> ) & <STR_LIT> ;

if ( isSigned ) return ~ ( - <NUM_LIT> << ( bits - <NUM_LIT> ) ) ;


<s> unsigned isSigned = ( F >> <STR_LIT> ) & <STR_LIT> ; unsigned bits = ( F >> <STR_LIT> ) & <STR_LIT> ;


<s> unsigned Size = getMemAccessSizeInBytes ( MemAccessSize ( S ) ) ; if ( Size != <NUM_LIT> ) return Size ; const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; switch ( S ) { case <STR_LIT> : return HRI . getSpillSize ( <STR_LIT> ) ; default :


<s> const uint64_t F = MI . getDesc ( ) . TSFlags ; unsigned S = ( F >> MemAccessSizePos ) & MemAccesSizeMask ; unsigned Size = getMemAccessSizeInBytes ( MemAccessSize ( S ) ) ; if ( Size != <NUM_LIT> ) return Size ; const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; switch ( S ) { case <STR_LIT> : return HRI . getSpillSize ( <STR_LIT> ) ; default :


<s> assert ( ( ! BaseOp || BaseOp -> isReg ( ) ) && <STR_LIT> <STR_LIT> ) ;


<s> const uint64_t F = MI . getDesc ( ) . TSFlags ; unsigned isSigned = ( F >> <STR_LIT> ) & <STR_LIT> ; unsigned bits = ( F >> <STR_LIT> ) & <STR_LIT> ;

if ( isSigned ) return - <NUM_LIT> << ( bits - <NUM_LIT> ) ;


<s> short <ISA_LIT>InstrInfo :: getNonExtOpcode ( const MachineInstr & MI ) const { short NonExtOpcode = <STR_LIT> ( MI . getOpcode ( ) ) ; if ( NonExtOpcode >= <NUM_LIT> ) return NonExtOpcode ; if ( MI . getDesc ( ) . mayLoad ( ) || MI . getDesc ( ) . mayStore ( ) ) { switch ( getAddrMode ( MI ) ) { case <STR_LIT> : return <STR_LIT> ( MI . getOpcode ( ) ) ; case <STR_LIT> : return <STR_LIT> ( MI . getOpcode ( ) ) ; case <STR_LIT> : return <STR_LIT> ( MI . getOpcode ( ) ) ; default : return - <NUM_LIT> ; } } return - <NUM_LIT> ;


<s> const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; const MachineOperand & DefMO = DefMI . getOperand ( DefIdx ) ; if ( DefMO . isReg ( ) && HRI . isPhysicalRegister ( DefMO . getReg ( ) ) ) { if ( DefMO . isImplicit ( ) ) { for ( MCSuperRegIterator SR ( DefMO . getReg ( ) , & HRI ) ; SR . isValid ( ) ; ++ SR ) { int Idx = DefMI . findRegisterDefOperandIdx ( * SR , false , false , & HRI ) ; if ( Idx != - <NUM_LIT> ) { DefIdx = Idx ; break ; } } } const MachineOperand & UseMO = UseMI . getOperand ( UseIdx ) ; if ( UseMO . isImplicit ( ) ) {

for ( MCSuperRegIterator SR ( UseMO . getReg ( ) , & HRI ) ; SR . isValid ( ) ; ++ SR ) {


<s> if ( Cond . empty ( ) ) return false ; assert ( Cond . size ( ) == <NUM_LIT> ) ; if ( isNewValueJump ( Cond [ <NUM_LIT> ] . getImm ( ) ) || Cond [ <NUM_LIT> ] . isMBB ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } PredReg = Cond [ <NUM_LIT> ] . getReg ( ) ; PredRegPos = <NUM_LIT> ; PredRegFlags = <NUM_LIT> ; if ( Cond [ <NUM_LIT> ] . isImplicit ( ) ) PredRegFlags = RegState :: Implicit ; if ( Cond [ <NUM_LIT> ] . isUndef ( ) ) PredRegFlags |= RegState :: Undef ; return true ;


<s> short <ISA_LIT>InstrInfo :: getPseudoInstrPair ( const MachineInstr & MI ) const {

return <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> ) ;


<s> return <STR_LIT> ( MI . getOpcode ( ) ) ;


<s> const MachineBasicBlock & MBB = * MI . getParent ( ) ; const MachineFunction * MF = MBB . getParent ( ) ; const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; unsigned NumDefs = <NUM_LIT> ; for ( ; MI . getOperand ( NumDefs ) . isReg ( ) && MI . getOperand ( NumDefs ) . isDef ( ) ; ++ NumDefs ) assert ( NumDefs != MI . getNumOperands ( ) - <NUM_LIT> && <STR_LIT> ) ; assert ( MI . getOperand ( NumDefs ) . isSymbol ( ) && <STR_LIT> ) ; const char * AsmStr = MI . getOperand ( NumDefs ) . getSymbolName ( ) ;

Size = getInlineAsmLength ( AsmStr , * MAI ) ;


<s> const uint64_t F = MI . getDesc ( ) . TSFlags ;


<s> const InstrItineraryData & II = * Subtarget . getInstrItineraryData ( ) ; const InstrStage & IS = * II . beginStage ( MI . getDesc ( ) . getSchedClass ( ) ) ; return IS . getUnits ( ) ;


<s> unsigned <ISA_LIT>InstrInfo :: getUnits ( const MachineInstr & MI ) const { const InstrItineraryData & II = * Subtarget . getInstrItineraryData ( ) ;

const InstrStage & IS = * II . beginStage ( MI . getDesc ( ) . getSchedClass ( ) ) ;


<s> if ( MI . isBundle ( ) ) { const MachineBasicBlock * MBB = MI . getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI . getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( TargetInstrInfo :: hasLoadFromStackSlot ( * MII , Accesses ) ) return true ; return false ; } return TargetInstrInfo :: hasLoadFromStackSlot ( MI , Accesses ) ;


<s> bool <ISA_LIT>InstrInfo :: hasLoadFromStackSlot ( const MachineInstr & MI , SmallVectorImpl < const MachineMemOperand * > & Accesses ) const { if ( MI . isBundle ( ) ) { const MachineBasicBlock * MBB = MI . getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI . getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( TargetInstrInfo :: hasLoadFromStackSlot ( * MII , Accesses ) ) return true ; return false ; }

return TargetInstrInfo :: hasLoadFromStackSlot ( MI , Accesses ) ;


<s> case <STR_LIT> : NonExtOpcode = <STR_LIT> ( MI . getOpcode ( ) ) ; break ; case <STR_LIT> : NonExtOpcode = <STR_LIT> ( MI . getOpcode ( ) ) ; break ; case <STR_LIT> : NonExtOpcode = <STR_LIT> ( MI . getOpcode ( ) ) ; break ; default : return false ;


<s> return <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> ) >= <NUM_LIT> ;


<s> MachineBasicBlock :: const_instr_iterator MII = MI . getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( TargetInstrInfo :: hasStoreToStackSlot ( * MII , Accesses ) ) return true ; return false ; }

return TargetInstrInfo :: hasStoreToStackSlot ( MI , Accesses ) ;


<s> bool <ISA_LIT>InstrInfo :: hasStoreToStackSlot ( const MachineInstr & MI , SmallVectorImpl < const MachineMemOperand * > & Accesses ) const { if ( MI . isBundle ( ) ) { const MachineBasicBlock * MBB = MI . getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI . getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( TargetInstrInfo :: hasStoreToStackSlot ( * MII , Accesses ) ) return true ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & ST ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , Subtarget ( ST ) {


<s> assert ( ( isExtendable ( MI ) || isConstExtended ( MI ) ) && <STR_LIT> ) ; short ExtOpNum = getCExtOpNum ( MI ) ; MachineOperand & MO = MI . getOperand ( ExtOpNum ) ;

assert ( ( MO . isMBB ( ) || MO . isImm ( ) ) && <STR_LIT> ) ;


<s> MachineOperand & MO = MI . getOperand ( ExtOpNum ) ; assert ( ( MO . isMBB ( ) || MO . isImm ( ) ) && <STR_LIT> ) ; MO . addTargetFlag ( <STR_LIT> ) ;


<s> assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Flags1 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( MBB ) ; ) ; if ( Cond [ <NUM_LIT> ] . isReg ( ) ) { unsigned Flags2 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags2 ) . addMBB ( TBB ) ; } else if ( Cond [ <NUM_LIT> ] . isImm ( ) ) { BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addMBB ( TBB ) ; } else llvm_unreachable ( <STR_LIT> ) ; } else { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; const MachineOperand & RO = Cond [ <NUM_LIT> ] ; unsigned Flags = getUndefRegState ( RO . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( RO . getReg ( ) , Flags ) . addMBB ( TBB ) ; } return <NUM_LIT> ; } assert ( ( ! Cond . empty ( ) ) && <STR_LIT> ) ; assert ( ( ! isNewValueJump ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) && <STR_LIT> ) ; if ( isEndLoopN ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { int EndLoopOp = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( Cond [ <NUM_LIT> ] . isMBB ( ) ) ;

SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ;


<s> bool <ISA_LIT>InstrInfo :: invertAndChangeJumpTarget ( MachineInstr & MI , MachineBasicBlock * NewTarget ) const { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * NewTarget ) ; MI . dump ( ) ; ) ; assert ( MI . isBranch ( ) ) ; unsigned NewOpcode = getInvertedPredicatedOpcode ( MI . getOpcode ( ) ) ; int TargetPos = MI . getNumOperands ( ) - <NUM_LIT> ; while ( ( TargetPos > - <NUM_LIT> ) && ! MI . getOperand ( TargetPos ) . isMBB ( ) ) -- TargetPos ; assert ( ( TargetPos >= <NUM_LIT> ) && MI . getOperand ( TargetPos ) . isMBB ( ) ) ; MI . getOperand ( TargetPos ) . setMBB ( NewTarget ) ; if ( EnableBranchPrediction && isPredicatedNew ( MI ) ) { NewOpcode = reversePrediction ( NewOpcode ) ; } MI . setDesc ( get ( NewOpcode ) ) ; return true ;


<s> return ( getAddrMode ( MI ) == <STR_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: isAccumulator ( const MachineInstr & MI ) const { const uint64_t F = MI . getDesc ( ) . TSFlags ;

return ( ( F >> <STR_LIT> ) & <STR_LIT> ) ;


<s> return true ; } const uint64_t F = MI . getDesc ( ) . TSFlags ; unsigned addrMode = ( ( F >> <STR_LIT> ) & <STR_LIT> ) ;

return ( addrMode == <STR_LIT> || addrMode == <STR_LIT> || addrMode == <STR_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: isBaseImmOffset ( const MachineInstr & MI ) const {

return getAddrMode ( MI ) == <STR_LIT> ;


<s> return ! isTC1 ( MI ) && ! isTC2Early ( MI ) && ! MI . getDesc ( ) . mayLoad ( ) && ! MI . getDesc ( ) . mayStore ( ) && MI . getDesc ( ) . getOpcode ( ) != <STR_LIT> && MI . getDesc ( ) . getOpcode ( ) != <STR_LIT> && ! isMemOp ( MI ) && ! MI . isBranch ( ) && ! MI . isReturn ( ) && ! MI . isCall ( ) ;


<s> bool <ISA_LIT>InstrInfo :: isComplex ( const MachineInstr & MI ) const { return ! isTC1 ( MI ) && ! isTC2Early ( MI ) && ! MI . getDesc ( ) . mayLoad ( ) && ! MI . getDesc ( ) . mayStore ( ) && MI . getDesc ( ) . getOpcode ( ) != <STR_LIT> && MI . getDesc ( ) . getOpcode ( ) != <STR_LIT> && ! isMemOp ( MI ) && ! MI . isBranch ( ) && ! MI . isReturn ( ) && ! MI . isCall ( ) ;


<s> bool <ISA_LIT>InstrInfo :: isCompoundBranchInstr ( const MachineInstr & MI ) const { return getType ( MI ) == <STR_LIT> && MI . isBranch ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return false ;


<s> bool <ISA_LIT>InstrInfo :: isDotCurInst ( const MachineInstr & MI ) const {


<s> bool <ISA_LIT>InstrInfo :: isDotNewInst ( const MachineInstr & MI ) const { if ( isNewValueInst ( MI ) || ( isPredicated ( MI ) && isPredicatedNew ( MI ) ) ) return true ; return false ;


<s> <STR_LIT> MIbG = getDuplexCandidateGroup ( MIb ) ; return ( isDuplexPairMatch ( MIaG , MIbG ) || isDuplexPairMatch ( MIbG , MIaG ) ) ;


<s> <STR_LIT> MIbG = getDuplexCandidateGroup ( MIb ) ;

return ( isDuplexPairMatch ( MIaG , MIbG ) || isDuplexPairMatch ( MIbG , MIaG ) ) ;


<s> if ( MI . mayLoad ( ) || MI . mayStore ( ) || MI . isCompare ( ) ) return true ; unsigned SchedClass = MI . getDesc ( ) . getSchedClass ( ) ; return is_TC4x ( SchedClass ) || is_TC3x ( SchedClass ) ;


<s> const uint64_t F = MI . getDesc ( ) . TSFlags ;

if ( ( F >> <STR_LIT> ) & <STR_LIT> ) return true ;


<s> const uint64_t F = MI . getDesc ( ) . TSFlags ; if ( ( F >> <STR_LIT> ) & <STR_LIT> ) return true ;

for ( const MachineOperand & MO : MI . operands ( ) ) if ( MO . getTargetFlags ( ) & <STR_LIT> ) return true ;


<s> bool <ISA_LIT>InstrInfo :: isFloat ( const MachineInstr & MI ) const {


<s> if ( ! I . mayLoad ( ) && ! I . mayStore ( ) ) return false ; return J . isIndirectBranch ( ) || isIndirectCall ( J ) || isIndirectL4Return ( J ) ;


<s> if ( ! isHVXVec ( I ) ) return false ; if ( ! I . mayLoad ( ) && ! I . mayStore ( ) ) return false ; return J . isIndirectBranch ( ) || isIndirectCall ( J ) || isIndirectL4Return ( J ) ;


<s> bool <ISA_LIT>InstrInfo :: isHVXVec ( const MachineInstr & MI ) const { const uint64_t V = getType ( MI ) ;

return <STR_LIT> <= V && V <= <STR_LIT> ;


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>InstrInfo :: isLateInstrFeedsEarlyInstr ( const MachineInstr & LRMI , const MachineInstr & ESMI ) const { bool isLate = isLateResultInstr ( LRMI ) ; bool isEarly = isEarlySourceInstr ( ESMI ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( isLate ? <STR_LIT> : <STR_LIT> ) ) ; LLVM_DEBUG ( LRMI . dump ( ) ) ;

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( isEarly ? <STR_LIT> : <STR_LIT> ) ) ;


<s> case TargetOpcode :: INSERT_SUBREG : case TargetOpcode :: SUBREG_TO_REG : case TargetOpcode :: REG_SEQUENCE : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: COPY : case TargetOpcode :: INLINEASM : case TargetOpcode :: PHI : return false ;


<s> bool <ISA_LIT>InstrInfo :: isLateResultInstr ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case TargetOpcode :: EXTRACT_SUBREG : case TargetOpcode :: INSERT_SUBREG : case TargetOpcode :: SUBREG_TO_REG : case TargetOpcode :: REG_SEQUENCE : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: COPY : case TargetOpcode :: INLINEASM : case TargetOpcode :: PHI : return false ; default : break ;


<s> bool <ISA_LIT>InstrInfo :: isLateSourceInstr ( const MachineInstr & MI ) const { return getType ( MI ) == <STR_LIT> ;


<s> return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand OpFI = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpFI . isFI ( ) ) return <NUM_LIT> ; const MachineOperand OpOff = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } }


<s> const MachineOperand OpFI = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpFI . isFI ( ) ) return <NUM_LIT> ; const MachineOperand OpOff = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand OpFI = MI . getOperand ( <NUM_LIT> ) ;


<s> return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>InstrInfo :: isNewValueInst ( const MachineInstr & MI ) const {

return isNewValueJump ( MI ) || isNewValueStore ( MI ) ;


<s> return isNewValue ( MI ) && MI . isBranch ( ) ;


<s> const uint64_t F = MI . getDesc ( ) . TSFlags ;


<s> return ( ( F >> <STR_LIT> ) & <STR_LIT> ) == OperandNum ;


<s> bool <ISA_LIT>InstrInfo :: isOperandExtended ( const MachineInstr & MI , unsigned OperandNum ) const { const uint64_t F = MI . getDesc ( ) . TSFlags ;

return ( ( F >> <STR_LIT> ) & <STR_LIT> ) == OperandNum ;


<s> return getAddrMode ( MI ) == <STR_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: isSaveCalleeSavedRegsCall ( const MachineInstr & MI ) const { return MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ;


<s> return MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ;


<s> if ( MI . isDebugInstr ( ) ) return false ; if ( MI . isCall ( ) ) { if ( doesNotReturn ( MI ) ) return true ;

for ( auto I : MBB -> successors ( ) ) if ( I -> isEHPad ( ) ) return true ;


<s> bool <ISA_LIT>InstrInfo :: isSolo ( const MachineInstr & MI ) const { const uint64_t F = MI . getDesc ( ) . TSFlags ;


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : return true ;


<s> } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand & OpFI = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpFI . isFI ( ) ) return <NUM_LIT> ; const MachineOperand & OpOff = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> bool <ISA_LIT>InstrInfo :: isTailCall ( const MachineInstr & MI ) const {

if ( ! MI . isBranch ( ) ) return false ;


<s> bool <ISA_LIT>InstrInfo :: isTC1 ( const MachineInstr & MI ) const { unsigned SchedClass = MI . getDesc ( ) . getSchedClass ( ) ;


<s> bool <ISA_LIT>InstrInfo :: isTC1 ( const MachineInstr & MI ) const {

unsigned SchedClass = MI . getDesc ( ) . getSchedClass ( ) ;


<s> unsigned SchedClass = MI . getDesc ( ) . getSchedClass ( ) ;


if ( mayBeNewStore ( MI2 ) ) if ( MI2 . getOpcode ( ) == <STR_LIT> ) if ( MI1 . getOperand ( <NUM_LIT> ) . isReg ( ) && MI2 . getOperand ( <NUM_LIT> ) . isReg ( ) && MI1 . getOperand ( <NUM_LIT> ) . getReg ( ) == MI2 . getOperand ( <NUM_LIT> ) . getReg ( ) ) return true ;


<s> unsigned DstReg = MI1 . getOperand ( <NUM_LIT> ) . getReg ( ) ; int N = MI2 . getNumOperands ( ) ; for ( int I = <NUM_LIT> ; I < N ; I ++ ) if ( MI2 . getOperand ( I ) . isReg ( ) && DstReg == MI2 . getOperand ( I ) . getReg ( ) ) return true ; } if ( mayBeNewStore ( MI2 ) ) if ( MI2 . getOpcode ( ) == <STR_LIT> ) if ( MI1 . getOperand ( <NUM_LIT> ) . isReg ( ) && MI2 . getOperand ( <NUM_LIT> ) . isReg ( ) && MI1 . getOperand ( <NUM_LIT> ) . getReg ( ) == MI2 . getOperand ( <NUM_LIT> ) . getReg ( ) ) return true ; return false ;


<s> case <STR_LIT> : return isInt < <NUM_LIT> > ( Count ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( Count ) ; default : break ; }


<s> return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; } if ( Extend ) return true ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMW_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMW_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; } llvm_unreachable ( <STR_LIT> <STR_LIT> ) ;


<s> case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>InstrInfo :: isVecAcc ( const MachineInstr & MI ) const {

return isHVXVec ( MI ) && isAccumulator ( MI ) ;


<s> const uint64_t F = get ( MI . getOpcode ( ) ) . TSFlags ;

const uint64_t V = ( ( F >> <STR_LIT> ) & <STR_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: isVecALU ( const MachineInstr & MI ) const { const uint64_t F = get ( MI . getOpcode ( ) ) . TSFlags ;


<s> if ( EnableACCForwarding && isVecAcc ( ProdMI ) && isVecAcc ( ConsMI ) ) return true ; if ( EnableALUForwarding && ( isVecALU ( ConsMI ) || isLateSourceInstr ( ConsMI ) ) ) return true ;

if ( mayBeNewStore ( ConsMI ) ) return true ;


<s> if ( EnableACCForwarding && isVecAcc ( ProdMI ) && isVecAcc ( ConsMI ) ) return true ;

if ( EnableALUForwarding && ( isVecALU ( ConsMI ) || isLateSourceInstr ( ConsMI ) ) ) return true ;


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( HasAlloca ) SlotAlign = HFI . getStackAlignment ( ) ; unsigned Opc = SlotAlign < RegAlign ? <STR_LIT> : <STR_LIT> ; MachineMemOperand * MMOA = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , SlotAlign ) ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMOA ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( HasAlloca ) SlotAlign = HFI . getStackAlignment ( ) ; unsigned Opc = SlotAlign < RegAlign ? <STR_LIT> : <STR_LIT> ; MachineMemOperand * MMOA = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , SlotAlign ) ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMOA ) ; } else { llvm_unreachable ( <STR_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: mayBeCurLoad ( const MachineInstr & MI ) const { const uint64_t F = MI . getDesc ( ) . TSFlags ; return ( ( F >> <STR_LIT> ) & <STR_LIT> ) && Subtarget . hasV60Ops ( ) ;


<s> bool <ISA_LIT>InstrInfo :: mayBeNewStore ( const MachineInstr & MI ) const { if ( MI . mayStore ( ) && ! Subtarget . useNewValueStores ( ) ) return false ; const uint64_t F = MI . getDesc ( ) . TSFlags ; return ( F >> <STR_LIT> ) & <STR_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: mayBeNewStore ( const MachineInstr & MI ) const { if ( MI . mayStore ( ) && ! Subtarget . useNewValueStores ( ) ) return false ; const uint64_t F = MI . getDesc ( ) . TSFlags ;


<s> return nonDbgMICount ( ++ MII , getBundleEnd ( BundleHead . getInstrIterator ( ) ) ) ;


<s> auto MII = BundleHead . getInstrIterator ( ) ; return nonDbgMICount ( ++ MII , getBundleEnd ( BundleHead . getInstrIterator ( ) ) ) ;


<s> if ( ! MIB -> isDebugInstr ( ) ) ++ Count ; } return Count ;


if ( ! MIB -> isDebugInstr ( ) ) ++ Count ;


<s> unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; if ( MO . isUse ( ) ) Uses . push_back ( MO . getReg ( ) ) ; if ( MO . isDef ( ) ) Defs . push_back ( MO . getReg ( ) ) ; }


<s> unsigned PredOpc = getCondOpcode ( Opc , invertJump ) ; MachineInstrBuilder T = BuildMI ( B , MI , DL , get ( PredOpc ) ) ; unsigned NOp = <NUM_LIT> , NumOps = MI . getNumOperands ( ) ; while ( NOp < NumOps ) { MachineOperand & Op = MI . getOperand ( NOp ) ; if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . isImplicit ( ) ) break ; T . add ( Op ) ; NOp ++ ; } unsigned PredReg , PredRegPos , PredRegFlags ; bool GotPredReg = getPredReg ( Cond , PredReg , PredRegPos , PredRegFlags ) ; ( void ) GotPredReg ; assert ( GotPredReg ) ; T . addReg ( PredReg , PredRegFlags ) ; while ( NOp < NumOps ) T . add ( MI . getOperand ( NOp ++ ) ) ; MI . setDesc ( get ( PredOpc ) ) ; while ( unsigned n = MI . getNumOperands ( ) ) MI . RemoveOperand ( n - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , n = T -> getNumOperands ( ) ; i < n ; ++ i ) MI . addOperand ( T -> getOperand ( i ) ) ; MachineBasicBlock :: instr_iterator TI = T -> getIterator ( ) ; B . erase ( TI ) ; MachineRegisterInfo & MRI = B . getParent ( ) -> getRegInfo ( ) ; MRI . clearKillFlags ( PredReg ) ; return true ;


<s> return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: PredOpcodeHasJMP_c ( unsigned Opcode ) const {

return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> MachineBasicBlock :: const_instr_iterator MIE = MII -> getParent ( ) -> instr_end ( ) ; if ( ! MII -> isBundle ( ) ) return producesStall ( * MII , MI ) ; for ( ++ MII ; MII != MIE && MII -> isInsideBundle ( ) ; ++ MII ) { const MachineInstr & J = * MII ; if ( producesStall ( J , MI ) ) return true ; } return false ;


<s> unsigned <ISA_LIT>InstrInfo :: reduceLoopCount ( MachineBasicBlock & MBB , MachineInstr * IndVar , MachineInstr & Cmp , SmallVectorImpl < MachineOperand > & Cond , SmallVectorImpl < MachineInstr * > & PrevInsts , unsigned Iter , unsigned MaxIter ) const { assert ( ( ! IndVar ) && isEndLoopN ( Cmp . getOpcode ( ) ) && <STR_LIT> ) ; MachineFunction * MF = MBB . getParent ( ) ; DebugLoc DL = Cmp . getDebugLoc ( ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( & MBB , Cmp . getOpcode ( ) , Cmp . getOperand ( <NUM_LIT> ) . getMBB ( ) , VisitedBBs ) ; if ( ! Loop ) return <NUM_LIT> ; if ( Loop -> getOpcode ( ) == <STR_LIT> || Loop -> getOpcode ( ) == <STR_LIT> ) { int64_t Offset = Loop -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Offset <= <NUM_LIT> ) Loop -> eraseFromParent ( ) ; else Loop -> getOperand ( <NUM_LIT> ) . setImm ( Offset - <NUM_LIT> ) ; return Offset - <NUM_LIT> ; } assert ( Loop -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned LoopCount = Loop -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LoopEnd = createVR ( MF , <STR_LIT> ) ; MachineInstr * NewCmp = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , LoopEnd ) . addReg ( LoopCount ) . addImm ( <NUM_LIT> ) ; unsigned NewLoopCount = createVR ( MF , <STR_LIT> ) ; MachineInstr * NewAdd = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , NewLoopCount ) . addReg ( LoopCount ) . addImm ( - <NUM_LIT> ) ; const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; for ( SmallVectorImpl < MachineInstr * > :: iterator I = PrevInsts . begin ( ) , E = PrevInsts . end ( ) ; I != E ; ++ I ) ( * I ) -> substituteRegister ( LoopCount , NewLoopCount , <NUM_LIT> , HRI ) ;


<s> DebugLoc DL = Cmp . getDebugLoc ( ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( & MBB , Cmp . getOpcode ( ) , Cmp . getOperand ( <NUM_LIT> ) . getMBB ( ) , VisitedBBs ) ; if ( ! Loop ) return <NUM_LIT> ; if ( Loop -> getOpcode ( ) == <STR_LIT> || Loop -> getOpcode ( ) == <STR_LIT> ) { int64_t Offset = Loop -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Offset <= <NUM_LIT> ) Loop -> eraseFromParent ( ) ; else Loop -> getOperand ( <NUM_LIT> ) . setImm ( Offset - <NUM_LIT> ) ; return Offset - <NUM_LIT> ; } assert ( Loop -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned LoopCount = Loop -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LoopEnd = createVR ( MF , <STR_LIT> ) ; MachineInstr * NewCmp = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , LoopEnd ) . addReg ( LoopCount ) . addImm ( <NUM_LIT> ) ; unsigned NewLoopCount = createVR ( MF , <STR_LIT> ) ; MachineInstr * NewAdd = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , NewLoopCount ) . addReg ( LoopCount ) . addImm ( - <NUM_LIT> ) ; const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; for ( SmallVectorImpl < MachineInstr * > :: iterator I = PrevInsts . begin ( ) , E = PrevInsts . end ( ) ; I != E ; ++ I ) ( * I ) -> substituteRegister ( LoopCount , NewLoopCount , <NUM_LIT> , HRI ) ; PrevInsts . clear ( ) ; PrevInsts . push_back ( NewCmp ) ; PrevInsts . push_back ( NewAdd ) ; if ( Iter == MaxIter ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( Loop -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addReg ( NewLoopCount ) ; if ( Iter == <NUM_LIT> ) Loop -> eraseFromParent ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <STR_LIT> ) ) ;

Cond . push_back ( NewCmp -> getOperand ( <NUM_LIT> ) ) ;


<s> unsigned Count = <NUM_LIT> ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugInstr ( ) ) continue ; if ( ! I -> isBranch ( ) ) return Count ; if ( Count && ( I -> getOpcode ( ) == <STR_LIT> ) ) llvm_unreachable ( <STR_LIT> ) ;


<s> if ( ! I -> isBranch ( ) ) return Count ; if ( Count && ( I -> getOpcode ( ) == <STR_LIT> ) ) llvm_unreachable ( <STR_LIT> ) ;


<s> if ( Cond . empty ( ) ) return true ; assert ( Cond [ <NUM_LIT> ] . isImm ( ) && <STR_LIT> ) ;

unsigned opcode = Cond [ <NUM_LIT> ] . getImm ( ) ;


<s> assert ( get ( opcode ) . isBranch ( ) && <STR_LIT> ) ; if ( isEndLoopN ( opcode ) ) return true ; unsigned NewOpcode = getInvertedPredicatedOpcode ( opcode ) ;

Cond [ <NUM_LIT> ] . setImm ( NewOpcode ) ;


<s> MI . setDesc ( get ( getInvertedPredicatedOpcode ( MI . getOpcode ( ) ) ) ) ; return true ;


<s> bool <ISA_LIT>InstrInfo :: reversePredSense ( MachineInstr & MI ) const { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ) ;

MI . setDesc ( get ( getInvertedPredicatedOpcode ( MI . getOpcode ( ) ) ) ) ;


<s> assert ( MIB -> isBundle ( ) ) ; MachineOperand & Operand = MIB -> getOperand ( <NUM_LIT> ) ;

if ( Operand . isImm ( ) ) Operand . setImm ( Operand . getImm ( ) | memShufDisabledMask ) ;


<s> MachineOperand & Operand = MIB -> getOperand ( <NUM_LIT> ) ;


<s> } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( HasAlloca ) SlotAlign = HFI . getStackAlignment ( ) ; unsigned Opc = SlotAlign < RegAlign ? <STR_LIT> : <STR_LIT> ; MachineMemOperand * MMOA = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , SlotAlign ) ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMOA ) ;


<s> bool <ISA_LIT>InstrInfo :: addLatencyToSchedule ( const MachineInstr * MI1 , const MachineInstr * MI2 ) const {

if ( isV60VectorInstruction ( MI1 ) && isV60VectorInstruction ( MI2 ) ) if ( ! isVecUsableNextPacket ( MI1 , MI2 ) ) return true ;


<s> int LastOpcode = LastInst -> getOpcode ( ) ; int SecLastOpcode = SecondLastInst ? SecondLastInst -> getOpcode ( ) : <NUM_LIT> ; if ( LastOpcode == <STR_LIT> && ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( SecLastOpcode == <STR_LIT> && ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( LastOpcode ) ; bool LastOpcodeHasNVJump = isNewValueJump ( LastInst ) ; if ( LastOpcodeHasJMP_c && ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( LastInst && ! SecondLastInst ) { if ( LastOpcode == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isEndLoopN ( LastOpcode ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOpcode ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastOpcodeHasJMP_c ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOpcode ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastOpcodeHasNVJump && ( LastInst -> getNumExplicitOperands ( ) == <NUM_LIT> ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOpcode ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> ; ) ; return true ; } bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( SecLastOpcode ) ; bool SecLastOpcodeHasNVJump = isNewValueJump ( SecondLastInst ) ; if ( SecLastOpcodeHasJMP_c && ( LastOpcode == <STR_LIT> ) ) { if ( ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( SecondLastInst -> getOpcode ( ) ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecLastOpcodeHasNVJump && ( SecondLastInst -> getNumExplicitOperands ( ) == <NUM_LIT> ) && ( LastOpcode == <STR_LIT> ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( SecondLastInst -> getOpcode ( ) ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = ~ <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = <NUM_LIT> ; break ; } switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( I != LoopEnd -> end ( ) && isEndLoopN ( I -> getOpcode ( ) ) ) { IndVarInst = nullptr ; CmpInst = & * I ; return false ; } return true ;


<s> bool <ISA_LIT>InstrInfo :: analyzeLoop ( MachineLoop & L , MachineInstr * & IndVarInst , MachineInstr * & CmpInst ) const { MachineBasicBlock * LoopEnd = L . getBottomBlock ( ) ;

MachineBasicBlock :: iterator I = LoopEnd -> getFirstTerminator ( ) ;


<s> void <ISA_LIT>InstrInfo :: anchor ( ) {


<s> if ( DisableNVSchedule ) return false ; if ( mayBeNewStore ( Second ) ) { const MachineOperand & Stored = Second -> getOperand ( Second -> getNumOperands ( ) - <NUM_LIT> ) ;

if ( ! Stored . isReg ( ) ) return false ;


<s> bool <ISA_LIT>InstrInfo :: canExecuteInBundle ( const MachineInstr * First , const MachineInstr * Second ) const { if ( DisableNVSchedule ) return false ; if ( mayBeNewStore ( Second ) ) { const MachineOperand & Stored = Second -> getOperand ( Second -> getNumOperands ( ) - <NUM_LIT> ) ; if ( ! Stored . isReg ( ) ) return false ;

for ( unsigned i = <NUM_LIT> , e = First -> getNumOperands ( ) ; i < e ; ++ i ) {


<s> if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( HRI . getSubReg ( SrcReg , <STR_LIT> ) , KillFlag ) . addReg ( HRI . getSubReg ( SrcReg , <STR_LIT> ) , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg , KillFlag ) ; return ; }


<s> DFAPacketizer * <ISA_LIT>InstrInfo :: CreateTargetScheduleState ( const TargetSubtargetInfo & STI ) const { const InstrItineraryData * II = STI . getInstrItineraryData ( ) ; return static_cast < const <ISA_LIT>Subtarget & > ( STI ) . createDFAPacketizer ( II ) ;


<s> return static_cast < const <ISA_LIT>Subtarget & > ( STI ) . createDFAPacketizer ( II ) ;


<s> TRC = & <STR_LIT> ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { TRC = & <STR_LIT> ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { TRC = & <STR_LIT> ;


<s> MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const TargetRegisterClass * TRC ; if ( VT == <STR_LIT> ) { TRC = & <STR_LIT> ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) {


<s> for ( unsigned oper = <NUM_LIT> ; oper < MI . getNumOperands ( ) ; ++ oper ) { MachineOperand MO = MI . getOperand ( oper ) ; if ( MO . isReg ( ) && MO . isDef ( ) ) { const TargetRegisterClass * RC = HRI . getMinimalPhysRegClass ( MO . getReg ( ) ) ; if ( RC == & <STR_LIT> ) { Pred . push_back ( MO ) ;


<s> } for ( MachineBasicBlock :: pred_iterator PB = BB -> pred_begin ( ) , PE = BB -> pred_end ( ) ; PB != PE ; ++ PB ) { if ( ! Visited . insert ( * PB ) . second ) continue ; if ( * PB == BB ) continue ; for ( MachineBasicBlock :: reverse_instr_iterator I = ( * PB ) -> instr_rbegin ( ) , E = ( * PB ) -> instr_rend ( ) ; I != E ; ++ I ) { int Opc = I -> getOpcode ( ) ; if ( Opc == LOOPi || Opc == LOOPr ) return & * I ; if ( Opc == EndLoopOp ) return <NUM_LIT> ; } MachineInstr * loop = findLoopInstr ( * PB , EndLoopOp , Visited ) ; if ( loop ) return loop ; }


<s> int LOOPr ; if ( EndLoopOp == <STR_LIT> ) { LOOPi = <STR_LIT> ; LOOPr = <STR_LIT> ; } else { LOOPi = <STR_LIT> ; LOOPr = <STR_LIT> ; } for ( MachineBasicBlock :: pred_iterator PB = BB -> pred_begin ( ) , PE = BB -> pred_end ( ) ; PB != PE ; ++ PB ) {

if ( ! Visited . insert ( * PB ) . second ) continue ;


<s> virtual MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const {


<s> NewMI = BuildMI ( B , MI , DL , get ( insn ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << getName ( NewMI -> getOpcode ( ) ) << <STR_LIT> << NewMI -> getDesc ( ) . getSchedClass ( ) ) ; NewMI -> eraseFromParent ( ) ;


<s> MachineBasicBlock & B = * A ; MachineBasicBlock :: iterator I = B . begin ( ) ; MachineInstr * MI = & * I ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstr * NewMI ; for ( unsigned insn = TargetOpcode :: GENERIC_OP_END + <NUM_LIT> ; insn < <STR_LIT> ; ++ insn ) { NewMI = BuildMI ( B , MI , DL , get ( insn ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << getName ( NewMI -> getOpcode ( ) ) << <STR_LIT> << NewMI -> getDesc ( ) . getSchedClass ( ) ) ; NewMI -> eraseFromParent ( ) ;


<s> short <ISA_LIT>InstrInfo :: getAbsoluteForm ( const MachineInstr * MI ) const {

return <STR_LIT> ( MI -> getOpcode ( ) ) ;


<s> short <ISA_LIT>InstrInfo :: getAbsoluteForm ( const MachineInstr * MI ) const { return <STR_LIT> ( MI -> getOpcode ( ) ) ;


<s> BasePos = <NUM_LIT> ; OffsetPos = <NUM_LIT> ; } else if ( MI -> mayStore ( ) ) { BasePos = <NUM_LIT> ; OffsetPos = <NUM_LIT> ; } else if ( MI -> mayLoad ( ) ) { BasePos = <NUM_LIT> ; OffsetPos = <NUM_LIT> ; } else return false ; if ( isPredicated ( * MI ) ) { BasePos ++ ; OffsetPos ++ ;


<s> short <ISA_LIT>InstrInfo :: getBaseWithLongOffset ( const MachineInstr * MI ) const {


<s> short <ISA_LIT>InstrInfo :: getBaseWithLongOffset ( const MachineInstr * MI ) const { return <STR_LIT> ( MI -> getOpcode ( ) ) ;


<s> short <ISA_LIT>InstrInfo :: getBaseWithRegOffset ( const MachineInstr * MI ) const {


<s> -- I ; if ( I -> isEHLabel ( ) ) return Jumpers ; } while ( I != MBB . instr_begin ( ) ) ; I = MBB . instr_end ( ) ; -- I ; while ( I -> isDebugValue ( ) ) { if ( I == MBB . instr_begin ( ) ) return Jumpers ; -- I ; } if ( ! isUnpredicatedTerminator ( * I ) ) return Jumpers ; MachineInstr * LastInst = & * I ; Jumpers . push_back ( LastInst ) ; MachineInstr * SecondLastInst = nullptr ; do { if ( & * I != LastInst && ! I -> isBundle ( ) && isUnpredicatedTerminator ( * I ) ) { if ( ! SecondLastInst ) { SecondLastInst = & * I ; Jumpers . push_back ( SecondLastInst ) ; } else return Jumpers ; } if ( I == MBB . instr_begin ( ) ) break ;


<s> unsigned <ISA_LIT>InstrInfo :: getCExtOpNum ( const MachineInstr * MI ) const { const uint64_t F = MI -> getDesc ( ) . TSFlags ;


<s> if ( ( GA -> getOpcode ( ) != <STR_LIT> ) || ( GB -> getOpcode ( ) != <STR_LIT> ) ) return - <NUM_LIT> ; unsigned DestReg = GA -> getOperand ( <NUM_LIT> ) . getReg ( ) ;

if ( ! GB -> readsRegister ( DestReg ) ) return - <NUM_LIT> ;


<s> enum <STR_LIT> inPredSense ; inPredSense = invertPredicate ? <STR_LIT> : <STR_LIT> ; int CondOpcode = <STR_LIT> ( Opc , inPredSense ) ; if ( CondOpcode >= <NUM_LIT> ) return CondOpcode ; switch ( Opc ) {


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; }


<s> if ( NVOpcode >= <NUM_LIT> ) return NVOpcode ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> bool taken = false ; const MachineBasicBlock * Src = MI -> getParent ( ) ; const MachineOperand * BrTarget = & MI -> getOperand ( <NUM_LIT> ) ; const MachineBasicBlock * Dst = BrTarget -> getMBB ( ) ; const BranchProbability Prediction = MBPI -> getEdgeProbability ( Src , Dst ) ;

if ( Prediction >= BranchProbability ( <NUM_LIT> , <NUM_LIT> ) ) taken = true ;


<s> case <STR_LIT> : return getDotNewPredJumpOp ( MI , MBPI ) ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; } return <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : return getDotNewPredJumpOp ( MI , MBPI ) ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; }


<s> int NewOp = opc ; if ( isPredicated ( NewOp ) && isPredicatedNew ( NewOp ) ) { NewOp = <STR_LIT> ( NewOp ) ;

assert ( NewOp >= <NUM_LIT> && <STR_LIT> ) ;


<s> short <ISA_LIT>InstrInfo :: getEquivalentHWInstr ( const MachineInstr * MI ) const {

return <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> ) ;


<s> return <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> ) ;


<s> for ( auto MII = BB -> instr_begin ( ) , End = BB -> instr_end ( ) ; MII != End ; MII ++ ) { MachineInstr * MI = & * MII ; if ( MI -> isDebugValue ( ) ) continue ; return MI ; }


<s> unsigned AccessSize ; return getBaseAndOffset ( MI , Value , AccessSize ) ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) {

Value = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> unsigned AccessSize ; return getBaseAndOffset ( MI , Value , AccessSize ) ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { Value = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ;


<s> atInsnStart = false ; } if ( atInsnStart && strncmp ( Str , MAI . getCommentString ( ) , strlen ( MAI . getCommentString ( ) ) ) == <NUM_LIT> ) atInsnStart = false ; } StringRef Occ ( <STR_LIT> ) ; Length += AStr . count ( Occ ) * <NUM_LIT> ;


<s> unsigned <ISA_LIT>InstrInfo :: getInstrLatency ( const InstrItineraryData * ItinData , const MachineInstr & MI , unsigned * PredCost ) const { return getInstrTimingClassLatency ( ItinData , & MI ) ;


<s> if ( ! ItinData ) return getInstrLatency ( ItinData , * MI ) ; if ( MI -> isTransient ( ) ) return <NUM_LIT> ;

unsigned Latency = ItinData -> getStageLatency ( MI -> getDesc ( ) . getSchedClass ( ) ) ;


<s> unsigned <ISA_LIT>InstrInfo :: getInstrTimingClassLatency ( const InstrItineraryData * ItinData , const MachineInstr * MI ) const { if ( ! ItinData ) return getInstrLatency ( ItinData , * MI ) ; if ( MI -> isTransient ( ) ) return <NUM_LIT> ; unsigned Latency = ItinData -> getStageLatency ( MI -> getDesc ( ) . getSchedClass ( ) ) ;

if ( ! EnableTimingClassLatency || MI -> getParent ( ) -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . useBSBScheduling ( ) ) if ( Latency > <NUM_LIT> ) Latency = <NUM_LIT> ;


<s> InvPredOpcode = isPredicatedTrue ( Opc ) ? <STR_LIT> ( Opc ) : <STR_LIT> ( Opc ) ; if ( InvPredOpcode >= <NUM_LIT> ) return InvPredOpcode ; llvm_unreachable ( <STR_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: getInvertedPredSense ( SmallVectorImpl < MachineOperand > & Cond ) const { if ( Cond . empty ( ) ) return false ; unsigned Opc = getInvertedPredicatedOpcode ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; Cond [ <NUM_LIT> ] . setImm ( Opc ) ;


<s> if ( isSigned ) return ~ ( - <NUM_LIT> << ( bits - <NUM_LIT> ) ) ; else return ~ ( - <NUM_LIT> << bits ) ;


<s> const uint64_t F = MI -> getDesc ( ) . TSFlags ;


<s> bool <ISA_LIT>InstrInfo :: getMemOpBaseRegImmOfs ( MachineInstr & LdSt , unsigned & BaseReg , int64_t & Offset , const TargetRegisterInfo * TRI ) const {


<s> unsigned isSigned = ( F >> <STR_LIT> ) & <STR_LIT> ;

unsigned bits = ( F >> <STR_LIT> ) & <STR_LIT> ;


<s> short NonExtOpcode = <STR_LIT> ( MI -> getOpcode ( ) ) ; if ( NonExtOpcode >= <NUM_LIT> ) return NonExtOpcode ; if ( MI -> getDesc ( ) . mayLoad ( ) || MI -> getDesc ( ) . mayStore ( ) ) { switch ( getAddrMode ( MI ) ) { case <STR_LIT> :


<s> short <ISA_LIT>InstrInfo :: getRegForm ( const MachineInstr * MI ) const {


<s> virtual const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const {


<s> for ( ; MI -> getOperand ( NumDefs ) . isReg ( ) && MI -> getOperand ( NumDefs ) . isDef ( ) ; ++ NumDefs ) assert ( NumDefs != MI -> getNumOperands ( ) - <NUM_LIT> && <STR_LIT> ) ; assert ( MI -> getOperand ( NumDefs ) . isSymbol ( ) && <STR_LIT> ) ; const char * AsmStr = MI -> getOperand ( NumDefs ) . getSymbolName ( ) ;

Size = getInlineAsmLength ( AsmStr , * MAI ) ;


<s> const uint64_t F = MI -> getDesc ( ) . TSFlags ; return ( F >> <STR_LIT> ) & <STR_LIT> ;


<s> const InstrItineraryData & II = * ST . getInstrItineraryData ( ) ; const InstrStage & IS = * II . beginStage ( MI -> getDesc ( ) . getSchedClass ( ) ) ; return IS . getUnits ( ) ;


<s> unsigned <ISA_LIT>InstrInfo :: getUnits ( const MachineInstr * MI ) const {

const TargetSubtargetInfo & ST = MI -> getParent ( ) -> getParent ( ) -> getSubtarget ( ) ;


<s> const uint64_t F = get ( Opcode ) . TSFlags ;


<s> bool <ISA_LIT>InstrInfo :: hasEHLabel ( const MachineBasicBlock * B ) const {

for ( auto & I : * B ) if ( I . isEHLabel ( ) ) return true ;


<s> for ( auto & I : * B ) if ( I . isEHLabel ( ) ) return true ;


<s> if ( MI -> getDesc ( ) . mayLoad ( ) || MI -> getDesc ( ) . mayStore ( ) ) { switch ( getAddrMode ( MI ) ) { case <STR_LIT> :

NonExtOpcode = <STR_LIT> ( MI -> getOpcode ( ) ) ;


<s> bool <ISA_LIT>InstrInfo :: hasPseudoInstrPair ( const MachineInstr * MI ) const { return <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> ) >= <NUM_LIT> ;


<s> if ( I -> isBarrier ( ) ) return true ; ++ I ; }


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & ST ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ) {


<s> void <ISA_LIT>InstrInfo :: immediateExtend ( MachineInstr * MI ) const { assert ( ( isExtendable ( MI ) || isConstExtended ( MI ) ) && <STR_LIT> ) ; short ExtOpNum = getCExtOpNum ( MI ) ; MachineOperand & MO = MI -> getOperand ( ExtOpNum ) ; assert ( ( MO . isMBB ( ) || MO . isImm ( ) ) && <STR_LIT> ) ; MO . addTargetFlag ( <STR_LIT> ) ;


<s> assert ( ( MO . isMBB ( ) || MO . isImm ( ) ) && <STR_LIT> ) ; MO . addTargetFlag ( <STR_LIT> ) ;


<s> RemoveBranch ( MBB ) ; return InsertBranch ( MBB , TBB , nullptr , Cond , DL ) ; } } BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else if ( isEndLoopN ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { int EndLoopOp = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( Cond [ <NUM_LIT> ] . isMBB ( ) ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( TBB , EndLoopOp , VisitedBBs ) ; assert ( Loop != <NUM_LIT> && <STR_LIT> ) ; Loop -> getOperand ( <NUM_LIT> ) . setMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( EndLoopOp ) ) . addMBB ( TBB ) ; } else if ( isNewValueJump ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Flags1 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) ; ) ; if ( Cond [ <NUM_LIT> ] . isReg ( ) ) { unsigned Flags2 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags2 ) . addMBB ( TBB ) ; } else if ( Cond [ <NUM_LIT> ] . isImm ( ) ) { BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addMBB ( TBB ) ; } else llvm_unreachable ( <STR_LIT> ) ; } else { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; const MachineOperand & RO = Cond [ <NUM_LIT> ] ; unsigned Flags = getUndefRegState ( RO . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( RO . getReg ( ) , Flags ) . addMBB ( TBB ) ; } return <NUM_LIT> ; } assert ( ( ! Cond . empty ( ) ) && <STR_LIT> ) ; assert ( ( ! isNewValueJump ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) && <STR_LIT> ) ; if ( isEndLoopN ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { int EndLoopOp = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( Cond [ <NUM_LIT> ] . isMBB ( ) ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ;


<s> void <ISA_LIT>InstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { DebugLoc DL ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ;


<s> unsigned NewOpcode = getInvertedPredicatedOpcode ( MI -> getOpcode ( ) ) ; int TargetPos = MI -> getNumOperands ( ) - <NUM_LIT> ; while ( ( TargetPos > - <NUM_LIT> ) && ! MI -> getOperand ( TargetPos ) . isMBB ( ) ) -- TargetPos ;

assert ( ( TargetPos >= <NUM_LIT> ) && MI -> getOperand ( TargetPos ) . isMBB ( ) ) ;


<s> bool <ISA_LIT>InstrInfo :: isAbsoluteSet ( const MachineInstr * MI ) const { return ( getAddrMode ( MI ) == <STR_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: isAbsoluteSet ( const MachineInstr * MI ) const {

return ( getAddrMode ( MI ) == <STR_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: isAccumulator ( const MachineInstr * MI ) const {

const uint64_t F = MI -> getDesc ( ) . TSFlags ;


<s> bool <ISA_LIT>InstrInfo :: isComplex ( const MachineInstr * MI ) const { const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const TargetInstrInfo * TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ;

const <ISA_LIT>InstrInfo * QII = ( const <ISA_LIT>InstrInfo * ) TII ;


<s> bool <ISA_LIT>InstrInfo :: isCompoundBranchInstr ( const MachineInstr * MI ) const { return ( getType ( MI ) == <STR_LIT> && MI -> isBranch ( ) ) ;


<s> return ( MI -> isBranch ( ) && isPredicated ( * MI ) ) || isConditionalTransfer ( MI ) || isConditionalALU32 ( MI ) || isConditionalLoad ( MI ) || ( MI -> mayStore ( ) && isPredicated ( * MI ) && ! isNewValueStore ( MI ) && ! isPredicatedNew ( * MI ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> int PNewOpcode = <STR_LIT> ( MI -> getOpcode ( ) ) ;


<s> if ( ! MI -> getDesc ( ) . mayLoad ( ) || ! isPredicated ( * MI ) ) return false ; int PNewOpcode = <STR_LIT> ( MI -> getOpcode ( ) ) ; return PNewOpcode >= <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>InstrInfo :: isConditionalTransfer ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> const MachineOperand & MO = MI -> getOperand ( ExtOpNum ) ; if ( MO . getTargetFlags ( ) && <STR_LIT> ) return true ; if ( MO . isMBB ( ) ) return false ; if ( MO . isGlobal ( ) || MO . isSymbol ( ) || MO . isBlockAddress ( ) || MO . isJTI ( ) || MO . isCPI ( ) ) return true ; assert ( MO . isImm ( ) && <STR_LIT> ) ;


<s> return isIntRegForSubInst ( HRI . getSubReg ( Reg , <STR_LIT> ) ) && isIntRegForSubInst ( HRI . getSubReg ( Reg , <STR_LIT> ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return false ;


<s> SmallVector < unsigned , <NUM_LIT> > DefsB ; SmallVector < unsigned , <NUM_LIT> > UsesA ; SmallVector < unsigned , <NUM_LIT> > UsesB ; parseOperands ( ProdMI , DefsA , UsesA ) ; parseOperands ( ConsMI , DefsB , UsesB ) ; for ( auto & RegA : DefsA ) for ( auto & RegB : UsesB ) { if ( RegA == RegB ) return true ; if ( <STR_LIT> . contains ( RegA ) ) for ( MCSubRegIterator SubRegs ( RegA , & HRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) if ( RegB == * SubRegs ) return true ; if ( <STR_LIT> . contains ( RegB ) ) for ( MCSubRegIterator SubRegs ( RegB , & HRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) if ( RegA == * SubRegs ) return true ;


<s> bool <ISA_LIT>InstrInfo :: isDotCurInst ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>InstrInfo :: isDotNewInst ( const MachineInstr * MI ) const {

if ( isNewValueInst ( MI ) || ( isPredicated ( * MI ) && isPredicatedNew ( * MI ) ) ) return true ;


<s> <STR_LIT> MIbG = getDuplexCandidateGroup ( MIb ) ;

return ( isDuplexPairMatch ( MIaG , MIbG ) || isDuplexPairMatch ( MIbG , MIaG ) ) ;


<s> bool <ISA_LIT>InstrInfo :: isDuplexPair ( const MachineInstr * MIa , const MachineInstr * MIb ) const {

<STR_LIT> MIaG = getDuplexCandidateGroup ( MIa ) ;


<s> case <STR_LIT> : return ( Gb == <STR_LIT> || Gb == <STR_LIT> || Gb == <STR_LIT> || Gb == <STR_LIT> ) ; case <STR_LIT> : return ( Gb == <STR_LIT> || Gb == <STR_LIT> || Gb == <STR_LIT> || Gb == <STR_LIT> || Gb == <STR_LIT> ) ; case <STR_LIT> : return ( Gb == <STR_LIT> ) ; case <STR_LIT> : return ( Gb == <STR_LIT> ) ; }


<s> if ( ! MI ) return false ; if ( MI -> mayLoad ( ) || MI -> mayStore ( ) || MI -> isCompare ( ) ) return true ; unsigned SchedClass = MI -> getDesc ( ) . getSchedClass ( ) ; if ( SchedClass == <STR_LIT> :: M_tc_3or4x_SLOT23 ) return true ;


<s> bool <ISA_LIT>InstrInfo :: isEarlySourceInstr ( const MachineInstr * MI ) const { if ( ! MI ) return false ;

if ( MI -> mayLoad ( ) || MI -> mayStore ( ) || MI -> isCompare ( ) ) return true ;


<s> return ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ;


<s> case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_BlockAddress : return true ;


<s> case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_BlockAddress : return true ; default : return false ;


<s> const uint64_t F = MID . TSFlags ; if ( ( F >> <STR_LIT> ) & <STR_LIT> ) return true ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : return true ; default : return false ; } return false ;


<s> bool <ISA_LIT>InstrInfo :: isExtended ( const MachineInstr * MI ) const { const uint64_t F = MI -> getDesc ( ) . TSFlags ; if ( ( F >> <STR_LIT> ) & <STR_LIT> ) return true ; for ( MachineInstr :: const_mop_iterator I = MI -> operands_begin ( ) , E = MI -> operands_end ( ) ; I != E ; ++ I ) { if ( I -> getTargetFlags ( ) && <STR_LIT> ) return true ; }


<s> unsigned Opcode = MI -> getOpcode ( ) ; const uint64_t F = get ( Opcode ) . TSFlags ; return ( F >> <STR_LIT> ) & <STR_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: isFloat ( const MachineInstr * MI ) const { unsigned Opcode = MI -> getOpcode ( ) ;

const uint64_t F = get ( Opcode ) . TSFlags ;


<s> if ( ! isV60VectorInstruction ( I ) ) return false ; if ( ! I -> mayLoad ( ) && ! I -> mayStore ( ) ) return false ; return J -> isIndirectBranch ( ) || isIndirectCall ( J ) || isIndirectL4Return ( J ) ;


<s> if ( ! isV60VectorInstruction ( I ) ) return false ; if ( ! I -> mayLoad ( ) && ! I -> mayStore ( ) ) return false ;

return J -> isIndirectBranch ( ) || isIndirectCall ( J ) || isIndirectL4Return ( J ) ;


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>InstrInfo :: isIndirectCall ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; }


<s> bool <ISA_LIT>InstrInfo :: isIndirectL4Return ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; }


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>InstrInfo :: isJumpR ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> :


<s> return isInt < <NUM_LIT> > ( offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( offset ) ; case <STR_LIT> : case <STR_LIT> :


<s> DEBUG ( LRMI -> dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ( isEarly ? <STR_LIT> : <STR_LIT> ) ) ; DEBUG ( ESMI -> dump ( ) ) ; if ( isLate && isEarly ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ; }


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand OpFI = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpFI . isFI ( ) ) return <NUM_LIT> ; const MachineOperand OpOff = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } case <STR_LIT> :


<s> return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>InstrInfo :: isNewValue ( unsigned Opcode ) const {


<s> const uint64_t F = get ( Opcode ) . TSFlags ;


<s> return isNewValueJump ( MI ) || isNewValueStore ( MI ) ;


<s> bool <ISA_LIT>InstrInfo :: isNewValueJump ( unsigned Opcode ) const {

return isNewValue ( Opcode ) && get ( Opcode ) . isBranch ( ) && isPredicated ( Opcode ) ;


<s> bool <ISA_LIT>InstrInfo :: isNewValueJump ( unsigned Opcode ) const { return isNewValue ( Opcode ) && get ( Opcode ) . isBranch ( ) && isPredicated ( Opcode ) ;


<s> const uint64_t F = get ( Opcode ) . TSFlags ; return ( F >> <STR_LIT> ) & <STR_LIT> ;


<s> return ( ( F >> <STR_LIT> ) & <STR_LIT> ) == OperandNum ;


<s> bool <ISA_LIT>InstrInfo :: isPostIncrement ( const MachineInstr * MI ) const { return getAddrMode ( MI ) == <STR_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: isPredicated ( unsigned Opcode ) const {


<s> const uint64_t F = get ( Opcode ) . TSFlags ; assert ( isPredicated ( Opcode ) ) ;


assert ( ( F >> <STR_LIT> ) & <STR_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: isPredicatedTrue ( unsigned Opcode ) const { const uint64_t F = get ( Opcode ) . TSFlags ; assert ( ( F >> <STR_LIT> ) & <STR_LIT> ) ; return ! ( ( F >> <STR_LIT> ) & <STR_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: isPredicateLate ( unsigned Opcode ) const { const uint64_t F = get ( Opcode ) . TSFlags ;

return ~ ( F >> <STR_LIT> ) & <STR_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: isPredicateLate ( unsigned Opcode ) const { const uint64_t F = get ( Opcode ) . TSFlags ; return ~ ( F >> <STR_LIT> ) & <STR_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumInstrs , BranchProbability Probability ) const { return NumInstrs <= <NUM_LIT> ;


<s> return nonDbgBBSize ( & TMBB ) <= <NUM_LIT> && nonDbgBBSize ( & FMBB ) <= <NUM_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumTCycles , unsigned ExtraTCycles , MachineBasicBlock & FMBB , unsigned NumFCycles , unsigned ExtraFCycles , BranchProbability Probability ) const {

return nonDbgBBSize ( & TMBB ) <= <NUM_LIT> && nonDbgBBSize ( & FMBB ) <= <NUM_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: isSaveCalleeSavedRegsCall ( const MachineInstr * MI ) const {

return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ;


<s> for ( auto I : MBB -> successors ( ) ) if ( I -> isEHPad ( ) ) return true ; } if ( MI . getOpcode ( ) == <STR_LIT> ) return true ;

if ( MI . getDesc ( ) . isTerminator ( ) || MI . isPosition ( ) ) return true ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>InstrInfo :: isSpillPredRegOp ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : return true ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand & OpFI = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpFI . isFI ( ) ) return <NUM_LIT> ; const MachineOperand & OpOff = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( ! MI -> isBranch ( ) ) return false ; for ( auto & Op : MI -> operands ( ) ) if ( Op . isGlobal ( ) || Op . isSymbol ( ) ) return true ;


<s> bool <ISA_LIT>InstrInfo :: isTailCall ( const MachineInstr * MI ) const {

if ( ! MI -> isBranch ( ) ) return false ;


<s> switch ( SchedClass ) { case <STR_LIT> :: ALU32_2op_tc_1_SLOT0123 : case <STR_LIT> :: ALU32_3op_tc_1_SLOT0123 : case <STR_LIT> :: ALU32_ADDI_tc_1_SLOT0123 : case <STR_LIT> :: ALU64_tc_1_SLOT23 : case <STR_LIT> :: EXTENDER_tc_1_SLOT0123 : case <STR_LIT> :: S_2op_tc_1_SLOT23 :


unsigned SchedClass = MI -> getDesc ( ) . getSchedClass ( ) ;


return <STR_LIT> <= V && V <= <STR_LIT> ;


<s> } if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { return ( Offset >= <ISA_LIT>_MEMV_AUTOINC_MIN_128B && Offset <= <ISA_LIT>_MEMV_AUTOINC_MAX_128B && ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ; } if ( VT == <STR_LIT> ) { return ( Offset >= <ISA_LIT>_MEMD_AUTOINC_MIN && Offset <= <ISA_LIT>_MEMD_AUTOINC_MAX && ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ; } if ( VT == <STR_LIT> ) { return ( Offset >= <ISA_LIT>_MEMW_AUTOINC_MIN && Offset <= <ISA_LIT>_MEMW_AUTOINC_MAX && ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ; } if ( VT == <STR_LIT> ) { return ( Offset >= <ISA_LIT>_MEMH_AUTOINC_MIN && Offset <= <ISA_LIT>_MEMH_AUTOINC_MAX && ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMV_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMV_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMV_OFFSET_MIN_128B ) && ( Offset <= <ISA_LIT>_MEMV_OFFSET_MAX_128B ) ; case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; } if ( Extend ) return true ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMW_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMW_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> :


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>InstrInfo :: isVecAcc ( const MachineInstr * MI ) const { return MI && isV60VectorInstruction ( MI ) && isAccumulator ( MI ) ;


<s> return MI && isV60VectorInstruction ( MI ) && isAccumulator ( MI ) ;


<s> if ( ! MI ) return false ; const uint64_t F = get ( MI -> getOpcode ( ) ) . TSFlags ;

const uint64_t V = ( ( F >> <STR_LIT> ) & <STR_LIT> ) ;


<s> if ( ! MI ) return false ; const uint64_t F = get ( MI -> getOpcode ( ) ) . TSFlags ; const uint64_t V = ( ( F >> <STR_LIT> ) & <STR_LIT> ) ; return V == <STR_LIT> || V == <STR_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: isVecUsableNextPacket ( const MachineInstr * ProdMI , const MachineInstr * ConsMI ) const { if ( EnableACCForwarding && isVecAcc ( ProdMI ) && isVecAcc ( ConsMI ) ) return true ;

if ( EnableALUForwarding && ( isVecALU ( ConsMI ) || isLateSourceInstr ( ConsMI ) ) ) return true ;


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , Align ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) {


<s> bool <ISA_LIT>InstrInfo :: mayBeCurLoad ( const MachineInstr * MI ) const { auto & HST = MI -> getParent ( ) -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ;

const uint64_t F = MI -> getDesc ( ) . TSFlags ;


<s> unsigned <ISA_LIT>InstrInfo :: nonDbgBBSize ( const MachineBasicBlock * BB ) const {

return nonDbgMICount ( BB -> instr_begin ( ) , BB -> instr_end ( ) ) ;


<s> return nonDbgMICount ( ++ MII , getBundleEnd ( * BundleHead ) ) ;


if ( ! MIB -> isDebugValue ( ) ) ++ Count ;


<s> unsigned Count = <NUM_LIT> ; for ( ; MIB != MIE ; ++ MIB ) { if ( ! MIB -> isDebugValue ( ) ) ++ Count ;


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ;


<s> if ( ! Reg ) continue ; if ( MO . isUse ( ) ) Uses . push_back ( MO . getReg ( ) ) ; if ( MO . isDef ( ) ) Defs . push_back ( MO . getReg ( ) ) ; }


<s> const MachineOperand & MO = MI -> getOperand ( opNum ) ; if ( MO . isReg ( ) && MO . isDef ( ) && MO . isImplicit ( ) && ( MO . getReg ( ) == PredReg ) ) return false ; } return MI -> getOpcode ( ) != <STR_LIT> ;


<s> while ( NOp < NumOps ) { MachineOperand & Op = MI . getOperand ( NOp ) ; if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . isImplicit ( ) ) break ; T . addOperand ( Op ) ; NOp ++ ; } unsigned PredReg , PredRegPos , PredRegFlags ; bool GotPredReg = getPredReg ( Cond , PredReg , PredRegPos , PredRegFlags ) ; ( void ) GotPredReg ; assert ( GotPredReg ) ; T . addReg ( PredReg , PredRegFlags ) ; while ( NOp < NumOps ) T . addOperand ( MI . getOperand ( NOp ++ ) ) ; MI . setDesc ( get ( PredOpc ) ) ; while ( unsigned n = MI . getNumOperands ( ) ) MI . RemoveOperand ( n - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , n = T -> getNumOperands ( ) ; i < n ; ++ i ) MI . addOperand ( T -> getOperand ( i ) ) ; MachineBasicBlock :: instr_iterator TI = T -> getIterator ( ) ; B . erase ( TI ) ;

MachineRegisterInfo & MRI = B . getParent ( ) -> getRegInfo ( ) ;


<s> bool <ISA_LIT>InstrInfo :: PredOpcodeHasJMP_c ( unsigned Opcode ) const {

return ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) ;


<s> return ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: predOpcodeHasNot ( ArrayRef < MachineOperand > Cond ) const {

if ( Cond . empty ( ) || ! isPredicated ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) return false ;


<s> if ( ! isV60VectorInstruction ( J ) ) return false ; else if ( isVecUsableNextPacket ( J , MI ) ) return false ; return true ; } for ( ++ MII ; MII != MIE && MII -> isInsideBundle ( ) ; ++ MII ) { const MachineInstr * J = & * MII ; if ( producesStall ( J , MI ) ) return true ;


<s> MachineInstr * NewAdd = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , NewLoopCount ) . addReg ( LoopCount ) . addImm ( - <NUM_LIT> ) ; for ( SmallVectorImpl < MachineInstr * > :: iterator I = PrevInsts . begin ( ) , E = PrevInsts . end ( ) ; I != E ; ++ I ) ( * I ) -> substituteRegister ( LoopCount , NewLoopCount , <NUM_LIT> , getRegisterInfo ( ) ) ; PrevInsts . clear ( ) ; PrevInsts . push_back ( NewCmp ) ; PrevInsts . push_back ( NewAdd ) ; if ( Iter == MaxIter ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( Loop -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addReg ( NewLoopCount ) ; if ( Iter == <NUM_LIT> ) Loop -> eraseFromParent ( ) ;

Cond . push_back ( MachineOperand :: CreateImm ( <STR_LIT> ) ) ;