<s> for ( NodeId N : DefQ ) { auto TA = DFG . addr < DefNode * > ( N ) ; bool IsPhi = TA . Addr -> getFlags ( ) & NodeAttrs :: PhiRef ; if ( ! IsPhi && ! PRI . alias ( RefRR , TA . Addr -> getRegRef ( DFG ) ) ) continue ; Defs . insert ( TA . Id ) ; Owners . insert ( TA . Addr -> getOwner ( DFG ) . Id ) ; } auto Block = [ this ] ( NodeAddr < InstrNode * > IA ) -> MachineBasicBlock * { if ( IA . Addr -> getKind ( ) == NodeAttrs :: Stmt ) return NodeAddr < StmtNode * > ( IA ) . Addr -> getCode ( ) -> getParent ( ) ; assert ( IA . Addr -> getKind ( ) == NodeAttrs :: Phi ) ; NodeAddr < PhiNode * > PA = IA ; NodeAddr < BlockNode * > BA = PA . Addr -> getOwner ( DFG ) ; return BA . Addr -> getCode ( ) ; } ; auto Less = [ & Block , this ] ( NodeId A , NodeId B ) -> bool { if ( A == B ) return false ; auto OA = DFG . addr < InstrNode * > ( A ) , OB = DFG . addr < InstrNode * > ( B ) ; MachineBasicBlock * BA = Block ( OA ) , * BB = Block ( OB ) ; if ( BA != BB ) return MDT . dominates ( BB , BA ) ; bool StmtA = OA . Addr -> getKind ( ) == NodeAttrs :: Stmt ; bool StmtB = OB . Addr -> getKind ( ) == NodeAttrs :: Stmt ; if ( StmtA ) { if ( ! StmtB ) return true ; MachineInstr * CA = NodeAddr < StmtNode * > ( OA ) . Addr -> getCode ( ) ; MachineInstr * CB = NodeAddr < StmtNode * > ( OB ) . Addr -> getCode ( ) ; if ( CA == CB ) return A < B ; return MDT . dominates ( CB , CA ) ; } else { if ( StmtB ) return false ;


<s> } IDFB . insert ( & B ) ; IDF [ & B ] . insert ( IDFB . begin ( ) , IDFB . end ( ) ) ; } for ( auto I : IDF ) for ( auto S : I . second ) IIDF [ S ] . insert ( I . first ) ; computePhiInfo ( ) ; NodeAddr < FuncNode * > FA = DFG . getFunc ( ) ; NodeList Blocks = FA . Addr -> members ( DFG ) ; for ( NodeAddr < BlockNode * > BA : Blocks ) { MachineBasicBlock * MB = BA . Addr -> getCode ( ) ; RefMap & LON = PhiLON [ MB ] ; for ( auto P : BA . Addr -> members_if ( DFG . IsCode < NodeAttrs :: Phi > , DFG ) ) for ( const RefMap :: value_type & S : RealUseMap [ P . Id ] ) LON [ S . first ] . insert ( S . second . begin ( ) , S . second . end ( ) ) ; } if ( Trace ) { dbgs ( ) << <STR_LIT> ; for ( auto & I : PhiLON ) dbgs ( ) << <STR_LIT> << I . first -> getNumber ( ) << <STR_LIT> << Print < RefMap > ( I . second , DFG ) << '\n' ; } for ( NodeAddr < BlockNode * > BA : Blocks ) { NodeList Phis = BA . Addr -> members_if ( DFG . IsCode < NodeAttrs :: Phi > , DFG ) ; for ( NodeAddr < PhiNode * > PA : Phis ) { RefMap & RUs = RealUseMap [ PA . Id ] ; if ( RUs . empty ( ) ) continue ; NodeSet SeenUses ; for ( auto U : PA . Addr -> members_if ( DFG . IsRef < NodeAttrs :: Use > , DFG ) ) {

if ( ! SeenUses . insert ( U . Id ) . second ) continue ;


<s> Liveness ( MachineRegisterInfo & mri , const DataFlowGraph & g ) : DFG ( g ) , TRI ( g . getTRI ( ) ) , PRI ( g . getPRI ( ) ) , MDT ( g . getDT ( ) ) , MDF ( g . getDF ( ) ) , LiveMap ( g . getPRI ( ) ) , Empty ( ) , NoRegs ( g . getPRI ( ) ) {


<s> continue ; } do { LaneBitmask M = TRI . getSubRegIndexLaneMask ( S . getSubRegIndex ( ) ) ; if ( ( M & I . LaneMask ) . any ( ) ) LV . set ( S . getSubReg ( ) ) ; ++ S ; } while ( S . isValid ( ) ) ; } } ; BitVector LiveIn ( TRI . getNumRegs ( ) ) , Live ( TRI . getNumRegs ( ) ) ; CopyLiveIns ( B , LiveIn ) ; for ( auto SI : B -> successors ( ) ) CopyLiveIns ( SI , Live ) ; for ( auto I = B -> rbegin ( ) , E = B -> rend ( ) ; I != E ; ++ I ) { MachineInstr * MI = & * I ; if ( MI -> isDebugValue ( ) ) continue ; MI -> clearKillInfo ( ) ;

for ( auto & Op : MI -> operands ( ) ) {


<s> do { LaneBitmask M = TRI . getSubRegIndexLaneMask ( S . getSubRegIndex ( ) ) ; if ( ( M & I . LaneMask ) . any ( ) ) LV . set ( S . getSubReg ( ) ) ; ++ S ; } while ( S . isValid ( ) ) ; } } ; BitVector LiveIn ( TRI . getNumRegs ( ) ) , Live ( TRI . getNumRegs ( ) ) ; CopyLiveIns ( B , LiveIn ) ; for ( auto SI : B -> successors ( ) ) CopyLiveIns ( SI , Live ) ; for ( auto I = B -> rbegin ( ) , E = B -> rend ( ) ; I != E ; ++ I ) { MachineInstr * MI = & * I ; if ( MI -> isDebugValue ( ) ) continue ; MI -> clearKillInfo ( ) ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . isImplicit ( ) ) continue ; unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isPhysicalRegister ( R ) ) continue ; for ( MCSubRegIterator SR ( R , & TRI , true ) ; SR . isValid ( ) ; ++ SR ) Live . reset ( * SR ) ; } for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isUse ( ) || Op . isUndef ( ) ) continue ; unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isPhysicalRegister ( R ) ) continue ; bool IsLive = false ;

for ( MCRegAliasIterator AR ( R , & TRI , true ) ; AR . isValid ( ) ; ++ AR ) {


<s> for ( auto I = B -> rbegin ( ) , E = B -> rend ( ) ; I != E ; ++ I ) { MachineInstr * MI = & * I ; if ( MI -> isDebugValue ( ) ) continue ; MI -> clearKillInfo ( ) ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . isImplicit ( ) ) continue ; unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isPhysicalRegister ( R ) ) continue ; for ( MCSubRegIterator SR ( R , & TRI , true ) ; SR . isValid ( ) ; ++ SR ) Live . reset ( * SR ) ; } for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isUse ( ) ) continue ; unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isPhysicalRegister ( R ) ) continue ; bool IsLive = false ; for ( MCRegAliasIterator AR ( R , & TRI , true ) ; AR . isValid ( ) ; ++ AR ) { if ( ! Live [ * AR ] ) continue ;


<s> auto CopyLiveIns = [ this ] ( MachineBasicBlock * B , BitVector & LV ) -> void { for ( auto I : B -> liveins ( ) ) { MCSubRegIndexIterator S ( I . PhysReg , & TRI ) ; if ( ! S . isValid ( ) ) { LV . set ( I . PhysReg ) ; continue ; } do { LaneBitmask M = TRI . getSubRegIndexLaneMask ( S . getSubRegIndex ( ) ) ; if ( ( M & I . LaneMask ) . any ( ) ) LV . set ( S . getSubReg ( ) ) ; ++ S ; } while ( S . isValid ( ) ) ; } } ; BitVector LiveIn ( TRI . getNumRegs ( ) ) , Live ( TRI . getNumRegs ( ) ) ; CopyLiveIns ( B , LiveIn ) ; for ( auto SI : B -> successors ( ) ) CopyLiveIns ( SI , Live ) ; for ( auto I = B -> rbegin ( ) , E = B -> rend ( ) ; I != E ; ++ I ) {


<s> Liveness ( MachineRegisterInfo & mri , const DataFlowGraph & g ) : DFG ( g ) , TRI ( g . getTRI ( ) ) , MDT ( g . getDT ( ) ) , MDF ( g . getDF ( ) ) , RAI ( g . getRAI ( ) ) , MRI ( mri ) , Empty ( ) , Trace ( false ) {


<s> return getAllReachingDefs ( RefRR , RefA , false , NoRegs ) ;


<s> Liveness ( MachineRegisterInfo & mri , const DataFlowGraph & g ) : DFG ( g ) , TRI ( g . getTRI ( ) ) , PRI ( g . getPRI ( ) ) , MDT ( g . getDT ( ) ) , MDF ( g . getDF ( ) ) , MRI ( mri ) , LiveMap ( g . getPRI ( ) ) , Empty ( ) , NoRegs ( g . getPRI ( ) ) , Trace ( false ) {


<s> for ( NodeAddr < BlockNode * > BA : Blocks ) { MachineBasicBlock * MB = BA . Addr -> getCode ( ) ; RefMap & LON = PhiLON [ MB ] ; for ( auto P : BA . Addr -> members_if ( DFG . IsCode < NodeAttrs :: Phi > , DFG ) ) for ( const RefMap :: value_type & S : RealUseMap [ P . Id ] ) LON [ S . first ] . insert ( S . second . begin ( ) , S . second . end ( ) ) ; } if ( Trace ) { dbgs ( ) << <STR_LIT> ; for ( auto & I : PhiLON ) dbgs ( ) << <STR_LIT> << I . first -> getNumber ( ) << <STR_LIT> << Print < RefMap > ( I . second , DFG ) << '\n' ; } for ( NodeAddr < BlockNode * > BA : Blocks ) { NodeList Phis = BA . Addr -> members_if ( DFG . IsCode < NodeAttrs :: Phi > , DFG ) ; for ( NodeAddr < PhiNode * > PA : Phis ) { RefMap & RUs = RealUseMap [ PA . Id ] ; if ( RUs . empty ( ) ) continue ; NodeSet SeenUses ; for ( auto U : PA . Addr -> members_if ( DFG . IsRef < NodeAttrs :: Use > , DFG ) ) { if ( ! SeenUses . insert ( U . Id ) . second ) continue ; NodeAddr < PhiUseNode * > PUA = U ; if ( PUA . Addr -> getReachingDef ( ) == <NUM_LIT> ) continue ; auto PrA = DFG . addr < BlockNode * > ( PUA . Addr -> getPredecessor ( ) ) ; RefMap & LOX = PhiLOX [ PrA . Addr -> getCode ( ) ] ; for ( const std :: pair < RegisterId , NodeRefSet > & RS : RUs ) { for ( std :: pair < NodeId , LaneBitmask > P : RS . second ) { RegisterRef S ( RS . first , P . second ) ; NodeList Ds = getAllReachingDefs ( S , PUA , true , false , NoRegs ) ; for ( NodeAddr < DefNode * > D : Ds ) LOX [ S . Reg ] . insert ( { D . Id , S . Mask } ) ;


<s> NodeSet Liveness :: getAllReachingDefsRec ( RegisterRef RefRR , NodeAddr < RefNode * > RefA , NodeSet & Visited , const NodeSet & Defs ) { RegisterAggr DefRRs ( PRI ) ; for ( NodeId D : Defs ) { const auto DA = DFG . addr < const DefNode * > ( D ) ; if ( ! ( DA . Addr -> getFlags ( ) & NodeAttrs :: PhiRef ) ) DefRRs . insert ( DA . Addr -> getRegRef ( DFG ) ) ; } NodeList RDs = getAllReachingDefs ( RefRR , RefA , true , DefRRs ) ;


<s> if ( ! ( DA . Addr -> getFlags ( ) & NodeAttrs :: PhiRef ) ) continue ; NodeAddr < PhiNode * > PA = DA . Addr -> getOwner ( DFG ) ; if ( Visited . count ( PA . Id ) ) continue ; Visited . insert ( PA . Id ) ; for ( auto U : PA . Addr -> members_if ( DFG . IsRef < NodeAttrs :: Use > , DFG ) ) { const auto & T = getAllReachingDefsRec ( RefRR , U , Visited , TmpDefs ) ; Result . insert ( T . begin ( ) , T . end ( ) ) ; } } return Result ;


<s> LiveMapType ( const TargetRegisterInfo & tri ) : Empty ( tri ) {


<s> Liveness ( MachineRegisterInfo & mri , const DataFlowGraph & g ) : DFG ( g ) , TRI ( g . getTRI ( ) ) , MDT ( g . getDT ( ) ) , MDF ( g . getDF ( ) ) , MRI ( mri ) , LiveMap ( g . getTRI ( ) ) , Empty ( ) , NoRegs ( g . getTRI ( ) ) , Trace ( false ) {


<s>
RefMap
&
LOX
=
PhiLOX
[
PrA
.
Addr
->
getCode
(
)
]
;
for
(
const
std
::
pair
<
RegisterId
,
NodeRefSet
>
&
RS
:
RUs
)
{
for
(
std
::
pair
<
NodeId
,
LaneBitmask
>
P
:
RS
.
second
)
{
RegisterRef
S
(
RS
.
first
,
P
.
second
)
;
NodeList
Ds
=
getAllReachingDefs
(
S
,
PUA
,
true
,
false
,
NoRegs
)
;
for
(
NodeAddr
<
DefNode
*
>
D
:
Ds
)
{
RegisterAggr
TA
(
PRI
)
;
TA
.
insert
(
D
.
Addr
->
getRegRef
(
DFG
)
)
.
intersect
(
S
)
;
LaneBitmask
TM
=
TA
.
makeRegRef
(
)
.
Mask
;
LOX
[
S
.
Reg
]
.
insert
(
{
D
.
Id
,
TM
}
)
;
}
}
}
for
(
NodeAddr
<
PhiUseNode
*
>
T
:
DFG
.
getRelatedRefs
(
PA
,
PUA
)
)
SeenUses
.
insert
(
T
.
Id
)
;
}
}
}
if
(
Trace
)
{
dbgs
(
)
<<
<STR_LIT>
;
for
(
auto
&
I
:
PhiLOX
)
dbgs
(
)
<<
<STR_LIT>
<<
I
.
first
->
getNumber
(
)
<<
<STR_LIT>
<<
Print
<
RefMap
>
(
I
.
second
,
DFG
)
<<
'\n'
;
}
RefMap
LiveIn
;
traverse
(
&
MF
.
front
(
)
,
LiveIn
)
;
LiveMap
[
&
MF
.
front
(
)
]
.
insert
(
DFG
.
getLiveIns
(
)
)
;
if
(
Trace
)
{
for
(
MachineBasicBlock
&
B
:
MF
)
{
std
::
vector
<
RegisterRef
>
LV
;
for
(
auto
I
=
B
.
livein_begin
(
)
,
E
=
B
.
livein_end
(
)
;
I
!=
E
;
++
I
)
LV
.
push_back
(
RegisterRef
(
I
->
PhysReg
,
I
->
LaneMask
)
)
;
llvm
::
sort
(
LV
.
begin
(
)
,
LV
.
end
(
)
)
;
dbgs
(
)
<<
printMBBReference
(
B
)
<<
<STR_LIT>
;
for
(
auto
I
:
LV
)
dbgs
(
)
<<
' '
<<
Print
<
RegisterRef
>
(
I
,
DFG
)
;
dbgs
(
)
<<
<STR_LIT>
;
LV
.
clear
(
)
;
const
RegisterAggr
&
LG
=
LiveMap
[
&
B
]
;
for
(
auto
I
=
LG
.
rr_begin
(
)
,
E
=
LG
.
rr_end
(
)
;
I
!=
E
;
++
I
)
LV
.
push_back
(
*
I
)
;
llvm
::
sort
(
LV
.
begin
(
)
,
LV
.
end
(
)
)
;
dbgs
(
)
<<
<STR_LIT>
;


<s> void Liveness :: emptify ( RefMap & M ) {

for ( auto I = M . begin ( ) , E = M . end ( ) ; I != E ; ) I = I -> second . empty ( ) ? M . erase ( I ) : std :: next ( I ) ;


<s> void Liveness :: emptify ( RefMap & M ) { for ( auto I = M . begin ( ) , E = M . end ( ) ; I != E ; ) I = I -> second . empty ( ) ? M . erase ( I ) : std :: next ( I ) ;


<s> return getAllReachedUses ( RefRR , DefA , NoRegs ) ;


<s> NodeSet getAllReachedUses ( RegisterRef RefRR , NodeAddr < DefNode * > DefA ) { return getAllReachedUses ( RefRR , DefA , NoRegs ) ;


<s> NodeList getAllReachingDefs ( RegisterRef RefRR , NodeAddr < RefNode * > RefA ) { return getAllReachingDefs ( RefRR , RefA , false , false , NoRegs ) ;


<s> RegisterAggr DefRRs ( PRI ) ; for ( NodeId D : Defs ) { const auto DA = DFG . addr < const DefNode * > ( D ) ; if ( ! ( DA . Addr -> getFlags ( ) & NodeAttrs :: PhiRef ) ) DefRRs . insert ( DA . Addr -> getRegRef ( DFG ) ) ; } NodeList RDs = getAllReachingDefs ( RefRR , RefA , false , true , DefRRs ) ; if ( RDs . empty ( ) ) return { Defs , true } ; NodeSet TmpDefs = Defs ; for ( NodeAddr < NodeBase * > R : RDs ) TmpDefs . insert ( R . Id ) ; NodeSet Result = Defs ; for ( NodeAddr < DefNode * > DA : RDs ) { Result . insert ( DA . Id ) ; if ( ! ( DA . Addr -> getFlags ( ) & NodeAttrs :: PhiRef ) ) continue ; NodeAddr < PhiNode * > PA = DA . Addr -> getOwner ( DFG ) ; if ( Visited . count ( PA . Id ) ) continue ; Visited . insert ( PA . Id ) ; for ( auto U : PA . Addr -> members_if ( DFG . IsRef < NodeAttrs :: Use > , DFG ) ) { const auto & T = getAllReachingDefsRecImpl ( RefRR , U , Visited , TmpDefs , Nest + <NUM_LIT> , MaxNest ) ; if ( ! T . second ) return { T . first , false } ; Result . insert ( T . first . begin ( ) , T . first . end ( ) ) ; } }


<s> auto F = NBMap . find ( RN ) ; if ( F != NBMap . end ( ) ) return F -> second ; llvm_unreachable ( <STR_LIT> ) ;


<s> const LiveMapType & getLiveMap ( ) const { return LiveMap ;


<s> if ( Clob . Id != <NUM_LIT> ) return Clob ; if ( Use . Id != <NUM_LIT> ) return Use ; } MachineBasicBlock * BB = BA . Addr -> getCode ( ) ; BA = NodeAddr < BlockNode * > ( ) ; if ( MachineDomTreeNode * N = MDT . getNode ( BB ) ) { if ( ( N = N -> getIDom ( ) ) ) BA = DFG . findBlock ( N -> getBlock ( ) ) ; } if ( ! BA . Id ) break ; Ins = BA . Addr -> members ( DFG ) ; B = Ins . rbegin ( ) ; E = Ins . rend ( ) ; } while ( true ) ; return NodeAddr < RefNode * > ( ) ;


<s> auto F = RealUseMap . find ( P ) ; return F == RealUseMap . end ( ) ? Empty : F -> second ;


<s> return F == RealUseMap . end ( ) ? Empty : F -> second ;


<s> LiveMapType ( const PhysicalRegisterInfo & pri ) : Empty ( pri ) {


<s> Liveness ( MachineRegisterInfo & mri , const DataFlowGraph & g ) : DFG ( g ) , TRI ( g . getTRI ( ) ) , PRI ( g . getPRI ( ) ) , MDT ( g . getDT ( ) ) , MDF ( g . getDF ( ) ) , LiveMap ( g . getPRI ( ) ) , NoRegs ( g . getPRI ( ) ) {


<s> do { LaneBitmask M = TRI . getSubRegIndexLaneMask ( S . getSubRegIndex ( ) ) ; if ( ( M & I . LaneMask ) . any ( ) ) LV . set ( S . getSubReg ( ) ) ; ++ S ; } while ( S . isValid ( ) ) ; } } ; BitVector LiveIn ( TRI . getNumRegs ( ) ) , Live ( TRI . getNumRegs ( ) ) ; CopyLiveIns ( B , LiveIn ) ; for ( auto SI : B -> successors ( ) ) CopyLiveIns ( SI , Live ) ; for ( auto I = B -> rbegin ( ) , E = B -> rend ( ) ; I != E ; ++ I ) { MachineInstr * MI = & * I ; if ( MI -> isDebugInstr ( ) ) continue ; MI -> clearKillInfo ( ) ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . isImplicit ( ) ) continue ; unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isPhysicalRegister ( R ) ) continue ; for ( MCSubRegIterator SR ( R , & TRI , true ) ; SR . isValid ( ) ; ++ SR ) Live . reset ( * SR ) ; }


<s> for ( auto I = B -> rbegin ( ) , E = B -> rend ( ) ; I != E ; ++ I ) { MachineInstr * MI = & * I ; if ( MI -> isDebugInstr ( ) ) continue ; MI -> clearKillInfo ( ) ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . isImplicit ( ) ) continue ; unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isPhysicalRegister ( R ) ) continue ; for ( MCSubRegIterator SR ( R , & TRI , true ) ; SR . isValid ( ) ; ++ SR ) Live . reset ( * SR ) ; } for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isUse ( ) || Op . isUndef ( ) ) continue ; unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isPhysicalRegister ( R ) ) continue ; bool IsLive = false ; for ( MCRegAliasIterator AR ( R , & TRI , true ) ; AR . isValid ( ) ; ++ AR ) { if ( ! Live [ * AR ] ) continue ; IsLive = true ; break ;


<s> for ( auto I = B . livein_begin ( ) , E = B . livein_end ( ) ; I != E ; ++ I ) T . push_back ( I -> PhysReg ) ;

for ( auto I : T ) B . removeLiveIn ( I ) ;


<s> std :: vector < unsigned > T ; for ( auto I = B . livein_begin ( ) , E = B . livein_end ( ) ; I != E ; ++ I ) T . push_back ( I -> PhysReg ) ; for ( auto I : T ) B . removeLiveIn ( I ) ; const RegisterAggr & LiveIns = LiveMap [ & B ] ; for ( auto I = LiveIns . rr_begin ( ) , E = LiveIns . rr_end ( ) ; I != E ; ++ I ) { RegisterRef R = * I ; B . addLiveIn ( { MCPhysReg ( R . Reg ) , R . Mask } ) ;


<s> LaneBitmask LA = PA . second & RA . Mask ; LaneBitmask LB = PB . second & RB . Mask ; if ( LA . any ( ) && LB . any ( ) ) { unsigned Root = * MCRegUnitRootIterator ( PA . first , & TRI ) ; uint32_t SubA = TRI . getSubRegIndex ( RA . Reg , Root ) ; uint32_t SubB = TRI . getSubRegIndex ( RB . Reg , Root ) ; const TargetRegisterClass * RC = RegInfos [ Root ] . RegClass ; LaneBitmask RCMask = RC != nullptr ? RC -> LaneMask : LaneBitmask ( <NUM_LIT> ) ; LaneBitmask MaskA = TRI . reverseComposeSubRegIndexLaneMask ( SubA , LA ) ; LaneBitmask MaskB = TRI . reverseComposeSubRegIndexLaneMask ( SubB , LB ) ; if ( ( MaskA & MaskB & RCMask ) . any ( ) ) return true ; } ++ UMA ; ++ UMB ; continue ; }


<s> unsigned Root = * MCRegUnitRootIterator ( PA . first , & TRI ) ; uint32_t SubA = TRI . getSubRegIndex ( RA . Reg , Root ) ; uint32_t SubB = TRI . getSubRegIndex ( RB . Reg , Root ) ; const TargetRegisterClass * RC = RegInfos [ Root ] . RegClass ; LaneBitmask RCMask = RC != nullptr ? RC -> LaneMask : LaneBitmask ( <NUM_LIT> ) ; LaneBitmask MaskA = TRI . reverseComposeSubRegIndexLaneMask ( SubA , LA ) ; LaneBitmask MaskB = TRI . reverseComposeSubRegIndexLaneMask ( SubB , LB ) ; if ( ( MaskA & MaskB & RCMask ) . any ( ) ) return true ; } ++ UMA ; ++ UMB ; continue ; } if ( PA . first < PB . first ) ++ UMA ; else if ( PB . first < PA . first ) ++ UMB ; }


<s> for ( unsigned i = <NUM_LIT> , e = PRI . getTRI ( ) . getNumRegs ( ) ; i != e ; ++ i ) { if ( MB [ i / <NUM_LIT> ] & ( <NUM_LIT> << ( i % <NUM_LIT> ) ) ) continue ; clear ( RegisterRef ( i , LaneBitmask :: getAll ( ) ) ) ; } return * this ; } RegisterRef NR = PRI . normalize ( RR ) ;


<s> clear ( RegisterRef ( i , LaneBitmask :: getAll ( ) ) ) ; } return * this ; } RegisterRef NR = PRI . normalize ( RR ) ; auto F = Masks . find ( NR . Reg ) ; if ( F == Masks . end ( ) ) return * this ; LaneBitmask NewM = F -> second & ~ NR . Mask ; if ( NewM . none ( ) ) Masks . erase ( F ) ;


<s> RegisterRef RegisterAggr :: clearIn ( RegisterRef RR ) const { RegisterAggr T ( PRI ) ;


<s> for ( unsigned i = <NUM_LIT> , e = PRI . getTRI ( ) . getNumRegs ( ) ; i != e ; ++ i ) { if ( MB [ i / <NUM_LIT> ] & ( <NUM_LIT> << ( i % <NUM_LIT> ) ) ) continue ; if ( hasAliasOf ( RegisterRef ( i , LaneBitmask :: getAll ( ) ) ) ) return true ; } } RegisterRef NR = PRI . normalize ( RR ) ; auto F = Masks . find ( NR . Reg ) ; if ( F != Masks . end ( ) ) { if ( ( F -> second & NR . Mask ) . any ( ) ) return true ;


<s> const uint32_t * MB = PRI . getRegMaskBits ( RR . Reg ) ; for ( unsigned i = <NUM_LIT> , e = PRI . getTRI ( ) . getNumRegs ( ) ; i != e ; ++ i ) { if ( MB [ i / <NUM_LIT> ] & ( <NUM_LIT> << ( i % <NUM_LIT> ) ) ) continue ; if ( ! hasCoverOf ( RegisterRef ( i , LaneBitmask :: getAll ( ) ) ) ) return false ; } return true ; } RegisterRef NR = PRI . normalize ( RR ) ;

if ( NR . Mask . none ( ) ) return true ;


<s> } RegisterRef NR = PRI . normalize ( RR ) ; auto F = Masks . find ( NR . Reg ) ; if ( F == Masks . end ( ) ) Masks . insert ( { NR . Reg , NR . Mask } ) ; else F -> second |= NR . Mask ; const TargetRegisterInfo & TRI = PRI . getTRI ( ) ; for ( MCRegUnitIterator U ( RR . Reg , & TRI ) ; U . isValid ( ) ; ++ U ) { MCRegUnitRootIterator R ( * U , & TRI ) ;


<s> if ( PhysicalRegisterInfo :: isRegMaskId ( RR . Reg ) ) return RR ; const TargetRegisterClass * RC = RegInfos [ RR . Reg ] . RegClass ; LaneBitmask RCMask = RC != nullptr ? RC -> LaneMask : LaneBitmask ( <NUM_LIT> ) ;

LaneBitmask Common = RR . Mask & RCMask ;


<s> RegInfo & RI = RegInfos [ R ] ; if ( RI . RegClass != nullptr && ! BadRC [ R ] ) { if ( RC -> LaneMask != RI . RegClass -> LaneMask ) { BadRC . set ( R ) ; RI . RegClass = nullptr ; } } else RI . RegClass = RC ; } } for ( MCPhysReg R = <NUM_LIT> , NR = TRI . getNumRegs ( ) ; R != NR ; ++ R ) { MCPhysReg SuperR = R ; for ( MCSuperRegIterator S ( R , & TRI , false ) ; S . isValid ( ) ; ++ S ) SuperR = * S ; RegInfos [ R ] . MaxSuper = SuperR ; } for ( const uint32_t * RM : TRI . getRegMasks ( ) ) RegMasks . insert ( RM ) ; for ( const MachineBasicBlock & B : mf ) for ( const MachineInstr & In : B ) for ( const MachineOperand & Op : In . operands ( ) ) if ( Op . isRegMask ( ) ) RegMasks . insert ( Op . getRegMask ( ) ) ;


for
(
auto
I
:
Masks
)
OS
<<
' '
<<
PrintReg
(
I
.
first
,
&
PRI
.
getTRI
(
)
)
<<
PrintLaneMaskOpt
(
I
.
second
)
;


<s> RegisterAggr ( const PhysicalRegisterInfo & pri ) : ExpAliasUnits ( pri . getTRI ( ) . getNumRegUnits ( ) ) , PRI ( pri ) {


<s> const BitVector & getMaskUnits ( RegisterId MaskId ) const { return MaskInfos [ Register :: stackSlot2Index ( MaskId ) ] . Units ;


<s> static bool isRegMaskId ( RegisterId R ) { return Register :: isStackSlot ( R ) ;


<s>
for
(
int
U
=
Units
.
find_first
(
)
;
U
>=
<NUM_LIT>
;
U
=
Units
.
find_next
(
U
)
)
OS
<<
' '
<<
PrintRegUnit
(
U
,
&
PRI
.
getTRI
(
)
)
;


<s> uint32_t SubA = TRI . getSubRegIndex ( RA . Reg , Root ) ; uint32_t SubB = TRI . getSubRegIndex ( RB . Reg , Root ) ; const TargetRegisterClass * RC = RegInfos [ Root ] . RegClass ; LaneBitmask RCMask = RC != nullptr ? RC -> LaneMask : LaneBitmask ( <NUM_LIT> ) ; LaneBitmask MaskA = TRI . reverseComposeSubRegIndexLaneMask ( SubA , LA ) ; LaneBitmask MaskB = TRI . reverseComposeSubRegIndexLaneMask ( SubB , LB ) ; if ( ( MaskA & MaskB & RCMask ) . any ( ) ) return true ; } ++ UMA ;


<s> if ( ( F -> second & NR . Mask ) . any ( ) ) return true ; } if ( CheckUnits ) { for ( MCRegUnitIterator U ( RR . Reg , & PRI . getTRI ( ) ) ; U . isValid ( ) ; ++ U ) if ( ExpAliasUnits . test ( * U ) ) return true ; } return false ;


<s> RegisterRef NR = normalize ( RR ) ; auto F = Masks . find ( NR . Reg ) ; if ( F != Masks . end ( ) ) { if ( ( F -> second & NR . Mask ) . any ( ) ) return true ; } if ( CheckUnits ) {

for ( MCRegUnitIterator U ( RR . Reg , & PRI . getTRI ( ) ) ; U . isValid ( ) ; ++ U ) if ( ExpAliasUnits . test ( * U ) ) return true ;


<s> const TargetRegisterInfo & TRI = PRI . getTRI ( ) ; for ( MCRegUnitIterator U ( RR . Reg , & TRI ) ; U . isValid ( ) ; ++ U ) { MCRegUnitRootIterator R ( * U , & TRI ) ; ++ R ;


<s> RegisterAggr & RegisterAggr :: insert ( RegisterRef RR ) { RegisterRef NR = normalize ( RR ) ; auto F = Masks . find ( NR . Reg ) ; if ( F == Masks . end ( ) ) Masks . insert ( { NR . Reg , NR . Mask } ) ; else F -> second |= NR . Mask ; const TargetRegisterInfo & TRI = PRI . getTRI ( ) ; for ( MCRegUnitIterator U ( RR . Reg , & TRI ) ; U . isValid ( ) ; ++ U ) { MCRegUnitRootIterator R ( * U , & TRI ) ; ++ R ; if ( ! R . isValid ( ) ) continue ; ExpAliasUnits . set ( * U ) ;


<s> LaneBitmask Common = RR . Mask & RCMask ; RegisterId SuperReg = PRI . RegInfos [ RR . Reg ] . MaxSuper ; uint32_t Sub = PRI . getTRI ( ) . getSubRegIndex ( SuperReg , RR . Reg ) ; LaneBitmask SuperMask = PRI . getTRI ( ) . composeSubRegIndexLaneMask ( Sub , Common ) ;

return RegisterRef ( SuperReg , SuperMask ) ;


<s> if ( RI . RegClass != nullptr && ! BadRC [ R ] ) { if ( RC -> LaneMask != RI . RegClass -> LaneMask ) { BadRC . set ( R ) ; RI . RegClass = nullptr ; } } else RI . RegClass = RC ; } }

for ( MCPhysReg R = <NUM_LIT> , NR = TRI . getNumRegs ( ) ; R != NR ; ++ R ) {


<s> } RegisterRef NR = PRI . normalize ( RR ) ; auto F = Masks . find ( NR . Reg ) ; if ( F != Masks . end ( ) ) { if ( ( F -> second & NR . Mask ) . any ( ) ) return true ; } if ( CheckUnits || PRI . hasPartialOverlaps ( NR . Reg ) ) { for ( MCRegUnitMaskIterator U ( RR . Reg , & PRI . getTRI ( ) ) ; U . isValid ( ) ; ++ U ) {

std :: pair < RegisterId , LaneBitmask > P = * U ;


<s> if ( PhysicalRegisterInfo :: isRegMaskId ( RR . Reg ) ) { const uint32_t * MB = PRI . getRegMaskBits ( RR . Reg ) ; for ( unsigned i = <NUM_LIT> , e = PRI . getTRI ( ) . getNumRegs ( ) ; i != e ; ++ i ) { if ( MB [ i / <NUM_LIT> ] & ( <NUM_LIT> << ( i % <NUM_LIT> ) ) ) continue ; if ( ! hasCoverOf ( RegisterRef ( i , LaneBitmask :: getAll ( ) ) ) ) return false ; } return true ; } RegisterRef NR = PRI . normalize ( RR ) ; if ( NR . Mask . none ( ) ) return true ; auto F = Masks . find ( NR . Reg ) ; if ( F != Masks . end ( ) ) {

if ( ( NR . Mask & F -> second ) == NR . Mask ) return true ;


<s> return true ; } RegisterRef NR = PRI . normalize ( RR ) ; if ( NR . Mask . none ( ) ) return true ; auto F = Masks . find ( NR . Reg ) ; if ( F != Masks . end ( ) ) { if ( ( NR . Mask & F -> second ) == NR . Mask ) return true ; } if ( CheckUnits || PRI . hasPartialOverlaps ( NR . Reg ) ) { for ( MCRegUnitMaskIterator U ( RR . Reg , & PRI . getTRI ( ) ) ; U . isValid ( ) ; ++ U ) { std :: pair < RegisterId , LaneBitmask > P = * U ; if ( P . second . none ( ) || ( P . second & RR . Mask ) . any ( ) ) if ( ! ExpUnits . test ( P . first ) ) return false ; } return true ;


<s> if ( PRI . hasPartialOverlaps ( NR . Reg ) ) { for ( MCRegUnitMaskIterator U ( RR . Reg , & PRI . getTRI ( ) ) ; U . isValid ( ) ; ++ U ) { std :: pair < RegisterId , LaneBitmask > P = * U ; if ( P . second . none ( ) || ( P . second & RR . Mask ) . none ( ) ) continue ; ExpUnits . set ( P . first ) ;


<s> RegisterId SuperReg = RegInfos [ RR . Reg ] . MaxSuper ; if ( RR . Reg == SuperReg ) return RR ; const TargetRegisterClass * RC = RegInfos [ RR . Reg ] . RegClass ; LaneBitmask RCMask = RC != nullptr ? RC -> LaneMask : LaneBitmask ( <NUM_LIT> ) ; LaneBitmask Common = RR . Mask & RCMask ; uint32_t Sub = TRI . getSubRegIndex ( SuperReg , RR . Reg ) ; LaneBitmask SuperMask = TRI . composeSubRegIndexLaneMask ( Sub , Common ) ; assert ( RR . Mask . none ( ) || SuperMask . any ( ) ) ; return RegisterRef ( SuperReg , SuperMask ) ;


<s> if ( RI . RegClass != nullptr && ! BadRC [ R ] ) { if ( RC -> LaneMask != RI . RegClass -> LaneMask ) { BadRC . set ( R ) ; RI . RegClass = nullptr ; } } else RI . RegClass = RC ; } } auto HasPartialOverlaps = [ this ] ( uint32_t Reg ) -> bool { for ( MCRegAliasIterator A ( Reg , & TRI , false ) ; A . isValid ( ) ; ++ A ) if ( ! TRI . isSubRegister ( Reg , * A ) && ! TRI . isSubRegister ( * A , Reg ) ) return true ;


<s> bool PhysicalRegisterInfo :: aliasRM ( RegisterRef RR , RegisterRef RM ) const { assert ( Register :: isPhysicalRegister ( RR . Reg ) && isRegMaskId ( RM . Reg ) ) ; const uint32_t * MB = getRegMaskBits ( RM . Reg ) ; bool Preserved = MB [ RR . Reg / <NUM_LIT> ] & ( <NUM_LIT> << ( RR . Reg % <NUM_LIT> ) ) ; if ( RR . Mask == LaneBitmask :: getAll ( ) ) return ! Preserved ; const TargetRegisterClass * RC = RegInfos [ RR . Reg ] . RegClass ; if ( RC != nullptr && ( RR . Mask & RC -> LaneMask ) == RC -> LaneMask ) return ! Preserved ; LaneBitmask M = RR . Mask ; for ( MCSubRegIndexIterator SI ( RR . Reg , & TRI ) ; SI . isValid ( ) ; ++ SI ) { LaneBitmask SM = TRI . getSubRegIndexLaneMask ( SI . getSubRegIndex ( ) ) ; if ( ( SM & RR . Mask ) . none ( ) ) continue ; unsigned SR = SI . getSubReg ( ) ; if ( ! ( MB [ SR / <NUM_LIT> ] & ( <NUM_LIT> << ( SR % <NUM_LIT> ) ) ) ) continue ; M &= ~ SM ; if ( M . none ( ) ) return false ;


<s> MCRegUnitMaskIterator UMB ( RB . Reg , & TRI ) ; while ( UMA . isValid ( ) && UMB . isValid ( ) ) { std :: pair < RegisterId , LaneBitmask > PA = * UMA ; if ( PA . second . any ( ) && ( PA . second & RA . Mask ) . none ( ) ) { ++ UMA ; continue ; } std :: pair < RegisterId , LaneBitmask > PB = * UMB ; if ( PB . second . any ( ) && ( PB . second & RB . Mask ) . none ( ) ) { ++ UMB ; continue ;


<s> } return AS ; } for ( MCRegAliasIterator AI ( Reg , & TRI , false ) ; AI . isValid ( ) ; ++ AI ) AS . insert ( * AI ) ; for ( const uint32_t * RM : RegMasks ) { RegisterId MI = getRegMaskId ( RM ) ; if ( aliasRM ( RegisterRef ( Reg ) , RegisterRef ( MI ) ) ) AS . insert ( MI ) ; } return AS ;


<s> std :: set < RegisterId > PhysicalRegisterInfo :: getAliasSet ( RegisterId Reg ) const { std :: set < RegisterId > AS ; assert ( isRegMaskId ( Reg ) || Register :: isPhysicalRegister ( Reg ) ) ; if ( isRegMaskId ( Reg ) ) { const uint32_t * MB = getRegMaskBits ( Reg ) ; for ( unsigned i = <NUM_LIT> , e = TRI . getNumRegs ( ) ; i != e ; ++ i ) { if ( MB [ i / <NUM_LIT> ] & ( <NUM_LIT> << ( i % <NUM_LIT> ) ) ) continue ; AS . insert ( i ) ; } for ( const uint32_t * RM : RegMasks ) { RegisterId MI = getRegMaskId ( RM ) ; if ( MI != Reg && aliasMM ( RegisterRef ( Reg ) , RegisterRef ( MI ) ) ) AS . insert ( MI ) ; } return AS ; } for ( MCRegAliasIterator AI ( Reg , & TRI , false ) ; AI . isValid ( ) ; ++ AI ) AS . insert ( * AI ) ;


<s> bool hasPartialOverlaps ( RegisterId Reg ) const { return RegInfos [ Reg ] . Partial ;


<s> RegisterAggr ( const PhysicalRegisterInfo & pri ) : ExpUnits ( pri . getTRI ( ) . getNumRegUnits ( ) ) , PRI ( pri ) {


<s> return ! isRegMaskId ( RB . Reg ) ? aliasRM ( RB , RA ) : aliasMM ( RA , RB ) ;


<s> if ( ! isRegMaskId ( RA . Reg ) ) return ! isRegMaskId ( RB . Reg ) ? aliasRR ( RA , RB ) : aliasRM ( RA , RB ) ;

return ! isRegMaskId ( RB . Reg ) ? aliasRM ( RB , RA ) : aliasMM ( RA , RB ) ;


<s> if ( w == <NUM_LIT> ) C &= ~ <NUM_LIT> ; if ( C ) return true ; } unsigned TailRegs = NumRegs % <NUM_LIT> ; if ( TailRegs == <NUM_LIT> ) return false ; unsigned TW = NumRegs / <NUM_LIT> ; uint32_t TailMask = ( <NUM_LIT> << TailRegs ) - <NUM_LIT> ; if ( ~ BM [ TW ] & ~ BN [ TW ] & TailMask ) return true ;


<s> assert ( isRegMaskId ( RM . Reg ) && isRegMaskId ( RN . Reg ) ) ; unsigned NumRegs = TRI . getNumRegs ( ) ; const uint32_t * BM = getRegMaskBits ( RM . Reg ) ; const uint32_t * BN = getRegMaskBits ( RN . Reg ) ; for ( unsigned w = <NUM_LIT> , nw = NumRegs / <NUM_LIT> ; w != nw ; ++ w ) { uint32_t C = ~ BM [ w ] & ~ BN [ w ] ; if ( w == <NUM_LIT> ) C &= ~ <NUM_LIT> ;


<s> for ( MCSubRegIndexIterator SI ( RR . Reg , & TRI ) ; SI . isValid ( ) ; ++ SI ) { LaneBitmask SM = TRI . getSubRegIndexLaneMask ( SI . getSubRegIndex ( ) ) ; if ( ( SM & RR . Mask ) . none ( ) ) continue ; unsigned SR = SI . getSubReg ( ) ; if ( ! ( MB [ SR / <NUM_LIT> ] & ( <NUM_LIT> << ( SR % <NUM_LIT> ) ) ) ) continue ; M &= ~ SM ; if ( M . none ( ) ) return false ;


<s> for ( MCSubRegIndexIterator SI ( RR . Reg , & TRI ) ; SI . isValid ( ) ; ++ SI ) { LaneBitmask SM = TRI . getSubRegIndexLaneMask ( SI . getSubRegIndex ( ) ) ; if ( ( SM & RR . Mask ) . none ( ) ) continue ; unsigned SR = SI . getSubReg ( ) ; if ( ! ( MB [ SR / <NUM_LIT> ] & ( <NUM_LIT> << ( SR % <NUM_LIT> ) ) ) ) continue ; M &= ~ SM ; if ( M . none ( ) ) return false ; }


<s> return RegisterAggr ( PRI ) . insert ( RR ) . clear ( * this ) . makeRegRef ( ) ;


<s> bool empty ( ) const { return Units . none ( ) ;


<s> uint32_t find ( T Val ) const { auto F = llvm :: find ( Map , Val ) ; assert ( F != Map . end ( ) ) ; return F - Map . begin ( ) + <NUM_LIT> ;


<s> if ( isRegMaskId ( Reg ) ) { const uint32_t * MB = getRegMaskBits ( Reg ) ; for ( unsigned i = <NUM_LIT> , e = TRI . getNumRegs ( ) ; i != e ; ++ i ) { if ( MB [ i / <NUM_LIT> ] & ( <NUM_LIT> << ( i % <NUM_LIT> ) ) ) continue ; AS . insert ( i ) ; } for ( const uint32_t * RM : RegMasks ) { RegisterId MI = getRegMaskId ( RM ) ; if ( MI != Reg && aliasMM ( RegisterRef ( Reg ) , RegisterRef ( MI ) ) ) AS . insert ( MI ) ; } return AS ; } for ( MCRegAliasIterator AI ( Reg , & TRI , false ) ; AI . isValid ( ) ; ++ AI ) AS . insert ( * AI ) ;


<s> const BitVector & getMaskUnits ( RegisterId MaskId ) const {

return MaskInfos [ TargetRegisterInfo :: stackSlot2Index ( MaskId ) ] . Units ;


<s> return MaskInfos [ TargetRegisterInfo :: stackSlot2Index ( MaskId ) ] . Units ;


<s> return RegisterRef ( UnitInfos [ U ] . Reg , UnitInfos [ U ] . Mask ) ;


<s> RegisterRef getRefForUnit ( uint32_t U ) const {

return RegisterRef ( UnitInfos [ U ] . Reg , UnitInfos [ U ] . Mask ) ;


<s> const uint32_t * getRegMaskBits ( RegisterId R ) const {

return RegMasks . get ( TargetRegisterInfo :: stackSlot2Index ( R ) ) ;


<s> return TargetRegisterInfo :: index2StackSlot ( RegMasks . find ( RM ) ) ;


<s> RegisterId getRegMaskId ( const uint32_t * RM ) const {

return TargetRegisterInfo :: index2StackSlot ( RegMasks . find ( RM ) ) ;


<s> if ( P . second . none ( ) || ( P . second & RR . Mask ) . any ( ) ) if ( Units . test ( P . first ) ) return true ;


<s> if ( PhysicalRegisterInfo :: isRegMaskId ( RR . Reg ) ) return Units . anyCommon ( PRI . getMaskUnits ( RR . Reg ) ) ;

for ( MCRegUnitMaskIterator U ( RR . Reg , & PRI . getTRI ( ) ) ; U . isValid ( ) ; ++ U ) {


<s> BitVector T ( PRI . getMaskUnits ( RR . Reg ) ) ; return T . reset ( Units ) . none ( ) ; } for ( MCRegUnitMaskIterator U ( RR . Reg , & PRI . getTRI ( ) ) ; U . isValid ( ) ; ++ U ) { std :: pair < uint32_t , LaneBitmask > P = * U ; if ( P . second . none ( ) || ( P . second & RR . Mask ) . any ( ) ) if ( ! Units . test ( P . first ) ) return false ; }


<s> return T . reset ( Units ) . none ( ) ; } for ( MCRegUnitMaskIterator U ( RR . Reg , & PRI . getTRI ( ) ) ; U . isValid ( ) ; ++ U ) { std :: pair < uint32_t , LaneBitmask > P = * U ; if ( P . second . none ( ) || ( P . second & RR . Mask ) . any ( ) ) if ( ! Units . test ( P . first ) ) return false ; }


<s> IndexedSet ( ) { Map . reserve ( N ) ;


<s> RegisterAggr & RegisterAggr :: insert ( const RegisterAggr & RG ) { Units |= RG . Units ; return * this ;


<s> RegisterAggr & RegisterAggr :: insert ( const RegisterAggr & RG ) {


<s> Units &= RG . Units ; return * this ;


<s> RegisterAggr T ( PRI ) ; T . insert ( RR ) . intersect ( * this ) ; if ( T . empty ( ) ) return RegisterRef ( ) ; RegisterRef NR = T . makeRegRef ( ) ; assert ( NR ) ; return NR ;


<s> return RegisterAggr ( PRI ) . insert ( RA ) . hasCoverOf ( RB ) ;


<s> return TargetRegisterInfo :: isStackSlot ( R ) ;


<s> for ( MCRegUnitRootIterator R ( Unit , & PRI . getTRI ( ) ) ; R . isValid ( ) ; ++ R ) for ( MCSuperRegIterator S ( * R , & PRI . getTRI ( ) , true ) ; S . isValid ( ) ; ++ S ) Regs . set ( * S ) ; } ; BitVector Regs ( PRI . getTRI ( ) . getNumRegs ( ) ) ; AliasedRegs ( U , Regs ) ; U = Units . find_next ( U ) ; while ( U >= <NUM_LIT> ) { BitVector AR ( PRI . getTRI ( ) . getNumRegs ( ) ) ; AliasedRegs ( U , AR ) ; Regs &= AR ; U = Units . find_next ( U ) ; } int F = Regs . find_first ( ) ; if ( F <= <NUM_LIT> ) return RegisterRef ( ) ; LaneBitmask M ; for ( MCRegUnitMaskIterator I ( F , & PRI . getTRI ( ) ) ; I . isValid ( ) ; ++ I ) {

std :: pair < uint32_t , LaneBitmask > P = * I ;


<s> const RegInfo & RI = RegInfos [ R ] ; LaneBitmask RCM = RI . RegClass ? RI . RegClass -> LaneMask : LaneBitmask :: getAll ( ) ; LaneBitmask M = TRI . reverseComposeSubRegIndexLaneMask ( Idx , RR . Mask ) ; return RegisterRef ( R , M & RCM ) ; }


<s> RegisterRef PhysicalRegisterInfo :: normalize ( RegisterRef RR ) const {


<s> } } UnitInfos . resize ( TRI . getNumRegUnits ( ) ) ; for ( uint32_t U = <NUM_LIT> , NU = TRI . getNumRegUnits ( ) ; U != NU ; ++ U ) { if ( UnitInfos [ U ] . Reg != <NUM_LIT> ) continue ; MCRegUnitRootIterator R ( U , & TRI ) ; assert ( R . isValid ( ) ) ; RegisterId F = * R ; ++ R ; if ( R . isValid ( ) ) { UnitInfos [ U ] . Mask = LaneBitmask :: getAll ( ) ; UnitInfos [ U ] . Reg = F ; } else { for ( MCRegUnitMaskIterator I ( F , & TRI ) ; I . isValid ( ) ; ++ I ) { std :: pair < uint32_t , LaneBitmask > P = * I ; UnitInfo & UI = UnitInfos [ P . first ] ; UI . Reg = F ; if ( P . second . any ( ) ) {


<s> if ( UnitInfos [ U ] . Reg != <NUM_LIT> ) continue ; MCRegUnitRootIterator R ( U , & TRI ) ; assert ( R . isValid ( ) ) ; RegisterId F = * R ; ++ R ; if ( R . isValid ( ) ) { UnitInfos [ U ] . Mask = LaneBitmask :: getAll ( ) ; UnitInfos [ U ] . Reg = F ; } else { for ( MCRegUnitMaskIterator I ( F , & TRI ) ; I . isValid ( ) ; ++ I ) { std :: pair < uint32_t , LaneBitmask > P = * I ; UnitInfo & UI = UnitInfos [ P . first ] ; UI . Reg = F ; if ( P . second . any ( ) ) { UI . Mask = P . second ; } else { if ( const TargetRegisterClass * RC = RegInfos [ F ] . RegClass ) UI . Mask = RC -> LaneMask ; else UI . Mask = LaneBitmask :: getAll ( ) ; } } } } for ( const uint32_t * RM : TRI . getRegMasks ( ) ) RegMasks . insert ( RM ) ; for ( const MachineBasicBlock & B : mf ) for ( const MachineInstr & In : B ) for ( const MachineOperand & Op : In . operands ( ) ) if ( Op . isRegMask ( ) ) RegMasks . insert ( Op . getRegMask ( ) ) ; MaskInfos . resize ( RegMasks . size ( ) + <NUM_LIT> ) ; for ( uint32_t M = <NUM_LIT> , NM = RegMasks . size ( ) ; M <= NM ; ++ M ) { BitVector PU ( TRI . getNumRegUnits ( ) ) ; const uint32_t * MB = RegMasks . get ( M ) ; for ( unsigned i = <NUM_LIT> , e = TRI . getNumRegs ( ) ; i != e ; ++ i ) { if ( ! ( MB [ i / <NUM_LIT> ] & ( <NUM_LIT> << ( i % <NUM_LIT> ) ) ) ) continue ; for ( MCRegUnitIterator U ( i , & TRI ) ; U . isValid ( ) ; ++ U ) PU . set ( * U ) ; } MaskInfos [ M ] . Units = PU . flip ( ) ; }


<s>
void
RegisterAggr
::
print
(
raw_ostream
&
OS
)
const
{
OS
<<
'{'
;
for
(
int
U
=
Units
.
find_first
(
)
;
U
>=
<NUM_LIT>
;
U
=
Units
.
find_next
(
U
)
)
OS
<<
' '
<<
printRegUnit
(
U
,
&
PRI
.
getTRI
(
)
)
;
OS
<<
<STR_LIT>
;


<s>
for
(
int
U
=
Units
.
find_first
(
)
;
U
>=
<NUM_LIT>
;
U
=
Units
.
find_next
(
U
)
)
OS
<<
' '
<<
printRegUnit
(
U
,
&
PRI
.
getTRI
(
)
)
;


<s> RegisterAggr ( const PhysicalRegisterInfo & pri ) : Units ( pri . getTRI ( ) . getNumRegUnits ( ) ) , PRI ( pri ) {


<s> return rr_iterator ( * this , false ) ;


<s> return rr_iterator ( * this , true ) ;