<s> if ( LS1 . properties ( ) & ConstantProperties :: Zero ) { const Constant * C = intToConst ( A2 ) ; Result . add ( C ) ; return ! Result . isBottom ( ) ; } return false ; } APInt A , XA ; for ( unsigned i = <NUM_LIT> ; i < LS1 . size ( ) ; ++ i ) { bool Eval = constToInt ( LS1 . Values [ i ] , A ) && evaluateXORii ( A , A2 , XA ) ; if ( ! Eval ) return false ; const Constant * C = intToConst ( XA ) ; Result . add ( C ) ; }


<s> if ( ! getCell ( R1 , Inputs , LS1 ) ) return false ; if ( LS1 . isProperty ( ) ) { if ( LS1 . properties ( ) & ConstantProperties :: Zero ) { const Constant * C = intToConst ( A2 ) ; Result . add ( C ) ; return ! Result . isBottom ( ) ; } return false ; }


<s> if ( LS1 . isProperty ( ) ) { if ( LS1 . properties ( ) & ConstantProperties :: Zero ) return ! ( Result = LS2 ) . isBottom ( ) ; return false ; } if ( LS2 . isProperty ( ) ) { if ( LS2 . properties ( ) & ConstantProperties :: Zero ) return ! ( Result = LS1 ) . isBottom ( ) ; return false ; } APInt A ; for ( unsigned i = <NUM_LIT> ; i < LS2 . size ( ) ; ++ i ) { LatticeCell RC ; bool Eval = constToInt ( LS2 . Values [ i ] , A ) && evaluateXORri ( R1 , A , Inputs , RC ) ; if ( ! Eval ) return false ; Result . meet ( RC ) ;


<s> assert ( Width >= Bits && BW >= Bits ) ; APInt Mask = APInt :: getLowBitsSet ( Width , Bits ) ; Result = A1 . zextOrTrunc ( Width ) & Mask ; return true ;


<s> ( void ) BW ; assert ( Width >= Bits && BW >= Bits ) ; APInt Mask = APInt :: getLowBitsSet ( Width , Bits ) ; Result = A1 . zextOrTrunc ( Width ) & Mask ; return true ;


<s> if ( ! getCell ( R1 , Inputs , LS1 ) ) return false ; if ( LS1 . isProperty ( ) ) return false ; APInt A , XA ;

for ( unsigned i = <NUM_LIT> ; i < LS1 . size ( ) ; ++ i ) {


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) return Bottom ;

MapType :: const_iterator F = Map . find ( R ) ;


<s> MapType :: const_iterator F = Map . find ( R ) ; if ( F != Map . end ( ) ) return F -> second ; return Top ;


<s> return ! RC . isBottom ( ) ; } bool Eval = evaluate ( R , L , RC ) ;


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( R . Reg ) ) return false ; const LatticeCell & L = Inputs . get ( R . Reg ) ;


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) return <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return <NUM_LIT> ;


<s> unsigned <ISA_LIT>ConstEvaluator :: getRegBitWidth ( unsigned Reg ) const { const TargetRegisterClass * RC = MRI -> getRegClass ( Reg ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return <NUM_LIT> ; llvm_unreachable ( <STR_LIT> ) ; return <NUM_LIT> ;


<s> bool has ( unsigned R ) const { if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) return true ; MapType :: const_iterator F = Map . find ( R ) ; return F != Map . end ( ) ;


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) return true ; MapType :: const_iterator F = Map . find ( R ) ; return F != Map . end ( ) ;


<s> <ISA_LIT>ConstEvaluator :: <ISA_LIT>ConstEvaluator ( MachineFunction & Fn ) : MachineConstEvaluator ( Fn ) , HII ( * Fn . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ) , HRI ( * Fn . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ) { MRI = & Fn . getRegInfo ( ) ;


<s> PassRegistry & Registry = * PassRegistry :: getPassRegistry ( ) ;

initialize<ISA_LIT>ConstPropagationPass ( Registry ) ;


<s> for ( unsigned i = <NUM_LIT> ; i < MaxCellSize ; ++ i ) Values [ i ] = <NUM_LIT> ;


<s> MachineConstEvaluator ( MachineFunction & Fn ) : TRI ( * Fn . getSubtarget ( ) . getRegisterInfo ( ) ) , MF ( Fn ) , CX ( Fn . getFunction ( ) -> getContext ( ) ) {


<s> return true ; } if ( L . isProperty ( ) ) return add ( L . properties ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < L . size ( ) ; ++ i ) {

const Constant * LC = L . Values [ i ] ;


<s> assert ( ( Cmp & ( L | G ) ) != ( L | G ) ) ; return Cmp ^ ( L | G ) ;


<s> if ( Ps & ConstantProperties :: NaN ) os << <STR_LIT> ; if ( Ps & ConstantProperties :: PosOrZero ) os << <STR_LIT> ; if ( Ps & ConstantProperties :: NegOrZero ) os << <STR_LIT> ; os << '}' ; return ; } os << <STR_LIT> ; if ( isBottom ( ) ) { os << <STR_LIT> ; } else if ( isTop ( ) ) { os << <STR_LIT> ; } else { for ( unsigned i = <NUM_LIT> ; i < size ( ) ; ++ i ) { const Constant * C = Values [ i ] ;


<s> if ( isProperty ( ) ) { os << <STR_LIT> ; uint32_t Ps = properties ( ) ; if ( Ps & ConstantProperties :: Zero ) os << <STR_LIT> ; if ( Ps & ConstantProperties :: NonZero ) os << <STR_LIT> ; if ( Ps & ConstantProperties :: Finite ) os << <STR_LIT> ; if ( Ps & ConstantProperties :: Infinity ) os << <STR_LIT> ; if ( Ps & ConstantProperties :: NaN ) os << <STR_LIT> ; if ( Ps & ConstantProperties :: PosOrZero ) os << <STR_LIT> ; if ( Ps & ConstantProperties :: NegOrZero ) os << <STR_LIT> ; os << '}' ; return ; } os << <STR_LIT> ; if ( isBottom ( ) ) { os << <STR_LIT> ; } else if ( isTop ( ) ) { os << <STR_LIT> ; } else { for ( unsigned i = <NUM_LIT> ; i < size ( ) ; ++ i ) { const Constant * C = Values [ i ] ; if ( i != <NUM_LIT> ) os << <STR_LIT> ; C -> print ( os ) ; } }


<s> unsigned EntryNum = Entry -> getNumber ( ) ; FlowQ . push ( CFGEdge ( EntryNum , EntryNum ) ) ; while ( ! FlowQ . empty ( ) ) { CFGEdge Edge = FlowQ . front ( ) ; FlowQ . pop ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << Edge . first << <STR_LIT> << Edge . second << '\n' ) ; if ( Edge . first != EntryNum ) if ( EdgeExec . count ( Edge ) ) continue ; EdgeExec . insert ( Edge ) ; MachineBasicBlock * SB = MF . getBlockNumbered ( Edge . second ) ; MachineBasicBlock :: const_iterator It = SB -> begin ( ) , End = SB -> end ( ) ; while ( It != End && It -> isPHI ( ) ) { InstrExec . insert ( & * It ) ; visitPHI ( * It ) ; ++ It ; } while ( It != End && It -> isDebugValue ( ) ) ++ It ; assert ( It == End || ! It -> isPHI ( ) ) ; if ( It != End && InstrExec . count ( & * It ) ) continue ; while ( It != End && ! It -> isBranch ( ) ) { if ( ! It -> isDebugValue ( ) ) { InstrExec . insert ( & * It ) ; visitNonBranch ( * It ) ; } ++ It ; } if ( It != End ) { visitBranchesFrom ( * It ) ; } else { unsigned SBN = SB -> getNumber ( ) ; for ( const MachineBasicBlock * SSB : SB -> successors ( ) ) FlowQ . push ( CFGEdge ( SBN , SSB -> getNumber ( ) ) ) ;


<s> CFGEdge Edge = FlowQ . front ( ) ; FlowQ . pop ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << Edge . first << <STR_LIT> << Edge . second << '\n' ) ; if ( Edge . first != EntryNum ) if ( EdgeExec . count ( Edge ) ) continue ; EdgeExec . insert ( Edge ) ; MachineBasicBlock * SB = MF . getBlockNumbered ( Edge . second ) ; MachineBasicBlock :: const_iterator It = SB -> begin ( ) , End = SB -> end ( ) ; while ( It != End && It -> isPHI ( ) ) { InstrExec . insert ( & * It ) ; visitPHI ( * It ) ; ++ It ; } while ( It != End && It -> isDebugValue ( ) ) ++ It ; assert ( It == End || ! It -> isPHI ( ) ) ; if ( It != End && InstrExec . count ( & * It ) ) continue ; while ( It != End && ! It -> isBranch ( ) ) { if ( ! It -> isDebugValue ( ) ) { InstrExec . insert ( & * It ) ; visitNonBranch ( * It ) ; } ++ It ; } if ( It != End ) { visitBranchesFrom ( * It ) ; } else { unsigned SBN = SB -> getNumber ( ) ; for ( const MachineBasicBlock * SSB : SB -> successors ( ) ) FlowQ . push ( CFGEdge ( SBN , SSB -> getNumber ( ) ) ) ; } } DEBUG ( { dbgs ( ) << <STR_LIT> ; Cells . print ( dbgs ( ) , MCE . TRI ) ; dbgs ( ) << <STR_LIT> ; for ( const MachineBasicBlock & B : MF ) { unsigned BN = B . getNumber ( ) ;

for ( const MachineBasicBlock * SB : B . successors ( ) ) {


<s> if ( isProperty ( ) ) return Properties ; assert ( ! isTop ( ) && <STR_LIT> ) ; if ( isBottom ( ) ) return ConstantProperties :: Unknown ; assert ( size ( ) > <NUM_LIT> && <STR_LIT> ) ; uint32_t Ps = ConstantProperties :: deduce ( Values [ <NUM_LIT> ] ) ;

for ( unsigned i = <NUM_LIT> ; i < size ( ) ; ++ i ) {


<s> for ( unsigned i = <NUM_LIT> ; i < size ( ) ; ++ i ) { if ( Ps == ConstantProperties :: Unknown ) break ; Ps &= ConstantProperties :: deduce ( Values [ i ] ) ; }


<s> explicit Register ( const MachineOperand & MO ) : Reg ( MO . getReg ( ) ) , SubReg ( MO . getSubReg ( ) ) {


<s> for ( auto I = To -> begin ( ) , E = To -> getFirstNonPHI ( ) ; I != E ; ++ I ) { MachineInstr * PN = & * I ; int N = PN -> getNumOperands ( ) - <NUM_LIT> ; while ( N > <NUM_LIT> ) { if ( PN -> getOperand ( N + <NUM_LIT> ) . getMBB ( ) == From ) { PN -> RemoveOperand ( N + <NUM_LIT> ) ; PN -> RemoveOperand ( N ) ; } N -= <NUM_LIT> ; } }


<s> void MachineConstPropagator :: removeCFGEdge ( MachineBasicBlock * From , MachineBasicBlock * To ) { From -> removeSuccessor ( To ) ; for ( auto I = To -> begin ( ) , E = To -> getFirstNonPHI ( ) ; I != E ; ++ I ) { MachineInstr * PN = & * I ; int N = PN -> getNumOperands ( ) - <NUM_LIT> ; while ( N > <NUM_LIT> ) { if ( PN -> getOperand ( N + <NUM_LIT> ) . getMBB ( ) == From ) { PN -> RemoveOperand ( N + <NUM_LIT> ) ; PN -> RemoveOperand ( N ) ; } N -= <NUM_LIT> ;


<s> MI . setDesc ( HII . get ( <STR_LIT> ) ) ;

while ( MI . getNumOperands ( ) > <NUM_LIT> ) MI . RemoveOperand ( <NUM_LIT> ) ;


<s> MI . setDesc ( HII . get ( <STR_LIT> ) ) ; while ( MI . getNumOperands ( ) > <NUM_LIT> ) MI . RemoveOperand ( <NUM_LIT> ) ;


<s> MRI = & MF . getRegInfo ( ) ; Cells . clear ( ) ; EdgeExec . clear ( ) ; InstrExec . clear ( ) ; assert ( FlowQ . empty ( ) ) ; propagate ( MF ) ; bool Changed = rewrite ( MF ) ; DEBUG ( { dbgs ( ) << <STR_LIT> << Changed << <STR_LIT> ;

if ( Changed ) MF . print ( dbgs ( ) , <NUM_LIT> ) ;


<s> InstrExec . clear ( ) ; assert ( FlowQ . empty ( ) ) ; propagate ( MF ) ; bool Changed = rewrite ( MF ) ; DEBUG ( { dbgs ( ) << <STR_LIT> << Changed << <STR_LIT> ; if ( Changed ) MF . print ( dbgs ( ) , <NUM_LIT> ) ; } ) ; return Changed ;


<s> if ( skipFunction ( * F ) ) return false ; <ISA_LIT>ConstEvaluator HCE ( MF ) ; return MachineConstPropagator ( HCE ) . run ( MF ) ;


<s> const Function * F = MF . getFunction ( ) ;


<s> bool Changed = ( Kind != Bottom ) ; Kind = Bottom ;


<s> void setProperty ( ) { IsSpecial = true ; Size = <NUM_LIT> ; Kind = Normal ;


<s> IsSpecial = true ; Size = <NUM_LIT> ; Kind = Normal ;


<s> unsigned size ( ) const { return Size ;


<s> void update ( unsigned R , const LatticeCell & L ) { Map [ R ] = L ;


<s> InstrExec . insert ( & MI ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ( EvalOk ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << MBN << <STR_LIT> << MI ) ; EvalOk = EvalOk && MCE . evaluate ( MI , Cells , Targets , FallsThru ) ; if ( ! EvalOk ) FallsThru = true ; if ( ! FallsThru ) break ; ++ It ; } if ( EvalOk ) { for ( const MachineBasicBlock * SB : B . successors ( ) ) { if ( SB -> isEHPad ( ) ) Targets . insert ( SB ) ; } if ( FallsThru ) { const MachineFunction & MF = * B . getParent ( ) ; MachineFunction :: const_iterator BI = B . getIterator ( ) ; MachineFunction :: const_iterator Next = std :: next ( BI ) ; if ( Next != MF . end ( ) ) Targets . insert ( & * Next ) ; } } else { Targets . clear ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; for ( const MachineBasicBlock * SB : B . successors ( ) ) Targets . insert ( SB ) ; } for ( const MachineBasicBlock * TB : Targets ) { unsigned TBN = TB -> getNumber ( ) ;

DEBUG ( dbgs ( ) << <STR_LIT> << MBN << <STR_LIT> << TBN << <STR_LIT> ) ;


<s> Cells . update ( DefR . Reg , Bottom ) ; } else { if ( ! Outputs . has ( DefR . Reg ) ) continue ; LatticeCell RC = Cells . get ( DefR . Reg ) ; Changed = RC . meet ( Outputs . get ( DefR . Reg ) ) ; Cells . update ( DefR . Reg , RC ) ; } if ( Changed ) visitUsesOf ( DefR . Reg ) ; }


<s> assert ( TargetRegisterInfo :: isVirtualRegister ( DefR . Reg ) ) ; bool Changed = false ; if ( DefR . SubReg ) { Bottomize : const LatticeCell & T = Cells . get ( DefR . Reg ) ; Changed = ! T . isBottom ( ) ; Cells . update ( DefR . Reg , Bottom ) ; if ( Changed ) visitUsesOf ( DefR . Reg ) ; return ; } LatticeCell DefC = Cells . get ( DefR . Reg ) ; for ( unsigned i = <NUM_LIT> , n = PN . getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) { const MachineBasicBlock * PB = PN . getOperand ( i + <NUM_LIT> ) . getMBB ( ) ; unsigned PBN = PB -> getNumber ( ) ; if ( ! EdgeExec . count ( CFGEdge ( PBN , MBN ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << PBN << <STR_LIT> << MBN << <STR_LIT> ) ; continue ; } const MachineOperand & SO = PN . getOperand ( i ) ;


<s> Changed = ! T . isBottom ( ) ; Cells . update ( DefR . Reg , Bottom ) ; if ( Changed ) visitUsesOf ( DefR . Reg ) ; return ; } LatticeCell DefC = Cells . get ( DefR . Reg ) ; for ( unsigned i = <NUM_LIT> , n = PN . getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) { const MachineBasicBlock * PB = PN . getOperand ( i + <NUM_LIT> ) . getMBB ( ) ; unsigned PBN = PB -> getNumber ( ) ; if ( ! EdgeExec . count ( CFGEdge ( PBN , MBN ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << PBN << <STR_LIT> << MBN << <STR_LIT> ) ; continue ; } const MachineOperand & SO = PN . getOperand ( i ) ; Register UseR ( SO ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( UseR . Reg ) ) goto Bottomize ; if ( ! Cells . has ( UseR . Reg ) ) continue ; LatticeCell SrcC ; bool Eval = MCE . evaluate ( UseR , Cells . get ( UseR . Reg ) , SrcC ) ;

DEBUG ( dbgs ( ) << <STR_LIT> << PBN << <STR_LIT> << PrintReg ( UseR . Reg , & MCE . TRI , UseR . SubReg ) << SrcC << '\n' ) ;


<s> for ( MachineInstr & MI : MRI -> use_nodbg_instructions ( Reg ) ) { if ( ! InstrExec . count ( & MI ) ) continue ; if ( MI . isPHI ( ) ) visitPHI ( MI ) ;

else if ( ! MI . isBranch ( ) ) visitNonBranch ( MI ) ;


<s> virtual ~ MachineConstEvaluator ( ) {


<s> llvm_unreachable ( <STR_LIT> ) ; } } ; verifyOpc ( HiOpc ) ; verifyOpc ( LoOpc ) ; if ( HiOpc == <STR_LIT> || LoOpc == <STR_LIT> ) return HiOpc == LoOpc ; if ( ! AllowC64 ) { if ( isGreaterThanNBitTFRI < <NUM_LIT> > ( HighRegInst ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( LowRegInst ) ) return false ; } if ( isGreaterThanNBitTFRI < <NUM_LIT> > ( HighRegInst ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( LowRegInst ) && ! IsConst64Disabled ) return ( HighRegInst . getOperand ( <NUM_LIT> ) . isImm ( ) && LowRegInst . getOperand ( <NUM_LIT> ) . isImm ( ) ) ; if ( isGreaterThanNBitTFRI < <NUM_LIT> > ( HighRegInst ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( LowRegInst ) ) return false ; return true ;


<s> } else llvm_unreachable ( <STR_LIT> ) ; unsigned DoubleRegDest = TRI -> getMatchingSuperReg ( LoRegDef , SubLo , SuperRC ) ; assert ( DoubleRegDest != <NUM_LIT> && <STR_LIT> ) ; MachineOperand & LoOperand = IsI1Loreg ? I1 . getOperand ( <NUM_LIT> ) : I2 . getOperand ( <NUM_LIT> ) ; MachineOperand & HiOperand = IsI1Loreg ? I2 . getOperand ( <NUM_LIT> ) : I1 . getOperand ( <NUM_LIT> ) ; bool IsHiReg = HiOperand . isReg ( ) ; bool IsLoReg = LoOperand . isReg ( ) ; bool IsC64 = OptForSize && LoOperand . isImm ( ) && HiOperand . isImm ( ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I1 ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I2 ) ; MachineBasicBlock :: iterator InsertPt ( DoInsertAtI1 ? I1 : I2 ) ;

if ( IsHiReg && IsLoReg ) emitCombineRR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ;


<s> assert ( DoubleRegDest != <NUM_LIT> && <STR_LIT> ) ; MachineOperand & LoOperand = IsI1Loreg ? I1 . getOperand ( <NUM_LIT> ) : I2 . getOperand ( <NUM_LIT> ) ; MachineOperand & HiOperand = IsI1Loreg ? I2 . getOperand ( <NUM_LIT> ) : I1 . getOperand ( <NUM_LIT> ) ; bool IsHiReg = HiOperand . isReg ( ) ; bool IsLoReg = LoOperand . isReg ( ) ; bool IsC64 = OptForSize && LoOperand . isImm ( ) && HiOperand . isImm ( ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I1 ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I2 ) ; MachineBasicBlock :: iterator InsertPt ( DoInsertAtI1 ? I1 : I2 ) ; if ( IsHiReg && IsLoReg ) emitCombineRR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsHiReg ) emitCombineRI ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsLoReg ) emitCombineIR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ;

else if ( IsC64 && ! IsConst64Disabled ) emitConst64 ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ;


<s> if ( HiOperand . isBlockAddress ( ) ) { BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addBlockAddress ( HiOperand . getBlockAddress ( ) , HiOperand . getOffset ( ) , HiOperand . getTargetFlags ( ) ) . addReg ( LoReg , LoRegKillFlag ) ; return ; } if ( HiOperand . isJTI ( ) ) { BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addJumpTableIndex ( HiOperand . getIndex ( ) , HiOperand . getTargetFlags ( ) ) . addReg ( LoReg , LoRegKillFlag ) ; return ; }


<s> if ( LoOperand . isBlockAddress ( ) ) { BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addReg ( HiReg , HiRegKillFlag ) . addBlockAddress ( LoOperand . getBlockAddress ( ) , LoOperand . getOffset ( ) , LoOperand . getTargetFlags ( ) ) ; return ; } if ( LoOperand . isJTI ( ) ) {

BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addReg ( HiOperand . getReg ( ) , HiRegKillFlag ) . addJumpTableIndex ( LoOperand . getIndex ( ) , LoOperand . getTargetFlags ( ) ) ;


<s> if ( LoOperand . isGlobal ( ) ) { BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addReg ( HiReg , HiRegKillFlag ) . addGlobalAddress ( LoOperand . getGlobal ( ) , LoOperand . getOffset ( ) , LoOperand . getTargetFlags ( ) ) ; return ; } if ( LoOperand . isBlockAddress ( ) ) { BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addReg ( HiReg , HiRegKillFlag ) . addBlockAddress ( LoOperand . getBlockAddress ( ) , LoOperand . getOffset ( ) , LoOperand . getTargetFlags ( ) ) ;


<s> void <ISA_LIT>CopyToCombine :: emitCombineRR ( MachineBasicBlock :: iterator & InsertPt , unsigned DoubleDestReg , MachineOperand & HiOperand , MachineOperand & LoOperand ) { unsigned LoRegKillFlag = getKillRegState ( LoOperand . isKill ( ) ) ; unsigned HiRegKillFlag = getKillRegState ( HiOperand . isKill ( ) ) ; Register LoReg = LoOperand . getReg ( ) ; Register HiReg = HiOperand . getReg ( ) ;

DebugLoc DL = InsertPt -> getDebugLoc ( ) ;


<s> Register HiReg = HiOperand . getReg ( ) ; DebugLoc DL = InsertPt -> getDebugLoc ( ) ; MachineBasicBlock * BB = InsertPt -> getParent ( ) ; unsigned NewOpc ; if ( <STR_LIT> . contains ( DoubleDestReg ) ) { NewOpc = <STR_LIT> ;

} else if ( <STR_LIT> . contains ( DoubleDestReg ) ) {


<s> V = ( V << <NUM_LIT> ) | ( <NUM_LIT> & LoOperand . getImm ( ) ) ; BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addImm ( V ) ;


<s> assert ( LoOperand . isImm ( ) && HiOperand . isImm ( ) && <STR_LIT> ) ; int64_t V = HiOperand . getImm ( ) ; V = ( V << <NUM_LIT> ) | ( <NUM_LIT> & LoOperand . getImm ( ) ) ;

BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addImm ( V ) ;


<s> MachineInstr * <ISA_LIT>CopyToCombine :: findPairable ( MachineInstr & I1 , bool & DoInsertAtI1 , bool AllowC64 ) { MachineBasicBlock :: iterator I2 = std :: next ( MachineBasicBlock :: iterator ( I1 ) ) ; while ( I2 != I1 . getParent ( ) -> end ( ) && I2 -> isDebugInstr ( ) ) ++ I2 ; Register I1DestReg = I1 . getOperand ( <NUM_LIT> ) . getReg ( ) ;

for ( MachineBasicBlock :: iterator End = I1 . getParent ( ) -> end ( ) ; I2 != End ;


<s> for ( MachineInstr & MI : BB ) { if ( MI . isDebugInstr ( ) ) continue ; if ( TII -> mayBeNewStore ( MI ) ) { for ( const MachineOperand & Op : MI . operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isUse ( ) || ! Op . getReg ( ) ) continue ; Register Reg = Op . getReg ( ) ; MachineInstr * DefInst = LastDef [ Reg ] ; if ( ! DefInst ) continue ; if ( ! isCombinableInstType ( * DefInst , TII , ShouldCombineAggressively ) ) continue ; MachineBasicBlock :: iterator It ( DefInst ) ; unsigned NumInstsToDef = <NUM_LIT> ; while ( & * It != & MI ) { if ( ! It -> isDebugInstr ( ) ) ++ NumInstsToDef ; ++ It ;


<s> for ( MachineInstr & MI : BB ) { if ( MI . isDebugInstr ( ) ) continue ; if ( TII -> mayBeNewStore ( MI ) ) { for ( const MachineOperand & Op : MI . operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isUse ( ) || ! Op . getReg ( ) ) continue ; Register Reg = Op . getReg ( ) ; MachineInstr * DefInst = LastDef [ Reg ] ; if ( ! DefInst ) continue ; if ( ! isCombinableInstType ( * DefInst , TII , ShouldCombineAggressively ) ) continue ; MachineBasicBlock :: iterator It ( DefInst ) ; unsigned NumInstsToDef = <NUM_LIT> ; while ( & * It != & MI ) {

if ( ! It -> isDebugInstr ( ) ) ++ NumInstsToDef ;


<s> StringRef getPassName ( ) const override {


<s> <ISA_LIT>CopyToCombine ( ) : MachineFunctionPass ( ID ) {


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : { const MachineOperand & Op0 = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & Op1 = MI . getOperand ( <NUM_LIT> ) ; assert ( Op0 . isReg ( ) && Op1 . isReg ( ) ) ; Register DestReg = Op0 . getReg ( ) ; Register SrcReg = Op1 . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ; } case <STR_LIT> : { const MachineOperand & Op0 = MI . getOperand ( <NUM_LIT> ) ;


<s> if ( <STR_LIT> . contains ( Reg ) ) return ( Reg - <STR_LIT> ) % <NUM_LIT> == <NUM_LIT> ; if ( <STR_LIT> . contains ( Reg ) ) return ( Reg - <STR_LIT> ) % <NUM_LIT> == <NUM_LIT> ;


<s> if ( <STR_LIT> . contains ( Reg ) ) return ( Reg - <STR_LIT> ) % <NUM_LIT> == <NUM_LIT> ;


<s> const MachineOperand & Op = I . getOperand ( <NUM_LIT> ) ; return ! Op . isImm ( ) || ! isInt < N > ( Op . getImm ( ) ) ; }


<s> } DoInsertAtI1 = true ; return true ; } } { MachineBasicBlock :: iterator I ( I1 ) , End ( I2 ) ; if ( ! ShouldCombineAggressively ) End = std :: next ( MachineBasicBlock :: iterator ( I2 ) ) ; Register I1UseReg = UseReg ( I1 . getOperand ( <NUM_LIT> ) ) ; MachineInstr * KillingInstr = nullptr ; unsigned KilledOperand = <NUM_LIT> ; while ( ++ I != End ) { MachineInstr & MI = * I ; if ( MI . isDebugInstr ( ) ) { if ( MI . readsRegister ( I1DestReg , TRI ) ) DbgMItoMove . push_back ( & MI ) ; continue ; } if ( isUnsafeToMoveAcross ( MI , I1UseReg , I1DestReg , TRI ) || ( ! MI . killsRegister ( I1UseReg ) && MI . killsRegister ( I1UseReg , TRI ) ) ) return false ; if ( I1UseReg && MI . killsRegister ( I1UseReg ) ) { assert ( ! KillingInstr && <STR_LIT> ) ; KilledOperand = I1UseReg ; KillingInstr = & MI ; } } if ( KillingInstr ) {

removeKillInfo ( * KillingInstr , KilledOperand ) ;


<s> static bool isUnsafeToMoveAcross ( MachineInstr & MI , unsigned UseReg , unsigned DestReg , const TargetRegisterInfo * TRI ) { return ( UseReg && ( MI . modifiesRegister ( UseReg , TRI ) ) ) || MI . modifiesRegister ( DestReg , TRI ) || MI . readsRegister ( DestReg , TRI ) || MI . hasUnmodeledSideEffects ( ) || MI . isInlineAsm ( ) || MI . isMetaInstruction ( ) ;


<s> for ( MachineOperand & Op : MI . operands ( ) ) if ( Op . isReg ( ) && Op . getReg ( ) == RegNotKilled && Op . isKill ( ) ) Op . setIsKill ( false ) ;


<s> TII = ST -> getInstrInfo ( ) ; const Function & F = MF . getFunction ( ) ; bool OptForSize = F . hasFnAttribute ( Attribute :: OptimizeForSize ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; if ( ! OptForSize && ST -> isTinyCore ( ) ) IsConst64Disabled = true ; for ( MachineBasicBlock & MBB : MF ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( MBB ) ; for ( MachineBasicBlock :: iterator MI = MBB . begin ( ) , End = MBB . end ( ) ; MI != End ; ) { MachineInstr & I1 = * MI ++ ; if ( I1 . isDebugInstr ( ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & I1 ) ) continue ;

if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ;


<s> bool OptForSize = F . hasFnAttribute ( Attribute :: OptimizeForSize ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; if ( ! OptForSize && ST -> isTinyCore ( ) ) IsConst64Disabled = true ; for ( MachineBasicBlock & MBB : MF ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( MBB ) ; for ( MachineBasicBlock :: iterator MI = MBB . begin ( ) , End = MBB . end ( ) ; MI != End ; ) { MachineInstr & I1 = * MI ++ ; if ( I1 . isDebugInstr ( ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & I1 ) ) continue ; if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ; bool DoInsertAtI1 = false ; DbgMItoMove . clear ( ) ; MachineInstr * I2 = findPairable ( I1 , DoInsertAtI1 , OptForSize ) ; if ( I2 ) {


<s> static Register UseReg ( const MachineOperand & MO ) {

return MO . isReg ( ) ? MO . getReg ( ) : Register ( ) ;


<s> unsigned LoOpc = LowRegInst -> getOpcode ( ) ; ( void ) HiOpc ; ( void ) LoOpc ; assert ( ( HiOpc == <STR_LIT> || HiOpc == <STR_LIT> ) && ( LoOpc == <STR_LIT> || LoOpc == <STR_LIT> ) && <STR_LIT> ) ;

if ( isGreaterThanNBitTFRI < <NUM_LIT> > ( HighRegInst ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( LowRegInst ) ) return false ;


<s> unsigned LoOpc = LowRegInst -> getOpcode ( ) ; ( void ) HiOpc ; ( void ) LoOpc ; assert ( ( HiOpc == <STR_LIT> || HiOpc == <STR_LIT> ) && ( LoOpc == <STR_LIT> || LoOpc == <STR_LIT> ) && <STR_LIT> ) ; if ( isGreaterThanNBitTFRI < <NUM_LIT> > ( HighRegInst ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( LowRegInst ) ) return false ; return true ;


<s> MachineBasicBlock :: iterator InsertPt ( DoInsertAtI1 ? I1 : I2 ) ; if ( IsHiReg && IsLoReg ) emitCombineRR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsHiReg ) emitCombineRI ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsLoReg ) emitCombineIR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else emitCombineII ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; I1 -> eraseFromParent ( ) ; I2 -> eraseFromParent ( ) ;


<s> MachineOperand & LoOperand = IsI1Loreg ? I1 -> getOperand ( <NUM_LIT> ) : I2 -> getOperand ( <NUM_LIT> ) ; MachineOperand & HiOperand = IsI1Loreg ? I2 -> getOperand ( <NUM_LIT> ) : I1 -> getOperand ( <NUM_LIT> ) ; bool IsHiReg = HiOperand . isReg ( ) ; bool IsLoReg = LoOperand . isReg ( ) ; MachineBasicBlock :: iterator InsertPt ( DoInsertAtI1 ? I1 : I2 ) ; if ( IsHiReg && IsLoReg ) emitCombineRR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsHiReg ) emitCombineRI ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsLoReg ) emitCombineIR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else emitCombineII ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; I1 -> eraseFromParent ( ) ;


<s> return new <ISA_LIT>CopyToCombine ( ) ;


<s> } if ( HiOperand . isBlockAddress ( ) ) { BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addBlockAddress ( HiOperand . getBlockAddress ( ) , HiOperand . getOffset ( ) , HiOperand . getTargetFlags ( ) ) . addImm ( LoOperand . getImm ( ) ) ; return ; } if ( LoOperand . isBlockAddress ( ) ) { BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addImm ( HiOperand . getImm ( ) ) . addBlockAddress ( LoOperand . getBlockAddress ( ) , LoOperand . getOffset ( ) , LoOperand . getTargetFlags ( ) ) ; return ; } if ( HiOperand . isJTI ( ) ) { BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addJumpTableIndex ( HiOperand . getIndex ( ) , HiOperand . getTargetFlags ( ) ) . addImm ( LoOperand . getImm ( ) ) ; return ; } if ( LoOperand . isJTI ( ) ) { BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addImm ( HiOperand . getImm ( ) ) . addJumpTableIndex ( LoOperand . getIndex ( ) , LoOperand . getTargetFlags ( ) ) ; return ; } if ( HiOperand . isCPI ( ) ) { BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addConstantPoolIndex ( HiOperand . getIndex ( ) , HiOperand . getOffset ( ) , HiOperand . getTargetFlags ( ) ) . addImm ( LoOperand . getImm ( ) ) ; return ; } if ( LoOperand . isCPI ( ) ) { BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addImm ( HiOperand . getImm ( ) ) . addConstantPoolIndex ( LoOperand . getIndex ( ) , LoOperand . getOffset ( ) , LoOperand . getTargetFlags ( ) ) ; return ;


<s> if ( LoOperand . isJTI ( ) ) { BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addReg ( HiOperand . getReg ( ) , HiRegKillFlag ) . addJumpTableIndex ( LoOperand . getIndex ( ) , LoOperand . getTargetFlags ( ) ) ; return ; } if ( LoOperand . isCPI ( ) ) { BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addReg ( HiOperand . getReg ( ) , HiRegKillFlag ) . addConstantPoolIndex ( LoOperand . getIndex ( ) , LoOperand . getOffset ( ) , LoOperand . getTargetFlags ( ) ) ; return ;


<s> void <ISA_LIT>CopyToCombine :: emitCombineRR ( MachineBasicBlock :: iterator & InsertPt , unsigned DoubleDestReg , MachineOperand & HiOperand , MachineOperand & LoOperand ) { unsigned LoRegKillFlag = getKillRegState ( LoOperand . isKill ( ) ) ; unsigned HiRegKillFlag = getKillRegState ( HiOperand . isKill ( ) ) ; unsigned LoReg = LoOperand . getReg ( ) ;

unsigned HiReg = HiOperand . getReg ( ) ;


<s> if ( ( ! IsI1LowReg && ! IsI2LowReg ) || ! isEvenReg ( FirstRegIndex ) ) continue ; if ( ( IsI2LowReg && ! areCombinableOperations ( TRI , I1 , I2 ) ) || ( IsI1LowReg && ! areCombinableOperations ( TRI , I2 , I1 ) ) ) break ; if ( isSafeToMoveTogether ( I1 , I2 , I1DestReg , I2DestReg , DoInsertAtI1 ) ) return I2 ; break ; }


<s> unsigned FirstRegIndex = IsI1LowReg ? I1DestReg : I2DestReg ; if ( ( ! IsI1LowReg && ! IsI2LowReg ) || ! isEvenReg ( FirstRegIndex ) ) continue ; if ( ( IsI2LowReg && ! areCombinableOperations ( TRI , I1 , I2 ) ) || ( IsI1LowReg && ! areCombinableOperations ( TRI , I2 , I1 ) ) ) break ;

if ( isSafeToMoveTogether ( I1 , I2 , I1DestReg , I2DestReg , DoInsertAtI1 ) ) return I2 ;


<s> } continue ; } for ( unsigned I = <NUM_LIT> , E = MI -> getNumOperands ( ) ; I != E ; ++ I ) { MachineOperand & Op = MI -> getOperand ( I ) ; if ( ! Op . isReg ( ) || ! Op . isDef ( ) || ! Op . getReg ( ) ) continue ; unsigned Reg = Op . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { for ( MCSubRegIterator SubRegs ( Reg , TRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) { LastDef [ * SubRegs ] = MI ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> const char * getPassName ( ) const override { return <STR_LIT> ;


<s> const char * getPassName ( ) const override {


<s> <ISA_LIT>CopyToCombine ( ) : MachineFunctionPass ( ID ) {

initialize<ISA_LIT>CopyToCombinePass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> return <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ; } case <STR_LIT> : { const MachineOperand & Op0 = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & Op1 = MI -> getOperand ( <NUM_LIT> ) ; assert ( Op0 . isReg ( ) ) ; unsigned DestReg = Op0 . getReg ( ) ; if ( ! Op1 . isImm ( ) && Op1 . getTargetFlags ( ) != <STR_LIT> ) return false ; bool NotExt = Op1 . isImm ( ) && isInt < <NUM_LIT> > ( Op1 . getImm ( ) ) ; return <STR_LIT> . contains ( DestReg ) && ( ShouldCombineAggressively || NotExt ) ;


<s> assert ( Op0 . isReg ( ) && Op1 . isReg ( ) ) ; unsigned DestReg = Op0 . getReg ( ) ; unsigned SrcReg = Op1 . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ; } case <STR_LIT> : { const MachineOperand & Op0 = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & Op1 = MI -> getOperand ( <NUM_LIT> ) ; assert ( Op0 . isReg ( ) ) ; unsigned DestReg = Op0 . getReg ( ) ; if ( ! Op1 . isImm ( ) && Op1 . getTargetFlags ( ) != <STR_LIT> ) return false ; bool NotExt = Op1 . isImm ( ) && isInt < <NUM_LIT> > ( Op1 . getImm ( ) ) ;

return <STR_LIT> . contains ( DestReg ) && ( ShouldCombineAggressively || NotExt ) ;


<s> static bool isEvenReg ( unsigned Reg ) {

assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) && <STR_LIT> . contains ( Reg ) ) ;


<s> assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) && <STR_LIT> . contains ( Reg ) ) ; return ( Reg - <STR_LIT> ) % <NUM_LIT> == <NUM_LIT> ;


<s> return ! Op . isImm ( ) || ! isInt < N > ( Op . getImm ( ) ) ;


<s> if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) { const MachineOperand & Op = I -> getOperand ( <NUM_LIT> ) ;

return ! Op . isImm ( ) || ! isInt < N > ( Op . getImm ( ) ) ;


<s> { MachineBasicBlock :: iterator I ( I1 ) , End ( I2 ) ; if ( ! ShouldCombineAggressively ) End = std :: next ( MachineBasicBlock :: iterator ( I2 ) ) ; unsigned I1UseReg = UseReg ( I1 -> getOperand ( <NUM_LIT> ) ) ; MachineInstr * KillingInstr = nullptr ; unsigned KilledOperand = <NUM_LIT> ; while ( ++ I != End ) { if ( isUnsafeToMoveAcross ( I , I1UseReg , I1DestReg , TRI ) || ( ! I -> killsRegister ( I1UseReg ) && I -> killsRegister ( I1UseReg , TRI ) ) ) return false ; if ( I1UseReg && I -> killsRegister ( I1UseReg ) ) { assert ( ! KillingInstr && <STR_LIT> ) ; KilledOperand = I1UseReg ; KillingInstr = & * I ; } } if ( KillingInstr ) { removeKillInfo ( KillingInstr , KilledOperand ) ; bool Added = I1 -> addRegisterKilled ( KilledOperand , TRI ) ;


<s> return ( UseReg && ( I -> modifiesRegister ( UseReg , TRI ) ) ) || I -> modifiesRegister ( DestReg , TRI ) || I -> readsRegister ( DestReg , TRI ) || I -> hasUnmodeledSideEffects ( ) || I -> isInlineAsm ( ) || I -> isDebugValue ( ) ;


<s> for ( unsigned I = <NUM_LIT> , E = MI -> getNumOperands ( ) ; I != E ; ++ I ) { MachineOperand & Op = MI -> getOperand ( I ) ; if ( ! Op . isReg ( ) || Op . getReg ( ) != RegNotKilled || ! Op . isKill ( ) ) continue ;


<s> MachineOperand & Op = MI -> getOperand ( I ) ;

if ( ! Op . isReg ( ) || Op . getReg ( ) != RegNotKilled || ! Op . isKill ( ) ) continue ;


<s> } if ( isGreaterThanNBitTFRI < <NUM_LIT> > ( HighRegInst ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( LowRegInst ) ) return ( HighRegInst . getOperand ( <NUM_LIT> ) . isImm ( ) && LowRegInst . getOperand ( <NUM_LIT> ) . isImm ( ) ) ;


<s> unsigned SubLo ; const TargetRegisterClass * SuperRC = nullptr ; if ( <STR_LIT> . contains ( LoRegDef ) ) { SuperRC = & <STR_LIT> ; SubLo = <STR_LIT> ; } else if ( <STR_LIT> . contains ( LoRegDef ) ) { assert ( ST -> useHVXOps ( ) ) ; SuperRC = & <STR_LIT> ; SubLo = <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; unsigned DoubleRegDest = TRI -> getMatchingSuperReg ( LoRegDef , SubLo , SuperRC ) ; assert ( DoubleRegDest != <NUM_LIT> && <STR_LIT> ) ; MachineOperand & LoOperand = IsI1Loreg ? I1 . getOperand ( <NUM_LIT> ) : I2 . getOperand ( <NUM_LIT> ) ; MachineOperand & HiOperand = IsI1Loreg ? I2 . getOperand ( <NUM_LIT> ) : I1 . getOperand ( <NUM_LIT> ) ; bool IsHiReg = HiOperand . isReg ( ) ; bool IsLoReg = LoOperand . isReg ( ) ; bool IsC64 = OptForSize && LoOperand . isImm ( ) && HiOperand . isImm ( ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I1 ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I2 ) ; MachineBasicBlock :: iterator InsertPt ( DoInsertAtI1 ? I1 : I2 ) ; if ( IsHiReg && IsLoReg ) emitCombineRR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsHiReg ) emitCombineRI ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsLoReg ) emitCombineIR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsC64 && ! IsConst64Disabled ) emitConst64 ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ;

else emitCombineII ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ;


<s> assert ( ST -> useHVXOps ( ) ) ; NewOpc = <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ;

BuildMI ( * BB , InsertPt , DL , TII -> get ( NewOpc ) , DoubleDestReg ) . addReg ( HiReg , HiRegKillFlag ) . addReg ( LoReg , LoRegKillFlag ) ;


<s> bool IsI1LowReg = ( I2DestReg - I1DestReg ) == <NUM_LIT> ; bool IsI2LowReg = ( I1DestReg - I2DestReg ) == <NUM_LIT> ; unsigned FirstRegIndex = IsI1LowReg ? I1DestReg : I2DestReg ; if ( ( ! IsI1LowReg && ! IsI2LowReg ) || ! isEvenReg ( FirstRegIndex ) ) continue ;

if ( ( IsI2LowReg && ! areCombinableOperations ( TRI , I1 , * I2 , AllowC64 ) ) || ( IsI1LowReg && ! areCombinableOperations ( TRI , * I2 , I1 , AllowC64 ) ) ) break ;


<s> if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & * I2 ) ) continue ; unsigned I2DestReg = I2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsI1LowReg = ( I2DestReg - I1DestReg ) == <NUM_LIT> ; bool IsI2LowReg = ( I1DestReg - I2DestReg ) == <NUM_LIT> ; unsigned FirstRegIndex = IsI1LowReg ? I1DestReg : I2DestReg ; if ( ( ! IsI1LowReg && ! IsI2LowReg ) || ! isEvenReg ( FirstRegIndex ) ) continue ; if ( ( IsI2LowReg && ! areCombinableOperations ( TRI , I1 , * I2 , AllowC64 ) ) || ( IsI1LowReg && ! areCombinableOperations ( TRI , * I2 , I1 , AllowC64 ) ) ) break ; if ( isSafeToMoveTogether ( I1 , * I2 , I1DestReg , I2DestReg , DoInsertAtI1 ) ) return & * I2 ; break ; } return nullptr ;


<s> if ( ! It -> isDebugInstr ( ) ) ++ NumInstsToDef ; ++ It ; } if ( NumInstsToDef > MaxNumOfInstsBetweenNewValueStoreAndTFR ) continue ; PotentiallyNewifiableTFR . insert ( DefInst ) ; } continue ; } for ( MachineOperand & Op : MI . operands ( ) ) { if ( Op . isReg ( ) ) { if ( ! Op . isDef ( ) || ! Op . getReg ( ) ) continue ; unsigned Reg = Op . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { for ( MCSubRegIterator SubRegs ( Reg , TRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) LastDef [ * SubRegs ] = & MI ; } else if ( <STR_LIT> . contains ( Reg ) ) LastDef [ Reg ] = & MI ; } else if ( Op . isRegMask ( ) ) {

for ( unsigned Reg : <STR_LIT> ) if ( Op . clobbersPhysReg ( Reg ) ) LastDef [ Reg ] = & MI ;


<s> const MachineOperand & Op0 = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & Op1 = MI . getOperand ( <NUM_LIT> ) ; assert ( Op0 . isReg ( ) && Op1 . isReg ( ) ) ; unsigned DestReg = Op0 . getReg ( ) ; unsigned SrcReg = Op1 . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ; }


<s> assert ( Op0 . isReg ( ) ) ; unsigned DestReg = Op0 . getReg ( ) ; if ( ! Op1 . isImm ( ) && Op1 . getTargetFlags ( ) != <STR_LIT> ) return false ; bool NotExt = Op1 . isImm ( ) && isInt < <NUM_LIT> > ( Op1 . getImm ( ) ) ;


<s> if ( <STR_LIT> . contains ( Reg ) ) return ( Reg - <STR_LIT> ) % <NUM_LIT> == <NUM_LIT> ; llvm_unreachable ( <STR_LIT> ) ;


<s> if ( ! ShouldCombineAggressively ) End = std :: next ( MachineBasicBlock :: iterator ( I2 ) ) ; unsigned I1UseReg = UseReg ( I1 . getOperand ( <NUM_LIT> ) ) ; MachineInstr * KillingInstr = nullptr ; unsigned KilledOperand = <NUM_LIT> ; while ( ++ I != End ) { MachineInstr & MI = * I ; if ( MI . isDebugInstr ( ) ) { if ( MI . readsRegister ( I1DestReg , TRI ) ) DbgMItoMove . push_back ( & MI ) ; continue ; } if ( isUnsafeToMoveAcross ( MI , I1UseReg , I1DestReg , TRI ) || ( ! MI . killsRegister ( I1UseReg ) && MI . killsRegister ( I1UseReg , TRI ) ) ) return false ; if ( I1UseReg && MI . killsRegister ( I1UseReg ) ) { assert ( ! KillingInstr && <STR_LIT> ) ; KilledOperand = I1UseReg ; KillingInstr = & MI ; } } if ( KillingInstr ) { removeKillInfo ( * KillingInstr , KilledOperand ) ; bool Added = I1 . addRegisterKilled ( KilledOperand , TRI ) ; ( void ) Added ;


<s> static void removeKillInfo ( MachineInstr & MI , unsigned RegNotKilled ) {

for ( unsigned I = <NUM_LIT> , E = MI . getNumOperands ( ) ; I != E ; ++ I ) {


<s> bool HasChanged = false ; ST = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = ST -> getInstrInfo ( ) ; const Function & F = MF . getFunction ( ) ; bool OptForSize = F . hasFnAttribute ( Attribute :: OptimizeForSize ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( * BI ) ;

for ( MachineBasicBlock :: iterator MI = BI -> begin ( ) , End = BI -> end ( ) ;


<s> if ( IsCombinesDisabled ) return false ; bool HasChanged = false ; ST = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = ST -> getInstrInfo ( ) ; const Function & F = MF . getFunction ( ) ; bool OptForSize = F . hasFnAttribute ( Attribute :: OptimizeForSize ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( * BI ) ; for ( MachineBasicBlock :: iterator MI = BI -> begin ( ) , End = BI -> end ( ) ; MI != End ; ) { MachineInstr & I1 = * MI ++ ; if ( I1 . isDebugInstr ( ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & I1 ) ) continue ; if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ; bool DoInsertAtI1 = false ; DbgMItoMove . clear ( ) ; MachineInstr * I2 = findPairable ( I1 , DoInsertAtI1 , OptForSize ) ; if ( I2 ) { HasChanged = true ; combine ( I1 , * I2 , MI , DoInsertAtI1 , OptForSize ) ; } }


<s> const <ISA_LIT>RegisterInfo * QRI = static_cast < const <ISA_LIT>RegisterInfo * > ( TRI ) ; if ( ! QRI -> Subtarget . hasV4TOps ( ) ) return HighRegInst -> getOpcode ( ) == LowRegInst -> getOpcode ( ) && ! isGreaterThan8BitTFRI ( HighRegInst ) && ! isGreaterThan6BitTFRI ( LowRegInst ) ; if ( ( HighRegInst -> getOpcode ( ) == <STR_LIT> || isGreaterThan8BitTFRI ( HighRegInst ) ) && ( LowRegInst -> getOpcode ( ) == <STR_LIT> || isGreaterThan6BitTFRI ( LowRegInst ) ) ) return false ; return true ;


<s> BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addGlobalAddress ( HiOperand . getGlobal ( ) , HiOperand . getOffset ( ) , HiOperand . getTargetFlags ( ) ) . addImm ( LoOperand . getImm ( ) ) ; return ; } if ( LoOperand . isGlobal ( ) ) { BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addImm ( HiOperand . getImm ( ) ) . addGlobalAddress ( LoOperand . getGlobal ( ) , LoOperand . getOffset ( ) , LoOperand . getTargetFlags ( ) ) ; return ; } if ( ! isInt < <NUM_LIT> > ( HiOperand . getImm ( ) ) ) { assert ( isInt < <NUM_LIT> > ( LoOperand . getImm ( ) ) ) ; BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addImm ( HiOperand . getImm ( ) ) . addImm ( LoOperand . getImm ( ) ) ; return ;


<s> BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addGlobalAddress ( HiOperand . getGlobal ( ) , HiOperand . getOffset ( ) , HiOperand . getTargetFlags ( ) ) . addReg ( LoReg , LoRegKillFlag ) ; return ;


<s> if ( LoOperand . isGlobal ( ) ) { BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addReg ( HiReg , HiRegKillFlag ) . addGlobalAddress ( LoOperand . getGlobal ( ) , LoOperand . getOffset ( ) , LoOperand . getTargetFlags ( ) ) ; return ;


<s> case <STR_LIT> : { assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ; } case <STR_LIT> : { assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) && ( ShouldCombineAggressively || isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; }


<s> unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) && ( ShouldCombineAggressively || isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; } case <STR_LIT> : { if ( ! ShouldCombineAggressively ) return false ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isGlobal ( ) ) ; if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> ) return false ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) ; } default : break ; } return false ;


<s> static bool isGreaterThan6BitTFRI ( MachineInstr * I ) {

return I -> getOpcode ( ) == <STR_LIT> && ! isUInt < <NUM_LIT> > ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> static bool isGreaterThan8BitTFRI ( MachineInstr * I ) {

return I -> getOpcode ( ) == <STR_LIT> && ! isInt < <NUM_LIT> > ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> ++ BI ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( * BI ) ; for ( MachineBasicBlock :: iterator MI = BI -> begin ( ) , End = BI -> end ( ) ; MI != End ; ) { MachineInstr * I1 = MI ++ ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( I1 ) ) continue ; if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ; bool DoInsertAtI1 = false ; MachineInstr * I2 = findPairable ( I1 , DoInsertAtI1 ) ; if ( I2 ) { HasChanged = true ; combine ( I1 , I2 , MI , DoInsertAtI1 ) ;


<s> PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( * BI ) ; for ( MachineBasicBlock :: iterator MI = BI -> begin ( ) , End = BI -> end ( ) ; MI != End ; ) { MachineInstr * I1 = MI ++ ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( I1 ) ) continue ; if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ; bool DoInsertAtI1 = false ;

MachineInstr * I2 = findPairable ( I1 , DoInsertAtI1 ) ;


<s> if ( skipFunction ( MF . getFunction ( ) ) ) return false ; if ( IsCombinesDisabled ) return false ; bool HasChanged = false ; ST = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = ST -> getInstrInfo ( ) ; const Function & F = MF . getFunction ( ) ; bool OptForSize = F . hasFnAttribute ( Attribute :: OptimizeForSize ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; if ( ! OptForSize && ST -> isTinyCore ( ) ) IsConst64Disabled = true ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( * BI ) ; for ( MachineBasicBlock :: iterator MI = BI -> begin ( ) , End = BI -> end ( ) ; MI != End ; ) { MachineInstr & I1 = * MI ++ ; if ( I1 . isDebugInstr ( ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & I1 ) ) continue ;

if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ;


<s> if ( I1 . isDebugInstr ( ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & I1 ) ) continue ; if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ; bool DoInsertAtI1 = false ; DbgMItoMove . clear ( ) ; MachineInstr * I2 = findPairable ( I1 , DoInsertAtI1 , OptForSize ) ; if ( I2 ) { HasChanged = true ; combine ( I1 , * I2 , MI , DoInsertAtI1 , OptForSize ) ;


<s> unsigned HiOpc = HighRegInst . getOpcode ( ) ; unsigned LoOpc = LowRegInst . getOpcode ( ) ; ( void ) HiOpc ; ( void ) LoOpc ; assert ( ( HiOpc == <STR_LIT> || HiOpc == <STR_LIT> ) && ( LoOpc == <STR_LIT> || LoOpc == <STR_LIT> ) && <STR_LIT> ) ;


<s> unsigned I1DestReg = I1 . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned I2DestReg = I2 . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsI1Loreg = ( I2DestReg - I1DestReg ) == <NUM_LIT> ; unsigned LoRegDef = IsI1Loreg ? I1DestReg : I2DestReg ; unsigned DoubleRegDest = TRI -> getMatchingSuperReg ( LoRegDef , <STR_LIT> , & <STR_LIT> ) ; assert ( DoubleRegDest != <NUM_LIT> && <STR_LIT> ) ; MachineOperand & LoOperand = IsI1Loreg ? I1 . getOperand ( <NUM_LIT> ) : I2 . getOperand ( <NUM_LIT> ) ; MachineOperand & HiOperand = IsI1Loreg ? I2 . getOperand ( <NUM_LIT> ) : I1 . getOperand ( <NUM_LIT> ) ; bool IsHiReg = HiOperand . isReg ( ) ; bool IsLoReg = LoOperand . isReg ( ) ; bool IsC64 = OptForSize && LoOperand . isImm ( ) && HiOperand . isImm ( ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I1 ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I2 ) ; MachineBasicBlock :: iterator InsertPt ( DoInsertAtI1 ? I1 : I2 ) ; if ( IsHiReg && IsLoReg ) emitCombineRR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsHiReg ) emitCombineRI ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsLoReg ) emitCombineIR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsC64 && ! IsConst64Disabled ) emitConst64 ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ;


<s> assert ( LoOperand . isImm ( ) && HiOperand . isImm ( ) && <STR_LIT> ) ; int64_t V = HiOperand . getImm ( ) ; V = ( V << <NUM_LIT> ) | ( <NUM_LIT> & LoOperand . getImm ( ) ) ; BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addImm ( V ) ;


<s> while ( I2 -> isDebugValue ( ) ) ++ I2 ; unsigned I1DestReg = I1 . getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineBasicBlock :: iterator End = I1 . getParent ( ) -> end ( ) ; I2 != End ; ++ I2 ) { if ( I2 -> modifiesRegister ( I1DestReg , TRI ) ) break ; if ( ! isCombinableInstType ( * I2 , TII , ShouldCombineAggressively ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & * I2 ) ) continue ; unsigned I2DestReg = I2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsI1LowReg = ( I2DestReg - I1DestReg ) == <NUM_LIT> ; bool IsI2LowReg = ( I1DestReg - I2DestReg ) == <NUM_LIT> ; unsigned FirstRegIndex = IsI1LowReg ? I1DestReg : I2DestReg ; if ( ( ! IsI1LowReg && ! IsI2LowReg ) || ! isEvenReg ( FirstRegIndex ) ) continue ; if ( ( IsI2LowReg && ! areCombinableOperations ( TRI , I1 , * I2 , AllowC64 ) ) || ( IsI1LowReg && ! areCombinableOperations ( TRI , * I2 , I1 , AllowC64 ) ) ) break ; if ( isSafeToMoveTogether ( I1 , * I2 , I1DestReg , I2DestReg , DoInsertAtI1 ) ) return & * I2 ; break ; } return nullptr ;


<s> if ( I -> isDebugValue ( ) ) continue ; if ( isUnsafeToMoveAcross ( * I , I2UseReg , I2DestReg , TRI ) ) { isSafe = false ; break ; } if ( ! KillingInstr && KilledOperand && I -> readsRegister ( KilledOperand , TRI ) ) KillingInstr = & * I ; } if ( isSafe ) { if ( KillingInstr ) { bool Added = KillingInstr -> addRegisterKilled ( KilledOperand , TRI , true ) ; ( void ) Added ; assert ( Added && <STR_LIT> ) ; removeKillInfo ( I2 , KilledOperand ) ; } DoInsertAtI1 = true ; return true ; } } { MachineBasicBlock :: iterator I ( I1 ) , End ( I2 ) ; if ( ! ShouldCombineAggressively ) End = std :: next ( MachineBasicBlock :: iterator ( I2 ) ) ; unsigned I1UseReg = UseReg ( I1 . getOperand ( <NUM_LIT> ) ) ; MachineInstr * KillingInstr = nullptr ; unsigned KilledOperand = <NUM_LIT> ; while ( ++ I != End ) { MachineInstr & MI = * I ; if ( MI . isDebugValue ( ) ) { if ( MI . readsRegister ( I1DestReg , TRI ) ) DbgMItoMove . push_back ( & MI ) ; continue ; } if ( isUnsafeToMoveAcross ( MI , I1UseReg , I1DestReg , TRI ) || ( ! MI . killsRegister ( I1UseReg ) && MI . killsRegister ( I1UseReg , TRI ) ) ) return false ; if ( I1UseReg && MI . killsRegister ( I1UseReg ) ) { assert ( ! KillingInstr && <STR_LIT> ) ; KilledOperand = I1UseReg ; KillingInstr = & MI ; } } if ( KillingInstr ) { removeKillInfo ( * KillingInstr , KilledOperand ) ; bool Added = I1 . addRegisterKilled ( KilledOperand , TRI ) ; ( void ) Added ; assert ( Added && <STR_LIT> ) ; } DoInsertAtI1 = false ; } return true ;


<s> return ( UseReg && ( MI . modifiesRegister ( UseReg , TRI ) ) ) || MI . modifiesRegister ( DestReg , TRI ) || MI . readsRegister ( DestReg , TRI ) || MI . hasUnmodeledSideEffects ( ) || MI . isInlineAsm ( ) || MI . isDebugValue ( ) ;


<s> TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const Function * F = MF . getFunction ( ) ; bool OptForSize = F -> hasFnAttribute ( Attribute :: OptimizeForSize ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( * BI ) ; for ( MachineBasicBlock :: iterator MI = BI -> begin ( ) , End = BI -> end ( ) ; MI != End ; ) { MachineInstr & I1 = * MI ++ ; if ( I1 . isDebugValue ( ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & I1 ) ) continue ; if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ; bool DoInsertAtI1 = false ; DbgMItoMove . clear ( ) ;

MachineInstr * I2 = findPairable ( I1 , DoInsertAtI1 , OptForSize ) ;


<s> V = ( V << <NUM_LIT> ) | ( <NUM_LIT> & LoOperand . getImm ( ) ) ;

BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addImm ( V ) ;


<s> MachineInstr * <ISA_LIT>CopyToCombine :: findPairable ( MachineInstr & I1 , bool & DoInsertAtI1 , bool AllowC64 ) { MachineBasicBlock :: iterator I2 = std :: next ( MachineBasicBlock :: iterator ( I1 ) ) ; while ( I2 != I1 . getParent ( ) -> end ( ) && I2 -> isDebugValue ( ) ) ++ I2 ; unsigned I1DestReg = I1 . getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineBasicBlock :: iterator End = I1 . getParent ( ) -> end ( ) ; I2 != End ; ++ I2 ) { if ( I2 -> modifiesRegister ( I1DestReg , TRI ) ) break ; if ( ! isCombinableInstType ( * I2 , TII , ShouldCombineAggressively ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & * I2 ) ) continue ;

unsigned I2DestReg = I2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> MachineBasicBlock :: iterator It ( DefInst ) ; unsigned NumInstsToDef = <NUM_LIT> ; while ( & * It != & MI ) { if ( ! It -> isDebugValue ( ) ) ++ NumInstsToDef ; ++ It ; } if ( NumInstsToDef > MaxNumOfInstsBetweenNewValueStoreAndTFR ) continue ; PotentiallyNewifiableTFR . insert ( DefInst ) ; } continue ; } for ( MachineOperand & Op : MI . operands ( ) ) { if ( Op . isReg ( ) ) { if ( ! Op . isDef ( ) || ! Op . getReg ( ) ) continue ; unsigned Reg = Op . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { for ( MCSubRegIterator SubRegs ( Reg , TRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) LastDef [ * SubRegs ] = & MI ; } else if ( <STR_LIT> . contains ( Reg ) ) LastDef [ Reg ] = & MI ; } else if ( Op . isRegMask ( ) ) {


<s> bool <ISA_LIT>CopyToCombine :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; if ( IsCombinesDisabled ) return false ; bool HasChanged = false ; ST = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = ST -> getInstrInfo ( ) ; const Function * F = MF . getFunction ( ) ; bool OptForSize = F -> hasFnAttribute ( Attribute :: OptimizeForSize ) ;

ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ;


<s> if ( ! AllowC64 ) { if ( isGreaterThanNBitTFRI < <NUM_LIT> > ( HighRegInst ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( LowRegInst ) ) return false ; }

if ( isGreaterThanNBitTFRI < <NUM_LIT> > ( HighRegInst ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( LowRegInst ) ) return ( HighRegInst -> getOperand ( <NUM_LIT> ) . isImm ( ) && LowRegInst -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ;


<s> } if ( isGreaterThanNBitTFRI < <NUM_LIT> > ( HighRegInst ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( LowRegInst ) ) return ( HighRegInst -> getOperand ( <NUM_LIT> ) . isImm ( ) && LowRegInst -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ;

if ( isGreaterThanNBitTFRI < <NUM_LIT> > ( HighRegInst ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( LowRegInst ) ) return false ;


<s> if ( ( MachineInstr * ) MI == I2 ) ++ MI ; unsigned I1DestReg = I1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned I2DestReg = I2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsI1Loreg = ( I2DestReg - I1DestReg ) == <NUM_LIT> ; unsigned LoRegDef = IsI1Loreg ? I1DestReg : I2DestReg ; unsigned DoubleRegDest = TRI -> getMatchingSuperReg ( LoRegDef , <STR_LIT> , & <STR_LIT> ) ; assert ( DoubleRegDest != <NUM_LIT> && <STR_LIT> ) ; MachineOperand & LoOperand = IsI1Loreg ? I1 -> getOperand ( <NUM_LIT> ) : I2 -> getOperand ( <NUM_LIT> ) ; MachineOperand & HiOperand = IsI1Loreg ? I2 -> getOperand ( <NUM_LIT> ) : I1 -> getOperand ( <NUM_LIT> ) ; bool IsHiReg = HiOperand . isReg ( ) ; bool IsLoReg = LoOperand . isReg ( ) ; bool IsC64 = OptForSize && LoOperand . isImm ( ) && HiOperand . isImm ( ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I1 ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I2 ) ; MachineBasicBlock :: iterator InsertPt ( DoInsertAtI1 ? I1 : I2 ) ; if ( IsHiReg && IsLoReg ) emitCombineRR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsHiReg ) emitCombineRI ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ;

else if ( IsLoReg ) emitCombineIR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ;


<s> while ( I2 -> isDebugValue ( ) ) ++ I2 ; unsigned I1DestReg = I1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineBasicBlock :: iterator End = I1 -> getParent ( ) -> end ( ) ; I2 != End ; ++ I2 ) { if ( I2 -> modifiesRegister ( I1DestReg , TRI ) ) break ; if ( ! isCombinableInstType ( I2 , TII , ShouldCombineAggressively ) ) continue ;

if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( I2 ) ) continue ;


<s> } continue ; } for ( unsigned I = <NUM_LIT> , E = MI -> getNumOperands ( ) ; I != E ; ++ I ) { MachineOperand & Op = MI -> getOperand ( I ) ; if ( ! Op . isReg ( ) || ! Op . isDef ( ) || ! Op . getReg ( ) ) continue ; unsigned Reg = Op . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { for ( MCSubRegIterator SubRegs ( Reg , TRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) { LastDef [ * SubRegs ] = MI ; } } else if ( <STR_LIT> . contains ( Reg ) ) LastDef [ Reg ] = MI ; } }


<s> if ( TII -> mayBeNewStore ( MI ) ) { for ( unsigned OpdIdx = <NUM_LIT> , OpdE = MI -> getNumOperands ( ) ; OpdIdx != OpdE ; ++ OpdIdx ) { MachineOperand & Op = MI -> getOperand ( OpdIdx ) ; if ( ! Op . isReg ( ) || ! Op . isUse ( ) || ! Op . getReg ( ) ) continue ; unsigned Reg = Op . getReg ( ) ; MachineInstr * DefInst = LastDef [ Reg ] ; if ( ! DefInst ) continue ; if ( ! isCombinableInstType ( DefInst , TII , ShouldCombineAggressively ) ) continue ; MachineBasicBlock :: iterator It ( DefInst ) ; unsigned NumInstsToDef = <NUM_LIT> ; while ( & * It != MI ) { if ( ! It -> isDebugValue ( ) ) ++ NumInstsToDef ; ++ It ; } if ( NumInstsToDef > MaxNumOfInstsBetweenNewValueStoreAndTFR ) continue ; PotentiallyNewifiableTFR . insert ( DefInst ) ; } continue ; } for ( unsigned I = <NUM_LIT> , E = MI -> getNumOperands ( ) ; I != E ; ++ I ) { MachineOperand & Op = MI -> getOperand ( I ) ; if ( ! Op . isReg ( ) || ! Op . isDef ( ) || ! Op . getReg ( ) ) continue ; unsigned Reg = Op . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { for ( MCSubRegIterator SubRegs ( Reg , TRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) { LastDef [ * SubRegs ] = MI ; } } else if ( <STR_LIT> . contains ( Reg ) ) LastDef [ Reg ] = MI ; } }


<s> if ( I -> isDebugValue ( ) ) continue ; if ( isUnsafeToMoveAcross ( & * I , I2UseReg , I2DestReg , TRI ) ) { isSafe = false ; break ; } if ( ! KillingInstr && KilledOperand && I -> readsRegister ( KilledOperand , TRI ) ) KillingInstr = & * I ; } if ( isSafe ) { if ( KillingInstr ) { bool Added = KillingInstr -> addRegisterKilled ( KilledOperand , TRI , true ) ; ( void ) Added ; assert ( Added && <STR_LIT> ) ; removeKillInfo ( I2 , KilledOperand ) ; } DoInsertAtI1 = true ; return true ; } } { MachineBasicBlock :: iterator I ( I1 ) , End ( I2 ) ; if ( ! ShouldCombineAggressively ) End = std :: next ( MachineBasicBlock :: iterator ( I2 ) ) ; unsigned I1UseReg = UseReg ( I1 -> getOperand ( <NUM_LIT> ) ) ; MachineInstr * KillingInstr = nullptr ; unsigned KilledOperand = <NUM_LIT> ; while ( ++ I != End ) { if ( I -> isDebugValue ( ) ) { if ( I -> readsRegister ( I1DestReg , TRI ) ) DbgMItoMove . push_back ( I ) ; continue ; }

if ( isUnsafeToMoveAcross ( I , I1UseReg , I1DestReg , TRI ) || ( ! I -> killsRegister ( I1UseReg ) && I -> killsRegister ( I1UseReg , TRI ) ) ) return false ;


<s> bool HasChanged = false ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const Function * F = MF . getFunction ( ) ; bool OptForSize = F -> hasFnAttribute ( Attribute :: OptimizeForSize ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( * BI ) ; for ( MachineBasicBlock :: iterator MI = BI -> begin ( ) , End = BI -> end ( ) ; MI != End ; ) { MachineInstr * I1 = MI ++ ; if ( I1 -> isDebugValue ( ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( I1 ) ) continue ; if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ; bool DoInsertAtI1 = false ; DbgMItoMove . clear ( ) ; MachineInstr * I2 = findPairable ( I1 , DoInsertAtI1 , OptForSize ) ; if ( I2 ) { HasChanged = true ; combine ( I1 , I2 , MI , DoInsertAtI1 , OptForSize ) ;


<s> } if ( NumInstsToDef > MaxNumOfInstsBetweenNewValueStoreAndTFR ) continue ; PotentiallyNewifiableTFR . insert ( DefInst ) ; } continue ; } for ( unsigned I = <NUM_LIT> , E = MI . getNumOperands ( ) ; I != E ; ++ I ) { MachineOperand & Op = MI . getOperand ( I ) ; if ( ! Op . isReg ( ) || ! Op . isDef ( ) || ! Op . getReg ( ) ) continue ; unsigned Reg = Op . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { for ( MCSubRegIterator SubRegs ( Reg , TRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) { LastDef [ * SubRegs ] = & MI ; } } else if ( <STR_LIT> . contains ( Reg ) ) LastDef [ Reg ] = & MI ; } }


<s> if ( ! isCombinableInstType ( * DefInst , TII , ShouldCombineAggressively ) ) continue ; MachineBasicBlock :: iterator It ( DefInst ) ; unsigned NumInstsToDef = <NUM_LIT> ; while ( & * It != & MI ) { if ( ! It -> isDebugValue ( ) ) ++ NumInstsToDef ; ++ It ; } if ( NumInstsToDef > MaxNumOfInstsBetweenNewValueStoreAndTFR ) continue ; PotentiallyNewifiableTFR . insert ( DefInst ) ; } continue ; } for ( unsigned I = <NUM_LIT> , E = MI . getNumOperands ( ) ; I != E ; ++ I ) { MachineOperand & Op = MI . getOperand ( I ) ; if ( ! Op . isReg ( ) || ! Op . isDef ( ) || ! Op . getReg ( ) ) continue ; unsigned Reg = Op . getReg ( ) ;


<s> unsigned I2DestReg = I2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsI1LowReg = ( I2DestReg - I1DestReg ) == <NUM_LIT> ; bool IsI2LowReg = ( I1DestReg - I2DestReg ) == <NUM_LIT> ; unsigned FirstRegIndex = IsI1LowReg ? I1DestReg : I2DestReg ; if ( ( ! IsI1LowReg && ! IsI2LowReg ) || ! isEvenReg ( FirstRegIndex ) ) continue ; if ( ( IsI2LowReg && ! areCombinableOperations ( TRI , I1 , I2 ) ) || ( IsI1LowReg && ! areCombinableOperations ( TRI , I2 , I1 ) ) ) break ; if ( isSafeToMoveTogether ( I1 , I2 , I1DestReg , I2DestReg , DoInsertAtI1 ) ) return I2 ;


<s> if ( ( ! IsI1LowReg && ! IsI2LowReg ) || ! isEvenReg ( FirstRegIndex ) ) continue ; if ( ( IsI2LowReg && ! areCombinableOperations ( TRI , I1 , I2 ) ) || ( IsI1LowReg && ! areCombinableOperations ( TRI , I2 , I1 ) ) ) break ; if ( isSafeToMoveTogether ( I1 , I2 , I1DestReg , I2DestReg , DoInsertAtI1 ) ) return I2 ;


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> const char * getPassName ( ) const { return <STR_LIT> ;


<s> const char * getPassName ( ) const {


<s> removeKillInfo ( I2 , KilledOperand ) ; } DoInsertAtI1 = true ; return true ; } } { MachineBasicBlock :: iterator I ( I1 ) , End ( I2 ) ; if ( ! ShouldCombineAggressively ) End = std :: next ( MachineBasicBlock :: iterator ( I2 ) ) ; IsImmUseReg = I1 -> getOperand ( <NUM_LIT> ) . isImm ( ) || I1 -> getOperand ( <NUM_LIT> ) . isGlobal ( ) ; unsigned I1UseReg = IsImmUseReg ? <NUM_LIT> : I1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * KillingInstr = <NUM_LIT> ; unsigned KilledOperand = <NUM_LIT> ; while ( ++ I != End ) { if ( isUnsafeToMoveAcross ( I , I1UseReg , I1DestReg , TRI ) || ( ! I -> killsRegister ( I1UseReg ) && I -> killsRegister ( I1UseReg , TRI ) ) ) return false ; if ( I1UseReg && I -> killsRegister ( I1UseReg ) ) { assert ( KillingInstr == <NUM_LIT> && <STR_LIT> ) ;


<s> } unsigned DoubleRegDest = TRI -> getMatchingSuperReg ( LoRegDef , <STR_LIT> , SuperRC ) ; assert ( DoubleRegDest != <NUM_LIT> && <STR_LIT> ) ; MachineOperand & LoOperand = IsI1Loreg ? I1 . getOperand ( <NUM_LIT> ) : I2 . getOperand ( <NUM_LIT> ) ; MachineOperand & HiOperand = IsI1Loreg ? I2 . getOperand ( <NUM_LIT> ) : I1 . getOperand ( <NUM_LIT> ) ; bool IsHiReg = HiOperand . isReg ( ) ; bool IsLoReg = LoOperand . isReg ( ) ; bool IsC64 = OptForSize && LoOperand . isImm ( ) && HiOperand . isImm ( ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I1 ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I2 ) ; MachineBasicBlock :: iterator InsertPt ( DoInsertAtI1 ? I1 : I2 ) ; if ( IsHiReg && IsLoReg ) emitCombineRR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsHiReg ) emitCombineRI ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsLoReg ) emitCombineIR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsC64 && ! IsConst64Disabled ) emitConst64 ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else emitCombineII ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; if ( ! DoInsertAtI1 && DbgMItoMove . size ( ) != <NUM_LIT> ) { MachineBasicBlock * BB = InsertPt -> getParent ( ) ;


<s> unsigned LoRegKillFlag = getKillRegState ( LoOperand . isKill ( ) ) ; unsigned HiRegKillFlag = getKillRegState ( HiOperand . isKill ( ) ) ; unsigned LoReg = LoOperand . getReg ( ) ; unsigned HiReg = HiOperand . getReg ( ) ; DebugLoc DL = InsertPt -> getDebugLoc ( ) ; MachineBasicBlock * BB = InsertPt -> getParent ( ) ; unsigned NewOpc ; if ( <STR_LIT> . contains ( DoubleDestReg ) ) { NewOpc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DoubleDestReg ) ) { assert ( ST -> useHVXOps ( ) ) ; if ( ST -> useHVXSglOps ( ) ) NewOpc = <STR_LIT> ; else NewOpc = <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( * BB , InsertPt , DL , TII -> get ( NewOpc ) , DoubleDestReg ) . addReg ( HiReg , HiRegKillFlag ) . addReg ( LoReg , LoRegKillFlag ) ;


<s> MachineInstr * <ISA_LIT>CopyToCombine :: findPairable ( MachineInstr & I1 , bool & DoInsertAtI1 , bool AllowC64 ) { MachineBasicBlock :: iterator I2 = std :: next ( MachineBasicBlock :: iterator ( I1 ) ) ; if ( I2 != I1 . getParent ( ) -> end ( ) ) while ( I2 -> isDebugValue ( ) ) ++ I2 ; unsigned I1DestReg = I1 . getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineBasicBlock :: iterator End = I1 . getParent ( ) -> end ( ) ; I2 != End ; ++ I2 ) { if ( I2 -> modifiesRegister ( I1DestReg , TRI ) ) break ; if ( ! isCombinableInstType ( * I2 , TII , ShouldCombineAggressively ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & * I2 ) ) continue ; unsigned I2DestReg = I2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsI1LowReg = ( I2DestReg - I1DestReg ) == <NUM_LIT> ;


<s> assert ( Op0 . isReg ( ) ) ; unsigned DestReg = Op0 . getReg ( ) ; if ( ! Op1 . isImm ( ) && Op1 . getTargetFlags ( ) != <STR_LIT> ) return false ; bool NotExt = Op1 . isImm ( ) && isInt < <NUM_LIT> > ( Op1 . getImm ( ) ) ; return <STR_LIT> . contains ( DestReg ) && ( ShouldCombineAggressively || NotExt ) ; } case <STR_LIT> : case <STR_LIT> : return true ; default :


<s> if ( <STR_LIT> . contains ( Reg ) ) return ( Reg - <STR_LIT> ) % <NUM_LIT> == <NUM_LIT> ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) return ( Reg - <STR_LIT> ) % <NUM_LIT> == <NUM_LIT> ; llvm_unreachable ( <STR_LIT> ) ;


<s> assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) ; if ( <STR_LIT> . contains ( Reg ) ) return ( Reg - <STR_LIT> ) % <NUM_LIT> == <NUM_LIT> ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) return ( Reg - <STR_LIT> ) % <NUM_LIT> == <NUM_LIT> ; llvm_unreachable ( <STR_LIT> ) ;


<s> MI != End ; ) { MachineInstr & I1 = * MI ++ ; if ( I1 . isDebugValue ( ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & I1 ) ) continue ; if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ; bool DoInsertAtI1 = false ; DbgMItoMove . clear ( ) ; MachineInstr * I2 = findPairable ( I1 , DoInsertAtI1 , OptForSize ) ; if ( I2 ) { HasChanged = true ; combine ( I1 , * I2 , MI , DoInsertAtI1 , OptForSize ) ; } }


<s> const Function * F = MF . getFunction ( ) ; bool OptForSize = F -> hasFnAttribute ( Attribute :: OptimizeForSize ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { PotentiallyNewifiableTFR . clear ( ) ;


<s> if ( I -> isDebugInstr ( ) ) continue ; if ( isUnsafeToMoveAcross ( * I , I2UseReg , I2DestReg , TRI ) ) { isSafe = false ; break ; } if ( ! KillingInstr && KilledOperand && I -> readsRegister ( KilledOperand , TRI ) ) KillingInstr = & * I ; } if ( isSafe ) { if ( KillingInstr ) { bool Added = KillingInstr -> addRegisterKilled ( KilledOperand , TRI , true ) ; ( void ) Added ; assert ( Added && <STR_LIT> ) ; removeKillInfo ( I2 , KilledOperand ) ; } DoInsertAtI1 = true ; return true ; } } { MachineBasicBlock :: iterator I ( I1 ) , End ( I2 ) ; if ( ! ShouldCombineAggressively ) End = std :: next ( MachineBasicBlock :: iterator ( I2 ) ) ; Register I1UseReg = UseReg ( I1 . getOperand ( <NUM_LIT> ) ) ; MachineInstr * KillingInstr = nullptr ; unsigned KilledOperand = <NUM_LIT> ; while ( ++ I != End ) { MachineInstr & MI = * I ; if ( MI . isDebugInstr ( ) ) { if ( MI . readsRegister ( I1DestReg , TRI ) ) DbgMItoMove . push_back ( & MI ) ; continue ; } if ( isUnsafeToMoveAcross ( MI , I1UseReg , I1DestReg , TRI ) || ( ! MI . killsRegister ( I1UseReg ) && MI . killsRegister ( I1UseReg , TRI ) ) ) return false ; if ( I1UseReg && MI . killsRegister ( I1UseReg ) ) { assert ( ! KillingInstr && <STR_LIT> ) ; KilledOperand = I1UseReg ; KillingInstr = & MI ; } } if ( KillingInstr ) { removeKillInfo ( * KillingInstr , KilledOperand ) ; bool Added = I1 . addRegisterKilled ( KilledOperand , TRI ) ; ( void ) Added ; assert ( Added && <STR_LIT> ) ;


<s> PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( * BI ) ; for ( MachineBasicBlock :: iterator MI = BI -> begin ( ) , End = BI -> end ( ) ; MI != End ; ) { MachineInstr & I1 = * MI ++ ; if ( I1 . isDebugValue ( ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & I1 ) ) continue ; if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ; bool DoInsertAtI1 = false ; DbgMItoMove . clear ( ) ; MachineInstr * I2 = findPairable ( I1 , DoInsertAtI1 , OptForSize ) ; if ( I2 ) { HasChanged = true ; combine ( I1 , * I2 , MI , DoInsertAtI1 , OptForSize ) ; } } } return HasChanged ;


<s> for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( * BI ) ; for ( MachineBasicBlock :: iterator MI = BI -> begin ( ) , End = BI -> end ( ) ; MI != End ; ) { MachineInstr & I1 = * MI ++ ; if ( I1 . isDebugValue ( ) ) continue ;

if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & I1 ) ) continue ;


<s> static bool areCombinableOperations ( const TargetRegisterInfo * TRI , MachineInstr * HighRegInst , MachineInstr * LowRegInst ) {

assert ( ( HighRegInst -> getOpcode ( ) == <STR_LIT> || HighRegInst -> getOpcode ( ) == <STR_LIT> || HighRegInst -> getOpcode ( ) == <STR_LIT> ) && ( LowRegInst -> getOpcode ( ) == <STR_LIT> || LowRegInst -> getOpcode ( ) == <STR_LIT> || LowRegInst -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ;


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : { assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ; } case <STR_LIT> : { const MachineOperand & Op0 = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & Op1 = MI -> getOperand ( <NUM_LIT> ) ; assert ( Op0 . isReg ( ) ) ; unsigned DestReg = Op0 . getReg ( ) ; if ( ! Op1 . isImm ( ) && Op1 . getTargetFlags ( ) != <STR_LIT> ) return false ; bool NotExt = Op1 . isImm ( ) && isInt < <NUM_LIT> > ( Op1 . getImm ( ) ) ;

return <STR_LIT> . contains ( DestReg ) && ( ShouldCombineAggressively || NotExt ) ;


<s> if ( ! Op1 . isImm ( ) && Op1 . getTargetFlags ( ) != <STR_LIT> ) return false ; bool NotExt = Op1 . isImm ( ) && isInt < <NUM_LIT> > ( Op1 . getImm ( ) ) ; return <STR_LIT> . contains ( DestReg ) && ( ShouldCombineAggressively || NotExt ) ; } case <STR_LIT> : { if ( ! ShouldCombineAggressively ) return false ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isGlobal ( ) ) ; if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> ) return false ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) ; } default : break ; }


<s> if ( ! QRI -> Subtarget . hasV4TOps ( ) ) return HighRegInst -> getOpcode ( ) == LowRegInst -> getOpcode ( ) && ! isGreaterThan8BitTFRI ( HighRegInst ) && ! isGreaterThan6BitTFRI ( LowRegInst ) ; if ( ( HighRegInst -> getOpcode ( ) == <STR_LIT> || isGreaterThan8BitTFRI ( HighRegInst ) ) && ( LowRegInst -> getOpcode ( ) == <STR_LIT> || isGreaterThan6BitTFRI ( LowRegInst ) ) ) return false ;


<s> MachineBasicBlock * BB = InsertPt -> getParent ( ) ; if ( HiOperand . isGlobal ( ) ) { BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addGlobalAddress ( HiOperand . getGlobal ( ) , HiOperand . getOffset ( ) , HiOperand . getTargetFlags ( ) ) . addImm ( LoOperand . getImm ( ) ) ; return ; } if ( LoOperand . isGlobal ( ) ) { BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addImm ( HiOperand . getImm ( ) ) . addGlobalAddress ( LoOperand . getGlobal ( ) , LoOperand . getOffset ( ) , LoOperand . getTargetFlags ( ) ) ; return ; } if ( ! isInt < <NUM_LIT> > ( HiOperand . getImm ( ) ) ) { assert ( isInt < <NUM_LIT> > ( LoOperand . getImm ( ) ) ) ; BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addImm ( HiOperand . getImm ( ) ) . addImm ( LoOperand . getImm ( ) ) ;


<s> unsigned LoRegKillFlag = getKillRegState ( LoOperand . isKill ( ) ) ; DebugLoc DL = InsertPt -> getDebugLoc ( ) ; MachineBasicBlock * BB = InsertPt -> getParent ( ) ; if ( HiOperand . isGlobal ( ) ) { BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addGlobalAddress ( HiOperand . getGlobal ( ) , HiOperand . getOffset ( ) , HiOperand . getTargetFlags ( ) ) . addReg ( LoReg , LoRegKillFlag ) ;


<s> unsigned HiRegKillFlag = getKillRegState ( HiOperand . isKill ( ) ) ; unsigned HiReg = HiOperand . getReg ( ) ; DebugLoc DL = InsertPt -> getDebugLoc ( ) ; MachineBasicBlock * BB = InsertPt -> getParent ( ) ; if ( LoOperand . isGlobal ( ) ) {

BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addReg ( HiReg , HiRegKillFlag ) . addGlobalAddress ( LoOperand . getGlobal ( ) , LoOperand . getOffset ( ) , LoOperand . getTargetFlags ( ) ) ;


<s> unsigned HiRegKillFlag = getKillRegState ( HiOperand . isKill ( ) ) ; unsigned HiReg = HiOperand . getReg ( ) ; DebugLoc DL = InsertPt -> getDebugLoc ( ) ; MachineBasicBlock * BB = InsertPt -> getParent ( ) ; if ( LoOperand . isGlobal ( ) ) { BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addReg ( HiReg , HiRegKillFlag ) . addGlobalAddress ( LoOperand . getGlobal ( ) , LoOperand . getOffset ( ) , LoOperand . getTargetFlags ( ) ) ; return ; } BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addReg ( HiReg , HiRegKillFlag ) . addImm ( LoOperand . getImm ( ) ) ;


<s> void <ISA_LIT>CopyToCombine :: emitCombineRR ( MachineBasicBlock :: iterator & InsertPt , unsigned DoubleDestReg , MachineOperand & HiOperand , MachineOperand & LoOperand ) { unsigned LoRegKillFlag = getKillRegState ( LoOperand . isKill ( ) ) ; unsigned HiRegKillFlag = getKillRegState ( HiOperand . isKill ( ) ) ; unsigned LoReg = LoOperand . getReg ( ) ; unsigned HiReg = HiOperand . getReg ( ) ; DebugLoc DL = InsertPt -> getDebugLoc ( ) ;

MachineBasicBlock * BB = InsertPt -> getParent ( ) ;


<s> DebugLoc DL = InsertPt -> getDebugLoc ( ) ; MachineBasicBlock * BB = InsertPt -> getParent ( ) ; BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addReg ( HiReg , HiRegKillFlag ) . addReg ( LoReg , LoRegKillFlag ) ;


<s> } case <STR_LIT> : { assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) && ( ShouldCombineAggressively || isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; } case <STR_LIT> : { if ( ! ShouldCombineAggressively ) return false ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isGlobal ( ) ) ;

if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> ) return false ;


<s> unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ; } case <STR_LIT> : { assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) && ( ShouldCombineAggressively || isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; } case <STR_LIT> : { if ( ! ShouldCombineAggressively ) return false ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isGlobal ( ) ) ; if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> ) return false ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) ; } default :


<s> return I -> getOpcode ( ) == <STR_LIT> && ! isUInt < <NUM_LIT> > ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> return I -> getOpcode ( ) == <STR_LIT> && ! isInt < <NUM_LIT> > ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> bool Added = KillingInstr -> addRegisterKilled ( KilledOperand , TRI , true ) ; ( void ) Added ; assert ( Added && <STR_LIT> ) ; removeKillInfo ( I2 , KilledOperand ) ; } DoInsertAtI1 = true ; return true ; } } { MachineBasicBlock :: iterator I ( I1 ) , End ( I2 ) ; if ( ! ShouldCombineAggressively ) End = std :: next ( MachineBasicBlock :: iterator ( I2 ) ) ; IsImmUseReg = I1 -> getOperand ( <NUM_LIT> ) . isImm ( ) || I1 -> getOperand ( <NUM_LIT> ) . isGlobal ( ) ; unsigned I1UseReg = IsImmUseReg ? <NUM_LIT> : I1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * KillingInstr = nullptr ; unsigned KilledOperand = <NUM_LIT> ; while ( ++ I != End ) { if ( isUnsafeToMoveAcross ( I , I1UseReg , I1DestReg , TRI ) || ( ! I -> killsRegister ( I1UseReg ) && I -> killsRegister ( I1UseReg , TRI ) ) ) return false ; if ( I1UseReg && I -> killsRegister ( I1UseReg ) ) { assert ( ! KillingInstr && <STR_LIT> ) ; KilledOperand = I1UseReg ; KillingInstr = & * I ; } } if ( KillingInstr ) { removeKillInfo ( KillingInstr , KilledOperand ) ;

bool Added = I1 -> addRegisterKilled ( KilledOperand , TRI ) ;


<s> bool <ISA_LIT>CopyToCombine :: runOnMachineFunction ( MachineFunction & MF ) { if ( IsCombinesDisabled ) return false ; bool HasChanged = false ; TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( * BI ) ; for ( MachineBasicBlock :: iterator MI = BI -> begin ( ) , End = BI -> end ( ) ; MI != End ; ) { MachineInstr * I1 = MI ++ ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( I1 ) ) continue ; if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ;


<s> return StringSwitch < Optional < <STR_LIT> >> ( CPU ) . Case ( <STR_LIT> , <STR_LIT> :: V5 ) . Case ( <STR_LIT> , <STR_LIT> :: V5 ) . Case ( <STR_LIT> , <STR_LIT> :: V55 ) . Case ( <STR_LIT> , <STR_LIT> :: V60 ) . Case ( <STR_LIT> , <STR_LIT> :: V62 ) . Case ( <STR_LIT> , <STR_LIT> :: V65 ) . Case ( <STR_LIT> , <STR_LIT> :: V66 ) . Case ( <STR_LIT> , <STR_LIT> :: V67 ) . Case ( <STR_LIT> , <STR_LIT> :: V67 ) . Case ( <STR_LIT> , <STR_LIT> :: V68 ) . Case ( <STR_LIT> , <STR_LIT> :: V69 ) . Default ( None ) ;


<s> static DecodeStatus s29_3ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ; return MCDisassembler :: Success ;


<s> static DecodeStatus s30_2ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ; return MCDisassembler :: Success ;


<s> static DecodeStatus s31_1ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) {

signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ;


<s> signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ; return MCDisassembler :: Success ;


<s> static DecodeStatus s3_0ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) {


<s> signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ;


<s> static DecodeStatus s4_3ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) {


<s> static DecodeStatus s6_0ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ;


<s> case <STR_LIT> :: tc_35fb9d13 : case <STR_LIT> :: tc_cbe45117 : return true ; default : return false ; }


<s> case <STR_LIT> :: tc_cbe45117 : return true ; default : return false ; }


<s> case <STR_LIT> :: tc_3bea1824 : case <STR_LIT> :: tc_e836c161 : case <STR_LIT> :: tc_f1aa2cdb : return true ; default :


<s> case <STR_LIT> :: tc_b4407292 : case <STR_LIT> :: tc_fc3999b4 : return true ; default : return false ; }


<s> inline bool is_TC4x ( unsigned SchedClass ) { switch ( SchedClass ) { case <STR_LIT> :: tc_2f7c551d : case <STR_LIT> :: tc_2ff964b4 :


<s> case <STR_LIT> :: tc_cbe45117 : return true ; default : return false ;


<s> switch ( SchedClass ) { case <STR_LIT> :: tc_35fb9d13 : case <STR_LIT> :: tc_cbe45117 : return true ; default : return false ; }


<s> case <STR_LIT> :: tc_a12a5971 : case <STR_LIT> :: tc_ae0722f7 : case <STR_LIT> :: tc_ae2c2dc2 : case <STR_LIT> :: tc_bc5561d8 : case <STR_LIT> :: tc_d6a805a8 : case <STR_LIT> :: tc_f055fbb6 : case <STR_LIT> :: tc_feb4974b : return true ; default : return false ;


<s> switch ( SchedClass ) { case <STR_LIT> :: tc_09c86199 : case <STR_LIT> :: tc_2d1e6f5c : case <STR_LIT> :: tc_2e55aa16 : case <STR_LIT> :: tc_3bea1824 :


<s> case <STR_LIT> :: tc_14cd4cfa : case <STR_LIT> :: tc_2a160009 : return true ;


<s> case <STR_LIT> :: tc_6792d5ff : case <STR_LIT> :: tc_9c00ce8d : case <STR_LIT> :: tc_d580173f : case <STR_LIT> :: tc_f3eaa14b : return true ; default : return false ; }


<s> switch ( SchedClass ) { case <STR_LIT> :: tc_45f9d1be : case <STR_LIT> :: tc_a4ee89db : return true ;


<s> case <STR_LIT> :: tc_7f7f45f5 : case <STR_LIT> :: tc_9783714b : case <STR_LIT> :: tc_9e72dc89 : case <STR_LIT> :: tc_9edb7c77 : case <STR_LIT> :: tc_f0e8e832 : case <STR_LIT> :: tc_f7569068 : return true ; default : return false ;


<s> DiagnosticLineInfo * create<ISA_LIT>DiagLineInfo ( const Target & pTarget , const std :: string & pTriple ) { return new DWARFLineInfo ( ) ;


<s> DiagnosticLineInfo * create<ISA_LIT>DiagLineInfo ( const Target & pTarget , const std :: string & pTriple ) {


<s> mcld :: TargetRegistry :: RegisterDiagnosticLineInfo ( mcld :: The<ISA_LIT>Target , mcld :: create<ISA_LIT>DiagLineInfo ) ;


<s> opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ;


<s> if ( Bits == <NUM_LIT> ) Bits = <NUM_LIT> ; uint32_t FullValue = fullValue ( * Disassembler . MCII , * * Disassembler . CurrentBundle , MI , SignExtend64 ( tmp , Bits ) ) ; int64_t Extended = SignExtend64 < <NUM_LIT> > ( FullValue ) + Address ;

if ( ! Disassembler . tryAddingSymbolicOperand ( MI , Extended , Address , true , <NUM_LIT> , <NUM_LIT> ) ) <ISA_LIT>MCInstrInfo :: addConstant ( MI , Extended , Disassembler . getContext ( ) ) ;


<s> int64_t Extended = SignExtend64 < <NUM_LIT> > ( FullValue ) + Address ;


<s> return disassembler ( Decoder ) . getContext ( ) ;


<s> static DecodeStatus DecodeCtrRegs64RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { static const MCPhysReg CtrlReg64DecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( RegNo >= array_lengthof ( CtrlReg64DecoderTable ) ) return MCDisassembler :: Fail ; if ( CtrlReg64DecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = CtrlReg64DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return MCDisassembler :: Success ;


if ( CtrlRegDecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ;


<s> Value |= ( ( insn & <NUM_LIT> ) << <NUM_LIT> ) ; MI . setOpcode ( <STR_LIT> ) ;

<ISA_LIT>MCInstrInfo :: addConstant ( MI , Value , contextFromDecoder ( Decoder ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Value = insn & UINT64_C ( <NUM_LIT> ) ; DecodeIntRegsRegisterClass ( MI , Value , <NUM_LIT> , nullptr ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; DecodePredRegsRegisterClass ( MI , Value , <NUM_LIT> , nullptr ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( Value ) ) ; break ; case ( <STR_LIT> ) : ++ shift ; case <STR_LIT> : case <STR_LIT> : ++ shift ; case <STR_LIT> : case <STR_LIT> : Value |= insn & UINT64_C ( <NUM_LIT> ) ; DecodeIntRegsRegisterClass ( MI , Value , <NUM_LIT> , nullptr ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( Value << shift ) ) ; break ; case <STR_LIT> : Value = insn & UINT64_C ( <NUM_LIT> ) ; DecodeDoubleRegsRegisterClass ( MI , Value , <NUM_LIT> , nullptr ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( Value << <NUM_LIT> ) ) ; break ; case <STR_LIT> : Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= insn & UINT64_C ( <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( Value << <NUM_LIT> ) ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; DecodeDoubleRegsRegisterClass ( MI , Value , <NUM_LIT> , nullptr ) ; break ; case <STR_LIT> : ++ shift ; case <STR_LIT> : ++ shift ; case <STR_LIT> : Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= insn & UINT64_C ( <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( Value << shift ) ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ;


<s> static DecodeStatus DecodeVecPredRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) {

static const MCPhysReg VecPredRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ;


<s> unsigned Alignment = <ISA_LIT>MCInstrInfo :: getExtentAlignment ( MCII , MI ) ; uint32_t Lower6 = static_cast < uint32_t > ( Value >> Alignment ) & <NUM_LIT> ; int64_t Bits ;

bool Success = Extender -> getOperand ( <NUM_LIT> ) . getExpr ( ) -> evaluateAsAbsolute ( Bits ) ;


<s> unsigned Alignment = <ISA_LIT>MCInstrInfo :: getExtentAlignment ( MCII , MI ) ; uint32_t Lower6 = static_cast < uint32_t > ( Value >> Alignment ) & <NUM_LIT> ; int64_t Bits ; bool Success = Extender -> getOperand ( <NUM_LIT> ) . getExpr ( ) -> evaluateAsAbsolute ( Bits ) ; assert ( Success ) ; ( void ) Success ;


<s> else if ( encoded_dreg < <NUM_LIT> ) return <STR_LIT> + encoded_dreg + <NUM_LIT> ; return <STR_LIT> ;


<s> Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } if ( Result == MCDisassembler :: Fail ) return Result ; <ISA_LIT>MCChecker Checker ( * MCII , STI , MI , MI , * getContext ( ) . getRegisterInfo ( ) ) ;

if ( ! Checker . check ( ) ) return MCDisassembler :: Fail ;


<s> DecodeStatus <ISA_LIT>Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { DecodeStatus Result = DecodeStatus :: Success ; bool Complete = false ; Size = <NUM_LIT> ; * CurrentBundle = & MI ; MI = <ISA_LIT>MCInstrInfo :: createBundle ( ) ; while ( Result == Success && ! Complete ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , os , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE ;

Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ;


<s> static unsigned getRegFromSubinstEncoding ( unsigned encoded_reg ) { if ( encoded_reg < <NUM_LIT> ) return <STR_LIT> + encoded_reg ; else if ( encoded_reg < <NUM_LIT> ) return <STR_LIT> + encoded_reg + <NUM_LIT> ;


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx , MCInstrInfo const * MCII ) : MCDisassembler ( STI , Ctx ) , MCII ( MCII ) , CurrentBundle ( new MCInst * ) {


<s> signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ; return MCDisassembler :: Success ;


<s> static DecodeStatus s11_1ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { <ISA_LIT>MCInstrInfo :: addConstant ( MI , SignExtend64 < <NUM_LIT> > ( tmp ) , contextFromDecoder ( Decoder ) ) ; return MCDisassembler :: Success ;


<s> static DecodeStatus s11_3ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ; return MCDisassembler :: Success ;


<s> static DecodeStatus s12_0ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ; return MCDisassembler :: Success ;


<s> signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ;


<s> static DecodeStatus s4_0ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ;


<s> static DecodeStatus s4_1ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ; return MCDisassembler :: Success ;


<s> static DecodeStatus s4_3ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ;


<s> static DecodeStatus s6_0ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) {


<s> int64_t Extended = SignExtend64 < <NUM_LIT> > ( FullValue ) ;

<ISA_LIT>MCInstrInfo :: addConstant ( MI , Extended , Disassembler . getContext ( ) ) ;


<s> <ISA_LIT>Disassembler const & Disassembler = disassembler ( Decoder ) ; int64_t FullValue = fullValue ( * Disassembler . MCII , * * Disassembler . CurrentBundle , MI , tmp ) ;

assert ( FullValue >= <NUM_LIT> && <STR_LIT> ) ;


<s> static DecodeStatus DecodeHvxWRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { static const MCPhysReg HvxWRDecoderTable [ ] = {


<s> SA0 , LC0 , SA1 , LC1 , P3_0 , C5 , C6 , C7 , USR , PC , UGP , GP , CS0 , CS1 , UPCYCLELO , UPCYCLEHI , FRAMELIMIT , FRAMEKEY , PKTCOUNTLO , PKTCOUNTHI , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , UTIMERLO , UTIMERHI } ; if ( RegNo >= array_lengthof ( CtrlRegDecoderTable ) ) return MCDisassembler :: Fail ; static_assert ( NoRegister == <NUM_LIT> , <STR_LIT> ) ; if ( CtrlRegDecoderTable [ RegNo ] == NoRegister ) return MCDisassembler :: Fail ; unsigned Register = CtrlRegDecoderTable [ RegNo ] ;

Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


<s> static const MCPhysReg CtrlRegDecoderTable [ ] = { SA0 , LC0 , SA1 , LC1 , P3_0 , C5 , C6 , C7 , USR , PC , UGP , GP , CS0 , CS1 , UPCYCLELO , UPCYCLEHI , FRAMELIMIT , FRAMEKEY , PKTCOUNTLO , PKTCOUNTHI , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , UTIMERLO , UTIMERHI } ; if ( RegNo >= array_lengthof ( CtrlRegDecoderTable ) ) return MCDisassembler :: Fail ; static_assert ( NoRegister == <NUM_LIT> , <STR_LIT> ) ; if ( CtrlRegDecoderTable [ RegNo ] == NoRegister ) return MCDisassembler :: Fail ; unsigned Register = CtrlRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return MCDisassembler :: Success ;


<s> <ISA_LIT>Disassembler const & disassembler ( void const * Decoder ) { return * static_cast < <ISA_LIT>Disassembler const * > ( Decoder ) ;


<s> bool Success = Extender -> getOperand ( <NUM_LIT> ) . getExpr ( ) -> evaluateAsAbsolute ( Bits ) ; assert ( Success ) ; ( void ) Success ; uint32_t Upper26 = static_cast < uint32_t > ( Bits ) ; uint32_t Operand = Upper26 | Lower6 ; return Operand ;


<s> MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , os , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } if ( Result == MCDisassembler :: Fail ) return Result ; if ( Size > HEXAGON_MAX_PACKET_SIZE ) return MCDisassembler :: Fail ; <ISA_LIT>MCChecker Checker ( * MCII , STI , MI , MI , * getContext ( ) . getRegisterInfo ( ) ) ;


<s> MI = <ISA_LIT>MCInstrInfo :: createBundle ( ) ; while ( Result == Success && ! Complete ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , os , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE ;


<s> break ; case <NUM_LIT> : DecodeLow = DecoderTableSUBINSN_S232 ; DecodeHigh = DecoderTableSUBINSN_S232 ; break ; } MI . setOpcode ( <STR_LIT> + duplexIClass ) ; MCInst * MILow = new ( getContext ( ) ) MCInst ; MCInst * MIHigh = new ( getContext ( ) ) MCInst ; Result = decodeInstruction ( DecodeLow , * MILow , Instruction & <NUM_LIT> , Address , this , STI ) ; if ( Result != DecodeStatus :: Success ) return DecodeStatus :: Fail ; adjustDuplex ( * MILow , getContext ( ) ) ; Result = decodeInstruction ( DecodeHigh , * MIHigh , ( Instruction >> <NUM_LIT> ) & <NUM_LIT> , Address , this , STI ) ; if ( Result != DecodeStatus :: Success ) return DecodeStatus :: Fail ; adjustDuplex ( * MIHigh , getContext ( ) ) ; MCOperand OPLow = MCOperand :: createInst ( MILow ) ; MCOperand OPHigh = MCOperand :: createInst ( MIHigh ) ; MI . addOperand ( OPLow ) ; MI . addOperand ( OPHigh ) ; Complete = true ; } else { if ( ( Instruction & <STR_LIT> ) == <STR_LIT> ) Complete = true ; if ( Extender != nullptr ) Result = decodeInstruction ( DecoderTableMustExtend32 , MI , Instruction , Address , this , STI ) ; if ( Result != MCDisassembler :: Success ) Result = decodeInstruction ( DecoderTable32 , MI , Instruction , Address , this , STI ) ; if ( Result != MCDisassembler :: Success && STI . getFeatureBits ( ) [ <STR_LIT> ] ) Result = decodeInstruction ( DecoderTableEXT_mmvec32 , MI , Instruction , Address , this , STI ) ; } switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MI . insert ( MI . begin ( ) + <NUM_LIT> , MCOperand :: createExpr ( MCConstantExpr :: create ( - <NUM_LIT> , getContext ( ) ) ) ) ;


<s> void signedDecoder ( MCInst & MI , unsigned tmp , const void * Decoder ) { <ISA_LIT>Disassembler const & Disassembler = disassembler ( Decoder ) ;

int64_t FullValue = fullValue ( * Disassembler . MCII , * * Disassembler . CurrentBundle , MI , SignExtend64 < T > ( tmp ) ) ;


<s> uint32_t Extended = FullValue + Address ; if ( ! Disassembler . tryAddingSymbolicOperand ( MI , Extended , Address , true , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) <ISA_LIT>MCInstrInfo :: addConstant ( MI , Extended , Disassembler . getContext ( ) ) ; return MCDisassembler :: Success ;


<s> return new <ISA_LIT>Disassembler ( STI , Ctx ) ;


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( RegNo >= sizeof ( CtrlReg64DecoderTable ) / sizeof ( CtrlReg64DecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ; if ( CtrlReg64DecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = CtrlReg64DecoderTable [ RegNo ] ;

Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ;


<s> if ( RegNo >= sizeof ( CtrlReg64DecoderTable ) / sizeof ( CtrlReg64DecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ; if ( CtrlReg64DecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = CtrlReg64DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ; return MCDisassembler :: Success ;


<s> if ( RegNo >= sizeof ( CtrlRegDecoderTable ) / sizeof ( CtrlRegDecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ; if ( CtrlRegDecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = CtrlRegDecoderTable [ RegNo ] ;


<s> static DecodeStatus DecodeDoubleRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { static const uint16_t DoubleRegDecoderTable [ ] = {


<s> Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ; return MCDisassembler :: Success ;