<s> for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) if ( SUnits [ su ] . getDepth ( ) > maxD ) maxD = SUnits [ su ] . getDepth ( ) ; dbgs ( ) << <STR_LIT> << maxD << <STR_LIT> ; ) ; DEBUG ( for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) SUnits [ su ] . dumpAll ( this ) ) ; initQueues ( ) ; bool IsTopNode = false ; while ( SUnit * SU = SchedImpl -> pickNode ( IsTopNode ) ) { if ( ! checkSchedLimit ( ) ) break ; scheduleMI ( SU , IsTopNode ) ; updateQueues ( SU , IsTopNode ) ; } assert ( CurrentTop == CurrentBottom && <STR_LIT> ) ; placeDebugValues ( ) ;


<s> VLIWResourceModel ( const TargetSubtargetInfo & STI , const TargetSchedModel * SM ) : SchedModel ( SM ) { ResourcesModel = STI . getInstrInfo ( ) -> CreateTargetScheduleState ( STI ) ; assert ( ResourcesModel && <STR_LIT> ) ; Packet . resize ( SchedModel -> getIssueWidth ( ) ) ;


<s> ResourcesModel = STI . getInstrInfo ( ) -> CreateTargetScheduleState ( STI ) ; assert ( ResourcesModel && <STR_LIT> ) ; Packet . resize ( SchedModel -> getIssueWidth ( ) ) ; Packet . clear ( ) ; ResourcesModel -> clearResources ( ) ;


<s> VLIWSchedBoundary ( unsigned ID , const Twine & Name ) : Available ( ID , Name + <STR_LIT> ) , Pending ( ID << ConvergingVLIWScheduler :: LogMaxQID , Name + <STR_LIT> ) {


<s> Top . init ( DAG , SchedModel ) ; Bot . init ( DAG , SchedModel ) ; const InstrItineraryData * Itin = DAG -> getSchedModel ( ) -> getInstrItineraries ( ) ; const TargetMachine & TM = DAG -> MF . getTarget ( ) ; Top . HazardRec = TM . getInstrInfo ( ) -> CreateTargetMIHazardRecognizer ( Itin , DAG ) ;

Bot . HazardRec = TM . getInstrInfo ( ) -> CreateTargetMIHazardRecognizer ( Itin , DAG ) ;


<s> case TargetOpcode :: SUBREG_TO_REG : case TargetOpcode :: REG_SEQUENCE : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: COPY : case TargetOpcode :: INLINEASM : break ; } for ( unsigned i = <NUM_LIT> , e = Packet . size ( ) ; i != e ; ++ i ) { if ( Packet [ i ] -> Succs . size ( ) == <NUM_LIT> ) continue ; for ( SUnit :: const_succ_iterator I = Packet [ i ] -> Succs . begin ( ) , E = Packet [ i ] -> Succs . end ( ) ; I != E ; ++ I ) {


<s> startNewCycle = true ; } switch ( SU -> getInstr ( ) -> getOpcode ( ) ) { default : ResourcesModel -> reserveResources ( * SU -> getInstr ( ) ) ; break ; case TargetOpcode :: EXTRACT_SUBREG : case TargetOpcode :: INSERT_SUBREG : case TargetOpcode :: SUBREG_TO_REG : case TargetOpcode :: REG_SEQUENCE : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: CFI_INSTRUCTION : case TargetOpcode :: EH_LABEL : case TargetOpcode :: COPY : case TargetOpcode :: INLINEASM : break ; } Packet . push_back ( SU ) ; DEBUG ( dbgs ( ) << <STR_LIT> << TotalPackets << <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Packet . size ( ) ; i != e ; ++ i ) { DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> ) ; DEBUG ( dbgs ( ) << Packet [ i ] -> NodeNum << <STR_LIT> ) ; DEBUG ( Packet [ i ] -> getInstr ( ) -> dump ( ) ) ; } if ( Packet . size ( ) >= SchedModel -> getIssueWidth ( ) ) { ResourcesModel -> clearResources ( ) ; Packet . clear ( ) ; TotalPackets ++ ; startNewCycle = true ; } return startNewCycle ;


<s> DAG ( <NUM_LIT> ) , SchedModel ( <NUM_LIT> ) , TRI ( <NUM_LIT> ) , Top ( TopQID , <STR_LIT> ) , Bot ( BotQID , <STR_LIT> ) {


<s> Bot . HazardRec = TM . getSubtargetImpl ( ) -> getInstrInfo ( ) -> CreateTargetMIHazardRecognizer ( Itin , DAG ) ; delete Top . ResourceModel ; delete Bot . ResourceModel ; Top . ResourceModel = new VLIWResourceModel ( TM , DAG -> getSchedModel ( ) ) ; Bot . ResourceModel = new VLIWResourceModel ( TM , DAG -> getSchedModel ( ) ) ;

assert ( ( ! llvm :: ForceTopDown || ! llvm :: ForceBottomUp ) && <STR_LIT> ) ;


<s> DAG = static_cast < VLIWMachineScheduler * > ( dag ) ; SchedModel = DAG -> getSchedModel ( ) ; Top . init ( DAG , SchedModel ) ; Bot . init ( DAG , SchedModel ) ; const InstrItineraryData * Itin = DAG -> getSchedModel ( ) -> getInstrItineraries ( ) ; const TargetMachine & TM = DAG -> MF . getTarget ( ) ; delete Top . HazardRec ; delete Bot . HazardRec ; Top . HazardRec = TM . getSubtargetImpl ( ) -> getInstrInfo ( ) -> CreateTargetMIHazardRecognizer ( Itin , DAG ) ; Bot . HazardRec = TM . getSubtargetImpl ( ) -> getInstrInfo ( ) -> CreateTargetMIHazardRecognizer ( Itin , DAG ) ; delete Top . ResourceModel ;


<s> dbgs ( ) << <STR_LIT> << maxH << <STR_LIT> ; ) ; DEBUG ( unsigned maxD = <NUM_LIT> ; for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) if ( SUnits [ su ] . getDepth ( ) > maxD ) maxD = SUnits [ su ] . getDepth ( ) ; dbgs ( ) << <STR_LIT> << maxD << <STR_LIT> ; ) ; DEBUG ( for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) SUnits [ su ] . dumpAll ( this ) ) ; initQueues ( TopRoots , BotRoots ) ;


<s> DEBUG ( unsigned maxD = <NUM_LIT> ; for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) if ( SUnits [ su ] . getDepth ( ) > maxD ) maxD = SUnits [ su ] . getDepth ( ) ; dbgs ( ) << <STR_LIT> << maxD << <STR_LIT> ; ) ; DEBUG ( for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) SUnits [ su ] . dumpAll ( this ) ) ; initQueues ( TopRoots , BotRoots ) ; bool IsTopNode = false ; while ( SUnit * SU = SchedImpl -> pickNode ( IsTopNode ) ) { if ( ! checkSchedLimit ( ) ) break ; scheduleMI ( SU , IsTopNode ) ; updateQueues ( SU , IsTopNode ) ; SchedImpl -> schedNode ( SU , IsTopNode ) ;


<s> Packet . resize ( SchedModel -> getIssueWidth ( ) ) ; Packet . clear ( ) ; ResourcesModel -> clearResources ( ) ;


<s> VLIWResourceModel ( const TargetMachine & TM , const TargetSchedModel * SM ) : SchedModel ( SM ) , TotalPackets ( <NUM_LIT> ) { ResourcesModel = TM . getSubtargetImpl ( ) -> getInstrInfo ( ) -> CreateTargetScheduleState ( & TM , nullptr ) ;

assert ( ResourcesModel && <STR_LIT> ) ;


<s> VLIWMachineScheduler ( MachineSchedContext * C , MachineSchedStrategy * S ) : ScheduleDAGMILive ( C , S ) {


<s> return std :: find ( Packet . begin ( ) , Packet . end ( ) , SU ) != Packet . end ( ) ;


<s> bool isInPacket ( SUnit * SU ) const { return std :: find ( Packet . begin ( ) , Packet . end ( ) , SU ) != Packet . end ( ) ;


<s> return ( IsTop ) ? SU -> WeakPredsLeft : SU -> WeakSuccsLeft ;


<s> auto & QST = MBB -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const auto & QII = * QST . getInstrInfo ( ) ; if ( IsTop ) { for ( unsigned i = <NUM_LIT> , e = Packet . size ( ) ; i != e ; ++ i ) if ( hasDependence ( Packet [ i ] , SU , QII ) ) return false ; } else { for ( unsigned i = <NUM_LIT> , e = Packet . size ( ) ; i != e ; ++ i ) if ( hasDependence ( SU , Packet [ i ] , QII ) ) return false ; }


<s> SU = BotCand . SU ; } IsTopNode = false ; } else { SU = pickNodeBidrectional ( IsTopNode ) ; } if ( SU -> isTopReady ( ) ) Top . removeReady ( SU ) ; if ( SU -> isBottomReady ( ) ) Bot . removeReady ( SU ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ( IsTopNode ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << ( IsTopNode ? Top . CurrCycle : Bot . CurrCycle ) << <STR_LIT> << reportPackets ( ) << <STR_LIT> ; SU -> dump ( DAG ) ) ; return SU ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; IsTopNode = false ; return SU ; } if ( SUnit * SU = Top . pickOnlyChoice ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; IsTopNode = true ; return SU ; } SchedCandidate BotCand ; CandResult BotResult = pickNodeFromQueue ( Bot , DAG -> getBotRPTracker ( ) , BotCand ) ; assert ( BotResult != NoCand && <STR_LIT> ) ; if ( BotResult == SingleExcess || BotResult == SingleCritical ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; IsTopNode = false ; return BotCand . SU ; } SchedCandidate TopCand ; CandResult TopResult = pickNodeFromQueue ( Top , DAG -> getTopRPTracker ( ) , TopCand ) ; assert ( TopResult != NoCand && <STR_LIT> ) ; if ( TopResult == SingleExcess || TopResult == SingleCritical ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> if ( SUnit * SU = Top . pickOnlyChoice ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; IsTopNode = true ; return SU ; } SchedCandidate BotCand ; CandResult BotResult = pickNodeFromQueue ( Bot , DAG -> getBotRPTracker ( ) , BotCand ) ; assert ( BotResult != NoCand && <STR_LIT> ) ; if ( BotResult == SingleExcess || BotResult == SingleCritical ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; IsTopNode = false ; return BotCand . SU ; } SchedCandidate TopCand ; CandResult TopResult = pickNodeFromQueue ( Top , DAG -> getTopRPTracker ( ) , TopCand ) ; assert ( TopResult != NoCand && <STR_LIT> ) ; if ( TopResult == SingleExcess || TopResult == SingleCritical ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> ReadyQueue & Q = Zone . Available ; DEBUG ( if ( SchedDebugVerboseLevel > <NUM_LIT> ) readyQueueVerboseDump ( RPTracker , Candidate , Q ) ; else Q . dump ( ) ; ) ; RegPressureTracker & TempTracker = const_cast < RegPressureTracker & > ( RPTracker ) ; CandResult FoundCandidate = NoCand ; for ( ReadyQueue :: iterator I = Q . begin ( ) , E = Q . end ( ) ; I != E ; ++ I ) { RegPressureDelta RPDelta ; TempTracker . getMaxPressureDelta ( ( * I ) -> getInstr ( ) , RPDelta , DAG -> getRegionCriticalPSets ( ) , DAG -> getRegPressure ( ) . MaxSetPressure ) ; int CurrentCost = SchedulingCost ( Q , * I , Candidate , RPDelta , false ) ; if ( ! Candidate . SU ) { DEBUG ( traceCandidate ( <STR_LIT> , Q , * I , CurrentCost ) ) ; Candidate . SU = * I ; Candidate . RPDelta = RPDelta ; Candidate . SCost = CurrentCost ; FoundCandidate = NodeOrder ; continue ; } if ( CurrentCost < <NUM_LIT> && Candidate . SCost < <NUM_LIT> ) { if ( ( Q . getID ( ) == TopQID && ( * I ) -> NodeNum < Candidate . SU -> NodeNum ) || ( Q . getID ( ) == BotQID && ( * I ) -> NodeNum > Candidate . SU -> NodeNum ) ) { DEBUG ( traceCandidate ( <STR_LIT> , Q , * I , CurrentCost ) ) ; Candidate . SU = * I ; Candidate . RPDelta = RPDelta ; Candidate . SCost = CurrentCost ; FoundCandidate = NodeOrder ; } continue ; } if ( CurrentCost > Candidate . SCost ) { DEBUG ( traceCandidate ( <STR_LIT> , Q , * I , CurrentCost ) ) ; Candidate . SU = * I ; Candidate . RPDelta = RPDelta ; Candidate . SCost = CurrentCost ; FoundCandidate = BestCost ; continue ; } unsigned CurrWeak = getWeakLeft ( * I , ( Q . getID ( ) == TopQID ) ) ; unsigned CandWeak = getWeakLeft ( Candidate . SU , ( Q . getID ( ) == TopQID ) ) ; if ( CurrWeak != CandWeak ) { if ( CurrWeak < CandWeak ) { DEBUG ( traceCandidate ( <STR_LIT> , Q , * I , CurrentCost ) ) ; Candidate . SU = * I ; Candidate . RPDelta = RPDelta ;


<s> Packet . clear ( ) ; TotalPackets ++ ; return false ; } if ( ! isResourceAvailable ( SU , IsTop ) || Packet . size ( ) >= SchedModel -> getIssueWidth ( ) ) { ResourcesModel -> clearResources ( ) ; Packet . clear ( ) ; TotalPackets ++ ; startNewCycle = true ; } switch ( SU -> getInstr ( ) -> getOpcode ( ) ) { default : ResourcesModel -> reserveResources ( * SU -> getInstr ( ) ) ; break ;


<s> SchedImpl -> initialize ( this ) ; DEBUG ( unsigned maxH = <NUM_LIT> ; for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) if ( SUnits [ su ] . getHeight ( ) > maxH ) maxH = SUnits [ su ] . getHeight ( ) ; dbgs ( ) << <STR_LIT> << maxH << <STR_LIT> ; ) ; DEBUG ( unsigned maxD = <NUM_LIT> ; for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) if ( SUnits [ su ] . getDepth ( ) > maxD ) maxD = SUnits [ su ] . getDepth ( ) ; dbgs ( ) << <STR_LIT> << maxD << <STR_LIT> ; ) ; DEBUG ( for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) SUnits [ su ] . dumpAll ( this ) ) ; initQueues ( TopRoots , BotRoots ) ; bool IsTopNode = false ; while ( true ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; SUnit * SU = SchedImpl -> pickNode ( IsTopNode ) ;


<s> SchedImpl -> initialize ( this ) ; DEBUG ( unsigned maxH = <NUM_LIT> ; for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) if ( SUnits [ su ] . getHeight ( ) > maxH ) maxH = SUnits [ su ] . getHeight ( ) ; dbgs ( ) << <STR_LIT> << maxH << <STR_LIT> ; ) ; DEBUG ( unsigned maxD = <NUM_LIT> ; for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) if ( SUnits [ su ] . getDepth ( ) > maxD ) maxD = SUnits [ su ] . getDepth ( ) ; dbgs ( ) << <STR_LIT> << maxD << <STR_LIT> ; ) ; DEBUG ( for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) SUnits [ su ] . dumpAll ( this ) ) ; initQueues ( TopRoots , BotRoots ) ; bool IsTopNode = false ; while ( true ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; SUnit * SU = SchedImpl -> pickNode ( IsTopNode ) ; if ( ! SU ) break ;


<s> DEBUG ( unsigned maxH = <NUM_LIT> ; for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) if ( SUnits [ su ] . getHeight ( ) > maxH ) maxH = SUnits [ su ] . getHeight ( ) ; dbgs ( ) << <STR_LIT> << maxH << <STR_LIT> ; ) ; DEBUG ( unsigned maxD = <NUM_LIT> ; for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) if ( SUnits [ su ] . getDepth ( ) > maxD ) maxD = SUnits [ su ] . getDepth ( ) ; dbgs ( ) << <STR_LIT> << maxD << <STR_LIT> ; ) ;

DEBUG ( for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) SUnits [ su ] . dumpAll ( this ) ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * BB ) << <STR_LIT> << BB -> getName ( ) << <STR_LIT> << BB -> getParent ( ) -> getName ( ) << <STR_LIT> << MLI -> getLoopDepth ( BB ) << <STR_LIT> ) ; buildDAGWithRegPressure ( ) ; SmallVector < SUnit * , <NUM_LIT> > TopRoots , BotRoots ; findRootsAndBiasEdges ( TopRoots , BotRoots ) ; SchedImpl -> initialize ( this ) ; DEBUG ( unsigned maxH = <NUM_LIT> ; for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) if ( SUnits [ su ] . getHeight ( ) > maxH ) maxH = SUnits [ su ] . getHeight ( ) ; dbgs ( ) << <STR_LIT> << maxH << <STR_LIT> ; ) ; DEBUG ( unsigned maxD = <NUM_LIT> ; for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) if ( SUnits [ su ] . getDepth ( ) > maxD ) maxD = SUnits [ su ] . getDepth ( ) ; dbgs ( ) << <STR_LIT> << maxD << <STR_LIT> ; ) ;


<s> Top . HazardRec = TM . getInstrInfo ( ) -> CreateTargetMIHazardRecognizer ( Itin , DAG ) ; Bot . HazardRec = TM . getInstrInfo ( ) -> CreateTargetMIHazardRecognizer ( Itin , DAG ) ; Top . ResourceModel = new VLIWResourceModel ( TM , DAG -> getSchedModel ( ) ) ; Bot . ResourceModel = new VLIWResourceModel ( TM , DAG -> getSchedModel ( ) ) ; assert ( ( ! llvm :: ForceTopDown || ! llvm :: ForceBottomUp ) && <STR_LIT> ) ;


<s> Bot . init ( DAG , SchedModel ) ; const InstrItineraryData * Itin = DAG -> getSchedModel ( ) -> getInstrItineraries ( ) ; const TargetMachine & TM = DAG -> MF . getTarget ( ) ; delete Top . HazardRec ; delete Bot . HazardRec ; Top . HazardRec = TM . getInstrInfo ( ) -> CreateTargetMIHazardRecognizer ( Itin , DAG ) ; Bot . HazardRec = TM . getInstrInfo ( ) -> CreateTargetMIHazardRecognizer ( Itin , DAG ) ; Top . ResourceModel = new VLIWResourceModel ( TM , DAG -> getSchedModel ( ) ) ; Bot . ResourceModel = new VLIWResourceModel ( TM , DAG -> getSchedModel ( ) ) ; assert ( ( ! llvm :: ForceTopDown || ! llvm :: ForceBottomUp ) && <STR_LIT> ) ;


<s> dbgs ( ) << Label << <STR_LIT> << Q . getName ( ) << <STR_LIT> ;

if ( P . isValid ( ) ) dbgs ( ) << DAG -> TRI -> getRegPressureSetName ( P . PSetID ) << <STR_LIT> << P . UnitIncrease << <STR_LIT> ;


<s> assert ( ResourcesModel && <STR_LIT> ) ; Packet . resize ( SchedModel -> getIssueWidth ( ) ) ; Packet . clear ( ) ; OldPacket . resize ( SchedModel -> getIssueWidth ( ) ) ; OldPacket . clear ( ) ;


<s> Packet . resize ( SchedModel -> getIssueWidth ( ) ) ; Packet . clear ( ) ; OldPacket . resize ( SchedModel -> getIssueWidth ( ) ) ; OldPacket . clear ( ) ; ResourcesModel -> clearResources ( ) ;


<s> if ( ForceTopDown ) { SU = Top . pickOnlyChoice ( ) ; if ( ! SU ) { SchedCandidate TopCand ; CandResult TopResult = pickNodeFromQueue ( Top , DAG -> getTopRPTracker ( ) , TopCand ) ; assert ( TopResult != NoCand && <STR_LIT> ) ; ( void ) TopResult ; SU = TopCand . SU ; } IsTopNode = true ; } else if ( ForceBottomUp ) { SU = Bot . pickOnlyChoice ( ) ; if ( ! SU ) { SchedCandidate BotCand ; CandResult BotResult = pickNodeFromQueue ( Bot , DAG -> getBotRPTracker ( ) , BotCand ) ; assert ( BotResult != NoCand && <STR_LIT> ) ; ( void ) BotResult ; SU = BotCand . SU ; } IsTopNode = false ; } else { SU = pickNodeBidrectional ( IsTopNode ) ; } if ( SU -> isTopReady ( ) ) Top . removeReady ( SU ) ; if ( SU -> isBottomReady ( ) ) Bot . removeReady ( SU ) ;

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( IsTopNode ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << ( IsTopNode ? Top . CurrCycle : Bot . CurrCycle ) << <STR_LIT> << reportPackets ( ) << <STR_LIT> ;


<s> assert ( TopResult != NoCand && <STR_LIT> ) ; ( void ) TopResult ; SU = TopCand . SU ; } IsTopNode = true ; } else if ( ForceBottomUp ) { SU = Bot . pickOnlyChoice ( ) ; if ( ! SU ) { SchedCandidate BotCand ; CandResult BotResult = pickNodeFromQueue ( Bot , DAG -> getBotRPTracker ( ) , BotCand ) ; assert ( BotResult != NoCand && <STR_LIT> ) ; ( void ) BotResult ; SU = BotCand . SU ; } IsTopNode = false ; } else { SU = pickNodeBidrectional ( IsTopNode ) ; }

if ( SU -> isTopReady ( ) ) Top . removeReady ( SU ) ;


<s> ConvergingVLIWScheduler ( ) : DAG ( nullptr ) , SchedModel ( nullptr ) , Top ( TopQID , <STR_LIT> ) , Bot ( BotQID , <STR_LIT> ) {


<s> unsigned getTotalPackets ( ) const {


<s> void init ( VLIWMachineScheduler * dag , const TargetSchedModel * smodel ) { DAG = dag ; SchedModel = smodel ;


<s> void init ( VLIWMachineScheduler * dag , const TargetSchedModel * smodel ) {


<s> bool isTop ( ) const { return Available . getID ( ) == ConvergingVLIWScheduler :: TopQID ;


<s> unsigned ReportPackets ( ) { return Top . ResourceModel -> getTotalPackets ( ) + Bot . ResourceModel -> getTotalPackets ( ) ;


return Top . ResourceModel -> getTotalPackets ( ) + Bot . ResourceModel -> getTotalPackets ( ) ;


<s> Packet . clear ( ) ; ResourcesModel -> clearResources ( ) ;


<s> ResourcesModel -> clearResources ( ) ;


<s> SchedCandidate ( ) : SU ( nullptr ) , SCost ( <NUM_LIT> ) {


<s> void VLIWMachineScheduler :: schedule ( ) { DEBUG ( dbgs ( ) << <STR_LIT> << BB -> getNumber ( ) << <STR_LIT> << BB -> getName ( ) << <STR_LIT> << BB -> getParent ( ) -> getFunction ( ) -> getName ( ) << <STR_LIT> << MLI . getLoopDepth ( BB ) << <STR_LIT> ) ; buildDAGWithRegPressure ( ) ; postprocessDAG ( ) ; SmallVector < SUnit * , <NUM_LIT> > TopRoots , BotRoots ; findRootsAndBiasEdges ( TopRoots , BotRoots ) ; SchedImpl -> initialize ( this ) ; DEBUG ( unsigned maxH = <NUM_LIT> ; for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) if ( SUnits [ su ] . getHeight ( ) > maxH ) maxH = SUnits [ su ] . getHeight ( ) ; dbgs ( ) << <STR_LIT> << maxH << <STR_LIT> ; ) ; DEBUG ( unsigned maxD = <NUM_LIT> ; for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) if ( SUnits [ su ] . getDepth ( ) > maxD ) maxD = SUnits [ su ] . getDepth ( ) ; dbgs ( ) << <STR_LIT> << maxD << <STR_LIT> ; ) ; DEBUG ( for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) SUnits [ su ] . dumpAll ( this ) ) ; initQueues ( TopRoots , BotRoots ) ; bool IsTopNode = false ; while ( SUnit * SU = SchedImpl -> pickNode ( IsTopNode ) ) { if ( ! checkSchedLimit ( ) ) break ; scheduleMI ( SU , IsTopNode ) ;


<s> DEBUG ( unsigned maxH = <NUM_LIT> ; for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) if ( SUnits [ su ] . getHeight ( ) > maxH ) maxH = SUnits [ su ] . getHeight ( ) ; dbgs ( ) << <STR_LIT> << maxH << <STR_LIT> ; ) ; DEBUG ( unsigned maxD = <NUM_LIT> ; for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) if ( SUnits [ su ] . getDepth ( ) > maxD ) maxD = SUnits [ su ] . getDepth ( ) ; dbgs ( ) << <STR_LIT> << maxD << <STR_LIT> ; ) ; DEBUG ( for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) SUnits [ su ] . dumpAll ( this ) ) ; initQueues ( TopRoots , BotRoots ) ; bool IsTopNode = false ; while ( SUnit * SU = SchedImpl -> pickNode ( IsTopNode ) ) { if ( ! checkSchedLimit ( ) ) break ; scheduleMI ( SU , IsTopNode ) ; updateQueues ( SU , IsTopNode ) ; SchedImpl -> schedNode ( SU , IsTopNode ) ; }

assert ( CurrentTop == CurrentBottom && <STR_LIT> ) ;


<s> VLIWMachineScheduler ( MachineSchedContext * C , std :: unique_ptr < MachineSchedStrategy > S ) : ScheduleDAGMILive ( C , std :: move ( S ) ) {


<s> Packet . resize ( SchedModel -> getIssueWidth ( ) ) ; Packet . clear ( ) ; ResourcesModel -> clearResources ( ) ;


<s> VLIWResourceModel ( const TargetSubtargetInfo & STI , const TargetSchedModel * SM ) : SchedModel ( SM ) , TotalPackets ( <NUM_LIT> ) { ResourcesModel = STI . getInstrInfo ( ) -> CreateTargetScheduleState ( STI ) ; assert ( ResourcesModel && <STR_LIT> ) ; Packet . resize ( SchedModel -> getIssueWidth ( ) ) ; Packet . clear ( ) ; ResourcesModel -> clearResources ( ) ;


<s> DAG ( nullptr ) , SchedModel ( nullptr ) , Available ( ID , Name + <STR_LIT> ) , Pending ( ID << ConvergingVLIWScheduler :: LogMaxQID , Name + <STR_LIT> ) , CheckPending ( false ) , HazardRec ( nullptr ) , ResourceModel ( nullptr ) , CurrCycle ( <NUM_LIT> ) , IssueCount ( <NUM_LIT> ) , MinReadyCycle ( UINT_MAX ) , MaxMinLatency ( <NUM_LIT> ) {


<s> ~ VLIWResourceModel ( ) { delete ResourcesModel ;


<s> ~ VLIWSchedBoundary ( ) { delete ResourceModel ;


<s> ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; HasLEB128 = true ; PrivateGlobalPrefix = <STR_LIT> ; LCOMMDirectiveType = LCOMM :: ByteAlignment ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ;


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TT ) { Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = nullptr ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; LCOMMDirectiveAlignmentType = LCOMM :: ByteAlignment ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ;


<s> InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; SupportsDebugInformation = true ; UsesELFSectionDirectiveForBSS = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ;


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( StringRef TT ) { Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = nullptr ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; LCOMMDirectiveAlignmentType = LCOMM :: ByteAlignment ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; SupportsDebugInformation = true ; UsesELFSectionDirectiveForBSS = true ;

ExceptionsType = ExceptionHandling :: DwarfCFI ;


<s> InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ;


<s> HasLEB128 = true ; PrivateGlobalPrefix = <STR_LIT> ; LCOMMDirectiveAlignmentType = LCOMM :: ByteAlignment ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; SupportsDebugInformation = true ;


<s> Data64bitsDirective = nullptr ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; LCOMMDirectiveAlignmentType = LCOMM :: ByteAlignment ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; SupportsDebugInformation = true ; MinInstAlignment = <NUM_LIT> ; UsesELFSectionDirectiveForBSS = true ;


<s> CommentString = <STR_LIT> ; LCOMMDirectiveAlignmentType = LCOMM :: ByteAlignment ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; SupportsDebugInformation = true ; MinInstAlignment = <NUM_LIT> ; UsesELFSectionDirectiveForBSS = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ;


<s> Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = nullptr ; CommentString = <STR_LIT> ; SupportsDebugInformation = true ; LCOMMDirectiveAlignmentType = LCOMM :: ByteAlignment ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; MinInstAlignment = <NUM_LIT> ;


<s> HasLEB128 = true ; PrivateGlobalPrefix = <STR_LIT> ; LCOMMDirectiveAlignmentType = LCOMM :: ByteAlignment ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; ZeroDirective = <STR_LIT> ;


<s> Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <NUM_LIT> ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; HasLEB128 = true ;


<s> InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; SupportsDebugInformation = true ;


<s> CommentString = <STR_LIT> ; LCOMMDirectiveAlignmentType = LCOMM :: ByteAlignment ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; SupportsDebugInformation = true ; MinInstAlignment = <NUM_LIT> ; UsesELFSectionDirectiveForBSS = true ;


<s> Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = nullptr ; CommentString = <STR_LIT> ; LCOMMDirectiveAlignmentType = LCOMM :: ByteAlignment ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; SupportsDebugInformation = true ; MinInstAlignment = <NUM_LIT> ;


<s> LCOMMDirectiveAlignmentType = LCOMM :: ByteAlignment ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; MinInstAlignment = <NUM_LIT> ;


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; HasLEB128 = true ; LCOMMDirectiveAlignmentType = LCOMM :: ByteAlignment ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ;


<s> LCOMMDirectiveAlignmentType = LCOMM :: ByteAlignment ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; SupportsDebugInformation = true ; UsesELFSectionDirectiveForBSS = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ;


<s> bool chkAXOK = checkAXOK ( ) ; bool chkCofMax1 = checkCOFMax1 ( ) ; bool chkHWLoop = checkHWLoop ( ) ; bool chkLegalVecRegPair = checkLegalVecRegPair ( ) ; bool chk = chkP && chkNV && chkR && chkRRO && chkS && chkSh && chkSl && chkAXOK && chkCofMax1 && chkHWLoop && chkLegalVecRegPair ;


<s> bool chkSl = true ; if ( FullCheck ) chkSl = checkSlots ( ) ; bool chkAXOK = checkAXOK ( ) ; bool chkCofMax1 = checkCOFMax1 ( ) ; bool chkHWLoop = checkHWLoop ( ) ; bool chkLegalVecRegPair = checkLegalVecRegPair ( ) ;

bool chk = chkP && chkNV && chkR && chkRRO && chkS && chkSh && chkSl && chkAXOK && chkCofMax1 && chkHWLoop && chkLegalVecRegPair ;


<s> const bool IsPermitted = STI . getFeatureBits ( ) [ <STR_LIT> ] ; const bool HasReversePairs = ReversePairs . size ( ) != <NUM_LIT> ; if ( ! IsPermitted && HasReversePairs ) { for ( auto R : ReversePairs ) reportError ( <STR_LIT> + Twine ( RI . getName ( R ) ) + <STR_LIT> ) ; return false ;


<s> const bool HasReversePairs = ReversePairs . size ( ) != <NUM_LIT> ; if ( ! IsPermitted && HasReversePairs ) {

for ( auto R : ReversePairs ) reportError ( <STR_LIT> + Twine ( RI . getName ( R ) ) + <STR_LIT> ) ;


<s> for ( const auto & I : NewPreds ) { unsigned P = I ; if ( ! Defs . count ( P ) || LatePreds . count ( P ) || Defs . count ( <STR_LIT> ) ) { reportErrorNewValue ( P ) ; return false ;


<s> if ( ! Defs . count ( P ) || LatePreds . count ( P ) || Defs . count ( <STR_LIT> ) ) { reportErrorNewValue ( P ) ; return false ; } } for ( const auto & I : LatePreds ) { unsigned P = I ; if ( LatePreds . count ( P ) > <NUM_LIT> || Defs . count ( P ) ) { reportErrorRegisters ( P ) ;


<s> <ISA_LIT>MCChecker :: <ISA_LIT>MCChecker ( <ISA_LIT>MCChecker const & Other , MCSubtargetInfo const & STI , bool CopyReportErrors ) : Context ( Other . Context ) , MCB ( Other . MCB ) , RI ( Other . RI ) , MCII ( Other . MCII ) , STI ( STI ) , ReportErrors ( CopyReportErrors ? Other . ReportErrors : false ) , ReversePairs ( ) { init ( ) ;


<s> if ( <STR_LIT> == R ) continue ; if ( <STR_LIT> == R ) SoftDefs . insert ( R ) ; else if ( isPredicateRegister ( R ) && <ISA_LIT>MCInstrInfo :: isPredicateLate ( MCII , MCI ) ) LatePreds . insert ( R ) ; else Defs [ R ] . insert ( PredSense ( PredReg , isTrue ) ) ; } for ( unsigned i = <NUM_LIT> ; i < MCID . getNumDefs ( ) ; ++ i ) { unsigned R = MCI . getOperand ( i ) . getReg ( ) , S = <STR_LIT> ; if ( R == <STR_LIT> ) R = <STR_LIT> ; if ( <ISA_LIT>MCInstrInfo :: IsReverseVecRegPair ( R ) ) ReversePairs . insert ( R ) ; for ( MCRegAliasIterator SRI ( R , & RI , ! MCSubRegIterator ( R , & RI ) . isValid ( ) ) ; SRI . isValid ( ) ; ++ SRI ) { if ( MCSubRegIterator ( * SRI , & RI ) . isValid ( ) ) continue ; if ( R == * SRI ) { if ( S == R ) continue ; else S = R ;


<s> isTrue = <ISA_LIT>MCInstrInfo :: isPredicatedTrue ( MCII , MCI ) ; if ( <ISA_LIT>MCInstrInfo :: isPredicatedNew ( MCII , MCI ) ) NewPreds . insert ( PredReg ) ;

} else for ( MCRegAliasIterator SRI ( R , & RI , ! MCSubRegIterator ( R , & RI ) . isValid ( ) ) ;


<s> bool chkP = checkPredicates ( ) ; bool chkNV = checkNewValues ( ) ; bool chkR = checkRegisters ( ) ; bool chkS = checkSolo ( ) ; bool chkSh = checkShuffle ( ) ;


<s> bool chkSl = checkSlots ( ) ; bool chk = chkB && chkP && chkNV && chkR && chkS && chkSh && chkSl ; return chk ;


<s> bool <ISA_LIT>MCChecker :: checkBranches ( ) { <ISA_LIT>MCErrInfo errInfo ; if ( <ISA_LIT>MCInstrInfo :: isBundle ( MCB ) ) { bool hasConditional = false ; unsigned Branches = <NUM_LIT> , Returns = <NUM_LIT> , NewIndirectBranches = <NUM_LIT> , NewValueBranches = <NUM_LIT> , Conditional = HEXAGON_PRESHUFFLE_PACKET_SIZE , Unconditional = HEXAGON_PRESHUFFLE_PACKET_SIZE ; for ( unsigned i = <ISA_LIT>MCInstrInfo :: bundleInstructionsOffset ; i < MCB . size ( ) ; ++ i ) { MCInst const & MCI = * MCB . begin ( ) [ i ] . getInst ( ) ; if ( <ISA_LIT>MCInstrInfo :: isImmext ( MCI ) ) continue ; if ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . isBranch ( ) || <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . isCall ( ) ) { ++ Branches ; if ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . isIndirectBranch ( ) && <ISA_LIT>MCInstrInfo :: isPredicatedNew ( MCII , MCI ) ) ++ NewIndirectBranches ; if ( <ISA_LIT>MCInstrInfo :: isNewValue ( MCII , MCI ) ) ++ NewValueBranches ; if ( <ISA_LIT>MCInstrInfo :: isPredicated ( MCII , MCI ) || <ISA_LIT>MCInstrInfo :: isPredicatedNew ( MCII , MCI ) ) { hasConditional = true ; Conditional = i ; } else { Unconditional = i ; } }

if ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . isReturn ( ) && <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . mayLoad ( ) ) ++ Returns ;


<s> if ( <ISA_LIT>MCInstrInfo :: isBundle ( MCB ) ) { bool hasConditional = false ; unsigned Branches = <NUM_LIT> , Returns = <NUM_LIT> , NewIndirectBranches = <NUM_LIT> , NewValueBranches = <NUM_LIT> , Conditional = HEXAGON_PRESHUFFLE_PACKET_SIZE , Unconditional = HEXAGON_PRESHUFFLE_PACKET_SIZE ; for ( unsigned i = <ISA_LIT>MCInstrInfo :: bundleInstructionsOffset ; i < MCB . size ( ) ; ++ i ) { MCInst const & MCI = * MCB . begin ( ) [ i ] . getInst ( ) ; if ( <ISA_LIT>MCInstrInfo :: isImmext ( MCI ) ) continue ; if ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . isBranch ( ) || <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . isCall ( ) ) { ++ Branches ; if ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . isIndirectBranch ( ) && <ISA_LIT>MCInstrInfo :: isPredicatedNew ( MCII , MCI ) ) ++ NewIndirectBranches ; if ( <ISA_LIT>MCInstrInfo :: isNewValue ( MCII , MCI ) ) ++ NewValueBranches ; if ( <ISA_LIT>MCInstrInfo :: isPredicated ( MCII , MCI ) || <ISA_LIT>MCInstrInfo :: isPredicatedNew ( MCII , MCI ) ) { hasConditional = true ;


<s> unsigned R = I . first ; NewSense & US = I . second ; if ( ! hasValidNewValueDef ( US , NewDefs [ R ] ) ) { errInfo . setError ( <STR_LIT> , R ) ; addErrInfo ( errInfo ) ; return false ; } } return true ;


<s> unsigned P = I ; if ( ! Defs . count ( P ) || LatePreds . count ( P ) ) { errInfo . setError ( <STR_LIT> , P ) ;


<s> for ( const auto & I : LatePreds ) { unsigned P = I ; if ( LatePreds . count ( P ) > <NUM_LIT> || Defs . count ( P ) ) {


<s> unsigned UsrR = <STR_LIT> ; unsigned BadR = RI . isSubRegister ( <STR_LIT> , R ) ? UsrR : R ; errInfo . setError ( <STR_LIT> , BadR ) ; addErrInfo ( errInfo ) ; return false ; } if ( ! isPredicateRegister ( R ) && Defs [ R ] . size ( ) > <NUM_LIT> ) { PredSet & PM = Defs [ R ] ; if ( PM . count ( Unconditional ) ) { unsigned UsrR = <STR_LIT> ; unsigned BadR = RI . isSubRegister ( <STR_LIT> , R ) ? UsrR : R ; errInfo . setError ( <STR_LIT> , BadR ) ; addErrInfo ( errInfo ) ; return false ; } for ( const auto & J : PM ) { PredSense P = J ; if ( PM . count ( P ) > <NUM_LIT> ) { errInfo . setError ( <STR_LIT> , R ) ; addErrInfo ( errInfo ) ; return false ; } P . second = ! P . second ; if ( PM . count ( P ) && PM . size ( ) > <NUM_LIT> ) { errInfo . setError ( <STR_LIT> , R ) ; addErrInfo ( errInfo ) ; return false ; } } } } for ( const auto & I : CurDefs ) { unsigned R = I ; if ( ! Uses . count ( R ) ) {

errInfo . setWarning ( <STR_LIT> , R ) ;


<s> bool <ISA_LIT>MCChecker :: checkShuffle ( ) { <ISA_LIT>MCErrInfo errInfo ; <ISA_LIT>MCShuffler MCS ( MCII , STI , MCB ) ; if ( ! MCS . check ( ) ) { if ( MCS . getError ( ) == <ISA_LIT>Shuffler :: SHUFFLE_ERROR_BRANCHES ) { errInfo . setError ( <STR_LIT> ) ; errInfo . setShuffleError ( MCS . getError ( ) ) ; addErrInfo ( errInfo ) ; return false ; } } <ISA_LIT>MCShuffler MCSDX ( MCII , STI , MCBDX ) ; if ( ! MCSDX . check ( ) ) { errInfo . setError ( <STR_LIT> ) ; errInfo . setShuffleError ( MCSDX . getError ( ) ) ; addErrInfo ( errInfo ) ; return false ;


<s> if ( ! MCSDX . check ( ) ) { errInfo . setError ( <STR_LIT> ) ; errInfo . setShuffleError ( MCSDX . getError ( ) ) ; addErrInfo ( errInfo ) ; return false ; }


<s> else ++ slotsUsed ; } if ( slotsUsed > HEXAGON_PACKET_SIZE ) { <ISA_LIT>MCErrInfo errInfo ; errInfo . setError ( <STR_LIT> ) ; addErrInfo ( errInfo ) ; return false ; } return true ;


<s> else ++ slotsUsed ; } if ( slotsUsed > HEXAGON_PACKET_SIZE ) { <ISA_LIT>MCErrInfo errInfo ; errInfo . setError ( <STR_LIT> ) ; addErrInfo ( errInfo ) ; return false ; }


<s> <ISA_LIT>MCErrInfo errInfo ; if ( <ISA_LIT>MCInstrInfo :: isBundle ( MCB ) && <ISA_LIT>MCInstrInfo :: bundleSize ( MCB ) > <NUM_LIT> ) { for ( auto const & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( MCB ) ) {

if ( llvm :: <ISA_LIT>MCInstrInfo :: isSolo ( MCII , * I . getInst ( ) ) ) {


<s> if ( Use . IsNVJ && ( Def . IsFloat || Def . PredReg != <NUM_LIT> ) ) continue ; if ( Def . PredReg == <NUM_LIT> ) return true ; if ( Strict ) { if ( Def . PredReg == Use . PredReg && Def . Cond == Use . Cond ) return true ;


<s> <ISA_LIT>MCChecker :: <ISA_LIT>MCChecker ( MCInstrInfo const & MCII , MCSubtargetInfo const & STI , MCInst & mcb , MCInst & mcbdx , MCRegisterInfo const & ri ) : MCB ( mcb ) , MCBDX ( mcbdx ) , RI ( ri ) , MCII ( MCII ) , STI ( STI ) , bLoadErrInfo ( false ) { init ( ) ;


<s> <ISA_LIT>MCChecker :: <ISA_LIT>MCChecker ( MCInstrInfo const & MCII , MCSubtargetInfo const & STI , MCInst & mcb , MCInst & mcbdx , MCRegisterInfo const & ri ) : MCB ( mcb ) , MCBDX ( mcbdx ) , RI ( ri ) , MCII ( MCII ) , STI ( STI ) , bLoadErrInfo ( false ) {


<s> PredReg = R ; isTrue = <ISA_LIT>MCInstrInfo :: isPredicatedTrue ( MCII , MCI ) ; if ( <ISA_LIT>MCInstrInfo :: isPredicatedNew ( MCII , MCI ) ) NewPreds . insert ( PredReg ) ; } else for ( MCRegAliasIterator SRI ( R , & RI , ! MCSubRegIterator ( R , & RI ) . isValid ( ) ) ; SRI . isValid ( ) ; ++ SRI ) if ( ! MCSubRegIterator ( * SRI , & RI ) . isValid ( ) ) Uses . insert ( * SRI ) ; } if ( const MCPhysReg * ImpDef = MCID . getImplicitDefs ( ) ) for ( ; * ImpDef ; ++ ImpDef ) { unsigned R = * ImpDef ; if ( <STR_LIT> != R && MCID . isCall ( ) ) continue ; if ( <STR_LIT> == R ) continue ; if ( <STR_LIT> == R ) SoftDefs . insert ( R ) ; else if ( isPredicateRegister ( R ) && <ISA_LIT>MCInstrInfo :: isPredicateLate ( MCII , MCI ) ) LatePreds . insert ( R ) ; else Defs [ R ] . insert ( PredSense ( PredReg , isTrue ) ) ; } for ( unsigned i = <NUM_LIT> ; i < MCID . getNumDefs ( ) ; ++ i ) { unsigned R = MCI . getOperand ( i ) . getReg ( ) , S = <STR_LIT> ; if ( R == <STR_LIT> ) R = <STR_LIT> ; for ( MCRegAliasIterator SRI ( R , & RI , ! MCSubRegIterator ( R , & RI ) . isValid ( ) ) ; SRI . isValid ( ) ; ++ SRI ) { if ( MCSubRegIterator ( * SRI , & RI ) . isValid ( ) ) continue ; if ( R == * SRI ) { if ( S == R ) continue ; else S = R ; } if ( <STR_LIT> != R && <STR_LIT> == * SRI ) SoftDefs . insert ( * SRI ) ; else if ( <ISA_LIT>MCInstrInfo :: isPredicateLate ( MCII , MCI ) && isPredicateRegister ( * SRI ) ) LatePreds . insert ( * SRI ) ; else if ( i == <NUM_LIT> && llvm :: <ISA_LIT>MCInstrInfo :: getType ( MCII , MCI ) == <STR_LIT> ) CurDefs . insert ( * SRI ) , Defs [ * SRI ] . insert ( PredSense ( PredReg , isTrue ) ) ; else if ( i == <NUM_LIT> && llvm :: <ISA_LIT>MCInstrInfo :: getType ( MCII , MCI ) == <STR_LIT> ) TmpDefs . insert ( * SRI ) ; else if ( i <= <NUM_LIT> && llvm :: <ISA_LIT>MCInstrInfo :: hasNewValue2 ( MCII , MCI ) ) Uses . insert ( * SRI ) ; else Defs [ * SRI ] . insert ( PredSense ( PredReg , isTrue ) ) ; } }

if ( <ISA_LIT>MCInstrInfo :: hasNewValue ( MCII , MCI ) ) {


<s> void <ISA_LIT>MCChecker :: reportWarning ( Twine const & Msg ) { if ( ReportErrors ) { auto SM = Context . getSourceManager ( ) ;

if ( SM ) SM -> PrintMessage ( MCB . getLoc ( ) , SourceMgr :: DK_Warning , Msg ) ;


<s> bool <ISA_LIT>MCChecker :: check ( bool FullCheck ) { bool chkB = checkBranches ( ) ; bool chkP = checkPredicates ( ) ; bool chkNV = checkNewValues ( ) ; bool chkR = checkRegisters ( ) ; bool chkS = checkSolo ( ) ; bool chkSh = true ; if ( FullCheck ) chkSh = checkShuffle ( ) ; bool chkSl = true ;

if ( FullCheck ) chkSl = checkSlots ( ) ;


<s> bool <ISA_LIT>MCChecker :: checkBranches ( ) { <ISA_LIT>MCErrInfo errInfo ; if ( <ISA_LIT>MCInstrInfo :: isBundle ( MCB ) ) { bool hasConditional = false ; unsigned Branches = <NUM_LIT> , Conditional = HEXAGON_PRESHUFFLE_PACKET_SIZE , Unconditional = HEXAGON_PRESHUFFLE_PACKET_SIZE ; for ( unsigned i = <ISA_LIT>MCInstrInfo :: bundleInstructionsOffset ; i < MCB . size ( ) ; ++ i ) { MCInst const & MCI = * MCB . begin ( ) [ i ] . getInst ( ) ; if ( <ISA_LIT>MCInstrInfo :: isImmext ( MCI ) ) continue ; if ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . isBranch ( ) || <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . isCall ( ) ) { ++ Branches ; if ( <ISA_LIT>MCInstrInfo :: isPredicated ( MCII , MCI ) || <ISA_LIT>MCInstrInfo :: isPredicatedNew ( MCII , MCI ) ) { hasConditional = true ; Conditional = i ;


<s> } } <ISA_LIT>MCShuffler MCSDX ( true , MCII , STI , MCBDX ) ; if ( ! MCSDX . check ( ) ) { errInfo . setError ( <STR_LIT> ) ;

errInfo . setShuffleError ( MCSDX . getError ( ) ) ;


<s> if ( <ISA_LIT>MCInstrInfo :: isPredicatedNew ( MCII , MCI ) ) NewPreds . insert ( PredReg ) ; }

else for ( MCRegAliasIterator SRI ( R , & RI , ! MCSubRegIterator ( R , & RI ) . isValid ( ) ) ;


<s> if ( <ISA_LIT>MCInstrInfo :: isPredicatedNew ( MCII , MCI ) ) NewPreds . insert ( PredReg ) ; } else for ( MCRegAliasIterator SRI ( R , & RI , ! MCSubRegIterator ( R , & RI ) . isValid ( ) ) ;


<s> bool <ISA_LIT>MCChecker :: check ( bool FullCheck ) { bool chkB = checkBranches ( ) ; bool chkP = checkPredicates ( ) ; bool chkNV = checkNewValues ( ) ; bool chkR = checkRegisters ( ) ; bool chkRRO = checkRegistersReadOnly ( ) ; bool chkELB = checkEndloopBranches ( ) ; checkRegisterCurDefs ( ) ; bool chkS = checkSolo ( ) ; bool chkSh = true ;

if ( FullCheck ) chkSh = checkShuffle ( ) ;


<s> if ( ! HasSoloAXInst ) return true ; for ( auto const & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( MCII , MCB ) ) {

if ( & I != HasSoloAXInst && isNeitherAnorX ( MCII , I ) ) {


<s> reportError ( I . getLoc ( ) , llvm :: Twine ( <STR_LIT> ) + ( Inner ? <STR_LIT> : <STR_LIT> ) + <STR_LIT> + <STR_LIT> + <STR_LIT> + llvm :: Twine ( RI . getName ( <STR_LIT> ) ) + <STR_LIT> ) ; return false ; } } }


<s> unsigned R = I . first ; NewSense & US = I . second ; if ( ! hasValidNewValueDef ( US , NewDefs [ R ] ) ) { reportErrorNewValue ( R ) ; return false ; }


<s> void <ISA_LIT>MCChecker :: checkRegisterCurDefs ( ) { for ( auto const & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( MCII , MCB ) ) {

if ( <ISA_LIT>MCInstrInfo :: isCVINew ( MCII , I ) && <ISA_LIT>MCInstrInfo :: getDesc ( MCII , I ) . mayLoad ( ) ) {


<s> for ( auto const & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( MCII , MCB ) ) { if ( <ISA_LIT>MCInstrInfo :: isCVINew ( MCII , I ) && <ISA_LIT>MCInstrInfo :: getDesc ( MCII , I ) . mayLoad ( ) ) { unsigned Register = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! registerUsed ( Register ) ) reportWarning ( <STR_LIT> + llvm :: Twine ( RI . getName ( Register ) ) + <STR_LIT> <STR_LIT> ) ;


<s> reportError ( <STR_LIT> <STR_LIT> ) ; return false ; } if ( SoftDefs . count ( R ) ) { unsigned UsrR = <STR_LIT> ; unsigned BadR = RI . isSubRegister ( <STR_LIT> , R ) ? UsrR : R ; reportErrorRegisters ( BadR ) ; return false ; } if ( ! isPredicateRegister ( R ) && Defs [ R ] . size ( ) > <NUM_LIT> ) { PredSet & PM = Defs [ R ] ; if ( PM . count ( Unconditional ) ) { unsigned UsrR = <STR_LIT> ; unsigned BadR = RI . isSubRegister ( <STR_LIT> , R ) ? UsrR : R ; reportErrorRegisters ( BadR ) ; return false ; } for ( const auto & J : PM ) { PredSense P = J ; if ( PM . count ( P ) > <NUM_LIT> ) { reportErrorRegisters ( R ) ; return false ; } P . second = ! P . second ; if ( PM . count ( P ) && PM . size ( ) > <NUM_LIT> ) { reportErrorRegisters ( R ) ; return false ; } } } } for ( const auto & I : TmpDefs ) { unsigned R = I ; if ( ! Uses . count ( R ) ) { bool vHistFound = false ; for ( auto const & HMI : <ISA_LIT>MCInstrInfo :: bundleInstructions ( MCB ) ) { if ( llvm :: <ISA_LIT>MCInstrInfo :: getType ( MCII , * HMI . getInst ( ) ) == <STR_LIT> ) { vHistFound = true ; break ; } } if ( vHistFound == false ) { reportWarning ( <STR_LIT> + llvm :: Twine ( RI . getName ( R ) ) + <STR_LIT> <STR_LIT> ) ; return true ; } } }


<s> if ( PM . count ( Unconditional ) ) { unsigned UsrR = <STR_LIT> ; unsigned BadR = RI . isSubRegister ( <STR_LIT> , R ) ? UsrR : R ; reportErrorRegisters ( BadR ) ; return false ; } for ( const auto & J : PM ) { PredSense P = J ; if ( PM . count ( P ) > <NUM_LIT> ) { reportErrorRegisters ( R ) ; return false ; } P . second = ! P . second ; if ( PM . count ( P ) && PM . size ( ) > <NUM_LIT> ) { reportErrorRegisters ( R ) ; return false ; } } } } for ( const auto & I : TmpDefs ) { unsigned R = I ; if ( ! Uses . count ( R ) ) {


<s> assert ( Operand . isReg ( ) && <STR_LIT> ) ; unsigned Register = Operand . getReg ( ) ; if ( ReadOnly . find ( Register ) != ReadOnly . end ( ) ) { reportError ( Inst . getLoc ( ) , <STR_LIT> + llvm :: Twine ( RI . getName ( Register ) ) + <STR_LIT> ) ; return false ; } } } return true ;


<s> reportError ( I . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; return false ; } } return true ;


<s> if ( llvm :: <ISA_LIT>MCInstrInfo :: isSolo ( MCII , I ) ) { reportError ( I . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; break ; default : return false ;


<s> unsigned Result = <NUM_LIT> ; unsigned Type = <ISA_LIT>MCInstrInfo :: getType ( MCII , ID ) ; if ( Type == <STR_LIT> ) { unsigned subInst0Opcode = ID . getOperand ( <NUM_LIT> ) . getInst ( ) -> getOpcode ( ) ; unsigned subInst1Opcode = ID . getOperand ( <NUM_LIT> ) . getInst ( ) -> getOpcode ( ) ; Result += ! isDuplexAGroup ( subInst0Opcode ) ; Result += ! isDuplexAGroup ( subInst1Opcode ) ; } else Result += Type != <STR_LIT> && Type != <STR_LIT> && Type != <STR_LIT> && Type != <STR_LIT> && Type != <STR_LIT> && ( Type != <STR_LIT> || <ISA_LIT>MCInstrInfo :: isFloat ( MCII , ID ) ) ; return Result != <NUM_LIT> ;


<s> if ( ReportErrors ) Context . reportError ( Loc , Msg ) ;


<s> void <ISA_LIT>MCChecker :: reportErrorNewValue ( unsigned Register ) { reportError ( <STR_LIT> + llvm :: Twine ( RI . getName ( Register ) ) + <STR_LIT> <STR_LIT> ) ;


<s> reportError ( <STR_LIT> + llvm :: Twine ( RI . getName ( Register ) ) + <STR_LIT> ) ;


<s> if ( ReportErrors ) { auto SM = Context . getSourceManager ( ) ; if ( SM ) SM -> PrintMessage ( MCB . getLoc ( ) , SourceMgr :: DK_Warning , Msg ) ; }


<s> if ( bLoadErrInfo == true ) { if ( ErrInfoQ . empty ( ) ) { CrntErrInfo . reset ( ) ; } else { CrntErrInfo . s = ErrInfoQ . front ( ) ; ErrInfoQ . pop ( ) ; } } bLoadErrInfo = false ;


<s> bool isPredicateRegister ( unsigned R ) const {

return ( <STR_LIT> == R || <STR_LIT> == R || <STR_LIT> == R || <STR_LIT> == R ) ;


<s> bool isPredicateRegister ( unsigned R ) const { return ( <STR_LIT> == R || <STR_LIT> == R || <STR_LIT> == R || <STR_LIT> == R ) ;


<s> NewSense NS = { <NUM_LIT> , false , isNVJ , false } ; return NS ;


<s> s . Warning = CHECK_SUCCESS ; s . ShuffleError = <ISA_LIT>Shuffler :: SHUFFLE_SUCCESS ; s . Register = <STR_LIT> ;


<s> s . ShuffleError = <ISA_LIT>Shuffler :: SHUFFLE_SUCCESS ;


<s> static NewSense Use ( unsigned PR , bool True ) { NewSense NS = { PR , false , false , True } ; return NS ;


<s> NewSense NS = { PR , false , false , True } ;


<s> if ( FullCheck ) chkSl = checkSlots ( ) ; bool chkAXOK = checkAXOK ( ) ; bool chkCofMax1 = checkCOFMax1 ( ) ; bool chkHWLoop = checkHWLoop ( ) ; bool chkValidTmpDst = FullCheck ? checkValidTmpDst ( ) : true ;

bool chkLegalVecRegPair = checkLegalVecRegPair ( ) ;


<s> bool <ISA_LIT>MCChecker :: check ( bool FullCheck ) { bool chkP = checkPredicates ( ) ; bool chkNV = checkNewValues ( ) ; bool chkR = checkRegisters ( ) ; bool chkRRO = checkRegistersReadOnly ( ) ; checkRegisterCurDefs ( ) ; bool chkS = checkSolo ( ) ; bool chkSh = true ; if ( FullCheck ) chkSh = checkShuffle ( ) ; bool chkSl = true ; if ( FullCheck ) chkSl = checkSlots ( ) ; bool chkAXOK = checkAXOK ( ) ; bool chkCofMax1 = checkCOFMax1 ( ) ;


<s> if ( S == R ) continue ; else S = R ; } if ( <STR_LIT> != R && <STR_LIT> == * SRI ) SoftDefs . insert ( * SRI ) ; else if ( <ISA_LIT>MCInstrInfo :: isPredicateLate ( MCII , MCI ) && isPredicateRegister ( * SRI ) ) LatePreds . insert ( * SRI ) ; else if ( i == <NUM_LIT> && <ISA_LIT>MCInstrInfo :: getType ( MCII , MCI ) == <STR_LIT> ) TmpDefs . insert ( * SRI ) ; else if ( i <= <NUM_LIT> && <ISA_LIT>MCInstrInfo :: hasNewValue2 ( MCII , MCI ) ) Uses . insert ( * SRI ) ; else if ( ! IgnoreTmpDst ) Defs [ * SRI ] . insert ( PredSense ( PredReg , isTrue ) ) ; } } if ( <ISA_LIT>MCInstrInfo :: isPredicatedNew ( MCII , MCI ) ) for ( unsigned i = MCID . getNumDefs ( ) ; i < MCID . getNumOperands ( ) ; ++ i ) if ( MCI . getOperand ( i ) . isReg ( ) ) {

unsigned P = MCI . getOperand ( i ) . getReg ( ) ;


<s> for ( unsigned i = <NUM_LIT> ; i < MCID . getNumImplicitUses ( ) ; ++ i ) initReg ( MCI , MCID . getImplicitUses ( ) [ i ] , PredReg , isTrue ) ; const bool IgnoreTmpDst = ( <ISA_LIT>MCInstrInfo :: hasTmpDst ( MCII , MCI ) || <ISA_LIT>MCInstrInfo :: hasHvxTmp ( MCII , MCI ) ) && STI . getFeatureBits ( ) [ <STR_LIT> ] ; if ( const MCPhysReg * ImpDef = MCID . getImplicitDefs ( ) ) for ( ; * ImpDef ; ++ ImpDef ) { unsigned R = * ImpDef ; if ( <STR_LIT> != R && MCID . isCall ( ) ) continue ; if ( <STR_LIT> == R ) continue ; if ( <STR_LIT> == R ) SoftDefs . insert ( R ) ; else if ( isPredicateRegister ( R ) && <ISA_LIT>MCInstrInfo :: isPredicateLate ( MCII , MCI ) ) LatePreds . insert ( R ) ; else if ( ! IgnoreTmpDst ) Defs [ R ] . insert ( PredSense ( PredReg , isTrue ) ) ; } for ( unsigned i = <NUM_LIT> ; i < MCID . getNumDefs ( ) ; ++ i ) { unsigned R = MCI . getOperand ( i ) . getReg ( ) , S = <STR_LIT> ; if ( R == <STR_LIT> ) R = <STR_LIT> ; if ( <ISA_LIT>MCInstrInfo :: IsReverseVecRegPair ( R ) ) ReversePairs . insert ( R ) ; for ( MCRegAliasIterator SRI ( R , & RI , ! MCSubRegIterator ( R , & RI ) . isValid ( ) ) ; SRI . isValid ( ) ; ++ SRI ) { if ( MCSubRegIterator ( * SRI , & RI ) . isValid ( ) ) continue ; if ( R == * SRI ) { if ( S == R ) continue ; else S = R ; }

if ( <STR_LIT> != R && <STR_LIT> == * SRI ) SoftDefs . insert ( * SRI ) ;


<s> if ( ! IsTarget ) continue ; unsigned int R = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; TmpDefsIterator It = TmpDefs . find ( R ) ; if ( It != TmpDefs . end ( ) ) { reportError ( <STR_LIT> + Twine ( RI . getName ( R ) ) + <STR_LIT> + <STR_LIT> ) ; return false ; } }


<s> bool IsTarget = <ISA_LIT>MCInstrInfo :: isAccumulator ( MCII , I ) && I . getOperand ( <NUM_LIT> ) . isReg ( ) ; if ( ! IsTarget ) continue ; unsigned int R = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; TmpDefsIterator It = TmpDefs . find ( R ) ; if ( It != TmpDefs . end ( ) ) {

reportError ( <STR_LIT> + Twine ( RI . getName ( R ) ) + <STR_LIT> + <STR_LIT> ) ;


<s> const unsigned RegDef = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool HasRegDefUse = false ; for ( MCRegAliasIterator Alias ( RegDef , & RI , true ) ; Alias . isValid ( ) ; ++ Alias ) HasRegDefUse = HasRegDefUse || registerUsed ( * Alias ) ; if ( ! HasRegDefUse ) reportWarning ( <STR_LIT> + Twine ( RI . getName ( RegDef ) ) + <STR_LIT> <STR_LIT> ) ;


<s> unsigned R = I . first ; if ( isLoopRegister ( R ) && Defs . count ( R ) > <NUM_LIT> && ( <ISA_LIT>MCInstrInfo :: isInnerLoop ( MCB ) || <ISA_LIT>MCInstrInfo :: isOuterLoop ( MCB ) ) ) { reportError ( <STR_LIT> <STR_LIT> ) ; return false ; } if ( SoftDefs . count ( R ) ) { unsigned UsrR = <STR_LIT> ; unsigned BadR = RI . isSubRegister ( <STR_LIT> , R ) ? UsrR : R ; reportErrorRegisters ( BadR ) ; return false ; } if ( ! <ISA_LIT>MCInstrInfo :: isPredReg ( RI , R ) && Defs [ R ] . size ( ) > <NUM_LIT> ) { PredSet & PM = Defs [ R ] ; if ( PM . count ( Unconditional ) ) { unsigned UsrR = <STR_LIT> ; unsigned BadR = RI . isSubRegister ( <STR_LIT> , R ) ? UsrR : R ; reportErrorRegisters ( BadR ) ; return false ; } for ( const auto & J : PM ) { PredSense P = J ; if ( PM . count ( P ) > <NUM_LIT> ) { reportErrorRegisters ( R ) ; return false ; } P . second = ! P . second ; if ( PM . count ( P ) && PM . size ( ) > <NUM_LIT> ) { reportErrorRegisters ( R ) ;


<s> } auto HasTmp = [ & ] ( MCInst const & I ) { return <ISA_LIT>MCInstrInfo :: hasTmpDst ( MCII , I ) || <ISA_LIT>MCInstrInfo :: hasHvxTmp ( MCII , I ) ; } ; unsigned HasTmpCount = llvm :: count_if ( <ISA_LIT>MCInstrInfo :: bundleInstructions ( MCII , MCB ) , HasTmp ) ; if ( HasTmpCount > <NUM_LIT> ) { reportError ( MCB . getLoc ( ) , <STR_LIT> ) ; for ( auto const & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( MCII , MCB ) ) if ( HasTmp ( I ) ) reportNote ( I . getLoc ( ) , <STR_LIT> ) ; return false ; } return true ;


<s> <ISA_LIT>MCChecker :: <ISA_LIT>MCChecker ( <ISA_LIT>MCChecker const & Other , MCSubtargetInfo const & STI , bool CopyReportErrors ) : Context ( Other . Context ) , MCB ( Other . MCB ) , RI ( Other . RI ) , MCII ( Other . MCII ) , STI ( STI ) , ReportErrors ( CopyReportErrors ? Other . ReportErrors : false ) { init ( ) ;


<s> if ( <STR_LIT> != R && <STR_LIT> == * SRI ) SoftDefs . insert ( * SRI ) ; else if ( <ISA_LIT>MCInstrInfo :: isPredicateLate ( MCII , MCI ) && <ISA_LIT>MCInstrInfo :: isPredReg ( RI , * SRI ) ) LatePreds . insert ( * SRI ) ; else if ( i == <NUM_LIT> && <ISA_LIT>MCInstrInfo :: getType ( MCII , MCI ) == <STR_LIT> ) TmpDefs . insert ( * SRI ) ; else if ( i <= <NUM_LIT> && <ISA_LIT>MCInstrInfo :: hasNewValue2 ( MCII , MCI ) ) Uses . insert ( * SRI ) ; else if ( ! IgnoreTmpDst ) Defs [ * SRI ] . insert ( PredSense ( PredReg , isTrue ) ) ; } } if ( <ISA_LIT>MCInstrInfo :: isPredicatedNew ( MCII , MCI ) ) for ( unsigned i = MCID . getNumDefs ( ) ; i < MCID . getNumOperands ( ) ; ++ i ) if ( MCI . getOperand ( i ) . isReg ( ) ) { unsigned P = MCI . getOperand ( i ) . getReg ( ) ; if ( <ISA_LIT>MCInstrInfo :: isPredReg ( RI , P ) ) NewPreds . insert ( P ) ;


<s> SRI . isValid ( ) ; ++ SRI ) if ( ! MCSubRegIterator ( * SRI , & RI ) . isValid ( ) ) Uses . insert ( * SRI ) ;

if ( <ISA_LIT>MCInstrInfo :: IsReverseVecRegPair ( R ) ) ReversePairs . insert ( R ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; case <STR_LIT> : { return ! isDuplexAGroup ( ID . getOpcode ( ) ) ; } case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; default : return true ;


<s> if ( <ISA_LIT>MCInstrInfo :: IsABranchingInst ( MCII , STI , I ) ) reportNote ( I . getLoc ( ) , <STR_LIT> ) ;


<s> static NewSense Def ( unsigned PR , bool True , bool Float ) {

NewSense NS = { PR , Float , false , True } ;


<s> NewSense NS = { PR , Float , false , True } ;


<s> static NewSense Jmp ( bool isNVJ ) {

NewSense NS = { <NUM_LIT> , false , isNVJ , false } ;


<s> NewSense NS = { PR , false , false , True } ; return NS ;


<s> static NewSense Use ( unsigned PR , bool True ) { NewSense NS = { PR , false , false , True } ;


<s> reportError ( I . getLoc ( ) , Twine ( <STR_LIT> ) + ( Inner ? <STR_LIT> : <STR_LIT> ) + <STR_LIT> + <STR_LIT> + <STR_LIT> + Twine ( RI . getName ( <STR_LIT> ) ) + <STR_LIT> ) ;


<s> bool chkSh = true ; if ( FullCheck ) chkSh = checkShuffle ( ) ; bool chkSl = true ; if ( FullCheck ) chkSl = checkSlots ( ) ; bool chkAXOK = checkAXOK ( ) ; bool chkCofMax1 = checkCOFMax1 ( ) ; bool chkHWLoop = checkHWLoop ( ) ; bool chk = chkP && chkNV && chkR && chkRRO && chkS && chkSh && chkSl && chkAXOK && chkCofMax1 && chkHWLoop ; return chk ;


<s> bool chkP = checkPredicates ( ) ; bool chkNV = checkNewValues ( ) ; bool chkR = checkRegisters ( ) ; bool chkRRO = checkRegistersReadOnly ( ) ; checkRegisterCurDefs ( ) ; bool chkS = checkSolo ( ) ; bool chkSh = true ; if ( FullCheck ) chkSh = checkShuffle ( ) ; bool chkSl = true ; if ( FullCheck ) chkSl = checkSlots ( ) ; bool chkAXOK = checkAXOK ( ) ; bool chkCofMax1 = checkCOFMax1 ( ) ; bool chkHWLoop = checkHWLoop ( ) ; bool chk = chkP && chkNV && chkR && chkRRO && chkS && chkSh && chkSl && chkAXOK && chkCofMax1 && chkHWLoop ; return chk ;


<s> if ( ! HasSoloAXInst ) return true ; for ( auto const & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( MCII , MCB ) ) { if ( & I != HasSoloAXInst && isNeitherAnorX ( MCII , I ) ) { reportError ( HasSoloAXInst -> getLoc ( ) , Twine ( <STR_LIT> <STR_LIT> ) ) ; reportError ( I . getLoc ( ) , Twine ( <STR_LIT> ) ) ; return false ;


<s> if ( & I != HasSoloAXInst && isNeitherAnorX ( MCII , I ) ) { reportError ( HasSoloAXInst -> getLoc ( ) , Twine ( <STR_LIT> <STR_LIT> ) ) ; reportError ( I . getLoc ( ) , Twine ( <STR_LIT> ) ) ; return false ; }


<s> MCInstrDesc const & Desc = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , I ) ; if ( Desc . isBranch ( ) || Desc . isCall ( ) || Desc . isReturn ( ) ) BranchLocations . push_back ( & I ) ; } for ( unsigned J = <NUM_LIT> , N = BranchLocations . size ( ) ; J < N ; ++ J ) { MCInst const & I = * BranchLocations [ J ] ; if ( <ISA_LIT>MCInstrInfo :: isCofMax1 ( MCII , I ) ) { bool Relax1 = <ISA_LIT>MCInstrInfo :: isCofRelax1 ( MCII , I ) ; bool Relax2 = <ISA_LIT>MCInstrInfo :: isCofRelax2 ( MCII , I ) ; if ( N > <NUM_LIT> && ! Relax1 && ! Relax2 ) { reportError ( I . getLoc ( ) , <STR_LIT> ) ; reportBranchErrors ( ) ; return false ; } if ( N > <NUM_LIT> && J == <NUM_LIT> && ! Relax1 ) { reportError ( I . getLoc ( ) , <STR_LIT> ) ; reportBranchErrors ( ) ; return false ; } if ( N > <NUM_LIT> && J == <NUM_LIT> && ! Relax2 ) { reportError ( I . getLoc ( ) , <STR_LIT> ) ; reportBranchErrors ( ) ; return false ; } } } return true ;


<s> if ( Desc . isBranch ( ) || Desc . isCall ( ) || Desc . isReturn ( ) ) { reportError ( MCB . getLoc ( ) , <STR_LIT> ) ; reportBranchErrors ( ) ; return false ; } } return true ;


<s> MCInstrDesc const & Desc = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , * std :: get < <NUM_LIT> > ( Producer ) ) ; if ( Desc . OpInfo [ std :: get < <NUM_LIT> > ( Producer ) ] . RegClass == <STR_LIT> ) { reportNote ( std :: get < <NUM_LIT> > ( Producer ) -> getLoc ( ) , <STR_LIT> ) ; reportError ( I . getLoc ( ) , <STR_LIT> ) ; return false ; } if ( ( Desc . mayLoad ( ) && std :: get < <NUM_LIT> > ( Producer ) == <NUM_LIT> ) || ( Desc . mayStore ( ) && std :: get < <NUM_LIT> > ( Producer ) == <NUM_LIT> ) ) { unsigned Mode = <ISA_LIT>MCInstrInfo :: getAddrMode ( MCII , * std :: get < <NUM_LIT> > ( Producer ) ) ; StringRef ModeError ; if ( Mode == <STR_LIT> ) ModeError = <STR_LIT> ; if ( Mode == <STR_LIT> ) ModeError = <STR_LIT> ; if ( ! ModeError . empty ( ) ) { reportNote ( std :: get < <NUM_LIT> > ( Producer ) -> getLoc ( ) , ModeError + <STR_LIT> <STR_LIT> ) ; reportError ( I . getLoc ( ) , <STR_LIT> ) ; return false ; } } if ( Branch && <ISA_LIT>MCInstrInfo :: isFloat ( MCII , * std :: get < <NUM_LIT> > ( Producer ) ) ) { reportNote ( std :: get < <NUM_LIT> > ( Producer ) -> getLoc ( ) , <STR_LIT> ) ; reportError ( I . getLoc ( ) , <STR_LIT> ) ; return false ; }


<s> unsigned P = I ; if ( LatePreds . count ( P ) > <NUM_LIT> || Defs . count ( P ) ) { reportErrorRegisters ( P ) ; return false ; } }


<s> for ( const auto & I : NewPreds ) { unsigned P = I ; if ( ! Defs . count ( P ) || LatePreds . count ( P ) ) { reportErrorNewValue ( P ) ; return false ; } } for ( const auto & I : LatePreds ) { unsigned P = I ;

if ( LatePreds . count ( P ) > <NUM_LIT> || Defs . count ( P ) ) {


<s> for ( auto const & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( MCII , MCB ) ) { if ( <ISA_LIT>MCInstrInfo :: isCVINew ( MCII , I ) && <ISA_LIT>MCInstrInfo :: getDesc ( MCII , I ) . mayLoad ( ) ) { unsigned Register = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! registerUsed ( Register ) ) reportWarning ( <STR_LIT> + Twine ( RI . getName ( Register ) ) + <STR_LIT> <STR_LIT> ) ; }


<s> return false ; } if ( SoftDefs . count ( R ) ) { unsigned UsrR = <STR_LIT> ; unsigned BadR = RI . isSubRegister ( <STR_LIT> , R ) ? UsrR : R ; reportErrorRegisters ( BadR ) ; return false ; } if ( ! isPredicateRegister ( R ) && Defs [ R ] . size ( ) > <NUM_LIT> ) { PredSet & PM = Defs [ R ] ; if ( PM . count ( Unconditional ) ) { unsigned UsrR = <STR_LIT> ; unsigned BadR = RI . isSubRegister ( <STR_LIT> , R ) ? UsrR : R ; reportErrorRegisters ( BadR ) ; return false ; } for ( const auto & J : PM ) { PredSense P = J ; if ( PM . count ( P ) > <NUM_LIT> ) { reportErrorRegisters ( R ) ; return false ; } P . second = ! P . second ; if ( PM . count ( P ) && PM . size ( ) > <NUM_LIT> ) { reportErrorRegisters ( R ) ; return false ; } } } } for ( const auto & I : TmpDefs ) { unsigned R = I ; if ( ! Uses . count ( R ) ) { bool vHistFound = false ; for ( auto const & HMI : <ISA_LIT>MCInstrInfo :: bundleInstructions ( MCB ) ) { if ( <ISA_LIT>MCInstrInfo :: getType ( MCII , * HMI . getInst ( ) ) == <STR_LIT> ) { vHistFound = true ; break ; }


<s> bool <ISA_LIT>MCChecker :: checkRegistersReadOnly ( ) { for ( auto I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( MCB ) ) { MCInst const & Inst = * I . getInst ( ) ; unsigned Defs = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , Inst ) . getNumDefs ( ) ; for ( unsigned j = <NUM_LIT> ; j < Defs ; ++ j ) { MCOperand const & Operand = Inst . getOperand ( j ) ; assert ( Operand . isReg ( ) && <STR_LIT> ) ; unsigned Register = Operand . getReg ( ) ; if ( ReadOnly . find ( Register ) != ReadOnly . end ( ) ) { reportError ( Inst . getLoc ( ) , <STR_LIT> + Twine ( RI . getName ( Register ) ) + <STR_LIT> ) ; return false ; } } }


<s> bool <ISA_LIT>MCChecker :: checkShuffle ( ) { <ISA_LIT>MCShuffler MCSDX ( Context , ReportErrors , MCII , STI , MCB ) ;


<s> bool <ISA_LIT>MCChecker :: checkShuffle ( ) { <ISA_LIT>MCShuffler MCSDX ( Context , ReportErrors , MCII , STI , MCB ) ; return MCSDX . check ( ) ;


<s> MCInst const & MCI = * HMI . getInst ( ) ; if ( <ISA_LIT>MCInstrInfo :: isImmext ( MCI ) ) continue ; if ( <ISA_LIT>MCInstrInfo :: isDuplex ( MCII , MCI ) ) slotsUsed += <NUM_LIT> ; else ++ slotsUsed ;


<s> break ; case <STR_LIT> : Register = <STR_LIT> ; break ; case <STR_LIT> : Register = <STR_LIT> ; break ; case <STR_LIT> : Register = <STR_LIT> ; break ; case <STR_LIT> : Register = <STR_LIT> ; break ; case <STR_LIT> :


<s> <ISA_LIT>MCChecker :: <ISA_LIT>MCChecker ( <ISA_LIT>MCChecker const & Other , MCSubtargetInfo const & STI , bool CopyReportErrors ) : Context ( Other . Context ) , MCB ( Other . MCB ) , RI ( Other . RI ) , MCII ( Other . MCII ) , STI ( STI ) , ReportErrors ( CopyReportErrors ? Other . ReportErrors : false ) {


<s> const MCInstrDesc & MCID = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) ; unsigned PredReg = <STR_LIT> ; bool isTrue = false ; for ( unsigned i = MCID . getNumDefs ( ) ; i < MCID . getNumOperands ( ) ; ++ i ) if ( MCI . getOperand ( i ) . isReg ( ) ) initReg ( MCI , MCI . getOperand ( i ) . getReg ( ) , PredReg , isTrue ) ; for ( unsigned i = <NUM_LIT> ; i < MCID . getNumImplicitUses ( ) ; ++ i ) initReg ( MCI , MCID . getImplicitUses ( ) [ i ] , PredReg , isTrue ) ; if ( const MCPhysReg * ImpDef = MCID . getImplicitDefs ( ) ) for ( ; * ImpDef ; ++ ImpDef ) { unsigned R = * ImpDef ; if ( <STR_LIT> != R && MCID . isCall ( ) ) continue ; if ( <STR_LIT> == R ) continue ; if ( <STR_LIT> == R ) SoftDefs . insert ( R ) ; else if ( isPredicateRegister ( R ) && <ISA_LIT>MCInstrInfo :: isPredicateLate ( MCII , MCI ) ) LatePreds . insert ( R ) ; else Defs [ R ] . insert ( PredSense ( PredReg , isTrue ) ) ; } for ( unsigned i = <NUM_LIT> ; i < MCID . getNumDefs ( ) ; ++ i ) { unsigned R = MCI . getOperand ( i ) . getReg ( ) , S = <STR_LIT> ; if ( R == <STR_LIT> ) R = <STR_LIT> ; for ( MCRegAliasIterator SRI ( R , & RI , ! MCSubRegIterator ( R , & RI ) . isValid ( ) ) ; SRI . isValid ( ) ; ++ SRI ) { if ( MCSubRegIterator ( * SRI , & RI ) . isValid ( ) ) continue ; if ( R == * SRI ) { if ( S == R ) continue ; else S = R ; } if ( <STR_LIT> != R && <STR_LIT> == * SRI ) SoftDefs . insert ( * SRI ) ; else if ( <ISA_LIT>MCInstrInfo :: isPredicateLate ( MCII , MCI ) && isPredicateRegister ( * SRI ) ) LatePreds . insert ( * SRI ) ; else if ( i == <NUM_LIT> && <ISA_LIT>MCInstrInfo :: getType ( MCII , MCI ) == <STR_LIT> ) TmpDefs . insert ( * SRI ) ; else if ( i <= <NUM_LIT> && <ISA_LIT>MCInstrInfo :: hasNewValue2 ( MCII , MCI ) ) Uses . insert ( * SRI ) ; else Defs [ * SRI ] . insert ( PredSense ( PredReg , isTrue ) ) ; } }

if ( <ISA_LIT>MCInstrInfo :: isPredicatedNew ( MCII , MCI ) ) for ( unsigned i = MCID . getNumDefs ( ) ; i < MCID . getNumOperands ( ) ; ++ i ) if ( MCI . getOperand ( i ) . isReg ( ) ) {


<s> if ( <ISA_LIT>MCInstrInfo :: isPredicatedNew ( MCII , MCI ) ) NewPreds . insert ( PredReg ) ; } else for ( MCRegAliasIterator SRI ( R , & RI , ! MCSubRegIterator ( R , & RI ) . isValid ( ) ) ;

SRI . isValid ( ) ; ++ SRI ) if ( ! MCSubRegIterator ( * SRI , & RI ) . isValid ( ) ) Uses . insert ( * SRI ) ;


<s> void <ISA_LIT>MCChecker :: initReg ( MCInst const & MCI , unsigned R , unsigned & PredReg , bool & isTrue ) { if ( <ISA_LIT>MCInstrInfo :: isPredicated ( MCII , MCI ) && isPredicateRegister ( R ) ) { PredReg = R ; isTrue = <ISA_LIT>MCInstrInfo :: isPredicatedTrue ( MCII , MCI ) ;

if ( <ISA_LIT>MCInstrInfo :: isPredicatedNew ( MCII , MCI ) ) NewPreds . insert ( PredReg ) ;


<s> static bool isDuplexAGroup ( unsigned Opcode ) { switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool isLoopRegister ( unsigned R ) const {


<s> Result += ! isDuplexAGroup ( subInst1Opcode ) ; } else Result += Type != <STR_LIT> && Type != <STR_LIT> && Type != <STR_LIT> && Type != <STR_LIT> && Type != <STR_LIT> && ( Type != <STR_LIT> || <ISA_LIT>MCInstrInfo :: isFloat ( MCII , ID ) ) ; return Result != <NUM_LIT> ;


<s> Result += ! isDuplexAGroup ( subInst1Opcode ) ;

} else Result += Type != <STR_LIT> && Type != <STR_LIT> && Type != <STR_LIT> && Type != <STR_LIT> && Type != <STR_LIT> && ( Type != <STR_LIT> || <ISA_LIT>MCInstrInfo :: isFloat ( MCII , ID ) ) ;


<s> for ( auto const & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( MCII , MCB ) ) for ( unsigned j = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , I ) . getNumDefs ( ) , n = I . getNumOperands ( ) ; j < n ; ++ j ) { MCOperand const & Operand = I . getOperand ( j ) ; if ( Operand . isReg ( ) && Operand . getReg ( ) == Register ) return true ; }


<s> j < n ; ++ j ) { MCOperand const & Operand = I . getOperand ( j ) ; if ( Operand . isReg ( ) && Operand . getReg ( ) == Register ) return true ; }


<s> void <ISA_LIT>MCChecker :: reportBranchErrors ( ) {

for ( auto const & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( MCII , MCB ) ) {


<s> for ( auto const & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( MCII , MCB ) ) { MCInstrDesc const & Desc = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , I ) ;

if ( Desc . isBranch ( ) || Desc . isCall ( ) || Desc . isReturn ( ) ) reportNote ( I . getLoc ( ) , <STR_LIT> ) ;


<s> if ( ReportErrors ) Context . reportError ( Loc , Msg ) ;


<s> void <ISA_LIT>MCChecker :: reportErrorNewValue ( unsigned Register ) { reportError ( <STR_LIT> + Twine ( RI . getName ( Register ) ) + <STR_LIT> <STR_LIT> ) ;


<s> void <ISA_LIT>MCChecker :: reportErrorNewValue ( unsigned Register ) {

reportError ( <STR_LIT> + Twine ( RI . getName ( Register ) ) + <STR_LIT> <STR_LIT> ) ;


<s> reportError ( <STR_LIT> + Twine ( RI . getName ( Register ) ) + <STR_LIT> ) ;


<s> if ( ReportErrors ) { auto SM = Context . getSourceManager ( ) ;

if ( SM ) SM -> PrintMessage ( Loc , SourceMgr :: DK_Note , Msg ) ;


<s> void <ISA_LIT>MCChecker :: reportWarning ( Twine const & Msg ) { if ( ReportErrors ) Context . reportWarning ( MCB . getLoc ( ) , Msg ) ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( MCInstrInfo const & MII , MCRegisterInfo const & MRI , MCContext & MCT ) { return new <ISA_LIT>MCCodeEmitter ( MII , MCT ) ;


<s> * Addend = <NUM_LIT> ; * Extended = false ; * CurrentBundle = & MI ; size_t Instruction = <NUM_LIT> ; size_t Last = <ISA_LIT>MCInstrInfo :: bundleSize ( HMB ) - <NUM_LIT> ; for ( auto & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( HMB ) ) { MCInst & HMI = const_cast < MCInst & > ( * I . getInst ( ) ) ; EncodeSingleInstruction ( HMI , OS , Fixups , STI , parseBits ( Instruction , Last , HMB , HMI ) , Instruction ) ; * Extended = <ISA_LIT>MCInstrInfo :: isImmext ( HMI ) ;


<s> MCInst & HMI = const_cast < MCInst & > ( * I . getInst ( ) ) ; EncodeSingleInstruction ( HMI , OS , Fixups , STI , parseBits ( Instruction , Last , HMB , HMI ) , Instruction ) ; * Extended = <ISA_LIT>MCInstrInfo :: isImmext ( HMI ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMachineOpValue ( MCInst const & MI , MCOperand const & MO , SmallVectorImpl < MCFixup > & Fixups , MCSubtargetInfo const & STI ) const {

if ( MO . isReg ( ) ) return MCT . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ;


<s> if ( MO . isReg ( ) ) return MCT . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MI , MO , MO . getExpr ( ) , Fixups , STI ) ;


<s> <ISA_LIT>MCCodeEmitter :: <ISA_LIT>MCCodeEmitter ( MCInstrInfo const & aMII , MCContext & aMCT ) : MCT ( aMCT ) , MCII ( aMII ) , Addend ( new unsigned ( <NUM_LIT> ) ) , Extended ( new bool ( false ) ) , CurrentBundle ( new MCInst const * ) {


<s> case fixup_<ISA_LIT>_B9_PCREL : case fixup_<ISA_LIT>_B32_PCREL_X : case fixup_<ISA_LIT>_B22_PCREL_X : case fixup_<ISA_LIT>_B15_PCREL_X : case fixup_<ISA_LIT>_B13_PCREL_X : case fixup_<ISA_LIT>_B9_PCREL_X : case fixup_<ISA_LIT>_B7_PCREL_X : case fixup_<ISA_LIT>_32_PCREL :


<s> case fixup_<ISA_LIT>_B15_PCREL : case fixup_<ISA_LIT>_B7_PCREL : case fixup_<ISA_LIT>_B13_PCREL : case fixup_<ISA_LIT>_B9_PCREL : case fixup_<ISA_LIT>_B32_PCREL_X : case fixup_<ISA_LIT>_B22_PCREL_X : case fixup_<ISA_LIT>_B15_PCREL_X : case fixup_<ISA_LIT>_B13_PCREL_X : case fixup_<ISA_LIT>_B9_PCREL_X : case fixup_<ISA_LIT>_B7_PCREL_X : case fixup_<ISA_LIT>_32_PCREL : case fixup_<ISA_LIT>_PLT_B22_PCREL :


<s> uint32_t <ISA_LIT>MCCodeEmitter :: parseBits ( size_t Instruction , size_t Last , MCInst const & MCB , MCInst const & MCI ) const { bool Duplex = <ISA_LIT>MCInstrInfo :: isDuplex ( MCII , MCI ) ; if ( Instruction == <NUM_LIT> ) { if ( <ISA_LIT>MCInstrInfo :: isInnerLoop ( MCB ) ) { assert ( ! Duplex ) ; assert ( Instruction != Last ) ; return <STR_LIT> ; } } if ( Instruction == <NUM_LIT> ) { if ( <ISA_LIT>MCInstrInfo :: isOuterLoop ( MCB ) ) { assert ( ! Duplex ) ; assert ( Instruction != Last ) ; return <STR_LIT> ; } } if ( Duplex ) { assert ( Instruction == Last ) ; return <STR_LIT> ; }

if ( Instruction == Last ) return <STR_LIT> ;


<s> bool Duplex = <ISA_LIT>MCInstrInfo :: isDuplex ( MCII , MCI ) ; if ( Instruction == <NUM_LIT> ) { if ( <ISA_LIT>MCInstrInfo :: isInnerLoop ( MCB ) ) { assert ( ! Duplex ) ; assert ( Instruction != Last ) ; return <STR_LIT> ; } } if ( Instruction == <NUM_LIT> ) { if ( <ISA_LIT>MCInstrInfo :: isOuterLoop ( MCB ) ) { assert ( ! Duplex ) ;


<s> State . Bundle = & MI ; State . Index = <NUM_LIT> ; size_t Last = <ISA_LIT>MCInstrInfo :: bundleSize ( HMB ) - <NUM_LIT> ; FeatureBitset Features = computeAvailableFeatures ( STI . getFeatureBits ( ) ) ; for ( auto & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( HMB ) ) { MCInst & HMI = const_cast < MCInst & > ( * I . getInst ( ) ) ; verifyInstructionPredicates ( HMI , Features ) ; EncodeSingleInstruction ( HMI , OS , Fixups , STI , parseBits ( Last , HMB , HMI ) ) ; State . Extended = <ISA_LIT>MCInstrInfo :: isImmext ( HMI ) ;


<s> if ( ! Binary && Opc != DuplexIClass0 && Opc != A4_ext ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>MCInstrInfo :: getName ( MCII , MI ) << <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } Binary |= Parse ; if ( Opc >= <STR_LIT> && Opc <= <STR_LIT> ) { assert ( Parse == <STR_LIT> && <STR_LIT> ) ; unsigned DupIClass = MI . getOpcode ( ) - <STR_LIT> ;

Binary = ( ( DupIClass & <NUM_LIT> ) << ( <NUM_LIT> - <NUM_LIT> ) ) | ( ( DupIClass & <NUM_LIT> ) << <NUM_LIT> ) ;


<s> assert ( I + <NUM_LIT> != N && <STR_LIT> ) ; const MCInst & NextI = * ( I + <NUM_LIT> ) -> getInst ( ) ; const MCInstrDesc & NextD = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , NextI ) ; if ( NextD . isBranch ( ) || NextD . isCall ( ) || <ISA_LIT>MCInstrInfo :: getType ( MCII , NextI ) == <STR_LIT> ) return fixup_<ISA_LIT>_B32_PCREL_X ; return fixup_<ISA_LIT>_32_6_X ; } } static const std :: map < unsigned , unsigned > Relocs = { { MCSymbolRefExpr :: VK_GOTREL , fixup_<ISA_LIT>_GOTREL_32_6_X } , { MCSymbolRefExpr :: VK_GOT , fixup_<ISA_LIT>_GOT_32_6_X } , { MCSymbolRefExpr :: VK_TPREL , fixup_<ISA_LIT>_TPREL_32_6_X } , { MCSymbolRefExpr :: VK_DTPREL , fixup_<ISA_LIT>_DTPREL_32_6_X } , { MCSymbolRefExpr :: VK_<ISA_LIT>_GD_GOT , fixup_<ISA_LIT>_GD_GOT_32_6_X } , { MCSymbolRefExpr :: VK_<ISA_LIT>_LD_GOT , fixup_<ISA_LIT>_LD_GOT_32_6_X } , { MCSymbolRefExpr :: VK_<ISA_LIT>_IE , fixup_<ISA_LIT>_IE_32_6_X } , { MCSymbolRefExpr :: VK_<ISA_LIT>_IE_GOT , fixup_<ISA_LIT>_IE_GOT_32_6_X } , { MCSymbolRefExpr :: VK_PCREL , fixup_<ISA_LIT>_B32_PCREL_X } , { MCSymbolRefExpr :: VK_<ISA_LIT>_GD_PLT , fixup_<ISA_LIT>_GD_PLT_B32_PCREL_X } , { MCSymbolRefExpr :: VK_<ISA_LIT>_LD_PLT , fixup_<ISA_LIT>_LD_PLT_B32_PCREL_X } , } ; auto F = Relocs . find ( VarKind ) ; if ( F != Relocs . end ( ) ) return <STR_LIT> ( F -> second ) ; raise_relocation_error ( <NUM_LIT> , VarKind ) ;


<s> for ( unsigned i = <NUM_LIT> , n = MI . getNumOperands ( ) ; i < n ; ++ i ) if ( & MI . getOperand ( i ) == & MO ) { OperandNumber = i ; break ; } assert ( ( OperandNumber != ~ <NUM_LIT> ) && <STR_LIT> ) ; if ( <ISA_LIT>MCInstrInfo :: isNewValue ( MCII , MI ) && & MO == & <ISA_LIT>MCInstrInfo :: getNewValueOperand ( MCII , MI ) ) { unsigned SOffset = <NUM_LIT> ; unsigned VOffset = <NUM_LIT> ; unsigned UseReg = MO . getReg ( ) ; unsigned DefReg1 = <STR_LIT> ; unsigned DefReg2 = <STR_LIT> ; auto Instrs = <ISA_LIT>MCInstrInfo :: bundleInstructions ( * State . Bundle ) ; const MCOperand * I = Instrs . begin ( ) + State . Index - <NUM_LIT> ; for ( ; ; -- I ) { assert ( I != Instrs . begin ( ) - <NUM_LIT> && <STR_LIT> ) ; MCInst const & Inst = * I -> getInst ( ) ; if ( <ISA_LIT>MCInstrInfo :: isImmext ( Inst ) ) continue ; DefReg1 = <STR_LIT> ; DefReg2 = <STR_LIT> ; ++ SOffset ; if ( <ISA_LIT>MCInstrInfo :: isVector ( MCII , Inst ) ) { ++ VOffset ; } if ( <ISA_LIT>MCInstrInfo :: hasNewValue ( MCII , Inst ) ) DefReg1 = <ISA_LIT>MCInstrInfo :: getNewValueOperand ( MCII , Inst ) . getReg ( ) ; if ( <ISA_LIT>MCInstrInfo :: hasNewValue2 ( MCII , Inst ) ) DefReg2 = <ISA_LIT>MCInstrInfo :: getNewValueOperand2 ( MCII , Inst ) . getReg ( ) ; if ( ! RegisterMatches ( UseReg , DefReg1 , DefReg2 ) ) { continue ; } if ( ! <ISA_LIT>MCInstrInfo :: isPredicated ( MCII , Inst ) ) { break ; } assert ( <ISA_LIT>MCInstrInfo :: isPredicated ( MCII , MI ) && <STR_LIT> ) ; if ( <ISA_LIT>MCInstrInfo :: isPredicatedTrue ( MCII , Inst ) == <ISA_LIT>MCInstrInfo :: isPredicatedTrue ( MCII , MI ) ) break ; } unsigned Offset = <ISA_LIT>MCInstrInfo :: isVector ( MCII , MI ) ? VOffset : SOffset ; Offset <<= <NUM_LIT> ; Offset |= <ISA_LIT>MCInstrInfo :: SubregisterBit ( UseReg , DefReg1 , DefReg2 ) ; return Offset ; } assert ( ! MO . isImm ( ) ) ; if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; switch ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MI ) . OpInfo [ OperandNumber ] . RegClass ) { case GeneralSubRegsRegClassID : case GeneralDoubleLow8RegsRegClassID : return <ISA_LIT>MCInstrInfo :: getDuplexRegisterNumbering ( Reg ) ; default : break ; }

return MCT . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ;


<s> size_t OperandNumber = ~ <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , n = MI . getNumOperands ( ) ; i < n ; ++ i ) if ( & MI . getOperand ( i ) == & MO ) { OperandNumber = i ; break ; } assert ( ( OperandNumber != ~ <NUM_LIT> ) && <STR_LIT> ) ; if ( <ISA_LIT>MCInstrInfo :: isNewValue ( MCII , MI ) && & MO == & <ISA_LIT>MCInstrInfo :: getNewValueOperand ( MCII , MI ) ) { unsigned SOffset = <NUM_LIT> ; unsigned VOffset = <NUM_LIT> ; unsigned UseReg = MO . getReg ( ) ; unsigned DefReg1 = <STR_LIT> ; unsigned DefReg2 = <STR_LIT> ; auto Instrs = <ISA_LIT>MCInstrInfo :: bundleInstructions ( * State . Bundle ) ; const MCOperand * I = Instrs . begin ( ) + State . Index - <NUM_LIT> ; for ( ; ; -- I ) { assert ( I != Instrs . begin ( ) - <NUM_LIT> && <STR_LIT> ) ; MCInst const & Inst = * I -> getInst ( ) ; if ( <ISA_LIT>MCInstrInfo :: isImmext ( Inst ) ) continue ; DefReg1 = <STR_LIT> ; DefReg2 = <STR_LIT> ; ++ SOffset ; if ( <ISA_LIT>MCInstrInfo :: isVector ( MCII , Inst ) ) { ++ VOffset ; } if ( <ISA_LIT>MCInstrInfo :: hasNewValue ( MCII , Inst ) ) DefReg1 = <ISA_LIT>MCInstrInfo :: getNewValueOperand ( MCII , Inst ) . getReg ( ) ; if ( <ISA_LIT>MCInstrInfo :: hasNewValue2 ( MCII , Inst ) ) DefReg2 = <ISA_LIT>MCInstrInfo :: getNewValueOperand2 ( MCII , Inst ) . getReg ( ) ; if ( ! RegisterMatches ( UseReg , DefReg1 , DefReg2 ) ) { continue ; } if ( ! <ISA_LIT>MCInstrInfo :: isPredicated ( MCII , Inst ) ) { break ; } assert ( <ISA_LIT>MCInstrInfo :: isPredicated ( MCII , MI ) && <STR_LIT> ) ; if ( <ISA_LIT>MCInstrInfo :: isPredicatedTrue ( MCII , Inst ) == <ISA_LIT>MCInstrInfo :: isPredicatedTrue ( MCII , MI ) ) break ; } unsigned Offset = <ISA_LIT>MCInstrInfo :: isVector ( MCII , MI ) ? VOffset : SOffset ; Offset <<= <NUM_LIT> ; Offset |= <ISA_LIT>MCInstrInfo :: SubregisterBit ( UseReg , DefReg1 , DefReg2 ) ; return Offset ;


<s> case fixup_<ISA_LIT>_B9_PCREL : case fixup_<ISA_LIT>_B32_PCREL_X : case fixup_<ISA_LIT>_B22_PCREL_X : case fixup_<ISA_LIT>_B15_PCREL_X : case fixup_<ISA_LIT>_B13_PCREL_X : case fixup_<ISA_LIT>_B9_PCREL_X : case fixup_<ISA_LIT>_B7_PCREL_X : case fixup_<ISA_LIT>_32_PCREL : case fixup_<ISA_LIT>_PLT_B22_PCREL : case fixup_<ISA_LIT>_GD_PLT_B22_PCREL : case fixup_<ISA_LIT>_LD_PLT_B22_PCREL : case fixup_<ISA_LIT>_GD_PLT_B22_PCREL_X : case fixup_<ISA_LIT>_LD_PLT_B22_PCREL_X :


<s> if ( <ISA_LIT>MCInstrInfo :: isInnerLoop ( MCB ) ) { assert ( ! Duplex ) ; assert ( State . Index != Last ) ; return <STR_LIT> ; } } if ( State . Index == <NUM_LIT> ) { if ( <ISA_LIT>MCInstrInfo :: isOuterLoop ( MCB ) ) { assert ( ! Duplex ) ; assert ( State . Index != Last ) ; return <STR_LIT> ; } } if ( Duplex ) { assert ( State . Index == Last ) ; return <STR_LIT> ; } if ( State . Index == Last ) return <STR_LIT> ; return <STR_LIT> ;


<s> raw_string_ostream Stream ( Text ) ;

Stream << <STR_LIT> << Width << <STR_LIT> << Kind ;


<s> [ [ noreturn ] ] static void raise_relocation_error ( unsigned Width , unsigned Kind ) { std :: string Text ; raw_string_ostream Stream ( Text ) ; Stream << <STR_LIT> << Width << <STR_LIT> << Kind ; report_fatal_error ( Twine ( Stream . str ( ) ) ) ;


<s> static bool RegisterMatches ( unsigned Consumer , unsigned Producer , unsigned Producer2 ) { return ( Consumer == Producer ) || ( Consumer == Producer2 ) || <ISA_LIT>MCInstrInfo :: IsSingleConsumerRefPairProducer ( Producer , Consumer ) ;


<s> if ( <ISA_LIT>MCInstrInfo :: isVector ( MCII , Inst ) ) { ++ VOffset ; } if ( <ISA_LIT>MCInstrInfo :: hasNewValue ( MCII , Inst ) ) DefReg1 = <ISA_LIT>MCInstrInfo :: getNewValueOperand ( MCII , Inst ) . getReg ( ) ; if ( <ISA_LIT>MCInstrInfo :: hasNewValue2 ( MCII , Inst ) ) DefReg2 = <ISA_LIT>MCInstrInfo :: getNewValueOperand2 ( MCII , Inst ) . getReg ( ) ; if ( ! RegisterMatches ( UseReg , DefReg1 , DefReg2 ) ) { continue ; } if ( ! <ISA_LIT>MCInstrInfo :: isPredicated ( MCII , Inst ) ) { break ; } assert ( <ISA_LIT>MCInstrInfo :: isPredicated ( MCII , MI ) && <STR_LIT> ) ; if ( <ISA_LIT>MCInstrInfo :: isPredicatedTrue ( MCII , Inst ) == <ISA_LIT>MCInstrInfo :: isPredicatedTrue ( MCII , MI ) ) break ; } unsigned Offset = <ISA_LIT>MCInstrInfo :: isVector ( MCII , MI ) ? VOffset : SOffset ; Offset <<= <NUM_LIT> ; Offset |= <ISA_LIT>MCInstrInfo :: SubregisterBit ( UseReg , DefReg1 , DefReg2 ) ; return Offset ;


<s> assert ( i != Instructions . begin ( ) - <NUM_LIT> && <STR_LIT> ) ; MCInst const & Inst = * i -> getInst ( ) ; if ( <ISA_LIT>MCInstrInfo :: isImmext ( Inst ) ) continue ; ++ SOffset ; Register1 = <ISA_LIT>MCInstrInfo :: hasNewValue ( MCII , Inst ) ? <ISA_LIT>MCInstrInfo :: getNewValueOperand ( MCII , Inst ) . getReg ( ) : static_cast < unsigned > ( <STR_LIT> ) ; if ( Register != Register1 ) continue ; if ( ! <ISA_LIT>MCInstrInfo :: isPredicated ( MCII , Inst ) ) break ; assert ( <ISA_LIT>MCInstrInfo :: isPredicated ( MCII , HMB ) && <STR_LIT> ) ; if ( <ISA_LIT>MCInstrInfo :: isPredicatedTrue ( MCII , Inst ) == <ISA_LIT>MCInstrInfo :: isPredicatedTrue ( MCII , HMB ) ) break ; } unsigned Offset = SOffset ; Offset <<= <NUM_LIT> ; MCO . setReg ( Offset + <STR_LIT> ) ; } Binary = getBinaryCodeForInstr ( HMB , Fixups , STI ) ; if ( ( ! Binary ) && ( ( HMB . getOpcode ( ) != DuplexIClass0 ) && ( HMB . getOpcode ( ) != A4_ext ) && ( HMB . getOpcode ( ) != A4_ext_b ) && ( HMB . getOpcode ( ) != A4_ext_c ) && ( HMB . getOpcode ( ) != A4_ext_g ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << <ISA_LIT>MCInstrInfo :: getName ( MCII , HMB ) << <STR_LIT> <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } Binary |= Parse ; if ( HMB . getOpcode ( ) >= <STR_LIT> && HMB . getOpcode ( ) <= <STR_LIT> ) { assert ( Parse == <STR_LIT> && <STR_LIT> ) ; unsigned dupIClass ; switch ( HMB . getOpcode ( ) ) { case <STR_LIT> : dupIClass = <NUM_LIT> ; break ; case <STR_LIT> : dupIClass = <NUM_LIT> ; break ; case <STR_LIT> : dupIClass = <NUM_LIT> ; break ; case <STR_LIT> : dupIClass = <NUM_LIT> ; break ; case <STR_LIT> : dupIClass = <NUM_LIT> ; break ;


<s> case llvm :: MCSymbolRefExpr :: VK_TPREL : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_DTPREL : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_<ISA_LIT>_GD_GOT : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_<ISA_LIT>_LD_GOT : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_<ISA_LIT>_IE : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_<ISA_LIT>_IE_GOT : return <STR_LIT> ; default : if ( MCID . isBranch ( ) ) return <STR_LIT> ; else return <STR_LIT> ; } } else if ( MCID . isBranch ( ) ) return ( <STR_LIT> ) ; switch ( MCID . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : switch ( kind ) { case llvm :: MCSymbolRefExpr :: VK_GOT : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_GOTOFF : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_<ISA_LIT>_GD_GOT : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_<ISA_LIT>_LD_GOT : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_<ISA_LIT>_IE : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_<ISA_LIT>_IE_GOT : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_TPREL : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_DTPREL : return <STR_LIT> ; default : return <STR_LIT> ; } case <STR_LIT> : case <STR_LIT> : switch ( kind ) { case llvm :: MCSymbolRefExpr :: VK_GOT : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_GOTOFF : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_<ISA_LIT>_GD_GOT : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_<ISA_LIT>_LD_GOT : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_<ISA_LIT>_IE : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_<ISA_LIT>_IE_GOT : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_TPREL : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_DTPREL : return <STR_LIT> ; default : return <STR_LIT> ;


<s> size_t Last = <ISA_LIT>MCInstrInfo :: bundleSize ( HMB ) - <NUM_LIT> ; for ( auto & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( HMB ) ) { MCInst & HMI = const_cast < MCInst & > ( * I . getInst ( ) ) ; verifyInstructionPredicates ( HMI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; EncodeSingleInstruction ( HMI , OS , Fixups , STI , parseBits ( Last , HMB , HMI ) ) ; * Extended = <ISA_LIT>MCInstrInfo :: isImmext ( HMI ) ; * Addend += HEXAGON_INSTR_SIZE ; ++ * CurrentIndex ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; * Addend = <NUM_LIT> ; * Extended = false ; * CurrentBundle = & MI ; * CurrentIndex = <NUM_LIT> ; size_t Last = <ISA_LIT>MCInstrInfo :: bundleSize ( HMB ) - <NUM_LIT> ; for ( auto & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( HMB ) ) { MCInst & HMI = const_cast < MCInst & > ( * I . getInst ( ) ) ; verifyInstructionPredicates ( HMI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; EncodeSingleInstruction ( HMI , OS , Fixups , STI , parseBits ( Last , HMB , HMI ) ) ; * Extended = <ISA_LIT>MCInstrInfo :: isImmext ( HMI ) ; * Addend += HEXAGON_INSTR_SIZE ;


<s> void <ISA_LIT>MCCodeEmitter :: EncodeSingleInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI , uint32_t Parse ) const { assert ( ! <ISA_LIT>MCInstrInfo :: isBundle ( MI ) ) ; uint64_t Binary ; assert ( ! <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MI ) . isPseudo ( ) && <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << <ISA_LIT>MCInstrInfo :: getName ( MCII , MI ) << <STR_LIT> <STR_LIT> ) ; Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; if ( ! Binary && MI . getOpcode ( ) != DuplexIClass0 && MI . getOpcode ( ) != A4_ext ) { DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << <ISA_LIT>MCInstrInfo :: getName ( MCII , MI ) << <STR_LIT> <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } Binary |= Parse ; if ( MI . getOpcode ( ) >= <STR_LIT> && MI . getOpcode ( ) <= <STR_LIT> ) { assert ( Parse == <STR_LIT> && <STR_LIT> ) ; unsigned dupIClass = MI . getOpcode ( ) - <STR_LIT> ; Binary = ( ( dupIClass & <NUM_LIT> ) << ( <NUM_LIT> - <NUM_LIT> ) ) | ( ( dupIClass & <NUM_LIT> ) << <NUM_LIT> ) ; const MCInst * subInst0 = MI . getOperand ( <NUM_LIT> ) . getInst ( ) ; const MCInst * subInst1 = MI . getOperand ( <NUM_LIT> ) . getInst ( ) ; unsigned subInstSlot0Bits = getBinaryCodeForInstr ( * subInst0 , Fixups , STI ) ; unsigned subInstSlot1Bits = getBinaryCodeForInstr ( * subInst1 , Fixups , STI ) ; Binary |= subInstSlot0Bits | ( subInstSlot1Bits << <NUM_LIT> ) ; } <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write < uint32_t > ( Binary ) ; ++ MCNumEmitted ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << <ISA_LIT>MCInstrInfo :: getName ( MCII , MI ) << <STR_LIT> <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } Binary |= Parse ; if ( MI . getOpcode ( ) >= <STR_LIT> && MI . getOpcode ( ) <= <STR_LIT> ) { assert ( Parse == <STR_LIT> && <STR_LIT> ) ; unsigned dupIClass = MI . getOpcode ( ) - <STR_LIT> ; Binary = ( ( dupIClass & <NUM_LIT> ) << ( <NUM_LIT> - <NUM_LIT> ) ) | ( ( dupIClass & <NUM_LIT> ) << <NUM_LIT> ) ; const MCInst * subInst0 = MI . getOperand ( <NUM_LIT> ) . getInst ( ) ; const MCInst * subInst1 = MI . getOperand ( <NUM_LIT> ) . getInst ( ) ; unsigned subInstSlot0Bits = getBinaryCodeForInstr ( * subInst0 , Fixups , STI ) ;

unsigned subInstSlot1Bits = getBinaryCodeForInstr ( * subInst1 , Fixups , STI ) ;


<s> for ( ; ; -- i ) { assert ( i != Instructions . begin ( ) - <NUM_LIT> && <STR_LIT> ) ; MCInst const & Inst = * i -> getInst ( ) ; if ( <ISA_LIT>MCInstrInfo :: isImmext ( Inst ) ) continue ; ++ SOffset ; if ( <ISA_LIT>MCInstrInfo :: isVector ( MCII , Inst ) ) ++ VOffset ; Register1 = <ISA_LIT>MCInstrInfo :: hasNewValue ( MCII , Inst ) ? <ISA_LIT>MCInstrInfo :: getNewValueOperand ( MCII , Inst ) . getReg ( ) : static_cast < unsigned > ( <STR_LIT> ) ; Register2 = <ISA_LIT>MCInstrInfo :: hasNewValue2 ( MCII , Inst ) ? <ISA_LIT>MCInstrInfo :: getNewValueOperand2 ( MCII , Inst ) . getReg ( ) : static_cast < unsigned > ( <STR_LIT> ) ; if ( ! RegisterMatches ( Register , Register1 , Register2 ) ) continue ; if ( ! <ISA_LIT>MCInstrInfo :: isPredicated ( MCII , Inst ) ) break ; assert ( <ISA_LIT>MCInstrInfo :: isPredicated ( MCII , MI ) && <STR_LIT> ) ; if ( <ISA_LIT>MCInstrInfo :: isPredicatedTrue ( MCII , Inst ) == <ISA_LIT>MCInstrInfo :: isPredicatedTrue ( MCII , MI ) ) break ; } unsigned Offset = <ISA_LIT>MCInstrInfo :: isVector ( MCII , MI ) ? VOffset : SOffset ;


<s> <ISA_LIT>MCCodeEmitter :: <ISA_LIT>MCCodeEmitter ( MCInstrInfo const & aMII , MCContext & aMCT ) : MCT ( aMCT ) , MCII ( aMII ) , Addend ( new unsigned ( <NUM_LIT> ) ) , Extended ( new bool ( false ) ) , CurrentBundle ( new MCInst const * ) , CurrentIndex ( new size_t ( <NUM_LIT> ) ) {


<s> switch ( Kind ) { case fixup_<ISA_LIT>_B22_PCREL : case fixup_<ISA_LIT>_B15_PCREL : case fixup_<ISA_LIT>_B7_PCREL : case fixup_<ISA_LIT>_B13_PCREL : case fixup_<ISA_LIT>_B9_PCREL : case fixup_<ISA_LIT>_B32_PCREL_X : case fixup_<ISA_LIT>_B22_PCREL_X : case fixup_<ISA_LIT>_B15_PCREL_X : case fixup_<ISA_LIT>_B13_PCREL_X :


<s> case fixup_<ISA_LIT>_B7_PCREL : case fixup_<ISA_LIT>_B13_PCREL : case fixup_<ISA_LIT>_B9_PCREL : case fixup_<ISA_LIT>_B32_PCREL_X : case fixup_<ISA_LIT>_B22_PCREL_X : case fixup_<ISA_LIT>_B15_PCREL_X : case fixup_<ISA_LIT>_B13_PCREL_X : case fixup_<ISA_LIT>_B9_PCREL_X : case fixup_<ISA_LIT>_B7_PCREL_X : case fixup_<ISA_LIT>_32_PCREL : case fixup_<ISA_LIT>_PLT_B22_PCREL : case fixup_<ISA_LIT>_GD_PLT_B22_PCREL :


<s> if ( VarKind == MCSymbolRefExpr :: VK_None ) { auto Instrs = <ISA_LIT>MCInstrInfo :: bundleInstructions ( * State . Bundle ) ; for ( auto I = Instrs . begin ( ) , N = Instrs . end ( ) ; I != N ; ++ I ) { if ( I -> getInst ( ) != & MI ) continue ; assert ( I + <NUM_LIT> != N && <STR_LIT> ) ; const MCInst & NextI = * ( I + <NUM_LIT> ) -> getInst ( ) ; const MCInstrDesc & NextD = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , NextI ) ; if ( NextD . isBranch ( ) || NextD . isCall ( ) || <ISA_LIT>MCInstrInfo :: getType ( MCII , NextI ) == <STR_LIT> ) return fixup_<ISA_LIT>_B32_PCREL_X ; return fixup_<ISA_LIT>_32_6_X ; } } static const std :: map < unsigned , unsigned > Relocs = { { MCSymbolRefExpr :: VK_GOTREL , fixup_<ISA_LIT>_GOTREL_32_6_X } , { MCSymbolRefExpr :: VK_GOT , fixup_<ISA_LIT>_GOT_32_6_X } , { MCSymbolRefExpr :: VK_TPREL , fixup_<ISA_LIT>_TPREL_32_6_X } , { MCSymbolRefExpr :: VK_DTPREL , fixup_<ISA_LIT>_DTPREL_32_6_X } , { MCSymbolRefExpr :: VK_<ISA_LIT>_GD_GOT , fixup_<ISA_LIT>_GD_GOT_32_6_X } , { MCSymbolRefExpr :: VK_<ISA_LIT>_LD_GOT , fixup_<ISA_LIT>_LD_GOT_32_6_X } , { MCSymbolRefExpr :: VK_<ISA_LIT>_IE , fixup_<ISA_LIT>_IE_32_6_X } , { MCSymbolRefExpr :: VK_<ISA_LIT>_IE_GOT , fixup_<ISA_LIT>_IE_GOT_32_6_X } , { MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL , fixup_<ISA_LIT>_B32_PCREL_X } , { MCSymbolRefExpr :: VK_<ISA_LIT>_GD_PLT , fixup_<ISA_LIT>_GD_PLT_B32_PCREL_X } , { MCSymbolRefExpr :: VK_<ISA_LIT>_LD_PLT , fixup_<ISA_LIT>_LD_PLT_B32_PCREL_X } , } ; auto F = Relocs . find ( VarKind ) ; if ( F != Relocs . end ( ) ) return <STR_LIT> ( F -> second ) ; raise_relocation_error ( <NUM_LIT> , VarKind ) ; }

if ( MCID . isBranch ( ) ) return fixup_<ISA_LIT>_B13_PCREL ;


<s> Stream << <STR_LIT> << Width << <STR_LIT> << Kind ; report_fatal_error ( Stream . str ( ) ) ;


<s> LLVM_ATTRIBUTE_NORETURN static void raise_relocation_error ( unsigned Width , unsigned Kind ) {


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : if ( Reg == <STR_LIT> ) Reg = <STR_LIT> ; if ( Reg == <STR_LIT> ) Reg = <STR_LIT> ; } return MCT . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ; } return getExprOpValue ( MI , MO , MO . getExpr ( ) , Fixups , STI ) ;


<s> if ( Reg == <STR_LIT> ) Reg = <STR_LIT> ; if ( Reg == <STR_LIT> ) Reg = <STR_LIT> ; } return MCT . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ; } return getExprOpValue ( MI , MO , MO . getExpr ( ) , Fixups , STI ) ;


<s> if ( Consumer == Producer ) return true ; if ( Consumer == Producer2 ) return true ; if ( Producer >= <STR_LIT> && Producer <= <STR_LIT> ) if ( Consumer >= <STR_LIT> && Consumer <= <STR_LIT> ) return ( ( Consumer - <STR_LIT> ) >> <NUM_LIT> ) == ( Producer - <STR_LIT> ) ; return false ;


<s> OS << static_cast < uint8_t > ( ( Binary >> <NUM_LIT> ) & <NUM_LIT> ) ; OS << static_cast < uint8_t > ( ( Binary >> <NUM_LIT> ) & <NUM_LIT> ) ;


<s> assert ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MI ) . getSize ( ) == <NUM_LIT> && <STR_LIT> ) ; ( void ) & MCII ; emitLittleEndian ( Binary , OS ) ; ++ MCNumEmitted ;


<s> if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ;


<s> unsigned const ParseFieldOffset = <NUM_LIT> ;

ParseField Field = <ISA_LIT>MCInstrInfo :: isPacketEnd ( HMI ) ? ParseField :: end : ParseField :: last0 ;


<s> uint32_t getPacketBits ( MCInst const & HMI ) { unsigned const ParseFieldOffset = <NUM_LIT> ;


<s> <ISA_LIT>MCCodeEmitter :: <ISA_LIT>MCCodeEmitter ( MCInstrInfo const & aMII , MCContext & aMCT ) : MCT ( aMCT ) , MCII ( aMII ) {


<s> return new <ISA_LIT>MCCodeEmitter ( MII , MST , MCT ) ;


<s> uint64_t Binary = getBinaryCodeForInstr ( HMB , Fixups , STI ) | getPacketBits ( HMB ) ;

assert ( HMB . getDesc ( ) . getSize ( ) == <NUM_LIT> && <STR_LIT> ) ;


<s> unsigned const ParseFieldOffset = <NUM_LIT> ; ParseField Field = HMI . isPacketEnd ( ) ? ParseField :: end : ParseField :: last0 ; return static_cast < uint32_t > ( Field ) << ParseFieldOffset ;


<s> MCSubtargetInfo const & <ISA_LIT>MCCodeEmitter :: getSubtargetInfo ( ) const { return MST ;


<s> <ISA_LIT>MCCodeEmitter :: <ISA_LIT>MCCodeEmitter ( MCInstrInfo const & aMII , MCSubtargetInfo const & aMST , MCContext & aMCT ) : MST ( aMST ) , MCT ( aMCT ) {


<s> void <ISA_LIT>MCCodeEmitter :: EncodeInstruction ( MCInst const & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , MCSubtargetInfo const & STI ) const { <ISA_LIT>MCInst const & HMB = static_cast < <ISA_LIT>MCInst const & > ( MI ) ; uint64_t Binary = getBinaryCodeForInstr ( HMB , Fixups , STI ) | getPacketBits ( HMB ) ; Binary |= getPacketBits ( HMB ) ; emitLittleEndian ( Binary , OS ) ; ++ MCNumEmitted ;


ParseField Field = HMI . isPacketEnd ( ) ? ParseField :: end : ParseField :: last0 ;


<s> ParseField Field = HMI . isPacketEnd ( ) ? ParseField :: end : ParseField :: last0 ; return static_cast < uint32_t > ( Field ) << ParseFieldOffset ;


<s> for ( auto & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( HMB ) ) { MCInst & HMI = const_cast < MCInst & > ( * I . getInst ( ) ) ; verifyInstructionPredicates ( HMI , Features ) ; EncodeSingleInstruction ( HMI , OS , Fixups , STI , parseBits ( Last , HMB , HMI ) ) ; State . Extended = <ISA_LIT>MCInstrInfo :: isImmext ( HMI ) ; State . Addend += HEXAGON_INSTR_SIZE ; ++ State . Index ;


<s> for ( auto & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( HMB ) ) { MCInst & HMI = const_cast < MCInst & > ( * I . getInst ( ) ) ; verifyInstructionPredicates ( HMI , Features ) ;

EncodeSingleInstruction ( HMI , OS , Fixups , STI , parseBits ( Last , HMB , HMI ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : switch ( kind ) { case llvm :: MCSymbolRefExpr :: VK_GOT : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_GOTOFF : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_<ISA_LIT>_GD_GOT : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_<ISA_LIT>_LD_GOT : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_<ISA_LIT>_IE : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_<ISA_LIT>_IE_GOT : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_TPREL : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_DTPREL : return <STR_LIT> ; default : return <STR_LIT> ; } case <STR_LIT> : case <STR_LIT> : switch ( kind ) { case llvm :: MCSymbolRefExpr :: VK_GOT : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_GOTOFF : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_<ISA_LIT>_GD_GOT : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_<ISA_LIT>_LD_GOT : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_<ISA_LIT>_IE : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_<ISA_LIT>_IE_GOT : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_TPREL : return <STR_LIT> ; case llvm :: MCSymbolRefExpr :: VK_DTPREL : return <STR_LIT> ; default : return <STR_LIT> ; } default : if ( MCID . mayStore ( ) || MCID . mayLoad ( ) ) { for ( const MCPhysReg * ImpUses = MCID . getImplicitUses ( ) ; ImpUses && * ImpUses ; ++ ImpUses ) { if ( * ImpUses != <STR_LIT> ) continue ; switch ( <ISA_LIT>MCInstrInfo :: getAccessSize ( MCII , MI ) ) { case <STR_LIT> :: ByteAccess : return fixup_<ISA_LIT>_GPREL16_0 ; case <STR_LIT> :: HalfWordAccess : return fixup_<ISA_LIT>_GPREL16_1 ; case <STR_LIT> :: WordAccess : return fixup_<ISA_LIT>_GPREL16_2 ; case <STR_LIT> :: DoubleWordAccess : return fixup_<ISA_LIT>_GPREL16_3 ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> Register1 = <ISA_LIT>MCInstrInfo :: hasNewValue ( MCII , Inst ) ? <ISA_LIT>MCInstrInfo :: getNewValueOperand ( MCII , Inst ) . getReg ( ) : static_cast < unsigned > ( <STR_LIT> ) ; Register2 = <ISA_LIT>MCInstrInfo :: hasNewValue2 ( MCII , Inst ) ? <ISA_LIT>MCInstrInfo :: getNewValueOperand2 ( MCII , Inst ) . getReg ( ) : static_cast < unsigned > ( <STR_LIT> ) ; if ( ! RegisterMatches ( Register , Register1 , Register2 ) ) continue ; if ( ! <ISA_LIT>MCInstrInfo :: isPredicated ( MCII , Inst ) ) break ; assert ( <ISA_LIT>MCInstrInfo :: isPredicated ( MCII , MI ) && <STR_LIT> ) ; if ( <ISA_LIT>MCInstrInfo :: isPredicatedTrue ( MCII , Inst ) == <ISA_LIT>MCInstrInfo :: isPredicatedTrue ( MCII , MI ) ) break ; } unsigned Offset = <ISA_LIT>MCInstrInfo :: isVector ( MCII , MI ) ? VOffset : SOffset ; Offset <<= <NUM_LIT> ; Offset |= <ISA_LIT>MCInstrInfo :: SubregisterBit ( Register , Register1 , Register2 ) ; return Offset ; } assert ( ! MO . isImm ( ) ) ; if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; if ( <ISA_LIT>MCInstrInfo :: isSubInstruction ( MI ) || llvm :: <ISA_LIT>MCInstrInfo :: getType ( MCII , MI ) == <STR_LIT> ) return <ISA_LIT>MCInstrInfo :: getDuplexRegisterNumbering ( Reg ) ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> :


<s> size_t Instruction = <NUM_LIT> ; size_t Last = <ISA_LIT>MCInstrInfo :: bundleSize ( HMB ) - <NUM_LIT> ; for ( auto & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( HMB ) ) { MCInst & HMI = const_cast < MCInst & > ( * I . getInst ( ) ) ; verifyInstructionPredicates ( HMI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; EncodeSingleInstruction ( HMI , OS , Fixups , STI , parseBits ( Instruction , Last , HMB , HMI ) , Instruction ) ; * Extended = <ISA_LIT>MCInstrInfo :: isImmext ( HMI ) ; * Addend += HEXAGON_INSTR_SIZE ;


<s> size_t Last = <ISA_LIT>MCInstrInfo :: bundleSize ( HMB ) - <NUM_LIT> ; for ( auto & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( HMB ) ) { MCInst & HMI = const_cast < MCInst & > ( * I . getInst ( ) ) ; verifyInstructionPredicates ( HMI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; EncodeSingleInstruction ( HMI , OS , Fixups , STI , parseBits ( Instruction , Last , HMB , HMI ) , Instruction ) ; * Extended = <ISA_LIT>MCInstrInfo :: isImmext ( HMI ) ; * Addend += HEXAGON_INSTR_SIZE ;


<s> assert ( <ISA_LIT>MCInstrInfo :: isBundle ( HMB ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; * Addend = <NUM_LIT> ; * Extended = false ; * CurrentBundle = & MI ; * CurrentIndex = <NUM_LIT> ; size_t Last = <ISA_LIT>MCInstrInfo :: bundleSize ( HMB ) - <NUM_LIT> ; for ( auto & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( HMB ) ) { MCInst & HMI = const_cast < MCInst & > ( * I . getInst ( ) ) ; verifyInstructionPredicates ( HMI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ;