<s> case 'L' : case 'H' : { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( ! MO . isReg ( ) ) return true ; Register RegNumber = MO . getReg ( ) ; if ( <STR_LIT> . contains ( RegNumber ) ) RegNumber = TRI -> getSubReg ( RegNumber , ExtraCode [ <NUM_LIT> ] == 'L' ? <STR_LIT> : <STR_LIT> ) ; OS << <ISA_LIT>InstPrinter :: getRegisterName ( RegNumber ) ; return false ; } case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) OS << <STR_LIT> ; return false ; } } printOperand ( MI , OpNo , OS ) ;


<s> switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : O << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; return ; case MachineOperand :: MO_MachineBasicBlock : MO . getMBB ( ) -> getSymbol ( ) -> print ( O , MAI ) ; return ;

case MachineOperand :: MO_ConstantPoolIndex :


<s> int64_t Value ; if ( Imm . getExpr ( ) -> evaluateAsAbsolute ( Value ) ) { StringRef sectionPrefix ; std :: string ImmString ; StringRef Name ; if ( AlignSize == <NUM_LIT> ) { Name = <STR_LIT> ; sectionPrefix = <STR_LIT> ; ImmString = utohexstr ( Value ) ; } else { Name = <STR_LIT> ; sectionPrefix = <STR_LIT> ; ImmString = utohexstr ( static_cast < uint32_t > ( Value ) ) ; } std :: string symbolName = Name . drop_back ( ImmString . size ( ) ) . str ( ) + ImmString ; std :: string sectionName = sectionPrefix . str ( ) + symbolName ; MCSectionELF * Section = OutStreamer . getContext ( ) . getELFSection ( sectionName , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; OutStreamer . SwitchSection ( Section ) ; Sym = AP . OutContext . getOrCreateSymbol ( Twine ( symbolName ) ) ; if ( Sym -> isUndefined ( ) ) { OutStreamer . emitLabel ( Sym ) ; OutStreamer . emitSymbolAttribute ( Sym , MCSA_Global ) ; OutStreamer . emitIntValue ( Value , AlignSize ) ; OutStreamer . emitCodeAlignment ( AlignSize , & STI ) ; } } else { assert ( Imm . isExpr ( ) && <STR_LIT> ) ;

const MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ;


<s> MCInst MCB ; MCB . setOpcode ( <STR_LIT> ) ; MCB . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; const MCInstrInfo & MCII = * Subtarget -> getInstrInfo ( ) ; if ( MI -> isBundle ( ) ) { assert ( Subtarget -> usePackets ( ) && <STR_LIT> ) ; const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI -> getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( ! MII -> isDebugValue ( ) && ! MII -> isImplicitDef ( ) ) <ISA_LIT>LowerToMC ( MCII , & * MII , MCB , * this ) ; } else <ISA_LIT>LowerToMC ( MCII , MI , MCB , * this ) ; bool Ok = <ISA_LIT>MCInstrInfo :: canonicalizePacket ( MCII , * Subtarget , OutStreamer -> getContext ( ) , MCB , nullptr ) ; assert ( Ok ) ; ( void ) Ok ;

if ( <ISA_LIT>MCInstrInfo :: bundleSize ( MCB ) == <NUM_LIT> ) return ;


<s> MCInst MCB ; MCB . setOpcode ( <STR_LIT> ) ; MCB . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; const MCInstrInfo & MCII = * Subtarget -> getInstrInfo ( ) ; if ( MI -> isBundle ( ) ) { assert ( Subtarget -> usePackets ( ) && <STR_LIT> ) ; const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI -> getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( ! MII -> isDebugValue ( ) && ! MII -> isImplicitDef ( ) ) <ISA_LIT>LowerToMC ( MCII , & * MII , MCB , * this ) ; } else <ISA_LIT>LowerToMC ( MCII , MI , MCB , * this ) ; bool Ok = <ISA_LIT>MCInstrInfo :: canonicalizePacket ( MCII , * Subtarget , OutStreamer -> getContext ( ) , MCB , nullptr ) ;


<s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst MCB ; MCB . setOpcode ( <STR_LIT> ) ; MCB . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; const MCInstrInfo & MCII = * Subtarget -> getInstrInfo ( ) ; if ( MI -> isBundle ( ) ) { assert ( Subtarget -> usePackets ( ) && <STR_LIT> ) ; const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI -> getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( ! MII -> isDebugInstr ( ) && ! MII -> isImplicitDef ( ) ) <ISA_LIT>LowerToMC ( MCII , & * MII , MCB , * this ) ;


<s> virtual const char * getPassName ( ) const {


<s> if ( SyntaxVariant == <NUM_LIT> ) return ( new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ) ; else return nullptr ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { if ( SyntaxVariant == <NUM_LIT> ) return ( new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ) ;


<s> if ( Imm . getExpr ( ) -> evaluateAsAbsolute ( Value ) ) { StringRef sectionPrefix ; std :: string ImmString ; StringRef Name ; if ( AlignSize == <NUM_LIT> ) { Name = <STR_LIT> ; sectionPrefix = <STR_LIT> ; ImmString = utohexstr ( Value ) ; } else { Name = <STR_LIT> ; sectionPrefix = <STR_LIT> ; ImmString = utohexstr ( static_cast < uint32_t > ( Value ) ) ; } std :: string symbolName = Name . drop_back ( ImmString . size ( ) ) . str ( ) + ImmString ; std :: string sectionName = sectionPrefix . str ( ) + symbolName ; MCSectionELF * Section = OutStreamer . getContext ( ) . getELFSection ( sectionName , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; OutStreamer . SwitchSection ( Section ) ; Sym = AP . OutContext . getOrCreateSymbol ( Twine ( symbolName ) ) ; if ( Sym -> isUndefined ( ) ) { OutStreamer . emitLabel ( Sym ) ; OutStreamer . emitSymbolAttribute ( Sym , MCSA_Global ) ; OutStreamer . emitIntValue ( Value , AlignSize ) ; OutStreamer . emitCodeAlignment ( AlignSize ) ; } } else {

assert ( Imm . isExpr ( ) && <STR_LIT> ) ;


<s> MachineBasicBlock :: const_instr_iterator MII = MI -> getIterator ( ) ; unsigned IgnoreCount = <NUM_LIT> ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) { if ( MII -> getOpcode ( ) == TargetOpcode :: DBG_VALUE || MII -> getOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ) ++ IgnoreCount ; else { <ISA_LIT>LowerToMC ( & * MII , MCB , * this ) ; } } }


<s> void printAbsAddrOperand ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O ) {


<s> const MachineOperand & MO1 = MI -> getOperand ( OpNo ) ; const MachineOperand & MO2 = MI -> getOperand ( OpNo + <NUM_LIT> ) ;

O << getRegisterName ( MO1 . getReg ( ) ) << <STR_LIT> << MO2 . getImm ( ) ;


<s> O << getRegisterName ( MO1 . getReg ( ) ) << <STR_LIT> << MO2 . getImm ( ) ;


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; const MachineOperand & Base = MI -> getOperand ( OpNo ) ; const MachineOperand & Offset = MI -> getOperand ( OpNo + <NUM_LIT> ) ; if ( Base . isReg ( ) ) printOperand ( MI , OpNo , O ) ; else assert ( <NUM_LIT> && <STR_LIT> ) ; if ( Offset . isImm ( ) ) {

if ( Offset . getImm ( ) ) O << <STR_LIT> << Offset . getImm ( ) ;


<s> return false ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + <NUM_LIT> == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) return true ; ++ OpNo ; break ; case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) OS << <STR_LIT> ; return false ; } }


<s> switch ( ExtraCode [ <NUM_LIT> ] ) { default : return true ; case 'c' : printOperand ( MI , OpNo , OS ) ; return false ; case 'L' :

if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + <NUM_LIT> == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) return true ;


<s> if ( MI -> getOperand ( OpNo ) . isImm ( ) ) { O << <STR_LIT> << MI -> getOperand ( OpNo ) . getImm ( ) * <NUM_LIT> ; } else {

printOp ( MI -> getOperand ( OpNo ) , O ) ;


<s> void printBranchOperand ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . isImm ( ) ) { O << <STR_LIT> << MI -> getOperand ( OpNo ) . getImm ( ) * <NUM_LIT> ; } else {


<s> void printCallOperand ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O ) {


<s> void print<ISA_LIT>ImmOperand ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O ) { int value = MI -> getOperand ( OpNo ) . getImm ( ) ; O << value ;


<s> const MachineOperand & MO2 = MI -> getOperand ( OpNo + <NUM_LIT> ) ;

O << getRegisterName ( MO1 . getReg ( ) ) << <STR_LIT> << ( int ) MO2 . getImm ( ) ;


<s> int value = MI -> getOperand ( OpNo ) . getImm ( ) ;


<s> void print<ISA_LIT>NegImmOperand ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O ) {

int value = MI -> getOperand ( OpNo ) . getImm ( ) ;


<s> return ; case MachineOperand :: MO_JumpTableIndex : O << * GetJTISymbol ( MO . getIndex ( ) ) ; return ; case MachineOperand :: MO_ConstantPoolIndex : O << * GetCPISymbol ( MO . getIndex ( ) ) ; return ; case MachineOperand :: MO_ExternalSymbol : O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ;


<s> if ( MO . isReg ( ) ) { printRegister ( MO , false , OS ) ;


<s> printRegister ( MO , false , OS ) ; } else if ( MO . isImm ( ) ) {


<s> void <ISA_LIT>AsmPrinter :: printPredicateOperand ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O ) { assert ( <NUM_LIT> && <STR_LIT> ) ;


<s> assert ( TargetRegisterInfo :: isPhysicalRegister ( RegNo ) && <STR_LIT> ) ; O << getRegisterName ( RegNo ) ;


<s> O << <STR_LIT> ; if ( MI -> getOperand ( OpNo ) . isImm ( ) ) { print<ISA_LIT>ImmOperand ( MI , OpNo , O ) ; } else { printOp ( MI -> getOperand ( OpNo ) , O ) ; }


<s> void printSymbolLo ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT> ; if ( MI -> getOperand ( OpNo ) . isImm ( ) ) { print<ISA_LIT>ImmOperand ( MI , OpNo , O ) ; } else { printOp ( MI -> getOperand ( OpNo ) , O ) ; }


<s> <ISA_LIT>LowerToMC ( MI , MCI , * this ) ;


<s> case MachineOperand :: MO_ConstantPoolIndex : O << * GetCPISymbol ( MO . getIndex ( ) ) ; return ; case MachineOperand :: MO_ExternalSymbol : O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; return ; case MachineOperand :: MO_GlobalAddress : O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ; printOffset ( MO . getOffset ( ) , O ) ;


<s> unsigned IgnoreCount = <NUM_LIT> ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) { if ( MII -> getOpcode ( ) == TargetOpcode :: DBG_VALUE || MII -> getOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ) ++ IgnoreCount ; else { <ISA_LIT>LowerToMC ( & * MII , MCB , * this ) ; } } } else { <ISA_LIT>LowerToMC ( MI , MCB , * this ) ;

<ISA_LIT>MCInstrInfo :: padEndloop ( OutStreamer -> getContext ( ) , MCB ) ;


<s> const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( ! MO . isReg ( ) ) return true ; unsigned RegNumber = MO . getReg ( ) ; if ( <STR_LIT> . contains ( RegNumber ) ) RegNumber = TRI -> getSubReg ( RegNumber , ExtraCode [ <NUM_LIT> ] == 'L' ? <STR_LIT> : <STR_LIT> ) ; OS << <ISA_LIT>InstPrinter :: getRegisterName ( RegNumber ) ; return false ; } case 'I' :

if ( MI -> getOperand ( OpNo ) . isImm ( ) ) OS << <STR_LIT> ;


<s> case 'L' : case 'H' : { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( ! MO . isReg ( ) ) return true ; unsigned RegNumber = MO . getReg ( ) ; if ( <STR_LIT> . contains ( RegNumber ) ) RegNumber = TRI -> getSubReg ( RegNumber , ExtraCode [ <NUM_LIT> ] == 'L' ? <STR_LIT> : <STR_LIT> ) ; OS << <ISA_LIT>InstPrinter :: getRegisterName ( RegNumber ) ; return false ; } case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) OS << <STR_LIT> ;


<s> const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI ; unsigned IgnoreCount = <NUM_LIT> ; for ( ++ MII ; MII != MBB -> end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) { if ( MII -> getOpcode ( ) == TargetOpcode :: DBG_VALUE || MII -> getOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ) ++ IgnoreCount ; else { <ISA_LIT>LowerToMC ( MII , MCB , * this ) ;


<s> <ISA_LIT>LowerToMC ( MI , MCB , * this ) ; <ISA_LIT>MCInstrInfo :: padEndloop ( MCB ) ; } <ISA_LIT>MCInstrInfo :: tryCompound ( * Subtarget -> getInstrInfo ( ) , OutStreamer -> getContext ( ) , MCB ) ; SmallVector < DuplexCandidate , <NUM_LIT> > possibleDuplexes ; possibleDuplexes = <ISA_LIT>MCInstrInfo :: getDuplexPossibilties ( * Subtarget -> getInstrInfo ( ) , MCB ) ;

<ISA_LIT>MCShuffle ( * Subtarget -> getInstrInfo ( ) , * Subtarget , OutStreamer -> getContext ( ) , MCB , possibleDuplexes ) ;


<s> MCInst MCB ; MCB . setOpcode ( <STR_LIT> ) ; MCB . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI ; unsigned IgnoreCount = <NUM_LIT> ; for ( ++ MII ; MII != MBB -> end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) { if ( MII -> getOpcode ( ) == TargetOpcode :: DBG_VALUE || MII -> getOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ) ++ IgnoreCount ; else { <ISA_LIT>LowerToMC ( MII , MCB , * this ) ; } } } else { <ISA_LIT>LowerToMC ( MI , MCB , * this ) ; <ISA_LIT>MCInstrInfo :: padEndloop ( MCB ) ;


<s> const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI -> getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( ! MII -> isDebugValue ( ) && ! MII -> isImplicitDef ( ) ) <ISA_LIT>LowerToMC ( MCII , & * MII , MCB , * this ) ; } else { <ISA_LIT>LowerToMC ( MCII , MI , MCB , * this ) ; } const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const auto & HII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; if ( MI -> isBundle ( ) && HII . getBundleNoShuf ( * MI ) ) <ISA_LIT>MCInstrInfo :: setMemReorderDisabled ( MCB ) ; MCContext & Ctx = OutStreamer -> getContext ( ) ; bool Ok = <ISA_LIT>MCInstrInfo :: canonicalizePacket ( MCII , * Subtarget , Ctx , MCB , nullptr ) ;


<s> unsigned RegNumber = MO . getReg ( ) ; if ( <STR_LIT> . contains ( RegNumber ) ) RegNumber = TRI -> getSubReg ( RegNumber , ExtraCode [ <NUM_LIT> ] == 'L' ? <STR_LIT> : <STR_LIT> ) ; OS << <ISA_LIT>InstPrinter :: getRegisterName ( RegNumber ) ; return false ; } case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) OS << <STR_LIT> ; return false ; } }


<s> MCInst MCB ; MCB . setOpcode ( <STR_LIT> ) ; MCB . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; const MCInstrInfo & MCII = * Subtarget -> getInstrInfo ( ) ; if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI -> getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( ! MII -> isDebugValue ( ) && ! MII -> isImplicitDef ( ) ) <ISA_LIT>LowerToMC ( MCII , & * MII , MCB , * this ) ; } else <ISA_LIT>LowerToMC ( MCII , MI , MCB , * this ) ; bool Ok = <ISA_LIT>MCInstrInfo :: canonicalizePacket ( MCII , * Subtarget , OutStreamer -> getContext ( ) , MCB , nullptr ) ;


<s> else O << <STR_LIT> << <STR_LIT> << addend << '\n' ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { O << <STR_LIT> ; print<ISA_LIT>MEMriOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; int addend = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( addend < <NUM_LIT> ) O << <STR_LIT> << <STR_LIT> << - addend << '\n' ; else O << <STR_LIT> << <STR_LIT> << addend << '\n' ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { O << <STR_LIT> ; print<ISA_LIT>MEMriOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; int addend = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( addend < <NUM_LIT> ) O << <STR_LIT> << <STR_LIT> << - addend << '\n' ; else O << <STR_LIT> << <STR_LIT> << addend << '\n' ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { O << <STR_LIT> ; print<ISA_LIT>MEMriOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; int addend = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( addend < <NUM_LIT> ) O << <STR_LIT> << <STR_LIT> << - addend << '\n' ; else O << <STR_LIT> << <STR_LIT> << addend << '\n' ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { O << <STR_LIT> ; print<ISA_LIT>MEMriOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; int addend = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( addend < <NUM_LIT> ) O << <STR_LIT> << <STR_LIT> << - addend << '\n' ; else O << <STR_LIT> << <STR_LIT> << addend << '\n' ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { O << <STR_LIT> ; print<ISA_LIT>MEMriOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; int addend = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( addend < <NUM_LIT> ) O << <STR_LIT> << <STR_LIT> << - addend << '\n' ; else O << <STR_LIT> << <STR_LIT> << addend << '\n' ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { O << <STR_LIT> ; printRegister ( MI -> getOperand ( <NUM_LIT> ) , false , O ) ; O << <STR_LIT> ;


<s> void print<ISA_LIT>NOneImmOperand ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O ) const { O << - <NUM_LIT> ;


<s> void print<ISA_LIT>NOneImmOperand ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O ) const {


<s> for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( ! MII -> isDebugInstr ( ) && ! MII -> isImplicitDef ( ) ) <ISA_LIT>LowerToMC ( MCII , & * MII , MCB , * this ) ; } else { <ISA_LIT>LowerToMC ( MCII , MI , MCB , * this ) ; } const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const auto & HII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; if ( MI -> isBundle ( ) && HII . getBundleNoShuf ( * MI ) ) <ISA_LIT>MCInstrInfo :: setMemReorderDisabled ( MCB ) ; MCContext & Ctx = OutStreamer -> getContext ( ) ; bool Ok = <ISA_LIT>MCInstrInfo :: canonicalizePacket ( MCII , * Subtarget , Ctx , MCB , nullptr ) ;


<s> const char * getPassName ( ) const override { return <STR_LIT> ;


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> bool <ISA_LIT>AsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { if ( MBB -> hasAddressTaken ( ) ) return false ; return AsmPrinter :: isBlockOnlyReachableByFallthrough ( MBB ) ;


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; const MachineOperand & Base = MI -> getOperand ( OpNo ) ; const MachineOperand & Offset = MI -> getOperand ( OpNo + <NUM_LIT> ) ; if ( Base . isReg ( ) ) printOperand ( MI , OpNo , O ) ; else llvm_unreachable ( <STR_LIT> ) ; if ( Offset . isImm ( ) ) { if ( Offset . getImm ( ) ) O << <STR_LIT> << Offset . getImm ( ) ; } else { llvm_unreachable ( <STR_LIT> ) ; }


<s> const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( ! MO . isReg ( ) ) return true ; unsigned RegNumber = MO . getReg ( ) ; if ( <STR_LIT> . contains ( RegNumber ) ) RegNumber = TRI -> getSubReg ( RegNumber , ExtraCode [ <NUM_LIT> ] == 'L' ? <STR_LIT> : <STR_LIT> ) ; OS << <ISA_LIT>InstPrinter :: getRegisterName ( RegNumber ) ; return false ; } case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) OS << <STR_LIT> ; return false ; }


<s> const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( ! MO . isReg ( ) ) return true ; unsigned RegNumber = MO . getReg ( ) ; if ( <STR_LIT> . contains ( RegNumber ) ) RegNumber = TRI -> getSubReg ( RegNumber , ExtraCode [ <NUM_LIT> ] == 'L' ? <STR_LIT> : <STR_LIT> ) ; OS << <ISA_LIT>InstPrinter :: getRegisterName ( RegNumber ) ; return false ; } case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) OS << <STR_LIT> ;


<s> const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : O << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return ; case MachineOperand :: MO_Immediate :


<s> int32_t V = cast < MCConstantExpr > ( HE -> getExpr ( ) ) -> getValue ( ) ; auto * NewCE = MCConstantExpr :: create ( V / int32_t ( VectorSize ) , Ctx ) ; auto * NewHE = <ISA_LIT>MCExpr :: create ( NewCE , Ctx ) ; T . addOperand ( MCOperand :: createExpr ( NewHE ) ) ; }


<s> if ( Imm . getExpr ( ) -> evaluateAsAbsolute ( Value ) ) { StringRef sectionPrefix ; std :: string ImmString ; StringRef Name ; if ( AlignSize == <NUM_LIT> ) { Name = <STR_LIT> ; sectionPrefix = <STR_LIT> ; ImmString = utohexstr ( Value ) ; } else { Name = <STR_LIT> ; sectionPrefix = <STR_LIT> ; ImmString = utohexstr ( static_cast < uint32_t > ( Value ) ) ; } std :: string symbolName = Name . drop_back ( ImmString . size ( ) ) . str ( ) + ImmString ; std :: string sectionName = sectionPrefix . str ( ) + symbolName ; MCSectionELF * Section = OutStreamer . getContext ( ) . getELFSection ( sectionName , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; OutStreamer . SwitchSection ( Section ) ; Sym = AP . OutContext . getOrCreateSymbol ( Twine ( symbolName ) ) ; if ( Sym -> isUndefined ( ) ) { OutStreamer . EmitLabel ( Sym ) ; OutStreamer . EmitSymbolAttribute ( Sym , MCSA_Global ) ; OutStreamer . EmitIntValue ( Value , AlignSize ) ; OutStreamer . EmitCodeAlignment ( AlignSize ) ; }


<s> BitSimplification ( BitTracker & bt , const MachineDominatorTree & mdt , const <ISA_LIT>InstrInfo & hii , const <ISA_LIT>RegisterInfo & hri , MachineRegisterInfo & mri , MachineFunction & mf ) : Transformation ( true ) , MDT ( mdt ) , HII ( hii ) , HRI ( hri ) , MRI ( mri ) , MF ( mf ) , BT ( bt ) {


<s> unsigned Opc = MI . getOpcode ( ) ; BitVector T ( Bits . size ( ) ) ; bool GotBits = HBS :: getUsedBits ( Opc , OpN , T , Begin , HII ) ; unsigned LB , LE ; if ( isLossyShiftLeft ( MI , OpN , LB , LE ) || isLossyShiftRight ( MI , OpN , LB , LE ) ) { assert ( MI . getOperand ( OpN ) . isReg ( ) ) ; BitTracker :: RegisterRef RR = MI . getOperand ( OpN ) ; const TargetRegisterClass * RC = HBS :: getFinalVRegClass ( RR , MRI ) ; uint16_t Width = HRI . getRegSizeInBits ( * RC ) ;

if ( ! GotBits ) T . set ( Begin , Begin + Width ) ;


<s> unsigned LB , LE ; if ( isLossyShiftLeft ( MI , OpN , LB , LE ) || isLossyShiftRight ( MI , OpN , LB , LE ) ) { assert ( MI . getOperand ( OpN ) . isReg ( ) ) ; BitTracker :: RegisterRef RR = MI . getOperand ( OpN ) ; const TargetRegisterClass * RC = HBS :: getFinalVRegClass ( RR , MRI ) ; uint16_t Width = HRI . getRegSizeInBits ( * RC ) ; if ( ! GotBits ) T . set ( Begin , Begin + Width ) ; assert ( LB <= LE && LB < Width && LE <= Width ) ; T . reset ( Begin + LB , Begin + LE ) ; GotBits = true ; } if ( GotBits ) Bits |= T ; return GotBits ;


<s> CopyGeneration ( BitTracker & bt , const <ISA_LIT>InstrInfo & hii , const <ISA_LIT>RegisterInfo & hri , MachineRegisterInfo & mri ) : Transformation ( true ) , HII ( hii ) , HRI ( hri ) , MRI ( mri ) , BT ( bt ) {


<s> CopyPropagation ( const <ISA_LIT>RegisterInfo & hri , MachineRegisterInfo & mri ) : Transformation ( false ) , HRI ( hri ) , MRI ( mri ) {


<s> bool CopyGeneration :: findMatch ( const BitTracker :: RegisterRef & Inp , BitTracker :: RegisterRef & Out , const RegisterSet & AVs ) { if ( ! BT . has ( Inp . Reg ) ) return false ; const BitTracker :: RegisterCell & InpRC = BT . lookup ( Inp . Reg ) ; auto * FRC = HBS :: getFinalVRegClass ( Inp , MRI ) ; unsigned B , W ; if ( ! HBS :: getSubregMask ( Inp , B , W , MRI ) ) return false ; for ( unsigned R = AVs . find_first ( ) ; R ; R = AVs . find_next ( R ) ) { if ( ! BT . has ( R ) || Forbidden [ R ] ) continue ; const BitTracker :: RegisterCell & RC = BT . lookup ( R ) ; unsigned RW = RC . width ( ) ; if ( W == RW ) { if ( FRC != MRI . getRegClass ( R ) ) continue ; if ( ! HBS :: isTransparentCopy ( R , Inp , MRI ) ) continue ; if ( ! HBS :: isEqual ( InpRC , B , RC , <NUM_LIT> , W ) ) continue ;


<s> if ( V . Type != BitTracker :: BitValue :: Ref ) break ; if ( V . RefI . Reg != SrcR || V . RefI . Pos != P + I ) break ; } if ( I != Z ) continue ; if ( MaxBitSplit . getNumOccurrences ( ) ) CountBitSplit ++ ; MachineInstr * DefS = MRI . getVRegDef ( S ) ; assert ( DefS != nullptr ) ; DebugLoc DL = DefS -> getDebugLoc ( ) ; MachineBasicBlock & B = * DefS -> getParent ( ) ; auto At = DefS -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( DefS ) ; if ( MRI . getRegClass ( SrcR ) -> getID ( ) == <STR_LIT> ) SrcSR = ( std :: min ( Pos , P ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( ! validateReg ( { SrcR , SrcSR } , <STR_LIT> , <NUM_LIT> ) ) continue ; unsigned ImmOp = Pos <= P ? W - Z : Z ; unsigned NewR = <NUM_LIT> ; for ( MachineInstr * In : NewMIs ) { if ( In -> getOpcode ( ) != <STR_LIT> ) continue ; MachineOperand & Op1 = In -> getOperand ( <NUM_LIT> ) ; if ( Op1 . getReg ( ) != SrcR || Op1 . getSubReg ( ) != SrcSR ) continue ; if ( In -> getOperand ( <NUM_LIT> ) . getImm ( ) != ImmOp ) continue ; MachineOperand & Op0 = In -> getOperand ( <NUM_LIT> ) ; MachineInstr * DefI = MRI . getVRegDef ( Op0 . getReg ( ) ) ; assert ( DefI != nullptr ) ; if ( ! MDT . dominates ( DefI , & * At ) ) continue ; assert ( Op0 . getSubReg ( ) == <NUM_LIT> ) ; NewR = Op0 . getReg ( ) ; break ; } if ( ! NewR ) { NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto NewBS = BuildMI ( B , At , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( SrcR , <NUM_LIT> , SrcSR ) . addImm ( ImmOp ) ; NewMIs . push_back ( NewBS ) ; }


<s> unsigned Opc = MI -> getOpcode ( ) ; unsigned COpc = getCombineOpcode ( H . Low , L . Low ) ; if ( COpc == Opc ) return false ; if ( ! validateReg ( H , COpc , <NUM_LIT> ) || ! validateReg ( L , COpc , <NUM_LIT> ) ) return false ; MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto At = MI -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( MI ) ; BuildMI ( B , At , DL , HII . get ( COpc ) , NewR ) . addReg ( H . Reg , <NUM_LIT> , H . Sub ) . addReg ( L . Reg , <NUM_LIT> , L . Sub ) ; HBS :: replaceSubWithSub ( RD . Reg , RD . Sub , NewR , <NUM_LIT> , MRI ) ; BT . put ( BitTracker :: RegisterRef ( NewR ) , RC ) ;


<s> RegHalf L , H ; if ( ! matchHalf ( RD . Reg , RC , <NUM_LIT> , L ) || ! matchHalf ( RD . Reg , RC , <NUM_LIT> , H ) ) return false ; if ( L . Reg == H . Reg && L . Sub == H . Sub && ! H . Low && L . Low ) return false ; unsigned Opc = MI -> getOpcode ( ) ; unsigned COpc = getCombineOpcode ( H . Low , L . Low ) ; if ( COpc == Opc ) return false ; if ( ! validateReg ( H , COpc , <NUM_LIT> ) || ! validateReg ( L , COpc , <NUM_LIT> ) ) return false ;

MachineBasicBlock & B = * MI -> getParent ( ) ;


<s> RegHalf L ; if ( ! matchHalf ( RD . Reg , RC , <NUM_LIT> , L ) || ! HBS :: isZero ( RC , <NUM_LIT> , <NUM_LIT> ) ) return false ; unsigned Opc = MI -> getOpcode ( ) ; MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned NewR = <NUM_LIT> ; auto At = MI -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( MI ) ; if ( L . Low && Opc != <STR_LIT> ) { if ( validateReg ( L , <STR_LIT> , <NUM_LIT> ) ) { NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( B , At , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( L . Reg , <NUM_LIT> , L . Sub ) ; } } else if ( ! L . Low && Opc != <STR_LIT> ) { if ( validateReg ( L , <STR_LIT> , <NUM_LIT> ) ) { NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( B , MI , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( L . Reg , <NUM_LIT> , L . Sub ) . addImm ( <NUM_LIT> ) ; } } if ( NewR == <NUM_LIT> ) return false ;

HBS :: replaceSubWithSub ( RD . Reg , RD . Sub , NewR , <NUM_LIT> , MRI ) ;


<s> unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } if ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { int32_t Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isInt < <NUM_LIT> > ( Imm ) ) return false ; } if ( MI -> hasUnmodeledSideEffects ( ) || MI -> isInlineAsm ( ) ) return false ; unsigned W = RC . width ( ) ; while ( W > <NUM_LIT> && RC [ W - <NUM_LIT> ] . is ( <NUM_LIT> ) ) W -- ; if ( W == <NUM_LIT> || W == RC . width ( ) ) return false ; unsigned NewOpc = ( W == <NUM_LIT> ) ? <STR_LIT> : ( W == <NUM_LIT> ) ? <STR_LIT> : ( W < <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; for ( auto & Op : MI -> uses ( ) ) { if ( ! Op . isReg ( ) ) continue ; BitTracker :: RegisterRef RS = Op ; if ( ! BT . has ( RS . Reg ) ) continue ; const BitTracker :: RegisterCell & SC = BT . lookup ( RS . Reg ) ; unsigned BN , BW ; if ( ! HBS :: getSubregMask ( RS , BN , BW , MRI ) ) continue ; if ( BW < W || ! HBS :: isEqual ( RC , <NUM_LIT> , SC , BN , W ) ) continue ; if ( ! validateReg ( RS , NewOpc , <NUM_LIT> ) ) continue ;

unsigned NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ;


<s> bool BitSimplification :: genExtractLow ( MachineInstr * MI , BitTracker :: RegisterRef RD , const BitTracker :: RegisterCell & RC ) { unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } if ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { int32_t Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isInt < <NUM_LIT> > ( Imm ) ) return false ; } if ( MI -> hasUnmodeledSideEffects ( ) || MI -> isInlineAsm ( ) ) return false ; unsigned W = RC . width ( ) ; while ( W > <NUM_LIT> && RC [ W - <NUM_LIT> ] . is ( <NUM_LIT> ) ) W -- ; if ( W == <NUM_LIT> || W == RC . width ( ) ) return false ; unsigned NewOpc = ( W == <NUM_LIT> ) ? <STR_LIT> : ( W == <NUM_LIT> ) ? <STR_LIT> : ( W < <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; for ( auto & Op : MI -> uses ( ) ) { if ( ! Op . isReg ( ) ) continue ; BitTracker :: RegisterRef RS = Op ; if ( ! BT . has ( RS . Reg ) ) continue ; const BitTracker :: RegisterCell & SC = BT . lookup ( RS . Reg ) ; unsigned BN , BW ; if ( ! HBS :: getSubregMask ( RS , BN , BW , MRI ) ) continue ; if ( BW < W || ! HBS :: isEqual ( RC , <NUM_LIT> , SC , BN , W ) ) continue ; if ( ! validateReg ( RS , NewOpc , <NUM_LIT> ) ) continue ; unsigned NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto At = MI -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( MI ) ; auto MIB = BuildMI ( B , At , DL , HII . get ( NewOpc ) , NewR ) . addReg ( RS . Reg , <NUM_LIT> , RS . Sub ) ; if ( NewOpc == <STR_LIT> ) MIB . addImm ( ( <NUM_LIT> << W ) - <NUM_LIT> ) ; else if ( NewOpc == <STR_LIT> ) MIB . addImm ( W ) . addImm ( <NUM_LIT> ) ; HBS :: replaceSubWithSub ( RD . Reg , RD . Sub , NewR , <NUM_LIT> , MRI ) ; BT . put ( BitTracker :: RegisterRef ( NewR ) , RC ) ;


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; auto At = MI -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( MI ) ;

BuildMI ( B , At , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( Rs . Reg , <NUM_LIT> , Rs . Sub ) . addReg ( Rt . Reg , <NUM_LIT> , Rt . Sub ) ;


<s> break ; default : return false ; } if ( ! MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) return false ; MachineOperand & OffOp = MI -> getOperand ( <NUM_LIT> ) ; if ( ! OffOp . isImm ( ) ) return false ; int64_t Off = OffOp . getImm ( ) ; if ( ! isUIntN ( <NUM_LIT> + Align , Off ) || ( Off & ( ( <NUM_LIT> << Align ) - <NUM_LIT> ) ) ) return false ; BitTracker :: RegisterRef RS = MI -> getOperand ( <NUM_LIT> ) ; if ( ! BT . has ( RS . Reg ) ) return false ; const BitTracker :: RegisterCell & RC = BT . lookup ( RS . Reg ) ; uint64_t U ; if ( ! HBS :: getConst ( RC , <NUM_LIT> , RC . width ( ) , U ) ) return false ; int V ; switch ( Opc ) { case <STR_LIT> : V = int8_t ( U ) ; break ; case <STR_LIT> : V = int16_t ( U ) ; break ; case <STR_LIT> : V = int32_t ( U ) ; break ; } if ( ! isInt < <NUM_LIT> > ( V ) ) return false ; MI -> RemoveOperand ( <NUM_LIT> ) ; switch ( Opc ) {


<s> AU . addPreserved < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> const TargetRegisterClass * <ISA_LIT>BitSimplify :: getFinalVRegClass ( const BitTracker :: RegisterRef & RR , MachineRegisterInfo & MRI ) { if ( ! TargetRegisterInfo :: isVirtualRegister ( RR . Reg ) ) return nullptr ; auto * RC = MRI . getRegClass ( RR . Reg ) ; if ( RR . Sub == <NUM_LIT> ) return RC ; auto & HRI = static_cast < const <ISA_LIT>RegisterInfo & > ( * MRI . getTargetRegisterInfo ( ) ) ; auto VerifySR = [ & HRI ] ( const TargetRegisterClass * RC , unsigned Sub ) -> void { ( void ) HRI ; assert ( Sub == HRI . get<ISA_LIT>SubRegIndex ( RC , <STR_LIT> ) || Sub == HRI . get<ISA_LIT>SubRegIndex ( RC , <STR_LIT> ) ) ;


<s> StringRef getPassName ( ) const override {


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> Begin = <NUM_LIT> ; Width = MRI . getTargetRegisterInfo ( ) -> getRegSizeInBits ( * RC ) ; return true ; } Begin = <NUM_LIT> ; switch ( RC -> getID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = MRI . getTargetRegisterInfo ( ) -> getRegSizeInBits ( * RC ) / <NUM_LIT> ; if ( RR . Sub == <STR_LIT> || RR . Sub == <STR_LIT> ) Begin = Width ; break ; default :


<s> bool <ISA_LIT>BitSimplify :: hasTiedUse ( unsigned Reg , MachineRegisterInfo & MRI , unsigned NewSub ) { if ( ! PreserveTiedOps ) return false ;

return llvm :: any_of ( MRI . use_operands ( Reg ) , [ NewSub ] ( const MachineOperand & Op ) -> bool {


<s> <ISA_LIT>BitSimplify ( ) : MachineFunctionPass ( ID ) , MDT ( nullptr ) {

initialize<ISA_LIT>BitSimplifyPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> <ISA_LIT>BitSimplify ( ) : MachineFunctionPass ( ID ) , MDT ( nullptr ) { initialize<ISA_LIT>BitSimplifyPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> <ISA_LIT>LoopRescheduling ( ) : MachineFunctionPass ( ID ) , HII ( nullptr ) , HRI ( nullptr ) , MRI ( nullptr ) , BTP ( nullptr ) {

initialize<ISA_LIT>LoopReschedulingPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return NoConv ; default :


<s> unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> :


<s> if ( Pos + <NUM_LIT> > SC . width ( ) ) return false ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { const BitTracker :: BitValue & RV = RC [ i + B ] ; if ( RV . Type == BitTracker :: BitValue :: Ref ) { if ( RV . RefI . Reg != Reg ) return false ; if ( RV . RefI . Pos != i + Pos ) return false ; continue ; } if ( RC [ i + B ] != SC [ i + Pos ] ) return false ; } unsigned Sub = <NUM_LIT> ; switch ( Pos ) { case <NUM_LIT> : Sub = <STR_LIT> ; Low = true ; break ; case <NUM_LIT> : Sub = <STR_LIT> ; Low = false ; break ; case <NUM_LIT> : Sub = <STR_LIT> ; Low = true ; break ; case <NUM_LIT> : Sub = <STR_LIT> ; Low = false ; break ; default : return false ; } RH . Reg = Reg ; RH . Sub = Sub ; RH . Low = Low ;

if ( ! HBS :: getFinalVRegClass ( RH , MRI ) ) RH . Sub = <NUM_LIT> ;


<s> if ( P < I - B ) return false ; unsigned Pos = P - ( I - B ) ; if ( Reg == <NUM_LIT> || Reg == SelfR ) return false ; if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) return false ; if ( ! BT . has ( Reg ) ) return false ; const BitTracker :: RegisterCell & SC = BT . lookup ( Reg ) ; if ( Pos + <NUM_LIT> > SC . width ( ) ) return false ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { const BitTracker :: BitValue & RV = RC [ i + B ] ; if ( RV . Type == BitTracker :: BitValue :: Ref ) { if ( RV . RefI . Reg != Reg ) return false ; if ( RV . RefI . Pos != i + Pos ) return false ; continue ; } if ( RC [ i + B ] != SC [ i + Pos ] ) return false ; } unsigned Sub = <NUM_LIT> ; switch ( Pos ) { case <NUM_LIT> : Sub = <STR_LIT> ; Low = true ; break ; case <NUM_LIT> : Sub = <STR_LIT> ; Low = false ; break ; case <NUM_LIT> : Sub = <STR_LIT> ; Low = true ;


<s> RegMap . insert ( std :: make_pair ( G . Inp . Reg , PhiR ) ) ; for ( unsigned i = G . Ins . size ( ) ; i > <NUM_LIT> ; -- i ) { const MachineInstr * SI = G . Ins [ i - <NUM_LIT> ] ; unsigned DR = getDefReg ( SI ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( DR ) ; unsigned NewDR = MRI -> createVirtualRegister ( RC ) ; DebugLoc DL = SI -> getDebugLoc ( ) ; auto MIB = BuildMI ( LB , At , DL , HII -> get ( SI -> getOpcode ( ) ) , NewDR ) ; for ( unsigned j = <NUM_LIT> , m = SI -> getNumOperands ( ) ; j < m ; ++ j ) { const MachineOperand & Op = SI -> getOperand ( j ) ; if ( ! Op . isReg ( ) ) { MIB . add ( Op ) ; continue ; } if ( ! Op . isUse ( ) ) continue ; unsigned UseR = RegMap [ Op . getReg ( ) ] ;

MIB . addReg ( UseR , <NUM_LIT> , Op . getSubReg ( ) ) ;


<s> auto & HRI = static_cast < const <ISA_LIT>RegisterInfo & > ( * MRI . getTargetRegisterInfo ( ) ) ; unsigned SubLo = HRI . get<ISA_LIT>SubRegIndex ( DstRC , <STR_LIT> ) ; unsigned SubHi = HRI . get<ISA_LIT>SubRegIndex ( DstRC , <STR_LIT> ) ; assert ( ( Sub1 == SubLo && Sub2 == SubHi ) || ( Sub1 == SubHi && Sub2 == SubLo ) ) ; if ( Sub1 == SubLo && Sub2 == SubHi ) { SL = I . getOperand ( <NUM_LIT> ) ; SH = I . getOperand ( <NUM_LIT> ) ; return true ; } if ( Sub1 == SubHi && Sub2 == SubLo ) { SH = I . getOperand ( <NUM_LIT> ) ; SL = I . getOperand ( <NUM_LIT> ) ; return true ;


<s> auto & HRI = static_cast < const <ISA_LIT>RegisterInfo & > ( * MRI . getTargetRegisterInfo ( ) ) ; unsigned SubLo = HRI . get<ISA_LIT>SubRegIndex ( DstRC , <STR_LIT> ) ; unsigned SubHi = HRI . get<ISA_LIT>SubRegIndex ( DstRC , <STR_LIT> ) ; assert ( ( Sub1 == SubLo && Sub2 == SubHi ) || ( Sub1 == SubHi && Sub2 == SubLo ) ) ;


<s> case TargetOpcode :: COPY : case <STR_LIT> : case <STR_LIT> : { BitTracker :: RegisterRef RS = MI . getOperand ( <NUM_LIT> ) ; if ( ! HBS :: isTransparentCopy ( RD , RS , MRI ) ) break ; if ( RS . Sub != <NUM_LIT> ) Changed = HBS :: replaceRegWithSub ( RD . Reg , RS . Reg , RS . Sub , MRI ) ; else Changed = HBS :: replaceReg ( RD . Reg , RS . Reg , MRI ) ; break ; } case TargetOpcode :: REG_SEQUENCE : { BitTracker :: RegisterRef SL , SH ; if ( HBS :: parseRegSequence ( MI , SL , SH , MRI ) ) { const TargetRegisterClass * RC = MRI . getRegClass ( RD . Reg ) ; unsigned SubLo = HRI . get<ISA_LIT>SubRegIndex ( RC , <STR_LIT> ) ; unsigned SubHi = HRI . get<ISA_LIT>SubRegIndex ( RC , <STR_LIT> ) ; Changed = HBS :: replaceSubWithSub ( RD . Reg , SubLo , SL . Reg , SL . Sub , MRI ) ; Changed |= HBS :: replaceSubWithSub ( RD . Reg , SubHi , SH . Reg , SH . Sub , MRI ) ; } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const TargetRegisterClass * RC = MRI . getRegClass ( RD . Reg ) ; unsigned SubLo = HRI . get<ISA_LIT>SubRegIndex ( RC , <STR_LIT> ) ; unsigned SubHi = HRI . get<ISA_LIT>SubRegIndex ( RC , <STR_LIT> ) ; BitTracker :: RegisterRef RH = MI . getOperand ( <NUM_LIT> ) , RL = MI . getOperand ( <NUM_LIT> ) ; Changed = HBS :: replaceSubWithSub ( RD . Reg , SubLo , RL . Reg , RL . Sub , MRI ) ; Changed |= HBS :: replaceSubWithSub ( RD . Reg , SubHi , RH . Reg , RH . Sub , MRI ) ; break ; } case <STR_LIT> : case <STR_LIT> : { unsigned SrcX = ( Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ;

unsigned Sub = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ;


<s> RedundantInstrElimination ( BitTracker & bt , const <ISA_LIT>InstrInfo & hii , const <ISA_LIT>RegisterInfo & hri , MachineRegisterInfo & mri ) : Transformation ( true ) , HII ( hii ) , HRI ( hri ) , MRI ( mri ) , BT ( bt ) {


<s> if ( hasTiedUse ( OldR , MRI , NewSR ) ) return false ; auto Begin = MRI . use_begin ( OldR ) , End = MRI . use_end ( ) ; decltype ( End ) NextI ;

for ( auto I = Begin ; I != End ; I = NextI ) {


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( OldR ) || ! TargetRegisterInfo :: isVirtualRegister ( NewR ) ) return false ; if ( OldSR != NewSR && hasTiedUse ( OldR , MRI , NewSR ) ) return false ; auto Begin = MRI . use_begin ( OldR ) , End = MRI . use_end ( ) ; decltype ( End ) NextI ;


<s> if ( OldSR != NewSR && hasTiedUse ( OldR , MRI , NewSR ) ) return false ; auto Begin = MRI . use_begin ( OldR ) , End = MRI . use_end ( ) ; decltype ( End ) NextI ; for ( auto I = Begin ; I != End ; I = NextI ) { NextI = std :: next ( I ) ; if ( I -> getSubReg ( ) != OldSR ) continue ; I -> setReg ( NewR ) ; I -> setSubReg ( NewSR ) ; } return Begin != End ;


<s> for ( auto I = B -> rbegin ( ) , E = B -> rend ( ) ; I != E ; ++ I ) Instrs . push_back ( & * I ) ; for ( auto MI : Instrs ) { unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == TargetOpcode :: LIFETIME_START || Opc == TargetOpcode :: LIFETIME_END ) continue ; bool Store = false ; if ( MI -> isInlineAsm ( ) ) continue ; if ( ! MI -> isPHI ( ) && ! MI -> isSafeToMove ( nullptr , Store ) ) continue ; bool AllDead = true ; SmallVector < unsigned , <NUM_LIT> > Regs ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) ) continue ; unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) || ! isDead ( R ) ) { AllDead = false ; break ; } Regs . push_back ( R ) ; }


<s> SmallVector < unsigned , <NUM_LIT> > Regs ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) ) continue ; unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) || ! isDead ( R ) ) { AllDead = false ; break ; } Regs . push_back ( R ) ; } if ( ! AllDead ) continue ; B -> erase ( MI ) ; for ( unsigned i = <NUM_LIT> , n = Regs . size ( ) ; i != n ; ++ i ) MRI . markUsesInDebugValueAsUndef ( Regs [ i ] ) ; Changed = true ; }


<s> for ( unsigned R = AVs . find_first ( ) ; R != <NUM_LIT> ; R = AVs . find_next ( R ) ) { if ( ! BT . has ( R ) ) continue ; const BitTracker :: RegisterCell & SC = BT . lookup ( R ) ; unsigned SW = SC . width ( ) ; if ( SW < RW || ( SW % RW ) != <NUM_LIT> ) continue ; unsigned Off = <NUM_LIT> ; while ( Off <= SW - Len ) { unsigned OE = ( Off + Len ) / RW ; if ( OE != Off / RW ) { Off = OE * RW ; continue ; } if ( HBS :: isEqual ( RC , <NUM_LIT> , SC , Off , Len ) ) break ; ++ Off ; } if ( Off > SW - Len ) continue ; unsigned ExtOpc = <NUM_LIT> ; if ( Off == <NUM_LIT> ) { if ( Len == <NUM_LIT> ) ExtOpc = Signed ? <STR_LIT> : <STR_LIT> ; else if ( Len == <NUM_LIT> ) ExtOpc = Signed ? <STR_LIT> : <STR_LIT> ; else if ( Len < <NUM_LIT> && ! Signed ) ExtOpc = <STR_LIT> ; } if ( ExtOpc == <NUM_LIT> ) { ExtOpc = Signed ? ( RW == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : ( RW == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; } unsigned SR = <NUM_LIT> ; if ( RW != SW && RW * <NUM_LIT> != SW ) continue ; if ( RW != SW ) SR = ( Off / RW == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; Off = Off % RW ; if ( ! validateReg ( { R , SR } , ExtOpc , <NUM_LIT> ) ) continue ; if ( MI -> getOpcode ( ) == ExtOpc ) { const MachineOperand & SrcOp = MI -> getOperand ( <NUM_LIT> ) ; if ( SrcOp . getReg ( ) == R ) continue ; } DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock & B = * MI -> getParent ( ) ; unsigned NewR = MRI . createVirtualRegister ( FRC ) ; auto At = MI -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( MI ) ; auto MIB = BuildMI ( B , At , DL , HII . get ( ExtOpc ) , NewR ) . addReg ( R , <NUM_LIT> , SR ) ; switch ( ExtOpc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> :

MIB . addImm ( ( <NUM_LIT> << Len ) - <NUM_LIT> ) ;


<s> auto At = MI -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( MI ) ; const BitTracker :: RegisterCell & SC = BT . lookup ( RS . Reg ) ; const BitTracker :: BitValue & V = SC [ F + BN ] ; if ( V . Type == BitTracker :: BitValue :: Ref && V . RefI . Reg != RS . Reg ) { const TargetRegisterClass * TC = MRI . getRegClass ( V . RefI . Reg ) ; unsigned P = std :: numeric_limits < unsigned > :: max ( ) ; BitTracker :: RegisterRef RR ( V . RefI . Reg , <NUM_LIT> ) ; if ( TC == & <STR_LIT> ) { P = V . RefI . Pos ; RR . Sub = <STR_LIT> ; if ( P >= <NUM_LIT> ) { P -= <NUM_LIT> ; RR . Sub = <STR_LIT> ; } } else if ( TC == & <STR_LIT> ) { P = V . RefI . Pos ; } if ( P != std :: numeric_limits < unsigned > :: max ( ) ) { unsigned NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( B , At , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( RR . Reg , <NUM_LIT> , RR . Sub ) . addImm ( P ) ; HBS :: replaceReg ( RD . Reg , NewR , MRI ) ; BT . put ( NewR , RC ) ; return true ; }

} else if ( V . is ( <NUM_LIT> ) || V . is ( <NUM_LIT> ) ) {


<s> auto * OpRC = HII . getRegClass ( HII . get ( Opc ) , OpNum , & HRI , MF ) ; auto * RRC = HBS :: getFinalVRegClass ( R , MRI ) ;


<s> auto * RRC = HBS :: getFinalVRegClass ( R , MRI ) ; return OpRC -> hasSubClassEq ( RRC ) ;


<s> bool Changed = false ; if ( T . TopDown ) Changed = T . processBlock ( B , AVs ) ; RegisterSet Defs ; for ( auto & I : B ) getInstrDefs ( I , Defs ) ;


<s> BitSimplification ( BitTracker & bt , const <ISA_LIT>InstrInfo & hii , MachineRegisterInfo & mri ) : Transformation ( true ) , HII ( hii ) , MRI ( mri ) , BT ( bt ) {


<s> bool RedundantInstrElimination :: computeUsedBits ( const MachineInstr & MI , unsigned OpN , BitVector & Bits , uint16_t Begin ) { unsigned Opc = MI . getOpcode ( ) ; BitVector T ( Bits . size ( ) ) ; bool GotBits = HBS :: getUsedBits ( Opc , OpN , T , Begin , HII ) ; unsigned LB , LE ; if ( isLossyShiftLeft ( MI , OpN , LB , LE ) || isLossyShiftRight ( MI , OpN , LB , LE ) ) { assert ( MI . getOperand ( OpN ) . isReg ( ) ) ; BitTracker :: RegisterRef RR = MI . getOperand ( OpN ) ; const TargetRegisterClass * RC = HBS :: getFinalVRegClass ( RR , MRI ) ; uint16_t Width = RC -> getSize ( ) * <NUM_LIT> ;


<s> ConstGeneration ( BitTracker & bt , const <ISA_LIT>InstrInfo & hii , MachineRegisterInfo & mri ) : Transformation ( true ) , HII ( hii ) , MRI ( mri ) , BT ( bt ) {


<s> CopyGeneration ( BitTracker & bt , const <ISA_LIT>InstrInfo & hii , MachineRegisterInfo & mri ) : Transformation ( true ) , HII ( hii ) , MRI ( mri ) , BT ( bt ) {


<s> CopyPropagation ( const <ISA_LIT>RegisterInfo & hri , MachineRegisterInfo & mri ) : Transformation ( false ) , MRI ( mri ) {


<s> DeadCodeElimination ( MachineFunction & mf , MachineDominatorTree & mdt ) : MF ( mf ) , HII ( * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ) , MDT ( mdt ) , MRI ( mf . getRegInfo ( ) ) {


<s> bool empty ( ) const { return ! BitVector :: any ( ) ;


if ( size ( ) <= Idx ) resize ( std :: max ( Idx + <NUM_LIT> , <NUM_LIT> ) ) ;


<s> void ensure ( unsigned Idx ) { if ( size ( ) <= Idx ) resize ( std :: max ( Idx + <NUM_LIT> , <NUM_LIT> ) ) ;


<s> bool CopyGeneration :: findMatch ( const BitTracker :: RegisterRef & Inp , BitTracker :: RegisterRef & Out , const RegisterSet & AVs ) { if ( ! BT . has ( Inp . Reg ) ) return false ; const BitTracker :: RegisterCell & InpRC = BT . lookup ( Inp . Reg ) ; unsigned B , W ; if ( ! HBS :: getSubregMask ( Inp , B , W , MRI ) ) return false ; for ( unsigned R = AVs . find_first ( ) ; R ; R = AVs . find_next ( R ) ) { if ( ! BT . has ( R ) || ! HBS :: isTransparentCopy ( R , Inp , MRI ) ) continue ; const BitTracker :: RegisterCell & RC = BT . lookup ( R ) ; unsigned RW = RC . width ( ) ; if ( W == RW ) { if ( MRI . getRegClass ( Inp . Reg ) != MRI . getRegClass ( R ) ) continue ; if ( ! HBS :: isEqual ( InpRC , B , RC , <NUM_LIT> , W ) ) continue ; Out . Reg = R ; Out . Sub = <NUM_LIT> ; return true ; } if ( W * <NUM_LIT> != RW ) continue ; if ( MRI . getRegClass ( R ) != & <STR_LIT> ) continue ; if ( HBS :: isEqual ( InpRC , B , RC , <NUM_LIT> , W ) ) Out . Sub = <STR_LIT> ;

else if ( HBS :: isEqual ( InpRC , B , RC , W , W ) ) Out . Sub = <STR_LIT> ;


<s> unsigned find_first ( ) const { int First = BitVector :: find_first ( ) ;

if ( First < <NUM_LIT> ) return <NUM_LIT> ;


<s> int Next = BitVector :: find_next ( v2x ( Prev ) ) ; if ( Next < <NUM_LIT> ) return <NUM_LIT> ;


<s> if ( COpc == Opc ) return false ; MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( B , MI , DL , HII . get ( COpc ) , NewR ) . addReg ( H . Reg , <NUM_LIT> , H . Sub ) . addReg ( L . Reg , <NUM_LIT> , L . Sub ) ; HBS :: replaceSubWithSub ( RD . Reg , RD . Sub , NewR , <NUM_LIT> , MRI ) ; BT . put ( BitTracker :: RegisterRef ( NewR ) , RC ) ;


<s> bool BitSimplification :: genExtractHalf ( MachineInstr * MI , BitTracker :: RegisterRef RD , const BitTracker :: RegisterCell & RC ) { RegHalf L ; if ( ! matchHalf ( RD . Reg , RC , <NUM_LIT> , L ) || ! HBS :: isZero ( RC , <NUM_LIT> , <NUM_LIT> ) ) return false ; unsigned Opc = MI -> getOpcode ( ) ; MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned NewR = <NUM_LIT> ; if ( L . Low && Opc != <STR_LIT> ) { NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( B , MI , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( L . Reg , <NUM_LIT> , L . Sub ) ; } else if ( ! L . Low && Opc != <STR_LIT> ) { NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( B , MI , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( L . Reg , <NUM_LIT> , L . Sub ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } if ( NewR == <NUM_LIT> ) return false ;


<s> if ( ! HBS :: getSubregMask ( RS , BN , BW , MRI ) ) continue ; if ( BW < W || ! HBS :: isEqual ( RC , <NUM_LIT> , SC , BN , W ) ) continue ; unsigned NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto MIB = BuildMI ( B , MI , DL , HII . get ( NewOpc ) , NewR ) . addReg ( RS . Reg , <NUM_LIT> , RS . Sub ) ; if ( NewOpc == <STR_LIT> ) MIB . addImm ( ( <NUM_LIT> << W ) - <NUM_LIT> ) ; else if ( NewOpc == <STR_LIT> ) MIB . addImm ( W ) . addImm ( <NUM_LIT> ) ; HBS :: replaceSubWithSub ( RD . Reg , RD . Sub , NewR , <NUM_LIT> , MRI ) ; BT . put ( BitTracker :: RegisterRef ( NewR ) , RC ) ; return true ; } return false ;


<s> BuildMI ( B , MI , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( Rs . Reg , <NUM_LIT> , Rs . Sub ) . addReg ( Rt . Reg , <NUM_LIT> , Rt . Sub ) ; HBS :: replaceSubWithSub ( RD . Reg , RD . Sub , NewR , <NUM_LIT> , MRI ) ; BT . put ( BitTracker :: RegisterRef ( NewR ) , RC ) ;


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; BuildMI ( B , MI , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( Rs . Reg , <NUM_LIT> , Rs . Sub ) . addReg ( Rt . Reg , <NUM_LIT> , Rt . Sub ) ; HBS :: replaceSubWithSub ( RD . Reg , RD . Sub , NewR , <NUM_LIT> , MRI ) ;

BT . put ( BitTracker :: RegisterRef ( NewR ) , RC ) ;


<s> if ( Opc != <STR_LIT> ) return false ; MachineOperand & ValOp = MI -> getOperand ( <NUM_LIT> ) ; BitTracker :: RegisterRef RS = ValOp ; if ( ! BT . has ( RS . Reg ) ) return false ; const BitTracker :: RegisterCell & RC = BT . lookup ( RS . Reg ) ; RegHalf H ; if ( ! matchHalf ( <NUM_LIT> , RC , <NUM_LIT> , H ) ) return false ; if ( H . Low ) return false ;

MI -> setDesc ( HII . get ( <STR_LIT> ) ) ;


<s> BuildMI ( B , At , DL , HII . get ( <STR_LIT> ) , Reg ) . addImm ( C ) ; return Reg ; } unsigned Lo = Lo_32 ( C ) , Hi = Hi_32 ( C ) ; if ( isInt < <NUM_LIT> > ( Lo ) || isInt < <NUM_LIT> > ( Hi ) ) { unsigned Opc = isInt < <NUM_LIT> > ( Lo ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , At , DL , HII . get ( Opc ) , Reg ) . addImm ( int32_t ( Hi ) ) . addImm ( int32_t ( Lo ) ) ; return Reg ; } BuildMI ( B , At , DL , HII . get ( <STR_LIT> ) , Reg ) . addImm ( C ) ; return Reg ; } if ( RC == & <STR_LIT> ) { unsigned Opc ; if ( C == <NUM_LIT> ) Opc = <STR_LIT> ; else if ( ( C & <NUM_LIT> ) == <NUM_LIT> ) Opc = <STR_LIT> ; else return <NUM_LIT> ; BuildMI ( B , At , DL , HII . get ( Opc ) , Reg ) ;


<s> AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> return HLow ? LLow ? <STR_LIT> : <STR_LIT> : LLow ? <STR_LIT> : <STR_LIT> ;


<s> assert ( B < RC . width ( ) && B + W <= RC . width ( ) ) ; int64_t T = <NUM_LIT> ; for ( uint16_t i = B + W ; i > B ; -- i ) { const BitTracker :: BitValue & BV = RC [ i - <NUM_LIT> ] ; T <<= <NUM_LIT> ; if ( BV . is ( <NUM_LIT> ) ) T |= <NUM_LIT> ; else if ( ! BV . is ( <NUM_LIT> ) ) return false ; }


<s> int64_t T = <NUM_LIT> ; for ( uint16_t i = B + W ; i > B ; -- i ) { const BitTracker :: BitValue & BV = RC [ i - <NUM_LIT> ] ; T <<= <NUM_LIT> ; if ( BV . is ( <NUM_LIT> ) ) T |= <NUM_LIT> ; else if ( ! BV . is ( <NUM_LIT> ) ) return false ; }


<s> unsigned <ISA_LIT>LoopRescheduling :: getDefReg ( const MachineInstr * MI ) { RegisterSet Defs ; HBS :: getInstrDefs ( * MI , Defs ) ; if ( Defs . count ( ) != <NUM_LIT> ) return <NUM_LIT> ;


<s> if ( ! Op . isReg ( ) || ! Op . isDef ( ) ) continue ; unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; Defs . insert ( R ) ; }


<s> for ( auto & Op : MI . operands ( ) ) {

if ( ! Op . isReg ( ) || ! Op . isUse ( ) ) continue ;


<s> unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ;


<s> bool <ISA_LIT>BitSimplify :: getSubregMask ( const BitTracker :: RegisterRef & RR , unsigned & Begin , unsigned & Width , MachineRegisterInfo & MRI ) { const TargetRegisterClass * RC = MRI . getRegClass ( RR . Reg ) ; if ( RC == & <STR_LIT> ) { assert ( RR . Sub == <NUM_LIT> ) ; Begin = <NUM_LIT> ; Width = <NUM_LIT> ; return true ; } if ( RC == & <STR_LIT> ) { if ( RR . Sub == <NUM_LIT> ) { Begin = <NUM_LIT> ; Width = <NUM_LIT> ; return true ; } assert ( RR . Sub == <STR_LIT> || RR . Sub == <STR_LIT> ) ; Width = <NUM_LIT> ; Begin = ( RR . Sub == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; return true ; }


<s> case A4_cmphgti : case A4_cmphgtui : if ( OpN == <NUM_LIT> ) { Bits . set ( Begin , Begin + <NUM_LIT> ) ; return true ; } break ; case A2_asrh : if ( OpN == <NUM_LIT> ) { Bits . set ( Begin + <NUM_LIT> , Begin + <NUM_LIT> ) ; return true ; } break ; case A4_cmpbeq : case A4_cmpbgt : case A4_cmpbgtu : if ( OpN == <NUM_LIT> ) { Bits . set ( Begin , Begin + <NUM_LIT> ) ; return true ; } break ; case A4_cmpheq : case A4_cmphgt : case A4_cmphgtu : case A2_addh_h16_ll : case A2_addh_h16_sat_ll : case A2_addh_l16_ll : case A2_addh_l16_sat_ll : case A2_combine_ll : case A2_subh_h16_ll : case A2_subh_h16_sat_ll : case A2_subh_l16_ll : case A2_subh_l16_sat_ll : case M2_mpy_acc_ll_s0 : case M2_mpy_acc_ll_s1 : case M2_mpy_acc_sat_ll_s0 : case M2_mpy_acc_sat_ll_s1 : case M2_mpy_ll_s0 : case M2_mpy_ll_s1 : case M2_mpy_nac_ll_s0 : case M2_mpy_nac_ll_s1 : case M2_mpy_nac_sat_ll_s0 : case M2_mpy_nac_sat_ll_s1 : case M2_mpy_rnd_ll_s0 : case M2_mpy_rnd_ll_s1 : case M2_mpy_sat_ll_s0 : case M2_mpy_sat_ll_s1 : case M2_mpy_sat_rnd_ll_s0 : case M2_mpy_sat_rnd_ll_s1 : case M2_mpyd_acc_ll_s0 : case M2_mpyd_acc_ll_s1 : case M2_mpyd_ll_s0 : case M2_mpyd_ll_s1 : case M2_mpyd_nac_ll_s0 : case M2_mpyd_nac_ll_s1 : case M2_mpyd_rnd_ll_s0 : case M2_mpyd_rnd_ll_s1 : case M2_mpyu_acc_ll_s0 : case M2_mpyu_acc_ll_s1 : case M2_mpyu_ll_s0 : case M2_mpyu_ll_s1 : case M2_mpyu_nac_ll_s0 : case M2_mpyu_nac_ll_s1 : case M2_mpyud_acc_ll_s0 : case M2_mpyud_acc_ll_s1 : case M2_mpyud_ll_s0 : case M2_mpyud_ll_s1 : case M2_mpyud_nac_ll_s0 : case M2_mpyud_nac_ll_s1 : if ( OpN == <NUM_LIT> || OpN == <NUM_LIT> ) { Bits . set ( Begin , Begin + <NUM_LIT> ) ; return true ; } break ; case A2_addh_h16_lh : case A2_addh_h16_sat_lh : case A2_combine_lh : case A2_subh_h16_lh : case A2_subh_h16_sat_lh : case M2_mpy_acc_lh_s0 : case M2_mpy_acc_lh_s1 : case M2_mpy_acc_sat_lh_s0 : case M2_mpy_acc_sat_lh_s1 : case M2_mpy_lh_s0 : case M2_mpy_lh_s1 : case M2_mpy_nac_lh_s0 : case M2_mpy_nac_lh_s1 : case M2_mpy_nac_sat_lh_s0 : case M2_mpy_nac_sat_lh_s1 : case M2_mpy_rnd_lh_s0 : case M2_mpy_rnd_lh_s1 : case M2_mpy_sat_lh_s0 : case M2_mpy_sat_lh_s1 : case M2_mpy_sat_rnd_lh_s0 : case M2_mpy_sat_rnd_lh_s1 : case M2_mpyd_acc_lh_s0 : case M2_mpyd_acc_lh_s1 : case M2_mpyd_lh_s0 : case M2_mpyd_lh_s1 : case M2_mpyd_nac_lh_s0 : case M2_mpyd_nac_lh_s1 : case M2_mpyd_rnd_lh_s0 : case M2_mpyd_rnd_lh_s1 : case M2_mpyu_acc_lh_s0 : case M2_mpyu_acc_lh_s1 : case M2_mpyu_lh_s0 : case M2_mpyu_lh_s1 : case M2_mpyu_nac_lh_s0 : case M2_mpyu_nac_lh_s1 : case M2_mpyud_acc_lh_s0 : case M2_mpyud_acc_lh_s1 : case M2_mpyud_lh_s0 : case M2_mpyud_lh_s1 : case M2_mpyud_nac_lh_s0 : case M2_mpyud_nac_lh_s1 : case A2_addh_l16_hl : case A2_addh_l16_sat_hl : case A2_subh_l16_hl : case A2_subh_l16_sat_hl : if ( OpN == <NUM_LIT> ) { Bits . set ( Begin , Begin + <NUM_LIT> ) ; return true ; } if ( OpN == <NUM_LIT> ) { Bits . set ( Begin + <NUM_LIT> , Begin + <NUM_LIT> ) ; return true ; } break ; case A2_addh_h16_hl : case A2_addh_h16_sat_hl : case A2_combine_hl : case A2_subh_h16_hl : case A2_subh_h16_sat_hl : case M2_mpy_acc_hl_s0 : case M2_mpy_acc_hl_s1 : case M2_mpy_acc_sat_hl_s0 : case M2_mpy_acc_sat_hl_s1 : case M2_mpy_hl_s0 :


<s> case A2_addh_l16_hl : case A2_addh_l16_sat_hl : case A2_subh_l16_hl : case A2_subh_l16_sat_hl : if ( OpN == <NUM_LIT> ) { Bits . set ( Begin , Begin + <NUM_LIT> ) ; return true ; } if ( OpN == <NUM_LIT> ) { Bits . set ( Begin + <NUM_LIT> , Begin + <NUM_LIT> ) ; return true ; } break ; case A2_addh_h16_hl : case A2_addh_h16_sat_hl : case A2_combine_hl : case A2_subh_h16_hl : case A2_subh_h16_sat_hl : case M2_mpy_acc_hl_s0 : case M2_mpy_acc_hl_s1 : case M2_mpy_acc_sat_hl_s0 : case M2_mpy_acc_sat_hl_s1 : case M2_mpy_hl_s0 : case M2_mpy_hl_s1 : case M2_mpy_nac_hl_s0 : case M2_mpy_nac_hl_s1 : case M2_mpy_nac_sat_hl_s0 : case M2_mpy_nac_sat_hl_s1 : case M2_mpy_rnd_hl_s0 : case M2_mpy_rnd_hl_s1 : case M2_mpy_sat_hl_s0 : case M2_mpy_sat_hl_s1 : case M2_mpy_sat_rnd_hl_s0 : case M2_mpy_sat_rnd_hl_s1 : case M2_mpyd_acc_hl_s0 : case M2_mpyd_acc_hl_s1 : case M2_mpyd_hl_s0 : case M2_mpyd_hl_s1 : case M2_mpyd_nac_hl_s0 : case M2_mpyd_nac_hl_s1 : case M2_mpyd_rnd_hl_s0 : case M2_mpyd_rnd_hl_s1 : case M2_mpyu_acc_hl_s0 : case M2_mpyu_acc_hl_s1 : case M2_mpyu_hl_s0 : case M2_mpyu_hl_s1 : case M2_mpyu_nac_hl_s0 : case M2_mpyu_nac_hl_s1 : case M2_mpyud_acc_hl_s0 : case M2_mpyud_acc_hl_s1 : case M2_mpyud_hl_s0 : case M2_mpyud_hl_s1 : case M2_mpyud_nac_hl_s0 : case M2_mpyud_nac_hl_s1 : if ( OpN == <NUM_LIT> ) { Bits . set ( Begin + <NUM_LIT> , Begin + <NUM_LIT> ) ; return true ; } if ( OpN == <NUM_LIT> ) { Bits . set ( Begin , Begin + <NUM_LIT> ) ; return true ; } break ; case A2_addh_h16_hh : case A2_addh_h16_sat_hh : case A2_combine_hh : case A2_subh_h16_hh : case A2_subh_h16_sat_hh : case M2_mpy_acc_hh_s0 : case M2_mpy_acc_hh_s1 : case M2_mpy_acc_sat_hh_s0 : case M2_mpy_acc_sat_hh_s1 : case M2_mpy_hh_s0 : case M2_mpy_hh_s1 : case M2_mpy_nac_hh_s0 : case M2_mpy_nac_hh_s1 : case M2_mpy_nac_sat_hh_s0 : case M2_mpy_nac_sat_hh_s1 : case M2_mpy_rnd_hh_s0 : case M2_mpy_rnd_hh_s1 : case M2_mpy_sat_hh_s0 : case M2_mpy_sat_hh_s1 : case M2_mpy_sat_rnd_hh_s0 : case M2_mpy_sat_rnd_hh_s1 : case M2_mpyd_acc_hh_s0 : case M2_mpyd_acc_hh_s1 : case M2_mpyd_hh_s0 : case M2_mpyd_hh_s1 : case M2_mpyd_nac_hh_s0 : case M2_mpyd_nac_hh_s1 : case M2_mpyd_rnd_hh_s0 : case M2_mpyd_rnd_hh_s1 : case M2_mpyu_acc_hh_s0 : case M2_mpyu_acc_hh_s1 : case M2_mpyu_hh_s0 : case M2_mpyu_hh_s1 : case M2_mpyu_nac_hh_s0 : case M2_mpyu_nac_hh_s1 : case M2_mpyud_acc_hh_s0 : case M2_mpyud_acc_hh_s1 : case M2_mpyud_hh_s0 : case M2_mpyud_hh_s1 : case M2_mpyud_nac_hh_s0 : case M2_mpyud_nac_hh_s1 :

if ( OpN == <NUM_LIT> || OpN == <NUM_LIT> ) {


<s> case S2_storerhnew_pbr : case S2_storerh_pci : case S2_storerhnew_pci : case S2_storerh_pcr : case S2_storerhnew_pcr : case S4_storerh_rr : case S4_pstorerht_rr : case S4_pstorerhf_rr : case S4_pstorerhtnew_rr : case S4_pstorerhfnew_rr : case S4_storerhnew_rr : case S4_pstorerhnewt_rr : case S4_pstorerhnewf_rr : case S4_pstorerhnewtnew_rr : case S4_pstorerhnewfnew_rr : case S2_storerhgp : case S2_storerhnewgp : case S4_pstorerht_abs : case S4_pstorerhf_abs : case S4_pstorerhtnew_abs : case S4_pstorerhfnew_abs : case S4_pstorerhnewt_abs : case S4_pstorerhnewf_abs : case S4_pstorerhnewtnew_abs : case S4_pstorerhnewfnew_abs : Bits . set ( Begin , Begin + <NUM_LIT> ) ; return true ; case S2_storerf_io : case S2_pstorerft_io : case S2_pstorerff_io : case S4_pstorerftnew_io : case S4_pstorerffnew_io : case S2_storerf_pi : case S2_pstorerft_pi : case S2_pstorerff_pi : case S2_pstorerftnew_pi : case S2_pstorerffnew_pi : case S4_storerf_ap : case S2_storerf_pr : case S4_storerf_ur : case S2_storerf_pbr : case S2_storerf_pci : case S2_storerf_pcr : case S4_storerf_rr : case S4_pstorerft_rr : case S4_pstorerff_rr : case S4_pstorerftnew_rr : case S4_pstorerffnew_rr : case S2_storerfgp : case S4_pstorerft_abs : case S4_pstorerff_abs : case S4_pstorerftnew_abs : case S4_pstorerffnew_abs : Bits . set ( Begin + <NUM_LIT> , Begin + <NUM_LIT> ) ; return true ; } return false ;


<s> using namespace <ISA_LIT> ; switch ( Opc ) { case S2_storerb_io : case S2_storerbnew_io : case S2_pstorerbt_io : case S2_pstorerbf_io : case S4_pstorerbtnew_io : case S4_pstorerbfnew_io : case S2_pstorerbnewt_io : case S2_pstorerbnewf_io : case S4_pstorerbnewtnew_io : case S4_pstorerbnewfnew_io : case S2_storerb_pi : case S2_storerbnew_pi : case S2_pstorerbt_pi : case S2_pstorerbf_pi : case S2_pstorerbtnew_pi : case S2_pstorerbfnew_pi : case S2_pstorerbnewt_pi : case S2_pstorerbnewf_pi : case S2_pstorerbnewtnew_pi : case S2_pstorerbnewfnew_pi : case S4_storerb_ap : case S4_storerbnew_ap : case S2_storerb_pr : case S2_storerbnew_pr : case S4_storerb_ur : case S4_storerbnew_ur : case S2_storerb_pbr : case S2_storerbnew_pbr : case S2_storerb_pci : case S2_storerbnew_pci : case S2_storerb_pcr : case S2_storerbnew_pcr : case S4_storerb_rr : case S4_storerbnew_rr : case S4_pstorerbt_rr : case S4_pstorerbf_rr : case S4_pstorerbtnew_rr : case S4_pstorerbfnew_rr : case S4_pstorerbnewt_rr : case S4_pstorerbnewf_rr : case S4_pstorerbnewtnew_rr : case S4_pstorerbnewfnew_rr : case S2_storerbgp : case S2_storerbnewgp : case S4_pstorerbt_abs : case S4_pstorerbf_abs : case S4_pstorerbtnew_abs : case S4_pstorerbfnew_abs : case S4_pstorerbnewt_abs : case S4_pstorerbnewf_abs : case S4_pstorerbnewtnew_abs : case S4_pstorerbnewfnew_abs : Bits . set ( Begin , Begin + <NUM_LIT> ) ; return true ; case S2_storerh_io : case S2_storerhnew_io : case S2_pstorerht_io : case S2_pstorerhf_io : case S4_pstorerhtnew_io : case S4_pstorerhfnew_io : case S2_pstorerhnewt_io : case S2_pstorerhnewf_io : case S4_pstorerhnewtnew_io : case S4_pstorerhnewfnew_io : case S2_storerh_pi : case S2_storerhnew_pi : case S2_pstorerht_pi : case S2_pstorerhf_pi : case S2_pstorerhtnew_pi : case S2_pstorerhfnew_pi : case S2_pstorerhnewt_pi : case S2_pstorerhnewf_pi : case S2_pstorerhnewtnew_pi : case S2_pstorerhnewfnew_pi : case S4_storerh_ap : case S4_storerhnew_ap : case S2_storerh_pr : case S2_storerhnew_pr : case S4_storerh_ur : case S4_storerhnew_ur : case S2_storerh_pbr : case S2_storerhnew_pbr : case S2_storerh_pci : case S2_storerhnew_pci : case S2_storerh_pcr : case S2_storerhnew_pcr : case S4_storerh_rr : case S4_pstorerht_rr : case S4_pstorerhf_rr : case S4_pstorerhtnew_rr : case S4_pstorerhfnew_rr : case S4_storerhnew_rr : case S4_pstorerhnewt_rr : case S4_pstorerhnewf_rr : case S4_pstorerhnewtnew_rr : case S4_pstorerhnewfnew_rr : case S2_storerhgp : case S2_storerhnewgp : case S4_pstorerht_abs : case S4_pstorerhf_abs : case S4_pstorerhtnew_abs : case S4_pstorerhfnew_abs : case S4_pstorerhnewt_abs : case S4_pstorerhnewf_abs : case S4_pstorerhnewtnew_abs : case S4_pstorerhnewfnew_abs : Bits . set ( Begin , Begin + <NUM_LIT> ) ; return true ; case S2_storerf_io : case S2_pstorerft_io : case S2_pstorerff_io : case S4_pstorerftnew_io : case S4_pstorerffnew_io : case S2_storerf_pi : case S2_pstorerft_pi : case S2_pstorerff_pi : case S2_pstorerftnew_pi : case S2_pstorerffnew_pi : case S4_storerf_ap : case S2_storerf_pr : case S4_storerf_ur : case S2_storerf_pbr : case S2_storerf_pci : case S2_storerf_pcr : case S4_storerf_rr : case S4_pstorerft_rr : case S4_pstorerff_rr : case S4_pstorerftnew_rr :


<s> <ISA_LIT>BitSimplify ( ) : MachineFunctionPass ( ID ) , MDT ( <NUM_LIT> ) { initialize<ISA_LIT>BitSimplifyPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> <ISA_LIT>LoopRescheduling ( ) : MachineFunctionPass ( ID ) , HII ( <NUM_LIT> ) , HRI ( <NUM_LIT> ) , MRI ( <NUM_LIT> ) , BTP ( <NUM_LIT> ) { initialize<ISA_LIT>LoopReschedulingPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> bool includes ( const RegisterSet & Rs ) const {

return ! Rs . BitVector :: test ( * this ) ;


<s> return static_cast < RegisterSet & > ( BitVector :: operator |= ( Rs ) ) ;


<s> RegisterSet & insert ( const RegisterSet & Rs ) {

return static_cast < RegisterSet & > ( BitVector :: operator |= ( Rs ) ) ;


<s> return BitVector :: anyCommon ( Rs ) ;


<s> case TargetOpcode :: COPY : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> for ( unsigned i = <NUM_LIT> , w = RC . width ( ) ; i < w ; ++ i ) { const BitTracker :: BitValue & V = RC [ i ] ;

if ( ! V . is ( <NUM_LIT> ) && ! V . is ( <NUM_LIT> ) ) return false ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : break ;


<s> bool DeadCodeElimination :: isDead ( unsigned R ) const { for ( auto I = MRI . use_begin ( R ) , E = MRI . use_end ( ) ; I != E ; ++ I ) { MachineInstr * UseI = I -> getParent ( ) ; if ( UseI -> isDebugValue ( ) ) continue ; if ( UseI -> isPHI ( ) ) { assert ( ! UseI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ) ; unsigned DR = UseI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DR == R ) continue ; } return false ; }


<s> bool DeadCodeElimination :: isDead ( unsigned R ) const { for ( auto I = MRI . use_begin ( R ) , E = MRI . use_end ( ) ; I != E ; ++ I ) { MachineInstr * UseI = I -> getParent ( ) ; if ( UseI -> isDebugValue ( ) ) continue ; if ( UseI -> isPHI ( ) ) { assert ( ! UseI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ) ; unsigned DR = UseI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DR == R ) continue ; }


<s> if ( RC1 [ B1 + i ] . Type == BitTracker :: BitValue :: Ref && RC1 [ B1 + i ] . RefI . Reg == <NUM_LIT> ) return false ; if ( RC2 [ B2 + i ] . Type == BitTracker :: BitValue :: Ref && RC2 [ B2 + i ] . RefI . Reg == <NUM_LIT> ) return false ; if ( RC1 [ B1 + i ] != RC2 [ B2 + i ] ) return false ; }


<s> case S2_asl_i_p : ImN = <NUM_LIT> ; RegN = <NUM_LIT> ; Width = <NUM_LIT> ; break ; case S2_asl_i_p_acc : case S2_asl_i_p_and : case S2_asl_i_p_nac : case S2_asl_i_p_or : case S2_asl_i_p_xacc : ImN = <NUM_LIT> ; RegN = <NUM_LIT> ; Width = <NUM_LIT> ; break ; case S2_asl_i_r : ImN = <NUM_LIT> ; RegN = <NUM_LIT> ; Width = <NUM_LIT> ; break ; case S2_addasl_rrri : case S4_andi_asl_ri : case S4_ori_asl_ri : case S4_addi_asl_ri : case S4_subi_asl_ri : case S2_asl_i_r_acc : case S2_asl_i_r_and : case S2_asl_i_r_nac : case S2_asl_i_r_or : case S2_asl_i_r_sat : case S2_asl_i_r_xacc : ImN = <NUM_LIT> ; RegN = <NUM_LIT> ; Width = <NUM_LIT> ; break ;


<s> for ( unsigned i = <NUM_LIT> ; i < W ; ++ i ) { const BitTracker :: BitValue & V1 = OutC1 [ i ] , & V2 = OutC2 [ i ] ; if ( V1 . Type != V2 . Type || V1 . Type == BitTracker :: BitValue :: One ) return false ; if ( V1 . Type != BitTracker :: BitValue :: Ref ) continue ; if ( V1 . RefI . Pos != V2 . RefI . Pos ) return false ; if ( V1 . RefI . Reg != InpR1 ) return false ;

if ( V2 . RefI . Reg == <NUM_LIT> || V2 . RefI . Reg == OutR2 ) return false ;


<s> if ( V1 . Type != BitTracker :: BitValue :: Ref ) continue ; if ( V1 . RefI . Pos != V2 . RefI . Pos ) return false ; if ( V1 . RefI . Reg != InpR1 ) return false ; if ( V2 . RefI . Reg == <NUM_LIT> || V2 . RefI . Reg == OutR2 ) return false ; if ( ! MatchR ) MatchR = V2 . RefI . Reg ; else if ( V2 . RefI . Reg != MatchR ) return false ;


<s> for ( unsigned i = <NUM_LIT> , w = OutC . width ( ) ; i < w ; ++ i ) { const BitTracker :: BitValue & V = OutC [ i ] ;

if ( V . Type != BitTracker :: BitValue :: Ref ) continue ;


<s> if ( ! BTP -> has ( OutR ) || ! BTP -> has ( InpR ) ) return false ; const BitTracker :: RegisterCell & OutC = BTP -> lookup ( OutR ) ; for ( unsigned i = <NUM_LIT> , w = OutC . width ( ) ; i < w ; ++ i ) { const BitTracker :: BitValue & V = OutC [ i ] ; if ( V . Type != BitTracker :: BitValue :: Ref ) continue ; if ( V . RefI . Reg != InpR ) return false ; }


<s> for ( unsigned i = <NUM_LIT> , n = MI -> getNumOperands ( ) ; i < n ; ++ i ) { const MachineOperand & Op = MI -> getOperand ( i ) ; if ( ! Op . isReg ( ) ) continue ; if ( Op . getReg ( ) == InpR ) return i == n - <NUM_LIT> ;


if ( Op . getReg ( ) == InpR ) return i == n - <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( RD . Reg ) || ! TargetRegisterInfo :: isVirtualRegister ( RS . Reg ) ) return false ; auto * DRC = getFinalVRegClass ( RD , MRI ) ;


<s> bool <ISA_LIT>BitSimplify :: isZero ( const BitTracker :: RegisterCell & RC , uint16_t B , uint16_t W ) { assert ( B < RC . width ( ) && B + W <= RC . width ( ) ) ;

for ( uint16_t i = B ; i < B + W ; ++ i ) if ( ! RC [ i ] . is ( <NUM_LIT> ) ) return false ;


<s> for ( uint16_t i = B ; i < B + W ; ++ i ) if ( ! RC [ i ] . is ( <NUM_LIT> ) ) return false ;


<s> LoopCand ( MachineBasicBlock * lb , MachineBasicBlock * pb , MachineBasicBlock * eb ) : LB ( lb ) , PB ( pb ) , EB ( eb ) {


<s> const BitTracker :: RegisterCell & SC = BT . lookup ( Reg ) ; if ( Pos + <NUM_LIT> > SC . width ( ) ) return false ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { const BitTracker :: BitValue & RV = RC [ i + B ] ; if ( RV . Type == BitTracker :: BitValue :: Ref ) { if ( RV . RefI . Reg != Reg ) return false ; if ( RV . RefI . Pos != i + Pos ) return false ; continue ; } if ( RC [ i + B ] != SC [ i + Pos ] ) return false ; } unsigned Sub = <NUM_LIT> ; switch ( Pos ) { case <NUM_LIT> : Sub = <STR_LIT> ; Low = true ; break ; case <NUM_LIT> : Sub = <STR_LIT> ; Low = false ; break ; case <NUM_LIT> :


<s> if ( ! matchHalf ( SelfR , RC , <NUM_LIT> , H2 ) || ! matchHalf ( SelfR , RC , <NUM_LIT> , H1 ) ) return false ;

if ( H1 . Reg != L1 . Reg || H1 . Sub != L1 . Sub || H1 . Low || ! L1 . Low ) return false ;


<s> void <ISA_LIT>LoopRescheduling :: moveGroup ( InstrGroup & G , MachineBasicBlock & LB , MachineBasicBlock & PB , MachineBasicBlock :: iterator At , unsigned OldPhiR , unsigned NewPredR ) { DenseMap < unsigned , unsigned > RegMap ; const TargetRegisterClass * PhiRC = MRI -> getRegClass ( NewPredR ) ; unsigned PhiR = MRI -> createVirtualRegister ( PhiRC ) ; BuildMI ( LB , At , At -> getDebugLoc ( ) , HII -> get ( TargetOpcode :: PHI ) , PhiR ) . addReg ( NewPredR ) . addMBB ( & PB ) . addReg ( G . Inp . Reg ) . addMBB ( & LB ) ; RegMap . insert ( std :: make_pair ( G . Inp . Reg , PhiR ) ) ; for ( unsigned i = G . Ins . size ( ) ; i > <NUM_LIT> ; -- i ) { const MachineInstr * SI = G . Ins [ i - <NUM_LIT> ] ; unsigned DR = getDefReg ( SI ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( DR ) ; unsigned NewDR = MRI -> createVirtualRegister ( RC ) ; DebugLoc DL = SI -> getDebugLoc ( ) ; auto MIB = BuildMI ( LB , At , DL , HII -> get ( SI -> getOpcode ( ) ) , NewDR ) ; for ( unsigned j = <NUM_LIT> , m = SI -> getNumOperands ( ) ; j < m ; ++ j ) { const MachineOperand & Op = SI -> getOperand ( j ) ; if ( ! Op . isReg ( ) ) { MIB . addOperand ( Op ) ;


<s> if ( Sub1 == <STR_LIT> && Sub2 == <STR_LIT> ) { SL = I . getOperand ( <NUM_LIT> ) ; SH = I . getOperand ( <NUM_LIT> ) ; return true ; } if ( Sub1 == <STR_LIT> && Sub2 == <STR_LIT> ) { SH = I . getOperand ( <NUM_LIT> ) ; SL = I . getOperand ( <NUM_LIT> ) ; return true ; }


<s> PrintRegSet ( const RegisterSet & S , const TargetRegisterInfo * RI ) : RS ( S ) , TRI ( RI ) {


<s> if ( ! BT . has ( RD . Reg ) ) continue ; const TargetRegisterClass * FRC = HBS :: getFinalVRegClass ( RD , MRI ) ; const BitTracker :: RegisterCell & RC = BT . lookup ( RD . Reg ) ; if ( FRC -> getID ( ) == <STR_LIT> ) { bool T = genPackhl ( MI , RD , RC ) ; Changed |= T ; continue ; } if ( FRC -> getID ( ) == <STR_LIT> ) { bool T = genExtractHalf ( MI , RD , RC ) ;

T = T || genCombineHalf ( MI , RD , RC ) ;


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<s> case <STR_LIT> : case <STR_LIT> : { BitTracker :: RegisterRef RS = MI . getOperand ( <NUM_LIT> ) ; if ( ! HBS :: isTransparentCopy ( RD , RS , MRI ) ) break ; if ( RS . Sub != <NUM_LIT> ) Changed = HBS :: replaceRegWithSub ( RD . Reg , RS . Reg , RS . Sub , MRI ) ; else Changed = HBS :: replaceReg ( RD . Reg , RS . Reg , MRI ) ; break ; } case TargetOpcode :: REG_SEQUENCE : { BitTracker :: RegisterRef SL , SH ; if ( HBS :: parseRegSequence ( MI , SL , SH ) ) { Changed = HBS :: replaceSubWithSub ( RD . Reg , <STR_LIT> , SL . Reg , SL . Sub , MRI ) ; Changed |= HBS :: replaceSubWithSub ( RD . Reg , <STR_LIT> , SH . Reg , SH . Sub , MRI ) ; } break ; } case <STR_LIT> : { BitTracker :: RegisterRef RH = MI . getOperand ( <NUM_LIT> ) , RL = MI . getOperand ( <NUM_LIT> ) ; Changed = HBS :: replaceSubWithSub ( RD . Reg , <STR_LIT> , RL . Reg , RL . Sub , MRI ) ; Changed |= HBS :: replaceSubWithSub ( RD . Reg , <STR_LIT> , RH . Reg , RH . Sub , MRI ) ; break ; } case <STR_LIT> : case <STR_LIT> : { unsigned SrcX = ( Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ;

unsigned Sub = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ;


<s> bool CopyPropagation :: propagateRegCopy ( MachineInstr & MI ) { bool Changed = false ; unsigned Opc = MI . getOpcode ( ) ; BitTracker :: RegisterRef RD = MI . getOperand ( <NUM_LIT> ) ; assert ( MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) ; switch ( Opc ) { case TargetOpcode :: COPY : case <STR_LIT> : case <STR_LIT> : { BitTracker :: RegisterRef RS = MI . getOperand ( <NUM_LIT> ) ; if ( ! HBS :: isTransparentCopy ( RD , RS , MRI ) ) break ; if ( RS . Sub != <NUM_LIT> ) Changed = HBS :: replaceRegWithSub ( RD . Reg , RS . Reg , RS . Sub , MRI ) ; else Changed = HBS :: replaceReg ( RD . Reg , RS . Reg , MRI ) ; break ; } case TargetOpcode :: REG_SEQUENCE : { BitTracker :: RegisterRef SL , SH ;

if ( HBS :: parseRegSequence ( MI , SL , SH ) ) {


<s> RedundantInstrElimination ( BitTracker & bt , const <ISA_LIT>InstrInfo & hii , MachineRegisterInfo & mri ) : Transformation ( true ) , HII ( hii ) , MRI ( mri ) , BT ( bt ) {


<s> RegisterSet ( const RegisterSet & RS ) : BitVector ( RS ) {


<s> RegisterSet & remove ( const RegisterSet & Rs ) { return static_cast < RegisterSet & > ( BitVector :: reset ( Rs ) ) ;


<s> auto Begin = MRI . use_begin ( OldR ) , End = MRI . use_end ( ) ; decltype ( End ) NextI ;

for ( auto I = Begin ; I != End ; I = NextI ) {


<s> decltype ( End ) NextI ; for ( auto I = Begin ; I != End ; I = NextI ) { NextI = std :: next ( I ) ; if ( I -> getSubReg ( ) != OldSR ) continue ;


<s> bool <ISA_LIT>BitSimplify :: replaceSubWithSub ( unsigned OldR , unsigned OldSR , unsigned NewR , unsigned NewSR , MachineRegisterInfo & MRI ) { if ( ! TargetRegisterInfo :: isVirtualRegister ( OldR ) || ! TargetRegisterInfo :: isVirtualRegister ( NewR ) ) return false ; auto Begin = MRI . use_begin ( OldR ) , End = MRI . use_end ( ) ; decltype ( End ) NextI ;


<s> return runOnNode ( MDT . getRootNode ( ) ) ;


<s> for ( auto I = GTN :: child_begin ( N ) , E = GTN :: child_end ( N ) ; I != E ; ++ I ) Changed |= runOnNode ( * I ) ; MachineBasicBlock * B = N -> getBlock ( ) ; std :: vector < MachineInstr * > Instrs ; for ( auto I = B -> rbegin ( ) , E = B -> rend ( ) ; I != E ; ++ I ) Instrs . push_back ( & * I ) ; for ( auto MI : Instrs ) { unsigned Opc = MI -> getOpcode ( ) ;

if ( Opc == TargetOpcode :: LIFETIME_START || Opc == TargetOpcode :: LIFETIME_END ) continue ;


<s> bool AllDead = true ; SmallVector < unsigned , <NUM_LIT> > Regs ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) ) continue ; unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) || ! isDead ( R ) ) { AllDead = false ; break ; } Regs . push_back ( R ) ; } if ( ! AllDead ) continue ; B -> erase ( MI ) ; for ( unsigned i = <NUM_LIT> , n = Regs . size ( ) ; i != n ; ++ i ) MRI . markUsesInDebugValueAsUndef ( Regs [ i ] ) ; Changed = true ; }


<s> MachineBasicBlock & B = * MI -> getParent ( ) ; const BitTracker :: RegisterCell & SC = BT . lookup ( RS . Reg ) ; const BitTracker :: BitValue & V = SC [ F + BN ] ; if ( V . Type == BitTracker :: BitValue :: Ref && V . RefI . Reg != RS . Reg ) { const TargetRegisterClass * TC = MRI . getRegClass ( V . RefI . Reg ) ; unsigned P = UINT_MAX ; BitTracker :: RegisterRef RR ( V . RefI . Reg , <NUM_LIT> ) ; if ( TC == & <STR_LIT> ) { P = V . RefI . Pos ; RR . Sub = <STR_LIT> ; if ( P >= <NUM_LIT> ) { P -= <NUM_LIT> ; RR . Sub = <STR_LIT> ; } } else if ( TC == & <STR_LIT> ) { P = V . RefI . Pos ; } if ( P != UINT_MAX ) { unsigned NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( B , MI , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( RR . Reg , <NUM_LIT> , RR . Sub ) . addImm ( P ) ; HBS :: replaceReg ( RD . Reg , NewR , MRI ) ;


<s> Transformation ( bool TD ) : TopDown ( TD ) {


<s> const BitTracker :: RegisterCell & SC = BT . lookup ( RS . Reg ) ; unsigned DB , DW ; if ( ! HBS :: getSubregMask ( RD , DB , DW , MRI ) ) return false ; unsigned SB , SW ; if ( ! HBS :: getSubregMask ( RS , SB , SW , MRI ) ) return false ; if ( SW != DW ) return false ; BitVector Used ( DC . width ( ) ) ; if ( ! computeUsedBits ( RD . Reg , Used ) ) return false ;

for ( unsigned i = <NUM_LIT> ; i != DW ; ++ i ) if ( Used [ i + DB ] && DC [ DB + i ] != SC [ SB + i ] ) return false ;


<s> if ( SW != DW ) return false ; BitVector Used ( DC . width ( ) ) ; if ( ! computeUsedBits ( RD . Reg , Used ) ) return false ;


<s> return TargetRegisterInfo :: virtReg2Index ( v ) ;


<s> static inline unsigned v2x ( unsigned v ) {

return TargetRegisterInfo :: virtReg2Index ( v ) ;


<s> if ( T . TopDown ) Changed = T . processBlock ( B , AVs ) ; RegisterSet Defs ; for ( auto & I : B ) getInstrDefs ( I , Defs ) ; RegisterSet NewAVs = AVs ; NewAVs . insert ( Defs ) ; for ( auto I = GTN :: child_begin ( N ) , E = GTN :: child_end ( N ) ; I != E ; ++ I ) {

MachineBasicBlock * SB = ( * I ) -> getBlock ( ) ;


<s> static inline unsigned x2v ( unsigned x ) {

return TargetRegisterInfo :: index2VirtReg ( x ) ;


<s> return TargetRegisterInfo :: index2VirtReg ( x ) ;


<s> bool DeadCodeElimination :: isDead ( unsigned R ) const { for ( const MachineOperand & MO : MRI . use_operands ( R ) ) {

const MachineInstr * UseI = MO . getParent ( ) ;


<s> for ( MachineInstr & MI : llvm :: reverse ( B ) ) Instrs . push_back ( & MI ) ; bool Changed = false ; for ( auto I : Instrs ) { unsigned Opc = I -> getOpcode ( ) ; if ( ! CopyPropagation :: isCopyReg ( Opc , true ) ) continue ; Changed |= propagateRegCopy ( * I ) ;


<s> for ( MachineInstr & MI : llvm :: reverse ( B ) ) Instrs . push_back ( & MI ) ; bool Changed = false ; for ( auto I : Instrs ) {


<s> std :: vector < PhiInfo > Phis ; for ( auto & I : * C . LB ) { if ( ! I . isPHI ( ) ) break ; unsigned PR = getDefReg ( & I ) ; if ( isConst ( PR ) ) continue ; bool BadUse = false , GoodUse = false ; for ( const MachineOperand & MO : MRI -> use_operands ( PR ) ) { const MachineInstr * UseI = MO . getParent ( ) ; if ( UseI -> getParent ( ) != C . LB ) {


<s>
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
printMBBReference
(
*
C
.
LB
)
<<
<STR_LIT>
)
;
std
::
vector
<
PhiInfo
>
Phis
;
for
(
auto
&
I
:
*
C
.
LB
)
{
if
(
!
I
.
isPHI
(
)
)
break
;
unsigned
PR
=
getDefReg
(
&
I
)
;
if
(
isConst
(
PR
)
)
continue
;
bool
BadUse
=
false
,
GoodUse
=
false
;
for
(
const
MachineOperand
&
MO
:
MRI
->
use_operands
(
PR
)
)
{
const
MachineInstr
*
UseI
=
MO
.
getParent
(
)
;
if
(
UseI
->
getParent
(
)
!=
C
.
LB
)
{
BadUse
=
true
;
break
;
}
if
(
isBitShuffle
(
UseI
,
PR
)
||
isStoreInput
(
UseI
,
PR
)
)
GoodUse
=
true
;
}
if
(
BadUse
||
!
GoodUse
)
continue
;
Phis
.
push_back
(
PhiInfo
(
I
,
*
C
.
LB
)
)
;
}
LLVM_DEBUG
(
{
dbgs
(
)
<<
<STR_LIT>
;
for
(
auto
&
I
:
Phis
)
{
dbgs
(
)
<<
' '
<<
printReg
(
I
.
DefR
,
HRI
)
<<
<STR_LIT>
<<
printReg
(
I
.
PR
.
Reg
,
HRI
,
I
.
PR
.
Sub
)
<<
<STR_LIT>
<<
I
.
PB
->
getNumber
(
)
<<
','
<<
printReg
(
I
.
LR
.
Reg
,
HRI
,
I
.
LR
.
Sub
)
<<
<STR_LIT>
<<
I
.
LB
->
getNumber
(
)
<<
')'
;
}


<s> ( void ) HRI ; assert ( Sub == HRI . get<ISA_LIT>SubRegIndex ( * RC , <STR_LIT> ) || Sub == HRI . get<ISA_LIT>SubRegIndex ( * RC , <STR_LIT> ) ) ; } ; switch ( RC -> getID ( ) ) { case <STR_LIT> : VerifySR ( RC , RR . Sub ) ; return & <STR_LIT> ; case <STR_LIT> :


<s> <ISA_LIT>BitSimplify ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>BitSimplifyPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> Forbidden . insert ( R ) ; continue ; } if ( FRC == & <STR_LIT> || FRC == & <STR_LIT> ) { unsigned SubLo = HRI . get<ISA_LIT>SubRegIndex ( * FRC , <STR_LIT> ) ; unsigned SubHi = HRI . get<ISA_LIT>SubRegIndex ( * FRC , <STR_LIT> ) ; BitTracker :: RegisterRef TL = { R , SubLo } ; BitTracker :: RegisterRef TH = { R , SubHi } ; BitTracker :: RegisterRef ML , MH ; if ( findMatch ( TL , ML , AVB ) && findMatch ( TH , MH , AVB ) ) { auto * FRC = HBS :: getFinalVRegClass ( R , MRI ) ; unsigned NewR = MRI . createVirtualRegister ( FRC ) ; BuildMI ( B , At , DL , HII . get ( TargetOpcode :: REG_SEQUENCE ) , NewR ) . addReg ( ML . Reg , <NUM_LIT> , ML . Sub ) . addImm ( SubLo ) . addReg ( MH . Reg , <NUM_LIT> , MH . Sub ) . addImm ( SubHi ) ; BT . put ( BitTracker :: RegisterRef ( NewR ) , BT . get ( R ) ) ;


<s> return C . width ( ) - Z ; } ; unsigned Z = ctlz ( RC ) ; if ( Z == <NUM_LIT> || Z == W ) return false ; const BitTracker :: BitValue & B0 = RC [ <NUM_LIT> ] ; if ( B0 . Type != BitTracker :: BitValue :: Ref ) return false ; unsigned SrcR = B0 . RefI . Reg ; unsigned SrcSR = <NUM_LIT> ; unsigned Pos = B0 . RefI . Pos ; for ( unsigned i = <NUM_LIT> ; i < W - Z ; ++ i ) { const BitTracker :: BitValue & V = RC [ i ] ; if ( V . Type != BitTracker :: BitValue :: Ref ) return false ; if ( V . RefI . Reg != SrcR || V . RefI . Pos != Pos + i ) return false ; } for ( unsigned S = AVs . find_first ( ) ; S ; S = AVs . find_next ( S ) ) { if ( ! BT . has ( S ) ) continue ; const BitTracker :: RegisterCell & SC = BT . lookup ( S ) ; if ( SC . width ( ) != W || ctlz ( SC ) != W - Z ) continue ; const BitTracker :: BitValue & S0 = SC [ <NUM_LIT> ] ; if ( S0 . Type != BitTracker :: BitValue :: Ref || S0 . RefI . Reg != SrcR ) continue ; unsigned P = S0 . RefI . Pos ; if ( Pos <= P && ( Pos + W - Z ) != P ) continue ; if ( P < Pos && ( P + Z ) != Pos ) continue ; if ( std :: min ( P , Pos ) != <NUM_LIT> && std :: min ( P , Pos ) != <NUM_LIT> ) continue ; unsigned I ;


<s> if ( I != Z ) continue ; CountBitSplit ++ ; MachineInstr * DefS = MRI . getVRegDef ( S ) ; assert ( DefS != nullptr ) ; DebugLoc DL = DefS -> getDebugLoc ( ) ; MachineBasicBlock & B = * DefS -> getParent ( ) ; auto At = DefS -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( DefS ) ; if ( MRI . getRegClass ( SrcR ) -> getID ( ) == <STR_LIT> ) SrcSR = ( std :: min ( Pos , P ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( ! validateReg ( { SrcR , SrcSR } , <STR_LIT> , <NUM_LIT> ) ) continue ; unsigned ImmOp = Pos <= P ? W - Z : Z ; unsigned NewR = <NUM_LIT> ; for ( MachineInstr * In : NewMIs ) { if ( In -> getOpcode ( ) != <STR_LIT> ) continue ; MachineOperand & Op1 = In -> getOperand ( <NUM_LIT> ) ; if ( Op1 . getReg ( ) != SrcR || Op1 . getSubReg ( ) != SrcSR ) continue ; if ( In -> getOperand ( <NUM_LIT> ) . getImm ( ) != ImmOp ) continue ; MachineOperand & Op0 = In -> getOperand ( <NUM_LIT> ) ; MachineInstr * DefI = MRI . getVRegDef ( Op0 . getReg ( ) ) ; assert ( DefI != nullptr ) ; if ( ! MDT . dominates ( DefI , & * At ) ) continue ; assert ( Op0 . getSubReg ( ) == <NUM_LIT> ) ; NewR = Op0 . getReg ( ) ; break ; } if ( ! NewR ) { NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto NewBS = BuildMI ( B , At , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( SrcR , <NUM_LIT> , SrcSR ) . addImm ( ImmOp ) ; NewMIs . push_back ( NewBS ) ; } if ( Pos <= P ) { HBS :: replaceRegWithSub ( RD . Reg , NewR , <STR_LIT> , MRI ) ; HBS :: replaceRegWithSub ( S , NewR , <STR_LIT> , MRI ) ; } else { HBS :: replaceRegWithSub ( S , NewR , <STR_LIT> , MRI ) ; HBS :: replaceRegWithSub ( RD . Reg , NewR , <STR_LIT> , MRI ) ; } return true ; }


<s> for ( unsigned I = <NUM_LIT> ; I != W ; ++ I ) { const BitTracker :: BitValue & V = RC [ I ] ; if ( V . Type == BitTracker :: BitValue :: Ref && V . RefI . Reg == RD . Reg ) return false ; IsConst = IsConst && ( V . is ( <NUM_LIT> ) || V . is ( <NUM_LIT> ) ) ; } if ( IsConst ) return false ; if ( TopV . is ( <NUM_LIT> ) || TopV . is ( <NUM_LIT> ) ) { bool S = TopV . is ( <NUM_LIT> ) ; for ( -- W ; W > <NUM_LIT> && RC [ W - <NUM_LIT> ] . is ( S ) ; -- W ) ; Len = W ; Signed = S ; if ( Signed ) ++ Len ; } else { assert ( TopV . Type == BitTracker :: BitValue :: Ref ) ; if ( TopV . RefI . Reg == RD . Reg || TopV . RefI . Pos == W - <NUM_LIT> ) return false ; for ( -- W ; W > <NUM_LIT> && RC [ W - <NUM_LIT> ] == TopV ; -- W ) ; Len = W + <NUM_LIT> ; Signed = true ; } if ( Len == RW ) return false ; DEBUG ( { dbgs ( ) << __func__ << <STR_LIT> << PrintReg ( RD . Reg , & HRI , RD . Sub ) << <STR_LIT> << * MI ; dbgs ( ) << <STR_LIT> << RC << '\n' ; dbgs ( ) << <STR_LIT> << Len << <STR_LIT> << ( Signed ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> ; } ) ; bool Changed = false ; for ( unsigned R = AVs . find_first ( ) ; R != <NUM_LIT> ; R = AVs . find_next ( R ) ) { if ( ! BT . has ( R ) ) continue ; const BitTracker :: RegisterCell & SC = BT . lookup ( R ) ; unsigned SW = SC . width ( ) ; if ( SW < RW || ( SW % RW ) != <NUM_LIT> ) continue ; unsigned Off = <NUM_LIT> ; while ( Off <= SW - Len ) { unsigned OE = ( Off + Len ) / RW ; if ( OE != Off / RW ) { Off = OE * RW ; continue ; } if ( HBS :: isEqual ( RC , <NUM_LIT> , SC , Off , Len ) ) break ; ++ Off ; } if ( Off > SW - Len ) continue ; unsigned ExtOpc = <NUM_LIT> ; if ( Off == <NUM_LIT> ) { if ( Len == <NUM_LIT> ) ExtOpc = Signed ? <STR_LIT> : <STR_LIT> ;

else if ( Len == <NUM_LIT> ) ExtOpc = Signed ? <STR_LIT> : <STR_LIT> ;


<s> if ( ! HBS :: getSubregMask ( RS , BN , BW , MRI ) ) continue ; const BitTracker :: RegisterCell & SC = BT . lookup ( RS . Reg ) ; if ( ! usedBitsEqual ( RD , RS ) && ! HBS :: isEqual ( DC , <NUM_LIT> , SC , BN , BW ) ) continue ; const DebugLoc & DL = MI -> getDebugLoc ( ) ; const TargetRegisterClass * FRC = HBS :: getFinalVRegClass ( RD , MRI ) ; unsigned NewR = MRI . createVirtualRegister ( FRC ) ; MachineInstr * CopyI = BuildMI ( B , At , DL , HII . get ( TargetOpcode :: COPY ) , NewR ) . addReg ( RS . Reg , <NUM_LIT> , RS . Sub ) ; HBS :: replaceSubWithSub ( RD . Reg , RD . Sub , NewR , <NUM_LIT> , MRI ) ; BT . visit ( * CopyI ) ; Changed = true ;


<s> bool BitSimplification :: simplifyExtractLow ( MachineInstr * MI , BitTracker :: RegisterRef RD , const BitTracker :: RegisterCell & RC , const RegisterSet & AVs ) { if ( ! GenExtract ) return false ; if ( MaxExtract . getNumOccurrences ( ) ) { if ( CountExtract >= MaxExtract ) return false ; CountExtract ++ ; } unsigned W = RC . width ( ) ; unsigned RW = W ; unsigned Len ; bool Signed ; const TargetRegisterClass * FRC = HBS :: getFinalVRegClass ( RD , MRI ) ; if ( FRC != & <STR_LIT> && FRC != & <STR_LIT> ) return false ; assert ( RD . Sub == <NUM_LIT> ) ; const BitTracker :: BitValue & TopV = RC [ W - <NUM_LIT> ] ; bool IsConst = true ; for ( unsigned I = <NUM_LIT> ; I != W ; ++ I ) { const BitTracker :: BitValue & V = RC [ I ] ; if ( V . Type == BitTracker :: BitValue :: Ref && V . RefI . Reg == RD . Reg ) return false ; IsConst = IsConst && ( V . is ( <NUM_LIT> ) || V . is ( <NUM_LIT> ) ) ; } if ( IsConst ) return false ; if ( TopV . is ( <NUM_LIT> ) || TopV . is ( <NUM_LIT> ) ) { bool S = TopV . is ( <NUM_LIT> ) ; for ( -- W ; W > <NUM_LIT> && RC [ W - <NUM_LIT> ] . is ( S ) ; -- W ) ; Len = W ; Signed = S ; if ( Signed ) ++ Len ; } else { assert ( TopV . Type == BitTracker :: BitValue :: Ref ) ; if ( TopV . RefI . Reg == RD . Reg || TopV . RefI . Pos == W - <NUM_LIT> ) return false ; for ( -- W ; W > <NUM_LIT> && RC [ W - <NUM_LIT> ] == TopV ; -- W ) ; Len = W + <NUM_LIT> ; Signed = true ; } if ( Len == RW ) return false ; LLVM_DEBUG ( {

dbgs ( ) << __func__ << <STR_LIT> << printReg ( RD . Reg , & HRI , RD . Sub ) << <STR_LIT> << * MI ;


<s> unsigned OE = ( Off + Len ) / RW ; if ( OE != Off / RW ) { Off = OE * RW ; continue ; } if ( HBS :: isEqual ( RC , <NUM_LIT> , SC , Off , Len ) ) break ; ++ Off ; } if ( Off > SW - Len ) continue ; unsigned ExtOpc = <NUM_LIT> ; if ( Off == <NUM_LIT> ) { if ( Len == <NUM_LIT> ) ExtOpc = Signed ? <STR_LIT> : <STR_LIT> ; else if ( Len == <NUM_LIT> ) ExtOpc = Signed ? <STR_LIT> : <STR_LIT> ; else if ( Len < <NUM_LIT> && ! Signed ) ExtOpc = <STR_LIT> ; } if ( ExtOpc == <NUM_LIT> ) { ExtOpc = Signed ? ( RW == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : ( RW == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; } unsigned SR = <NUM_LIT> ; if ( RW != SW && RW * <NUM_LIT> != SW ) continue ; if ( RW != SW ) SR = ( Off / RW == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; Off = Off % RW ; if ( ! validateReg ( { R , SR } , ExtOpc , <NUM_LIT> ) ) continue ; if ( MI -> getOpcode ( ) == ExtOpc ) { const MachineOperand & SrcOp = MI -> getOperand ( <NUM_LIT> ) ; if ( SrcOp . getReg ( ) == R ) continue ; } DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock & B = * MI -> getParent ( ) ; unsigned NewR = MRI . createVirtualRegister ( FRC ) ; auto At = MI -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( MI ) ; auto MIB = BuildMI ( B , At , DL , HII . get ( ExtOpc ) , NewR ) . addReg ( R , <NUM_LIT> , SR ) ; switch ( ExtOpc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : MIB . addImm ( ( <NUM_LIT> << Len ) - <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MIB . addImm ( Len ) . addImm ( Off ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } HBS :: replaceReg ( RD . Reg , NewR , MRI ) ; BT . put ( BitTracker :: RegisterRef ( NewR ) , RC ) ; Changed = true ; break ; }


<s> std :: vector < PhiInfo > Phis ; for ( auto & I : * C . LB ) { if ( ! I . isPHI ( ) ) break ; unsigned PR = getDefReg ( & I ) ; if ( isConst ( PR ) ) continue ; bool BadUse = false , GoodUse = false ; for ( auto UI = MRI -> use_begin ( PR ) , UE = MRI -> use_end ( ) ; UI != UE ; ++ UI ) { MachineInstr * UseI = UI -> getParent ( ) ; if ( UseI -> getParent ( ) != C . LB ) { BadUse = true ; break ; } if ( isBitShuffle ( UseI , PR ) || isStoreInput ( UseI , PR ) ) GoodUse = true ; } if ( BadUse || ! GoodUse ) continue ; Phis . push_back ( PhiInfo ( I , * C . LB ) ) ; }


<s>
DEBUG
(
{
dbgs
(
)
<<
<STR_LIT>
;
for
(
auto
&
I
:
Phis
)
{
dbgs
(
)
<<
' '
<<
printReg
(
I
.
DefR
,
HRI
)
<<
<STR_LIT>
<<
printReg
(
I
.
PR
.
Reg
,
HRI
,
I
.
PR
.
Sub
)
<<
<STR_LIT>
<<
I
.
PB
->
getNumber
(
)
<<
','
<<
printReg
(
I
.
LR
.
Reg
,
HRI
,
I
.
LR
.
Sub
)
<<
<STR_LIT>
<<
I
.
LB
->
getNumber
(
)
<<
')'
;
}
dbgs
(
)
<<
<STR_LIT>
;


<s> CopyPropagation CopyP ( HRI , MRI ) ; Changed |= visitBlock ( Entry , CopyP , ACP ) ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) || Changed ; BT . run ( ) ; RegisterSet ABS ; BitSimplification BitS ( BT , * MDT , HII , HRI , MRI , MF ) ; Changed |= visitBlock ( Entry , BitS , ABS ) ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) || Changed ; if ( Changed ) {

for ( auto & B : MF ) for ( auto & I : B ) I . clearKillInfo ( ) ;


<s> } unsigned W = RC . width ( ) ; unsigned RW = W ; unsigned Len ; bool Signed ; const TargetRegisterClass * FRC = HBS :: getFinalVRegClass ( RD , MRI ) ; if ( FRC != & <STR_LIT> && FRC != & <STR_LIT> ) return false ; assert ( RD . Sub == <NUM_LIT> ) ; const BitTracker :: BitValue & TopV = RC [ W - <NUM_LIT> ] ; bool IsConst = true ; for ( unsigned I = <NUM_LIT> ; I != W ; ++ I ) { const BitTracker :: BitValue & V = RC [ I ] ; if ( V . Type == BitTracker :: BitValue :: Ref && V . RefI . Reg == RD . Reg ) return false ; IsConst = IsConst && ( V . is ( <NUM_LIT> ) || V . is ( <NUM_LIT> ) ) ; } if ( IsConst ) return false ; if ( TopV . is ( <NUM_LIT> ) || TopV . is ( <NUM_LIT> ) ) { bool S = TopV . is ( <NUM_LIT> ) ; for ( -- W ; W > <NUM_LIT> && RC [ W - <NUM_LIT> ] . is ( S ) ; -- W ) ; Len = W ; Signed = S ; if ( Signed ) ++ Len ; } else { assert ( TopV . Type == BitTracker :: BitValue :: Ref ) ; if ( TopV . RefI . Reg == RD . Reg || TopV . RefI . Pos == W - <NUM_LIT> ) return false ; for ( -- W ; W > <NUM_LIT> && RC [ W - <NUM_LIT> ] == TopV ; -- W ) ; Len = W + <NUM_LIT> ; Signed = true ; } if ( Len == RW ) return false ; DEBUG ( { dbgs ( ) << __func__ << <STR_LIT> << printReg ( RD . Reg , & HRI , RD . Sub ) << <STR_LIT> << * MI ; dbgs ( ) << <STR_LIT> << RC << '\n' ; dbgs ( ) << <STR_LIT> << Len << <STR_LIT> << ( Signed ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> ; } ) ; bool Changed = false ; for ( unsigned R = AVs . find_first ( ) ; R != <NUM_LIT> ; R = AVs . find_next ( R ) ) { if ( ! BT . has ( R ) ) continue ; const BitTracker :: RegisterCell & SC = BT . lookup ( R ) ; unsigned SW = SC . width ( ) ; if ( SW < RW || ( SW % RW ) != <NUM_LIT> ) continue ; unsigned Off = <NUM_LIT> ;


<s> BitSimplification ( BitTracker & bt , const <ISA_LIT>InstrInfo & hii , const <ISA_LIT>RegisterInfo & hri , MachineRegisterInfo & mri , MachineFunction & mf ) : Transformation ( true ) , HII ( hii ) , HRI ( hri ) , MRI ( mri ) , MF ( mf ) , BT ( bt ) {


<s> bool <ISA_LIT>BitSimplify :: getSubregMask ( const BitTracker :: RegisterRef & RR , unsigned & Begin , unsigned & Width , MachineRegisterInfo & MRI ) { const TargetRegisterClass * RC = MRI . getRegClass ( RR . Reg ) ; if ( RR . Sub == <NUM_LIT> ) { Begin = <NUM_LIT> ; Width = RC -> getSize ( ) * <NUM_LIT> ; return true ; } Begin = <NUM_LIT> ; switch ( RC -> getID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :

Width = RC -> getSize ( ) * <NUM_LIT> / <NUM_LIT> ;


<s> return true ; } Begin = <NUM_LIT> ; switch ( RC -> getID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = RC -> getSize ( ) * <NUM_LIT> / <NUM_LIT> ; if ( RR . Sub == <STR_LIT> || RR . Sub == <STR_LIT> ) Begin = Width ; break ; default : return false ; } return true ;


<s> auto & HII = * HST . getInstrInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool Changed ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) ; const <ISA_LIT>Evaluator HE ( HRI , MRI , HII , MF ) ; BitTracker BT ( HE , MF ) ; DEBUG ( BT . trace ( true ) ) ; BT . run ( ) ; MachineBasicBlock & Entry = MF . front ( ) ; RegisterSet AIG ; ConstGeneration ImmG ( BT , HII , MRI ) ;

Changed |= visitBlock ( Entry , ImmG , AIG ) ;


<s> ConstGeneration ImmG ( BT , HII , MRI ) ; Changed |= visitBlock ( Entry , ImmG , AIG ) ; RegisterSet ARE ; RedundantInstrElimination RIE ( BT , HII , MRI ) ; bool Ried = visitBlock ( Entry , RIE , ARE ) ; if ( Ried ) { Changed = true ; BT . run ( ) ; } RegisterSet ACG ; CopyGeneration CopyG ( BT , HII , HRI , MRI ) ; Changed |= visitBlock ( Entry , CopyG , ACG ) ; RegisterSet ACP ; CopyPropagation CopyP ( HRI , MRI ) ; Changed |= visitBlock ( Entry , CopyP , ACP ) ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) || Changed ; BT . run ( ) ; RegisterSet ABS ; BitSimplification BitS ( BT , HII , HRI , MRI , MF ) ; Changed |= visitBlock ( Entry , BitS , ABS ) ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) || Changed ; if ( Changed ) { for ( auto & B : MF ) for ( auto & I : B ) I . clearKillInfo ( ) ; DeadCodeElimination ( MF , * MDT ) . run ( ) ; }


<s> return new <ISA_LIT>BitSimplify ( ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>LoopRescheduling ( ) { return new <ISA_LIT>LoopRescheduling ( ) ;


<s> V = int16_t ( U ) ; break ; case <STR_LIT> : V = int32_t ( U ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( ! isInt < <NUM_LIT> > ( V ) ) return false ; MI -> removeOperand ( <NUM_LIT> ) ; switch ( Opc ) { case <STR_LIT> : MI -> setDesc ( HII . get ( <STR_LIT> ) ) ; break ; case <STR_LIT> : MI -> setDesc ( HII . get ( <STR_LIT> ) ) ; break ; case <STR_LIT> : MI -> setDesc ( HII . get ( <STR_LIT> ) ) ; break ; }

MI -> addOperand ( MachineOperand :: CreateImm ( V ) ) ;


<s> switch ( Opc ) { case <STR_LIT> : V = int8_t ( U ) ; break ; case <STR_LIT> : V = int16_t ( U ) ; break ; case <STR_LIT> : V = int32_t ( U ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( ! isInt < <NUM_LIT> > ( V ) ) return false ; MI -> removeOperand ( <NUM_LIT> ) ; switch ( Opc ) { case <STR_LIT> : MI -> setDesc ( HII . get ( <STR_LIT> ) ) ; break ; case <STR_LIT> : MI -> setDesc ( HII . get ( <STR_LIT> ) ) ; break ; case <STR_LIT> : MI -> setDesc ( HII . get ( <STR_LIT> ) ) ; break ; }


<s> void <ISA_LIT>LoopRescheduling :: moveGroup ( InstrGroup & G , MachineBasicBlock & LB , MachineBasicBlock & PB , MachineBasicBlock :: iterator At , unsigned OldPhiR , unsigned NewPredR ) { DenseMap < unsigned , unsigned > RegMap ; const TargetRegisterClass * PhiRC = MRI -> getRegClass ( NewPredR ) ; Register PhiR = MRI -> createVirtualRegister ( PhiRC ) ; BuildMI ( LB , At , At -> getDebugLoc ( ) , HII -> get ( TargetOpcode :: PHI ) , PhiR ) . addReg ( NewPredR ) . addMBB ( & PB ) . addReg ( G . Inp . Reg ) . addMBB ( & LB ) ; RegMap . insert ( std :: make_pair ( G . Inp . Reg , PhiR ) ) ; for ( const MachineInstr * SI : llvm :: reverse ( G . Ins ) ) { unsigned DR = getDefReg ( SI ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( DR ) ; Register NewDR = MRI -> createVirtualRegister ( RC ) ; DebugLoc DL = SI -> getDebugLoc ( ) ; auto MIB = BuildMI ( LB , At , DL , HII -> get ( SI -> getOpcode ( ) ) , NewDR ) ; for ( unsigned j = <NUM_LIT> , m = SI -> getNumOperands ( ) ; j < m ; ++ j ) { const MachineOperand & Op = SI -> getOperand ( j ) ; if ( ! Op . isReg ( ) ) { MIB . add ( Op ) ;


<s> RegMap . insert ( std :: make_pair ( G . Inp . Reg , PhiR ) ) ; for ( const MachineInstr * SI : llvm :: reverse ( G . Ins ) ) { unsigned DR = getDefReg ( SI ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( DR ) ; Register NewDR = MRI -> createVirtualRegister ( RC ) ; DebugLoc DL = SI -> getDebugLoc ( ) ; auto MIB = BuildMI ( LB , At , DL , HII -> get ( SI -> getOpcode ( ) ) , NewDR ) ; for ( unsigned j = <NUM_LIT> , m = SI -> getNumOperands ( ) ; j < m ; ++ j ) { const MachineOperand & Op = SI -> getOperand ( j ) ; if ( ! Op . isReg ( ) ) { MIB . add ( Op ) ; continue ; } if ( ! Op . isUse ( ) ) continue ; unsigned UseR = RegMap [ Op . getReg ( ) ] ; MIB . addReg ( UseR , <NUM_LIT> , Op . getSubReg ( ) ) ; } RegMap . insert ( std :: make_pair ( DR , NewDR ) ) ;