<s> bool hasGAOpnd = false ; std :: vector < MachineOperand > tmpOpnds ; bool needShift = true ; if ( MI -> getNumOperands ( ) == <NUM_LIT> ) { needShift = false ; oper = - <NUM_LIT> ; } else if ( MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) . isDef ( ) && ! MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) . isImplicit ( ) ) { MI -> addOperand ( MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) ) ; needShift = false ; oper = MI -> getNumOperands ( ) - <NUM_LIT> ; } else { MI -> addOperand ( MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) ) ; } if ( needShift ) { for ( oper = MI -> getNumOperands ( ) - <NUM_LIT> ; oper >= <NUM_LIT> ; -- oper ) { MachineOperand & MO = MI -> getOperand ( oper ) ; if ( MO . isReg ( ) && ! MO . isUse ( ) && ! MO . isImplicit ( ) ) { break ; } if ( MO . isReg ( ) ) { MI -> getOperand ( oper + <NUM_LIT> ) . ChangeToRegister ( MO . getReg ( ) , MO . isDef ( ) , MO . isImplicit ( ) , MO . isKill ( ) , MO . isDead ( ) , MO . isUndef ( ) , MO . isDebug ( ) ) ; } else if ( MO . isImm ( ) ) { MI -> getOperand ( oper + <NUM_LIT> ) . ChangeToImmediate ( MO . getImm ( ) ) ; }


<s> unsigned AccessSize = <NUM_LIT> ; OffsetIsScalable = false ; const MachineOperand * BaseOp = getBaseAndOffset ( LdSt , Offset , AccessSize ) ;

if ( ! BaseOp || ! BaseOp -> isReg ( ) ) return false ;


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , SlotAlign ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) {


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) {


<s> unsigned AccessSize = <NUM_LIT> ; BaseOp = getBaseAndOffset ( LdSt , Offset , AccessSize ) ; return BaseOp != nullptr && BaseOp -> isReg ( ) ;


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) {


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else { llvm_unreachable ( <STR_LIT> ) ;


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned SlotAlign = MFI . getObjectAlignment ( FI ) ; unsigned KillFlag = getKillRegState ( isKill ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , SlotAlign ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ;


<s> if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg ) ; return ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { if ( SrcReg == RI . getSubReg ( DestReg , <STR_LIT> ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addReg ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addImm ( <NUM_LIT> ) ; } return ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return ;


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return QRI . Subtarget . hasV4TOps ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> } } MachineOperand UseMO = UseMI . getOperand ( UseIdx ) ; if ( UseMO . isImplicit ( ) ) { for ( MCSuperRegIterator SR ( UseMO . getReg ( ) , & HRI ) ; SR . isValid ( ) ; ++ SR ) { int Idx = UseMI . findRegisterUseOperandIdx ( * SR , false , & HRI ) ; if ( Idx != - <NUM_LIT> ) { UseIdx = Idx ; break ; } } } } return TargetInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ;


<s> switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> int <ISA_LIT>InstrInfo :: getNonDotCurOp ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } return <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand OpFI = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpFI . isFI ( ) ) return <NUM_LIT> ; const MachineOperand OpOff = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; }


<s> case <STR_LIT> : case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; } if ( Extend ) return true ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMW_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMW_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> :


<s> return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( HRI . getSubReg ( SrcReg , <STR_LIT> ) , KillFlag ) . addReg ( HRI . getSubReg ( SrcReg , <STR_LIT> ) , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { llvm_unreachable ( <STR_LIT> ) ; return ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { llvm_unreachable ( <STR_LIT> ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { unsigned DstHi = HRI . getSubReg ( DestReg , <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstHi ) . addReg ( HRI . getSubReg ( SrcReg , <STR_LIT> ) , KillFlag ) ; unsigned DstLo = HRI . getSubReg ( DestReg , <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstLo ) . addReg ( HRI . getSubReg ( SrcReg , <STR_LIT> ) , KillFlag ) ; return ;


<s> MachineInstr * SecondLastInst = nullptr ; for ( ; ; ) { if ( & * I != LastInst && ! I -> isBundle ( ) && isUnpredicatedTerminator ( & * I ) ) { if ( ! SecondLastInst ) SecondLastInst = & * I ; else return true ; } if ( I == MBB . instr_begin ( ) ) break ; -- I ; } int LastOpcode = LastInst -> getOpcode ( ) ; int SecLastOpcode = SecondLastInst ? SecondLastInst -> getOpcode ( ) : <NUM_LIT> ; if ( LastOpcode == <STR_LIT> && ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( SecLastOpcode == <STR_LIT> && ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( LastOpcode ) ; bool LastOpcodeHasNVJump = isNewValueJump ( LastInst ) ; if ( LastOpcodeHasJMP_c && ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( LastInst && ! SecondLastInst ) { if ( LastOpcode == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isEndLoopN ( LastOpcode ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOpcode ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastOpcodeHasJMP_c ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOpcode ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ;


<s> if ( SrcReg == RI . getSubReg ( DestReg , <STR_LIT> ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addReg ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addImm ( <NUM_LIT> ) ; } return ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( HRI . getSubReg ( SrcReg , <STR_LIT> ) , getKillRegState ( KillSrc ) ) . addReg ( HRI . getSubReg ( SrcReg , <STR_LIT> ) , getKillRegState ( KillSrc ) ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) {

BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> auto & HRI = getRegisterInfo ( ) ; for ( unsigned oper = <NUM_LIT> ; oper < MI -> getNumOperands ( ) ; ++ oper ) { MachineOperand MO = MI -> getOperand ( oper ) ; if ( MO . isReg ( ) && MO . isDef ( ) ) { const TargetRegisterClass * RC = HRI . getMinimalPhysRegClass ( MO . getReg ( ) ) ; if ( RC == & <STR_LIT> ) { Pred . push_back ( MO ) ; return true ;


<s> for ( unsigned oper = <NUM_LIT> ; oper < MI -> getNumOperands ( ) ; ++ oper ) { MachineOperand MO = MI -> getOperand ( oper ) ; if ( MO . isReg ( ) && MO . isDef ( ) ) { const TargetRegisterClass * RC = HRI . getMinimalPhysRegClass ( MO . getReg ( ) ) ;


<s> bool <ISA_LIT>InstrInfo :: getBaseAndOffsetPosition ( const MachineInstr * MI , unsigned & BasePos , unsigned & OffsetPos ) const { if ( isMemOp ( MI ) ) { assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; BasePos = <NUM_LIT> ; OffsetPos = <NUM_LIT> ; } else if ( MI -> mayStore ( ) ) { BasePos = <NUM_LIT> ; OffsetPos = <NUM_LIT> ; } else if ( MI -> mayLoad ( ) ) { BasePos = <NUM_LIT> ; OffsetPos = <NUM_LIT> ; } else return false ; if ( isPredicated ( MI ) ) { BasePos ++ ; OffsetPos ++ ; } if ( isPostIncrement ( MI ) ) { BasePos ++ ; OffsetPos ++ ; } if ( ! MI -> getOperand ( BasePos ) . isReg ( ) || ! MI -> getOperand ( OffsetPos ) . isImm ( ) ) return false ;


<s> SmallVector < MachineInstr * , <NUM_LIT> > <ISA_LIT>InstrInfo :: getBranchingInstrs ( MachineBasicBlock & MBB ) const { SmallVector < MachineInstr * , <NUM_LIT> > Jumpers ; MachineBasicBlock :: instr_iterator I = MBB . instr_end ( ) ; if ( I == MBB . instr_begin ( ) ) return Jumpers ; do { -- I ; if ( I -> isEHLabel ( ) ) return Jumpers ;

} while ( I != MBB . instr_begin ( ) ) ;


<s> assert ( ( TargetPos >= <NUM_LIT> ) && MI -> getOperand ( TargetPos ) . isMBB ( ) ) ; MI -> getOperand ( TargetPos ) . setMBB ( NewTarget ) ; if ( EnableBranchPrediction && isPredicatedNew ( MI ) ) { NewOpcode = reversePrediction ( NewOpcode ) ;


<s> return ( MI -> isBranch ( ) && isPredicated ( MI ) ) || isConditionalTransfer ( MI ) || isConditionalALU32 ( MI ) || isConditionalLoad ( MI ) || ( MI -> mayStore ( ) && isPredicated ( MI ) && ! isNewValueStore ( MI ) && ! isPredicatedNew ( MI ) ) ;


<s> bool <ISA_LIT>InstrInfo :: isConditionalLoad ( const MachineInstr * MI ) const {

if ( ! MI -> getDesc ( ) . mayLoad ( ) || ! isPredicated ( MI ) ) return false ;


<s> if ( isNewValueInst ( MI ) || ( isPredicated ( MI ) && isPredicatedNew ( MI ) ) ) return true ;


<s> case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( OpCExtended [ <NUM_LIT> ] || isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) && ( OpCExtended [ <NUM_LIT> ] || isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; case <STR_LIT> : return isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> :


<s> return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( OpCExtended [ <NUM_LIT> ] || isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) && ( OpCExtended [ <NUM_LIT> ] || isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; case <STR_LIT> :


<s> const uint64_t F = MI -> getDesc ( ) . TSFlags ; return ( F >> <STR_LIT> ) & <STR_LIT> ;


<s> const uint64_t F = MI -> getDesc ( ) . TSFlags ;


return ! ( ( F >> <STR_LIT> ) & <STR_LIT> ) ;


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else { llvm_unreachable ( <STR_LIT> ) ;


<s> unsigned <ISA_LIT>InstrInfo :: nonDbgBundleSize ( MachineBasicBlock :: const_iterator BundleHead ) const { assert ( BundleHead -> isBundle ( ) && <STR_LIT> ) ; auto MII = BundleHead . getInstrIterator ( ) ;

return nonDbgMICount ( ++ MII , getBundleEnd ( BundleHead ) ) ;


<s> unsigned PredOpc = getCondOpcode ( Opc , invertJump ) ; MachineInstrBuilder T = BuildMI ( B , MI , DL , get ( PredOpc ) ) ; unsigned NOp = <NUM_LIT> , NumOps = MI -> getNumOperands ( ) ; while ( NOp < NumOps ) { MachineOperand & Op = MI -> getOperand ( NOp ) ; if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . isImplicit ( ) ) break ; T . addOperand ( Op ) ; NOp ++ ; } unsigned PredReg , PredRegPos , PredRegFlags ; bool GotPredReg = getPredReg ( Cond , PredReg , PredRegPos , PredRegFlags ) ; ( void ) GotPredReg ;


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ;


<s> TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; if ( ( ( SecondLastInst -> getOpcode ( ) == <STR_LIT> ) || ( SecondLastInst -> getOpcode ( ) == <STR_LIT> ) ) && LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( ( SecondLastInst -> getOpcode ( ) == <STR_LIT> ) && LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecondLastInst -> getOpcode ( ) == <STR_LIT> && LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; }


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addReg ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addImm ( <NUM_LIT> ) ; } return ; }

if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) {


<s> return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ;


<s> case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> :


<s> unsigned <ISA_LIT>InstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , const SmallVectorImpl < MachineOperand > & Cond , DebugLoc DL ) const { int BOpc = <STR_LIT> ; int BccOpc = <STR_LIT> ; assert ( TBB && <STR_LIT> ) ; int regPos = <NUM_LIT> ; if ( ! Cond . empty ( ) && Cond [ <NUM_LIT> ] . isImm ( ) && Cond [ <NUM_LIT> ] . getImm ( ) == <NUM_LIT> ) { BccOpc = <STR_LIT> ; regPos = <NUM_LIT> ; } if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) { MachineBasicBlock * NewTBB , * NewFBB ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; MachineInstr * Term = MBB . getFirstTerminator ( ) ; if ( isPredicated ( Term ) && ! AnalyzeBranch ( MBB , NewTBB , NewFBB , Cond , false ) ) { MachineBasicBlock * NextBB = llvm :: next ( MachineFunction :: iterator ( & MBB ) ) ; if ( NewTBB == NextBB ) { ReverseBranchCondition ( Cond ) ; RemoveBranch ( MBB ) ; return InsertBranch ( MBB , TBB , <NUM_LIT> , Cond , DL ) ; } } BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else { BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ regPos ] . getReg ( ) ) . addMBB ( TBB ) ; } return <NUM_LIT> ; } BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ regPos ] . getReg ( ) ) . addMBB ( TBB ) ;

BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( FBB ) ;


<s> } if ( VT == <STR_LIT> ) { return ( Offset >= <ISA_LIT>_MEMH_AUTOINC_MIN && Offset <= <ISA_LIT>_MEMH_AUTOINC_MAX && ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ; } if ( VT == <STR_LIT> ) {

return ( Offset >= <ISA_LIT>_MEMB_AUTOINC_MIN && Offset <= <ISA_LIT>_MEMB_AUTOINC_MAX ) ;


<s> return ( Offset >= <ISA_LIT>_MEMD_AUTOINC_MIN && Offset <= <ISA_LIT>_MEMD_AUTOINC_MAX && ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ; } if ( VT == <STR_LIT> ) { return ( Offset >= <ISA_LIT>_MEMW_AUTOINC_MIN && Offset <= <ISA_LIT>_MEMW_AUTOINC_MAX && ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ; } if ( VT == <STR_LIT> ) { return ( Offset >= <ISA_LIT>_MEMH_AUTOINC_MIN && Offset <= <ISA_LIT>_MEMH_AUTOINC_MAX && ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ; } if ( VT == <STR_LIT> ) { return ( Offset >= <ISA_LIT>_MEMB_AUTOINC_MIN && Offset <= <ISA_LIT>_MEMB_AUTOINC_MAX ) ;


<s> case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> return ( Offset >= <ISA_LIT>_MEMW_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMW_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ;


<s> void <ISA_LIT>InstrInfo :: loadRegFromAddr ( MachineFunction & MF , unsigned DestReg , SmallVectorImpl < MachineOperand > & Addr , const TargetRegisterClass * RC , SmallVectorImpl < MachineInstr * > & NewMIs ) const { assert ( <NUM_LIT> && <STR_LIT> ) ;


<s> unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , Align ) ; if ( RC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == <STR_LIT> ) {


<s> MI -> getOperand ( oper + <NUM_LIT> ) . ChangeToRegister ( MO . getReg ( ) , MO . isDef ( ) , MO . isImplicit ( ) , MO . isKill ( ) , MO . isDead ( ) , MO . isUndef ( ) , MO . isDebug ( ) ) ; } else if ( MO . isImm ( ) ) { MI -> getOperand ( oper + <NUM_LIT> ) . ChangeToImmediate ( MO . getImm ( ) ) ; } else { assert ( false && <STR_LIT> ) ; } }

int regPos = invertJump ? <NUM_LIT> : <NUM_LIT> ;


<s> I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( I -> getOpcode ( ) != BccOpc && I -> getOpcode ( ) != BccOpcNot ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; return <NUM_LIT> ;


<s> void <ISA_LIT>InstrInfo :: storeRegToAddr ( MachineFunction & MF , unsigned SrcReg , bool isKill , SmallVectorImpl < MachineOperand > & Addr , const TargetRegisterClass * RC , SmallVectorImpl < MachineInstr * > & NewMIs ) const { assert ( <NUM_LIT> && <STR_LIT> ) ; return ;


<s> if ( <STR_LIT> -> hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> -> hasSubClassEq ( RC ) ) {


<s> bool LastOpcodeHasNVJump = isNewValueJump ( LastInst ) ; if ( LastOpcodeHasJMP_c && ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( LastInst && ! SecondLastInst ) { if ( LastOpcode == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isEndLoopN ( LastOpcode ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOpcode ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastOpcodeHasJMP_c ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOpcode ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastOpcodeHasNVJump && ( LastInst -> getNumExplicitOperands ( ) == <NUM_LIT> ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOpcode ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> ; ) ; return true ; } bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( SecLastOpcode ) ; bool SecLastOpcodeHasNVJump = isNewValueJump ( SecondLastInst ) ; if ( SecLastOpcodeHasJMP_c && ( LastOpcode == <STR_LIT> ) ) { if ( ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( SecondLastInst -> getOpcode ( ) ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecLastOpcodeHasNVJump && ( SecondLastInst -> getNumExplicitOperands ( ) == <NUM_LIT> ) && ( LastOpcode == <STR_LIT> ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( SecondLastInst -> getOpcode ( ) ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecLastOpcode == <STR_LIT> && LastOpcode == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst -> getIterator ( ) ;

if ( AllowModify ) I -> eraseFromParent ( ) ;


<s> int OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; unsigned SizeA = <NUM_LIT> , SizeB = <NUM_LIT> ; if ( MIa -> hasUnmodeledSideEffects ( ) || MIb -> hasUnmodeledSideEffects ( ) || MIa -> hasOrderedMemoryRef ( ) || MIa -> hasOrderedMemoryRef ( ) ) return false ; if ( MIa -> mayLoad ( ) && ! isMemOp ( MIa ) && MIb -> mayLoad ( ) && ! isMemOp ( MIb ) ) return true ; unsigned BaseRegA = getBaseAndOffset ( MIa , OffsetA , SizeA ) ; if ( ! BaseRegA || ! SizeA ) return false ; unsigned BaseRegB = getBaseAndOffset ( MIb , OffsetB , SizeB ) ; if ( ! BaseRegB || ! SizeB ) return false ; if ( BaseRegA != BaseRegB ) return false ; if ( OffsetA > OffsetB ) { uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetA - ( int64_t ) OffsetB ) ; return ( SizeB <= offDiff ) ; } else if ( OffsetA < OffsetB ) {

uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetB - ( int64_t ) OffsetA ) ;


<s> int OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; unsigned SizeA = <NUM_LIT> , SizeB = <NUM_LIT> ; if ( MIa -> hasUnmodeledSideEffects ( ) || MIb -> hasUnmodeledSideEffects ( ) || MIa -> hasOrderedMemoryRef ( ) || MIa -> hasOrderedMemoryRef ( ) ) return false ; if ( MIa -> mayLoad ( ) && ! isMemOp ( MIa ) && MIb -> mayLoad ( ) && ! isMemOp ( MIb ) ) return true ; unsigned BaseRegA = getBaseAndOffset ( MIa , OffsetA , SizeA ) ;

if ( ! BaseRegA || ! SizeA ) return false ;


<s> auto MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; for ( auto & Op : I -> operands ( ) ) if ( Op . isReg ( ) && Op . isKill ( ) && Op . isImplicit ( ) && Op . isUse ( ) ) MIB . addReg ( Op . getReg ( ) , RegState :: Kill | RegState :: Implicit ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ;


<s> return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( HRI . getSubReg ( SrcReg , <STR_LIT> ) , KillFlag ) . addReg ( HRI . getSubReg ( SrcReg , <STR_LIT> ) , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { llvm_unreachable ( <STR_LIT> ) ; return ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { llvm_unreachable ( <STR_LIT> ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { unsigned DstHi = HRI . getSubReg ( DestReg , <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstHi ) . addReg ( HRI . getSubReg ( SrcReg , <STR_LIT> ) , KillFlag ) ; unsigned DstLo = HRI . getSubReg ( DestReg , <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstLo ) . addReg ( HRI . getSubReg ( SrcReg , <STR_LIT> ) , KillFlag ) ; return ; } dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> << PrintReg ( DestReg , & HRI ) << <STR_LIT> << PrintReg ( SrcReg , & HRI ) << '\n' ;


<s> unsigned <ISA_LIT>InstrInfo :: getInstrLatency ( const InstrItineraryData * ItinData , const MachineInstr * MI , unsigned * PredCost ) const { return getInstrTimingClassLatency ( ItinData , MI ) ;


<s> unsigned Latency = ItinData -> getStageLatency ( MI -> getDesc ( ) . getSchedClass ( ) ) ; if ( ! EnableTimingClassLatency || MI -> getParent ( ) -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . useBSBScheduling ( ) ) if ( Latency > <NUM_LIT> ) Latency = <NUM_LIT> ;


<s> assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; const MachineOperand & RO = Cond [ <NUM_LIT> ] ; unsigned Flags = getUndefRegState ( RO . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( RO . getReg ( ) , Flags ) . addMBB ( TBB ) ; } return <NUM_LIT> ; } assert ( ( ! Cond . empty ( ) ) && <STR_LIT> ) ; assert ( ( ! isNewValueJump ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) && <STR_LIT> ) ; if ( isEndLoopN ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { int EndLoopOp = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( Cond [ <NUM_LIT> ] . isMBB ( ) ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( TBB , EndLoopOp , VisitedBBs ) ; assert ( Loop != <NUM_LIT> && <STR_LIT> ) ; Loop -> getOperand ( <NUM_LIT> ) . setMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( EndLoopOp ) ) . addMBB ( TBB ) ; } else { const MachineOperand & RO = Cond [ <NUM_LIT> ] ; unsigned Flags = getUndefRegState ( RO . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( RO . getReg ( ) , Flags ) . addMBB ( TBB ) ;


<s> unsigned Flags1 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) ; ) ; if ( Cond [ <NUM_LIT> ] . isReg ( ) ) { unsigned Flags2 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags2 ) . addMBB ( TBB ) ; } else if ( Cond [ <NUM_LIT> ] . isImm ( ) ) { BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addMBB ( TBB ) ; } else llvm_unreachable ( <STR_LIT> ) ; } else { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; const MachineOperand & RO = Cond [ <NUM_LIT> ] ; unsigned Flags = getUndefRegState ( RO . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( RO . getReg ( ) , Flags ) . addMBB ( TBB ) ; } return <NUM_LIT> ; } assert ( ( ! Cond . empty ( ) ) && <STR_LIT> ) ; assert ( ( ! isNewValueJump ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) && <STR_LIT> ) ; if ( isEndLoopN ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { int EndLoopOp = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( Cond [ <NUM_LIT> ] . isMBB ( ) ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( TBB , EndLoopOp , VisitedBBs ) ; assert ( Loop != <NUM_LIT> && <STR_LIT> ) ;

Loop -> getOperand ( <NUM_LIT> ) . setMBB ( TBB ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand OpFI = MI -> getOperand ( <NUM_LIT> ) ; if ( ! OpFI . isFI ( ) ) return <NUM_LIT> ; const MachineOperand OpOff = MI -> getOperand ( <NUM_LIT> ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; FrameIndex = OpFI . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand OpFI = MI -> getOperand ( <NUM_LIT> ) ; if ( ! OpFI . isFI ( ) ) return <NUM_LIT> ; const MachineOperand OpOff = MI -> getOperand ( <NUM_LIT> ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; FrameIndex = OpFI . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } } return <NUM_LIT> ;


<s> return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( OpCExtended [ <NUM_LIT> ] || isUInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) && ( OpCExtended [ <NUM_LIT> ] || isInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; case <STR_LIT> : return isInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>InstrInfo :: isSaveCalleeSavedRegsCall ( const MachineInstr * MI ) const {

return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ;


<s> if ( MI -> isCall ( ) ) { for ( auto I : MBB -> successors ( ) ) if ( I -> isEHPad ( ) ) return true ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) return true ; if ( MI -> getDesc ( ) . isTerminator ( ) || MI -> isPosition ( ) ) return true ;

if ( MI -> isInlineAsm ( ) && ! ScheduleInlineAsm ) return true ;


<s> for ( auto I : MBB -> successors ( ) ) if ( I -> isEHPad ( ) ) return true ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) return true ;

if ( MI -> getDesc ( ) . isTerminator ( ) || MI -> isPosition ( ) ) return true ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand & OpFI = MI -> getOperand ( <NUM_LIT> ) ; if ( ! OpFI . isFI ( ) ) return <NUM_LIT> ; const MachineOperand & OpOff = MI -> getOperand ( <NUM_LIT> ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; FrameIndex = OpFI . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } case <STR_LIT> :


<s> } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> OffsetPos = <NUM_LIT> ; } else return false ; if ( isPredicated ( * MI ) ) { BasePos ++ ; OffsetPos ++ ; } if ( isPostIncrement ( MI ) ) { BasePos ++ ; OffsetPos ++ ; } if ( ! MI -> getOperand ( BasePos ) . isReg ( ) || ! MI -> getOperand ( OffsetPos ) . isImm ( ) ) return false ; return true ;


if ( mayBeNewStore ( MI2 ) ) if ( MI2 -> getOpcode ( ) == <STR_LIT> ) if ( MI1 -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI2 -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI1 -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return true ;


<s> unsigned DstReg = MI1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int N = MI2 -> getNumOperands ( ) ; for ( int I = <NUM_LIT> ; I < N ; I ++ ) if ( MI2 -> getOperand ( I ) . isReg ( ) && DstReg == MI2 -> getOperand ( I ) . getReg ( ) ) return true ; }


<s> } case <STR_LIT> : { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src2Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1SubHi = TRI . getSubReg ( Src1Reg , <STR_LIT> ) ; unsigned Src1SubLo = TRI . getSubReg ( Src1Reg , <STR_LIT> ) ; unsigned Src2SubHi = TRI . getSubReg ( Src2Reg , <STR_LIT> ) ; unsigned Src2SubLo = TRI . getSubReg ( Src2Reg , <STR_LIT> ) ; BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , TRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg ( Src1SubHi ) . addReg ( Src2SubHi ) ; BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , TRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg ( Src1SubLo ) . addReg ( Src2SubLo ) ; MBB . erase ( MI ) ; MRI . clearKillFlags ( Src1SubHi ) ; MRI . clearKillFlags ( Src1SubLo ) ; MRI . clearKillFlags ( Src2SubHi ) ; MRI . clearKillFlags ( Src2SubLo ) ; return true ; } case <STR_LIT> : { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src2Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;

unsigned Src3Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> if ( Cond . empty ( ) ) return false ; assert ( Cond . size ( ) == <NUM_LIT> ) ; if ( isNewValueJump ( Cond [ <NUM_LIT> ] . getImm ( ) ) || Cond [ <NUM_LIT> ] . isMBB ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ;


<s> Opcode_t BccOpc = <STR_LIT> ; assert ( TBB && <STR_LIT> ) ; if ( ! Cond . empty ( ) && Cond [ <NUM_LIT> ] . isImm ( ) ) BccOpc = Cond [ <NUM_LIT> ] . getImm ( ) ; if ( ! FBB ) { if ( Cond . empty ( ) ) { MachineBasicBlock * NewTBB , * NewFBB ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; MachineInstr * Term = MBB . getFirstTerminator ( ) ; if ( Term != MBB . end ( ) && isPredicated ( Term ) && ! AnalyzeBranch ( MBB , NewTBB , NewFBB , Cond , false ) ) { MachineBasicBlock * NextBB = std :: next ( MachineFunction :: iterator ( & MBB ) ) ; if ( NewTBB == NextBB ) { ReverseBranchCondition ( Cond ) ; RemoveBranch ( MBB ) ; return InsertBranch ( MBB , TBB , nullptr , Cond , DL ) ; } } BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else if ( isEndLoopN ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { int EndLoopOp = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( Cond [ <NUM_LIT> ] . isMBB ( ) ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( TBB , EndLoopOp , VisitedBBs ) ; assert ( Loop != <NUM_LIT> && <STR_LIT> ) ; Loop -> getOperand ( <NUM_LIT> ) . setMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( EndLoopOp ) ) . addMBB ( TBB ) ;

} else if ( isNewValueJump ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) {


<s> case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMW_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMW_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :

return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ;


<s> return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return true ;


<s> bool GotPredReg = getPredReg ( Cond , PredReg , PredRegPos , PredRegFlags ) ; ( void ) GotPredReg ; assert ( GotPredReg ) ; T . addReg ( PredReg , PredRegFlags ) ; while ( NOp < NumOps ) T . addOperand ( MI -> getOperand ( NOp ++ ) ) ; MI -> setDesc ( get ( PredOpc ) ) ; while ( unsigned n = MI -> getNumOperands ( ) ) MI -> RemoveOperand ( n - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , n = T -> getNumOperands ( ) ; i < n ; ++ i ) MI -> addOperand ( T -> getOperand ( i ) ) ; MachineBasicBlock :: instr_iterator TI = & * T ;


<s> MachineInstrBuilder T = BuildMI ( B , MI , DL , get ( PredOpc ) ) ; unsigned NOp = <NUM_LIT> , NumOps = MI -> getNumOperands ( ) ; while ( NOp < NumOps ) { MachineOperand & Op = MI -> getOperand ( NOp ) ; if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . isImplicit ( ) ) break ; T . addOperand ( Op ) ; NOp ++ ; } unsigned PredReg , PredRegPos , PredRegFlags ; bool GotPredReg = getPredReg ( Cond , PredReg , PredRegPos , PredRegFlags ) ; ( void ) GotPredReg ; assert ( GotPredReg ) ; T . addReg ( PredReg , PredRegFlags ) ; while ( NOp < NumOps ) T . addOperand ( MI -> getOperand ( NOp ++ ) ) ; MI -> setDesc ( get ( PredOpc ) ) ; while ( unsigned n = MI -> getNumOperands ( ) ) MI -> RemoveOperand ( n - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , n = T -> getNumOperands ( ) ; i < n ; ++ i ) MI -> addOperand ( T -> getOperand ( i ) ) ; MachineBasicBlock :: instr_iterator TI = & * T ; B . erase ( TI ) ; MachineRegisterInfo & MRI = B . getParent ( ) -> getRegInfo ( ) ;


<s> if ( Cond . empty ( ) || ! isPredicated ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) return false ;

return ! isPredicatedTrue ( Cond [ <NUM_LIT> ] . getImm ( ) ) ;


<s> MachineInstr * <ISA_LIT>InstrInfo :: emitFrameIndexDebugValue ( MachineFunction & MF , int FrameIx , uint64_t Offset , const MDNode * MDPtr , DebugLoc DL ) const { MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( Offset ) . addMetadata ( MDPtr ) ;


<s> <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> :


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg ) ; return ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { if ( SrcReg == RI . getSubReg ( DestReg , <STR_LIT> ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addReg ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addImm ( <NUM_LIT> ) ; } return ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return ; } llvm_unreachable ( <STR_LIT> ) ;


<s> assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> :


<s> BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else if ( isEndLoopN ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { int EndLoopOp = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( Cond [ <NUM_LIT> ] . isMBB ( ) ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( TBB , EndLoopOp , VisitedBBs ) ; assert ( Loop != <NUM_LIT> && <STR_LIT> ) ; Loop -> getOperand ( <NUM_LIT> ) . setMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( EndLoopOp ) ) . addMBB ( TBB ) ; } else if ( isNewValueJump ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Flags1 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) ; ) ; if ( Cond [ <NUM_LIT> ] . isReg ( ) ) { unsigned Flags2 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags2 ) . addMBB ( TBB ) ; } else if ( Cond [ <NUM_LIT> ] . isImm ( ) ) {

BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addMBB ( TBB ) ;


<s> return TM -> getSubtarget < <ISA_LIT>GenSubtargetInfo > ( ) . createDFAPacketizer ( II ) ;


<s> unsigned BaseRegB = BaseB . getReg ( ) ; unsigned BaseSubB = BaseB . getSubReg ( ) ; if ( BaseRegA != BaseRegB || BaseSubA != BaseSubB ) return false ; unsigned SizeA = ( <NUM_LIT> << ( getMemAccessSize ( MIa ) - <NUM_LIT> ) ) ; unsigned SizeB = ( <NUM_LIT> << ( getMemAccessSize ( MIb ) - <NUM_LIT> ) ) ; const MachineOperand & OffA = MIa . getOperand ( OffsetPosA ) ; const MachineOperand & OffB = MIb . getOperand ( OffsetPosB ) ;

if ( ! MIa . getOperand ( OffsetPosA ) . isImm ( ) || ! MIb . getOperand ( OffsetPosB ) . isImm ( ) ) return false ;


<s> if ( getAddrMode ( MI ) != <STR_LIT> && getAddrMode ( MI ) != <STR_LIT> && ! isMemOp ( MI ) && ! isPostIncrement ( MI ) ) return <NUM_LIT> ; assert ( getMemAccessSize ( MI ) && <STR_LIT> ) ; AccessSize = ( <NUM_LIT> << ( getMemAccessSize ( MI ) - <NUM_LIT> ) ) ; unsigned BasePos = <NUM_LIT> , OffsetPos = <NUM_LIT> ; if ( ! getBaseAndOffsetPosition ( MI , BasePos , OffsetPos ) ) return <NUM_LIT> ; if ( isPostIncrement ( MI ) ) {


<s> AccessSize = ( <NUM_LIT> << ( getMemAccessSize ( MI ) - <NUM_LIT> ) ) ; unsigned BasePos = <NUM_LIT> , OffsetPos = <NUM_LIT> ; if ( ! getBaseAndOffsetPosition ( MI , BasePos , OffsetPos ) ) return <NUM_LIT> ; if ( isPostIncrement ( MI ) ) { Offset = <NUM_LIT> ; } else {

const MachineOperand & OffsetOp = MI . getOperand ( OffsetPos ) ;


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else { llvm_unreachable ( <STR_LIT> ) ; }


<s> MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , Align ) ; if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) {

BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ;


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) {


<s> if ( OffsetA > OffsetB ) { uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetA - ( int64_t ) OffsetB ) ; return ( SizeB <= offDiff ) ; } else if ( OffsetA < OffsetB ) { uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetB - ( int64_t ) OffsetA ) ; return ( SizeA <= offDiff ) ;


<s> if ( ! BaseRegB || ! SizeB ) return false ; if ( BaseRegA != BaseRegB ) return false ; if ( OffsetA > OffsetB ) { uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetA - ( int64_t ) OffsetB ) ; return ( SizeB <= offDiff ) ; } else if ( OffsetA < OffsetB ) {


<s> if ( ! Cond . empty ( ) && Cond [ <NUM_LIT> ] . isImm ( ) ) BccOpc = Cond [ <NUM_LIT> ] . getImm ( ) ; if ( ! FBB ) { if ( Cond . empty ( ) ) { MachineBasicBlock * NewTBB , * NewFBB ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; MachineInstr * Term = MBB . getFirstTerminator ( ) ; if ( Term != MBB . end ( ) && isPredicated ( * Term ) && ! AnalyzeBranch ( MBB , NewTBB , NewFBB , Cond , false ) ) { MachineBasicBlock * NextBB = & * ++ MBB . getIterator ( ) ; if ( NewTBB == NextBB ) { ReverseBranchCondition ( Cond ) ; RemoveBranch ( MBB ) ; return InsertBranch ( MBB , TBB , nullptr , Cond , DL ) ; } } BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else if ( isEndLoopN ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { int EndLoopOp = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( Cond [ <NUM_LIT> ] . isMBB ( ) ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( TBB , EndLoopOp , VisitedBBs ) ; assert ( Loop != <NUM_LIT> && <STR_LIT> ) ; Loop -> getOperand ( <NUM_LIT> ) . setMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( EndLoopOp ) ) . addMBB ( TBB ) ; } else if ( isNewValueJump ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Flags1 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) ; ) ; if ( Cond [ <NUM_LIT> ] . isReg ( ) ) { unsigned Flags2 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags2 ) . addMBB ( TBB ) ; } else if ( Cond [ <NUM_LIT> ] . isImm ( ) ) { BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addMBB ( TBB ) ;


<s> ReverseBranchCondition ( Cond ) ; RemoveBranch ( MBB ) ; return InsertBranch ( MBB , TBB , nullptr , Cond , DL ) ; } } BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else if ( isEndLoopN ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { int EndLoopOp = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( Cond [ <NUM_LIT> ] . isMBB ( ) ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( TBB , EndLoopOp , VisitedBBs ) ; assert ( Loop != <NUM_LIT> && <STR_LIT> ) ; Loop -> getOperand ( <NUM_LIT> ) . setMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( EndLoopOp ) ) . addMBB ( TBB ) ; } else if ( isNewValueJump ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Flags1 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) ; ) ; if ( Cond [ <NUM_LIT> ] . isReg ( ) ) { unsigned Flags2 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags2 ) . addMBB ( TBB ) ; } else if ( Cond [ <NUM_LIT> ] . isImm ( ) ) { BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addMBB ( TBB ) ; } else llvm_unreachable ( <STR_LIT> ) ; } else { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; const MachineOperand & RO = Cond [ <NUM_LIT> ] ; unsigned Flags = getUndefRegState ( RO . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( RO . getReg ( ) , Flags ) . addMBB ( TBB ) ; } return <NUM_LIT> ;


<s> int NVOpcode = <STR_LIT> ( MI -> getOpcode ( ) ) ; if ( NVOpcode >= <NUM_LIT> ) return NVOpcode ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } return <NUM_LIT> ;


<s> return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : return true ; } llvm_unreachable ( <STR_LIT> <STR_LIT> ) ;


<s> switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMW_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMW_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : return true ; } llvm_unreachable ( <STR_LIT> <STR_LIT> ) ;


<s> if ( ! BaseOp || ! BaseOp -> isReg ( ) ) return false ; BaseOps . push_back ( BaseOp ) ;


<s> const MachineOperand * BaseOp = getBaseAndOffset ( LdSt , Offset , AccessSize ) ; if ( ! BaseOp || ! BaseOp -> isReg ( ) ) return false ; BaseOps . push_back ( BaseOp ) ;


<s> return false ; } if ( LastOpcodeHasJMP_c ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOpcode ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastOpcodeHasNVJump && ( LastInst -> getNumExplicitOperands ( ) == <NUM_LIT> ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOpcode ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> ; ) ; return true ; } bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( SecLastOpcode ) ; bool SecLastOpcodeHasNVJump = isNewValueJump ( SecondLastInst ) ; if ( SecLastOpcodeHasJMP_c && ( LastOpcode == <STR_LIT> ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( SecondLastInst -> getOpcode ( ) ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecLastOpcodeHasNVJump && ( SecondLastInst -> getNumExplicitOperands ( ) == <NUM_LIT> ) && ( LastOpcode == <STR_LIT> ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( SecondLastInst -> getOpcode ( ) ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecLastOpcode == <STR_LIT> && LastOpcode == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } if ( isEndLoopN ( SecLastOpcode ) && LastOpcode == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( SecondLastInst -> getOpcode ( ) ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> ; ) ; return true ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = ~ <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = <NUM_LIT> ; break ; } switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg ) ; return ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) {

if ( SrcReg == RI . getSubReg ( DestReg , <STR_LIT> ) ) {


<s> TRC = & <STR_LIT> ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { TRC = & <STR_LIT> ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { TRC = & <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; }

unsigned NewReg = RegInfo . createVirtualRegister ( TRC ) ;


<s> TRC = & <STR_LIT> ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { TRC = & <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } unsigned NewReg = RegInfo . createVirtualRegister ( TRC ) ; return NewReg ;


<s> for ( unsigned oper = <NUM_LIT> ; oper < MI -> getNumOperands ( ) ; ++ oper ) { MachineOperand MO = MI -> getOperand ( oper ) ; if ( MO . isReg ( ) && MO . isDef ( ) ) { const TargetRegisterClass * RC = RI . getMinimalPhysRegClass ( MO . getReg ( ) ) ; if ( RC == & <STR_LIT> ) { Pred . push_back ( MO ) ;


<s> const <ISA_LIT>RegisterInfo & HRI = getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( HRI . getFrameRegister ( ) ) . addImm ( - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; MBB . erase ( MI ) ; return true ; case <STR_LIT> : { unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; MBB . erase ( MI ) ; return true ; } case <STR_LIT> : { unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; MBB . erase ( MI ) ; return true ; } case <STR_LIT> : { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src2Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1SubHi = HRI . getSubReg ( Src1Reg , <STR_LIT> ) ; unsigned Src1SubLo = HRI . getSubReg ( Src1Reg , <STR_LIT> ) ; unsigned Src2SubHi = HRI . getSubReg ( Src2Reg , <STR_LIT> ) ; unsigned Src2SubLo = HRI . getSubReg ( Src2Reg , <STR_LIT> ) ; BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , HRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg ( Src1SubHi ) . addReg ( Src2SubHi ) ; BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , HRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg ( Src1SubLo ) . addReg ( Src2SubLo ) ; MBB . erase ( MI ) ; MRI . clearKillFlags ( Src1SubHi ) ; MRI . clearKillFlags ( Src1SubLo ) ; MRI . clearKillFlags ( Src2SubHi ) ; MRI . clearKillFlags ( Src2SubLo ) ; return true ; } case <STR_LIT> : { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> if ( ! Visited . insert ( * PB ) . second ) continue ; if ( * PB == BB ) continue ; for ( MachineBasicBlock :: reverse_instr_iterator I = ( * PB ) -> instr_rbegin ( ) , E = ( * PB ) -> instr_rend ( ) ; I != E ; ++ I ) { int Opc = I -> getOpcode ( ) ; if ( Opc == LOOPi || Opc == LOOPr ) return & * I ; if ( Opc == EndLoopOp ) return <NUM_LIT> ; } MachineInstr * loop = findLoopInstr ( * PB , EndLoopOp , Visited ) ; if ( loop ) return loop ; } return <NUM_LIT> ;


<s> MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const override {


<s> unsigned short <ISA_LIT>InstrInfo :: getCExtOpNum ( const MachineInstr * MI ) const {

const uint64_t F = MI -> getDesc ( ) . TSFlags ;


<s> enum <STR_LIT> inPredSense ; inPredSense = invertPredicate ? <STR_LIT> : <STR_LIT> ; int CondOpcode = <STR_LIT> ( Opc , inPredSense ) ; if ( CondOpcode >= <NUM_LIT> ) return CondOpcode ; switch ( Opc ) { case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> :


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; }


<s> MachineBasicBlock * Dst = BrTarget -> getMBB ( ) ; const BranchProbability Prediction = MBPI -> getEdgeProbability ( Src , Dst ) ; if ( Prediction >= BranchProbability ( <NUM_LIT> , <NUM_LIT> ) ) taken = true ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : return taken ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return taken ? <STR_LIT> : <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> MachineBasicBlock * Dst = BrTarget -> getMBB ( ) ; const BranchProbability Prediction = MBPI -> getEdgeProbability ( Src , Dst ) ; if ( Prediction >= BranchProbability ( <NUM_LIT> , <NUM_LIT> ) ) taken = true ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> :


<s> if ( NewOpcode >= <NUM_LIT> ) return NewOpcode ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return getDotNewPredJumpOp ( MI , MBPI ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> } if ( isNewValueStore ( NewOp ) ) { NewOp = <STR_LIT> ( NewOp ) ;

assert ( NewOp >= <NUM_LIT> && <STR_LIT> ) ;


<s> } if ( isNewValueStore ( NewOp ) ) { NewOp = <STR_LIT> ( NewOp ) ; assert ( NewOp >= <NUM_LIT> && <STR_LIT> ) ; }


<s> InvPredOpcode = isPredicatedTrue ( Opc ) ? <STR_LIT> ( Opc ) : <STR_LIT> ( Opc ) ; if ( InvPredOpcode >= <NUM_LIT> ) return InvPredOpcode ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> InvPredOpcode = isPredicatedTrue ( Opc ) ? <STR_LIT> ( Opc ) : <STR_LIT> ( Opc ) ; if ( InvPredOpcode >= <NUM_LIT> ) return InvPredOpcode ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> if ( NonExtOpcode >= <NUM_LIT> ) return NonExtOpcode ; if ( MI -> getDesc ( ) . mayLoad ( ) || MI -> getDesc ( ) . mayStore ( ) ) { switch ( getAddrMode ( MI ) ) { case <STR_LIT> : return <STR_LIT> ( MI -> getOpcode ( ) ) ; case <STR_LIT> : return <STR_LIT> ( MI -> getOpcode ( ) ) ; default : return - <NUM_LIT> ; }


<s> if ( MI -> isDebugValue ( ) || MI -> isPosition ( ) ) return <NUM_LIT> ; unsigned Size = MI -> getDesc ( ) . getSize ( ) ; if ( ! Size ) Size = HEXAGON_INSTR_SIZE ; if ( isConstExtended ( MI ) || isExtended ( MI ) ) Size += HEXAGON_INSTR_SIZE ; return Size ;


<s> if ( MI -> isDebugValue ( ) || MI -> isPosition ( ) ) return <NUM_LIT> ; unsigned Size = MI -> getDesc ( ) . getSize ( ) ;

if ( ! Size ) Size = HEXAGON_INSTR_SIZE ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & ST ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ) , Subtarget ( ST ) {


<s> return MI -> getDesc ( ) . isBranch ( ) ;


<s> isConditionalLoad ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>InstrInfo :: isConditionalStore ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>InstrInfo :: isConditionalTransfer ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) {


<s> unsigned isExtendable = ( F >> <STR_LIT> ) & <STR_LIT> ; if ( ! isExtendable ) return false ; short ExtOpNum = getCExtOpNum ( MI ) ; const MachineOperand & MO = MI -> getOperand ( ExtOpNum ) ; if ( MO . getTargetFlags ( ) && <STR_LIT> ) return true ; if ( MO . isMBB ( ) ) return false ; if ( MO . isGlobal ( ) || MO . isSymbol ( ) || MO . isBlockAddress ( ) || MO . isJTI ( ) || MO . isCPI ( ) ) return true ;

assert ( MO . isImm ( ) && <STR_LIT> ) ;


<s> return ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ;


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :

if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) {


<s> bool <ISA_LIT>InstrInfo :: isNewValue ( Opcode_t Opcode ) const {

const uint64_t F = get ( Opcode ) . TSFlags ;


<s> return ( ( F >> <STR_LIT> ) & <STR_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: isNewValueInst ( const MachineInstr * MI ) const { if ( isNewValueJump ( MI ) ) return true ; if ( isNewValueStore ( MI ) ) return true ;


<s> if ( isNewValueStore ( MI ) ) return true ;


<s> bool <ISA_LIT>InstrInfo :: isNewValueJump ( Opcode_t Opcode ) const { return isNewValue ( Opcode ) && get ( Opcode ) . isBranch ( ) && isPredicated ( Opcode ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ;


<s> const uint64_t F = get ( Opcode ) . TSFlags ;

return ( ( F >> <STR_LIT> ) & <STR_LIT> ) ;


<s> const uint64_t F = get ( Opcode ) . TSFlags ; return ( ( F >> <STR_LIT> ) & <STR_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: isOperandExtended ( const MachineInstr * MI , unsigned short OperandNum ) const {


<s> bool <ISA_LIT>InstrInfo :: isPostIncrement ( const MachineInstr * MI ) const {

return ( getAddrMode ( MI ) == <STR_LIT> ) ;


<s> return ( getAddrMode ( MI ) == <STR_LIT> ) ;


<s> case <STR_LIT> : return isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> bool <ISA_LIT>InstrInfo :: isPredicated ( unsigned Opcode ) const { const uint64_t F = get ( Opcode ) . TSFlags ; return ( ( F >> <STR_LIT> ) & <STR_LIT> ) ;


<s> assert ( isPredicated ( Opcode ) ) ; return ( ( F >> <STR_LIT> ) & <STR_LIT> ) ;


<s> const uint64_t F = get ( Opcode ) . TSFlags ; assert ( ( F >> <STR_LIT> ) & <STR_LIT> ) ; return ( ! ( ( F >> <STR_LIT> ) & <STR_LIT> ) ) ;


<s> bool <ISA_LIT>InstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumTCycles , unsigned ExtraTCycles , MachineBasicBlock & FMBB , unsigned NumFCycles , unsigned ExtraFCycles , BranchProbability Probability ) const { return true ;