<s> assert ( Loop -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned LoopCount = Loop -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LoopEnd = createVR ( MF , <STR_LIT> ) ; MachineInstr * NewCmp = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , LoopEnd ) . addReg ( LoopCount ) . addImm ( <NUM_LIT> ) ; unsigned NewLoopCount = createVR ( MF , <STR_LIT> ) ; MachineInstr * NewAdd = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , NewLoopCount ) . addReg ( LoopCount ) . addImm ( - <NUM_LIT> ) ; for ( SmallVectorImpl < MachineInstr * > :: iterator I = PrevInsts . begin ( ) , E = PrevInsts . end ( ) ; I != E ; ++ I ) ( * I ) -> substituteRegister ( LoopCount , NewLoopCount , <NUM_LIT> , getRegisterInfo ( ) ) ;


<s> while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! I -> isBranch ( ) ) return Count ; if ( Count && ( I -> getOpcode ( ) == <STR_LIT> ) ) llvm_unreachable ( <STR_LIT> ) ; MBB . erase ( & MBB . back ( ) ) ; I = MBB . end ( ) ;


<s> bool <ISA_LIT>InstrInfo :: ReverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { if ( Cond . empty ( ) ) return true ; assert ( Cond [ <NUM_LIT> ] . isImm ( ) && <STR_LIT> ) ; unsigned opcode = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( get ( opcode ) . isBranch ( ) && <STR_LIT> ) ; if ( isEndLoopN ( opcode ) ) return true ; unsigned NewOpcode = getInvertedPredicatedOpcode ( opcode ) ;

Cond [ <NUM_LIT> ] . setImm ( NewOpcode ) ;


<s> unsigned <ISA_LIT>InstrInfo :: reversePrediction ( unsigned Opcode ) const { int PredRevOpcode = - <NUM_LIT> ; if ( isPredictedTaken ( Opcode ) ) PredRevOpcode = <STR_LIT> ( Opcode ) ; else PredRevOpcode = <STR_LIT> ( Opcode ) ; assert ( PredRevOpcode > <NUM_LIT> ) ;


<s> MI -> setDesc ( get ( getInvertedPredicatedOpcode ( MI -> getOpcode ( ) ) ) ) ; return true ;


<s> unsigned Align = MFI . getObjectAlignment ( FI ) ; unsigned KillFlag = getKillRegState ( isKill ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> if ( ! BaseRegB || ! SizeB ) return false ; if ( BaseRegA != BaseRegB ) return false ; if ( OffsetA > OffsetB ) { uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetA - ( int64_t ) OffsetB ) ; return ( SizeB <= offDiff ) ; } else if ( OffsetA < OffsetB ) {

uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetB - ( int64_t ) OffsetA ) ;


<s> unsigned BaseRegB = getBaseAndOffset ( MIb , OffsetB , SizeB ) ; if ( ! BaseRegB || ! SizeB ) return false ; if ( BaseRegA != BaseRegB ) return false ; if ( OffsetA > OffsetB ) { uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetA - ( int64_t ) OffsetB ) ; return ( SizeB <= offDiff ) ; } else if ( OffsetA < OffsetB ) { uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetB - ( int64_t ) OffsetA ) ; return ( SizeA <= offDiff ) ; }


<s> } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { unsigned LoSrc = HRI . getSubReg ( SrcReg , <STR_LIT> ) ; unsigned HiSrc = HRI . getSubReg ( SrcReg , <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( HiSrc , KillFlag ) . addReg ( LoSrc , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) {


<s> ScheduleHazardRecognizer * <ISA_LIT>InstrInfo :: CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAG * DAG ) const { if ( UseDFAHazardRec ) { auto & HST = DAG -> MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

return new <ISA_LIT>HazardRecognizer ( II , this , HST ) ;


<s> if ( UseDFAHazardRec ) { auto & HST = DAG -> MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; return new <ISA_LIT>HazardRecognizer ( II , this , HST ) ; }

return TargetInstrInfo :: CreateTargetPostRAHazardRecognizer ( II , DAG ) ;


<s> const TargetRegisterClass * RC = HRI . getMinimalPhysRegClass ( MO . getReg ( ) ) ; if ( RC == & <STR_LIT> ) { Pred . push_back ( MO ) ; return true ; } continue ; } else if ( MO . isRegMask ( ) ) { for ( unsigned PR : <STR_LIT> ) { if ( ! MI . modifiesRegister ( PR , & HRI ) ) continue ; Pred . push_back ( MO ) ; return true ;


<s> for ( MachineBasicBlock * PB : BB -> predecessors ( ) ) { if ( ! Visited . insert ( PB ) . second ) continue ; if ( PB == BB ) continue ; for ( auto I = PB -> instr_rbegin ( ) , E = PB -> instr_rend ( ) ; I != E ; ++ I ) { unsigned Opc = I -> getOpcode ( ) ; if ( Opc == LOOPi || Opc == LOOPr ) return & * I ; if ( Opc == EndLoopOp && I -> getOperand ( <NUM_LIT> ) . getMBB ( ) != TargetBB ) return nullptr ; } if ( MachineInstr * Loop = findLoopInstr ( PB , EndLoopOp , TargetBB , Visited ) ) return Loop ; } return nullptr ;


<s> if ( PB == BB ) continue ; for ( auto I = PB -> instr_rbegin ( ) , E = PB -> instr_rend ( ) ; I != E ; ++ I ) { unsigned Opc = I -> getOpcode ( ) ; if ( Opc == LOOPi || Opc == LOOPr ) return & * I ; if ( Opc == EndLoopOp && I -> getOperand ( <NUM_LIT> ) . getMBB ( ) != TargetBB ) return nullptr ; } if ( MachineInstr * Loop = findLoopInstr ( PB , EndLoopOp , TargetBB , Visited ) ) return Loop ;


<s> void <ISA_LIT>InstrInfo :: genAllInsnTimingClasses ( MachineFunction & MF ) const { MachineFunction :: iterator A = MF . begin ( ) ; MachineBasicBlock & B = * A ; MachineBasicBlock :: iterator I = B . begin ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; MachineInstr * NewMI ; for ( unsigned insn = TargetOpcode :: GENERIC_OP_END + <NUM_LIT> ; insn < <STR_LIT> ; ++ insn ) { NewMI = BuildMI ( B , I , DL , get ( insn ) ) ;

DEBUG ( dbgs ( ) << <STR_LIT> << getName ( NewMI -> getOpcode ( ) ) << <STR_LIT> << NewMI -> getDesc ( ) . getSchedClass ( ) ) ;


<s> return <STR_LIT> ( MI . getOpcode ( ) ) ;


<s> short <ISA_LIT>InstrInfo :: getAbsoluteForm ( const MachineInstr & MI ) const { return <STR_LIT> ( MI . getOpcode ( ) ) ;


<s> assert ( getMemAccessSize ( MI ) && <STR_LIT> ) ; AccessSize = ( <NUM_LIT> << ( getMemAccessSize ( MI ) - <NUM_LIT> ) ) ; unsigned basePos = <NUM_LIT> , offsetPos = <NUM_LIT> ; if ( ! getBaseAndOffsetPosition ( MI , basePos , offsetPos ) ) return <NUM_LIT> ; if ( isPostIncrement ( MI ) ) Offset = <NUM_LIT> ; else { Offset = MI . getOperand ( offsetPos ) . getImm ( ) ; }

return MI . getOperand ( basePos ) . getReg ( ) ;


<s> if ( getAddrMode ( MI ) != <STR_LIT> && getAddrMode ( MI ) != <STR_LIT> && ! isMemOp ( MI ) && ! isPostIncrement ( MI ) ) return <NUM_LIT> ; assert ( getMemAccessSize ( MI ) && <STR_LIT> ) ; AccessSize = ( <NUM_LIT> << ( getMemAccessSize ( MI ) - <NUM_LIT> ) ) ; unsigned basePos = <NUM_LIT> , offsetPos = <NUM_LIT> ;

if ( ! getBaseAndOffsetPosition ( MI , basePos , offsetPos ) ) return <NUM_LIT> ;


<s> } else if ( MI . mayStore ( ) ) { BasePos = <NUM_LIT> ; OffsetPos = <NUM_LIT> ; } else if ( MI . mayLoad ( ) ) { BasePos = <NUM_LIT> ; OffsetPos = <NUM_LIT> ; } else return false ; if ( isPredicated ( MI ) ) { BasePos ++ ; OffsetPos ++ ; } if ( isPostIncrement ( MI ) ) { BasePos ++ ; OffsetPos ++ ; } if ( ! MI . getOperand ( BasePos ) . isReg ( ) || ! MI . getOperand ( OffsetPos ) . isImm ( ) ) return false ; return true ;


<s> bool <ISA_LIT>InstrInfo :: getBaseAndOffsetPosition ( const MachineInstr & MI , unsigned & BasePos , unsigned & OffsetPos ) const { if ( isMemOp ( MI ) ) { BasePos = <NUM_LIT> ; OffsetPos = <NUM_LIT> ; } else if ( MI . mayStore ( ) ) { BasePos = <NUM_LIT> ;


<s> short <ISA_LIT>InstrInfo :: getBaseWithLongOffset ( const MachineInstr & MI ) const {

return <STR_LIT> ( MI . getOpcode ( ) ) ;


<s> short <ISA_LIT>InstrInfo :: getBaseWithRegOffset ( const MachineInstr & MI ) const {


<s> return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Src1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Src2Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( DstReg ) && ( <STR_LIT> == DstReg || <STR_LIT> == DstReg ) && isIntRegForSubInst ( Src1Reg ) && isIntRegForSubInst ( Src2Reg ) ) return <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( DstReg ) && ( <STR_LIT> == DstReg || <STR_LIT> == DstReg ) && isIntRegForSubInst ( SrcReg ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && ( ( isUInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) || ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == - <NUM_LIT> ) ) ) return <STR_LIT> ; break ; case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isIntRegForSubInst ( DstReg ) && isIntRegForSubInst ( SrcReg ) ) return <STR_LIT> ; break ; case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isIntRegForSubInst ( DstReg ) ) return <STR_LIT> ; break ; case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Src1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( DstReg ) && ( <STR_LIT> == DstReg || <STR_LIT> == DstReg ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && isIntRegForSubInst ( Src1Reg ) && ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) return <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Src1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( Src1Reg ) && ( <STR_LIT> == Src1Reg || <STR_LIT> == Src1Reg ) ) return <STR_LIT> ;


<s> SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isIntRegForSubInst ( DstReg ) && isIntRegForSubInst ( SrcReg ) ) return <STR_LIT> ; break ; case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isIntRegForSubInst ( DstReg ) ) return <STR_LIT> ; break ; case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Src1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( DstReg ) && ( <STR_LIT> == DstReg || <STR_LIT> == DstReg ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && isIntRegForSubInst ( Src1Reg ) && ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) return <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Src1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;

if ( <STR_LIT> . contains ( Src1Reg ) && ( <STR_LIT> == Src1Reg || <STR_LIT> == Src1Reg ) ) return <STR_LIT> ;


<s> unsigned DestReg = GA . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! GB . readsRegister ( DestReg ) ) return - <NUM_LIT> ; if ( DestReg == <STR_LIT> ) return <STR_LIT> ; if ( DestReg == <STR_LIT> ) return <STR_LIT> ; return - <NUM_LIT> ;


<s> if ( NVOpcode >= <NUM_LIT> ) return NVOpcode ; switch ( MI . getOpcode ( ) ) { default : llvm :: report_fatal_error ( std :: string ( <STR_LIT> ) + std :: to_string ( MI . getOpcode ( ) ) . c_str ( ) ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> default : llvm :: report_fatal_error ( std :: string ( <STR_LIT> ) + std :: to_string ( MI . getOpcode ( ) ) . c_str ( ) ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> case <STR_LIT> : NewOp = <STR_LIT> ; break ; case <STR_LIT> : NewOp = <STR_LIT> ; break ; } } assert ( NewOp >= <NUM_LIT> && <STR_LIT> ) ; } if ( isNewValueStore ( NewOp ) ) { NewOp = <STR_LIT> ( NewOp ) ; assert ( NewOp >= <NUM_LIT> && <STR_LIT> ) ; } if ( HST . hasV60TOps ( ) ) return NewOp ; switch ( NewOp ) { case <STR_LIT> :


<s> bool <ISA_LIT>InstrInfo :: getIncrementValue ( const MachineInstr & MI , int & Value ) const { if ( isPostIncrement ( MI ) ) { unsigned AccessSize ; return getBaseAndOffset ( MI , Value , AccessSize ) ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { Value = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; }


<s> unsigned <ISA_LIT>InstrInfo :: getMemAccessSize ( const MachineInstr & MI ) const { const uint64_t F = MI . getDesc ( ) . TSFlags ; return ( F >> <STR_LIT> ) & <STR_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: getMemOpBaseRegImmOfs ( MachineInstr & LdSt , unsigned & BaseReg , int64_t & Offset , const TargetRegisterInfo * TRI ) const {


<s> if ( MI . getDesc ( ) . mayLoad ( ) || MI . getDesc ( ) . mayStore ( ) ) { switch ( getAddrMode ( MI ) ) { case <STR_LIT> : return <STR_LIT> ( MI . getOpcode ( ) ) ; case <STR_LIT> : return <STR_LIT> ( MI . getOpcode ( ) ) ; case <STR_LIT> :


<s> return <STR_LIT> ( MI . getOpcode ( ) ) ; case <STR_LIT> : return <STR_LIT> ( MI . getOpcode ( ) ) ; case <STR_LIT> : return <STR_LIT> ( MI . getOpcode ( ) ) ; default : return - <NUM_LIT> ;


<s> int Idx = DefMI . findRegisterDefOperandIdx ( * SR , false , false , & RI ) ; if ( Idx != - <NUM_LIT> ) { DefIdx = Idx ; break ; } } } MachineOperand UseMO = UseMI . getOperand ( UseIdx ) ; if ( UseMO . isImplicit ( ) ) { for ( MCSuperRegIterator SR ( UseMO . getReg ( ) , & RI ) ; SR . isValid ( ) ; ++ SR ) { int Idx = UseMI . findRegisterUseOperandIdx ( * SR , false , & RI ) ; if ( Idx != - <NUM_LIT> ) { UseIdx = Idx ; break ; } }


<s> for ( MCSuperRegIterator SR ( DefMO . getReg ( ) , & RI ) ; SR . isValid ( ) ; ++ SR ) { int Idx = DefMI . findRegisterDefOperandIdx ( * SR , false , false , & RI ) ; if ( Idx != - <NUM_LIT> ) { DefIdx = Idx ; break ; } } } MachineOperand UseMO = UseMI . getOperand ( UseIdx ) ; if ( UseMO . isImplicit ( ) ) { for ( MCSuperRegIterator SR ( UseMO . getReg ( ) , & RI ) ; SR . isValid ( ) ; ++ SR ) { int Idx = UseMI . findRegisterUseOperandIdx ( * SR , false , & RI ) ; if ( Idx != - <NUM_LIT> ) { UseIdx = Idx ; break ; } } } } return TargetInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ;


<s> if ( MI . isDebugValue ( ) || MI . isPosition ( ) ) return <NUM_LIT> ; unsigned Size = MI . getDesc ( ) . getSize ( ) ; if ( ! Size ) Size = HEXAGON_INSTR_SIZE ; if ( isConstExtended ( MI ) || isExtended ( MI ) ) Size += HEXAGON_INSTR_SIZE ; if ( BranchRelaxAsmLarge && MI . getOpcode ( ) == <STR_LIT> ) { const MachineBasicBlock & MBB = * MI . getParent ( ) ; const MachineFunction * MF = MBB . getParent ( ) ; const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; unsigned NumDefs = <NUM_LIT> ; for ( ; MI . getOperand ( NumDefs ) . isReg ( ) && MI . getOperand ( NumDefs ) . isDef ( ) ; ++ NumDefs ) assert ( NumDefs != MI . getNumOperands ( ) - <NUM_LIT> && <STR_LIT> ) ; assert ( MI . getOperand ( NumDefs ) . isSymbol ( ) && <STR_LIT> ) ;

const char * AsmStr = MI . getOperand ( NumDefs ) . getSymbolName ( ) ;


<s> const TargetSubtargetInfo & ST = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) ;

const InstrItineraryData & II = * ST . getInstrItineraryData ( ) ;


<s> const InstrStage & IS = * II . beginStage ( MI . getDesc ( ) . getSchedClass ( ) ) ;


<s> if ( <STR_LIT> ( MI . getOpcode ( ) ) >= <NUM_LIT> ) return true ; if ( MI . getDesc ( ) . mayLoad ( ) || MI . getDesc ( ) . mayStore ( ) ) { switch ( getAddrMode ( MI ) ) { case <STR_LIT> : NonExtOpcode = <STR_LIT> ( MI . getOpcode ( ) ) ; break ; case <STR_LIT> : NonExtOpcode = <STR_LIT> ( MI . getOpcode ( ) ) ; break ; case <STR_LIT> : NonExtOpcode = <STR_LIT> ( MI . getOpcode ( ) ) ; break ; default : return false ; } if ( NonExtOpcode < <NUM_LIT> ) return false ;


<s> if ( MI . getDesc ( ) . mayLoad ( ) || MI . getDesc ( ) . mayStore ( ) ) { switch ( getAddrMode ( MI ) ) { case <STR_LIT> : NonExtOpcode = <STR_LIT> ( MI . getOpcode ( ) ) ; break ; case <STR_LIT> :


<s> DEBUG ( dbgs ( ) << <STR_LIT> << NewTarget -> getNumber ( ) ; MI . dump ( ) ; ) ; assert ( MI . isBranch ( ) ) ; unsigned NewOpcode = getInvertedPredicatedOpcode ( MI . getOpcode ( ) ) ; int TargetPos = MI . getNumOperands ( ) - <NUM_LIT> ;

while ( ( TargetPos > - <NUM_LIT> ) && ! MI . getOperand ( TargetPos ) . isMBB ( ) ) -- TargetPos ;


<s> if ( ! ( isTC1 ( MI ) ) && ! ( QII -> isTC2Early ( MI ) ) && ! ( MI . getDesc ( ) . mayLoad ( ) ) && ! ( MI . getDesc ( ) . mayStore ( ) ) && ( MI . getDesc ( ) . getOpcode ( ) != <STR_LIT> ) && ( MI . getDesc ( ) . getOpcode ( ) != <STR_LIT> ) && ! ( QII -> isMemOp ( MI ) ) && ! ( MI . isBranch ( ) ) && ! ( MI . isReturn ( ) ) && ! MI . isCall ( ) ) return true ; return false ;


<s> if ( ! isExtendable ) return false ; if ( MI . isCall ( ) ) return false ; short ExtOpNum = getCExtOpNum ( MI ) ; const MachineOperand & MO = MI . getOperand ( ExtOpNum ) ; if ( MO . getTargetFlags ( ) && <STR_LIT> ) return true ; if ( MO . isMBB ( ) ) return false ; if ( MO . isGlobal ( ) || MO . isSymbol ( ) || MO . isBlockAddress ( ) || MO . isJTI ( ) || MO . isCPI ( ) || MO . isFPImm ( ) ) return true ; assert ( MO . isImm ( ) && <STR_LIT> ) ;


<s> if ( MO . isGlobal ( ) || MO . isSymbol ( ) || MO . isBlockAddress ( ) || MO . isJTI ( ) || MO . isCPI ( ) || MO . isFPImm ( ) ) return true ; assert ( MO . isImm ( ) && <STR_LIT> ) ; int MinValue = getMinValue ( MI ) ; int MaxValue = getMaxValue ( MI ) ;


<s> bool <ISA_LIT>InstrInfo :: isDependent ( const MachineInstr & ProdMI , const MachineInstr & ConsMI ) const { if ( ! ProdMI . getDesc ( ) . getNumDefs ( ) ) return false ; auto & HRI = getRegisterInfo ( ) ; SmallVector < unsigned , <NUM_LIT> > DefsA ; SmallVector < unsigned , <NUM_LIT> > DefsB ; SmallVector < unsigned , <NUM_LIT> > UsesA ; SmallVector < unsigned , <NUM_LIT> > UsesB ; parseOperands ( ProdMI , DefsA , UsesA ) ; parseOperands ( ConsMI , DefsB , UsesB ) ; for ( auto & RegA : DefsA ) for ( auto & RegB : UsesB ) { if ( RegA == RegB ) return true ; if ( TargetRegisterInfo :: isPhysicalRegister ( RegA ) ) for ( MCSubRegIterator SubRegs ( RegA , & HRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) if ( RegB == * SubRegs ) return true ; if ( TargetRegisterInfo :: isPhysicalRegister ( RegB ) ) for ( MCSubRegIterator SubRegs ( RegB , & HRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) if ( RegA == * SubRegs ) return true ; }


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> const uint64_t F = MI . getDesc ( ) . TSFlags ; if ( ( F >> <STR_LIT> ) & <STR_LIT> ) return true ; for ( MachineInstr :: const_mop_iterator I = MI . operands_begin ( ) , E = MI . operands_end ( ) ; I != E ; ++ I ) {

if ( I -> getTargetFlags ( ) && <STR_LIT> ) return true ;


<s> for ( MachineInstr :: const_mop_iterator I = MI . operands_begin ( ) , E = MI . operands_end ( ) ; I != E ; ++ I ) { if ( I -> getTargetFlags ( ) && <STR_LIT> ) return true ; }


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; }


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> DEBUG ( LRMI . dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ( isEarly ? <STR_LIT> : <STR_LIT> ) ) ; DEBUG ( ESMI . dump ( ) ) ; if ( isLate && isEarly ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand OpFI = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpFI . isFI ( ) ) return <NUM_LIT> ; const MachineOperand OpOff = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } case <STR_LIT> :


<s> bool <ISA_LIT>InstrInfo :: isMemOp ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( MI . isCall ( ) || isTailCall ( MI ) ) { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . usePredicatedCalls ( ) ) return false ;


<s> bool <ISA_LIT>InstrInfo :: isPredicable ( const MachineInstr & MI ) const { if ( ! MI . getDesc ( ) . isPredicable ( ) ) return false ; if ( MI . isCall ( ) || isTailCall ( MI ) ) { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . usePredicatedCalls ( ) ) return false ; }


<s> if ( MI . isCall ( ) ) { if ( doesNotReturn ( MI ) ) return true ;

for ( auto I : MBB -> successors ( ) ) if ( I -> isEHPad ( ) ) return true ;


<s> if ( MI . getDesc ( ) . isTerminator ( ) || MI . isPosition ( ) ) return true ;

if ( MI . isInlineAsm ( ) && ! ScheduleInlineAsm ) return true ;


<s> if ( ! OpFI . isFI ( ) ) return <NUM_LIT> ; const MachineOperand & OpOff = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand & OpFI = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpFI . isFI ( ) ) return <NUM_LIT> ; const MachineOperand & OpOff = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; }


<s> bool <ISA_LIT>InstrInfo :: isValidOffset ( unsigned Opcode , int Offset , bool Extend ) const { switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMV_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMV_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMV_OFFSET_MIN_128B ) && ( Offset <= <ISA_LIT>_MEMV_OFFSET_MAX_128B ) ; case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; } if ( Extend ) return true ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMW_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMW_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; } if ( Extend ) return true ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMW_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMW_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>InstrInfo :: mayBeCurLoad ( const MachineInstr & MI ) const {

auto & HST = MI . getParent ( ) -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> bool <ISA_LIT>InstrInfo :: mayBeNewStore ( const MachineInstr & MI ) const { const uint64_t F = MI . getDesc ( ) . TSFlags ; return ( F >> <STR_LIT> ) & <STR_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: predCanBeUsedAsDotNew ( const MachineInstr & MI , unsigned PredReg ) const { for ( const MachineOperand & MO : MI . operands ( ) ) { if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( PredReg ) ) return false ; if ( MO . isReg ( ) && MO . isDef ( ) && MO . isImplicit ( ) && ( MO . getReg ( ) == PredReg ) ) return false ; } return MI . getOpcode ( ) != <STR_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: predCanBeUsedAsDotNew ( const MachineInstr & MI , unsigned PredReg ) const { for ( const MachineOperand & MO : MI . operands ( ) ) { if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( PredReg ) ) return false ; if ( MO . isReg ( ) && MO . isDef ( ) && MO . isImplicit ( ) && ( MO . getReg ( ) == PredReg ) ) return false ;


<s> int Opc = MI . getOpcode ( ) ; assert ( isPredicable ( MI ) && <STR_LIT> ) ; bool invertJump = predOpcodeHasNot ( Cond ) ; MachineBasicBlock & B = * MI . getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned PredOpc = getCondOpcode ( Opc , invertJump ) ; MachineInstrBuilder T = BuildMI ( B , MI , DL , get ( PredOpc ) ) ; unsigned NOp = <NUM_LIT> , NumOps = MI . getNumOperands ( ) ; while ( NOp < NumOps ) { MachineOperand & Op = MI . getOperand ( NOp ) ; if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . isImplicit ( ) ) break ; T . add ( Op ) ; NOp ++ ; } unsigned PredReg , PredRegPos , PredRegFlags ; bool GotPredReg = getPredReg ( Cond , PredReg , PredRegPos , PredRegFlags ) ; ( void ) GotPredReg ; assert ( GotPredReg ) ; T . addReg ( PredReg , PredRegFlags ) ; while ( NOp < NumOps ) T . add ( MI . getOperand ( NOp ++ ) ) ; MI . setDesc ( get ( PredOpc ) ) ; while ( unsigned n = MI . getNumOperands ( ) ) MI . RemoveOperand ( n - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , n = T -> getNumOperands ( ) ; i < n ; ++ i ) MI . addOperand ( T -> getOperand ( i ) ) ; MachineBasicBlock :: instr_iterator TI = T -> getIterator ( ) ;


<s> const MachineInstr & J = * MII ; return producesStall ( J , MI ) ; } for ( ++ MII ; MII != MIE && MII -> isInsideBundle ( ) ; ++ MII ) { const MachineInstr & J = * MII ; if ( producesStall ( J , MI ) ) return true ;


<s> MachineBasicBlock :: const_instr_iterator MII = BII ; MachineBasicBlock :: const_instr_iterator MIE = MII -> getParent ( ) -> instr_end ( ) ; if ( ! ( * MII ) . isBundle ( ) ) { const MachineInstr & J = * MII ; return producesStall ( J , MI ) ; } for ( ++ MII ; MII != MIE && MII -> isInsideBundle ( ) ; ++ MII ) { const MachineInstr & J = * MII ; if ( producesStall ( J , MI ) ) return true ; }


<s> if ( I -> isDebugValue ( ) ) continue ; if ( ! I -> isBranch ( ) ) return Count ; if ( Count && ( I -> getOpcode ( ) == <STR_LIT> ) ) llvm_unreachable ( <STR_LIT> ) ; MBB . erase ( & MBB . back ( ) ) ; I = MBB . end ( ) ; ++ Count ; }


<s> -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! I -> isBranch ( ) ) return Count ; if ( Count && ( I -> getOpcode ( ) == <STR_LIT> ) ) llvm_unreachable ( <STR_LIT> ) ; MBB . erase ( & MBB . back ( ) ) ; I = MBB . end ( ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ) ; MI . setDesc ( get ( getInvertedPredicatedOpcode ( MI . getOpcode ( ) ) ) ) ;


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( HasAlloca ) Align = HFI . getStackAlignment ( ) ; unsigned Opc = Align < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( HasAlloca ) Align = HFI . getStackAlignment ( ) ; unsigned Opc = Align < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( HasAlloca ) Align = HFI . getStackAlignment ( ) ; unsigned Opc = Align < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( HasAlloca ) Align = HFI . getStackAlignment ( ) ; unsigned Opc = Align < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ;


<s> MachineInstr * SecondLastInst = NULL ; do { if ( & * I != LastInst && ! I -> isBundle ( ) && isUnpredicatedTerminator ( I ) ) { if ( ! SecondLastInst ) SecondLastInst = I ; else return true ; } if ( I == MBB . instr_begin ( ) ) break ; -- I ; } while ( I ) ; int LastOpcode = LastInst -> getOpcode ( ) ; bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( LastOpcode ) ; bool LastOpcodeHasNot = PredOpcodeHasNot ( LastOpcode ) ; if ( LastInst && ! SecondLastInst ) { if ( LastOpcode == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( LastOpcode == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastOpcodeHasJMP_c ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( LastOpcodeHasNot ) { Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } int SecLastOpcode = SecondLastInst -> getOpcode ( ) ; bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( SecLastOpcode ) ; bool SecLastOpcodeHasNot = PredOpcodeHasNot ( SecLastOpcode ) ; if ( SecLastOpcodeHasJMP_c && ( LastOpcode == <STR_LIT> ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( SecLastOpcodeHasNot ) Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecLastOpcode == <STR_LIT> && LastOpcode == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } if ( SecLastOpcode == <STR_LIT> && LastOpcode == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ;


<s> bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( LastOpcode ) ; bool LastOpcodeHasNot = PredOpcodeHasNot ( LastOpcode ) ; if ( LastInst && ! SecondLastInst ) { if ( LastOpcode == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( LastOpcode == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastOpcodeHasJMP_c ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( LastOpcodeHasNot ) { Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } int SecLastOpcode = SecondLastInst -> getOpcode ( ) ; bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( SecLastOpcode ) ; bool SecLastOpcodeHasNot = PredOpcodeHasNot ( SecLastOpcode ) ; if ( SecLastOpcodeHasJMP_c && ( LastOpcode == <STR_LIT> ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( SecLastOpcodeHasNot ) Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecLastOpcode == <STR_LIT> && LastOpcode == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } if ( SecLastOpcode == <STR_LIT> && LastOpcode == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; }


<s> short changeAddrMode_abs_io ( const MachineInstr & MI ) const { return changeAddrMode_abs_io ( MI . getOpcode ( ) ) ;


<s> short changeAddrMode_io_abs ( const MachineInstr & MI ) const {

return changeAddrMode_io_abs ( MI . getOpcode ( ) ) ;


<s> short changeAddrMode_rr_io ( const MachineInstr & MI ) const { return changeAddrMode_rr_io ( MI . getOpcode ( ) ) ;


<s> return changeAddrMode_ur_rr ( MI . getOpcode ( ) ) ;


<s> if ( SrcReg == RI . getSubReg ( DestReg , <STR_LIT> ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addReg ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addImm ( <NUM_LIT> ) ; } return ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ;


<s> MachineInstr * <ISA_LIT>InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , int FI ) const { return ( <NUM_LIT> ) ;


<s> int <ISA_LIT>InstrInfo :: GetDotNewOp ( const MachineInstr * MI ) const { int NVOpcode = <STR_LIT> ( MI -> getOpcode ( ) ) ; if ( NVOpcode >= <NUM_LIT> ) return NVOpcode ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> :


<s> int <ISA_LIT>InstrInfo :: getDotNewPredJumpOp ( MachineInstr * MI , const MachineBranchProbabilityInfo * MBPI ) const { bool taken = false ; MachineBasicBlock * Src = MI -> getParent ( ) ; MachineOperand * BrTarget = & MI -> getOperand ( <NUM_LIT> ) ;

MachineBasicBlock * Dst = BrTarget -> getMBB ( ) ;


<s> int NewOp = opc ; if ( isPredicated ( NewOp ) && isPredicatedNew ( NewOp ) ) { NewOp = <STR_LIT> ( NewOp ) ; if ( NewOp < <NUM_LIT> ) assert ( <NUM_LIT> && <STR_LIT> ) ; } if ( isNewValueStore ( NewOp ) ) { NewOp = <STR_LIT> ( NewOp ) ; if ( NewOp < <NUM_LIT> ) assert ( <NUM_LIT> && <STR_LIT> ) ; } return NewOp ;


<s> int <ISA_LIT>InstrInfo :: GetDotOldOp ( const int opc ) const { int NewOp = opc ;

if ( isPredicated ( NewOp ) && isPredicatedNew ( NewOp ) ) {


<s> InvPredOpcode = isPredicatedTrue ( Opc ) ? <STR_LIT> ( Opc ) : <STR_LIT> ( Opc ) ; if ( InvPredOpcode >= <NUM_LIT> ) return InvPredOpcode ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> if ( CondOpcode >= <NUM_LIT> ) return CondOpcode ; switch ( Opc ) { case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ;


<s> unsigned bits = ( F >> <STR_LIT> ) & <STR_LIT> ; if ( isSigned ) return ~ ( - <NUM_LIT> << ( bits - <NUM_LIT> ) ) ; else return ~ ( - <NUM_LIT> << bits ) ;


<s> int <ISA_LIT>InstrInfo :: getMaxValue ( const MachineInstr * MI ) const { const uint64_t F = MI -> getDesc ( ) . TSFlags ; unsigned isSigned = ( F >> <STR_LIT> ) & <STR_LIT> ;

unsigned bits = ( F >> <STR_LIT> ) & <STR_LIT> ;


<s> unsigned bits = ( F >> <STR_LIT> ) & <STR_LIT> ; if ( isSigned ) return - <NUM_LIT> << ( bits - <NUM_LIT> ) ;


<s> int <ISA_LIT>InstrInfo :: getMinValue ( const MachineInstr * MI ) const {

const uint64_t F = MI -> getDesc ( ) . TSFlags ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & ST ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ST ) , Subtarget ( ST ) {


<s> unsigned <ISA_LIT>InstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , const SmallVectorImpl < MachineOperand > & Cond , DebugLoc DL ) const { int BOpc = <STR_LIT> ; int BccOpc = <STR_LIT> ; assert ( TBB && <STR_LIT> ) ; int regPos = <NUM_LIT> ; if ( ! Cond . empty ( ) && Cond [ <NUM_LIT> ] . isImm ( ) && Cond [ <NUM_LIT> ] . getImm ( ) == <NUM_LIT> ) { BccOpc = <STR_LIT> ; regPos = <NUM_LIT> ; } if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) { MachineBasicBlock * NewTBB , * NewFBB ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; MachineInstr * Term = MBB . getFirstTerminator ( ) ; if ( isPredicated ( Term ) && ! AnalyzeBranch ( MBB , NewTBB , NewFBB , Cond , false ) ) { MachineBasicBlock * NextBB = llvm :: next ( MachineFunction :: iterator ( & MBB ) ) ; if ( NewTBB == NextBB ) { ReverseBranchCondition ( Cond ) ; RemoveBranch ( MBB ) ; return InsertBranch ( MBB , TBB , <NUM_LIT> , Cond , DL ) ; }


<s> if ( NewTBB == NextBB ) { ReverseBranchCondition ( Cond ) ; RemoveBranch ( MBB ) ; return InsertBranch ( MBB , TBB , <NUM_LIT> , Cond , DL ) ; } } BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else { BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ regPos ] . getReg ( ) ) . addMBB ( TBB ) ; } return <NUM_LIT> ; }


<s> bool <ISA_LIT>InstrInfo :: isConditionalALU32 ( const MachineInstr * MI ) const { const <ISA_LIT>RegisterInfo & QRI = getRegisterInfo ( ) ; switch ( MI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( ! Subtarget . hasV4TOps ( ) ) return false ; const uint64_t F = MI -> getDesc ( ) . TSFlags ; unsigned isExtended = ( F >> <STR_LIT> ) & <STR_LIT> ; if ( isExtended ) return true ; unsigned isExtendable = ( F >> <STR_LIT> ) & <STR_LIT> ; if ( ! isExtendable ) return false ; short ExtOpNum = getCExtOpNum ( MI ) ; const MachineOperand & MO = MI -> getOperand ( ExtOpNum ) ; if ( MO . getTargetFlags ( ) && <STR_LIT> ) return true ; if ( MO . isMBB ( ) ) return false ; if ( MO . isGlobal ( ) || MO . isSymbol ( ) ) return true ; assert ( MO . isImm ( ) && <STR_LIT> ) ; int MinValue = getMinValue ( MI ) ;


<s> bool <ISA_LIT>InstrInfo :: isConstExtended ( MachineInstr * MI ) const { if ( ! Subtarget . hasV4TOps ( ) ) return false ; const uint64_t F = MI -> getDesc ( ) . TSFlags ; unsigned isExtended = ( F >> <STR_LIT> ) & <STR_LIT> ; if ( isExtended ) return true ; unsigned isExtendable = ( F >> <STR_LIT> ) & <STR_LIT> ; if ( ! isExtendable ) return false ; short ExtOpNum = getCExtOpNum ( MI ) ; const MachineOperand & MO = MI -> getOperand ( ExtOpNum ) ; if ( MO . getTargetFlags ( ) && <STR_LIT> ) return true ; if ( MO . isMBB ( ) ) return false ; if ( MO . isGlobal ( ) || MO . isSymbol ( ) ) return true ; assert ( MO . isImm ( ) && <STR_LIT> ) ; int MinValue = getMinValue ( MI ) ;


<s> bool <ISA_LIT>InstrInfo :: isDeallocRet ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> if ( ! Subtarget . hasV4TOps ( ) ) return false ; const uint64_t F = MI -> getDesc ( ) . TSFlags ; return ( ( F >> <STR_LIT> ) & <STR_LIT> ) == OperandNum ;


<s> const int Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : return isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) && isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; case <STR_LIT> : return isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Subtarget . hasV4TOps ( ) ;


<s> isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumInstrs , const BranchProbability & Probability ) const {


<s> bool <ISA_LIT>InstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumTCycles , unsigned ExtraTCycles , MachineBasicBlock & FMBB , unsigned NumFCycles , unsigned ExtraFCycles , const BranchProbability & Probability ) const {


<s> bool <ISA_LIT>InstrInfo :: isSchedulingBoundary ( const MachineInstr * MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const {

if ( MI -> isDebugValue ( ) ) return false ;


<s> if ( MI -> getDesc ( ) . isTerminator ( ) || MI -> isLabel ( ) || MI -> isInlineAsm ( ) ) return true ;


<s> default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; } return <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , Align ) ; if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else { llvm_unreachable ( <STR_LIT> ) ; }


<s> const <ISA_LIT>RegisterInfo & QRI = getRegisterInfo ( ) ; const uint64_t F = MI -> getDesc ( ) . TSFlags ; return ( ( F >> <STR_LIT> ) & <STR_LIT> & QRI . Subtarget . hasV4TOps ( ) ) ;


<s> for ( oper = MI -> getNumOperands ( ) - <NUM_LIT> ; oper >= <NUM_LIT> ; -- oper ) { MachineOperand & MO = MI -> getOperand ( oper ) ; if ( MO . isReg ( ) && ! MO . isUse ( ) && ! MO . isImplicit ( ) ) { break ; } if ( MO . isReg ( ) ) { MI -> getOperand ( oper + <NUM_LIT> ) . ChangeToRegister ( MO . getReg ( ) , MO . isDef ( ) , MO . isImplicit ( ) , MO . isKill ( ) , MO . isDead ( ) , MO . isUndef ( ) , MO . isDebug ( ) ) ; } else if ( MO . isImm ( ) ) { MI -> getOperand ( oper + <NUM_LIT> ) . ChangeToImmediate ( MO . getImm ( ) ) ; } else if ( MO . isGlobal ( ) ) { assert ( hasGAOpnd == false && <STR_LIT> ) ; tmpOpnds . push_back ( MO ) ; hasGAOpnd = true ; GAIdx = oper ; continue ; } else { assert ( false && <STR_LIT> ) ; } } }

int regPos = invertJump ? <NUM_LIT> : <NUM_LIT> ;


<s> return ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: PredOpcodeHasNot ( Opcode_t Opcode ) const { return ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) ;


<s> -- I ; if ( I -> getOpcode ( ) != BOpc && I -> getOpcode ( ) != BccOpc && I -> getOpcode ( ) != BccOpcNot ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ;

if ( I == MBB . begin ( ) ) return <NUM_LIT> ;


<s> MachineBasicBlock :: iterator I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( I -> getOpcode ( ) != BOpc && I -> getOpcode ( ) != BccOpc && I -> getOpcode ( ) != BccOpcNot ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( I -> getOpcode ( ) != BccOpc && I -> getOpcode ( ) != BccOpcNot ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; return <NUM_LIT> ;


<s> } else { Cond . insert ( Cond . begin ( ) , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } return false ;


<s> storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ;

} else if ( <STR_LIT> . hasSubClassEq ( RC ) ) {


<s> DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) {


<s> bool <ISA_LIT>InstrInfo :: SubsumesPredicate ( const SmallVectorImpl < MachineOperand > & Pred1 , const SmallVectorImpl < MachineOperand > & Pred2 ) const { return false ;


<s> short <ISA_LIT>InstrInfo :: getNonExtOpcode ( const MachineInstr * MI ) const { short NonExtOpcode = <STR_LIT> ( MI -> getOpcode ( ) ) ; if ( NonExtOpcode >= <NUM_LIT> ) return NonExtOpcode ; if ( MI -> getDesc ( ) . mayLoad ( ) || MI -> getDesc ( ) . mayStore ( ) ) { switch ( getAddrMode ( MI ) ) { case <STR_LIT> : return <STR_LIT> ( MI -> getOpcode ( ) ) ; case <STR_LIT> : return <STR_LIT> ( MI -> getOpcode ( ) ) ; default : return - <NUM_LIT> ; } }


<s> MachineBasicBlock * NextBB = & * ++ MBB . getIterator ( ) ; if ( NewTBB == NextBB ) { ReverseBranchCondition ( Cond ) ; RemoveBranch ( MBB ) ; return InsertBranch ( MBB , TBB , nullptr , Cond , DL ) ; } } BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else if ( isEndLoopN ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { int EndLoopOp = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( Cond [ <NUM_LIT> ] . isMBB ( ) ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( TBB , EndLoopOp , VisitedBBs ) ; assert ( Loop != <NUM_LIT> && <STR_LIT> ) ; Loop -> getOperand ( <NUM_LIT> ) . setMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( EndLoopOp ) ) . addMBB ( TBB ) ; } else if ( isNewValueJump ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Flags1 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) ; ) ; if ( Cond [ <NUM_LIT> ] . isReg ( ) ) { unsigned Flags2 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags2 ) . addMBB ( TBB ) ; } else if ( Cond [ <NUM_LIT> ] . isImm ( ) ) { BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addMBB ( TBB ) ; } else llvm_unreachable ( <STR_LIT> ) ; } else { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; const MachineOperand & RO = Cond [ <NUM_LIT> ] ;

unsigned Flags = getUndefRegState ( RO . isUndef ( ) ) ;


<s> if ( MI -> getDesc ( ) . mayLoad ( ) || MI -> getDesc ( ) . mayStore ( ) ) { switch ( getAddrMode ( MI ) ) { case <STR_LIT> : NonExtOpcode = <STR_LIT> ( MI -> getOpcode ( ) ) ; break ; case <STR_LIT> : NonExtOpcode = <STR_LIT> ( MI -> getOpcode ( ) ) ;


<s> if ( <STR_LIT> ( MI -> getOpcode ( ) ) >= <NUM_LIT> ) return true ; if ( MI -> getDesc ( ) . mayLoad ( ) || MI -> getDesc ( ) . mayStore ( ) ) { switch ( getAddrMode ( MI ) ) { case <STR_LIT> : NonExtOpcode = <STR_LIT> ( MI -> getOpcode ( ) ) ; break ; case <STR_LIT> : NonExtOpcode = <STR_LIT> ( MI -> getOpcode ( ) ) ;


<s> while ( NOp < NumOps ) T . addOperand ( MI -> getOperand ( NOp ++ ) ) ; MI -> setDesc ( get ( PredOpc ) ) ; while ( unsigned n = MI -> getNumOperands ( ) ) MI -> RemoveOperand ( n - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , n = T -> getNumOperands ( ) ; i < n ; ++ i ) MI -> addOperand ( T -> getOperand ( i ) ) ; MachineBasicBlock :: instr_iterator TI = T -> getIterator ( ) ; B . erase ( TI ) ; MachineRegisterInfo & MRI = B . getParent ( ) -> getRegInfo ( ) ;


<s> bool invertJump = predOpcodeHasNot ( Cond ) ; MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned PredOpc = getCondOpcode ( Opc , invertJump ) ; MachineInstrBuilder T = BuildMI ( B , MI , DL , get ( PredOpc ) ) ; unsigned NOp = <NUM_LIT> , NumOps = MI -> getNumOperands ( ) ; while ( NOp < NumOps ) { MachineOperand & Op = MI -> getOperand ( NOp ) ; if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . isImplicit ( ) ) break ; T . addOperand ( Op ) ; NOp ++ ; } unsigned PredReg , PredRegPos , PredRegFlags ; bool GotPredReg = getPredReg ( Cond , PredReg , PredRegPos , PredRegFlags ) ; ( void ) GotPredReg ; assert ( GotPredReg ) ; T . addReg ( PredReg , PredRegFlags ) ; while ( NOp < NumOps ) T . addOperand ( MI -> getOperand ( NOp ++ ) ) ; MI -> setDesc ( get ( PredOpc ) ) ; while ( unsigned n = MI -> getNumOperands ( ) ) MI -> RemoveOperand ( n - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , n = T -> getNumOperands ( ) ; i < n ; ++ i ) MI -> addOperand ( T -> getOperand ( i ) ) ; MachineBasicBlock :: instr_iterator TI = T -> getIterator ( ) ; B . erase ( TI ) ;

MachineRegisterInfo & MRI = B . getParent ( ) -> getRegInfo ( ) ;


<s> Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastOpcodeHasNVJump && ( LastInst -> getNumExplicitOperands ( ) == <NUM_LIT> ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOpcode ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( MBB ) << <STR_LIT> ; ) ; return true ; } bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( SecLastOpcode ) ; bool SecLastOpcodeHasNVJump = isNewValueJump ( * SecondLastInst ) ; if ( SecLastOpcodeHasJMP_c && ( LastOpcode == <STR_LIT> ) ) { if ( ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( SecondLastInst -> getOpcode ( ) ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecLastOpcodeHasNVJump && ( SecondLastInst -> getNumExplicitOperands ( ) == <NUM_LIT> ) && ( LastOpcode == <STR_LIT> ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( SecondLastInst -> getOpcode ( ) ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecLastOpcode == <STR_LIT> && LastOpcode == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst -> getIterator ( ) ; if ( AllowModify ) I -> eraseFromParent ( ) ;


<s> if ( ! OffsetOp . isImm ( ) ) return <NUM_LIT> ; Offset = OffsetOp . getImm ( ) ; } const MachineOperand & BaseOp = MI . getOperand ( BasePos ) ; if ( BaseOp . getSubReg ( ) != <NUM_LIT> ) return <NUM_LIT> ;


<s> if ( isPredicated ( NewOp ) && isPredicatedNew ( NewOp ) ) { NewOp = <STR_LIT> ( NewOp ) ; if ( ! Subtarget . getFeatureBits ( ) [ <STR_LIT> ] ) { switch ( NewOp ) { case <STR_LIT> : NewOp = <STR_LIT> ; break ; case <STR_LIT> : NewOp = <STR_LIT> ; break ; case <STR_LIT> : NewOp = <STR_LIT> ; break ; case <STR_LIT> : NewOp = <STR_LIT> ; break ; }


<s> if ( UseMO . isImplicit ( ) ) { for ( MCSuperRegIterator SR ( UseMO . getReg ( ) , & HRI ) ; SR . isValid ( ) ; ++ SR ) { int Idx = UseMI . findRegisterUseOperandIdx ( * SR , false , & HRI ) ; if ( Idx != - <NUM_LIT> ) { UseIdx = Idx ; break ; } } } } int Latency = TargetInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ;


<s> bool <ISA_LIT>InstrInfo :: hasLoadFromStackSlot ( const MachineInstr & MI , const MachineMemOperand * & MMO , int & FrameIndex ) const { if ( MI . isBundle ( ) ) { const MachineBasicBlock * MBB = MI . getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI . getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( TargetInstrInfo :: hasLoadFromStackSlot ( * MII , MMO , FrameIndex ) ) return true ; return false ; }

return TargetInstrInfo :: hasLoadFromStackSlot ( MI , MMO , FrameIndex ) ;


<s> for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( TargetInstrInfo :: hasLoadFromStackSlot ( * MII , MMO , FrameIndex ) ) return true ; return false ;


<s> const MachineBasicBlock * MBB = MI . getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI . getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( TargetInstrInfo :: hasStoreToStackSlot ( * MII , MMO , FrameIndex ) ) return true ; return false ; }

return TargetInstrInfo :: hasStoreToStackSlot ( MI , MMO , FrameIndex ) ;


<s> for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( TargetInstrInfo :: hasStoreToStackSlot ( * MII , MMO , FrameIndex ) ) return true ; return false ;


<s> int EndLoopOp = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( Cond [ <NUM_LIT> ] . isMBB ( ) ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( TBB , EndLoopOp , Cond [ <NUM_LIT> ] . getMBB ( ) , VisitedBBs ) ; assert ( Loop != nullptr && <STR_LIT> ) ; Loop -> getOperand ( <NUM_LIT> ) . setMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( EndLoopOp ) ) . addMBB ( TBB ) ; } else if ( isNewValueJump ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Flags1 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( MBB ) ; ) ; if ( Cond [ <NUM_LIT> ] . isReg ( ) ) { unsigned Flags2 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags2 ) . addMBB ( TBB ) ; } else if ( Cond [ <NUM_LIT> ] . isImm ( ) ) {

BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addMBB ( TBB ) ;


<s> unsigned NewOpcode = getInvertedPredicatedOpcode ( MI . getOpcode ( ) ) ; int TargetPos = MI . getNumOperands ( ) - <NUM_LIT> ; while ( ( TargetPos > - <NUM_LIT> ) && ! MI . getOperand ( TargetPos ) . isMBB ( ) ) -- TargetPos ; assert ( ( TargetPos >= <NUM_LIT> ) && MI . getOperand ( TargetPos ) . isMBB ( ) ) ; MI . getOperand ( TargetPos ) . setMBB ( NewTarget ) ; if ( EnableBranchPrediction && isPredicatedNew ( MI ) ) { NewOpcode = reversePrediction ( NewOpcode ) ;


<s> bool <ISA_LIT>InstrInfo :: invertAndChangeJumpTarget ( MachineInstr & MI , MachineBasicBlock * NewTarget ) const { DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * NewTarget ) ; MI . dump ( ) ; ) ; assert ( MI . isBranch ( ) ) ; unsigned NewOpcode = getInvertedPredicatedOpcode ( MI . getOpcode ( ) ) ;

int TargetPos = MI . getNumOperands ( ) - <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand OpFI = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpFI . isFI ( ) ) return <NUM_LIT> ; const MachineOperand OpOff = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand OpFI = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpFI . isFI ( ) ) return <NUM_LIT> ; const MachineOperand OpOff = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; }


<s> bool <ISA_LIT>InstrInfo :: isPredicable ( const MachineInstr & MI ) const { if ( ! MI . getDesc ( ) . isPredicable ( ) ) return false ; if ( MI . isCall ( ) || isTailCall ( MI ) ) { if ( ! Subtarget . usePredicatedCalls ( ) ) return false ; } if ( ! Subtarget . hasV62TOps ( ) ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> } if ( ! Subtarget . hasV62TOps ( ) ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand & OpFI = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpFI . isFI ( ) ) return <NUM_LIT> ; const MachineOperand & OpOff = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; FrameIndex = OpFI . getIndex ( ) ;

return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> if ( Offset % Size != <NUM_LIT> ) return false ; int Count = Offset / Size ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( Count ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> case <STR_LIT> : case <STR_LIT> : { unsigned VectorSize = TRI -> getSpillSize ( <STR_LIT> ) ; assert ( isPowerOf2_32 ( VectorSize ) ) ; if ( Offset & ( VectorSize - <NUM_LIT> ) ) return false ; return isInt < <NUM_LIT> > ( Offset >> Log2_32 ( VectorSize ) ) ; } case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; } if ( Extend ) return true ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMW_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMW_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) {


<s> } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( HasAlloca ) SlotAlign = HFI . getStackAlignment ( ) ; unsigned Opc = SlotAlign < RegAlign ? <STR_LIT> : <STR_LIT> ; MachineMemOperand * MMOA = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , SlotAlign ) ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMOA ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( HasAlloca ) SlotAlign = HFI . getStackAlignment ( ) ;


<s> bool <ISA_LIT>InstrInfo :: mayBeCurLoad ( const MachineInstr & MI ) const { const uint64_t F = MI . getDesc ( ) . TSFlags ;

return ( ( F >> <STR_LIT> ) & <STR_LIT> ) && Subtarget . hasV60TOps ( ) ;


<s> const uint64_t F = MI . getDesc ( ) . TSFlags ;


<s> -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! I -> isBranch ( ) ) return Count ; if ( Count && ( I -> getOpcode ( ) == <STR_LIT> ) ) llvm_unreachable ( <STR_LIT> ) ; MBB . erase ( & MBB . back ( ) ) ;


<s> while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! I -> isBranch ( ) ) return Count ; if ( Count && ( I -> getOpcode ( ) == <STR_LIT> ) ) llvm_unreachable ( <STR_LIT> ) ; MBB . erase ( & MBB . back ( ) ) ; I = MBB . end ( ) ; ++ Count ;


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( HasAlloca ) SlotAlign = HFI . getStackAlignment ( ) ; unsigned Opc = SlotAlign < RegAlign ? <STR_LIT> : <STR_LIT> ; MachineMemOperand * MMOA = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , SlotAlign ) ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMOA ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( HasAlloca ) SlotAlign = HFI . getStackAlignment ( ) ; unsigned Opc = SlotAlign < RegAlign ? <STR_LIT> : <STR_LIT> ; MachineMemOperand * MMOA = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , SlotAlign ) ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMOA ) ; } else {


<s> const <ISA_LIT>FrameLowering & HFI = * Subtarget . getFrameLowering ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , SlotAlign ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( HasAlloca ) SlotAlign = HFI . getStackAlignment ( ) ; unsigned Opc = SlotAlign < RegAlign ? <STR_LIT> : <STR_LIT> ; MachineMemOperand * MMOA = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , SlotAlign ) ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMOA ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( HasAlloca ) SlotAlign = HFI . getStackAlignment ( ) ; unsigned Opc = SlotAlign < RegAlign ? <STR_LIT> : <STR_LIT> ; MachineMemOperand * MMOA = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , SlotAlign ) ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMOA ) ; } else { llvm_unreachable ( <STR_LIT> ) ; }


<s> if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) || MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( MIa . mayLoad ( ) && ! isMemOp ( MIa ) && MIb . mayLoad ( ) && ! isMemOp ( MIb ) ) return true ; unsigned BasePosA , OffsetPosA ; if ( ! getBaseAndOffsetPosition ( MIa , BasePosA , OffsetPosA ) ) return false ; const MachineOperand & BaseA = MIa . getOperand ( BasePosA ) ; unsigned BaseRegA = BaseA . getReg ( ) ; unsigned BaseSubA = BaseA . getSubReg ( ) ; unsigned BasePosB , OffsetPosB ; if ( ! getBaseAndOffsetPosition ( MIb , BasePosB , OffsetPosB ) ) return false ; const MachineOperand & BaseB = MIb . getOperand ( BasePosB ) ; unsigned BaseRegB = BaseB . getReg ( ) ; unsigned BaseSubB = BaseB . getSubReg ( ) ; if ( BaseRegA != BaseRegB || BaseSubA != BaseSubB ) return false ; unsigned SizeA = getMemAccessSize ( MIa ) ; unsigned SizeB = getMemAccessSize ( MIb ) ; const MachineOperand & OffA = MIa . getOperand ( OffsetPosA ) ; const MachineOperand & OffB = MIb . getOperand ( OffsetPosB ) ; if ( ! MIa . getOperand ( OffsetPosA ) . isImm ( ) || ! MIb . getOperand ( OffsetPosB ) . isImm ( ) ) return false ; int OffsetA = isPostIncrement ( MIa ) ? <NUM_LIT> : OffA . getImm ( ) ; int OffsetB = isPostIncrement ( MIb ) ? <NUM_LIT> : OffB . getImm ( ) ; if ( OffsetA > OffsetB ) { uint64_t OffDiff = ( uint64_t ) ( ( int64_t ) OffsetA - ( int64_t ) OffsetB ) ;


<s> CrashPseudoSourceValue ( const TargetInstrInfo & TII ) : PseudoSourceValue ( TargetCustom , TII ) {


<s> if ( atInsnStart && ! std :: isspace ( static_cast < unsigned char > ( * Str ) ) ) { Length += MaxInstLength ; atInsnStart = false ; } if ( atInsnStart && strncmp ( Str , MAI . getCommentString ( ) . data ( ) , MAI . getCommentString ( ) . size ( ) ) == <NUM_LIT> ) atInsnStart = false ; } StringRef Occ ( <STR_LIT> ) ; Length += AStr . count ( Occ ) * <NUM_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: getMemOperandWithOffset ( const MachineInstr & LdSt , const MachineOperand * & BaseOp , int64_t & Offset , const TargetRegisterInfo * TRI ) const {


<s> bool <ISA_LIT>InstrInfo :: getMemOperandWithOffset ( const MachineInstr & LdSt , const MachineOperand * & BaseOp , int64_t & Offset , const TargetRegisterInfo * TRI ) const { unsigned AccessSize = <NUM_LIT> ; BaseOp = getBaseAndOffset ( LdSt , Offset , AccessSize ) ; assert ( ( ! BaseOp || BaseOp -> isReg ( ) ) && <STR_LIT> <STR_LIT> ) ; return BaseOp != nullptr ;


<s> bool isAliased ( const MachineFrameInfo * ) const override {


<s> bool isAliased ( const MachineFrameInfo * ) const override { return false ;


<s> bool isConstant ( const MachineFrameInfo * ) const override { return false ;


<s> const uint64_t F = get ( Opcode ) . TSFlags ;


<s> void printCustom ( raw_ostream & OS ) const override { OS << <STR_LIT> ;


<s> if ( Offset <= <NUM_LIT> ) Loop -> eraseFromParent ( ) ; else Loop -> getOperand ( <NUM_LIT> ) . setImm ( Offset - <NUM_LIT> ) ; return Offset - <NUM_LIT> ; } assert ( Loop -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned LoopCount = Loop -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LoopEnd = createVR ( MF , <STR_LIT> ) ; MachineInstr * NewCmp = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , LoopEnd ) . addReg ( LoopCount ) . addImm ( <NUM_LIT> ) ; unsigned NewLoopCount = createVR ( MF , <STR_LIT> ) ; MachineInstr * NewAdd = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , NewLoopCount ) . addReg ( LoopCount ) . addImm ( - <NUM_LIT> ) ; const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; for ( SmallVectorImpl < MachineInstr * > :: iterator I = PrevInsts . begin ( ) , E = PrevInsts . end ( ) ; I != E ; ++ I ) ( * I ) -> substituteRegister ( LoopCount , NewLoopCount , <NUM_LIT> , HRI ) ; PrevInsts . clear ( ) ; PrevInsts . push_back ( NewCmp ) ; PrevInsts . push_back ( NewAdd ) ; if ( Iter == MaxIter ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( Loop -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addReg ( NewLoopCount ) ; if ( Iter == <NUM_LIT> ) Loop -> eraseFromParent ( ) ;

Cond . push_back ( MachineOperand :: CreateImm ( <STR_LIT> ) ) ;


<s> MachineFunction * MF = MBB . getParent ( ) ; DebugLoc DL = Cmp . getDebugLoc ( ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( & MBB , Cmp . getOpcode ( ) , Cmp . getOperand ( <NUM_LIT> ) . getMBB ( ) , VisitedBBs ) ; if ( ! Loop ) return <NUM_LIT> ; if ( Loop -> getOpcode ( ) == <STR_LIT> || Loop -> getOpcode ( ) == <STR_LIT> ) { int64_t Offset = Loop -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Offset <= <NUM_LIT> ) Loop -> eraseFromParent ( ) ; else Loop -> getOperand ( <NUM_LIT> ) . setImm ( Offset - <NUM_LIT> ) ; return Offset - <NUM_LIT> ; } assert ( Loop -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned LoopCount = Loop -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LoopEnd = createVR ( MF , <STR_LIT> ) ;

MachineInstr * NewCmp = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , LoopEnd ) . addReg ( LoopCount ) . addImm ( <NUM_LIT> ) ;


<s> BuildMI ( * Loop -> getParent ( ) , Loop , Loop -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , NewLoopCount ) . addReg ( LoopCount ) . addImm ( TripCountAdjust ) ;

Loop -> getOperand ( <NUM_LIT> ) . setReg ( NewLoopCount ) ;


<s> return ; } Register LoopCount = Loop -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register NewLoopCount = TII -> createVR ( MF , <STR_LIT> ) ; BuildMI ( * Loop -> getParent ( ) , Loop , Loop -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , NewLoopCount ) . addReg ( LoopCount ) . addImm ( TripCountAdjust ) ;


<s> unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = ~ <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( I != LoopBB -> end ( ) && isEndLoopN ( I -> getOpcode ( ) ) ) { SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * LoopInst = findLoopInstr ( LoopBB , I -> getOpcode ( ) , I -> getOperand ( <NUM_LIT> ) . getMBB ( ) , VisitedBBs ) ; if ( LoopInst ) return std :: make_unique < <ISA_LIT>PipelinerLoopInfo > ( LoopInst , & * I ) ; }


<s> unsigned SizeA = getMemAccessSize ( MIa ) ; unsigned SizeB = getMemAccessSize ( MIb ) ; const MachineOperand & OffA = MIa . getOperand ( OffsetPosA ) ; const MachineOperand & OffB = MIb . getOperand ( OffsetPosB ) ; if ( ! MIa . getOperand ( OffsetPosA ) . isImm ( ) || ! MIb . getOperand ( OffsetPosB ) . isImm ( ) ) return false ; int OffsetA = isPostIncrement ( MIa ) ? <NUM_LIT> : OffA . getImm ( ) ; int OffsetB = isPostIncrement ( MIb ) ? <NUM_LIT> : OffB . getImm ( ) ; if ( OffsetA > OffsetB ) { uint64_t OffDiff = ( uint64_t ) ( ( int64_t ) OffsetA - ( int64_t ) OffsetB ) ; return SizeB <= OffDiff ;


<s> void <ISA_LIT>InstrInfo :: changeDuplexOpcode ( MachineBasicBlock :: instr_iterator MII , bool ToBigInstrs ) const { int Opcode = - <NUM_LIT> ; if ( ToBigInstrs ) {

if ( getDuplexCandidateGroup ( * MII ) ) Opcode = getDuplexOpcode ( * MII , ToBigInstrs ) ;


<s> int Opcode = - <NUM_LIT> ; if ( ToBigInstrs ) { if ( getDuplexCandidateGroup ( * MII ) ) Opcode = getDuplexOpcode ( * MII , ToBigInstrs ) ;

} else Opcode = getDuplexOpcode ( * MII , ToBigInstrs ) ;


<s> if ( ! MO . isDef ( ) ) continue ; const TargetRegisterClass * RC = HRI . getMinimalPhysRegClass ( MO . getReg ( ) ) ; if ( RC == & <STR_LIT> ) { Pred . push_back ( MO ) ; return true ; } continue ; } else if ( MO . isRegMask ( ) ) {


<s> Optional < bool > createTripCountGreaterCondition ( int TC , MachineBasicBlock & MBB , SmallVectorImpl < MachineOperand > & Cond ) override { if ( TripCount == - <NUM_LIT> ) { unsigned Done = TII -> createVR ( MF , <STR_LIT> ) ; MachineInstr * NewCmp = BuildMI ( & MBB , DL , TII -> get ( <STR_LIT> ) , Done ) . addReg ( LoopCount ) . addImm ( TC ) ; Cond . push_back ( MachineOperand :: CreateImm ( <STR_LIT> ) ) ;

Cond . push_back ( NewCmp -> getOperand ( <NUM_LIT> ) ) ;


<s> const TargetRegisterClass * TRC ; if ( VT == <STR_LIT> ) { TRC = & <STR_LIT> ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { TRC = & <STR_LIT> ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { TRC = & <STR_LIT> ;


<s> void disposed ( ) override { Loop -> eraseFromParent ( ) ;


<s> } for ( MachineBasicBlock * PB : BB -> predecessors ( ) ) { if ( ! Visited . insert ( PB ) . second ) continue ; if ( PB == BB ) continue ; for ( MachineInstr & I : llvm :: reverse ( PB -> instrs ( ) ) ) { unsigned Opc = I . getOpcode ( ) ; if ( Opc == LOOPi || Opc == LOOPr ) return & I ; if ( Opc == EndLoopOp && I . getOperand ( <NUM_LIT> ) . getMBB ( ) != TargetBB ) return nullptr ;


<s> if ( ( GA . getOpcode ( ) != <STR_LIT> ) || ( GB . getOpcode ( ) != <STR_LIT> ) ) return - <NUM_LIT> ; Register DestReg = GA . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! GB . readsRegister ( DestReg ) ) return - <NUM_LIT> ; if ( DestReg != <STR_LIT> && DestReg != <STR_LIT> ) return - <NUM_LIT> ; const MachineOperand & CmpOp = GA . getOperand ( <NUM_LIT> ) ; if ( ! CmpOp . isImm ( ) ) return - <NUM_LIT> ; int V = CmpOp . getImm ( ) ; if ( V == - <NUM_LIT> ) return DestReg == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( ! isUInt < <NUM_LIT> > ( V ) ) return - <NUM_LIT> ;


<s> int NVOpcode = <STR_LIT> ( MI . getOpcode ( ) ) ; if ( NVOpcode >= <NUM_LIT> ) return NVOpcode ; switch ( MI . getOpcode ( ) ) { default : report_fatal_error ( Twine ( <STR_LIT> ) + std :: to_string ( MI . getOpcode ( ) ) ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> int <ISA_LIT>InstrInfo :: getDuplexOpcode ( const MachineInstr & MI , bool ForBigCore ) const { static const std :: map < unsigned , unsigned > DupMap = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , } ; unsigned OpNum = MI . getOpcode ( ) ;


<s> bool atInsnStart = true ; unsigned Length = <NUM_LIT> ; const unsigned MaxInstLength = MAI . getMaxInstLength ( STI ) ; for ( ; * Str ; ++ Str ) { if ( * Str == '\n' || strncmp ( Str , MAI . getSeparatorString ( ) , strlen ( MAI . getSeparatorString ( ) ) ) == <NUM_LIT> ) atInsnStart = true ; if ( atInsnStart && ! isSpace ( static_cast < unsigned char > ( * Str ) ) ) { Length += MaxInstLength ; atInsnStart = false ; } if ( atInsnStart && strncmp ( Str , MAI . getCommentString ( ) . data ( ) , MAI . getCommentString ( ) . size ( ) ) == <NUM_LIT> ) atInsnStart = false ;


<s> SmallVector < std :: pair < MCPhysReg , const MachineOperand * > , <NUM_LIT> > Clobbers ; const MachineBasicBlock & B = * MI . getParent ( ) ; Regs . addLiveIns ( B ) ; auto E = MachineBasicBlock :: const_iterator ( MI . getIterator ( ) ) ;

for ( auto I = B . begin ( ) ; I != E ; ++ I ) {


<s> for ( auto I = B . begin ( ) ; I != E ; ++ I ) { Clobbers . clear ( ) ; Regs . stepForward ( * I , Clobbers ) ; }


<s> auto E = ++ MachineBasicBlock :: const_iterator ( MI . getIterator ( ) ) . getReverse ( ) ; for ( auto I = B . rbegin ( ) ; I != E ; ++ I ) Regs . stepBackward ( * I ) ;


<s> const MachineOperand * BaseOp = getBaseAndOffset ( LdSt , Offset , Width ) ;

if ( ! BaseOp || ! BaseOp -> isReg ( ) ) return false ;


<s> if ( DefMO . isReg ( ) && Register :: isPhysicalRegister ( DefMO . getReg ( ) ) ) { if ( DefMO . isImplicit ( ) ) { for ( MCSuperRegIterator SR ( DefMO . getReg ( ) , & HRI ) ; SR . isValid ( ) ; ++ SR ) { int Idx = DefMI . findRegisterDefOperandIdx ( * SR , false , false , & HRI ) ; if ( Idx != - <NUM_LIT> ) { DefIdx = Idx ; break ; } } } const MachineOperand & UseMO = UseMI . getOperand ( UseIdx ) ; if ( UseMO . isImplicit ( ) ) { for ( MCSuperRegIterator SR ( UseMO . getReg ( ) , & HRI ) ; SR . isValid ( ) ; ++ SR ) { int Idx = UseMI . findRegisterUseOperandIdx ( * SR , false , & HRI ) ; if ( Idx != - <NUM_LIT> ) { UseIdx = Idx ;


<s> const InstrStage & IS = * II . beginStage ( MI . getDesc ( ) . getSchedClass ( ) ) ; return IS . getUnits ( ) ;


<s> const InstrItineraryData & II = * Subtarget . getInstrItineraryData ( ) ; const InstrStage & IS = * II . beginStage ( MI . getDesc ( ) . getSchedClass ( ) ) ; return IS . getUnits ( ) ;


<s> <ISA_LIT>PipelinerLoopInfo ( MachineInstr * Loop , MachineInstr * EndLoop ) : Loop ( Loop ) , EndLoop ( EndLoop ) , MF ( Loop -> getParent ( ) -> getParent ( ) ) , TII ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ) , DL ( Loop -> getDebugLoc ( ) ) { TripCount = Loop -> getOpcode ( ) == <STR_LIT> ? - <NUM_LIT> : Loop -> getOperand ( <NUM_LIT> ) . getImm ( ) ;

if ( TripCount == - <NUM_LIT> ) LoopCount = Loop -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> <ISA_LIT>PipelinerLoopInfo ( MachineInstr * Loop , MachineInstr * EndLoop ) : Loop ( Loop ) , EndLoop ( EndLoop ) , MF ( Loop -> getParent ( ) -> getParent ( ) ) , TII ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ) , DL ( Loop -> getDebugLoc ( ) ) {

TripCount = Loop -> getOpcode ( ) == <STR_LIT> ? - <NUM_LIT> : Loop -> getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; SmallVector < unsigned , <NUM_LIT> > DefsA ; SmallVector < unsigned , <NUM_LIT> > DefsB ; SmallVector < unsigned , <NUM_LIT> > UsesA ; SmallVector < unsigned , <NUM_LIT> > UsesB ; parseOperands ( ProdMI , DefsA , UsesA ) ; parseOperands ( ConsMI , DefsB , UsesB ) ; for ( auto & RegA : DefsA ) for ( auto & RegB : UsesB ) { if ( RegA == RegB ) return true ; if ( Register :: isPhysicalRegister ( RegA ) ) for ( MCSubRegIterator SubRegs ( RegA , & HRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) if ( RegB == * SubRegs ) return true ;

if ( Register :: isPhysicalRegister ( RegB ) ) for ( MCSubRegIterator SubRegs ( RegB , & HRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) if ( RegA == * SubRegs ) return true ;


<s> SmallVector < unsigned , <NUM_LIT> > DefsA ; SmallVector < unsigned , <NUM_LIT> > DefsB ; SmallVector < unsigned , <NUM_LIT> > UsesA ; SmallVector < unsigned , <NUM_LIT> > UsesB ; parseOperands ( ProdMI , DefsA , UsesA ) ; parseOperands ( ConsMI , DefsB , UsesB ) ; for ( auto & RegA : DefsA ) for ( auto & RegB : UsesB ) { if ( RegA == RegB ) return true ; if ( Register :: isPhysicalRegister ( RegA ) ) for ( MCSubRegIterator SubRegs ( RegA , & HRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) if ( RegB == * SubRegs ) return true ; if ( Register :: isPhysicalRegister ( RegB ) ) for ( MCSubRegIterator SubRegs ( RegB , & HRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) if ( RegA == * SubRegs ) return true ; } return false ;


<s> unsigned SchedClass = MI . getDesc ( ) . getSchedClass ( ) ;

return is_TC4x ( SchedClass ) || is_TC3x ( SchedClass ) ;


<s> bool <ISA_LIT>InstrInfo :: isPureSlot0 ( const MachineInstr & MI ) const { if ( MI . getOpcode ( ) == <STR_LIT> ) return false ; unsigned FuncUnits = getUnits ( MI ) ; return <STR_LIT> ( FuncUnits ) ;


<s> const uint64_t F = MI . getDesc ( ) . TSFlags ;

return ( ( F >> <STR_LIT> ) & <STR_LIT> ) ;


<s> for ( auto I : MBB -> successors ( ) ) if ( I -> isEHPad ( ) ) return true ; } if ( MI . getDesc ( ) . isTerminator ( ) || MI . isPosition ( ) ) return true ;

if ( MI . getOpcode ( ) == TargetOpcode :: INLINEASM_BR ) return true ;


<s> } if ( mayBeNewStore ( MI2 ) ) if ( MI2 . getOpcode ( ) == <STR_LIT> ) if ( MI1 . getOperand ( <NUM_LIT> ) . isReg ( ) && MI2 . getOperand ( <NUM_LIT> ) . isReg ( ) && MI1 . getOperand ( <NUM_LIT> ) . getReg ( ) == MI2 . getOperand ( <NUM_LIT> ) . getReg ( ) ) return true ; return false ;


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) {


<s> Uses . clear ( ) ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; if ( MO . isUse ( ) ) Uses . push_back ( MO . getReg ( ) ) ; if ( MO . isDef ( ) ) Defs . push_back ( MO . getReg ( ) ) ;


<s> Uses . clear ( ) ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; Register Reg = MO . getReg ( ) ;


<s> NewPreheader -> splice ( NewPreheader -> getFirstTerminator ( ) , Loop -> getParent ( ) , Loop ) ;


<s> void setPreheader ( MachineBasicBlock * NewPreheader ) override { NewPreheader -> splice ( NewPreheader -> getFirstTerminator ( ) , Loop -> getParent ( ) , Loop ) ;


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else { llvm_unreachable ( <STR_LIT> ) ; }


<s> return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = ~ <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = <NUM_LIT> ; break ; } switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Value = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( ! MO . isDef ( ) ) continue ; const TargetRegisterClass * RC = HRI . getMinimalPhysRegClass ( MO . getReg ( ) ) ; if ( RC == & <STR_LIT> ) { Pred . push_back ( MO ) ; return true ; } continue ; } else if ( MO . isRegMask ( ) ) { for ( unsigned PR : <STR_LIT> ) { if ( ! MI . modifiesRegister ( PR , & HRI ) ) continue ; Pred . push_back ( MO ) ; return true ;


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> static const std :: map < unsigned , unsigned > DupMap = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , } ; unsigned OpNum = MI . getOpcode ( ) ; if ( ForBigCore ) { auto Iter = DupMap . find ( OpNum ) ; if ( Iter != DupMap . end ( ) ) return Iter -> second ; } else { for ( const auto & Iter : DupMap ) if ( Iter . second == OpNum ) return Iter . first ; } return - <NUM_LIT> ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; }


<s> MCInst <ISA_LIT>InstrInfo :: getNop ( ) const { static const MCInst Nop = MCInstBuilder ( <STR_LIT> ) ;

return MCInstBuilder ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addInst ( & Nop ) ;


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) { auto Op = MI . getOperand ( <NUM_LIT> ) ; if ( Op . getType ( ) == MachineOperand :: MO_GlobalAddress ) return false ;