<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; } SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> ) ; SDValue Ops [ ] = { Address , Predicate , Base , Modifier , Offset , Chain } ;

SDNode * Result = CurDAG -> getMachineNode ( Opcode , dl , VTs , Ops ) ;


<s> SmallVector < SDNode * , <NUM_LIT> > Loads ; SetVector < SDNode * > WorkQ ; auto IsLoadToSelect = [ ] ( SDNode * N ) { if ( ! N -> isMachineOpcode ( ) && N -> getOpcode ( ) == <STR_LIT> ) { SDValue Addr = cast < LoadSDNode > ( N ) -> getBasePtr ( ) ; unsigned AddrOpc = Addr . getOpcode ( ) ; if ( AddrOpc == <STR_LIT> || AddrOpc == <STR_LIT> ) if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return true ; } return false ; } ; WorkQ . insert ( N ) ; for ( unsigned i = <NUM_LIT> ; i != WorkQ . size ( ) ; ++ i ) {


<s> OpRef R = shuffp1 ( ShuffleMask ( MaskR ) , Vb , Results ) ; if ( ! L . isValid ( ) || ! R . isValid ( ) ) return OpRef :: fail ( ) ; SmallVector < uint8_t , <NUM_LIT> > Bytes ( VecLen ) ; for ( int I = <NUM_LIT> ; I != VecLen ; ++ I ) { if ( MaskL [ I ] != - <NUM_LIT> ) Bytes [ I ] = <NUM_LIT> ; }

return vmuxp ( Bytes , L , R , Results ) ;


<s> for ( int Idx : Mask ) { if ( Idx == - <NUM_LIT> ) return false ; Sum += Idx ; } int N = Mask . size ( ) ;

return <NUM_LIT> * Sum == N * ( N - <NUM_LIT> ) ;


<s> } if ( ! HasUnused ) return Va ; SDValue B = getVectorConstant ( UsedBytes , SDLoc ( Results . InpNode ) ) ; Results . push ( <STR_LIT> , getSingleVT ( <STR_LIT> ) , { Va , OpRef ( B ) } ) ;

return OpRef :: res ( Results . top ( ) ) ;


<s> FirstQ . insert ( Q . begin ( ) , Q . end ( ) ) ; } ; for ( Node N : Needed ) Enqueue ( N ) ; for ( Node N : FirstQ ) { if ( Colors . count ( N ) ) continue ; NodeSet & Ns = Edges [ N ] ; auto P = getUniqueColor ( Ns ) ; if ( ! P . first ) return false ; Colors [ N ] = other ( P . second ) ; } for ( auto E : Edges ) { Node N = E . first ; if ( ! Needed . count ( conj ( N ) ) || Colors . count ( N ) ) continue ; auto P = getUniqueColor ( E . second ) ; if ( ! P . first ) return false ; Colors [ N ] = other ( P . second ) ; } std :: vector < Node > WorkQ ; for ( auto E : Edges ) { Node N = E . first ; if ( ! Colors . count ( N ) ) WorkQ . push_back ( N ) ; } for ( Node N : WorkQ ) { NodeSet & Ns = Edges [ N ] ; auto P = getUniqueColor ( Ns ) ; if ( P . first ) { Colors [ N ] = other ( P . second ) ; continue ; } Node C = conj ( N ) ; ColorKind ColorN = other ( ColorKind :: None ) ; ColorKind ColorC = other ( ColorN ) ; NodeSet & Cs = Edges [ C ] ; NodeSet CopyNs = Ns ; for ( Node M : CopyNs ) { ColorKind ColorM = getColor ( M ) ; if ( ColorM == ColorC ) { Cs . insert ( M ) ; Edges [ M ] . insert ( C ) ; Ns . erase ( M ) ; Edges [ M ] . erase ( N ) ;


<s>
for
(
Node
P
:
Order
)
{
if
(
P
!=
Ignore
)
dbgs
(
)
<<
' '
<<
P
;
else
dbgs
(
)
<<
<STR_LIT>
;
}
dbgs
(
)
<<
<STR_LIT>
;
dbgs
(
)
<<
<STR_LIT>
;
for
(
Node
N
:
Needed
)
dbgs
(
)
<<
' '
<<
N
;
dbgs
(
)
<<
<STR_LIT>
;
dbgs
(
)
<<
<STR_LIT>
;
for
(
auto
E
:
Edges
)
{
dbgs
(
)
<<
<STR_LIT>
<<
E
.
first
<<
<STR_LIT>
;
for
(
auto
N
:
E
.
second
)
dbgs
(
)
<<
' '
<<
N
;
dbgs
(
)
<<
<STR_LIT>
;
}
dbgs
(
)
<<
<STR_LIT>
;
auto
ColorKindToName
=
[
]
(
ColorKind
C
)
{
switch
(
C
)
{
case
ColorKind
::
:


<s>
for
(
Node
P
:
Order
)
{
if
(
P
!=
Ignore
)
dbgs
(
)
<<
' '
<<
P
;
else
dbgs
(
)
<<
<STR_LIT>
;
}
dbgs
(
)
<<
<STR_LIT>
;
dbgs
(
)
<<
<STR_LIT>
;
for
(
Node
N
:
Needed
)
dbgs
(
)
<<
' '
<<
N
;
dbgs
(
)
<<
<STR_LIT>
;
dbgs
(
)
<<
<STR_LIT>
;
for
(
auto
E
:
Edges
)
{
dbgs
(
)
<<
<STR_LIT>
<<
E
.
first
<<
<STR_LIT>
;
for
(
auto
N
:
E
.
second
)
dbgs
(
)
<<
' '
<<
N
;
dbgs
(
)
<<
<STR_LIT>
;
}
dbgs
(
)
<<
<STR_LIT>
;
auto
ColorKindToName
=
[
]
(
ColorKind
C
)
{
switch
(
C
)
{
case
ColorKind
::
:
return
<STR_LIT>
;
case
ColorKind
::
Red
:
return
<STR_LIT>
;
case
ColorKind
::
Black
:
return
<STR_LIT>
;
}
llvm_unreachable
(
<STR_LIT>
)
;


<s> assert ( isPowerOf2_32 ( SegLen ) ) ; SmallVector < unsigned , <NUM_LIT> > SegList ; if ( SM . MaxSrc == - <NUM_LIT> ) return SegList ; unsigned Shift = Log2_32 ( SegLen ) ; BitVector Segs ( alignTo ( SM . MaxSrc + <NUM_LIT> , SegLen ) >> Shift ) ; for ( int M : SM . Mask ) { if ( M >= <NUM_LIT> ) Segs . set ( M >> Shift ) ; } for ( unsigned B : Segs . set_bits ( ) ) SegList . push_back ( B ) ;


<s> assert ( isPowerOf2_32 ( SegLen ) ) ; SmallVector < unsigned , <NUM_LIT> > SegList ; if ( SM . MaxSrc == - <NUM_LIT> ) return SegList ; unsigned Shift = Log2_32 ( SegLen ) ; BitVector Segs ( alignTo ( SM . MaxSrc + <NUM_LIT> , SegLen ) >> Shift ) ; for ( int M : SM . Mask ) { if ( M >= <NUM_LIT> ) Segs . set ( M >> Shift ) ;


<s> Opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; } SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> ) ; SDValue Ops [ ] = { Address , ImmOperand , Base , Modifier , Offset , Chain } ; SDNode * Result = CurDAG -> getMachineNode ( Opcode , dl , VTs , Ops ) ; MachineMemOperand * MemOp = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( Result ) , { MemOp } ) ;


<s> case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; } SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> ) ; SDValue Ops [ ] = { Address , ImmOperand , Predicate , Base , Modifier , Offset , Chain } ; SDNode * Result = CurDAG -> getMachineNode ( Opcode , dl , VTs , Ops ) ; MachineMemOperand * MemOp = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ;

CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( Result ) , { MemOp } ) ;


<s> ShuffleMask ( ArrayRef < int > M ) : Mask ( M ) { for ( int M : Mask ) {


<s> return G . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> BenesNetwork ( ArrayRef < ElemType > Ord ) : PermNetwork ( Ord , <NUM_LIT> ) {


<s> } } for ( unsigned I = <NUM_LIT> ; I != Order . size ( ) ; ++ I ) { if ( ! Needed . count ( I ) ) continue ; Node C = conj ( I ) ;


<s> if ( PC != Ignore && PC != I ) Edges [ I ] . insert ( PC ) ; } } for ( unsigned I = <NUM_LIT> ; I != Order . size ( ) ; ++ I ) { if ( ! Needed . count ( I ) ) continue ;


<s> const SDLoc & dl ( Results . InpNode ) ; int VecLen = SM . Mask . size ( ) ; for ( int M : SM . Mask ) { if ( M != - <NUM_LIT> && M >= VecLen ) return OpRef :: fail ( ) ; } ForwardDeltaNetwork FN ( SM . Mask ) ; if ( FN . run ( FC ) ) { SDValue Ctl = getVectorConstant ( FC , dl ) ; Results . push ( <STR_LIT> , ResTy , { Va , OpRef ( Ctl ) } ) ; return OpRef :: res ( Results . top ( ) ) ; } ReverseDeltaNetwork RN ( SM . Mask ) ; if ( RN . run ( RC ) ) { SDValue Ctl = getVectorConstant ( RC , dl ) ;


<s> if ( ! P . first ) return false ; Colors [ N ] = other ( P . second ) ; } for ( auto E : Edges ) { Node N = E . first ; if ( ! Needed . count ( conj ( N ) ) || Colors . count ( N ) ) continue ; auto P = getUniqueColor ( E . second ) ; if ( ! P . first ) return false ; Colors [ N ] = other ( P . second ) ; } std :: vector < Node > WorkQ ; for ( auto E : Edges ) { Node N = E . first ; if ( ! Colors . count ( N ) ) WorkQ . push_back ( N ) ; } for ( unsigned I = <NUM_LIT> ; I < WorkQ . size ( ) ; ++ I ) { Node N = WorkQ [ I ] ;


<s> NodeSet & Ns = Edges [ N ] ; auto P = getUniqueColor ( Ns ) ; if ( P . first ) { Colors [ N ] = other ( P . second ) ; continue ; } Node C = conj ( N ) ; ColorKind ColorN = other ( ColorKind :: None ) ; ColorKind ColorC = other ( ColorN ) ; NodeSet & Cs = Edges [ C ] ; NodeSet CopyNs = Ns ; for ( Node M : CopyNs ) { ColorKind ColorM = getColor ( M ) ; if ( ColorM == ColorC ) { Cs . insert ( M ) ; Edges [ M ] . insert ( C ) ; Ns . erase ( M ) ; Edges [ M ] . erase ( N ) ; } } Colors [ N ] = ColorN ; Colors [ C ] = ColorC ; }

for ( unsigned I = <NUM_LIT> ; I != Order . size ( ) ; ++ I ) if ( Colors . count ( I ) == <NUM_LIT> ) Colors [ I ] = ColorKind :: None ;


<s> if ( ! color ( ) ) Colors . clear ( ) ;


<s> const MapType & colors ( ) const { return Colors ;


<s> Results . push ( TargetOpcode :: REG_SEQUENCE , getPairVT ( <STR_LIT> ) , {

DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , Lo , DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , Hi , DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , } ) ;


<s> return ( Pos < Num / <NUM_LIT> ) ? Pos + Num / <NUM_LIT> : Pos - Num / <NUM_LIT> ;


<s> int NextInMask = SM . Mask [ Strip . second ] ; if ( NextInMask < VecLen ) { if ( Strip . first == <NUM_LIT> && Strip . second == <NUM_LIT> && NextInMask == <NUM_LIT> ) { int N = VecLen ; for ( int I = <NUM_LIT> ; I != N / <NUM_LIT> ; ++ I ) if ( SM . Mask [ I ] != <NUM_LIT> * I ) return OpRef :: fail ( ) ; for ( int I = <NUM_LIT> ; I != N / <NUM_LIT> ; ++ I ) if ( SM . Mask [ I + N / <NUM_LIT> ] != <NUM_LIT> + <NUM_LIT> * I ) return OpRef :: fail ( ) ; for ( int I = <NUM_LIT> ; I != N / <NUM_LIT> ; ++ I ) if ( SM . Mask [ I + N / <NUM_LIT> ] != N + <NUM_LIT> * I ) return OpRef :: fail ( ) ; for ( int I = <NUM_LIT> ; I != N / <NUM_LIT> ; ++ I ) if ( SM . Mask [ I + <NUM_LIT> * N / <NUM_LIT> ] != N + <NUM_LIT> + <NUM_LIT> * I ) return OpRef :: fail ( ) ; Results . push ( <STR_LIT> , ResTy , { Vb , Va } ) ; return OpRef :: res ( Results . top ( ) ) ; } int N = VecLen ; int L = Strip . second ; if ( Strip . first != <NUM_LIT> && Strip . first != L ) return OpRef :: fail ( ) ; for ( int I = L ; I < N ; I += L ) { auto S = findStrip ( SM . Mask . drop_front ( I ) , <NUM_LIT> , N - I ) ; if ( S . first - Strip . first != <NUM_LIT> * I ) return OpRef :: fail ( ) ; if ( S . second != unsigned ( L ) ) return OpRef :: fail ( ) ; } assert ( Strip . first == <NUM_LIT> || Strip . first == L ) ;


<s> if ( Strip . first == <NUM_LIT> && Strip . second == <NUM_LIT> && NextInMask == <NUM_LIT> ) { int N = VecLen ; for ( int I = <NUM_LIT> ; I != N / <NUM_LIT> ; ++ I ) if ( SM . Mask [ I ] != <NUM_LIT> * I ) return OpRef :: fail ( ) ; for ( int I = <NUM_LIT> ; I != N / <NUM_LIT> ; ++ I ) if ( SM . Mask [ I + N / <NUM_LIT> ] != <NUM_LIT> + <NUM_LIT> * I ) return OpRef :: fail ( ) ; for ( int I = <NUM_LIT> ; I != N / <NUM_LIT> ; ++ I ) if ( SM . Mask [ I + N / <NUM_LIT> ] != N + <NUM_LIT> * I ) return OpRef :: fail ( ) ; for ( int I = <NUM_LIT> ; I != N / <NUM_LIT> ; ++ I ) if ( SM . Mask [ I + <NUM_LIT> * N / <NUM_LIT> ] != N + <NUM_LIT> + <NUM_LIT> * I ) return OpRef :: fail ( ) ; Results . push ( <STR_LIT> , ResTy , { Vb , Va } ) ; return OpRef :: res ( Results . top ( ) ) ; } int N = VecLen ; int L = Strip . second ; if ( Strip . first != <NUM_LIT> && Strip . first != L ) return OpRef :: fail ( ) ; for ( int I = L ; I < N ; I += L ) { auto S = findStrip ( SM . Mask . drop_front ( I ) , <NUM_LIT> , N - I ) ; if ( S . first - Strip . first != <NUM_LIT> * I ) return OpRef :: fail ( ) ; if ( S . second != unsigned ( L ) ) return OpRef :: fail ( ) ; } assert ( Strip . first == <NUM_LIT> || Strip . first == L ) ; using namespace <ISA_LIT> ;


<s> uint8_t ctl ( ElemType Pos , unsigned Step ) const {


<s>
for
(
Node
N
:
Needed
)
dbgs
(
)
<<
' '
<<
N
;
dbgs
(
)
<<
<STR_LIT>
;
dbgs
(
)
<<
<STR_LIT>
;
for
(
auto
E
:
Edges
)
{
dbgs
(
)
<<
<STR_LIT>
<<
E
.
first
<<
<STR_LIT>
;
for
(
auto
N
:
E
.
second
)
dbgs
(
)
<<
' '
<<
N
;
dbgs
(
)
<<
<STR_LIT>
;
}
dbgs
(
)
<<
<STR_LIT>
;
auto
ColorKindToName
=
[
]
(
ColorKind
C
)
{
switch
(
C
)
{
case
ColorKind
::
:
return
<STR_LIT>
;


<s> BaseType :: const_iterator end ( ) const {


<s> for ( int I = L ; I < <NUM_LIT> * N ; I += <NUM_LIT> * L ) { auto S = findStrip ( SM . Mask . drop_front ( I ) , <NUM_LIT> , N - I ) ; if ( S . first != - <NUM_LIT> || S . second != unsigned ( L ) ) return OpRef :: fail ( ) ; } unsigned Opc = Strip . second == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; Results . push ( Opc , getPairVT ( <STR_LIT> ) , { Va } ) ; return OpRef :: res ( Results . top ( ) ) ;


<s> DEBUG_WITH_TYPE ( <STR_LIT> , { dbgs ( ) << __func__ << '\n' ; } ) ; int VecLen = SM . Mask . size ( ) ; assert ( <NUM_LIT> * HwLen == unsigned ( VecLen ) && <STR_LIT> ) ; std :: pair < int , unsigned > Strip = findStrip ( SM . Mask , <NUM_LIT> , VecLen ) ; if ( Strip . first != <NUM_LIT> ) return OpRef :: fail ( ) ; if ( Strip . second != <NUM_LIT> && Strip . second != <NUM_LIT> ) return OpRef :: fail ( ) ; int N = VecLen ; int L = Strip . second ; for ( int I = <NUM_LIT> * L ; I < <NUM_LIT> * N ; I += <NUM_LIT> * L ) { auto S = findStrip ( SM . Mask . drop_front ( I ) , <NUM_LIT> , N - I ) ; if ( S . second != unsigned ( L ) ) return OpRef :: fail ( ) ; if ( <NUM_LIT> * S . first != I ) return OpRef :: fail ( ) ; } for ( int I = L ; I < <NUM_LIT> * N ; I += <NUM_LIT> * L ) { auto S = findStrip ( SM . Mask . drop_front ( I ) , <NUM_LIT> , N - I ) ; if ( S . first != - <NUM_LIT> || S . second != unsigned ( L ) ) return OpRef :: fail ( ) ; } unsigned Opc = Strip . second == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; Results . push ( Opc , getPairVT ( <STR_LIT> ) , { Va } ) ; return OpRef :: res ( Results . top ( ) ) ;


<s> int F = A [ <NUM_LIT> ] ; int E = F ; for ( unsigned I = <NUM_LIT> ; I != MaxLen ; ++ I ) { if ( A [ I ] - E != Inc ) return { F , I } ;


<s> ForwardDeltaNetwork ( ArrayRef < ElemType > Ord ) : PermNetwork ( Ord ) {


return F != Colors . end ( ) ? F -> second : ColorKind :: None ;


<s> auto F = Colors . find ( N ) ; return F != Colors . end ( ) ? F -> second : ColorKind :: None ;


<s> if ( Dir == Forward ) W |= C << ( Log - <NUM_LIT> - L ) ; else W |= C << L ; } assert ( isUInt < <NUM_LIT> > ( W ) ) ; V [ I ] = uint8_t ( W ) ;


<s> MVT getPairVT ( MVT ElemTy ) const { unsigned NumElems = ( <NUM_LIT> * HwLen ) / ( ElemTy . getSizeInBits ( ) / <NUM_LIT> ) ; return <STR_LIT> ( ElemTy , NumElems ) ;


<s> unsigned NumElems = HwLen / ( ElemTy . getSizeInBits ( ) / <NUM_LIT> ) ;

return <STR_LIT> ( ElemTy , NumElems ) ;


<s> if ( ColorN == ColorKind :: None ) continue ; if ( Color == ColorKind :: None ) Color = ColorN ;

else if ( Color != ColorKind :: None && Color != ColorN ) return { false , ColorKind :: None } ;


<s> if ( Color == ColorKind :: None ) Color = ColorN ; else if ( Color != ColorKind :: None && Color != ColorN ) return { false , ColorKind :: None } ;


<s> return ShuffleMask ( Mask . take_back ( H ) ) ;


<s> HvxSelector ( <ISA_LIT>DAGToDAGISel & HS , SelectionDAG & G ) : Lower ( get<ISA_LIT>Lowering ( G ) ) , ISel ( HS ) , DAG ( G ) , HST ( get<ISA_LIT>Subtarget ( G ) ) , HwLen ( HST . getVectorLength ( ) ) {


if ( M >= <NUM_LIT> && M != I ) return false ;


<s> int N = Mask . size ( ) ; return <NUM_LIT> * Sum == N * ( N - <NUM_LIT> ) ;


<s> int Sum = <NUM_LIT> ; for ( int Idx : Mask ) { if ( Idx == - <NUM_LIT> ) return false ; Sum += Idx ; } int N = Mask . size ( ) ;


<s> static bool isUndef ( ArrayRef < int > Mask ) {

for ( int Idx : Mask ) if ( Idx != - <NUM_LIT> ) return false ;


<s> bool isValue ( ) const { return OpV . getNode ( ) != nullptr ;


<s> return ShuffleMask ( Mask . take_front ( H ) ) ;


<s> ShuffleMask lo ( ) const { size_t H = Mask . size ( ) / <NUM_LIT> ; return ShuffleMask ( Mask . take_front ( H ) ) ;


<s> unsigned Part = R . OpN & OpRef :: Whole ; int Idx = SignExtend32 ( R . OpN & OpRef :: Index , OpRef :: IndexBits ) ; if ( Idx < <NUM_LIT> ) Idx += I ; assert ( Idx >= <NUM_LIT> && unsigned ( Idx ) < Output . size ( ) ) ; SDValue Op = Output [ Idx ] ; MVT OpTy = Op . getValueType ( ) . getSimpleVT ( ) ; if ( Part != OpRef :: Whole ) { assert ( Part == OpRef :: LoHalf || Part == OpRef :: HiHalf ) ; MVT HalfTy = <STR_LIT> ( OpTy . getVectorElementType ( ) , OpTy . getVectorNumElements ( ) / <NUM_LIT> ) ; unsigned Sub = ( Part == OpRef :: LoHalf ) ? <STR_LIT> : <STR_LIT> ; Op = DAG . getTargetExtractSubreg ( Sub , dl , HalfTy , Op ) ; } Ops . push_back ( Op ) ; } assert ( Node . Ty != <STR_LIT> ) ;

SDNode * ResN = ( Node . Opc == TargetOpcode :: COPY ) ? Ops . front ( ) . getNode ( ) : DAG . getMachineNode ( Node . Opc , dl , Node . Ty , Ops ) ;


<s> if ( Color == ColorKind :: None ) return ColorKind :: Red ; return Color == ColorKind :: Red ? ColorKind :: Black : ColorKind :: Red ;


<s> uint8_t HalfIdx [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; unsigned Idx = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != <NUM_LIT> ; ++ I ) { if ( ( HalfMask & ( <NUM_LIT> << I ) ) == <NUM_LIT> ) continue ; assert ( Idx < <NUM_LIT> ) ; OpRef Op = Inp [ I / <NUM_LIT> ] ; Out [ Idx ] = ( I & <NUM_LIT> ) ? OpRef :: hi ( Op ) : OpRef :: lo ( Op ) ; HalfIdx [ I ] = Idx ++ ; } int VecLen = SM . Mask . size ( ) ; for ( int I = <NUM_LIT> ; I != VecLen ; ++ I ) { int M = SM . Mask [ I ] ; if ( M >= <NUM_LIT> ) { uint8_t Idx = HalfIdx [ M >> LogHw ] ; assert ( Idx == <NUM_LIT> || Idx == <NUM_LIT> ) ;

M = ( M & ( HwLen - <NUM_LIT> ) ) + HwLen * Idx ;


<s> Va = Vb ; MinSrc = SM . MinSrc - HwLen ; } const SDLoc & dl ( Results . InpNode ) ; if ( isUInt < <NUM_LIT> > ( MinSrc ) || isUInt < <NUM_LIT> > ( HwLen - MinSrc ) ) { bool IsRight = isUInt < <NUM_LIT> > ( MinSrc ) ; SDValue S = DAG . getTargetConstant ( IsRight ? MinSrc : HwLen - MinSrc , dl , <STR_LIT> ) ; unsigned Opc = IsRight ? <STR_LIT> : <STR_LIT> ; Results . push ( Opc , Ty , { Vb , Va , S } ) ; } else { SDValue S = DAG . getTargetConstant ( MinSrc , dl , <STR_LIT> ) ; Results . push ( <STR_LIT> , <STR_LIT> , { S } ) ; unsigned Top = Results . top ( ) ; Results . push ( <STR_LIT> , Ty , { Vb , Va , OpRef :: res ( Top ) } ) ; } for ( int I = <NUM_LIT> ; I != VecLen ; ++ I ) { int M = SM . Mask [ I ] ; if ( M != - <NUM_LIT> ) M -= SM . MinSrc ; NewMask [ I ] = M ; } return OpRef :: res ( Results . top ( ) ) ; } if ( Options & PackMux ) { BitVector Picked ( HwLen ) ; SmallVector < uint8_t , <NUM_LIT> > MuxBytes ( HwLen ) ; bool CanMux = true ; for ( int I = <NUM_LIT> ; I != VecLen ; ++ I ) { int M = SM . Mask [ I ] ; if ( M == - <NUM_LIT> ) continue ;


<s> if ( M != - <NUM_LIT> ) M -= HwLen ; NewMask [ I ] = M ; } return Vb ; } } int MinSrc = SM . MinSrc ; if ( SM . MaxSrc < int ( HwLen ) ) { Vb = Va ; } else if ( SM . MinSrc > int ( HwLen ) ) { Va = Vb ; MinSrc = SM . MinSrc - HwLen ; } const SDLoc & dl ( Results . InpNode ) ; if ( isUInt < <NUM_LIT> > ( MinSrc ) || isUInt < <NUM_LIT> > ( HwLen - MinSrc ) ) { bool IsRight = isUInt < <NUM_LIT> > ( MinSrc ) ; SDValue S = DAG . getTargetConstant ( IsRight ? MinSrc : HwLen - MinSrc , dl , <STR_LIT> ) ; unsigned Opc = IsRight ? <STR_LIT> : <STR_LIT> ; Results . push ( Opc , Ty , { Vb , Va , S } ) ; } else { SDValue S = DAG . getTargetConstant ( MinSrc , dl , <STR_LIT> ) ; Results . push ( <STR_LIT> , <STR_LIT> , { S } ) ; unsigned Top = Results . top ( ) ; Results . push ( <STR_LIT> , Ty , { Vb , Va , OpRef :: res ( Top ) } ) ; } for ( int I = <NUM_LIT> ; I != VecLen ; ++ I ) { int M = SM . Mask [ I ] ; if ( M != - <NUM_LIT> ) M -= SM . MinSrc ; NewMask [ I ] = M ; } return OpRef :: res ( Results . top ( ) ) ; } if ( Options & PackMux ) { BitVector Picked ( HwLen ) ; SmallVector < uint8_t , <NUM_LIT> > MuxBytes ( HwLen ) ; bool CanMux = true ; for ( int I = <NUM_LIT> ; I != VecLen ; ++ I ) { int M = SM . Mask [ I ] ; if ( M == - <NUM_LIT> ) continue ; if ( M >= int ( HwLen ) ) M -= HwLen ; else MuxBytes [ M ] = <NUM_LIT> ; if ( Picked [ M ] ) { CanMux = false ; break ; } NewMask [ I ] = M ;


<s> assert ( VecLen > <NUM_LIT> ) ; for ( unsigned I = VecLen ; I >= <NUM_LIT> ; I >>= <NUM_LIT> ) { unsigned X = XorPow2 ( SM . Mask , I ) ; if ( ! isPowerOf2_32 ( X ) ) return OpRef :: fail ( ) ; for ( int J = I ; J < VecLen ; J += I ) { if ( XorPow2 ( SM . Mask . slice ( J , I ) , I ) != X ) return OpRef :: fail ( ) ; } Perm [ Log2_32 ( X ) ] = Log2_32 ( I ) - <NUM_LIT> ; } using CycleType = SmallVector < unsigned , <NUM_LIT> > ; std :: set < CycleType > Cycles ; std :: set < unsigned > All ; for ( unsigned I : Perm ) All . insert ( I ) ; auto canonicalize = [ LogLen ] ( const CycleType & C ) -> CycleType { unsigned LogPos , N = C . size ( ) ; for ( LogPos = <NUM_LIT> ; LogPos != N ; ++ LogPos ) if ( C [ LogPos ] == LogLen - <NUM_LIT> ) break ; if ( LogPos == N ) return C ; CycleType NewC ( C . begin ( ) + LogPos , C . end ( ) ) ; NewC . append ( C . begin ( ) , C . begin ( ) + LogPos ) ; return NewC ; } ; auto pfs = [ ] ( const std :: set < CycleType > & Cs , unsigned Len ) { if ( Cs . size ( ) != <NUM_LIT> ) return <NUM_LIT> ; const CycleType & C = * Cs . begin ( ) ; if ( C [ <NUM_LIT> ] != Len - <NUM_LIT> ) return <NUM_LIT> ; int D = Len - C . size ( ) ; if ( D != <NUM_LIT> && D != <NUM_LIT> ) return <NUM_LIT> ; bool IsDeal = true , IsShuff = true ; for ( unsigned I = <NUM_LIT> ; I != Len - D ; ++ I ) { if ( C [ I ] != Len - <NUM_LIT> - I ) IsDeal = false ; if ( C [ I ] != I - ( <NUM_LIT> - D ) ) IsShuff = false ; } assert ( ! ( IsDeal || IsShuff ) || IsDeal != IsShuff ) ; static unsigned Deals [ ] = { <STR_LIT> , <STR_LIT> } ; static unsigned Shufs [ ] = { <STR_LIT> , <STR_LIT> } ; return IsDeal ? Deals [ D ] : ( IsShuff ? Shufs [ D ] : <NUM_LIT> ) ; } ;


<s> Table . resize ( Order . size ( ) ) ; for ( RowType & Row : Table ) Row . resize ( Mult * Log , None ) ;


<s>
void
print
(
raw_ostream
&
OS
)
const
{
OS
<<
<STR_LIT>
<<
MinSrc
<<
<STR_LIT>
<<
MaxSrc
<<
<STR_LIT>
;
for
(
int
M
:
Mask
)
OS
<<
' '
<<
M
;


<s> unsigned push ( unsigned Opc , MVT Ty , std :: vector < OpRef > && Ops ) { NodeTemplate Res ; Res . Opc = Opc ; Res . Ty = Ty ;


<s> return OpRef ( Whole | ( N & Index ) ) ;


<s> unsigned reset ( unsigned NewTop ) {


<s> List . resize ( NewTop + <NUM_LIT> ) ;


<s> ResultStack ( SDNode * Inp ) : InpNode ( Inp ) , InpTy ( Inp -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ) {


<s> ReverseDeltaNetwork ( ArrayRef < ElemType > Ord ) : PermNetwork ( Ord ) {


<s> const Coloring :: MapType & M = G . colors ( ) ; if ( M . empty ( ) ) return false ; ElemType Num = Size ; unsigned Pets = <NUM_LIT> * Log - <NUM_LIT> - Step ; bool UseUp = false , UseDown = false ; ColorKind ColorUp = ColorKind :: None ; for ( ElemType J = <NUM_LIT> ; J != Num ; ++ J ) { ElemType I = P [ J ] ; if ( I == Ignore ) continue ; ColorKind C = M . at ( I ) ; if ( C == ColorKind :: None ) continue ; if ( ColorUp == ColorKind :: None ) { ColorUp = ( I < Num / <NUM_LIT> ) ? ColorKind :: Red : ColorKind :: Black ; } unsigned CI = ( I < Num / <NUM_LIT> ) ? I + Num / <NUM_LIT> : I - Num / <NUM_LIT> ;


<s> bool BenesNetwork :: route ( ElemType * P , RowType * T , unsigned Size , unsigned Step ) { Coloring G ( { P , Size } ) ; const Coloring :: MapType & M = G . colors ( ) ; if ( M . empty ( ) ) return false ; ElemType Num = Size ; unsigned Pets = <NUM_LIT> * Log - <NUM_LIT> - Step ; bool UseUp = false , UseDown = false ; ColorKind ColorUp = ColorKind :: None ; for ( ElemType J = <NUM_LIT> ; J != Num ; ++ J ) { ElemType I = P [ J ] ; if ( I == Ignore ) continue ; ColorKind C = M . at ( I ) ; if ( C == ColorKind :: None ) continue ; if ( ColorUp == ColorKind :: None ) { ColorUp = ( I < Num / <NUM_LIT> ) ? ColorKind :: Red : ColorKind :: Black ; } unsigned CI = ( I < Num / <NUM_LIT> ) ? I + Num / <NUM_LIT> : I - Num / <NUM_LIT> ; if ( C == ColorUp ) { if ( I < Num / <NUM_LIT> ) T [ I ] [ Step ] = Pass ; else T [ CI ] [ Step ] = Switch ; T [ J ] [ Pets ] = ( J < Num / <NUM_LIT> ) ? Pass : Switch ; UseUp = true ; } else {

if ( I < Num / <NUM_LIT> ) T [ CI ] [ Step ] = Switch ;


<s> bool run ( Controls & F , Controls & R ) { if ( ! route ( Order . data ( ) , Table . data ( ) , size ( ) , <NUM_LIT> ) ) return false ; getControls ( F , <NUM_LIT> , Forward ) ;


<s> if ( HavePairs ) { if ( M < HwLen ) { Vec = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , SingleTy , Vec ) ; } else { Vec = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , SingleTy , Vec ) ; M -= HwLen ; } } SDValue Idx = DAG . getConstant ( M , dl , <STR_LIT> ) ; SDValue Ex = DAG . getNode ( <STR_LIT> , dl , ElemTy , { Vec , Idx } ) ; SDValue L = Lower . LowerOperation ( Ex , DAG ) ; assert ( L . getNode ( ) ) ; Ops . push_back ( L ) ; } SDValue LV ; if ( <NUM_LIT> * HwLen == VecLen ) { SDValue B0 = DAG . getBuildVector ( SingleTy , dl , { Ops . data ( ) , HwLen } ) ; SDValue L0 = Lower . LowerOperation ( B0 , DAG ) ; SDValue B1 = DAG . getBuildVector ( SingleTy , dl , { Ops . data ( ) + HwLen , HwLen } ) ; SDValue L1 = Lower . LowerOperation ( B1 , DAG ) ; LV = DAG . getNode ( <STR_LIT> , dl , ResTy , { L0 , L1 } ) ; } else { SDValue BV = DAG . getBuildVector ( ResTy , dl , Ops ) ; LV = Lower . LowerOperation ( BV , DAG ) ; } assert ( ! N -> use_empty ( ) ) ; ISel . ReplaceNode ( N , LV . getNode ( ) ) ; DAG . RemoveDeadNodes ( ) ;


<s> unsigned IID = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDNode * Result ; switch ( IID ) { case <STR_LIT> : { SmallVector < SDValue , <NUM_LIT> > Ops = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , VTs , Ops ) ; break ; } case <STR_LIT> : { SmallVector < SDValue , <NUM_LIT> > Ops = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , VTs , Ops ) ; break ; } case <STR_LIT> : { SmallVector < SDValue , <NUM_LIT> > Ops = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , VTs , Ops ) ; break ; } case <STR_LIT> : { SmallVector < SDValue , <NUM_LIT> > Ops = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ;


<s> SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , VTs , Ops ) ; break ; } case <STR_LIT> : { SmallVector < SDValue , <NUM_LIT> > Ops = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , VTs , Ops ) ; break ; } case <STR_LIT> : { SmallVector < SDValue , <NUM_LIT> > Ops = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , VTs , Ops ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } ReplaceUses ( N , Result ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) ) ;


<s> HvxSelector ( * this , * CurDAG ) . selectShuffle ( N ) ;


<s> void <ISA_LIT>DAGToDAGISel :: SelectHvxVAlign ( SDNode * N ) {

HvxSelector ( * this , * CurDAG ) . selectVAlign ( N ) ;


<s> if ( auto * CN = dyn_cast < ConstantSDNode > ( RotV . getNode ( ) ) ) { unsigned S = CN -> getZExtValue ( ) % HST . getVectorLength ( ) ; if ( S == <NUM_LIT> ) { NewN = VecV . getNode ( ) ; } else if ( isUInt < <NUM_LIT> > ( S ) ) { SDValue C = DAG . getTargetConstant ( S , dl , <STR_LIT> ) ; NewN = DAG . getMachineNode ( <STR_LIT> , dl , Ty , { VecV , VecV , C } ) ; }


<s> SDValue VecV = N -> getOperand ( <NUM_LIT> ) ; SDValue RotV = N -> getOperand ( <NUM_LIT> ) ; SDNode * NewN = nullptr ; if ( auto * CN = dyn_cast < ConstantSDNode > ( RotV . getNode ( ) ) ) { unsigned S = CN -> getZExtValue ( ) % HST . getVectorLength ( ) ;


<s> } DEBUG_WITH_TYPE ( <STR_LIT> , { dbgs ( ) << <STR_LIT> << VecLen << <STR_LIT> << HwLen << <STR_LIT> << UseLeft << <STR_LIT> << UseRight << <STR_LIT> << HavePairs << '\n' ; } ) ; if ( ! UseLeft && ! UseRight ) { ISel . ReplaceNode ( N , ISel . selectUndef ( SDLoc ( SN ) , ResTy ) . getNode ( ) ) ; return ; } SDValue Vec0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Vec1 = N -> getOperand ( <NUM_LIT> ) ; ResultStack Results ( SN ) ; Results . push ( TargetOpcode :: COPY , ResTy , { Vec0 } ) ; Results . push ( TargetOpcode :: COPY , ResTy , { Vec1 } ) ; OpRef Va = OpRef :: res ( Results . top ( ) - <NUM_LIT> ) ; OpRef Vb = OpRef :: res ( Results . top ( ) ) ; OpRef Res = ! HavePairs ? shuffs2 ( ShuffleMask ( Mask ) , Va , Vb , Results ) : shuffp2 ( ShuffleMask ( Mask ) , Va , Vb , Results ) ;


<s> unsigned IntNo = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; } SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> ) ; SDValue Ops [ ] = { Address , Base , Modifier , Offset , Chain } ; SDNode * Result = CurDAG -> getMachineNode ( Opcode , dl , VTs , Ops ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( Result ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ;


<s> const SDLoc & dl ( N ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Address = N -> getOperand ( <NUM_LIT> ) ; SDValue Predicate = N -> getOperand ( <NUM_LIT> ) ; SDValue Base = N -> getOperand ( <NUM_LIT> ) ; SDValue Modifier = N -> getOperand ( <NUM_LIT> ) ; SDValue Offset = N -> getOperand ( <NUM_LIT> ) ; unsigned Opcode ; unsigned IntNo = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { default : llvm_unreachable ( <STR_LIT> ) ;


<s> SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> ) ; SDValue Ops [ ] = { Address , Predicate , Base , Modifier , Offset , Chain } ; SDNode * Result = CurDAG -> getMachineNode ( Opcode , dl , VTs , Ops ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ;

cast < MachineSDNode > ( Result ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ;


<s> void HvxSelector :: selectVAlign ( SDNode * N ) { SDValue Vv = N -> getOperand ( <NUM_LIT> ) ;

SDValue Vu = N -> getOperand ( <NUM_LIT> ) ;


<s> SDValue Rt = N -> getOperand ( <NUM_LIT> ) ;

SDNode * NewN = DAG . getMachineNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , { Vv , Vu , Rt } ) ;


<s> SmallVector < SDNode * , <NUM_LIT> > Nodes ; SetVector < SDNode * > WorkQ ; DAG . RemoveDeadNodes ( ) ; auto IsNodeToSelect = [ ] ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) return false ; switch ( N -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : { SDValue Addr = cast < LoadSDNode > ( N ) -> getBasePtr ( ) ; unsigned AddrOpc = Addr . getOpcode ( ) ; if ( AddrOpc == <STR_LIT> || AddrOpc == <STR_LIT> ) if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return true ;


<s> if ( M == - <NUM_LIT> ) continue ; MinSrc = ( MinSrc == - <NUM_LIT> ) ? M : std :: min ( MinSrc , M ) ; MaxSrc = ( MaxSrc == - <NUM_LIT> ) ? M : std :: max ( MaxSrc , M ) ;


<s> DEBUG_WITH_TYPE ( <STR_LIT> , { dbgs ( ) << __func__ << '\n' ; } ) ; int VecLen = SM . Mask . size ( ) ; if ( isIdentity ( SM . Mask ) ) return Va ; if ( isUndef ( SM . Mask ) ) return OpRef :: undef ( getPairVT ( <STR_LIT> ) ) ; SmallVector < int , <NUM_LIT> > PackedMask ( VecLen ) ; OpRef P = packs ( SM , OpRef :: lo ( Va ) , OpRef :: hi ( Va ) , Results , PackedMask ) ; if ( P . isValid ( ) ) { ShuffleMask PM ( PackedMask ) ; OpRef E = expanding ( PM , P , Results ) ; if ( E . isValid ( ) ) return E ; OpRef L = shuffs1 ( PM . lo ( ) , P , Results ) ; OpRef H = shuffs1 ( PM . hi ( ) , P , Results ) ; if ( L . isValid ( ) && H . isValid ( ) ) return concat ( L , H , Results ) ;


<s> OpRef L = shuffp1 ( ShuffleMask ( MaskL ) , Va , Results ) ; OpRef R = shuffp1 ( ShuffleMask ( MaskR ) , Vb , Results ) ; if ( ! L . isValid ( ) || ! R . isValid ( ) ) return OpRef :: fail ( ) ; SmallVector < uint8_t , <NUM_LIT> > Bytes ( VecLen ) ;

for ( int I = <NUM_LIT> ; I != VecLen ; ++ I ) {


<s> OpRef HvxSelector :: shuffp2 ( ShuffleMask SM , OpRef Va , OpRef Vb , ResultStack & Results ) { DEBUG_WITH_TYPE ( <STR_LIT> , { dbgs ( ) << __func__ << '\n' ; } ) ; if ( isUndef ( SM . Mask ) ) return OpRef :: undef ( getPairVT ( <STR_LIT> ) ) ; int VecLen = SM . Mask . size ( ) ; SmallVector < int , <NUM_LIT> > PackedMask ( VecLen ) ; OpRef P = packp ( SM , Va , Vb , Results , PackedMask ) ; if ( P . isValid ( ) ) return shuffp1 ( ShuffleMask ( PackedMask ) , P , Results ) ; SmallVector < int , <NUM_LIT> > MaskL ( VecLen ) , MaskR ( VecLen ) ; splitMask ( SM . Mask , MaskL , MaskR ) ; OpRef L = shuffp1 ( ShuffleMask ( MaskL ) , Va , Results ) ; OpRef R = shuffp1 ( ShuffleMask ( MaskR ) , Vb , Results ) ; if ( ! L . isValid ( ) || ! R . isValid ( ) ) return OpRef :: fail ( ) ; SmallVector < uint8_t , <NUM_LIT> > Bytes ( VecLen ) ;


<s> DEBUG_WITH_TYPE ( <STR_LIT> , { dbgs ( ) << __func__ << '\n' ; } ) ; unsigned VecLen = SM . Mask . size ( ) ; assert ( HwLen == VecLen ) ; ( void ) VecLen ; assert ( all_of ( SM . Mask , [ this ] ( int M ) { return M == - <NUM_LIT> || M < int ( HwLen ) ; } ) ) ; if ( isIdentity ( SM . Mask ) ) return Va ; if ( isUndef ( SM . Mask ) ) return OpRef :: undef ( getSingleVT ( <STR_LIT> ) ) ; OpRef P = perfect ( SM , Va , Results ) ;


<s> OpRef C = contracting ( SM , Va , Vb , Results ) ; if ( C . isValid ( ) ) return C ; int VecLen = SM . Mask . size ( ) ; SmallVector < int , <NUM_LIT> > NewMask ( VecLen ) ; OpRef P = packs ( SM , Va , Vb , Results , NewMask ) ; if ( P . isValid ( ) ) return shuffs1 ( ShuffleMask ( NewMask ) , P , Results ) ; SmallVector < int , <NUM_LIT> > MaskL ( VecLen ) , MaskR ( VecLen ) ; splitMask ( SM . Mask , MaskL , MaskR ) ; OpRef L = shuffs1 ( ShuffleMask ( MaskL ) , Va , Results ) ; OpRef R = shuffs1 ( ShuffleMask ( MaskR ) , Vb , Results ) ; if ( ! L . isValid ( ) || ! R . isValid ( ) ) return OpRef :: fail ( ) ; SmallVector < uint8_t , <NUM_LIT> > Bytes ( VecLen ) ; for ( int I = <NUM_LIT> ; I != VecLen ; ++ I ) { if ( MaskL [ I ] != - <NUM_LIT> ) Bytes [ I ] = <NUM_LIT> ; }

return vmuxs ( Bytes , L , R , Results ) ;


<s> unsigned size ( ) const { return List . size ( ) ;


<s> } else if ( unsigned ( M ) < VecLen ) { MaskL [ I ] = M ; MaskR [ I ] = - <NUM_LIT> ; } else { MaskL [ I ] = - <NUM_LIT> ; MaskR [ I ] = M - VecLen ;


<s> OpRef H = vmuxs ( Bytes . drop_front ( S ) , OpRef :: hi ( Va ) , OpRef :: hi ( Vb ) , Results ) ; return concat ( L , H , Results ) ;


<s> SDValue B = getVectorConstant ( Bytes , dl ) ; Results . push ( <STR_LIT> , ByteTy , { } ) ; Results . push ( <STR_LIT> , BoolTy , { OpRef ( B ) , OpRef :: res ( - <NUM_LIT> ) } ) ; Results . push ( <STR_LIT> , ByteTy , { OpRef :: res ( - <NUM_LIT> ) , Vb , Va } ) ; return OpRef :: res ( Results . top ( ) ) ;


<s> bool ComplexPatternFuncMutatesDAG ( ) const override {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> auto & HII = * HST . getInstrInfo ( ) ; BuildMI ( EntryBB , DebugLoc ( ) , HII . get ( <STR_LIT> ) , AR ) . addImm ( MaxA ) ; MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> setStackAlignBaseVReg ( AR ) ;


<s> if ( ! HFI . needsAligna ( * MF ) ) return ; MachineFrameInfo * MFI = MF -> getFrameInfo ( ) ; MachineBasicBlock * EntryBB = MF -> begin ( ) ; unsigned AR = FuncInfo -> CreateReg ( <STR_LIT> ) ; unsigned MaxA = MFI -> getMaxAlignment ( ) ; auto & HII = * HST . getInstrInfo ( ) ; BuildMI ( EntryBB , DebugLoc ( ) , HII . get ( <STR_LIT> ) , AR ) . addImm ( MaxA ) ;

MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> setStackAlignBaseVReg ( AR ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & tm , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( tm , OptLevel ) , HST ( nullptr ) , HII ( nullptr ) , HRI ( nullptr ) {


<s> bool ImmIsSingleBit ( uint32_t v ) const { return isPowerOf2_32 ( v ) ;


<s> static void initializePassOnce ( PassRegistry & Registry ) {


<s> PassInfo * PI = new PassInfo ( Name , <STR_LIT> , & SelectionDAGISel :: ID , nullptr , false , false ) ; Registry . registerPass ( * PI , true ) ;


<s> unsigned UseCount = <NUM_LIT> ; unsigned CallCount = <NUM_LIT> ; for ( SDNode :: use_iterator I = N -> use_begin ( ) , E = N -> use_end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) == <STR_LIT> ) ++ CallCount ; UseCount ++ ;


<s> if ( IsZero ( SY ) ) { SDValue NewOr = DAG . getNode ( <STR_LIT> , DLS , VT , SX , VOp ) ; SDValue NewSel = DAG . getNode ( <STR_LIT> , DLS , VT , SC , NewOr , VOp ) ; DAG . ReplaceAllUsesWith ( I , NewSel . getNode ( ) ) ; } else if ( IsZero ( SX ) ) { SDValue NewOr = DAG . getNode ( <STR_LIT> , DLS , VT , SY , VOp ) ; SDValue NewSel = DAG . getNode ( <STR_LIT> , DLS , VT , SC , VOp , NewOr ) ; DAG . ReplaceAllUsesWith ( I , NewSel . getNode ( ) ) ; } }


SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { HST = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> case <STR_LIT> : return SelectConstantFP ( N ) ; case <STR_LIT> : return SelectFrameIndex ( N ) ; case <STR_LIT> : return SelectAdd ( N ) ; case <STR_LIT> : return SelectSHL ( N ) ; case <STR_LIT> : return SelectLoad ( N ) ; case <STR_LIT> : return SelectStore ( N ) ; case <STR_LIT> : return SelectMul ( N ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SelectBitOp ( N ) ; case <STR_LIT> : return SelectZeroExtend ( N ) ;


<s> if ( Src1 -> getOpcode ( ) != <STR_LIT> || ! Src1 -> hasOneUse ( ) || Src1 -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) { return SelectCode ( N ) ; } SDNode * Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , Src1 -> getOperand ( <NUM_LIT> ) , Src1 -> getOperand ( <NUM_LIT> ) ) ; ReplaceUses ( N , Result ) ;


<s> SDNode * Src1 = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( Src1 -> getOpcode ( ) != <STR_LIT> || ! Src1 -> hasOneUse ( ) || Src1 -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) { return SelectCode ( N ) ; }

SDNode * Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , Src1 -> getOperand ( <NUM_LIT> ) , Src1 -> getOperand ( <NUM_LIT> ) ) ;


<s> auto & HFI = * HST -> getFrameLowering ( ) ; MachineFrameInfo * MFI = MF -> getFrameInfo ( ) ; int FX = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ;

if ( ! MFI -> isFixedObjectIndex ( FX ) && HFI . needsAligna ( * MF ) ) return false ;


<s> return SelectGlobalAddress ( N , R , false ) ;


<s> inline bool <ISA_LIT>DAGToDAGISel :: SelectAddrGP ( SDValue & N , SDValue & R ) {

return SelectGlobalAddress ( N , R , true ) ;


<s> return SelectGlobalAddress ( N , R , true ) ;


<s> } else if ( Val == <NUM_LIT> ) { Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> ) ; } if ( Result ) { ReplaceUses ( N , Result ) ; return Result ; }


<s> else if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , CurDAG -> getTargetConstantFP ( APF . convertToDouble ( ) , dl , <STR_LIT> ) ) ; } return SelectCode ( N ) ;


<s> unsigned MaxA = MFI -> getMaxAlignment ( ) ; SDValue FI = CurDAG -> getTargetFrameIndex ( FX , <STR_LIT> ) ; SDLoc DL ( N ) ; SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDNode * R = <NUM_LIT> ; if ( FX < <NUM_LIT> || MaxA <= StkA || ! MFI -> hasVarSizedObjects ( ) ) { R = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , FI , Zero ) ; } else { auto & HMFI = * MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned AR = HMFI . getStackAlignBaseVReg ( ) ; SDValue CH = CurDAG -> getEntryNode ( ) ; SDValue Ops [ ] = { CurDAG -> getCopyFromReg ( CH , DL , AR , <STR_LIT> ) , FI , Zero } ;

R = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops ) ;


<s> SDValue N0 = N . getOperand ( <NUM_LIT> ) ; SDValue N1 = N . getOperand ( <NUM_LIT> ) ; unsigned GAOpc = N0 . getOpcode ( ) ; if ( UseGP && GAOpc != <STR_LIT> ) return false ; if ( ! UseGP && GAOpc != <STR_LIT> ) return false ; if ( ConstantSDNode * Const = dyn_cast < ConstantSDNode > ( N1 ) ) { SDValue Addr = N0 . getOperand ( <NUM_LIT> ) ; if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( Addr ) ) { if ( GA -> getOpcode ( ) == <STR_LIT> ) { uint64_t NewOff = GA -> getOffset ( ) + ( uint64_t ) Const -> getSExtValue ( ) ; R = CurDAG -> getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( Const ) , N . getValueType ( ) , NewOff ) ; return true ; } } } break ; } case <STR_LIT> : if ( ! UseGP ) R = N . getOperand ( <NUM_LIT> ) ; return ! UseGP ; case <STR_LIT> : if ( UseGP ) R = N . getOperand ( <NUM_LIT> ) ; return UseGP ; default :


<s> if ( ! UseGP && GAOpc != <STR_LIT> ) return false ; if ( ConstantSDNode * Const = dyn_cast < ConstantSDNode > ( N1 ) ) { SDValue Addr = N0 . getOperand ( <NUM_LIT> ) ; if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( Addr ) ) { if ( GA -> getOpcode ( ) == <STR_LIT> ) { uint64_t NewOff = GA -> getOffset ( ) + ( uint64_t ) Const -> getSExtValue ( ) ; R = CurDAG -> getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( Const ) , N . getValueType ( ) , NewOff ) ; return true ; } } } break ; } case <STR_LIT> :

if ( ! UseGP ) R = N . getOperand ( <NUM_LIT> ) ;


<s> } else if ( LoadedVT == <STR_LIT> ) { if ( TII . isValidAutoIncImm ( LoadedVT , Val ) ) Opcode = IsZeroExt ? <STR_LIT> : <STR_LIT> ; else Opcode = IsZeroExt ? <STR_LIT> : <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; if ( LD -> getValueType ( <NUM_LIT> ) == <STR_LIT> && IsZeroExt ) return SelectIndexedLoadZeroExtend64 ( LD , Opcode , dl ) ; if ( LD -> getValueType ( <NUM_LIT> ) == <STR_LIT> && ExtType == <STR_LIT> ) return SelectIndexedLoadSignExtend64 ( LD , Opcode , dl ) ; if ( TII . isValidAutoIncImm ( LoadedVT , Val ) ) { SDValue TargetConstVal = CurDAG -> getTargetConstant ( Val , dl , <STR_LIT> ) ; SDNode * Result = CurDAG -> getMachineNode ( Opcode , dl , LD -> getValueType ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , Base , TargetConstVal , Chain ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ; return Result ; } else { SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue TargetConstVal = CurDAG -> getTargetConstant ( Val , dl , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , LD -> getValueType ( <NUM_LIT> ) , <STR_LIT> , Base , TargetConst0 , Chain ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Base , TargetConstVal , SDValue ( Result_1 , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result_1 , <NUM_LIT> ) , SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ; return Result_1 ; }


<s> cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ; return Result_2 ; } SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue TargetConstVal = CurDAG -> getTargetConstant ( Val , dl , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , Base , TargetConst0 , Chain ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Result_1 , <NUM_LIT> ) ) ; SDNode * Result_3 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Base , TargetConstVal , SDValue ( Result_1 , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ;

const SDValue Tos [ ] = { SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_3 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) } ;


<s> SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , <STR_LIT> , Base , TargetConstVal , Chain ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , TargetConst0 , SDValue ( Result_1 , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ; return Result_2 ; } SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue TargetConstVal = CurDAG -> getTargetConstant ( Val , dl , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , Base , TargetConst0 , Chain ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , TargetConst0 , SDValue ( Result_1 , <NUM_LIT> ) ) ; SDNode * Result_3 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Base , TargetConstVal , SDValue ( Result_1 , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_3 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ;


<s> cast < MachineSDNode > ( Result ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; ReplaceUses ( ST , Result ) ; ReplaceUses ( SDValue ( ST , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) ) ; return Result ; } SDValue Ops [ ] = { Base , CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) , Value , Chain } ; unsigned Opcode = <NUM_LIT> ; if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; SDValue TargetConstVal = CurDAG -> getTargetConstant ( Val , dl , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , Ops ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Base , TargetConstVal , SDValue ( Result_1 , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = ST -> getMemOperand ( ) ; cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ;

ReplaceUses ( SDValue ( ST , <NUM_LIT> ) , SDValue ( Result_2 , <NUM_LIT> ) ) ;


<s> case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_v : case InlineAsm :: Constraint_m : if ( SelectAddrFI ( Inp , Res ) ) OutOps . push_back ( Res ) ; else OutOps . push_back ( Inp ) ; break ;


<s> Bits = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; break ; default : return SelectCode ( N ) ; } SDValue const & V = N -> getOperand ( <NUM_LIT> ) ; SDValue U ; if ( isValueExtension ( V , Bits , U ) ) { SDValue R = CurDAG -> getNode ( N -> getOpcode ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , U ) ;


<s> case <STR_LIT> : Bits = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; break ; default : return SelectCode ( N ) ; } SDValue const & V = N -> getOperand ( <NUM_LIT> ) ; SDValue U ; if ( isValueExtension ( V , Bits , U ) ) { SDValue R = CurDAG -> getNode ( N -> getOpcode ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , U ) ; return SelectCode ( R . getNode ( ) ) ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectLoad ( SDNode * N ) { SDNode * result ; SDLoc dl ( N ) ; LoadSDNode * LD = cast < LoadSDNode > ( N ) ;

<STR_LIT> AM = LD -> getAddressingMode ( ) ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectLoad ( SDNode * N ) { SDNode * result ; SDLoc dl ( N ) ; LoadSDNode * LD = cast < LoadSDNode > ( N ) ; <STR_LIT> AM = LD -> getAddressingMode ( ) ;


<s> if ( MulOp1 . getOpcode ( ) == <STR_LIT> ) { SDValue Sext1 = MulOp1 . getOperand ( <NUM_LIT> ) ; if ( Sext1 . getNode ( ) -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) { return SelectCode ( N ) ; } OP1 = Sext1 ; } else if ( MulOp1 . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * LD = cast < LoadSDNode > ( MulOp1 . getNode ( ) ) ; if ( LD -> getMemoryVT ( ) != <STR_LIT> || LD -> getExtensionType ( ) != <STR_LIT> || LD -> getAddressingMode ( ) != <STR_LIT> ) { return SelectCode ( N ) ; } SDValue Chain = LD -> getChain ( ) ; SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; OP1 = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , LD -> getBasePtr ( ) , TargetConst0 , Chain ) , <NUM_LIT> ) ; } else { return SelectCode ( N ) ;


<s> SDLoc dl ( N ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDValue MulOp0 = N -> getOperand ( <NUM_LIT> ) ; SDValue MulOp1 = N -> getOperand ( <NUM_LIT> ) ; SDValue OP0 ; SDValue OP1 ; if ( MulOp0 . getOpcode ( ) == <STR_LIT> ) { SDValue Sext0 = MulOp0 . getOperand ( <NUM_LIT> ) ; if ( Sext0 . getNode ( ) -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) { return SelectCode ( N ) ; } OP0 = Sext0 ; } else if ( MulOp0 . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * LD = cast < LoadSDNode > ( MulOp0 . getNode ( ) ) ; if ( LD -> getMemoryVT ( ) != <STR_LIT> || LD -> getExtensionType ( ) != <STR_LIT> || LD -> getAddressingMode ( ) != <STR_LIT> ) { return SelectCode ( N ) ; } SDValue Chain = LD -> getChain ( ) ; SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; OP0 = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , LD -> getBasePtr ( ) , TargetConst0 , Chain ) , <NUM_LIT> ) ; } else { return SelectCode ( N ) ; } if ( MulOp1 . getOpcode ( ) == <STR_LIT> ) { SDValue Sext1 = MulOp1 . getOperand ( <NUM_LIT> ) ; if ( Sext1 . getNode ( ) -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) { return SelectCode ( N ) ; } OP1 = Sext1 ; } else if ( MulOp1 . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * LD = cast < LoadSDNode > ( MulOp1 . getNode ( ) ) ; if ( LD -> getMemoryVT ( ) != <STR_LIT> || LD -> getExtensionType ( ) != <STR_LIT> || LD -> getAddressingMode ( ) != <STR_LIT> ) {


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectStore ( SDNode * N ) { SDLoc dl ( N ) ;

StoreSDNode * ST = cast < StoreSDNode > ( N ) ;


<s> } return CurDAG -> getMachineNode ( <STR_LIT> , dl , ExVT , SDValue ( Mask , <NUM_LIT> ) , SDValue ( OnesReg , <NUM_LIT> ) ) ; } SDNode * IsIntrinsic = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( ( IsIntrinsic -> getOpcode ( ) == <STR_LIT> ) ) { unsigned ID = cast < ConstantSDNode > ( IsIntrinsic -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( doesIntrinsicReturnPredicate ( ID ) ) { if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( IsIntrinsic , <NUM_LIT> ) ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , TargetConst0 ) ; SDNode * Result_3 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) ) ; ReplaceUses ( N , Result_3 ) ; return Result_3 ; } if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDNode * RsPd = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( IsIntrinsic , <NUM_LIT> ) ) ; ReplaceUses ( N , RsPd ) ; return RsPd ; } llvm_unreachable ( <STR_LIT> ) ;


<s> SDValue Ones = CurDAG -> getTargetConstant ( MV , dl , <STR_LIT> ) ; SDNode * OnesReg = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ones ) ; if ( ExVT . getSizeInBits ( ) == <NUM_LIT> ) { SDNode * And = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Mask , <NUM_LIT> ) , SDValue ( OnesReg , <NUM_LIT> ) ) ; SDValue SubR = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , ExVT , SDValue ( And , <NUM_LIT> ) , SubR ) ; } return CurDAG -> getMachineNode ( <STR_LIT> , dl , ExVT , SDValue ( Mask , <NUM_LIT> ) , SDValue ( OnesReg , <NUM_LIT> ) ) ; } SDNode * IsIntrinsic = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( ( IsIntrinsic -> getOpcode ( ) == <STR_LIT> ) ) { unsigned ID = cast < ConstantSDNode > ( IsIntrinsic -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( doesIntrinsicReturnPredicate ( ID ) ) { if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( IsIntrinsic , <NUM_LIT> ) ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , TargetConst0 ) ; SDNode * Result_3 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) ) ; ReplaceUses ( N , Result_3 ) ; return Result_3 ; } if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) {

SDNode * RsPd = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( IsIntrinsic , <NUM_LIT> ) ) ;


<s> inline SDValue XformM5ToU5Imm ( signed Imm , SDLoc DL ) { assert ( ( Imm >= - <NUM_LIT> && Imm <= - <NUM_LIT> ) && <STR_LIT> ) ; return CurDAG -> getTargetConstant ( - Imm , DL , <STR_LIT> ) ;


<s> inline SDValue XformM5ToU5Imm ( signed Imm , SDLoc DL ) {

assert ( ( Imm >= - <NUM_LIT> && Imm <= - <NUM_LIT> ) && <STR_LIT> ) ;


<s> SDValue XformMskToBitPosU3Imm ( uint8_t Imm , SDLoc DL ) { return XformMskToBitPosU5Imm ( Imm , DL ) ;


<s> return XformMskToBitPosU5Imm ( Imm , DL ) ;


<s> SDValue XformMskToBitPosU5Imm ( uint32_t Imm , SDLoc DL ) { int32_t bitPos ; bitPos = Log2_32 ( Imm ) ;

assert ( bitPos >= <NUM_LIT> && bitPos < <NUM_LIT> && <STR_LIT> ) ;


<s> inline SDValue XformSToSM1Imm ( signed Imm , SDLoc DL ) { return CurDAG -> getTargetConstant ( Imm - <NUM_LIT> , DL , <STR_LIT> ) ;


<s> return CurDAG -> getTargetConstant ( Imm - <NUM_LIT> , DL , <STR_LIT> ) ;


<s> inline SDValue XformSToSM3Imm ( unsigned Imm , SDLoc DL ) { return CurDAG -> getTargetConstant ( Imm - <NUM_LIT> , DL , <STR_LIT> ) ;


<s> inline SDValue XformUToUM1Imm ( unsigned Imm , SDLoc DL ) { assert ( ( Imm >= <NUM_LIT> ) && <STR_LIT> ) ; return CurDAG -> getTargetConstant ( Imm - <NUM_LIT> , DL , <STR_LIT> ) ;


<s> assert ( ( Imm >= <NUM_LIT> ) && <STR_LIT> ) ;

return CurDAG -> getTargetConstant ( Imm - <NUM_LIT> , DL , <STR_LIT> ) ;


<s> if ( Fast ) * Fast = false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( First == Num ) return DAG . getUNDEF ( VecTy ) ; if ( AllConst && llvm :: all_of ( Consts , [ ] ( ConstantInt * CI ) { return CI -> isZero ( ) ; } ) ) return getZero ( dl , VecTy , DAG ) ; if ( ElemTy == <STR_LIT> ) { assert ( Elem . size ( ) == <NUM_LIT> ) ; if ( AllConst ) { uint32_t V = ( Consts [ <NUM_LIT> ] -> getZExtValue ( ) & <NUM_LIT> ) | Consts [ <NUM_LIT> ] -> getZExtValue ( ) << <NUM_LIT> ; return DAG . getBitcast ( <STR_LIT> , DAG . getConstant ( V , dl , <STR_LIT> ) ) ; } SDValue N = getNode ( <STR_LIT> , dl , <STR_LIT> , { Elem [ <NUM_LIT> ] , Elem [ <NUM_LIT> ] } , DAG ) ; return DAG . getBitcast ( <STR_LIT> , N ) ; } if ( ElemTy == <STR_LIT> ) { if ( AllConst ) { int32_t V = ( Consts [ <NUM_LIT> ] -> getZExtValue ( ) & <NUM_LIT> ) | ( Consts [ <NUM_LIT> ] -> getZExtValue ( ) & <NUM_LIT> ) << <NUM_LIT> | ( Consts [ <NUM_LIT> ] -> getZExtValue ( ) & <NUM_LIT> ) << <NUM_LIT> | Consts [ <NUM_LIT> ] -> getZExtValue ( ) << <NUM_LIT> ; return DAG . getBitcast ( <STR_LIT> , DAG . getConstant ( V , dl , <STR_LIT> ) ) ;


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ;

return CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT> ) ;


<s> if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) {


<s> for ( unsigned i = <NUM_LIT> ; i < NumVectorElements / <NUM_LIT> ; ++ i ) { uint8_t x = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) { uint8_t y = CV -> getOperand ( i * <NUM_LIT> + j ) -> getUniqueInteger ( ) . getZExtValue ( ) ;


<s> MVT VecTy = ty ( VecV ) ; assert ( ! ValTy . isVector ( ) || VecTy . getVectorElementType ( ) == ValTy . getVectorElementType ( ) ) ; unsigned VecWidth = VecTy . getSizeInBits ( ) ; unsigned ValWidth = ValTy . getSizeInBits ( ) ; unsigned ElemWidth = VecTy . getVectorElementType ( ) . getSizeInBits ( ) ; assert ( VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> ) ; assert ( ( VecWidth % ElemWidth ) == <NUM_LIT> ) ; MVT ScalarTy = tyScalar ( VecTy ) ; VecV = DAG . getBitcast ( ScalarTy , VecV ) ; SDValue WidthV = DAG . getConstant ( ValWidth , dl , <STR_LIT> ) ; SDValue ExtV ;

if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( IdxV ) ) {


<s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasV60TOps ( ) && Subtarget . useHVXOps ( ) && Subtarget . useHVX128BOps ( ) ) RRC = & <STR_LIT> ; else RRC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RRC = & <STR_LIT> ; break ;


<s> Consts [ i ] = ConstantInt :: get ( IntTy , <NUM_LIT> ) ; continue ; } if ( auto * CN = dyn_cast < ConstantSDNode > ( V . getNode ( ) ) ) { const ConstantInt * CI = CN -> getConstantIntValue ( ) ; Consts [ i ] = const_cast < ConstantInt * > ( CI ) ; } else if ( auto * CN = dyn_cast < ConstantFPSDNode > ( V . getNode ( ) ) ) {

const ConstantFP * CF = CN -> getConstantFPValue ( ) ;


<s> const uint32_t * Mask = HRI . getCallPreservedMask ( MF , CallingConv :: C ) ; assert ( Mask && <STR_LIT> ) ; SDValue Ops [ ] = { Chain , TGA , DAG . getRegister ( <STR_LIT> , PtrVT ) , DAG . getRegisterMask ( Mask ) , Glue } ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops ) ;


<s> auto & HST = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; bool ValidHVX128BType = HST . useHVX128BOps ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ; bool ValidHVXType = HST . useHVX64BOps ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ; if ( ValidHVX128BType || ValidHVXType || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { IsInc = ( Ptr -> getOpcode ( ) == <STR_LIT> ) ; Base = Ptr -> getOperand ( <NUM_LIT> ) ; Offset = Ptr -> getOperand ( <NUM_LIT> ) ; return isa < ConstantSDNode > ( Offset ) ; }


<s> unsigned getInlineAsmMemConstraint ( StringRef ConstraintCode ) const override { if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_o ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_v ; return TargetLowering :: getInlineAsmMemConstraint ( ConstraintCode ) ;


<s> auto Aligned = [ ] ( unsigned GivenA , unsigned MinA ) -> bool { return ( GivenA % MinA ) == <NUM_LIT> ; } ;

if ( Size >= <NUM_LIT> && Aligned ( DstAlign , <NUM_LIT> ) && ( IsMemset || Aligned ( SrcAlign , <NUM_LIT> ) ) ) return <STR_LIT> ;


<s> bool <ISA_LIT>TargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , <STR_LIT> & AM , SelectionDAG & DAG ) const { EVT VT ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ;

} else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) {


<s> if ( ElemTy == <STR_LIT> ) return TargetLoweringBase :: TypeWidenVector ; if ( Subtarget . useHVXOps ( ) ) { ArrayRef < MVT > Tys = Subtarget . getHVXElementTypes ( ) ; if ( llvm :: find ( Tys , ElemTy ) != Tys . end ( ) ) { unsigned HwWidth = <NUM_LIT> * Subtarget . getVectorLength ( ) ; unsigned VecWidth = VT . getSizeInBits ( ) ; if ( VecWidth >= HwWidth / <NUM_LIT> && VecWidth < HwWidth ) return TargetLoweringBase :: TypeWidenVector ; }


<s> return { <NUM_LIT> , & <STR_LIT> } ; case 'q' : switch ( VT . getSizeInBits ( ) ) { default : return { <NUM_LIT> , nullptr } ; case <NUM_LIT> : case <NUM_LIT> : return { <NUM_LIT> , & <STR_LIT> } ; } break ; case 'v' : switch ( VT . getSizeInBits ( ) ) { default : return { <NUM_LIT> , nullptr } ; case <NUM_LIT> : return { <NUM_LIT> , & <STR_LIT> } ; case <NUM_LIT> : if ( Subtarget . hasV60TOps ( ) && Subtarget . useHVX128BOps ( ) ) return { <NUM_LIT> , & <STR_LIT> } ; return { <NUM_LIT> , & <STR_LIT> } ; case <NUM_LIT> : return { <NUM_LIT> , & <STR_LIT> } ; }


<s> case <STR_LIT> : case <STR_LIT> : return { <NUM_LIT> , & <STR_LIT> } ; } break ; case 'a' : if ( VT != <STR_LIT> ) return { <NUM_LIT> , nullptr } ; return { <NUM_LIT> , & <STR_LIT> } ; case 'q' : switch ( VT . getSizeInBits ( ) ) { default : return { <NUM_LIT> , nullptr } ; case <NUM_LIT> : case <NUM_LIT> : return { <NUM_LIT> , & <STR_LIT> } ; } break ; case 'v' : switch ( VT . getSizeInBits ( ) ) { default : return { <NUM_LIT> , nullptr } ; case <NUM_LIT> : return { <NUM_LIT> , & <STR_LIT> } ; case <NUM_LIT> : if ( Subtarget . hasV60TOps ( ) && Subtarget . useHVX128BOps ( ) ) return { <NUM_LIT> , & <STR_LIT> } ; return { <NUM_LIT> , & <STR_LIT> } ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const Module & M = * I . getParent ( ) -> getParent ( ) -> getParent ( ) ; Info . opc = <STR_LIT> ; Type * VecTy = I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ; Info . memVT = <STR_LIT> ( VecTy ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = M . getDataLayout ( ) . getTypeAllocSizeInBits ( VecTy ) / <NUM_LIT> ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; } default : break ; }


<s> if ( Ty . isVector ( ) ) { assert ( Ty . isInteger ( ) && <STR_LIT> ) ; unsigned W = Ty . getSizeInBits ( ) ;

if ( W <= <NUM_LIT> ) return DAG . getBitcast ( Ty , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ( W ) ) ) ;


<s> unsigned W = Ty . getSizeInBits ( ) ; if ( W <= <NUM_LIT> ) return DAG . getBitcast ( Ty , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ( W ) ) ) ; return DAG . getNode ( <STR_LIT> , dl , Ty ) ; } if ( Ty . isInteger ( ) ) return DAG . getConstant ( <NUM_LIT> , dl , Ty ) ; if ( Ty . isFloatingPoint ( ) ) return DAG . getConstantFP ( <NUM_LIT> , dl , Ty ) ;


<s> SDValue OffV = DAG . getConstant ( W , dl , <STR_LIT> ) ; InsV = DAG . getNode ( <STR_LIT> , dl , ScalarTy , { VecV , ValV , WidthV , OffV } ) ; } else { if ( ty ( IdxV ) != <STR_LIT> ) IdxV = DAG . getZExtOrTrunc ( IdxV , dl , <STR_LIT> ) ; SDValue OffV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , WidthV ) ; SDValue CombV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { WidthV , OffV } ) ; InsV = DAG . getNode ( <STR_LIT> , dl , ScalarTy , { VecV , ValV , CombV } ) ;


<s> bool <ISA_LIT>TargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { return isOperationLegalOrCustom ( <STR_LIT> , VT ) ;


<s> if ( ! isInt < <NUM_LIT> > ( AM . BaseOffs >> Log2_32 ( A ) ) ) return false ; } if ( AM . BaseGV ) return false ; int Scale = AM . Scale ; if ( Scale < <NUM_LIT> ) Scale = - Scale ; switch ( Scale ) { case <NUM_LIT> : break ; default : return false ; }


<s> bool <ISA_LIT>TargetLowering :: isShuffleMaskLegal ( ArrayRef < int > Mask , EVT VT ) const { return true ;


<s> bool <ISA_LIT>TargetLowering :: isShuffleMaskLegal ( ArrayRef < int > Mask , EVT VT ) const {


<s> const SDLoc & dl ( Op ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> , e = Op . getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( Op . getOperand ( i ) ) ;

if ( BW == <NUM_LIT> ) return buildVector32 ( Ops , dl , VecTy , DAG ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerCallResult ( SDValue Chain , SDValue Glue , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SmallVectorImpl < SDValue > & OutVals , SDValue Callee ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue RetVal ; if ( RVLocs [ i ] . getValVT ( ) == <STR_LIT> ) { auto & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue FR0 = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , <STR_LIT> , Glue ) ; unsigned PredR = MRI . createVirtualRegister ( & <STR_LIT> ) ; SDValue TPR = DAG . getCopyToReg ( FR0 . getValue ( <NUM_LIT> ) , dl , PredR , FR0 . getValue ( <NUM_LIT> ) , FR0 . getValue ( <NUM_LIT> ) ) ; RetVal = DAG . getCopyFromReg ( TPR . getValue ( <NUM_LIT> ) , dl , PredR , <STR_LIT> ) ; Glue = TPR . getValue ( <NUM_LIT> ) ; Chain = TPR . getValue ( <NUM_LIT> ) ; } else { RetVal = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , Glue ) ; Glue = RetVal . getValue ( <NUM_LIT> ) ;

Chain = RetVal . getValue ( <NUM_LIT> ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue RetVal ; if ( RVLocs [ i ] . getValVT ( ) == <STR_LIT> ) { auto & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue FR0 = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , <STR_LIT> , Glue ) ; unsigned PredR = MRI . createVirtualRegister ( & <STR_LIT> ) ; SDValue TPR = DAG . getCopyToReg ( FR0 . getValue ( <NUM_LIT> ) , dl , PredR , FR0 . getValue ( <NUM_LIT> ) , FR0 . getValue ( <NUM_LIT> ) ) ; RetVal = DAG . getCopyFromReg ( TPR . getValue ( <NUM_LIT> ) , dl , PredR , <STR_LIT> ) ; Glue = TPR . getValue ( <NUM_LIT> ) ;


<s> assert ( Op . getNumOperands ( ) == <NUM_LIT> ) ;

return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VecTy , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { EVT ValTy = Op . getValueType ( ) ; ConstantPoolSDNode * CPN = cast < ConstantPoolSDNode > ( Op ) ; Constant * CVal = nullptr ; bool isVTi1Type = false ; if ( const Constant * ConstVal = dyn_cast < Constant > ( CPN -> getConstVal ( ) ) ) { Type * CValTy = ConstVal -> getType ( ) ; if ( CValTy -> isVectorTy ( ) && CValTy -> getVectorElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { CVal = convert_i1_to_i8 ( ConstVal ) ; isVTi1Type = ( CVal != nullptr ) ; } } unsigned Align = CPN -> getAlignment ( ) ; bool IsPositionIndependent = isPositionIndependent ( ) ;

unsigned char TF = IsPositionIndependent ? <STR_LIT> : <NUM_LIT> ;


<s> assert ( AlignConst && <STR_LIT> ) ; unsigned A = AlignConst -> getSExtValue ( ) ; auto & HFI = * Subtarget . getFrameLowering ( ) ; if ( A == <NUM_LIT> ) A = HFI . getStackAlignment ( ) ; DEBUG ( { dbgs ( ) << __func__ << <STR_LIT> << A << <STR_LIT> ; Size . getNode ( ) -> dump ( & DAG ) ; dbgs ( ) << <STR_LIT> ; } ) ; SDValue AC = DAG . getConstant ( A , dl , <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue AA = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Size , AC ) ; DAG . ReplaceAllUsesOfValueWith ( Op , AA ) ; return AA ;


<s> SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getRegister ( <STR_LIT> , PtrVT ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; Chain = DAG . getStore ( Chain , dl , Handler , StoreAddr , MachinePointerInfo ( ) ) ;

Chain = DAG . getCopyToReg ( Chain , dl , OffsetReg , Offset ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerEXTRACT_SUBVECTOR ( SDValue Op , SelectionDAG & DAG ) const { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; MVT VecTy = ty ( Vec ) ; if ( Subtarget . useHVXOps ( ) && Subtarget . isHVXVectorType ( VecTy ) ) return LowerHvxExtractSubvector ( Op , DAG ) ; return extractVector ( Vec , Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , ty ( Op ) , ty ( Op ) , DAG ) ;


<s> if ( Subtarget . useHVXOps ( ) && Subtarget . isHVXVectorType ( VecTy ) ) return LowerHvxExtractElement ( Op , DAG ) ; MVT ElemTy = ty ( Vec ) . getVectorElementType ( ) ; return extractVector ( Vec , Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , ElemTy , ty ( Op ) , DAG ) ;


<s> if ( Subtarget . useHVXOps ( ) && Subtarget . isHVXVectorType ( VecTy ) ) return LowerHvxExtractElement ( Op , DAG ) ; MVT ElemTy = ty ( Vec ) . getVectorElementType ( ) ;

return extractVector ( Vec , Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , ElemTy , ty ( Op ) , DAG ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;

SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , HRI . getFrameRegister ( ) , VT ) ;


<s> const GlobalObject * GO = GV -> getBaseObject ( ) ; if ( GO && HLOF . isGlobalInSmallSection ( GO , HTM ) ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA ) ; } bool UsePCRel = getTargetMachine ( ) . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ; if ( UsePCRel ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , Offset , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA ) ; } SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ;

SDValue Off = DAG . getConstant ( Offset , dl , <STR_LIT> ) ;


<s> if ( Op . getOperand ( NumOps - <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) -- NumOps ; for ( unsigned i = InlineAsm :: Op_FirstOperand ; i != NumOps ; ) { unsigned Flags = cast < ConstantSDNode > ( Op . getOperand ( i ) ) -> getZExtValue ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; ++ i ; switch ( InlineAsm :: getKind ( Flags ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Kind_RegUse : case InlineAsm :: Kind_Imm : case InlineAsm :: Kind_Mem : i += NumVals ; break ; case InlineAsm :: Kind_Clobber : case InlineAsm :: Kind_RegDef : case InlineAsm :: Kind_RegDefEarlyClobber : { for ( ; NumVals ; -- NumVals , ++ i ) {

unsigned Reg = cast < RegisterSDNode > ( Op . getOperand ( i ) ) -> getReg ( ) ;


<s> if ( Subtarget . useHVXOps ( ) && Subtarget . isHVXVectorType ( ty ( Op ) ) ) return LowerHvxInsertSubvector ( Op , DAG ) ; SDValue ValV = Op . getOperand ( <NUM_LIT> ) ; return insertVector ( Op . getOperand ( <NUM_LIT> ) , ValV , Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , ty ( ValV ) , DAG ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerINSERT_SUBVECTOR ( SDValue Op , SelectionDAG & DAG ) const { if ( Subtarget . useHVXOps ( ) && Subtarget . isHVXVectorType ( ty ( Op ) ) ) return LowerHvxInsertSubvector ( Op , DAG ) ; SDValue ValV = Op . getOperand ( <NUM_LIT> ) ; return insertVector ( Op . getOperand ( <NUM_LIT> ) , ValV , Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , ty ( ValV ) , DAG ) ;


if ( Subtarget . useHVXOps ( ) && Subtarget . isHVXVectorType ( VecTy ) ) return LowerHvxInsertElement ( Op , DAG ) ;


<s> case <STR_LIT> : return LowerINSERT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVECTOR_SHIFT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG ) ;

case <STR_LIT> : return LowerINLINEASM ( Op , DAG ) ;


<s> case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG ) ; case <STR_LIT> : return LowerINLINEASM ( Op , DAG ) ;

case <STR_LIT> : return LowerPREFETCH ( Op , DAG ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerREADCYCLECOUNTER ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerREADCYCLECOUNTER ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , dl , VTs , Chain ) ;


<s> return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ; } unsigned Reg = MF . addLiveIn ( HRI . getRARegister ( ) , getRegClassFor ( <STR_LIT> ) ) ;

return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , Reg , VT ) ;


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ; } unsigned Reg = MF . addLiveIn ( HRI . getRARegister ( ) , getRegClassFor ( <STR_LIT> ) ) ;


<s> return SC ; } if ( VT . isVector ( ) ) return Op ; if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && ( RHSVT == <STR_LIT> || RHSVT == <STR_LIT> ) && ( LHSVT == <STR_LIT> || LHSVT == <STR_LIT> ) ) { ConstantSDNode * C = dyn_cast < ConstantSDNode > ( RHS ) ; if ( C && C -> getAPIntValue ( ) . isNegative ( ) ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS , Op . getOperand ( <NUM_LIT> ) ) ; } if ( isSExtFree ( LHS ) || isSExtFree ( RHS ) ) {


<s> SDValue Chain = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOT , Sym ) ; SDValue InFlag ; Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , Chain , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ;

unsigned Flags = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . useLongCalls ( ) ? <STR_LIT> | <STR_LIT> : <STR_LIT> ;


<s> SDValue GOT = LowerGLOBAL_OFFSET_TABLE ( Sym , DAG ) ; Sym = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOT , Sym ) ; } SDValue LoadOffset = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Sym , MachinePointerInfo ( ) ) ;

return DAG . getNode ( <STR_LIT> , dl , PtrVT , TP , LoadOffset ) ;


<s> <ISA_LIT>MachineFunctionInfo * QFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SDValue Addr = DAG . getFrameIndex ( QFI -> getVarArgsFrameIndex ( ) , <STR_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , Addr , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerVASTART ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * QFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;

SDValue Addr = DAG . getFrameIndex ( QFI -> getVarArgsFrameIndex ( ) , <STR_LIT> ) ;


<s> if ( V2 . isUndef ( ) ) V2 = V1 ; if ( SVN -> isSplat ( ) ) { int Lane = SVN -> getSplatIndex ( ) ; if ( Lane == - <NUM_LIT> ) Lane = <NUM_LIT> ; if ( Lane == <NUM_LIT> && V1 . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 . getOperand ( <NUM_LIT> ) ) ; if ( Lane == <NUM_LIT> && V1 . getOpcode ( ) == <STR_LIT> && ! isa < ConstantSDNode > ( V1 . getOperand ( <NUM_LIT> ) ) ) { bool IsScalarToVector = true ; for ( unsigned i = <NUM_LIT> , e = V1 . getNumOperands ( ) ; i != e ; ++ i ) {

if ( ! V1 . getOperand ( i ) . isUndef ( ) ) {


<s> auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( <STR_LIT> ) ; if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == <STR_LIT> ) return false ; return true ;


<s> auto & MF = State . getMachineFunction ( ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; LocInfo = CCValAssign :: BCvt ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ;


<s> if ( unsigned Reg = State . AllocateReg ( RegList ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ;


<s> if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { static const uint16_t RegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList ) ) {

State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ;


<s> if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( unsigned Reg = State . AllocateReg ( <STR_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; }


<s> } else if ( LocVT == <STR_LIT> ) { unsigned Req = HST . useHVX128BOps ( ) ? <STR_LIT> : <STR_LIT> ; if ( unsigned Reg = State . AllocateReg ( Req ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } else if ( LocVT == <STR_LIT> ) { if ( unsigned Reg = State . AllocateReg ( <STR_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ;


<s> } } else if ( LocVT == <STR_LIT> ) { unsigned Req = HST . useHVX128BOps ( ) ? <STR_LIT> : <STR_LIT> ; if ( unsigned Reg = State . AllocateReg ( Req ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; }


<s> else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! CC_<ISA_LIT>32 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! CC_<ISA_LIT>64 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; }


<s> static bool CC_<ISA_LIT>32 ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { static const MCPhysReg RegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ;

State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ;


<s> static const MCPhysReg RegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ;


<s> State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } static const MCPhysReg RegList1 [ ] = { <STR_LIT> , <STR_LIT> } ; static const MCPhysReg RegList2 [ ] = { <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList1 , RegList2 , <NUM_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ;


<s> if ( ( int ) ValNo < HState . getNumNamedVarArgParams ( ) ) { return CC_<ISA_LIT> ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ; } unsigned ofst ; if ( ArgFlags . isByVal ( ) ) { assert ( ( ArgFlags . getByValSize ( ) > <NUM_LIT> ) && <STR_LIT> ) ; ofst = State . AllocateStack ( ArgFlags . getByValSize ( ) , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , ofst , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { ofst = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , ofst , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { ofst = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , ofst , LocVT , LocInfo ) ) ; return false ; }


<s> } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { ofst = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , ofst , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { ofst = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , ofst , LocVT , LocInfo ) ) ; return false ; }


<s> SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , <STR_LIT> ) ; return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getByValAlign ( ) , false , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> case <STR_LIT> : { MachineFunction * MF = BB -> getParent ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; FuncInfo -> addAllocaAdjustInst ( MI ) ;


<s> isInc = ( Ptr -> getOpcode ( ) == <STR_LIT> ) ; Base = Ptr -> getOperand ( <NUM_LIT> ) ; Offset = Ptr -> getOperand ( <NUM_LIT> ) ;

return ( isa < ConstantSDNode > ( Offset ) ) ;


<s> int getNumNamedVarArgParams ( ) const { return NumNamedVarArgParams ;


<s> VT = ST -> getMemoryVT ( ) ; if ( ST -> getValue ( ) . getValueType ( ) == <STR_LIT> && ST -> isTruncatingStore ( ) ) { return false ; } } else { return false ; } bool isInc = false ; bool isLegal = getIndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; int ShiftAmount = VT . getSizeInBits ( ) / <NUM_LIT> ; if ( isLegal && Is_PostInc_S4_Offset ( Offset . getNode ( ) , ShiftAmount ) ) { AM = isInc ? <STR_LIT> : <STR_LIT> ; return true ; } return false ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; }


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; }


<s> bool <ISA_LIT>TargetLowering :: IsEligibleForTailCallOptimization ( SDValue Callee , CallingConv :: ID CalleeCC , bool isVarArg , bool isCalleeStructRet , bool isCallerStructRet , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SmallVectorImpl < <STR_LIT> > & Ins , SelectionDAG & DAG ) const {

const Function * CallerF = DAG . getMachineFunction ( ) . getFunction ( ) ;


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const {


<s> return false ; } if ( AM . BaseGV ) { return false ; } int Scale = AM . Scale ; if ( Scale < <NUM_LIT> ) Scale = - Scale ; switch ( Scale ) { case <NUM_LIT> :


<s> if ( ! VT1 . isSimple ( ) || ! VT2 . isSimple ( ) ) {


return ( ( VT1 . getSimpleVT ( ) == <STR_LIT> ) && ( VT2 . getSimpleVT ( ) == <STR_LIT> ) ) ;


<s> ConstantSDNode * N = cast < ConstantSDNode > ( S ) ; int64_t v = ( int64_t ) N -> getSExtValue ( ) ; int64_t m = <NUM_LIT> ; if ( ShiftAmount > <NUM_LIT> ) { m = v % ShiftAmount ; v = v >> ShiftAmount ; }

return ( v <= <NUM_LIT> ) && ( v >= - <NUM_LIT> ) && ( m == <NUM_LIT> ) ;


<s> int64_t v = ( int64_t ) N -> getSExtValue ( ) ; int64_t m = <NUM_LIT> ; if ( ShiftAmount > <NUM_LIT> ) { m = v % ShiftAmount ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ;

SDValue BA_SD = DAG . getTargetBlockAddress ( BA , <STR_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const {

const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ;


<s> SDLoc dl ( Op ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Table ) ; unsigned JTI = JT -> getIndex ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const MachineJumpTableInfo * MJTI = MF . getJumpTableInfo ( ) ; SDValue TargetJT = DAG . getTargetJumpTable ( JT -> getIndex ( ) , <STR_LIT> ) ; const std :: vector < MachineJumpTableEntry > & JTE = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JTE [ JTI ] . MBBs ; for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = JTBBs [ i ] ; MBB -> setHasAddressTaken ( ) ; BlockAddress :: get ( const_cast < BasicBlock * > ( MBB -> getBasicBlock ( ) ) ) ; } SDValue JumpTableBase = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , TargetJT ) ; SDValue ShiftIndex = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Index , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue JTAddress = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , JumpTableBase , ShiftIndex ) ;

SDValue LoadTarget = DAG . getLoad ( <STR_LIT> , dl , Chain , JTAddress , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; } return Chain ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ;

for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) {


<s> SDValue Res ; if ( CP -> isMachineConstantPoolEntry ( ) ) Res = DAG . getTargetConstantPool ( CP -> getMachineCPVal ( ) , ValTy , CP -> getAlignment ( ) ) ; else Res = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , ValTy , CP -> getAlignment ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , ValTy , Res ) ;


<s> ConstantPoolSDNode * CP = cast < ConstantPoolSDNode > ( Op ) ; SDValue Res ; if ( CP -> isMachineConstantPoolEntry ( ) ) Res = DAG . getTargetConstantPool ( CP -> getMachineCPVal ( ) , ValTy , CP -> getAlignment ( ) ) ;

else Res = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , ValTy , CP -> getAlignment ( ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerDYNAMIC_STACKALLOC ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; unsigned SPReg = getStackPointerRegisterToSaveRestore ( ) ; SDValue StackPointer = DAG . getCopyFromReg ( Chain , dl , SPReg , <STR_LIT> ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPointer , Size ) ; SDValue ArgAdjust = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; const <ISA_LIT>RegisterInfo * QRI = Subtarget -> getRegisterInfo ( ) ;

SDValue CopyChain = DAG . getCopyToReg ( Chain , dl , QRI -> getStackRegister ( ) , Sub ) ;


<s> SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPointer , Size ) ; SDValue ArgAdjust = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; const <ISA_LIT>RegisterInfo * QRI = Subtarget -> getRegisterInfo ( ) ; SDValue CopyChain = DAG . getCopyToReg ( Chain , dl , QRI -> getStackRegister ( ) , Sub ) ;

SDValue Ops [ <NUM_LIT> ] = { ArgAdjust , CopyChain } ;


<s> SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , DAG . getRegister ( <STR_LIT> , getPointerTy ( ) ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; Chain = DAG . getStore ( Chain , dl , Handler , StoreAddr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ;

Chain = DAG . getCopyToReg ( Chain , dl , OffsetReg , Offset ) ;


<s> CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; <STR_LIT> Flags = Ins [ i ] . Flags ; unsigned ObjSize ; unsigned StackLocation ; int FI ; if ( ( VA . isRegLoc ( ) && ! Flags . isByVal ( ) ) || ( VA . isRegLoc ( ) && Flags . isByVal ( ) && Flags . getByValSize ( ) > <NUM_LIT> ) ) { EVT RegVT = VA . getLocVT ( ) ; if ( RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> ) { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ;

InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ;


<s> MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;

SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , TRI -> getFrameRegister ( ) , VT ) ;


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , TRI -> getFrameRegister ( ) , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return FrameAddr ;


<s> Result = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , Offset ) ; const <ISA_LIT>TargetObjectFile & TLOF = static_cast < const <ISA_LIT>TargetObjectFile & > ( getObjFileLowering ( ) ) ; if ( TLOF . IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) { return DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ;


<s> const <ISA_LIT>TargetObjectFile & TLOF = static_cast < const <ISA_LIT>TargetObjectFile & > ( getObjFileLowering ( ) ) ; if ( TLOF . IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) { return DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ;


<s> SDNode * Node = Op . getNode ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; switch ( Node -> getOpcode ( ) ) { case <STR_LIT> : { unsigned NumOps = Node -> getNumOperands ( ) ; if ( Node -> getOperand ( NumOps - <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) -- NumOps ; for ( unsigned i = InlineAsm :: Op_FirstOperand ; i != NumOps ; ) { if ( FuncInfo -> hasClobberLR ( ) ) break ; unsigned Flags = cast < ConstantSDNode > ( Node -> getOperand ( i ) ) -> getZExtValue ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; ++ i ; switch ( InlineAsm :: getKind ( Flags ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Kind_RegDef : case InlineAsm :: Kind_RegUse : case InlineAsm :: Kind_Imm : case InlineAsm :: Kind_Clobber : case InlineAsm :: Kind_Mem : { for ( ; NumVals ; -- NumVals , ++ i ) { } break ; } case InlineAsm :: Kind_RegDefEarlyClobber : { for ( ; NumVals ; -- NumVals , ++ i ) { unsigned Reg = cast < RegisterSDNode > ( Node -> getOperand ( i ) ) -> getReg ( ) ; const <ISA_LIT>RegisterInfo * QRI = Subtarget -> getRegisterInfo ( ) ; if ( Reg == QRI -> getRARegister ( ) ) { FuncInfo -> setHasClobberLR ( true ) ; break ; } } break ; } } }


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return Op ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ;

case <STR_LIT> : return LowerINLINEASM ( Op , DAG ) ;