<s> SDValue C0 = Cond . getOperand ( <NUM_LIT> ) , C1 = Cond . getOperand ( <NUM_LIT> ) ; if ( C1 -> getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , ty ( Op ) , C0 , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; } break ; } case <STR_LIT> : if ( Ops [ <NUM_LIT> ] . getOpcode ( ) == <STR_LIT> ) { if ( const auto * C = dyn_cast < ConstantSDNode > ( Ops [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) ) ) return C -> isNullValue ( ) ? DAG . getNode ( <STR_LIT> , dl , ty ( Op ) ) : DAG . getNode ( <STR_LIT> , dl , ty ( Op ) ) ; } break ; case <STR_LIT> : if ( Ops [ <NUM_LIT> ] . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , ty ( Op ) , DAG . getConstant ( - <NUM_LIT> , dl , <STR_LIT> ) ) ; if ( Ops [ <NUM_LIT> ] . getOpcode ( ) == <STR_LIT> ) return getZero ( dl , ty ( Op ) , DAG ) ; break ; case <STR_LIT> : if ( isUndef ( Ops [ <NUM_LIT> ] ) ) return Ops [ <NUM_LIT> ] ; ; break ; case <STR_LIT> : { if ( Ops [ <NUM_LIT> ] . getOpcode ( ) == <STR_LIT> ) { SDValue Vec = Ops [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) ; SDValue Rot0 = Ops [ <NUM_LIT> ] , Rot1 = Ops [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) ;

SDValue Rot = DAG . getNode ( <STR_LIT> , dl , ty ( Rot0 ) , { Rot0 , Rot1 } ) ;


<s> SDValue Base1 = DAG . getMemBasePlusOffset ( Base0 , TypeSize :: Fixed ( HwLen ) , dl ) ; MachineMemOperand * MOp0 = nullptr , * MOp1 = nullptr ; if ( MachineMemOperand * MMO = MemN -> getMemOperand ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MOp0 = MF . getMachineMemOperand ( MMO , <NUM_LIT> , HwLen ) ; MOp1 = MF . getMachineMemOperand ( MMO , HwLen , HwLen ) ; } unsigned MemOpc = MemN -> getOpcode ( ) ; if ( MemOpc == <STR_LIT> ) { assert ( cast < LoadSDNode > ( Op ) -> isUnindexed ( ) ) ; SDValue Load0 = DAG . getLoad ( SingleTy , dl , Chain , Base0 , MOp0 ) ; SDValue Load1 = DAG . getLoad ( SingleTy , dl , Chain , Base1 , MOp1 ) ; return DAG . getMergeValues ( { DAG . getNode ( <STR_LIT> , dl , MemTy , Load0 , Load1 ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load0 . getValue ( <NUM_LIT> ) , Load1 . getValue ( <NUM_LIT> ) ) } , dl ) ; } if ( MemOpc == <STR_LIT> ) { assert ( cast < StoreSDNode > ( Op ) -> isUnindexed ( ) ) ; VectorPair Vals = opSplit ( cast < StoreSDNode > ( Op ) -> getValue ( ) , dl , DAG ) ; SDValue Store0 = DAG . getStore ( Chain , dl , Vals . first , Base0 , MOp0 ) ; SDValue Store1 = DAG . getStore ( Chain , dl , Vals . second , Base1 , MOp1 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Store0 , Store1 ) ; } assert ( MemOpc == <STR_LIT> || MemOpc == <STR_LIT> ) ; auto MaskN = cast < MaskedLoadStoreSDNode > ( Op ) ; assert ( MaskN -> isUnindexed ( ) ) ; VectorPair Masks = opSplit ( MaskN -> getMask ( ) , dl , DAG ) ; SDValue Offset = DAG . getUNDEF ( <STR_LIT> ) ; if ( MemOpc == <STR_LIT> ) {

VectorPair Thru = opSplit ( cast < MaskedLoadSDNode > ( Op ) -> getPassThru ( ) , dl , DAG ) ;


<s> EVT ResTy = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , WideOpTy ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , ResTy , { WideOp0 , WideOp1 , Op . getOperand ( <NUM_LIT> ) } ) ; EVT RetTy = getTypeToTransformTo ( * DAG . getContext ( ) , ty ( Op ) ) ; return DAG . getNode ( <STR_LIT> , dl , RetTy , { SetCC , getZero ( dl , <STR_LIT> , DAG ) } ) ;


<s> SDValue Bytes = DAG . getLoad ( ByteTy , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( MF ) , Align ) ; SDValue Sel = DAG . getSelect ( dl , VecTy , VecQ , DAG . getBitcast ( VecTy , Bytes ) , getZero ( dl , VecTy , DAG ) ) ; SDValue All1 = DAG . getSplatBuildVector ( <STR_LIT> , dl , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Vrmpy = getInstr ( <STR_LIT> , dl , ByteTy , { Sel , All1 } , DAG ) ; SDValue Rot = getInstr ( <STR_LIT> , dl , ByteTy , { Vrmpy , Vrmpy , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) } , DAG ) ; SDValue Vor = DAG . getNode ( <STR_LIT> , dl , ByteTy , { Vrmpy , Rot } ) ;


<s> for ( unsigned j = <NUM_LIT> ; j != <NUM_LIT> ; ++ j ) Tmp . push_back ( ConstantInt :: get ( Int8Ty , <NUM_LIT> << j ) ) ; } Constant * CV = ConstantVector :: get ( Tmp ) ; unsigned Align = HwLen ; SDValue CP = LowerConstantPool ( DAG . getConstantPool ( CV , ByteTy , Align ) , DAG ) ; SDValue Bytes = DAG . getLoad ( ByteTy , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( MF ) , Align ) ; SDValue Sel = DAG . getSelect ( dl , VecTy , VecQ , DAG . getBitcast ( VecTy , Bytes ) , getZero ( dl , VecTy , DAG ) ) ; SDValue All1 = DAG . getSplatBuildVector ( <STR_LIT> , dl , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Vrmpy = getInstr ( <STR_LIT> , dl , ByteTy , { Sel , All1 } , DAG ) ; SDValue Rot = getInstr ( <STR_LIT> , dl , ByteTy , { Vrmpy , Vrmpy , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) } , DAG ) ; SDValue Vor = DAG . getNode ( <STR_LIT> , dl , ByteTy , { Vrmpy , Rot } ) ; SmallVector < int , <NUM_LIT> > Mask ; for ( unsigned i = <NUM_LIT> ; i != HwLen ; ++ i ) Mask . push_back ( ( <NUM_LIT> * i ) % HwLen + i / ( HwLen / <NUM_LIT> ) ) ;

SDValue Collect = DAG . getVectorShuffle ( ByteTy , dl , Vor , DAG . getUNDEF ( ByteTy ) , Mask ) ;


<s> } assert ( BitWidth == <NUM_LIT> || BitWidth == <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Words ; for ( unsigned i = <NUM_LIT> ; i != BitWidth / <NUM_LIT> ; ++ i ) { SDValue W = extractHvxElementReg ( VQ , DAG . getConstant ( i , dl , <STR_LIT> ) , dl , <STR_LIT> , DAG ) ; Words . push_back ( W ) ; } SmallVector < SDValue , <NUM_LIT> > Combines ; assert ( Words . size ( ) % <NUM_LIT> == <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Words . size ( ) ; i < e ; i += <NUM_LIT> ) { SDValue C = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { Words [ i ] , Words [ i + <NUM_LIT> ] } ) ; Combines . push_back ( C ) ; } if ( BitWidth == <NUM_LIT> ) return Combines [ <NUM_LIT> ] ; return DAG . getNode ( <STR_LIT> , dl , ResTy , Combines ) ;


<s> if ( VecTy . getSizeInBits ( ) > <NUM_LIT> * Subtarget . getVectorLength ( ) ) return false ; if ( ! Subtarget . isHVXVectorType ( VecTy , false ) ) return false ;


<s> bool <ISA_LIT>TargetLowering :: allowsHvxMisalignedMemoryAccesses ( MVT VecTy , unsigned Align , MachineMemOperand :: Flags Flags , bool * Fast ) const { if ( ! Subtarget . isHVXVectorType ( VecTy ) ) return false ;


<s> bool <ISA_LIT>TargetLowering :: allowsHvxMisalignedMemoryAccesses ( MVT VecTy , unsigned Align , MachineMemOperand :: Flags Flags , bool * Fast ) const { if ( ! Subtarget . isHVXVectorType ( VecTy ) ) return false ; if ( Fast ) * Fast = true ;


<s> } unsigned NumWords = Words . size ( ) ; bool IsSplat = true , IsUndef = true ; SDValue SplatV ; for ( unsigned i = <NUM_LIT> ; i != NumWords && IsSplat ; ++ i ) { if ( isUndef ( Words [ i ] ) ) continue ; IsUndef = false ; if ( ! SplatV . getNode ( ) ) SplatV = Words [ i ] ; else if ( SplatV != Words [ i ] ) IsSplat = false ; } if ( IsUndef ) return DAG . getUNDEF ( VecTy ) ; if ( IsSplat ) { assert ( SplatV . getNode ( ) ) ; auto * IdxN = dyn_cast < ConstantSDNode > ( SplatV . getNode ( ) ) ; if ( IdxN && IdxN -> isNullValue ( ) ) return getZero ( dl , VecTy , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , SplatV ) ; } SmallVector < ConstantInt * , <NUM_LIT> > Consts ( VecLen ) ; bool AllConst = getBuildVectorConstInts ( Values , VecTy , DAG , Consts ) ; if ( AllConst ) { ArrayRef < Constant * > Tmp ( ( Constant * * ) Consts . begin ( ) , ( Constant * * ) Consts . end ( ) ) ; Constant * CV = ConstantVector :: get ( Tmp ) ; Align Alignment ( HwLen ) ; SDValue CP = LowerConstantPool ( DAG . getConstantPool ( CV , VecTy , Alignment ) , DAG ) ; return DAG . getLoad ( VecTy , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( MF ) , Alignment ) ; } auto IsBuildFromExtracts = [ this , & Values ] ( SDValue & SrcVec , SmallVectorImpl < int > & SrcIdx ) { SDValue Vec ; for ( SDValue V : Values ) { if ( isUndef ( V ) ) { SrcIdx . push_back ( - <NUM_LIT> ) ; continue ; } if ( V . getOpcode ( ) != <STR_LIT> ) return false ;

SDValue T = V . getOperand ( <NUM_LIT> ) ;


<s> return Ty . isSimple ( ) && Subtarget . isHVXVectorType ( Ty . getSimpleVT ( ) , true ) ; } ; auto IsHvxOp = [ this ] ( SDValue Op ) { return Subtarget . isHVXVectorType ( ty ( Op ) , true ) ; } ;

return llvm :: any_of ( N -> values ( ) , IsHvxTy ) || llvm :: any_of ( N -> ops ( ) , IsHvxOp ) ;


<s> return DAG . getZExtOrTrunc ( W0 , dl , ResTy ) ; } assert ( BitWidth == <NUM_LIT> || BitWidth == <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Words ; for ( unsigned i = <NUM_LIT> ; i != BitWidth / <NUM_LIT> ; ++ i ) { SDValue W = extractHvxElementReg ( VQ , DAG . getConstant ( i , dl , <STR_LIT> ) , dl , <STR_LIT> , DAG ) ; Words . push_back ( W ) ; } SmallVector < SDValue , <NUM_LIT> > Combines ; assert ( Words . size ( ) % <NUM_LIT> == <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Words . size ( ) ; i < e ; i += <NUM_LIT> ) { SDValue C = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { Words [ i + <NUM_LIT> ] , Words [ i ] } ) ; Combines . push_back ( C ) ; }

if ( BitWidth == <NUM_LIT> ) return Combines [ <NUM_LIT> ] ;


<s> void <ISA_LIT>TargetLowering :: LowerHvxOperationWrapper ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const {


<s> if ( C1 -> getOpcode ( ) == <STR_LIT> ) { SDValue VSel = DCI . DAG . getNode ( <STR_LIT> , dl , ty ( Op ) , C0 , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; return VSel ;


<s> const SDLoc & dl ( N ) ; SDValue Op ( N , <NUM_LIT> ) ; unsigned Opc = Op . getOpcode ( ) ; if ( Opc == <STR_LIT> ) { SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; if ( Cond -> getOpcode ( ) == <STR_LIT> ) { SDValue C0 = Cond . getOperand ( <NUM_LIT> ) , C1 = Cond . getOperand ( <NUM_LIT> ) ;

if ( C1 -> getOpcode ( ) == <STR_LIT> ) {


<s> MVT VecTy ; int Length ; if ( Subtarget . useHVX64BOps ( ) ) { VecTy = <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ; Length = <NUM_LIT> ; } if ( Subtarget . useHVX128BOps ( ) ) { VecTy = <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ; Length = <NUM_LIT> ; } SDValue C8421 = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue InstrC8421 = getInstr ( <STR_LIT> , dl , <STR_LIT> , C8421 , DAG ) ; SDValue Vand = getInstr ( <STR_LIT> , dl , VecTy , { Op , InstrC8421 } , DAG ) ; SDValue C2 = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Valign = getInstr ( <STR_LIT> , dl , VecTy , { Vand , Vand , C2 } , DAG ) ; SDValue Vor = getInstr ( <STR_LIT> , dl , VecTy , { Vand , Valign } , DAG ) ; SDValue C1 = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Valign1 = getInstr ( <STR_LIT> , dl , VecTy , { Vor , Vor , C1 } , DAG ) ; SDValue Vor1 = getInstr ( <STR_LIT> , dl , VecTy , { Vor , Valign1 } , DAG ) ; SDValue Cff = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue InstrCff = getInstr ( <STR_LIT> , dl , <STR_LIT> , Cff , DAG ) ; SDValue Vsplat = getInstr ( <STR_LIT> , dl , VecTy , InstrCff , DAG ) ; SDValue Vand1 = getInstr ( <STR_LIT> , dl , VecTy , { Vor1 , Vsplat } , DAG ) ; SmallVector < SDValue , <NUM_LIT> > Elems ; for ( int i = <NUM_LIT> ; i < Length ; ++ i ) { Elems . push_back ( DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Elems . push_back ( DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Elems . push_back ( DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Elems . push_back ( DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SplitHvxPairOp ( Op , DAG ) ; } } switch ( Opc ) { default : break ; case <STR_LIT> : return LowerHvxBuildVector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxConcatVectors ( Op , DAG ) ; case <STR_LIT> : return LowerHvxInsertSubvector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxInsertElement ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtractSubvector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtractElement ( Op , DAG ) ; case <STR_LIT> : return LowerHvxBitcast ( Op , DAG ) ; case <STR_LIT> : return LowerHvxAnyExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxSignExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxZeroExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxCttz ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerHvxShift ( Op , DAG ) ; case <STR_LIT> : return LowerHvxMul ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerHvxMulh ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtend ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return Op ; case <STR_LIT> : return LowerHvxIntrinsic ( Op , DAG ) ; case <STR_LIT> : return LowerHvxStore ( Op , DAG ) ; case <STR_LIT> : return SDValue ( ) ;


<s> case <STR_LIT> : return LowerHvxConcatVectors ( Op , DAG ) ; case <STR_LIT> : return LowerHvxInsertSubvector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxInsertElement ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtractSubvector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtractElement ( Op , DAG ) ; case <STR_LIT> : return LowerHvxBitcast ( Op , DAG ) ; case <STR_LIT> : return LowerHvxAnyExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxSignExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxZeroExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxCttz ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerHvxShift ( Op , DAG ) ; case <STR_LIT> : return LowerHvxMul ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerHvxMulh ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtend ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return Op ; case <STR_LIT> : return LowerHvxIntrinsic ( Op , DAG ) ; case <STR_LIT> : return LowerHvxStore ( Op , DAG ) ; case <STR_LIT> : return SDValue ( ) ; } Op . dumpr ( & DAG ) ; llvm_unreachable ( <STR_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerHvxStore ( SDValue Op , SelectionDAG & DAG ) const { auto * N = Op . getNode ( ) ; const SDLoc & dl ( Op ) ; SDValue Q0 = N -> getOperand ( <NUM_LIT> ) ; EVT VTOp = Q0 . getNode ( ) -> getValueType ( <NUM_LIT> ) ; if ( Op . getOpcode ( ) != <STR_LIT> || VTOp != <STR_LIT> ) return Op ; SDValue Vor4 = HvxVecPredBitcastComputation ( Q0 , DAG ) ; SDValue C0 = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue InstrC0 = getInstr ( <STR_LIT> , dl , <STR_LIT> , C0 , DAG ) ; SDValue Vextract0 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { Vor4 , InstrC0 } , DAG ) ; SDValue C32 = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue InstrC32 = getInstr ( <STR_LIT> , dl , <STR_LIT> , C32 , DAG ) ; SDValue Vextract1 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { Vor4 , InstrC32 } , DAG ) ; SDValue Combine0 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { Vextract1 , Vextract0 } , DAG ) ; SDValue C64 = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue InstrC64 = getInstr ( <STR_LIT> , dl , <STR_LIT> , C64 , DAG ) ; SDValue Vextract2 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { Vor4 , InstrC64 } , DAG ) ; SDValue C96 = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue InstrC96 = getInstr ( <STR_LIT> , dl , <STR_LIT> , C96 , DAG ) ; SDValue Vextract3 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { Vor4 , InstrC96 } , DAG ) ; SDValue Combine1 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { Vextract3 , Vextract2 } , DAG ) ; StoreSDNode * ST = cast < StoreSDNode > ( Op . getNode ( ) ) ;

SDValue C8 = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ;


<s> const SDLoc & dl ( Op ) ; SmallVector < int , <NUM_LIT> > ShuffMask ; MVT ElemTy = ResTy . getVectorElementType ( ) ; unsigned VecLen = ResTy . getVectorNumElements ( ) ; SDValue Vs = Op . getOperand ( <NUM_LIT> ) ; SDValue Vt = Op . getOperand ( <NUM_LIT> ) ; switch ( ElemTy . SimpleTy ) { case <STR_LIT> : { MVT ExtTy = typeExtElem ( ResTy , <NUM_LIT> ) ; unsigned MpyOpc = ElemTy == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue M = getInstr ( MpyOpc , dl , ExtTy , { Vs , Vt } , DAG ) ; for ( unsigned I = <NUM_LIT> ; I < VecLen ; I += <NUM_LIT> ) { ShuffMask . push_back ( I ) ; ShuffMask . push_back ( I + VecLen ) ; } VectorPair P = opSplit ( opCastElem ( M , ElemTy , DAG ) , dl , DAG ) ; SDValue BS = getByteShuffle ( dl , P . first , P . second , ShuffMask , DAG ) ; return DAG . getBitcast ( ResTy , BS ) ; } case <STR_LIT> : return getInstr ( <STR_LIT> , dl , ResTy , { Vs , Vt } , DAG ) ; case <STR_LIT> : { auto MulL_V60 = [ & ] ( SDValue Vs , SDValue Vt ) { SDValue S16 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue T0 = getInstr ( <STR_LIT> , dl , ResTy , { Vs , Vt } , DAG ) ; SDValue T1 = getInstr ( <STR_LIT> , dl , ResTy , { T0 , S16 } , DAG ) ; SDValue T2 = getInstr ( <STR_LIT> , dl , ResTy , { T1 , Vs , Vt } , DAG ) ; return T2 ; } ;

auto MulL_V62 = [ & ] ( SDValue Vs , SDValue Vt ) {


<s> SDValue <ISA_LIT>TargetLowering :: PerformHvxDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; const SDLoc & dl ( N ) ; SelectionDAG & DAG = DCI . DAG ; SDValue Op ( N , <NUM_LIT> ) ; unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : { SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; if ( Cond -> getOpcode ( ) == <STR_LIT> ) { SDValue C0 = Cond . getOperand ( <NUM_LIT> ) , C1 = Cond . getOperand ( <NUM_LIT> ) ; if ( C1 -> getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , ty ( Op ) , C0 , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } break ; } case <STR_LIT> : if ( isUndef ( Op . getOperand ( <NUM_LIT> ) ) ) return Op . getOperand ( <NUM_LIT> ) ; break ; case <STR_LIT> : {

SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ;


<s> } break ; } case <STR_LIT> : if ( isUndef ( Op . getOperand ( <NUM_LIT> ) ) ) return Op . getOperand ( <NUM_LIT> ) ; break ; case <STR_LIT> : { SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { SDValue Vec = Op0 . getOperand ( <NUM_LIT> ) ; SDValue Rot0 = Op . getOperand ( <NUM_LIT> ) , Rot1 = Op0 . getOperand ( <NUM_LIT> ) ; SDValue Rot = DAG . getNode ( <STR_LIT> , dl , ty ( Rot0 ) , { Rot0 , Rot1 } ) ; return DAG . getNode ( <STR_LIT> , dl , ty ( Op ) , { Vec , Rot } ) ; } break ; }


<s> unsigned HwLen = Subtarget . getVectorLength ( ) ; assert ( VecLen <= HwLen || VecLen == <NUM_LIT> * HwLen ) ; SmallVector < SDValue , <NUM_LIT> > Bytes ; if ( VecLen <= HwLen ) { assert ( HwLen % VecLen == <NUM_LIT> ) ; unsigned BitBytes = HwLen / VecLen ; for ( SDValue V : Values ) { SDValue Ext = ! V . isUndef ( ) ? DAG . getZExtOrTrunc ( V , dl , <STR_LIT> ) : DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; for ( unsigned B = <NUM_LIT> ; B != BitBytes ; ++ B ) Bytes . push_back ( Ext ) ; } } else { for ( unsigned I = <NUM_LIT> ; I != VecLen ; I += <NUM_LIT> ) { unsigned B = <NUM_LIT> ; for ( ; B != <NUM_LIT> ; ++ B ) { if ( ! Values [ I + B ] . isUndef ( ) ) break ; } SDValue F = Values [ I + B ] ; SDValue Ext = ( B < <NUM_LIT> ) ? DAG . getZExtOrTrunc ( F , dl , <STR_LIT> ) : DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; Bytes . push_back ( Ext ) ; for ( ; B != <NUM_LIT> ; ++ B ) assert ( Values [ I + B ] . isUndef ( ) || Values [ I + B ] == F ) ; } }

MVT ByteTy = <STR_LIT> ( <STR_LIT> , HwLen ) ;


<s> unsigned Align = HwLen ; SDValue CP = LowerConstantPool ( DAG . getConstantPool ( CV , VecTy , Align ) , DAG ) ; return DAG . getLoad ( VecTy , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( MF ) , Align ) ; } unsigned ElemSize = ElemWidth / <NUM_LIT> ; assert ( ElemSize * VecLen == HwLen ) ; SmallVector < SDValue , <NUM_LIT> > Words ; if ( VecTy . getVectorElementType ( ) != <STR_LIT> ) { assert ( ( ElemSize == <NUM_LIT> || ElemSize == <NUM_LIT> ) && <STR_LIT> ) ; unsigned OpsPerWord = ( ElemSize == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; MVT PartVT = <STR_LIT> ( VecTy . getVectorElementType ( ) , OpsPerWord ) ; for ( unsigned i = <NUM_LIT> ; i != VecLen ; i += OpsPerWord ) { SDValue W = buildVector32 ( Values . slice ( i , OpsPerWord ) , dl , PartVT , DAG ) ; Words . push_back ( DAG . getBitcast ( <STR_LIT> , W ) ) ; } } else { Words . assign ( Values . begin ( ) , Values . end ( ) ) ; } assert ( <NUM_LIT> * Words . size ( ) == Subtarget . getVectorLength ( ) ) ; SDValue HalfV0 = getNode ( <STR_LIT> , dl , VecTy , { } , DAG ) ;

SDValue HalfV1 = getNode ( <STR_LIT> , dl , VecTy , { } , DAG ) ;


<s> MVT <ISA_LIT>TargetLowering :: getVecBoolVT ( ) const { return <STR_LIT> ( <STR_LIT> , <NUM_LIT> * Subtarget . getVectorLength ( ) ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) Ops . push_back ( Op . getOperand ( i ) ) ; if ( VecTy . getVectorElementType ( ) == <STR_LIT> ) return buildHvxVectorPred ( Ops , dl , VecTy , DAG ) ;

if ( VecTy . getSizeInBits ( ) == <NUM_LIT> * Subtarget . getVectorLength ( ) ) {


<s> SDValue V0 = buildHvxVectorSingle ( A . take_front ( Size / <NUM_LIT> ) , dl , SingleTy , DAG ) ; SDValue V1 = buildHvxVectorSingle ( A . drop_front ( Size / <NUM_LIT> ) , dl , SingleTy , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , V0 , V1 ) ; }

return buildHvxVectorSingle ( Ops , dl , VecTy , DAG ) ;


<s> if ( Idx == <NUM_LIT> ) return DAG . getTargetExtractSubreg ( <STR_LIT> , dl , DstTy , SrcV ) ; if ( Idx == SrcElems / <NUM_LIT> ) return DAG . getTargetExtractSubreg ( <STR_LIT> , dl , DstTy , SrcV ) ; return SDValue ( ) ;


<s> SDValue ValV = Op . getOperand ( <NUM_LIT> ) ; SDValue IdxV = Op . getOperand ( <NUM_LIT> ) ; MVT ElemTy = ty ( VecV ) . getVectorElementType ( ) ; unsigned ElemWidth = ElemTy . getSizeInBits ( ) ; assert ( ElemWidth >= <NUM_LIT> && ElemWidth <= <NUM_LIT> ) ; ( void ) ElemWidth ; auto InsertWord = [ & DAG , & dl , this ] ( SDValue VecV , SDValue ValV , SDValue ByteIdxV ) { MVT VecTy = ty ( VecV ) ; unsigned HwLen = Subtarget . getVectorLength ( ) ; SDValue MaskV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { ByteIdxV , DAG . getConstant ( - <NUM_LIT> , dl , <STR_LIT> ) } ) ; SDValue RotV = DAG . getNode ( <STR_LIT> , dl , VecTy , { VecV , MaskV } ) ; SDValue InsV = DAG . getNode ( <STR_LIT> , dl , VecTy , { RotV , ValV } ) ; SDValue SubV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { DAG . getConstant ( HwLen / <NUM_LIT> , dl , <STR_LIT> ) , MaskV } ) ; SDValue TorV = DAG . getNode ( <STR_LIT> , dl , VecTy , { InsV , SubV } ) ; return TorV ; } ; SDValue ByteIdx = convertToByteIndex ( IdxV , ElemTy , DAG ) ; if ( ElemTy == <STR_LIT> ) return InsertWord ( VecV , ValV , ByteIdx ) ; SDValue WordIdx = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { ByteIdx , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) } ) ; SDValue Ex0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { opCastElem ( VecV , <STR_LIT> , DAG ) , WordIdx } ) ; SDValue Ext = LowerHvxExtractElement ( Ex0 , DAG ) ; SDValue SubIdx = getIndexInWord32 ( IdxV , ElemTy , DAG ) ; MVT SubVecTy = tyVector ( ty ( Ext ) , ElemTy ) ;

SDValue Ins = insertVector ( DAG . getBitcast ( SubVecTy , Ext ) , ValV , SubIdx , dl , ElemTy , DAG ) ;


<s> SDValue ValV = Op . getOperand ( <NUM_LIT> ) ; SDValue IdxV = Op . getOperand ( <NUM_LIT> ) ; MVT ElemTy = ty ( VecV ) . getVectorElementType ( ) ; unsigned ElemWidth = ElemTy . getSizeInBits ( ) ; assert ( ElemWidth >= <NUM_LIT> && ElemWidth <= <NUM_LIT> ) ; ( void ) ElemWidth ; auto InsertWord = [ & DAG , & dl , this ] ( SDValue VecV , SDValue ValV , SDValue ByteIdxV ) { MVT VecTy = ty ( VecV ) ; unsigned HwLen = Subtarget . getVectorLength ( ) ; SDValue MaskV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { ByteIdxV , DAG . getConstant ( - <NUM_LIT> , dl , <STR_LIT> ) } ) ; SDValue RotV = DAG . getNode ( <STR_LIT> , dl , VecTy , { VecV , MaskV } ) ; SDValue InsV = DAG . getNode ( <STR_LIT> , dl , VecTy , { RotV , ValV } ) ; SDValue SubV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { DAG . getConstant ( HwLen / <NUM_LIT> , dl , <STR_LIT> ) , MaskV } ) ; SDValue TorV = DAG . getNode ( <STR_LIT> , dl , VecTy , { InsV , SubV } ) ; return TorV ; } ; SDValue ByteIdx = convertToByteIndex ( IdxV , ElemTy , DAG ) ; if ( ElemTy == <STR_LIT> ) return InsertWord ( VecV , ValV , ByteIdx ) ; SDValue WordIdx = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { ByteIdx , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) } ) ; SDValue Ex0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { opCastElem ( VecV , <STR_LIT> , DAG ) , WordIdx } ) ; SDValue Ext = LowerHvxExtractElement ( Ex0 , DAG ) ;

SDValue SubIdx = getIndexInWord32 ( IdxV , ElemTy , DAG ) ;


<s> SDValue IdxV = Op . getOperand ( <NUM_LIT> ) ; auto * IdxN = dyn_cast < ConstantSDNode > ( IdxV . getNode ( ) ) ; if ( ! IdxN ) return SDValue ( ) ; unsigned Idx = IdxN -> getZExtValue ( ) ; SDValue DstV = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcV = Op . getOperand ( <NUM_LIT> ) ; MVT DstTy = ty ( DstV ) ;


<s> } VectorPair P = opSplit ( opCastElem ( M , ElemTy , DAG ) , dl , DAG ) ; return getByteShuffle ( dl , P . first , P . second , ShuffMask , DAG ) ; } case <STR_LIT> : { SDValue S16 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue T0 = getNode ( <STR_LIT> , dl , ResTy , { Vs , Vt } , DAG ) ; SDValue T1 = getNode ( <STR_LIT> , dl , ResTy , { T0 , S16 } , DAG ) ; SDValue T2 = getNode ( <STR_LIT> , dl , ResTy , { T1 , Vs , Vt } , DAG ) ; return T2 ; } default :


<s> ShuffMask . push_back ( I + VecLen ) ; } VectorPair P = opSplit ( opCastElem ( M , ElemTy , DAG ) , dl , DAG ) ; return getByteShuffle ( dl , P . first , P . second , ShuffMask , DAG ) ; } case <STR_LIT> : { SDValue S16 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue T0 = getNode ( <STR_LIT> , dl , ResTy , { Vs , Vt } , DAG ) ; SDValue T1 = getNode ( <STR_LIT> , dl , ResTy , { T0 , S16 } , DAG ) ; SDValue T2 = getNode ( <STR_LIT> , dl , ResTy , { T1 , Vs , Vt } , DAG ) ; return T2 ; } default :


<s> MVT ElemTy = VecTy . getVectorElementType ( ) ; unsigned ElemWidth = ElemTy . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( ElemWidth ) ) ; auto getIdx = [ ] ( unsigned Code ) { static const unsigned Idx [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; for ( unsigned I = <NUM_LIT> , E = array_lengthof ( Idx ) ; I != E ; ++ I ) if ( Code == Idx [ I ] ) return I ; llvm_unreachable ( <STR_LIT> ) ; } ; static unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } ;

unsigned CmpOpc = OpcTable [ Log2_32 ( ElemWidth ) - <NUM_LIT> ] [ getIdx ( CC ) ] ;


<s> MVT VecTy = ty ( Op . getOperand ( <NUM_LIT> ) ) ; assert ( VecTy == ty ( Op . getOperand ( <NUM_LIT> ) ) ) ; SDValue Cmp = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Cmp ) -> get ( ) ; bool Negate = false , Swap = false ; switch ( CC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ( CC , true ) ; Negate = true ; break ; default : break ; } switch ( CC ) { case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ( CC ) ; Swap = true ; break ; default : break ; } assert ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ;

MVT ElemTy = VecTy . getVectorElementType ( ) ;


<s> TypePair Tys = typeSplit ( ty ( Vec ) ) ;

return DAG . SplitVector ( Vec , dl , Tys . first , Tys . second ) ;


<s> <ISA_LIT>TargetLowering :: VectorPair <ISA_LIT>TargetLowering :: opSplit ( SDValue Vec , const SDLoc & dl , SelectionDAG & DAG ) const { TypePair Tys = typeSplit ( ty ( Vec ) ) ;


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) Ops . push_back ( Op . getOperand ( i ) ) ; if ( VecTy . getVectorElementType ( ) == <STR_LIT> ) return buildHvxVectorPred ( Ops , dl , VecTy , DAG ) ; if ( VecTy . getVectorElementType ( ) == <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > NewOps ; for ( unsigned i = <NUM_LIT> ; i != Size ; i ++ ) NewOps . push_back ( DAG . getBitcast ( <STR_LIT> , Ops [ i ] ) ) ; SDValue T0 = DAG . getNode ( <STR_LIT> , dl , tyVector ( VecTy , <STR_LIT> ) , NewOps ) ; return DAG . getBitcast ( tyVector ( VecTy , <STR_LIT> ) , T0 ) ; } if ( VecTy . getSizeInBits ( ) == <NUM_LIT> * Subtarget . getVectorLength ( ) ) { ArrayRef < SDValue > A ( Ops ) ; MVT SingleTy = typeSplit ( VecTy ) . first ; SDValue V0 = buildHvxVectorReg ( A . take_front ( Size / <NUM_LIT> ) , dl , SingleTy , DAG ) ; SDValue V1 = buildHvxVectorReg ( A . drop_front ( Size / <NUM_LIT> ) , dl , SingleTy , DAG ) ;

return DAG . getNode ( <STR_LIT> , dl , VecTy , V0 , V1 ) ;


<s> SmallVector < SDValue , <NUM_LIT> > NewOps ; for ( unsigned i = <NUM_LIT> ; i != Size ; i ++ ) NewOps . push_back ( DAG . getBitcast ( <STR_LIT> , Ops [ i ] ) ) ; SDValue T0 = DAG . getNode ( <STR_LIT> , dl , tyVector ( VecTy , <STR_LIT> ) , NewOps ) ; return DAG . getBitcast ( tyVector ( VecTy , <STR_LIT> ) , T0 ) ; } if ( VecTy . getSizeInBits ( ) == <NUM_LIT> * Subtarget . getVectorLength ( ) ) { ArrayRef < SDValue > A ( Ops ) ; MVT SingleTy = typeSplit ( VecTy ) . first ; SDValue V0 = buildHvxVectorReg ( A . take_front ( Size / <NUM_LIT> ) , dl , SingleTy , DAG ) ; SDValue V1 = buildHvxVectorReg ( A . drop_front ( Size / <NUM_LIT> ) , dl , SingleTy , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , V0 , V1 ) ;


<s> case <STR_LIT> : case <STR_LIT> : return SplitHvxPairOp ( Op , DAG ) ; } } switch ( Opc ) { default : break ; case <STR_LIT> : return LowerHvxBuildVector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxConcatVectors ( Op , DAG ) ; case <STR_LIT> : return LowerHvxInsertSubvector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxInsertElement ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtractSubvector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtractElement ( Op , DAG ) ; case <STR_LIT> : return LowerHvxAnyExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxSignExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxZeroExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxCttz ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerHvxShift ( Op , DAG ) ; case <STR_LIT> : return LowerHvxMul ( Op , DAG ) ;


<s> bool HaveThreshold = HvxWidenThreshold . getNumOccurrences ( ) > <NUM_LIT> ; if ( HaveThreshold && <NUM_LIT> * HvxWidenThreshold <= VecWidth ) return TargetLoweringBase :: TypeWidenVector ; unsigned HwWidth = <NUM_LIT> * HwLen ; if ( VecWidth >= HwWidth / <NUM_LIT> && VecWidth < HwWidth ) return TargetLoweringBase :: TypeWidenVector ; } return ~ <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : return SplitHvxMemOp ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SplitHvxPairOp ( Op , DAG ) ; } } switch ( Opc ) { default : break ; case <STR_LIT> : return LowerHvxBuildVector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxConcatVectors ( Op , DAG ) ; case <STR_LIT> : return LowerHvxInsertSubvector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxInsertElement ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtractSubvector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtractElement ( Op , DAG ) ; case <STR_LIT> : return LowerHvxBitcast ( Op , DAG ) ; case <STR_LIT> : return LowerHvxAnyExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxSignExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxZeroExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxCttz ( Op , DAG ) ; case <STR_LIT> : return LowerHvxSelect ( Op , DAG ) ; case <STR_LIT> :


<s> assert ( shouldWidenToHvx ( ty ( cast < StoreSDNode > ( N ) -> getValue ( ) ) , DAG ) && <STR_LIT> ) ; SDValue Store = WidenHvxStore ( SDValue ( N , <NUM_LIT> ) , DAG ) ; Results . push_back ( Store ) ; break ; } case <STR_LIT> : if ( isHvxPairTy ( ty ( Op ) ) ) { SDValue S = SplitHvxMemOp ( Op , DAG ) ; assert ( S -> getOpcode ( ) == <STR_LIT> ) ; Results . push_back ( S . getOperand ( <NUM_LIT> ) ) ; Results . push_back ( S . getOperand ( <NUM_LIT> ) ) ;


<s> void <ISA_LIT>TargetLowering :: LowerHvxOperationWrapper ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { unsigned Opc = N -> getOpcode ( ) ; SDValue Op ( N , <NUM_LIT> ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( shouldWidenToHvx ( ty ( Op . getOperand ( <NUM_LIT> ) ) , DAG ) && <STR_LIT> ) ; if ( SDValue T = WidenHvxExtend ( Op , DAG ) ) Results . push_back ( T ) ; break ; case <STR_LIT> : assert ( shouldWidenToHvx ( ty ( Op . getOperand ( <NUM_LIT> ) ) , DAG ) && <STR_LIT> ) ; if ( SDValue T = WidenHvxTruncate ( Op , DAG ) ) Results . push_back ( T ) ; break ; case <STR_LIT> : { assert ( shouldWidenToHvx ( ty ( cast < StoreSDNode > ( N ) -> getValue ( ) ) , DAG ) && <STR_LIT> ) ; SDValue Store = WidenHvxStore ( SDValue ( N , <NUM_LIT> ) , DAG ) ; Results . push_back ( Store ) ; break ; } case <STR_LIT> : if ( isHvxPairTy ( ty ( Op ) ) ) { SDValue S = SplitHvxMemOp ( Op , DAG ) ; assert ( S -> getOpcode ( ) == <STR_LIT> ) ; Results . push_back ( S . getOperand ( <NUM_LIT> ) ) ; Results . push_back ( S . getOperand ( <NUM_LIT> ) ) ; } break ; case <STR_LIT> : if ( isHvxPairTy ( ty ( Op -> getOperand ( <NUM_LIT> ) ) ) ) {


<s> auto Action = getPreferredHvxVectorAction ( Ty ) ; if ( Action == TargetLoweringBase :: TypeWidenVector ) { EVT WideTy = getTypeToTransformTo ( * DAG . getContext ( ) , Ty ) ;


<s> case <STR_LIT> : if ( isUndef ( Op . getOperand ( <NUM_LIT> ) ) ) return Op . getOperand ( <NUM_LIT> ) ; break ; case <STR_LIT> : { SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { SDValue Vec = Op0 . getOperand ( <NUM_LIT> ) ; SDValue Rot0 = Op . getOperand ( <NUM_LIT> ) , Rot1 = Op0 . getOperand ( <NUM_LIT> ) ; SDValue Rot = DAG . getNode ( <STR_LIT> , dl , ty ( Rot0 ) , { Rot0 , Rot1 } ) ; return DAG . getNode ( <STR_LIT> , dl , ty ( Op ) , { Vec , Rot } ) ; }


<s> if ( Cond -> getOpcode ( ) == <STR_LIT> ) { SDValue C0 = Cond . getOperand ( <NUM_LIT> ) , C1 = Cond . getOperand ( <NUM_LIT> ) ; if ( C1 -> getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , ty ( Op ) , C0 , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } break ; } case <STR_LIT> : if ( isUndef ( Op . getOperand ( <NUM_LIT> ) ) ) return Op . getOperand ( <NUM_LIT> ) ; break ; case <STR_LIT> : { SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ;

if ( Op0 . getOpcode ( ) == <STR_LIT> ) {


<s> bool Use64b = Subtarget . useHVX64BOps ( ) ; ArrayRef < MVT > LegalV = Use64b ? LegalV64 : LegalV128 ; ArrayRef < MVT > LegalW = Use64b ? LegalW64 : LegalW128 ; MVT ByteV = Use64b ? <STR_LIT> : <STR_LIT> ; MVT ByteW = Use64b ? <STR_LIT> : <STR_LIT> ; auto setPromoteTo = [ this ] ( unsigned Opc , MVT FromTy , MVT ToTy ) { setOperationAction ( Opc , FromTy , Promote ) ; AddPromotedToType ( Opc , FromTy , ToTy ) ; } ; setOperationAction ( <STR_LIT> , ByteV , Legal ) ; setOperationAction ( <STR_LIT> , ByteW , Legal ) ; setOperationAction ( <STR_LIT> , ByteV , Legal ) ; setOperationAction ( <STR_LIT> , ByteV , Legal ) ; setOperationAction ( <STR_LIT> , ByteV , Legal ) ; for ( MVT T : LegalV ) { setIndexedLoadAction ( <STR_LIT> , T , Legal ) ; setIndexedStoreAction ( <STR_LIT> , T , Legal ) ; setOperationAction ( <STR_LIT> , T , Legal ) ; setOperationAction ( <STR_LIT> , T , Legal ) ; if ( T != ByteV ) { setOperationAction ( <STR_LIT> , T , Legal ) ; setOperationAction ( <STR_LIT> , T , Legal ) ; } setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; if ( T != ByteV ) { setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; } setCondCodeAction ( <STR_LIT> , T , Expand ) ; setCondCodeAction ( <STR_LIT> , T , Expand ) ; setCondCodeAction ( <STR_LIT> , T , Expand ) ; setCondCodeAction ( <STR_LIT> , T , Expand ) ; setCondCodeAction ( <STR_LIT> , T , Expand ) ; setCondCodeAction ( <STR_LIT> , T , Expand ) ; setCondCodeAction ( <STR_LIT> , T , Expand ) ;


<s> bool IsPairOp = isHvxPairTy ( ty ( Op ) ) || llvm :: any_of ( Op . getNode ( ) -> ops ( ) , [ this ] ( SDValue V ) { return isHvxPairTy ( ty ( V ) ) ; } ) ; if ( IsPairOp ) { switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SplitHvxPairOp ( Op , DAG ) ; } } switch ( Opc ) {


<s> MVT ElemTy = VecTy . getVectorElementType ( ) ; unsigned VecLen = VecTy . getVectorNumElements ( ) ; unsigned HwLen = Subtarget . getVectorLength ( ) ; if ( ElemTy == <STR_LIT> && VecLen == <NUM_LIT> * HwLen ) return TargetLoweringBase :: TypeSplitVector ; if ( ElemTy == <STR_LIT> ) ElemTy = <STR_LIT> ; ArrayRef < MVT > Tys = Subtarget . getHVXElementTypes ( ) ; if ( llvm :: is_contained ( Tys , ElemTy ) ) { unsigned VecWidth = VecTy . getSizeInBits ( ) ;

bool HaveThreshold = HvxWidenThreshold . getNumOccurrences ( ) > <NUM_LIT> ;


<s> for ( unsigned I = <NUM_LIT> ; I != VecLen ; I += <NUM_LIT> ) { unsigned B = <NUM_LIT> ; for ( ; B != <NUM_LIT> ; ++ B ) { if ( ! Values [ I + B ] . isUndef ( ) ) break ; } SDValue F = Values [ I + B ] ; SDValue Ext = ( B < <NUM_LIT> ) ? DAG . getZExtOrTrunc ( F , dl , <STR_LIT> ) : DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; Bytes . push_back ( Ext ) ; for ( ; B != <NUM_LIT> ; ++ B ) assert ( Values [ I + B ] . isUndef ( ) || Values [ I + B ] == F ) ;


<s> if ( ! SplatV . getNode ( ) ) SplatV = Words [ i ] ; else if ( SplatV != Words [ i ] ) IsSplat = false ; } if ( IsSplat ) { assert ( SplatV . getNode ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , SplatV ) ; } assert ( <NUM_LIT> * Words . size ( ) == Subtarget . getVectorLength ( ) ) ; SDValue HalfV0 = getNode ( <STR_LIT> , dl , VecTy , { } , DAG ) ; SDValue HalfV1 = getNode ( <STR_LIT> , dl , VecTy , { } , DAG ) ; SDValue S = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumWords / <NUM_LIT> ; ++ i ) { SDValue N = DAG . getNode ( <STR_LIT> , dl , VecTy , { HalfV0 , Words [ i ] } ) ; SDValue M = DAG . getNode ( <STR_LIT> , dl , VecTy , { HalfV1 , Words [ i + NumWords / <NUM_LIT> ] } ) ; HalfV0 = DAG . getNode ( <STR_LIT> , dl , VecTy , { N , S } ) ; HalfV1 = DAG . getNode ( <STR_LIT> , dl , VecTy , { M , S } ) ; }

HalfV0 = DAG . getNode ( <STR_LIT> , dl , VecTy , { HalfV0 , DAG . getConstant ( HwLen / <NUM_LIT> , dl , <STR_LIT> ) } ) ;


<s> if ( AllConst ) { if ( llvm :: all_of ( Consts , [ ] ( ConstantInt * CI ) { return CI -> isZero ( ) ; } ) ) return getZero ( dl , VecTy , DAG ) ; ArrayRef < Constant * > Tmp ( ( Constant * * ) Consts . begin ( ) , ( Constant * * ) Consts . end ( ) ) ; Constant * CV = ConstantVector :: get ( Tmp ) ; unsigned Align = HwLen ; SDValue CP = LowerConstantPool ( DAG . getConstantPool ( CV , VecTy , Align ) , DAG ) ; return DAG . getLoad ( VecTy , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( MF ) , Align ) ; } unsigned ElemSize = ElemWidth / <NUM_LIT> ; assert ( ElemSize * VecLen == HwLen ) ; SmallVector < SDValue , <NUM_LIT> > Words ; if ( VecTy . getVectorElementType ( ) != <STR_LIT> ) { assert ( ( ElemSize == <NUM_LIT> || ElemSize == <NUM_LIT> ) && <STR_LIT> ) ; unsigned OpsPerWord = ( ElemSize == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; MVT PartVT = <STR_LIT> ( VecTy . getVectorElementType ( ) , OpsPerWord ) ; for ( unsigned i = <NUM_LIT> ; i != VecLen ; i += OpsPerWord ) { SDValue W = buildVector32 ( Values . slice ( i , OpsPerWord ) , dl , PartVT , DAG ) ; Words . push_back ( DAG . getBitcast ( <STR_LIT> , W ) ) ; } } else { Words . assign ( Values . begin ( ) , Values . end ( ) ) ; } unsigned NumWords = Words . size ( ) ; bool IsUndef = true , IsSplat = true ; SDValue SplatV ; for ( unsigned i = <NUM_LIT> ; i != NumWords && IsSplat ; ++ i ) { if ( isUndef ( Words [ i ] ) ) continue ; IsUndef = false ; if ( ! SplatV . getNode ( ) ) SplatV = Words [ i ] ; else if ( SplatV != Words [ i ] ) IsSplat = false ;


<s> MVT PredTy = ty ( PredV ) ; unsigned HwLen = Subtarget . getVectorLength ( ) ; MVT ByteTy = <STR_LIT> ( <STR_LIT> , HwLen ) ; if ( Subtarget . isHVXVectorType ( PredTy , true ) ) { SDValue T = DAG . getNode ( <STR_LIT> , dl , ByteTy , PredV ) ; SmallVector < int , <NUM_LIT> > Mask ( HwLen ) ; unsigned Scale = HwLen / ( PredTy . getVectorNumElements ( ) * BitBytes ) ; unsigned BlockLen = PredTy . getVectorNumElements ( ) * BitBytes ; for ( unsigned i = <NUM_LIT> ; i != HwLen ; ++ i ) { unsigned Num = i % Scale ; unsigned Off = i / Scale ; Mask [ BlockLen * Num + Off ] = i ; } SDValue S = DAG . getVectorShuffle ( ByteTy , dl , T , DAG . getUNDEF ( ByteTy ) , Mask ) ; if ( ! ZeroFill ) return S ; MVT BoolTy = <STR_LIT> ( <STR_LIT> , HwLen ) ; SDValue Q = getNode ( <STR_LIT> , dl , BoolTy , { DAG . getConstant ( BlockLen , dl , <STR_LIT> ) } , DAG ) ; SDValue M = DAG . getNode ( <STR_LIT> , dl , ByteTy , Q ) ; return DAG . getNode ( <STR_LIT> , dl , ByteTy , S , M ) ; } assert ( PredTy == <STR_LIT> || PredTy == <STR_LIT> || PredTy == <STR_LIT> ) ; unsigned Bytes = <NUM_LIT> / PredTy . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > Words [ <NUM_LIT> ] ; unsigned IdxW = <NUM_LIT> ; auto Lo32 = [ & DAG , & dl ] ( SDValue P ) { return DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , P ) ; } ; auto Hi32 = [ & DAG , & dl ] ( SDValue P ) { return DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , P ) ; } ; SDValue W0 = isUndef ( PredV ) ? DAG . getUNDEF ( <STR_LIT> ) : DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , PredV ) ; Words [ IdxW ] . push_back ( Hi32 ( W0 ) ) ; Words [ IdxW ] . push_back ( Lo32 ( W0 ) ) ; while ( Bytes < BitBytes ) { IdxW ^= <NUM_LIT> ; Words [ IdxW ] . clear ( ) ; if ( Bytes < <NUM_LIT> ) { for ( const SDValue & W : Words [ IdxW ^ <NUM_LIT> ] ) { SDValue T = expandPredicate ( W , dl , DAG ) ; Words [ IdxW ] . push_back ( Hi32 ( T ) ) ; Words [ IdxW ] . push_back ( Lo32 ( T ) ) ; }


<s> SDValue ByteVec = DAG . getNode ( <STR_LIT> , dl , ByteTy , VecV ) ; unsigned Scale = HwLen / ty ( VecV ) . getVectorNumElements ( ) ; SDValue ScV = DAG . getConstant ( Scale , dl , <STR_LIT> ) ; IdxV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , ScV ) ; SDValue ExtB = extractHvxElementReg ( ByteVec , IdxV , dl , <STR_LIT> , DAG ) ; SDValue Zero = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ;

return getNode ( <STR_LIT> , dl , <STR_LIT> , { ExtB , Zero } , DAG ) ;


<s> unsigned Rep = VecTy . getVectorNumElements ( ) / ResLen ; assert ( isPowerOf2_32 ( Rep ) && HwLen % Rep == <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != HwLen / Rep ; ++ i ) { for ( unsigned j = <NUM_LIT> ; j != Rep ; ++ j ) Mask . push_back ( i + Offset ) ; } SDValue ShuffV = DAG . getVectorShuffle ( ByteTy , dl , ByteVec , Undef , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , ResTy , ShuffV ) ; } unsigned Rep = <NUM_LIT> / ResLen ; for ( unsigned r = <NUM_LIT> ; r != HwLen / ResLen ; ++ r ) { for ( unsigned i = <NUM_LIT> ; i != ResLen ; ++ i ) { for ( unsigned j = <NUM_LIT> ; j != Rep ; ++ j ) Mask . push_back ( Offset + i * BitBytes ) ; }


<s> SmallVector < int , <NUM_LIT> > Mask ; if ( Subtarget . isHVXVectorType ( ResTy , true ) ) { unsigned Rep = VecTy . getVectorNumElements ( ) / ResLen ; assert ( isPowerOf2_32 ( Rep ) && HwLen % Rep == <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != HwLen / Rep ; ++ i ) { for ( unsigned j = <NUM_LIT> ; j != Rep ; ++ j ) Mask . push_back ( i + Offset ) ; } SDValue ShuffV = DAG . getVectorShuffle ( ByteTy , dl , ByteVec , Undef , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , ResTy , ShuffV ) ; } unsigned Rep = <NUM_LIT> / ResLen ; for ( unsigned r = <NUM_LIT> ; r != HwLen / ResLen ; ++ r ) { for ( unsigned i = <NUM_LIT> ; i != ResLen ; ++ i ) { for ( unsigned j = <NUM_LIT> ; j != Rep ; ++ j ) Mask . push_back ( Offset + i * BitBytes ) ; }


<s> if ( Idx * ElemWidth >= <NUM_LIT> * HwLen ) { SubIdx = <STR_LIT> ; Idx -= VecTy . getVectorNumElements ( ) / <NUM_LIT> ; } else { SubIdx = <STR_LIT> ; } VecTy = typeSplit ( VecTy ) . first ; VecV = DAG . getTargetExtractSubreg ( SubIdx , dl , VecTy , VecV ) ; if ( VecTy == ResTy ) return VecV ; } assert ( ResTy . getSizeInBits ( ) == <NUM_LIT> || ResTy . getSizeInBits ( ) == <NUM_LIT> ) ; MVT WordTy = tyVector ( VecTy , <STR_LIT> ) ; SDValue WordVec = DAG . getBitcast ( WordTy , VecV ) ; unsigned WordIdx = ( Idx * ElemWidth ) / <NUM_LIT> ;

SDValue W0Idx = DAG . getConstant ( WordIdx , dl , <STR_LIT> ) ;


<s> unsigned Scale = VecLen / SubTy . getVectorNumElements ( ) ; unsigned BitBytes = HwLen / VecLen ; unsigned BlockLen = HwLen / Scale ; MVT ByteTy = <STR_LIT> ( <STR_LIT> , HwLen ) ; SDValue ByteVec = DAG . getNode ( <STR_LIT> , dl , ByteTy , VecV ) ; SDValue ByteSub = createHvxPrefixPred ( SubV , dl , BitBytes , false , DAG ) ; SDValue ByteIdx ; auto * IdxN = dyn_cast < ConstantSDNode > ( IdxV . getNode ( ) ) ; if ( ! IdxN || ! IdxN -> isNullValue ( ) ) { ByteIdx = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , DAG . getConstant ( BitBytes , dl , <STR_LIT> ) ) ; ByteVec = DAG . getNode ( <STR_LIT> , dl , ByteTy , ByteVec , ByteIdx ) ; } MVT BoolTy = <STR_LIT> ( <STR_LIT> , HwLen ) ; SDValue Q = getNode ( <STR_LIT> , dl , BoolTy , { DAG . getConstant ( BlockLen , dl , <STR_LIT> ) } , DAG ) ; ByteVec = getNode ( <STR_LIT> , dl , ByteTy , { Q , ByteSub , ByteVec } , DAG ) ; if ( ! IdxN || ! IdxN -> isNullValue ( ) ) { SDValue HwLenV = DAG . getConstant ( HwLen , dl , <STR_LIT> ) ; SDValue ByteXdi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HwLenV , ByteIdx ) ; ByteVec = DAG . getNode ( <STR_LIT> , dl , ByteTy , ByteVec , ByteXdi ) ;


<s> unsigned BitBytes = HwLen / VecLen ; unsigned BlockLen = HwLen / Scale ; MVT ByteTy = <STR_LIT> ( <STR_LIT> , HwLen ) ; SDValue ByteVec = DAG . getNode ( <STR_LIT> , dl , ByteTy , VecV ) ; SDValue ByteSub = createHvxPrefixPred ( SubV , dl , BitBytes , false , DAG ) ; SDValue ByteIdx ; auto * IdxN = dyn_cast < ConstantSDNode > ( IdxV . getNode ( ) ) ; if ( ! IdxN || ! IdxN -> isNullValue ( ) ) { ByteIdx = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , DAG . getConstant ( BitBytes , dl , <STR_LIT> ) ) ; ByteVec = DAG . getNode ( <STR_LIT> , dl , ByteTy , ByteVec , ByteIdx ) ; } MVT BoolTy = <STR_LIT> ( <STR_LIT> , HwLen ) ; SDValue Q = getNode ( <STR_LIT> , dl , BoolTy , { DAG . getConstant ( BlockLen , dl , <STR_LIT> ) } , DAG ) ; ByteVec = getNode ( <STR_LIT> , dl , ByteTy , { Q , ByteSub , ByteVec } , DAG ) ; if ( ! IdxN || ! IdxN -> isNullValue ( ) ) { SDValue HwLenV = DAG . getConstant ( HwLen , dl , <STR_LIT> ) ;

SDValue ByteXdi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HwLenV , ByteIdx ) ;


<s> unsigned NumOp = Op . getNumOperands ( ) ; assert ( isPowerOf2_32 ( NumOp ) && HwLen % NumOp == <NUM_LIT> ) ; ( void ) NumOp ; unsigned BitBytes = HwLen / VecTy . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > Prefixes ; for ( SDValue V : Op . getNode ( ) -> op_values ( ) ) { SDValue P = createHvxPrefixPred ( V , dl , BitBytes , true , DAG ) ; Prefixes . push_back ( P ) ; } unsigned InpLen = ty ( Op . getOperand ( <NUM_LIT> ) ) . getVectorNumElements ( ) ; MVT ByteTy = <STR_LIT> ( <STR_LIT> , HwLen ) ;

SDValue S = DAG . getConstant ( InpLen * BitBytes , dl , <STR_LIT> ) ;


<s> ShuffMask . push_back ( I ) ; ShuffMask . push_back ( I + VecLen ) ; } VectorPair P = opSplit ( opCastElem ( M , ElemTy , DAG ) , dl , DAG ) ; SDValue BS = getByteShuffle ( dl , P . first , P . second , ShuffMask , DAG ) ; return DAG . getBitcast ( ResTy , BS ) ; } case <STR_LIT> : { SDValue S16 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue T0 = getNode ( <STR_LIT> , dl , ResTy , { Vs , Vt } , DAG ) ; SDValue T1 = getNode ( <STR_LIT> , dl , ResTy , { T0 , S16 } , DAG ) ; SDValue T2 = getNode ( <STR_LIT> , dl , ResTy , { T1 , Vs , Vt } , DAG ) ; return T2 ; } default : break ; } return SDValue ( ) ;


<s> SDValue Vs = Op . getOperand ( <NUM_LIT> ) ; SDValue Vt = Op . getOperand ( <NUM_LIT> ) ; switch ( ElemTy . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : { MVT ExtTy = typeExtElem ( ResTy , <NUM_LIT> ) ; unsigned MpyOpc = ElemTy == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue M = getNode ( MpyOpc , dl , ExtTy , { Vs , Vt } , DAG ) ; for ( unsigned I = <NUM_LIT> ; I < VecLen ; I += <NUM_LIT> ) { ShuffMask . push_back ( I ) ; ShuffMask . push_back ( I + VecLen ) ; } VectorPair P = opSplit ( opCastElem ( M , ElemTy , DAG ) , dl , DAG ) ; SDValue BS = getByteShuffle ( dl , P . first , P . second , ShuffMask , DAG ) ; return DAG . getBitcast ( ResTy , BS ) ; } case <STR_LIT> : { SDValue S16 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue T0 = getNode ( <STR_LIT> , dl , ResTy , { Vs , Vt } , DAG ) ; SDValue T1 = getNode ( <STR_LIT> , dl , ResTy , { T0 , S16 } , DAG ) ; SDValue T2 = getNode ( <STR_LIT> , dl , ResTy , { T1 , Vs , Vt } , DAG ) ; return T2 ; } default : break ;


<s> ShuffMask . push_back ( I + VecLen + <NUM_LIT> ) ; } VectorPair P = opSplit ( opCastElem ( M , ElemTy , DAG ) , dl , DAG ) ; SDValue BS = getByteShuffle ( dl , P . first , P . second , ShuffMask , DAG ) ; return DAG . getBitcast ( ResTy , BS ) ; } assert ( ElemTy == <STR_LIT> ) ; SDValue S16 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; if ( IsSigned ) { SDValue T0 = getNode ( <STR_LIT> , dl , ResTy , { Vt , Vs } , DAG ) ; SDValue S0 = getNode ( <STR_LIT> , dl , ResTy , { Vs , S16 } , DAG ) ; SDValue T1 = getNode ( <STR_LIT> , dl , ResTy , { T0 , S0 , Vt } , DAG ) ; SDValue S2 = getNode ( <STR_LIT> , dl , ResTy , { T1 , S16 } , DAG ) ; SDValue T2 = getNode ( <STR_LIT> , dl , ResTy , { S0 , Vt } , DAG ) ; SDValue T3 = DAG . getNode ( <STR_LIT> , dl , ResTy , { S2 , T2 } ) ; return T3 ; } auto LoVec = [ & DAG , ResTy , dl ] ( SDValue Pair ) { return DAG . getTargetExtractSubreg ( <STR_LIT> , dl , ResTy , Pair ) ; } ; auto HiVec = [ & DAG , ResTy , dl ] ( SDValue Pair ) { return DAG . getTargetExtractSubreg ( <STR_LIT> , dl , ResTy , Pair ) ; } ; MVT PairTy = typeJoin ( { ResTy , ResTy } ) ; SDValue P = getNode ( <STR_LIT> , dl , ResTy , { DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) } , DAG ) ; SDValue T0 = getNode ( <STR_LIT> , dl , PairTy , { Vs , Vt } , DAG ) ; SDValue T1 = getNode ( <STR_LIT> , dl , ResTy , { LoVec ( T0 ) , S16 } , DAG ) ; SDValue D0 = getNode ( <STR_LIT> , dl , ResTy , { Vt , P } , DAG ) ;

SDValue T2 = getNode ( <STR_LIT> , dl , PairTy , { Vs , D0 } , DAG ) ;


<s> bool AllT = true , AllF = true ; auto IsTrue = [ ] ( SDValue V ) { if ( const auto * N = dyn_cast < ConstantSDNode > ( V . getNode ( ) ) ) return ! N -> isNullValue ( ) ; return false ; } ; auto IsFalse = [ ] ( SDValue V ) { if ( const auto * N = dyn_cast < ConstantSDNode > ( V . getNode ( ) ) ) return N -> isNullValue ( ) ; return false ; } ; if ( VecLen <= HwLen ) { assert ( HwLen % VecLen == <NUM_LIT> ) ; unsigned BitBytes = HwLen / VecLen ; for ( SDValue V : Values ) { AllT &= IsTrue ( V ) ; AllF &= IsFalse ( V ) ; SDValue Ext = ! V . isUndef ( ) ? DAG . getZExtOrTrunc ( V , dl , <STR_LIT> ) : DAG . getUNDEF ( <STR_LIT> ) ; for ( unsigned B = <NUM_LIT> ; B != BitBytes ; ++ B ) Bytes . push_back ( Ext ) ; } } else { for ( unsigned I = <NUM_LIT> ; I != VecLen ; I += <NUM_LIT> ) { unsigned B = <NUM_LIT> ; for ( ; B != <NUM_LIT> ; ++ B ) { if ( ! Values [ I + B ] . isUndef ( ) ) break ; } SDValue F = Values [ I + B ] ; AllT &= IsTrue ( F ) ;


<s> MVT ElemTy = VecTy . getVectorElementType ( ) ; unsigned ElemWidth = ElemTy . getSizeInBits ( ) ; unsigned HwLen = Subtarget . getVectorLength ( ) ; unsigned ElemSize = ElemWidth / <NUM_LIT> ; assert ( ElemSize * VecLen == HwLen ) ; SmallVector < SDValue , <NUM_LIT> > Words ; if ( VecTy . getVectorElementType ( ) != <STR_LIT> ) { assert ( ( ElemSize == <NUM_LIT> || ElemSize == <NUM_LIT> ) && <STR_LIT> ) ; unsigned OpsPerWord = ( ElemSize == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; MVT PartVT = <STR_LIT> ( VecTy . getVectorElementType ( ) , OpsPerWord ) ; for ( unsigned i = <NUM_LIT> ; i != VecLen ; i += OpsPerWord ) { SDValue W = buildVector32 ( Values . slice ( i , OpsPerWord ) , dl , PartVT , DAG ) ; Words . push_back ( DAG . getBitcast ( <STR_LIT> , W ) ) ; } } else { Words . assign ( Values . begin ( ) , Values . end ( ) ) ; } unsigned NumWords = Words . size ( ) ; bool IsSplat = true , IsUndef = true ; SDValue SplatV ; for ( unsigned i = <NUM_LIT> ; i != NumWords && IsSplat ; ++ i ) { if ( isUndef ( Words [ i ] ) ) continue ; IsUndef = false ; if ( ! SplatV . getNode ( ) ) SplatV = Words [ i ] ; else if ( SplatV != Words [ i ] ) IsSplat = false ; } if ( IsUndef ) return DAG . getUNDEF ( VecTy ) ; if ( IsSplat ) { assert ( SplatV . getNode ( ) ) ; auto * IdxN = dyn_cast < ConstantSDNode > ( SplatV . getNode ( ) ) ; if ( IdxN && IdxN -> isNullValue ( ) ) return getZero ( dl , VecTy , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , SplatV ) ; } SmallVector < ConstantInt * , <NUM_LIT> > Consts ( VecLen ) ; bool AllConst = getBuildVectorConstInts ( Values , VecTy , DAG , Consts ) ; if ( AllConst ) { ArrayRef < Constant * > Tmp ( ( Constant * * ) Consts . begin ( ) , ( Constant * * ) Consts . end ( ) ) ; Constant * CV = ConstantVector :: get ( Tmp ) ; unsigned Align = HwLen ; SDValue CP = LowerConstantPool ( DAG . getConstantPool ( CV , VecTy , Align ) , DAG ) ; return DAG . getLoad ( VecTy , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( MF ) , Align ) ; } auto IsBuildFromExtracts = [ this , & Values ] ( SDValue & SrcVec , SmallVectorImpl < int > & SrcIdx ) { SDValue Vec ;


<s> MVT PartVT = <STR_LIT> ( VecTy . getVectorElementType ( ) , OpsPerWord ) ; for ( unsigned i = <NUM_LIT> ; i != VecLen ; i += OpsPerWord ) { SDValue W = buildVector32 ( Values . slice ( i , OpsPerWord ) , dl , PartVT , DAG ) ; Words . push_back ( DAG . getBitcast ( <STR_LIT> , W ) ) ; } } else { Words . assign ( Values . begin ( ) , Values . end ( ) ) ; } unsigned NumWords = Words . size ( ) ; bool IsSplat = true , IsUndef = true ; SDValue SplatV ; for ( unsigned i = <NUM_LIT> ; i != NumWords && IsSplat ; ++ i ) { if ( isUndef ( Words [ i ] ) ) continue ; IsUndef = false ; if ( ! SplatV . getNode ( ) ) SplatV = Words [ i ] ; else if ( SplatV != Words [ i ] ) IsSplat = false ; } if ( IsUndef ) return DAG . getUNDEF ( VecTy ) ; if ( IsSplat ) { assert ( SplatV . getNode ( ) ) ; auto * IdxN = dyn_cast < ConstantSDNode > ( SplatV . getNode ( ) ) ; if ( IdxN && IdxN -> isNullValue ( ) ) return getZero ( dl , VecTy , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , SplatV ) ; } SmallVector < ConstantInt * , <NUM_LIT> > Consts ( VecLen ) ; bool AllConst = getBuildVectorConstInts ( Values , VecTy , DAG , Consts ) ; if ( AllConst ) { ArrayRef < Constant * > Tmp ( ( Constant * * ) Consts . begin ( ) , ( Constant * * ) Consts . end ( ) ) ; Constant * CV = ConstantVector :: get ( Tmp ) ; unsigned Align = HwLen ; SDValue CP = LowerConstantPool ( DAG . getConstantPool ( CV , VecTy , Align ) , DAG ) ; return DAG . getLoad ( VecTy , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( MF ) , Align ) ; } auto IsBuildFromExtracts = [ this , & Values ] ( SDValue & SrcVec , SmallVectorImpl < int > & SrcIdx ) { SDValue Vec ; for ( SDValue V : Values ) { if ( isUndef ( V ) ) { SrcIdx . push_back ( - <NUM_LIT> ) ; continue ; } if ( V . getOpcode ( ) != <STR_LIT> ) return false ;

SDValue T = V . getOperand ( <NUM_LIT> ) ;


<s> unsigned IdxW = <NUM_LIT> ; auto Lo32 = [ & DAG , & dl ] ( SDValue P ) { return DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , P ) ; } ; auto Hi32 = [ & DAG , & dl ] ( SDValue P ) { return DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , P ) ; } ; SDValue W0 = isUndef ( PredV ) ? DAG . getUNDEF ( <STR_LIT> ) : DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , PredV ) ; Words [ IdxW ] . push_back ( Hi32 ( W0 ) ) ; Words [ IdxW ] . push_back ( Lo32 ( W0 ) ) ; while ( Bytes < BitBytes ) { IdxW ^= <NUM_LIT> ; Words [ IdxW ] . clear ( ) ; if ( Bytes < <NUM_LIT> ) { for ( const SDValue & W : Words [ IdxW ^ <NUM_LIT> ] ) { SDValue T = expandPredicate ( W , dl , DAG ) ; Words [ IdxW ] . push_back ( Hi32 ( T ) ) ; Words [ IdxW ] . push_back ( Lo32 ( T ) ) ; } } else {


<s> return DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , P ) ; } ; auto Hi32 = [ & DAG , & dl ] ( SDValue P ) { return DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , P ) ; } ; SDValue W0 = isUndef ( PredV ) ? DAG . getUNDEF ( <STR_LIT> ) : DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , PredV ) ; Words [ IdxW ] . push_back ( Hi32 ( W0 ) ) ; Words [ IdxW ] . push_back ( Lo32 ( W0 ) ) ; while ( Bytes < BitBytes ) { IdxW ^= <NUM_LIT> ; Words [ IdxW ] . clear ( ) ; if ( Bytes < <NUM_LIT> ) { for ( const SDValue & W : Words [ IdxW ^ <NUM_LIT> ] ) { SDValue T = expandPredicate ( W , dl , DAG ) ; Words [ IdxW ] . push_back ( Hi32 ( T ) ) ; Words [ IdxW ] . push_back ( Lo32 ( T ) ) ; } } else { for ( const SDValue & W : Words [ IdxW ^ <NUM_LIT> ] ) { Words [ IdxW ] . push_back ( W ) ; Words [ IdxW ] . push_back ( W ) ; } } Bytes *= <NUM_LIT> ; } assert ( Bytes == BitBytes ) ; SDValue Vec = ZeroFill ? getZero ( dl , ByteTy , DAG ) : DAG . getUNDEF ( ByteTy ) ; SDValue S4 = DAG . getConstant ( HwLen - <NUM_LIT> , dl , <STR_LIT> ) ; for ( const SDValue & W : Words [ IdxW ] ) { Vec = DAG . getNode ( <STR_LIT> , dl , ByteTy , Vec , S4 ) ; Vec = DAG . getNode ( <STR_LIT> , dl , ByteTy , Vec , W ) ; }


<s> if ( ! ZeroExt ) return DAG . getNode ( <STR_LIT> , dl , ResTy , VecV ) ; assert ( ty ( VecV ) . getVectorNumElements ( ) == ResTy . getVectorNumElements ( ) ) ; SDValue True = DAG . getNode ( <STR_LIT> , dl , ResTy , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue False = getZero ( dl , ResTy , DAG ) ; return DAG . getSelect ( dl , ResTy , VecV , True , False ) ;


<s> for ( const SDValue & Op : Ops ) IntOps . push_back ( Op ) ;

return DAG . getNode ( <STR_LIT> , dl , ResTy , IntOps ) ;


<s> SmallVector < SDValue , <NUM_LIT> > IntOps ; IntOps . push_back ( DAG . getConstant ( IntId , dl , <STR_LIT> ) ) ; for ( const SDValue & Op : Ops ) IntOps . push_back ( Op ) ;


<s> setOperationAction ( Opc , FromTy , Promote ) ; AddPromotedToType ( Opc , FromTy , ToTy ) ; } ; setOperationAction ( <STR_LIT> , ByteV , Legal ) ; setOperationAction ( <STR_LIT> , ByteW , Legal ) ; for ( MVT T : LegalV ) { setIndexedLoadAction ( <STR_LIT> , T , Legal ) ; setIndexedStoreAction ( <STR_LIT> , T , Legal ) ; setOperationAction ( <STR_LIT> , T , Legal ) ; setOperationAction ( <STR_LIT> , T , Legal ) ; setOperationAction ( <STR_LIT> , T , Legal ) ; setOperationAction ( <STR_LIT> , T , Legal ) ; setOperationAction ( <STR_LIT> , T , Legal ) ; setOperationAction ( <STR_LIT> , T , Legal ) ; setOperationAction ( <STR_LIT> , T , Legal ) ; if ( T != ByteV ) { setOperationAction ( <STR_LIT> , T , Legal ) ; setOperationAction ( <STR_LIT> , T , Legal ) ; setOperationAction ( <STR_LIT> , T , Legal ) ; } setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; if ( T != ByteV ) { setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setPromoteTo ( <STR_LIT> , T , ByteV ) ; } setCondCodeAction ( <STR_LIT> , T , Expand ) ; setCondCodeAction ( <STR_LIT> , T , Expand ) ; setCondCodeAction ( <STR_LIT> , T , Expand ) ; setCondCodeAction ( <STR_LIT> , T , Expand ) ; setCondCodeAction ( <STR_LIT> , T , Expand ) ; setCondCodeAction ( <STR_LIT> , T , Expand ) ; setCondCodeAction ( <STR_LIT> , T , Expand ) ; } for ( MVT T : LegalW ) { setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ; setOperationAction ( <STR_LIT> , T , Custom ) ;


<s> MVT ByteTy = <STR_LIT> ( <STR_LIT> , HwLen ) ; SDValue ByteVec = DAG . getNode ( <STR_LIT> , dl , ByteTy , VecV ) ; SDValue ByteSub = createHvxPrefixPred ( SubV , dl , BitBytes , false , DAG ) ; SDValue ByteIdx ; auto * IdxN = dyn_cast < ConstantSDNode > ( IdxV . getNode ( ) ) ; if ( ! IdxN || ! IdxN -> isNullValue ( ) ) { ByteIdx = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , DAG . getConstant ( BitBytes , dl , <STR_LIT> ) ) ; ByteVec = DAG . getNode ( <STR_LIT> , dl , ByteTy , ByteVec , ByteIdx ) ; }

MVT BoolTy = <STR_LIT> ( <STR_LIT> , HwLen ) ;


<s> MVT VecTy = ty ( VecV ) ; MVT SubTy = ty ( SubV ) ; assert ( Subtarget . isHVXVectorType ( VecTy , true ) ) ; unsigned VecLen = VecTy . getVectorNumElements ( ) ; unsigned HwLen = Subtarget . getVectorLength ( ) ; assert ( HwLen % VecLen == <NUM_LIT> && <STR_LIT> ) ; unsigned Scale = VecLen / SubTy . getVectorNumElements ( ) ; unsigned BitBytes = HwLen / VecLen ; unsigned BlockLen = HwLen / Scale ; MVT ByteTy = <STR_LIT> ( <STR_LIT> , HwLen ) ; SDValue ByteVec = DAG . getNode ( <STR_LIT> , dl , ByteTy , VecV ) ; SDValue ByteSub = createHvxPrefixPred ( SubV , dl , BitBytes , false , DAG ) ; SDValue ByteIdx ; auto * IdxN = dyn_cast < ConstantSDNode > ( IdxV . getNode ( ) ) ; if ( ! IdxN || ! IdxN -> isNullValue ( ) ) {

ByteIdx = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , DAG . getConstant ( BitBytes , dl , <STR_LIT> ) ) ;


<s> bool <ISA_LIT>TargetLowering :: isHvxOperation ( SDValue Op ) const { return Subtarget . isHVXVectorType ( ty ( Op ) , true ) || llvm :: any_of ( Op . getNode ( ) -> ops ( ) , [ this ] ( SDValue V ) { return Subtarget . isHVXVectorType ( ty ( V ) , true ) ; } ) ;


<s> unsigned Size = Op . getNumOperands ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) Ops . push_back ( Op . getOperand ( i ) ) ; if ( VecTy . getVectorElementType ( ) == <STR_LIT> ) return buildHvxVectorPred ( Ops , dl , VecTy , DAG ) ;

if ( VecTy . getSizeInBits ( ) == <NUM_LIT> * Subtarget . getVectorLength ( ) ) {


<s> unsigned Size = Op . getNumOperands ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) Ops . push_back ( Op . getOperand ( i ) ) ; if ( VecTy . getVectorElementType ( ) == <STR_LIT> ) return buildHvxVectorPred ( Ops , dl , VecTy , DAG ) ; if ( VecTy . getSizeInBits ( ) == <NUM_LIT> * Subtarget . getVectorLength ( ) ) { ArrayRef < SDValue > A ( Ops ) ; MVT SingleTy = typeSplit ( VecTy ) . first ; SDValue V0 = buildHvxVectorReg ( A . take_front ( Size / <NUM_LIT> ) , dl , SingleTy , DAG ) ;

SDValue V1 = buildHvxVectorReg ( A . drop_front ( Size / <NUM_LIT> ) , dl , SingleTy , DAG ) ;


<s> assert ( VecTy . getVectorElementType ( ) == <STR_LIT> ) ; unsigned HwLen = Subtarget . getVectorLength ( ) ; assert ( isPowerOf2_32 ( NumOp ) && HwLen % NumOp == <NUM_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Subtarget . isHVXVectorType ( ty ( Op0 ) , true ) ) { if ( NumOp == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VecTy , Op0 , Op . getOperand ( <NUM_LIT> ) ) ; ArrayRef < SDUse > U ( Op . getNode ( ) -> ops ( ) ) ; SmallVector < SDValue , <NUM_LIT> > SV ( U . begin ( ) , U . end ( ) ) ; ArrayRef < SDValue > Ops ( SV ) ; MVT HalfTy = typeSplit ( VecTy ) . first ; SDValue V0 = DAG . getNode ( <STR_LIT> , dl , HalfTy , Ops . take_front ( NumOp / <NUM_LIT> ) ) ; SDValue V1 = DAG . getNode ( <STR_LIT> , dl , HalfTy , Ops . take_back ( NumOp / <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , V0 , V1 ) ; } unsigned BitBytes = HwLen / VecTy . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > Prefixes ; for ( SDValue V : Op . getNode ( ) -> op_values ( ) ) { SDValue P = createHvxPrefixPred ( V , dl , BitBytes , true , DAG ) ; Prefixes . push_back ( P ) ; } unsigned InpLen = ty ( Op . getOperand ( <NUM_LIT> ) ) . getVectorNumElements ( ) ; MVT ByteTy = <STR_LIT> ( <STR_LIT> , HwLen ) ; SDValue S = DAG . getConstant ( InpLen * BitBytes , dl , <STR_LIT> ) ; SDValue Res = getZero ( dl , ByteTy , DAG ) ; for ( unsigned i = <NUM_LIT> , e = Prefixes . size ( ) ; i != e ; ++ i ) { Res = DAG . getNode ( <STR_LIT> , dl , ByteTy , Res , S ) ; Res = DAG . getNode ( <STR_LIT> , dl , ByteTy , Res , Prefixes [ e - i - <NUM_LIT> ] ) ; }

return DAG . getNode ( <STR_LIT> , dl , VecTy , Res ) ;


<s> assert ( isPowerOf2_32 ( ElemWidth ) && ElemWidth <= <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> / ElemWidth ; ++ i ) { Splat1 = ( Splat1 << ElemWidth ) | <NUM_LIT> ; SplatW = ( SplatW << ElemWidth ) | ElemWidth ; } SDValue Vec1 = DAG . getNode ( <STR_LIT> , dl , ResTy , DAG . getConstant ( uint32_t ( Splat1 ) , dl , <STR_LIT> ) ) ; SDValue VecW = DAG . getNode ( <STR_LIT> , dl , ResTy , DAG . getConstant ( uint32_t ( SplatW ) , dl , <STR_LIT> ) ) ; SDValue VecN1 = DAG . getNode ( <STR_LIT> , dl , ResTy , DAG . getConstant ( - <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue A = DAG . getNode ( <STR_LIT> , dl , ResTy , { DAG . getNode ( <STR_LIT> , dl , ResTy , { InpV , VecN1 } ) , DAG . getNode ( <STR_LIT> , dl , ResTy , { InpV , Vec1 } ) } ) ;

return DAG . getNode ( <STR_LIT> , dl , ResTy , { VecW , DAG . getNode ( <STR_LIT> , dl , ResTy , A ) } ) ;


<s> SDValue IdxV = Op . getOperand ( <NUM_LIT> ) ; MVT ElemTy = ty ( VecV ) . getVectorElementType ( ) ; if ( ElemTy == <STR_LIT> ) return insertHvxElementPred ( VecV , IdxV , ValV , dl , DAG ) ;

return insertHvxElementReg ( VecV , IdxV , ValV , dl , DAG ) ;


<s> const SDLoc & dl ( Op ) ; SDValue VecV = Op . getOperand ( <NUM_LIT> ) ; SDValue ValV = Op . getOperand ( <NUM_LIT> ) ;

SDValue IdxV = Op . getOperand ( <NUM_LIT> ) ;


<s> unsigned VecLen = ResTy . getVectorNumElements ( ) ; SDValue Vs = Op . getOperand ( <NUM_LIT> ) ; SDValue Vt = Op . getOperand ( <NUM_LIT> ) ; switch ( ElemTy . SimpleTy ) { case <STR_LIT> : { MVT ExtTy = typeExtElem ( ResTy , <NUM_LIT> ) ; unsigned MpyOpc = ElemTy == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue M = getInstr ( MpyOpc , dl , ExtTy , { Vs , Vt } , DAG ) ; for ( unsigned I = <NUM_LIT> ; I < VecLen ; I += <NUM_LIT> ) { ShuffMask . push_back ( I ) ; ShuffMask . push_back ( I + VecLen ) ; } VectorPair P = opSplit ( opCastElem ( M , ElemTy , DAG ) , dl , DAG ) ; SDValue BS = getByteShuffle ( dl , P . first , P . second , ShuffMask , DAG ) ; return DAG . getBitcast ( ResTy , BS ) ; } case <STR_LIT> : return getInstr ( <STR_LIT> , dl , ResTy , { Vs , Vt } , DAG ) ; case <STR_LIT> : { SDValue S16 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ;

SDValue T0 = getInstr ( <STR_LIT> , dl , ResTy , { Vs , Vt } , DAG ) ;


<s> } assert ( ElemTy == <STR_LIT> ) ; SDValue S16 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; if ( IsSigned ) { SDValue T0 = getInstr ( <STR_LIT> , dl , ResTy , { Vt , Vs } , DAG ) ; SDValue S0 = getInstr ( <STR_LIT> , dl , ResTy , { Vs , S16 } , DAG ) ; SDValue T1 = getInstr ( <STR_LIT> , dl , ResTy , { T0 , S0 , Vt } , DAG ) ; SDValue S2 = getInstr ( <STR_LIT> , dl , ResTy , { T1 , S16 } , DAG ) ; SDValue T2 = getInstr ( <STR_LIT> , dl , ResTy , { S0 , Vt } , DAG ) ; SDValue T3 = DAG . getNode ( <STR_LIT> , dl , ResTy , { S2 , T2 } ) ; return T3 ; } auto LoVec = [ & DAG , ResTy , dl ] ( SDValue Pair ) { return DAG . getTargetExtractSubreg ( <STR_LIT> , dl , ResTy , Pair ) ; } ; auto HiVec = [ & DAG , ResTy , dl ] ( SDValue Pair ) { return DAG . getTargetExtractSubreg ( <STR_LIT> , dl , ResTy , Pair ) ; } ; MVT PairTy = typeJoin ( { ResTy , ResTy } ) ; SDValue P = getInstr ( <STR_LIT> , dl , ResTy , { DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) } , DAG ) ; SDValue T0 = getInstr ( <STR_LIT> , dl , PairTy , { Vs , Vt } , DAG ) ; SDValue T1 = getInstr ( <STR_LIT> , dl , ResTy , { LoVec ( T0 ) , S16 } , DAG ) ; SDValue D0 = getInstr ( <STR_LIT> , dl , ResTy , { Vt , P } , DAG ) ; SDValue T2 = getInstr ( <STR_LIT> , dl , PairTy , { Vs , D0 } , DAG ) ; SDValue T3 = getInstr ( <STR_LIT> , dl , PairTy , { LoVec ( T2 ) , HiVec ( T2 ) } , DAG ) ; SDValue T4 = DAG . getNode ( <STR_LIT> , dl , ResTy , { T1 , LoVec ( T3 ) } ) ; SDValue T5 = getInstr ( <STR_LIT> , dl , ResTy , { T4 , S16 } , DAG ) ;

SDValue T6 = DAG . getNode ( <STR_LIT> , dl , ResTy , { HiVec ( T0 ) , HiVec ( T3 ) } ) ;


<s> SDValue S2 = getInstr ( <STR_LIT> , dl , ResTy , { T1 , S16 } , DAG ) ; SDValue T2 = getInstr ( <STR_LIT> , dl , ResTy , { S0 , Vt } , DAG ) ; SDValue T3 = DAG . getNode ( <STR_LIT> , dl , ResTy , { S2 , T2 } ) ; return T3 ; } auto LoVec = [ & DAG , ResTy , dl ] ( SDValue Pair ) { return DAG . getTargetExtractSubreg ( <STR_LIT> , dl , ResTy , Pair ) ; } ; auto HiVec = [ & DAG , ResTy , dl ] ( SDValue Pair ) { return DAG . getTargetExtractSubreg ( <STR_LIT> , dl , ResTy , Pair ) ; } ; MVT PairTy = typeJoin ( { ResTy , ResTy } ) ; SDValue P = getInstr ( <STR_LIT> , dl , ResTy , { DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) } , DAG ) ; SDValue T0 = getInstr ( <STR_LIT> , dl , PairTy , { Vs , Vt } , DAG ) ; SDValue T1 = getInstr ( <STR_LIT> , dl , ResTy , { LoVec ( T0 ) , S16 } , DAG ) ; SDValue D0 = getInstr ( <STR_LIT> , dl , ResTy , { Vt , P } , DAG ) ; SDValue T2 = getInstr ( <STR_LIT> , dl , PairTy , { Vs , D0 } , DAG ) ; SDValue T3 = getInstr ( <STR_LIT> , dl , PairTy , { LoVec ( T2 ) , HiVec ( T2 ) } , DAG ) ; SDValue T4 = DAG . getNode ( <STR_LIT> , dl , ResTy , { T1 , LoVec ( T3 ) } ) ; SDValue T5 = getInstr ( <STR_LIT> , dl , ResTy , { T4 , S16 } , DAG ) ; SDValue T6 = DAG . getNode ( <STR_LIT> , dl , ResTy , { HiVec ( T0 ) , HiVec ( T3 ) } ) ;

SDValue T7 = DAG . getNode ( <STR_LIT> , dl , ResTy , { T5 , T6 } ) ;


<s> unsigned Opc = Op . getOpcode ( ) ; bool IsPairOp = isHvxPairTy ( ty ( Op ) ) || llvm :: any_of ( Op . getNode ( ) -> ops ( ) , [ this ] ( SDValue V ) { return isHvxPairTy ( ty ( V ) ) ; } ) ; if ( IsPairOp ) { switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : return SplitHvxMemOp ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SplitHvxPairOp ( Op , DAG ) ; } } switch ( Opc ) { default : break ; case <STR_LIT> : return LowerHvxBuildVector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxConcatVectors ( Op , DAG ) ; case <STR_LIT> : return LowerHvxInsertSubvector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxInsertElement ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtractSubvector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtractElement ( Op , DAG ) ; case <STR_LIT> : return LowerHvxAnyExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxSignExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxZeroExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxCttz ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerHvxShift ( Op , DAG ) ; case <STR_LIT> : return LowerHvxMul ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerHvxMulh ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtend ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return Op ; case <STR_LIT> : return SDValue ( ) ; } Op . dumpr ( & DAG ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SplitHvxPairOp ( Op , DAG ) ; } } switch ( Opc ) { default : break ; case <STR_LIT> : return LowerHvxBuildVector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxConcatVectors ( Op , DAG ) ; case <STR_LIT> : return LowerHvxInsertSubvector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxInsertElement ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtractSubvector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtractElement ( Op , DAG ) ; case <STR_LIT> : return LowerHvxAnyExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxSignExt ( Op , DAG ) ;

case <STR_LIT> : return LowerHvxZeroExt ( Op , DAG ) ;


<s> MOp1 = MF . getMachineMemOperand ( MMO , HwLen , HwLen ) ; } unsigned MemOpc = BN -> getOpcode ( ) ; SDValue NewOp ; if ( MemOpc == <STR_LIT> ) { SDValue Load0 = DAG . getLoad ( SingleTy , dl , Chain , Base0 , MOp0 ) ; SDValue Load1 = DAG . getLoad ( SingleTy , dl , Chain , Base1 , MOp1 ) ; NewOp = DAG . getMergeValues ( { DAG . getNode ( <STR_LIT> , dl , MemTy , Load0 , Load1 ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load0 . getValue ( <NUM_LIT> ) , Load1 . getValue ( <NUM_LIT> ) ) } , dl ) ; } else {


<s> LSBaseSDNode * BN = cast < LSBaseSDNode > ( Op . getNode ( ) ) ; assert ( BN -> isUnindexed ( ) ) ; MVT MemTy = BN -> getMemoryVT ( ) . getSimpleVT ( ) ; if ( ! isHvxPairTy ( MemTy ) ) return Op ; const SDLoc & dl ( Op ) ; unsigned HwLen = Subtarget . getVectorLength ( ) ; MVT SingleTy = typeSplit ( MemTy ) . first ; SDValue Chain = BN -> getChain ( ) ; SDValue Base0 = BN -> getBasePtr ( ) ; SDValue Base1 = DAG . getMemBasePlusOffset ( Base0 , HwLen , dl ) ; MachineMemOperand * MOp0 = nullptr , * MOp1 = nullptr ; if ( MachineMemOperand * MMO = BN -> getMemOperand ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ;

MOp0 = MF . getMachineMemOperand ( MMO , <NUM_LIT> , HwLen ) ;


<s> if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { ofst = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , ofst , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { ofst = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , ofst , LocVT , LocInfo ) ) ; return false ;


<s> SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , dl , <STR_LIT> ) ;

return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getByValAlign ( ) , false , false , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> if ( VT . getSimpleVT ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Val ) ; if ( VT . getSimpleVT ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Val ) ;


<s> if ( VT . getSimpleVT ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Val ) ;


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : {

MachineFunction * MF = BB -> getParent ( ) ;


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : { MachineFunction * MF = BB -> getParent ( ) ; auto * FuncInfo = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; FuncInfo -> addAllocaAdjustInst ( MI ) ; return BB ; }

default : llvm_unreachable ( <STR_LIT> ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDValue BA_SD = DAG . getTargetBlockAddress ( BA , <STR_LIT> ) ; SDLoc dl ( Op ) ;

return DAG . getNode ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) ) , BA_SD ) ;


<s> LowerBR_JT ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Table = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Table ) ; unsigned JTI = JT -> getIndex ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const MachineJumpTableInfo * MJTI = MF . getJumpTableInfo ( ) ; SDValue TargetJT = DAG . getTargetJumpTable ( JT -> getIndex ( ) , <STR_LIT> ) ;

const std :: vector < MachineJumpTableEntry > & JTE = MJTI -> getJumpTables ( ) ;


<s> unsigned SplatBits = APSplatBits . getZExtValue ( ) ; int32_t SextVal = ( ( int32_t ) ( SplatBits << ( <NUM_LIT> - SplatBitSize ) ) >> ( <NUM_LIT> - SplatBitSize ) ) ; return createSplat ( DAG , dl , VT , DAG . getConstant ( SextVal , dl , <STR_LIT> ) ) ; } if ( VT . getSimpleVT ( ) == <STR_LIT> ) { SDValue V0 = BVN -> getOperand ( <NUM_LIT> ) ; SDValue V1 = BVN -> getOperand ( <NUM_LIT> ) ; if ( V0 . getOpcode ( ) == <STR_LIT> ) V0 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; if ( V1 . getOpcode ( ) == <STR_LIT> ) V1 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; ConstantSDNode * C0 = dyn_cast < ConstantSDNode > ( V0 ) ; ConstantSDNode * C1 = dyn_cast < ConstantSDNode > ( V1 ) ; if ( ! C0 || ! C1 ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V0 ) ; if ( isInt < <NUM_LIT> > ( C0 -> getSExtValue ( ) ) || isInt < <NUM_LIT> > ( C1 -> getSExtValue ( ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V0 ) ; } if ( VT . getSimpleVT ( ) == <STR_LIT> ) { for ( unsigned i = <NUM_LIT> , e = NElts ; i != e ; ++ i ) { if ( BVN -> getOperand ( i ) . getOpcode ( ) == <STR_LIT> ) continue ; ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( i ) ) ; if ( ! Cst ) { SDValue pack = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BVN -> getOperand ( <NUM_LIT> ) , BVN -> getOperand ( <NUM_LIT> ) ) ; return DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , pack ) ; } } } uint64_t Res = <NUM_LIT> ; unsigned EltSize = Size / NElts ;


<s> ConstantSDNode * S = dyn_cast < ConstantSDNode > ( Shifted ) ; if ( ( VecVT . getSimpleVT ( ) == <STR_LIT> ) && ( NElts == <NUM_LIT> ) && W && S ) { if ( ( W -> getZExtValue ( ) == <NUM_LIT> ) && ( ( S -> getZExtValue ( ) >> <NUM_LIT> ) == <NUM_LIT> ) ) { SDValue Vec0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Combined = DAG . getNode ( <STR_LIT> , dl , VT , Vec0 , Vec ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Combined ) ; } } if ( ( VecVT . getSimpleVT ( ) == <STR_LIT> ) && ( NElts == <NUM_LIT> ) && W && S ) { if ( ( W -> getZExtValue ( ) == <NUM_LIT> ) && ( ( S -> getZExtValue ( ) >> <NUM_LIT> ) == <NUM_LIT> ) ) { SDValue Vec0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Combined = DAG . getNode ( <STR_LIT> , dl , VT , Vec0 , Vec ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Combined ) ; } } for ( unsigned i = <NUM_LIT> , e = NElts ; i != e ; ++ i ) { unsigned OpIdx = NElts - i - <NUM_LIT> ; SDValue Operand = Op . getOperand ( OpIdx ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && Operand . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> ) { SDValue C = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; Operand = DAG . getNode ( <STR_LIT> , dl , VT , C , Operand ) ; } SDValue Idx = DAG . getConstant ( OpIdx , dl , <STR_LIT> ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Idx , Width ) ; SDValue Combined = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Shifted , Offset ) ; const SDValue Ops [ ] = { ConstVal , Operand , Combined } ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) ConstVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; else ConstVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } return DAG . getNode ( <STR_LIT> , dl , VT , ConstVal ) ;


<s> EVT VecVT = Vec . getValueType ( ) ; SDValue Width = DAG . getConstant ( VecVT . getSizeInBits ( ) , dl , <STR_LIT> ) ; SDValue Shifted = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Width , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue ConstVal = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; ConstantSDNode * W = dyn_cast < ConstantSDNode > ( Width ) ; ConstantSDNode * S = dyn_cast < ConstantSDNode > ( Shifted ) ; if ( ( VecVT . getSimpleVT ( ) == <STR_LIT> ) && ( NElts == <NUM_LIT> ) && W && S ) { if ( ( W -> getZExtValue ( ) == <NUM_LIT> ) && ( ( S -> getZExtValue ( ) >> <NUM_LIT> ) == <NUM_LIT> ) ) { SDValue Vec0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Combined = DAG . getNode ( <STR_LIT> , dl , VT , Vec0 , Vec ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , Combined ) ;


<s> SDValue Res ; if ( CP -> isMachineConstantPoolEntry ( ) ) Res = DAG . getTargetConstantPool ( CP -> getMachineCPVal ( ) , ValTy , CP -> getAlignment ( ) ) ; else Res = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , ValTy , CP -> getAlignment ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , ValTy , Res ) ;


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; SDValue Align = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; ConstantSDNode * AlignConst = dyn_cast < ConstantSDNode > ( Align ) ; assert ( AlignConst && <STR_LIT> ) ; unsigned A = AlignConst -> getSExtValue ( ) ; auto & HFI = * Subtarget . getFrameLowering ( ) ; if ( A == <NUM_LIT> ) A = HFI . getStackAlignment ( ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; auto & FuncInfo = * MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; <STR_LIT> Flags = Ins [ i ] . Flags ; unsigned ObjSize ; unsigned StackLocation ; int FI ; if ( ( VA . isRegLoc ( ) && ! Flags . isByVal ( ) ) || ( VA . isRegLoc ( ) && Flags . isByVal ( ) && Flags . getByValSize ( ) > <NUM_LIT> ) ) { EVT RegVT = VA . getLocVT ( ) ; if ( RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> ) { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else if ( RegVT == <STR_LIT> || RegVT == <STR_LIT> ) { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else { assert ( <NUM_LIT> ) ; } } else if ( VA . isRegLoc ( ) && Flags . isByVal ( ) && Flags . getByValSize ( ) <= <NUM_LIT> ) { assert ( <NUM_LIT> && <STR_LIT> ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( Flags . isByVal ( ) ) { ObjSize = Flags . getByValSize ( ) ; } else { ObjSize = VA . getLocVT ( ) . getStoreSizeInBits ( ) >> <NUM_LIT> ; }

StackLocation = HEXAGON_LRFP_SIZE + VA . getLocMemOffset ( ) ;


<s> default : Op . getNode ( ) -> dumpr ( & DAG ) ; if ( Opc > <STR_LIT> && Opc < <STR_LIT> ) errs ( ) << <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVECTOR_SHIFT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerCTPOP ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINLINEASM ( Op , DAG ) ; }


<s> EVT VT = Op . getValueType ( ) ; if ( V2 . getOpcode ( ) == <STR_LIT> ) V2 = V1 ; if ( SVN -> isSplat ( ) ) { int Lane = SVN -> getSplatIndex ( ) ; if ( Lane == - <NUM_LIT> ) Lane = <NUM_LIT> ; if ( Lane == <NUM_LIT> && V1 . getOpcode ( ) == <STR_LIT> ) return createSplat ( DAG , dl , VT , V1 . getOperand ( <NUM_LIT> ) ) ; if ( Lane == <NUM_LIT> && V1 . getOpcode ( ) == <STR_LIT> && ! isa < ConstantSDNode > ( V1 . getOperand ( <NUM_LIT> ) ) ) { bool IsScalarToVector = true ; for ( unsigned i = <NUM_LIT> , e = V1 . getNumOperands ( ) ; i != e ; ++ i ) if ( V1 . getOperand ( i ) . getOpcode ( ) != <STR_LIT> ) { IsScalarToVector = false ; break ;


<s> static SDValue LowerVECTOR_SHUFFLE ( SDValue Op , SelectionDAG & DAG ) { const ShuffleVectorSDNode * SVN = cast < ShuffleVectorSDNode > ( Op ) ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( V2 . getOpcode ( ) == <STR_LIT> ) V2 = V1 ; if ( SVN -> isSplat ( ) ) { int Lane = SVN -> getSplatIndex ( ) ; if ( Lane == - <NUM_LIT> ) Lane = <NUM_LIT> ; if ( Lane == <NUM_LIT> && V1 . getOpcode ( ) == <STR_LIT> ) return createSplat ( DAG , dl , VT , V1 . getOperand ( <NUM_LIT> ) ) ; if ( Lane == <NUM_LIT> && V1 . getOpcode ( ) == <STR_LIT> && ! isa < ConstantSDNode > ( V1 . getOperand ( <NUM_LIT> ) ) ) { bool IsScalarToVector = true ; for ( unsigned i = <NUM_LIT> , e = V1 . getNumOperands ( ) ; i != e ; ++ i ) if ( V1 . getOperand ( i ) . getOpcode ( ) != <STR_LIT> ) { IsScalarToVector = false ; break ; }

if ( IsScalarToVector ) return createSplat ( DAG , dl , VT , V1 . getOperand ( <NUM_LIT> ) ) ;


<s> setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Promote ) ;

AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedLdStVT . getSimpleVT ( ) ) ;


<s> ValVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; LocInfo = CCValAssign :: BCvt ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; LocInfo = CCValAssign :: BCvt ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! RetCC_<ISA_LIT>32 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! RetCC_<ISA_LIT>64 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ;


<s> LocVT = <STR_LIT> ; LocInfo = CCValAssign :: BCvt ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! RetCC_<ISA_LIT>32 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! RetCC_<ISA_LIT>64 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } return true ;


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const {

return LI -> getType ( ) -> getPrimitiveSizeInBits ( ) > <NUM_LIT> ? AtomicExpansionKind :: LLSC : AtomicExpansionKind :: None ;


<s> return LI -> getType ( ) -> getPrimitiveSizeInBits ( ) > <NUM_LIT> ? AtomicExpansionKind :: LLSC : AtomicExpansionKind :: None ;


<s> for ( com_sym = symbol_list . localBegin ( ) ; com_sym != com_end ; ++ com_sym ) { if ( ResolveInfo :: Common == ( * com_sym ) -> desc ( ) ) { ( * com_sym ) -> resolveInfo ( ) -> setDesc ( ResolveInfo :: Define ) ; Fragment * frag = new FillFragment ( <NUM_LIT> , <NUM_LIT> , ( * com_sym ) -> size ( ) ) ; switch ( ( * com_sym ) -> size ( ) ) { case <NUM_LIT> : if ( maxGPSize <= <NUM_LIT> ) break ; ObjectBuilder :: AppendFragment ( * frag , * ( m_pscommon_1 -> getSectionData ( ) ) , ( * com_sym ) -> value ( ) ) ; ( * com_sym ) -> setFragmentRef ( FragmentRef :: Create ( * frag , <NUM_LIT> ) ) ; continue ; case <NUM_LIT> : if ( maxGPSize <= <NUM_LIT> ) break ; ObjectBuilder :: AppendFragment ( * frag , * ( m_pscommon_2 -> getSectionData ( ) ) , ( * com_sym ) -> value ( ) ) ; ( * com_sym ) -> setFragmentRef ( FragmentRef :: Create ( * frag , <NUM_LIT> ) ) ; continue ; case <NUM_LIT> : if ( maxGPSize <= <NUM_LIT> ) break ; ObjectBuilder :: AppendFragment ( * frag , * ( m_pscommon_4 -> getSectionData ( ) ) , ( * com_sym ) -> value ( ) ) ; ( * com_sym ) -> setFragmentRef ( FragmentRef :: Create ( * frag , <NUM_LIT> ) ) ; continue ; case <NUM_LIT> : if ( maxGPSize <= <NUM_LIT> ) break ; ObjectBuilder :: AppendFragment ( * frag , * ( m_pscommon_8 -> getSectionData ( ) ) , ( * com_sym ) -> value ( ) ) ; ( * com_sym ) -> setFragmentRef ( FragmentRef :: Create ( * frag , <NUM_LIT> ) ) ; continue ; default : break ;


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; }

return new <ISA_LIT>LDBackend ( pConfig , new <ISA_LIT>GNUInfo ( pConfig . targets ( ) ) ) ;


<s> if ( pConfig . targets ( ) . triple ( ) . isOSDarwin ( ) ) { assert ( <NUM_LIT> && <STR_LIT> ) ; } if ( pConfig . targets ( ) . triple ( ) . isOSWindows ( ) ) { assert ( <NUM_LIT> && <STR_LIT> ) ; } return new <ISA_LIT>LDBackend ( pConfig , new <ISA_LIT>GNUInfo ( pConfig . targets ( ) ) ) ;


m_pGOTSymbol = pBuilder . AddSymbol < IRBuilder :: Force , IRBuilder :: Resolve > ( <STR_LIT> , ResolveInfo :: Object , ResolveInfo :: Define , ResolveInfo :: Local , <NUM_LIT> , <NUM_LIT> , FragmentRef :: Create ( pFrag , <NUM_LIT> ) , ResolveInfo :: Hidden ) ;


<s> void <ISA_LIT>LDBackend :: defineGOTSymbol ( IRBuilder & pBuilder , Fragment & pFrag ) { if ( m_pGOTSymbol != NULL ) { pBuilder . AddSymbol < IRBuilder :: Force , IRBuilder :: Unresolve > ( <STR_LIT> , ResolveInfo :: Object , ResolveInfo :: Define , ResolveInfo :: Local , <NUM_LIT> , <NUM_LIT> , FragmentRef :: Create ( pFrag , <NUM_LIT> ) , ResolveInfo :: Hidden ) ; } else { m_pGOTSymbol = pBuilder . AddSymbol < IRBuilder :: Force , IRBuilder :: Resolve > ( <STR_LIT> , ResolveInfo :: Object , ResolveInfo :: Define , ResolveInfo :: Local , <NUM_LIT> , <NUM_LIT> , FragmentRef :: Create ( pFrag , <NUM_LIT> ) , ResolveInfo :: Hidden ) ;


<s> void <ISA_LIT>LDBackend :: doCreateProgramHdrs ( Module & pModule ) {


<s> void <ISA_LIT>LDBackend :: doPostLayout ( Module & pModule , IRBuilder & pBuilder ) {


<s> setGOTSectionSize ( pBuilder ) ; if ( m_pPLT -> hasPLT1 ( ) ) m_pPLT -> finalizeSectionSize ( ) ; if ( ! m_pRelaDyn -> empty ( ) ) { assert ( ! config ( ) . isCodeStatic ( ) && <STR_LIT> ) ; setRelaDynSize ( ) ; }


<s> if ( m_pPLT -> hasPLT1 ( ) ) m_pPLT -> finalizeSectionSize ( ) ; if ( ! m_pRelaDyn -> empty ( ) ) { assert ( ! config ( ) . isCodeStatic ( ) && <STR_LIT> ) ; setRelaDynSize ( ) ; } if ( ! m_pRelaPLT -> empty ( ) ) {


<s> } } } } std :: vector < Fragment * > invalid_frags ; pFinished = true ; for ( BranchIslandFactory :: iterator island = getBRIslandFactory ( ) -> begin ( ) , island_end = getBRIslandFactory ( ) -> end ( ) ; island != island_end ; ++ island ) { if ( ( * island ) . size ( ) > stubGroupSize ( ) ) { error ( diag :: err_no_space_to_place_stubs ) << stubGroupSize ( ) ; return false ; } if ( ( * island ) . numOfStubs ( ) == <NUM_LIT> ) { continue ; } Fragment * exit = & * ( * island ) . end ( ) ; if ( exit == & * ( * island ) . begin ( ) -> getParent ( ) -> end ( ) ) { continue ; } if ( ( ( * island ) . offset ( ) + ( * island ) . size ( ) ) > exit -> getOffset ( ) ) { if ( invalid_frags . empty ( ) || ( invalid_frags . back ( ) -> getParent ( ) != ( * island ) . getParent ( ) ) ) { invalid_frags . push_back ( exit ) ; pFinished = false ; } continue ; } } for ( auto it = invalid_frags . begin ( ) , ie = invalid_frags . end ( ) ; it != ie ; ++ it ) { Fragment * invalid = * it ; while ( invalid != NULL ) { invalid -> setOffset ( invalid -> getPrevNode ( ) -> getOffset ( ) + invalid -> getPrevNode ( ) -> size ( ) ) ; invalid = invalid -> getNextNode ( ) ; } } if ( isRelaxed ) { SectionData * prev = NULL ; for ( BranchIslandFactory :: iterator island = getBRIslandFactory ( ) -> begin ( ) , island_end = getBRIslandFactory ( ) -> end ( ) ; island != island_end ; ++ island ) { SectionData * sd = ( * island ) . begin ( ) -> getParent ( ) ;

if ( ( * island ) . numOfStubs ( ) != <NUM_LIT> ) {


<s> } } break ; default : break ; } } } } std :: vector < Fragment * > invalid_frags ; pFinished = true ; for ( BranchIslandFactory :: iterator island = getBRIslandFactory ( ) -> begin ( ) , island_end = getBRIslandFactory ( ) -> end ( ) ; island != island_end ; ++ island ) { if ( ( * island ) . size ( ) > stubGroupSize ( ) ) { error ( diag :: err_no_space_to_place_stubs ) << stubGroupSize ( ) ; return false ; } if ( ( * island ) . numOfStubs ( ) == <NUM_LIT> ) { continue ; } Fragment * exit = & * ( * island ) . end ( ) ; if ( exit == & * ( * island ) . begin ( ) -> getParent ( ) -> end ( ) ) { continue ; } if ( ( ( * island ) . offset ( ) + ( * island ) . size ( ) ) > exit -> getOffset ( ) ) { if ( invalid_frags . empty ( ) || ( invalid_frags . back ( ) -> getParent ( ) != ( * island ) . getParent ( ) ) ) { invalid_frags . push_back ( exit ) ; pFinished = false ; } continue ; } } for ( auto it = invalid_frags . begin ( ) , ie = invalid_frags . end ( ) ; it != ie ; ++ it ) { Fragment * invalid = * it ; while ( invalid != NULL ) { invalid -> setOffset ( invalid -> getPrevNode ( ) -> getOffset ( ) + invalid -> getPrevNode ( ) -> size ( ) ) ; invalid = invalid -> getNextNode ( ) ; }


<s> const <ISA_LIT>ELFDynamic & <ISA_LIT>LDBackend :: dynamic ( ) const { assert ( m_pDynamic != NULL ) ;


<s> uint64_t RegionSize = <NUM_LIT> ; for ( <ISA_LIT>GOTPLT :: iterator it = m_pGOTPLT -> begin ( ) , ie = m_pGOTPLT -> end ( ) ; it != ie ; ++ it , ++ buffer ) { got = & ( llvm :: cast < <ISA_LIT>GOTEntry > ( ( * it ) ) ) ; * buffer = static_cast < uint32_t > ( got -> getValue ( ) ) ; RegionSize += EntrySize ; }


<s> uint32_t * buffer = reinterpret_cast < uint32_t * > ( pRegion . begin ( ) ) ; <ISA_LIT>GOTEntry * got = <NUM_LIT> ; unsigned int EntrySize = <STR_LIT> ; uint64_t RegionSize = <NUM_LIT> ;

for ( <ISA_LIT>GOTPLT :: iterator it = m_pGOTPLT -> begin ( ) , ie = m_pGOTPLT -> end ( ) ;


<s> assert ( m_pGOT && <STR_LIT> ) ; uint32_t * buffer = reinterpret_cast < uint32_t * > ( pRegion . begin ( ) ) ; <ISA_LIT>GOTEntry * got = <NUM_LIT> ; unsigned int EntrySize = <STR_LIT> ; uint64_t RegionSize = <NUM_LIT> ; for ( <STR_LIT> it = m_pGOT -> begin ( ) , ie = m_pGOT -> end ( ) ; it != ie ; ++ it , ++ buffer ) { got = & ( llvm :: cast < <ISA_LIT>GOTEntry > ( ( * it ) ) ) ; * buffer = static_cast < uint32_t > ( got -> getValue ( ) ) ; RegionSize += EntrySize ; } return RegionSize ;


<s> bool <ISA_LIT>LDBackend :: finalizeTargetSymbols ( ) { if ( config ( ) . codeGenType ( ) == LinkerConfig :: Object ) return true ; if ( m_psdabase ) m_psdabase -> setValue ( m_psdata -> addr ( ) ) ; ELFSegmentFactory :: const_iterator edata = elfSegmentTable ( ) . find ( llvm :: ELF :: PT_LOAD , llvm :: ELF :: PF_W , llvm :: ELF :: PF_X ) ; if ( elfSegmentTable ( ) . end ( ) != edata ) { if ( f_pEData != NULL && ResolveInfo :: ThreadLocal != f_pEData -> type ( ) ) { f_pEData -> setValue ( ( * edata ) -> vaddr ( ) + ( * edata ) -> filesz ( ) ) ; } if ( f_p_EData != NULL && ResolveInfo :: ThreadLocal != f_p_EData -> type ( ) ) {

f_p_EData -> setValue ( ( * edata ) -> vaddr ( ) + ( * edata ) -> filesz ( ) ) ;


<s> Relocation :: Type getCopyRelType ( ) const {


<s> assert ( m_pGOT != NULL ) ; return * m_pGOT ;


<s> const <ISA_LIT>GOTPLT & <ISA_LIT>LDBackend :: getGOTPLT ( ) const { assert ( m_pGOTPLT != NULL ) ; return * m_pGOTPLT ;


<s> uint32_t getGP ( ) { return m_psdata -> addr ( ) ;


<s> const <ISA_LIT>PLT & <ISA_LIT>LDBackend :: getPLT ( ) const { assert ( m_pPLT != NULL && <STR_LIT> ) ;


<s> const OutputRelocSection & <ISA_LIT>LDBackend :: getRelaDyn ( ) const { assert ( m_pRelaDyn != NULL && <STR_LIT> ) ;


<s> size_t getRelEntrySize ( ) { return <NUM_LIT> ;


<s> ResolveInfo :: Desc getSymDesc ( uint16_t shndx ) const {

if ( shndx >= llvm :: ELF :: SHN_HEXAGON_SCOMMON && shndx <= llvm :: ELF :: SHN_HEXAGON_SCOMMON_8 ) return ResolveInfo :: Common ;


<s> <ISA_LIT>LDBackend :: <ISA_LIT>LDBackend ( const LinkerConfig & pConfig , <ISA_LIT>GNUInfo * pInfo ) : GNULDBackend ( pConfig , pInfo ) , m_pRelocator ( NULL ) , m_pGOT ( NULL ) , m_pGOTPLT ( NULL ) , m_pPLT ( NULL ) , m_pRelaDyn ( NULL ) , m_pRelaPLT ( NULL ) , m_pDynamic ( NULL ) , m_pGOTSymbol ( NULL ) , m_CopyRel ( llvm :: ELF :: R_HEX_COPY ) {


<s> m_pBRIslandFactory = new BranchIslandFactory ( maxFwdBranchOffset ( ) , maxBwdBranchOffset ( ) , <NUM_LIT> ) ;


<s> bool <ISA_LIT>LDBackend :: initBRIslandFactory ( ) { if ( m_pBRIslandFactory == NULL ) {

m_pBRIslandFactory = new BranchIslandFactory ( maxFwdBranchOffset ( ) , maxBwdBranchOffset ( ) , <NUM_LIT> ) ;


<s> bool <ISA_LIT>LDBackend :: initRelocator ( ) {


<s> bool <ISA_LIT>LDBackend :: initStubFactory ( ) {


<s> m_pPLT = new <ISA_LIT>PLT ( plt , * m_pGOTPLT , config ( ) ) ; LDSection & relaplt = file_format -> getRelaPlt ( ) ; relaplt . setLink ( & plt ) ; m_pRelaPLT = new OutputRelocSection ( pModule , relaplt ) ; LDSection & reladyn = file_format -> getRelaDyn ( ) ; m_pRelaDyn = new OutputRelocSection ( pModule , reladyn ) ; } m_psdata = pBuilder . CreateSection ( <STR_LIT> , LDFileFormat :: Target , llvm :: ELF :: SHT_PROGBITS , llvm :: ELF :: SHF_ALLOC | llvm :: ELF :: SHF_WRITE , <NUM_LIT> * <NUM_LIT> ) ; m_pscommon_1 = pBuilder . CreateSection ( <STR_LIT> , LDFileFormat :: Target , llvm :: ELF :: SHT_PROGBITS , llvm :: ELF :: SHF_ALLOC | llvm :: ELF :: SHF_WRITE , <NUM_LIT> ) ;

IRBuilder :: CreateSectionData ( * m_pscommon_1 ) ;