<s> static DecodeStatus DecodePredRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , void const * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ;

unsigned Register = PredRegDecoderTable [ RegNo ] ;


<s> static DecodeStatus DecodeRegisterClass ( MCInst & Inst , unsigned RegNo , const uint16_t Table [ ] , size_t Size ) {


<s> uint32_t insn = llvm :: <STR_LIT> :: read < uint32_t , llvm :: <STR_LIT> , llvm :: <STR_LIT> > ( Bytes . data ( ) ) ; insn &= ~ static_cast < uint32_t > ( <STR_LIT> :: INST_PARSE_MASK ) ; DecodeStatus Result = decodeInstruction ( DecoderTable32 , MI , insn , Address , this , STI ) ;

<ISA_LIT>MCInstrInfo :: AppendImplicitOperands ( MI ) ;


<s> insn &= ~ static_cast < uint32_t > ( <STR_LIT> :: INST_PARSE_MASK ) ; DecodeStatus Result = decodeInstruction ( DecoderTable32 , MI , insn , Address , this , STI ) ; <ISA_LIT>MCInstrInfo :: AppendImplicitOperands ( MI ) ;


<s> <ISA_LIT>Disassembler ( MCSubtargetInfo const & STI , MCContext & Ctx ) : MCDisassembler ( STI , Ctx ) {


<s> void LLVMInitialize<ISA_LIT>Disassembler ( ) {

TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>Target , create<ISA_LIT>Disassembler ) ;


<s> uint64_t FullValue = fullValue ( Disassembler , MI , SignExtend64 ( tmp , Bits ) ) ; uint32_t Extended = FullValue + Address ; if ( ! Disassembler . tryAddingSymbolicOperand ( MI , Extended , Address , true , <NUM_LIT> , <NUM_LIT> ) ) <ISA_LIT>MCInstrInfo :: addConstant ( MI , Extended , Disassembler . getContext ( ) ) ;


<s> if ( Bits == <NUM_LIT> ) Bits = <NUM_LIT> ; uint64_t FullValue = fullValue ( Disassembler , MI , SignExtend64 ( tmp , Bits ) ) ; uint32_t Extended = FullValue + Address ;

if ( ! Disassembler . tryAddingSymbolicOperand ( MI , Extended , Address , true , <NUM_LIT> , <NUM_LIT> ) ) <ISA_LIT>MCInstrInfo :: addConstant ( MI , Extended , Disassembler . getContext ( ) ) ;


<s> static DecodeStatus DecodeCtrRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const MCDisassembler * Decoder ) { using namespace <ISA_LIT> ; static const MCPhysReg CtrlRegDecoderTable [ ] = { SA0 , LC0 , SA1 , LC1 , P3_0 , C5 , M0 , M1 , USR , PC , UGP , GP , CS0 , CS1 , UPCYCLELO , UPCYCLEHI , FRAMELIMIT , FRAMEKEY , PKTCOUNTLO , PKTCOUNTHI , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , UTIMERLO , UTIMERHI } ; if ( RegNo >= array_lengthof ( CtrlRegDecoderTable ) ) return MCDisassembler :: Fail ;

static_assert ( NoRegister == <NUM_LIT> , <STR_LIT> ) ;


<s> static const MCPhysReg CtrlRegDecoderTable [ ] = { SA0 , LC0 , SA1 , LC1 , P3_0 , C5 , M0 , M1 , USR , PC , UGP , GP , CS0 , CS1 , UPCYCLELO , UPCYCLEHI , FRAMELIMIT , FRAMEKEY , PKTCOUNTLO , PKTCOUNTHI , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , UTIMERLO , UTIMERHI } ; if ( RegNo >= array_lengthof ( CtrlRegDecoderTable ) ) return MCDisassembler :: Fail ;


<s> static DecodeStatus DecodeDoubleRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const MCDisassembler * Decoder ) { static const MCPhysReg DoubleRegDecoderTable [ ] = {


<s> static const MCPhysReg GeneralDoubleLow8RegDecoderTable [ ] = {


return DecodeRegisterClass ( Inst , RegNo , GeneralDoubleLow8RegDecoderTable ) ;


<s> static DecodeStatus DecodeGeneralSubRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { static const MCPhysReg GeneralSubRegDecoderTable [ ] = {


<s> static DecodeStatus DecodeGeneralSubRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { static const MCPhysReg GeneralSubRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ;

return DecodeRegisterClass ( Inst , RegNo , GeneralSubRegDecoderTable ) ;


Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


<s> GELR , GSR , GOSP , G3 , G4 , G5 , G6 , G7 , G8 , G9 , G10 , G11 , G12 , G13 , G14 , G15 , GPMUCNT4 , GPMUCNT5 , GPMUCNT6 , GPMUCNT7 , G20 , G21 , G22 , G23 , GPCYCLELO , GPCYCLEHI , GPMUCNT0 , GPMUCNT1 , GPMUCNT2 , GPMUCNT3 , G30 , G31 } ; if ( RegNo >= array_lengthof ( GuestRegDecoderTable ) ) return MCDisassembler :: Fail ; if ( GuestRegDecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = GuestRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


<s> static const MCPhysReg HvxQRDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ;

return DecodeRegisterClass ( Inst , RegNo , HvxQRDecoderTable ) ;


<s> LLVM_ATTRIBUTE_UNUSED static DecodeStatus DecodeHvxVQRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const MCDisassembler * Decoder ) { static const MCPhysReg HvxVQRDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ;

return DecodeRegisterClass ( Inst , RegNo >> <NUM_LIT> , HvxVQRDecoderTable ) ;


return DecodeRegisterClass ( Inst , RegNo , HvxVRDecoderTable ) ;


return DecodeRegisterClass ( Inst , RegNo , HvxWRDecoderTable ) ;


return DecodeRegisterClass ( Inst , RegNo , IntRegDecoderTable ) ;


<s> break ; case <NUM_LIT> : Register = <STR_LIT> ; break ; default : return MCDisassembler :: Fail ; } Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return MCDisassembler :: Success ;


<s> static const MCPhysReg PredRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ;

return DecodeRegisterClass ( Inst , RegNo , PredRegDecoderTable ) ;


<s> static DecodeStatus DecodeSysRegs64RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const MCDisassembler * Decoder ) { RegNo = RegNo >> <NUM_LIT> ; if ( RegNo >= sizeof ( SysReg64DecoderTable ) / sizeof ( SysReg64DecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ; if ( SysReg64DecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = SysReg64DecoderTable [ RegNo ] ;


<s> if ( RegNo >= sizeof ( SysRegDecoderTable ) / sizeof ( SysRegDecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ; if ( SysRegDecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ;

unsigned Register = SysRegDecoderTable [ RegNo ] ;


<s> static <ISA_LIT>Disassembler const & disassembler ( const MCDisassembler * Decoder ) { return * static_cast < <ISA_LIT>Disassembler const * > ( Decoder ) ;


<s> return * static_cast < <ISA_LIT>Disassembler const * > ( Decoder ) ;


<s> Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } if ( Result == MCDisassembler :: Fail ) return Result ; if ( Size > HEXAGON_MAX_PACKET_SIZE ) return MCDisassembler :: Fail ; const auto ArchSTI = <ISA_LIT>_MC :: getArchSubtarget ( & STI ) ; const auto STI_ = ( ArchSTI != nullptr ) ? * ArchSTI : STI ; <ISA_LIT>MCChecker Checker ( getContext ( ) , * MCII , STI_ , MI , * getContext ( ) . getRegisterInfo ( ) , false ) ;

if ( ! Checker . check ( ) ) return MCDisassembler :: Fail ;


<s> static void signedDecoder ( MCInst & MI , unsigned tmp , const MCDisassembler * Decoder ) { <ISA_LIT>Disassembler const & Disassembler = disassembler ( Decoder ) ;

int64_t FullValue = fullValue ( Disassembler , MI , SignExtend64 < T > ( tmp ) ) ;


<s> int64_t FullValue = fullValue ( Disassembler , MI , tmp ) ; assert ( FullValue >= <NUM_LIT> && <STR_LIT> ) ; <ISA_LIT>MCInstrInfo :: addConstant ( MI , FullValue , Disassembler . getContext ( ) ) ; return MCDisassembler :: Success ;


<s> DecodeStatus Result = DecodeStatus :: Success ; bool Complete = false ; Size = <NUM_LIT> ; * CurrentBundle = & MI ; MI = <ISA_LIT>MCInstrInfo :: createBundle ( ) ; while ( Result == Success && ! Complete ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , os , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } if ( Result == MCDisassembler :: Fail ) return Result ; if ( Size > HEXAGON_MAX_PACKET_SIZE ) return MCDisassembler :: Fail ; <ISA_LIT>MCChecker Checker ( getContext ( ) , * MCII , STI , MI , * getContext ( ) . getRegisterInfo ( ) , false ) ; if ( ! Checker . check ( ) ) return MCDisassembler :: Fail ;


<s> static const uint16_t CtrlReg64DecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( RegNo >= sizeof ( CtrlReg64DecoderTable ) / sizeof ( CtrlReg64DecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ; if ( CtrlReg64DecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = CtrlReg64DecoderTable [ RegNo ] ;


<s> static DecodeStatus DecodeCtrRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { static const uint16_t CtrlRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( RegNo >= sizeof ( CtrlRegDecoderTable ) / sizeof ( CtrlRegDecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ; if ( CtrlRegDecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = CtrlRegDecoderTable [ RegNo ] ;


return ( DecodeRegisterClass ( Inst , RegNo >> <NUM_LIT> , DoubleRegDecoderTable , sizeof ( DoubleRegDecoderTable ) ) ) ;


<s> static const uint16_t DoubleRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return ( DecodeRegisterClass ( Inst , RegNo >> <NUM_LIT> , DoubleRegDecoderTable , sizeof ( DoubleRegDecoderTable ) ) ) ;


return ( DecodeRegisterClass ( Inst , RegNo , IntRegDecoderTable , sizeof ( IntRegDecoderTable ) ) ) ;


<s> static DecodeStatus DecodeIntRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { static const uint16_t IntRegDecoderTable [ ] = {


<s> static const uint16_t PredRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ;

return ( DecodeRegisterClass ( Inst , RegNo , PredRegDecoderTable , sizeof ( PredRegDecoderTable ) ) ) ;


<s> static const uint16_t PredRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return ( DecodeRegisterClass ( Inst , RegNo , PredRegDecoderTable , sizeof ( PredRegDecoderTable ) ) ) ;


<s> Inst . addOperand ( MCOperand :: createReg ( Table [ RegNo ] ) ) ; return MCDisassembler :: Success ; } else return MCDisassembler :: Fail ;


<s> case <STR_LIT> : case <STR_LIT> : { Value |= insn & UINT64_C ( <NUM_LIT> ) ; DecodeIntRegsRegisterClass ( MI , Value , <NUM_LIT> , <NUM_LIT> ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( Value << shift ) ) ; break ; } case <STR_LIT> : { Value = insn & UINT64_C ( <NUM_LIT> ) ; DecodeDoubleRegsRegisterClass ( MI , Value , <NUM_LIT> , <NUM_LIT> ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( Value << <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= insn & UINT64_C ( <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( Value << <NUM_LIT> ) ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; DecodeDoubleRegsRegisterClass ( MI , Value , <NUM_LIT> , <NUM_LIT> ) ; break ; } case <STR_LIT> : ++ shift ; case <STR_LIT> : ++ shift ; case <STR_LIT> : { Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= insn & UINT64_C ( <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( Value << shift ) ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; DecodeIntRegsRegisterClass ( MI , Value , <NUM_LIT> , <NUM_LIT> ) ; break ; } case <STR_LIT> : ++ shift ; case <STR_LIT> : case <STR_LIT> : ++ shift ; case <STR_LIT> : { Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= insn & UINT64_C ( <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( Value << shift ) ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; DecodeIntRegsRegisterClass ( MI , Value , <NUM_LIT> , <NUM_LIT> ) ; break ; } } return MCDisassembler :: Success ;


<s> static const uint16_t VecDblRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return ( DecodeRegisterClass ( Inst , RegNo >> <NUM_LIT> , VecDblRegDecoderTable , sizeof ( VecDblRegDecoderTable ) ) ) ;


<s> static const uint16_t VecPredRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return ( DecodeRegisterClass ( Inst , RegNo , VecPredRegDecoderTable , sizeof ( VecPredRegDecoderTable ) ) ) ;


<s> static DecodeStatus DecodeVecPredRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { static const uint16_t VecPredRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return ( DecodeRegisterClass ( Inst , RegNo , VecPredRegDecoderTable , sizeof ( VecPredRegDecoderTable ) ) ) ;


return ( DecodeRegisterClass ( Inst , RegNo , VecRegDecoderTable , sizeof ( VecRegDecoderTable ) ) ) ;


<s> static const uint16_t VecRegDecoderTable [ ] = {


<s> Size = <NUM_LIT> ; * CurrentBundle = & MI ; MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; while ( Result == Success && ! Complete ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } if ( Result == MCDisassembler :: Fail ) return Result ;

if ( Size > HEXAGON_MAX_PACKET_SIZE ) return MCDisassembler :: Fail ;


<s> if ( Result == MCDisassembler :: Fail ) return Result ; if ( Size > HEXAGON_MAX_PACKET_SIZE ) return MCDisassembler :: Fail ; <ISA_LIT>MCChecker Checker ( getContext ( ) , * MCII , STI , MI , * getContext ( ) . getRegisterInfo ( ) , false ) ; if ( ! Checker . check ( ) ) return MCDisassembler :: Fail ; remapInstruction ( MI ) ; return MCDisassembler :: Success ;


<s> Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } if ( Result == MCDisassembler :: Fail ) return Result ; if ( Size > HEXAGON_MAX_PACKET_SIZE ) return MCDisassembler :: Fail ; const auto ArchSTI = <ISA_LIT>_MC :: getArchSubtarget ( & STI ) ; const auto STI_ = ( ArchSTI != nullptr ) ? * ArchSTI : STI ; <ISA_LIT>MCChecker Checker ( getContext ( ) , * MCII , STI_ , MI , * getContext ( ) . getRegisterInfo ( ) , false ) ; if ( ! Checker . check ( ) ) return MCDisassembler :: Fail ;


<s> MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } if ( Result == MCDisassembler :: Fail ) return Result ; if ( Size > HEXAGON_MAX_PACKET_SIZE ) return MCDisassembler :: Fail ; const auto ArchSTI = <ISA_LIT>_MC :: getArchSubtarget ( & STI ) ; const auto STI_ = ( ArchSTI != nullptr ) ? * ArchSTI : STI ; <ISA_LIT>MCChecker Checker ( getContext ( ) , * MCII , STI_ , MI , * getContext ( ) . getRegisterInfo ( ) , false ) ; if ( ! Checker . check ( ) ) return MCDisassembler :: Fail ;


<s> uint32_t fullValue ( MCInstrInfo const & MCII , MCInst & MCB , MCInst & MI , int64_t Value ) { MCInst const * Extender = <ISA_LIT>MCInstrInfo :: extenderForIndex ( MCB , <ISA_LIT>MCInstrInfo :: bundleSize ( MCB ) ) ; if ( ! Extender || MI . size ( ) != <ISA_LIT>MCInstrInfo :: getExtendableOp ( MCII , MI ) ) return Value ; unsigned Alignment = <ISA_LIT>MCInstrInfo :: getExtentAlignment ( MCII , MI ) ; uint32_t Lower6 = static_cast < uint32_t > ( Value >> Alignment ) & <NUM_LIT> ; int64_t Bits ; bool Success = Extender -> getOperand ( <NUM_LIT> ) . getExpr ( ) -> evaluateAsAbsolute ( Bits ) ; assert ( Success ) ; ( void ) Success ; uint32_t Upper26 = static_cast < uint32_t > ( Bits ) ; uint32_t Operand = Upper26 | Lower6 ; return Operand ;


<s> DecodeStatus <ISA_LIT>Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { DecodeStatus Result = DecodeStatus :: Success ; bool Complete = false ; Size = <NUM_LIT> ; * CurrentBundle = & MI ; MI = <ISA_LIT>MCInstrInfo :: createBundle ( ) ; while ( Result == Success && Complete == false ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , os , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } if ( Result == MCDisassembler :: Fail ) return Result ; <ISA_LIT>MCChecker Checker ( * MCII , STI , MI , MI , * getContext ( ) . getRegisterInfo ( ) ) ; if ( ! Checker . check ( ) ) return MCDisassembler :: Fail ;


<s> signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ; return MCDisassembler :: Success ;


<s> static DecodeStatus s16ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ;


<s> signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ;


<s> static const uint16_t CtrlReg64DecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( RegNo >= sizeof ( CtrlReg64DecoderTable ) / sizeof ( CtrlReg64DecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ;

if ( CtrlReg64DecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ;


<s> static DecodeStatus DecodeCtrRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { static const uint16_t CtrlRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( RegNo >= sizeof ( CtrlRegDecoderTable ) / sizeof ( CtrlRegDecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ;

if ( CtrlRegDecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ;


<s> static DecodeStatus DecodeCtrRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { static const uint16_t CtrlRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( RegNo >= sizeof ( CtrlRegDecoderTable ) / sizeof ( CtrlRegDecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ; if ( CtrlRegDecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ;

unsigned Register = CtrlRegDecoderTable [ RegNo ] ;


<s> Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return MCDisassembler :: Success ;


<s> while ( Result == Success && Complete == false ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ;

Result = getSingleInstruction ( * Inst , MI , Bytes , Address , os , cs , Complete ) ;


<s> <ISA_LIT>Disassembler ( MCSubtargetInfo const & STI , MCContext & Ctx ) : MCDisassembler ( STI , Ctx ) , CurrentBundle ( new MCInst * ) {


<s> DecodeStatus <ISA_LIT>Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { Size = <NUM_LIT> ;

if ( Bytes . size ( ) < <NUM_LIT> ) return MCDisassembler :: Fail ;


<s> static DecodeStatus s10ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { uint64_t imm = SignExtend64 < <NUM_LIT> > ( tmp ) ;

MI . addOperand ( MCOperand :: createImm ( imm ) ) ;


<s> static DecodeStatus s10ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) {

uint64_t imm = SignExtend64 < <NUM_LIT> > ( tmp ) ;


<s> uint64_t imm = SignExtend64 < <NUM_LIT> > ( tmp ) ; MI . addOperand ( MCOperand :: createImm ( imm ) ) ;


<s> MI . addOperand ( MCOperand :: createImm ( imm ) ) ; return MCDisassembler :: Success ;


<s> static DecodeStatus s11_3ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { uint64_t imm = SignExtend64 < <NUM_LIT> > ( tmp ) ;


<s> uint64_t imm = SignExtend64 < <NUM_LIT> > ( tmp ) ; MI . addOperand ( MCOperand :: createImm ( imm ) ) ; return MCDisassembler :: Success ;


<s> static DecodeStatus s16ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) {


<s> static DecodeStatus s4_1ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { uint64_t imm = SignExtend64 < <NUM_LIT> > ( tmp ) ; MI . addOperand ( MCOperand :: createImm ( imm ) ) ; return MCDisassembler :: Success ;


<s> uint64_t imm = SignExtend64 < <NUM_LIT> > ( tmp ) ;


<s> static DecodeStatus s6_0ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { uint64_t imm = SignExtend64 < <NUM_LIT> > ( tmp ) ;


<s> static DecodeStatus s8ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { uint64_t imm = SignExtend64 < <NUM_LIT> > ( tmp ) ; MI . addOperand ( MCOperand :: createImm ( imm ) ) ;


<s> MI . clear ( ) ; MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; while ( Result == Success && Complete == false ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ;


<s> while ( Result == Success && Complete == false ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , os , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ;


<s> uint32_t insn = llvm :: <STR_LIT> :: read < uint32_t , llvm :: <STR_LIT> , llvm :: <STR_LIT> > ( Bytes . data ( ) ) ; insn &= ~ static_cast < uint32_t > ( <STR_LIT> :: INST_PARSE_MASK ) ;

return decodeInstruction ( DecoderTable32 , MI , insn , Address , this , STI ) ;


<s> Size = <NUM_LIT> ; if ( Region . readBytes ( Address , Bytes . size ( ) , Bytes . data ( ) ) == - <NUM_LIT> ) { return MCDisassembler :: Fail ; } uint32_t insn = llvm :: <STR_LIT> :: read < uint32_t , llvm :: <STR_LIT> , llvm :: <STR_LIT> > ( Bytes . data ( ) ) ;

insn &= ~ static_cast < uint32_t > ( <STR_LIT> :: INST_PARSE_MASK ) ;


<s> using namespace <ISA_LIT> ; static const MCPhysReg CtrlReg64DecoderTable [ ] = { C1_0 , <NUM_LIT> , C3_2 , <NUM_LIT> , C5_4 , <NUM_LIT> , C7_6 , <NUM_LIT> , C9_8 , <NUM_LIT> , C11_10 , <NUM_LIT> , CS , <NUM_LIT> , UPC , <NUM_LIT> , C17_16 , <NUM_LIT> , PKTCOUNT , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , UTIMER , <NUM_LIT> } ; if ( RegNo >= array_lengthof ( CtrlReg64DecoderTable ) ) return MCDisassembler :: Fail ; static_assert ( NoRegister == <NUM_LIT> , <STR_LIT> ) ; if ( CtrlReg64DecoderTable [ RegNo ] == NoRegister ) return MCDisassembler :: Fail ; unsigned Register = CtrlReg64DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


static_assert ( NoRegister == <NUM_LIT> , <STR_LIT> ) ;


<s> SA0 , LC0 , SA1 , LC1 , P3_0 , C5 , C6 , C7 , USR , PC , UGP , GP , CS0 , CS1 , UPCL , UPCH , FRAMELIMIT , FRAMEKEY , PKTCOUNTLO , PKTCOUNTHI , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , UTIMERLO , UTIMERHI } ; if ( RegNo >= array_lengthof ( CtrlRegDecoderTable ) ) return MCDisassembler :: Fail ; static_assert ( NoRegister == <NUM_LIT> , <STR_LIT> ) ; if ( CtrlRegDecoderTable [ RegNo ] == NoRegister ) return MCDisassembler :: Fail ;


<s> using namespace <ISA_LIT> ; static const MCPhysReg CtrlRegDecoderTable [ ] = { SA0 , LC0 , SA1 , LC1 , P3_0 , C5 , C6 , C7 , USR , PC , UGP , GP , CS0 , CS1 , UPCL , UPCH , FRAMELIMIT , FRAMEKEY , PKTCOUNTLO , PKTCOUNTHI , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , UTIMERLO , UTIMERHI } ; if ( RegNo >= array_lengthof ( CtrlRegDecoderTable ) ) return MCDisassembler :: Fail ; static_assert ( NoRegister == <NUM_LIT> , <STR_LIT> ) ; if ( CtrlRegDecoderTable [ RegNo ] == NoRegister ) return MCDisassembler :: Fail ; unsigned Register = CtrlRegDecoderTable [ RegNo ] ;

Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


<s> static DecodeStatus s3_6ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { uint64_t imm = SignExtend64 < <NUM_LIT> > ( tmp ) ; MI . addOperand ( MCOperand :: createImm ( imm ) ) ;


<s> static DecodeStatus s4_6ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { uint64_t imm = SignExtend64 < <NUM_LIT> > ( tmp ) ;


<s> RegNo = RegNo >> <NUM_LIT> ; if ( RegNo >= sizeof ( SysReg64DecoderTable ) / sizeof ( SysReg64DecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ; if ( SysReg64DecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = SysReg64DecoderTable [ RegNo ] ;


if ( RegNo >= sizeof ( SysReg64DecoderTable ) / sizeof ( SysReg64DecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ;


<s> static DecodeStatus DecodeSysRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { if ( RegNo >= sizeof ( SysRegDecoderTable ) / sizeof ( SysRegDecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ; if ( SysRegDecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = SysRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return MCDisassembler :: Success ;


<s> unsigned Register = SysRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return MCDisassembler :: Success ;


<s> MI . insert ( MI . begin ( ) + <NUM_LIT> , MCOperand :: createExpr ( MCConstantExpr :: create ( - <NUM_LIT> , Context ) ) ) ; break ; default : break ; }


<s> uint32_t Extended = FullValue + Address ;

if ( ! Disassembler . tryAddingSymbolicOperand ( MI , Extended , Address , true , <NUM_LIT> , <NUM_LIT> ) ) <ISA_LIT>MCInstrInfo :: addConstant ( MI , Extended , Disassembler . getContext ( ) ) ;


<s> <ISA_LIT>Disassembler const & Disassembler = disassembler ( Decoder ) ; unsigned Bits = <ISA_LIT>MCInstrInfo :: getExtentBits ( * Disassembler . MCII , MI ) ; if ( Bits == <NUM_LIT> ) Bits = <NUM_LIT> ;

uint64_t FullValue = fullValue ( Disassembler , MI , SignExtend64 ( tmp , Bits ) ) ;


<s> return new <ISA_LIT>Disassembler ( STI , Ctx , T . createMCInstrInfo ( ) ) ;


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>Disassembler ( STI , Ctx , T . createMCInstrInfo ( ) ) ;


<s> if ( RegNo >= array_lengthof ( CtrlReg64DecoderTable ) ) return MCDisassembler :: Fail ; static_assert ( NoRegister == <NUM_LIT> , <STR_LIT> ) ; if ( CtrlReg64DecoderTable [ RegNo ] == NoRegister ) return MCDisassembler :: Fail ; unsigned Register = CtrlReg64DecoderTable [ RegNo ] ;


<s> static const MCPhysReg CtrlRegDecoderTable [ ] = { SA0 , LC0 , SA1 , LC1 , P3_0 , C5 , M0 , M1 , USR , PC , UGP , GP , CS0 , CS1 , UPCYCLELO , UPCYCLEHI , FRAMELIMIT , FRAMEKEY , PKTCOUNTLO , PKTCOUNTHI , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , UTIMERLO , UTIMERHI } ; if ( RegNo >= array_lengthof ( CtrlRegDecoderTable ) ) return MCDisassembler :: Fail ; static_assert ( NoRegister == <NUM_LIT> , <STR_LIT> ) ;

if ( CtrlRegDecoderTable [ RegNo ] == NoRegister ) return MCDisassembler :: Fail ;


<s> using namespace <ISA_LIT> ; static const MCPhysReg CtrlRegDecoderTable [ ] = { SA0 , LC0 , SA1 , LC1 , P3_0 , C5 , M0 , M1 , USR , PC , UGP , GP , CS0 , CS1 , UPCYCLELO , UPCYCLEHI , FRAMELIMIT , FRAMEKEY , PKTCOUNTLO , PKTCOUNTHI , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , UTIMERLO , UTIMERHI } ; if ( RegNo >= array_lengthof ( CtrlRegDecoderTable ) ) return MCDisassembler :: Fail ; static_assert ( NoRegister == <NUM_LIT> , <STR_LIT> ) ; if ( CtrlRegDecoderTable [ RegNo ] == NoRegister ) return MCDisassembler :: Fail ; unsigned Register = CtrlRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


<s> static DecodeStatus DecodeDoubleRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { static const MCPhysReg DoubleRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ;

return DecodeRegisterClass ( Inst , RegNo >> <NUM_LIT> , DoubleRegDecoderTable ) ;


static const MCPhysReg GeneralDoubleLow8RegDecoderTable [ ] = {


return DecodeRegisterClass ( Inst , RegNo , GeneralDoubleLow8RegDecoderTable ) ;


return DecodeRegisterClass ( Inst , RegNo , GeneralSubRegDecoderTable ) ;


<s> static DecodeStatus DecodeGuestRegs64RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { using namespace <ISA_LIT> ; static const MCPhysReg GuestReg64DecoderTable [ ] = { G1_0 , <NUM_LIT> , G3_2 , <NUM_LIT> , G5_4 , <NUM_LIT> , G7_6 , <NUM_LIT> , G9_8 , <NUM_LIT> , G11_10 , <NUM_LIT> , G13_12 , <NUM_LIT> , G15_14 , <NUM_LIT> , G17_16 , <NUM_LIT> , G19_18 , <NUM_LIT> , G21_20 , <NUM_LIT> , G23_22 , <NUM_LIT> , G25_24 , <NUM_LIT> , G27_26 , <NUM_LIT> , G29_28 , <NUM_LIT> , G31_30 , <NUM_LIT> } ; if ( RegNo >= array_lengthof ( GuestReg64DecoderTable ) ) return MCDisassembler :: Fail ; if ( GuestReg64DecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = GuestReg64DecoderTable [ RegNo ] ;


<s> static DecodeStatus DecodeHvxQRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { static const MCPhysReg HvxQRDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ;

return DecodeRegisterClass ( Inst , RegNo , HvxQRDecoderTable ) ;


<s> static const MCPhysReg HvxQRDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ;


<s> static const MCPhysReg HvxVQRDecoderTable [ ] = {


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return DecodeRegisterClass ( Inst , RegNo >> <NUM_LIT> , HvxVQRDecoderTable ) ;


return DecodeRegisterClass ( Inst , RegNo , HvxVRDecoderTable ) ;


<s> static DecodeStatus DecodeHvxWRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { static const MCPhysReg HvxWRDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return ( DecodeRegisterClass ( Inst , RegNo >> <NUM_LIT> , HvxWRDecoderTable ) ) ;


<s> static DecodeStatus DecodeIntRegsLow8RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { return DecodeIntRegsRegisterClass ( Inst , RegNo , Address , Decoder ) ;


<s> return DecodeIntRegsRegisterClass ( Inst , RegNo , Address , Decoder ) ;


<s> switch ( RegNo ) { case <NUM_LIT> : Register = <STR_LIT> ; break ; case <NUM_LIT> : Register = <STR_LIT> ; break ; default : return MCDisassembler :: Fail ; }


<s> unsigned Register = <NUM_LIT> ; switch ( RegNo ) { case <NUM_LIT> : Register = <STR_LIT> ; break ; case <NUM_LIT> : Register = <STR_LIT> ; break ; default :


<s> static const MCPhysReg PredRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return DecodeRegisterClass ( Inst , RegNo , PredRegDecoderTable ) ;


<s> static <ISA_LIT>Disassembler const & disassembler ( void const * Decoder ) {

return * static_cast < <ISA_LIT>Disassembler const * > ( Decoder ) ;


<s> uint32_t Lower6 = static_cast < uint32_t > ( Value >> Alignment ) & <NUM_LIT> ; int64_t Bits ; bool Success = Disassembler . CurrentExtender -> getOperand ( <NUM_LIT> ) . getExpr ( ) -> evaluateAsAbsolute ( Bits ) ; assert ( Success ) ;


<s> if ( ! Disassembler . CurrentExtender || MI . size ( ) != <ISA_LIT>MCInstrInfo :: getExtendableOp ( MCII , MI ) ) return Value ; unsigned Alignment = <ISA_LIT>MCInstrInfo :: getExtentAlignment ( MCII , MI ) ; uint32_t Lower6 = static_cast < uint32_t > ( Value >> Alignment ) & <NUM_LIT> ; int64_t Bits ; bool Success = Disassembler . CurrentExtender -> getOperand ( <NUM_LIT> ) . getExpr ( ) -> evaluateAsAbsolute ( Bits ) ;


<s> * CurrentBundle = & MI ; MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; while ( Result == Success && ! Complete ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , os , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } if ( Result == MCDisassembler :: Fail ) return Result ;

if ( Size > HEXAGON_MAX_PACKET_SIZE ) return MCDisassembler :: Fail ;


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx , MCInstrInfo const * MCII ) : MCDisassembler ( STI , Ctx ) , MCII ( MCII ) , CurrentBundle ( new MCInst * ) , CurrentExtender ( nullptr ) {


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>Disassembler ) ;


<s> } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { MI . setOpcode ( L4_return_map_to_raw_t ) ; MI . erase ( MI . begin ( ) + <NUM_LIT> ) ; MI . erase ( MI . begin ( ) ) ; } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { MI . setOpcode ( L4_return_map_to_raw_f ) ; MI . erase ( MI . begin ( ) + <NUM_LIT> ) ; MI . erase ( MI . begin ( ) ) ; } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { MI . setOpcode ( L4_return_map_to_raw_tnew_pt ) ; MI . erase ( MI . begin ( ) + <NUM_LIT> ) ; MI . erase ( MI . begin ( ) ) ; } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { MI . setOpcode ( L4_return_map_to_raw_fnew_pt ) ; MI . erase ( MI . begin ( ) + <NUM_LIT> ) ; MI . erase ( MI . begin ( ) ) ; } break ;


<s> static DecodeStatus s32_0ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { <ISA_LIT>Disassembler const & Disassembler = disassembler ( Decoder ) ; unsigned Bits = <ISA_LIT>MCInstrInfo :: getExtentBits ( * Disassembler . MCII , MI ) ; tmp = SignExtend64 ( tmp , Bits ) ; signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ; return MCDisassembler :: Success ;


<s> <ISA_LIT>Disassembler const & Disassembler = disassembler ( Decoder ) ; int64_t FullValue = fullValue ( Disassembler , MI , SignExtend64 < T > ( tmp ) ) ; int64_t Extended = SignExtend64 < <NUM_LIT> > ( FullValue ) ;

<ISA_LIT>MCInstrInfo :: addConstant ( MI , Extended , Disassembler . getContext ( ) ) ;


<s> static void signedDecoder ( MCInst & MI , unsigned tmp , const void * Decoder ) { <ISA_LIT>Disassembler const & Disassembler = disassembler ( Decoder ) ;

int64_t FullValue = fullValue ( Disassembler , MI , SignExtend64 < T > ( tmp ) ) ;


<s> <ISA_LIT>Disassembler const & Disassembler = disassembler ( Decoder ) ; int64_t FullValue = fullValue ( Disassembler , MI , tmp ) ; assert ( FullValue >= <NUM_LIT> && <STR_LIT> ) ; <ISA_LIT>MCInstrInfo :: addConstant ( MI , FullValue , Disassembler . getContext ( ) ) ;


<s> MachineBasicBlock :: const_iterator I , E = B -> getFirstNonPHI ( ) ; for ( I = B -> begin ( ) ; I != E ; ++ I ) { const MachineOperand & RO1 = I -> getOperand ( <NUM_LIT> ) ; const MachineOperand & RO3 = I -> getOperand ( <NUM_LIT> ) ; assert ( RO1 . isReg ( ) && RO3 . isReg ( ) ) ; if ( RO1 . getSubReg ( ) != <NUM_LIT> || RO3 . getSubReg ( ) != <NUM_LIT> ) { Cost ++ ; continue ; } MachineInstr * Def1 = MRI -> getVRegDef ( RO1 . getReg ( ) ) ; MachineInstr * Def3 = MRI -> getVRegDef ( RO3 . getReg ( ) ) ; if ( ! TII -> isPredicable ( Def1 ) || ! TII -> isPredicable ( Def3 ) ) Cost ++ ; } return Cost ;


<s> assert ( ! SSB ) ; SSB = T ; } FP . SplitB -> removeSuccessor ( FP . SplitB -> succ_begin ( ) ) ; } if ( FP . JoinB ) { assert ( ! SSB || SSB == FP . JoinB ) ; BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( FP . JoinB ) ; FP . SplitB -> addSuccessor ( FP . JoinB ) ; } else { bool HasBranch = false ; if ( TSB ) { BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addReg ( FP . PredR ) . addMBB ( TSB ) ; FP . SplitB -> addSuccessor ( TSB ) ; HasBranch = true ; } if ( FSB ) { const MCInstrDesc & D = HasBranch ? TII -> get ( <STR_LIT> ) : TII -> get ( <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , D ) ; if ( ! HasBranch ) MIB . addReg ( FP . PredR ) ; MIB . addMBB ( FSB ) ; FP . SplitB -> addSuccessor ( FSB ) ; } if ( SSB ) { BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( SSB ) ; FP . SplitB -> addSuccessor ( SSB ) ; } } if ( FP . JoinB ) {


<s> predicateBlockNB ( FP . SplitB , OldTI , FP . TrueB , FP . PredR , true ) ; } if ( FP . FalseB ) { FSB = * FP . FalseB -> succ_begin ( ) ; MachineBasicBlock :: iterator At = FP . SplitB -> getFirstTerminator ( ) ; predicateBlockNB ( FP . SplitB , At , FP . FalseB , FP . PredR , false ) ; } MachineBasicBlock * SSB = <NUM_LIT> ; FP . SplitB -> erase ( OldTI , FP . SplitB -> end ( ) ) ; while ( FP . SplitB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * T = * FP . SplitB -> succ_begin ( ) ; if ( T != FP . TrueB && T != FP . FalseB ) { assert ( ! SSB ) ; SSB = T ; } FP . SplitB -> removeSuccessor ( FP . SplitB -> succ_begin ( ) ) ; } if ( FP . JoinB ) { assert ( ! SSB || SSB == FP . JoinB ) ; BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( FP . JoinB ) ; FP . SplitB -> addSuccessor ( FP . JoinB ) ; } else { bool HasBranch = false ; if ( TSB ) { BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addReg ( FP . PredR ) . addMBB ( TSB ) ; FP . SplitB -> addSuccessor ( TSB ) ; HasBranch = true ;


<s> for ( ConstMIOperands MO ( & MI ) ; MO . isValid ( ) ; ++ MO ) { if ( ! MO -> isReg ( ) || ! MO -> isDef ( ) ) continue ; unsigned R = MO -> getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; if ( MRI -> getRegClass ( R ) == & <STR_LIT> ) PredDefs ++ ; }


<s> return new <ISA_LIT>EarlyIfConversion ( ) ;


<s> DebugLoc DL = PN -> getDebugLoc ( ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( DefR ) ; NewR = MRI -> createVirtualRegister ( RC ) ; NonPHI = BuildMI ( * B , NonPHI , DL , TII -> get ( TargetOpcode :: COPY ) , NewR ) . addReg ( UseR , <NUM_LIT> , UseSR ) ; } MRI -> replaceRegWith ( DefR , NewR ) ;


<s> void <ISA_LIT>EarlyIfConversion :: eliminatePhis ( MachineBasicBlock * B ) { DEBUG ( dbgs ( ) << <STR_LIT> << PrintMB ( B ) << <STR_LIT> ) ; MachineBasicBlock :: iterator I , NextI , NonPHI = B -> getFirstNonPHI ( ) ; for ( I = B -> begin ( ) ; I != NonPHI ; I = NextI ) { NextI = std :: next ( I ) ;


<s> FlowPattern ( MachineBasicBlock * B , unsigned PR , MachineBasicBlock * TB , MachineBasicBlock * FB , MachineBasicBlock * JB ) : SplitB ( B ) , TrueB ( TB ) , FalseB ( FB ) , JoinB ( JB ) , PredR ( PR ) {


<s> AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ;

MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> case S2_storerhabs : case S2_storerhgp : return IfTrue ? S4_pstorerht_abs : S4_pstorerhf_abs ; case S2_storerf_io : return IfTrue ? S2_pstorerft_io : S2_pstorerff_io ; case S4_storerf_rr : return IfTrue ? S4_pstorerft_rr : S4_pstorerff_rr ; case S2_storerfabs : case S2_storerfgp : return IfTrue ? S4_pstorerft_abs : S4_pstorerff_abs ; case S4_storeirh_io : return IfTrue ? S4_storeirht_io : S4_storeirhf_io ; case S2_storeri_io : return IfTrue ? S2_pstorerit_io : S2_pstorerif_io ; case S4_storeri_rr : return IfTrue ? S4_pstorerit_rr : S4_pstorerif_rr ; case S2_storeriabs : case S2_storerigp :

return IfTrue ? S4_pstorerit_abs : S4_pstorerif_abs ;


<s> for ( auto & I : * B ) if ( I . isEHLabel ( ) ) return true ; return false ;


<s> MachineBasicBlock :: const_iterator I = B -> getFirstTerminator ( ) , E = B -> end ( ) ; while ( I != E ) { if ( I -> isBarrier ( ) ) return true ; ++ I ; } return false ;


<s> case S2_storerhabs : case S4_storeirh_io : case S2_storerhgp : case S2_storerf_io : case S4_storerf_rr : case S2_storerfabs : case S2_storerfgp : case S2_storeri_io : case S4_storeri_rr : case S2_storeriabs : case S4_storeiri_io : case S2_storerigp : case S2_storerd_io : case S4_storerd_rr : case S2_storerdabs : case S2_storerdgp : return true ; }


<s> bool <ISA_LIT>EarlyIfConversion :: isPreheader ( const MachineBasicBlock * B ) const { if ( B -> succ_size ( ) != <NUM_LIT> ) return false ; MachineBasicBlock * SB = * B -> succ_begin ( ) ; MachineLoop * L = MLI -> getLoopFor ( SB ) ;


<s> if ( B -> succ_size ( ) != <NUM_LIT> ) return false ; MachineBasicBlock * SB = * B -> succ_begin ( ) ; MachineLoop * L = MLI -> getLoopFor ( SB ) ;


<s> MachineBasicBlock * TSB = * FP . TrueB -> succ_begin ( ) ; MachineBasicBlock * FSB = * FP . FalseB -> succ_begin ( ) ; if ( TSB != FSB ) return false ; if ( TSB -> pred_size ( ) != <NUM_LIT> ) return false ; } unsigned TS = <NUM_LIT> , FS = <NUM_LIT> , Spare = <NUM_LIT> ; if ( FP . TrueB ) { TS = std :: distance ( FP . TrueB -> begin ( ) , FP . TrueB -> getFirstTerminator ( ) ) ; if ( TS < HEXAGON_PACKET_SIZE ) Spare += HEXAGON_PACKET_SIZE - TS ; } if ( FP . FalseB ) { FS = std :: distance ( FP . FalseB -> begin ( ) , FP . FalseB -> getFirstTerminator ( ) ) ; if ( FS < HEXAGON_PACKET_SIZE ) Spare += HEXAGON_PACKET_SIZE - TS ; } unsigned TotalIn = TS + FS ; DEBUG ( dbgs ( ) << <STR_LIT> << TotalIn << <STR_LIT> << Spare << <STR_LIT> ) ; if ( TotalIn >= SizeLimit + Spare ) return false ; unsigned TotalPh = <NUM_LIT> ; unsigned PredDefs = countPredicateDefs ( FP . SplitB ) ; if ( FP . JoinB ) { TotalPh = computePhiCost ( FP . JoinB ) ;

PredDefs += countPredicateDefs ( FP . JoinB ) ;


<s> } MachineBasicBlock * TSB = * FP . TrueB -> succ_begin ( ) ; MachineBasicBlock * FSB = * FP . FalseB -> succ_begin ( ) ; if ( TSB != FSB ) return false ; if ( TSB -> pred_size ( ) != <NUM_LIT> ) return false ; } unsigned TS = <NUM_LIT> , FS = <NUM_LIT> , Spare = <NUM_LIT> ; if ( FP . TrueB ) { TS = std :: distance ( FP . TrueB -> begin ( ) , FP . TrueB -> getFirstTerminator ( ) ) ; if ( TS < HEXAGON_PACKET_SIZE ) Spare += HEXAGON_PACKET_SIZE - TS ; } if ( FP . FalseB ) { FS = std :: distance ( FP . FalseB -> begin ( ) , FP . FalseB -> getFirstTerminator ( ) ) ; if ( FS < HEXAGON_PACKET_SIZE ) Spare += HEXAGON_PACKET_SIZE - TS ; } unsigned TotalIn = TS + FS ; DEBUG ( dbgs ( ) << <STR_LIT> << TotalIn << <STR_LIT> << Spare << <STR_LIT> ) ; if ( TotalIn >= SizeLimit + Spare ) return false ; unsigned TotalPh = <NUM_LIT> ; unsigned PredDefs = countPredicateDefs ( FP . SplitB ) ; if ( FP . JoinB ) { TotalPh = computePhiCost ( FP . JoinB ) ; PredDefs += countPredicateDefs ( FP . JoinB ) ; } else { if ( FP . TrueB && FP . TrueB -> succ_size ( ) > <NUM_LIT> ) {

MachineBasicBlock * SB = * FP . TrueB -> succ_begin ( ) ;


<s> if ( MI -> mayLoad ( ) || MI -> mayStore ( ) ) return false ;

if ( MI -> isCall ( ) || MI -> isBarrier ( ) || MI -> isBranch ( ) ) return false ;


<s> const MachineBasicBlock & B = * FP . JoinB ; for ( auto & MI : B ) { if ( ! MI . isPHI ( ) ) break ; if ( usesUndefVReg ( & MI ) ) return false ; unsigned DefR = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( DefR ) ; if ( RC == & <STR_LIT> ) return false ; } }


<s> if ( ! isPredicableStore ( & MI ) && ! IsJMP && ! isSafeToSpeculate ( & MI ) ) return false ; for ( ConstMIOperands MO ( & MI ) ; MO . isValid ( ) ; ++ MO ) { if ( ! MO -> isReg ( ) || ! MO -> isDef ( ) ) continue ; unsigned R = MO -> getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ;

if ( MRI -> getRegClass ( R ) != & <STR_LIT> ) continue ;


<s> if ( MI . isDebugValue ( ) ) continue ; if ( MI . isConditionalBranch ( ) ) return false ; unsigned Opc = MI . getOpcode ( ) ; bool IsJMP = ( Opc == <STR_LIT> ) ; if ( ! isPredicableStore ( & MI ) && ! IsJMP && ! isSafeToSpeculate ( & MI ) ) return false ; for ( ConstMIOperands MO ( & MI ) ; MO . isValid ( ) ; ++ MO ) { if ( ! MO -> isReg ( ) || ! MO -> isDef ( ) ) continue ; unsigned R = MO -> getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; if ( MRI -> getRegClass ( R ) != & <STR_LIT> ) continue ; for ( auto U = MRI -> use_begin ( R ) ; U != MRI -> use_end ( ) ; ++ U ) if ( U -> getParent ( ) -> isPHI ( ) ) return false ; } }


<s> return false ; } if ( MLI -> getLoopFor ( T1B ) != L || MLI -> getLoopFor ( T2B ) != L ) return false ; if ( Opc == <STR_LIT> ) TB = T1B , FB = T2B ; else TB = T2B , FB = T1B ; if ( ! MDT -> properlyDominates ( B , TB ) || ! MDT -> properlyDominates ( B , FB ) ) return false ; unsigned TNP = TB -> pred_size ( ) , FNP = FB -> pred_size ( ) ; unsigned TNS = TB -> succ_size ( ) , FNS = FB -> succ_size ( ) ; bool TOk = ( TNP == <NUM_LIT> ) && ( TNS == <NUM_LIT> ) ; bool FOk = ( FNP == <NUM_LIT> ) && ( FNS == <NUM_LIT> ) ; if ( ! TOk && ! FOk ) return false ; MachineBasicBlock * TSB = ( TNS > <NUM_LIT> ) ? * TB -> succ_begin ( ) : <NUM_LIT> ; MachineBasicBlock * FSB = ( FNS > <NUM_LIT> ) ? * FB -> succ_begin ( ) : <NUM_LIT> ; MachineBasicBlock * JB = <NUM_LIT> ; if ( TOk ) { if ( FOk ) { if ( TSB == FSB ) JB = TSB ; } else { if ( TSB == FB ) { JB = FB ; FB = <NUM_LIT> ; }


<s> PredB -> splice ( PredB -> end ( ) , SuccB , SuccB -> begin ( ) , SuccB -> end ( ) ) ; MachineBasicBlock :: succ_iterator I , E = SuccB -> succ_end ( ) ; for ( I = SuccB -> succ_begin ( ) ; I != E ; ++ I ) PredB -> addSuccessor ( * I ) ; PredB -> normalizeSuccProbs ( ) ; replacePhiEdges ( SuccB , PredB ) ;


<s> NextI = std :: next ( I ) ; if ( isSafeToSpeculate ( & * I ) ) ToB -> splice ( At , FromB , I ) ; else predicateInstr ( ToB , At , & * I , PredR , IfTrue ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> << PrintMB ( FromB ) << <STR_LIT> ) ; MachineBasicBlock :: iterator End = FromB -> getFirstTerminator ( ) ; MachineBasicBlock :: iterator I , NextI ; for ( I = FromB -> begin ( ) ; I != End ; I = NextI ) { assert ( ! I -> isPHI ( ) ) ; NextI = std :: next ( I ) ;

if ( isSafeToSpeculate ( & * I ) ) ToB -> splice ( At , FromB , I ) ;


<s> else if ( ! ToB -> empty ( ) ) DL = ToB -> back ( ) . getDebugLoc ( ) ; unsigned Opc = MI -> getOpcode ( ) ; if ( isPredicableStore ( MI ) ) { unsigned COpc = getCondStoreOpcode ( Opc , IfTrue ) ; assert ( COpc ) ; MachineInstrBuilder MIB = BuildMI ( * ToB , At , DL , TII -> get ( COpc ) ) . addReg ( PredR ) ; for ( MIOperands MO ( MI ) ; MO . isValid ( ) ; ++ MO ) MIB . addOperand ( * MO ) ; MachineInstr :: mmo_iterator MMOBegin = MI -> memoperands_begin ( ) ; MachineInstr :: mmo_iterator MMOEnd = MI -> memoperands_end ( ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MI -> eraseFromParent ( ) ; return ;


<s> PrintFP ( const FlowPattern & P , const TargetRegisterInfo & T ) : FP ( P ) , TRI ( T ) {


<s> PrintMB ( const MachineBasicBlock * B ) : MB ( B ) {


<s> } } while ( B -> succ_size ( ) > <NUM_LIT> ) B -> removeSuccessor ( B -> succ_begin ( ) ) ; for ( auto I = B -> pred_begin ( ) , E = B -> pred_end ( ) ; I != E ; ++ I ) ( * I ) -> removeSuccessor ( B , true ) ; Deleted . insert ( B ) ;


<s> if ( IDN ) { MachineBasicBlock * IDB = IDN -> getBlock ( ) ; typedef GraphTraits < MachineDomTreeNode * > GTN ; typedef SmallVector < MachineDomTreeNode * , <NUM_LIT> > DTNodeVectType ; DTNodeVectType Cn ( GTN :: child_begin ( N ) , GTN :: child_end ( N ) ) ; for ( DTNodeVectType :: iterator I = Cn . begin ( ) , E = Cn . end ( ) ; I != E ; ++ I ) {

MachineBasicBlock * SB = ( * I ) -> getBlock ( ) ;


<s> for ( auto I = OldB -> succ_begin ( ) , E = OldB -> succ_end ( ) ; I != E ; ++ I ) { MachineBasicBlock * SB = * I ;

MachineBasicBlock :: iterator P , N = SB -> getFirstNonPHI ( ) ;


<s> MachineBasicBlock :: iterator P , N = SB -> getFirstNonPHI ( ) ; for ( P = SB -> begin ( ) ; P != N ; ++ P ) { MachineInstr * PN = & * P ; for ( MIOperands MO ( PN ) ; MO . isValid ( ) ; ++ MO ) if ( MO -> isMBB ( ) && MO -> getMBB ( ) == OldB ) MO -> setMBB ( NewB ) ; }


<s> MLI = & getAnalysis < MachineLoopInfo > ( ) ; MBPI = Enable<ISA_LIT>BP ? & getAnalysis < MachineBranchProbabilityInfo > ( ) : nullptr ; Deleted . clear ( ) ; bool Changed = false ; for ( MachineLoopInfo :: iterator I = MLI -> begin ( ) , E = MLI -> end ( ) ; I != E ; ++ I ) Changed |= visitLoop ( * I ) ;


<s> MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MBPI = Enable<ISA_LIT>BP ? & getAnalysis < MachineBranchProbabilityInfo > ( ) : nullptr ; Deleted . clear ( ) ;


<s> if ( FP . TrueB ) removeBlock ( FP . TrueB ) ; if ( FP . FalseB ) removeBlock ( FP . FalseB ) ; FP . SplitB -> updateTerminator ( ) ; if ( FP . SplitB -> succ_size ( ) != <NUM_LIT> ) return ; MachineBasicBlock * SB = * FP . SplitB -> succ_begin ( ) ; if ( SB -> pred_size ( ) != <NUM_LIT> ) return ; if ( ! hasEHLabel ( SB ) || hasUncondBranch ( SB ) ) mergeBlocks ( FP . SplitB , SB ) ;


<s> PN -> RemoveOperand ( i ) ; } if ( TR == <NUM_LIT> ) TR = SR , TSR = SSR ; else if ( FR == <NUM_LIT> ) FR = SR , FSR = SSR ; assert ( TR && FR ) ; using namespace <ISA_LIT> ; unsigned DR = PN -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( DR ) ; const MCInstrDesc & D = RC == & IntRegsRegClass ? TII -> get ( C2_mux ) : TII -> get ( MUX64_rr ) ; MachineBasicBlock :: iterator MuxAt = FP . SplitB -> getFirstTerminator ( ) ; DebugLoc DL ; if ( MuxAt != FP . SplitB -> end ( ) ) DL = MuxAt -> getDebugLoc ( ) ; unsigned MuxR = MRI -> createVirtualRegister ( RC ) ; BuildMI ( * FP . SplitB , MuxAt , DL , D , MuxR ) . addReg ( FP . PredR ) . addReg ( TR , <NUM_LIT> , TSR ) . addReg ( FR , <NUM_LIT> , FSR ) ; PN -> addOperand ( MachineOperand :: CreateReg ( MuxR , false ) ) ; PN -> addOperand ( MachineOperand :: CreateMBB ( FP . SplitB ) ) ; }


<s> bool <ISA_LIT>EarlyIfConversion :: usesUndefVReg ( const MachineInstr * MI ) const { for ( ConstMIOperands MO ( MI ) ; MO . isValid ( ) ; ++ MO ) { if ( ! MO -> isReg ( ) || ! MO -> isUse ( ) ) continue ;


<s> if ( ! MO -> isReg ( ) || ! MO -> isUse ( ) ) continue ; unsigned R = MO -> getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; const MachineInstr * DefI = MRI -> getVRegDef ( R ) ; assert ( DefI && <STR_LIT> ) ;

if ( DefI -> isImplicitDef ( ) ) return true ;


<s> typedef SmallVector < MachineDomTreeNode * , <NUM_LIT> > DTNodeVectType ; DTNodeVectType Cn ( GTN :: child_begin ( N ) , GTN :: child_end ( N ) ) ; for ( DTNodeVectType :: iterator I = Cn . begin ( ) , E = Cn . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * SB = ( * I ) -> getBlock ( ) ; if ( ! Deleted . count ( SB ) ) Changed |= visitBlock ( SB , L ) ; } if ( MLI -> getLoopFor ( B ) != L ) return Changed ; FlowPattern FP ;

if ( ! matchFlowPattern ( B , L , FP ) ) return Changed ;


<s> DTNodeVectType Cn ( GTN :: child_begin ( N ) , GTN :: child_end ( N ) ) ; for ( DTNodeVectType :: iterator I = Cn . begin ( ) , E = Cn . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * SB = ( * I ) -> getBlock ( ) ; if ( ! Deleted . count ( SB ) ) Changed |= visitBlock ( SB , L ) ; } if ( MLI -> getLoopFor ( B ) != L ) return Changed ; FlowPattern FP ; if ( ! matchFlowPattern ( B , L , FP ) ) return Changed ;


<s> MachineBasicBlock * HB = L ? L -> getHeader ( ) : <NUM_LIT> ; DEBUG ( ( L ? dbgs ( ) << <STR_LIT> << PrintMB ( HB ) : dbgs ( ) << <STR_LIT> ) << <STR_LIT> ) ; bool Changed = false ; if ( L ) { for ( MachineLoop :: iterator I = L -> begin ( ) , E = L -> end ( ) ; I != E ; ++ I ) Changed |= visitLoop ( * I ) ;


<s> for ( MachineLoop :: iterator I = L -> begin ( ) , E = L -> end ( ) ; I != E ; ++ I ) Changed |= visitLoop ( * I ) ; } MachineBasicBlock * EntryB = GraphTraits < MachineFunction * > :: getEntryNode ( MFN ) ;

Changed |= visitBlock ( L ? HB : EntryB , L ) ;


<s> bool <ISA_LIT>EarlyIfConversion :: isValidCandidate ( const MachineBasicBlock * B ) const { if ( ! B ) return true ; if ( B -> isEHPad ( ) || B -> hasAddressTaken ( ) ) return false ; if ( B -> succ_empty ( ) ) return false ; for ( auto & MI : * B ) { if ( MI . isDebugInstr ( ) ) continue ; if ( MI . isConditionalBranch ( ) ) return false ; unsigned Opc = MI . getOpcode ( ) ; bool IsJMP = ( Opc == <STR_LIT> ) ; if ( ! isPredicableStore ( & MI ) && ! IsJMP && ! isSafeToSpeculate ( & MI ) ) return false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ;


<s> bool <ISA_LIT>EarlyIfConversion :: isValidCandidate ( const MachineBasicBlock * B ) const { if ( ! B ) return true ; if ( B -> isEHPad ( ) || B -> hasAddressTaken ( ) ) return false ; if ( B -> succ_empty ( ) ) return false ; for ( auto & MI : * B ) { if ( MI . isDebugInstr ( ) ) continue ; if ( MI . isConditionalBranch ( ) ) return false ;


<s> using GTN = GraphTraits < MachineDomTreeNode * > ; using DTNodeVectType = SmallVector < MachineDomTreeNode * , <NUM_LIT> > ; DTNodeVectType Cn ( GTN :: child_begin ( N ) , GTN :: child_end ( N ) ) ; for ( auto & I : Cn ) { MachineBasicBlock * SB = I -> getBlock ( ) ; MDT -> changeImmediateDominator ( SB , IDB ) ; } } while ( ! B -> succ_empty ( ) ) B -> removeSuccessor ( B -> succ_begin ( ) ) ; for ( MachineBasicBlock * Pred : B -> predecessors ( ) ) Pred -> removeSuccessor ( B , true ) ; Deleted . insert ( B ) ; MDT -> eraseNode ( B ) ;


<s> MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MBPI = Enable<ISA_LIT>BP ? & getAnalysis < MachineBranchProbabilityInfo > ( ) : nullptr ; Deleted . clear ( ) ; bool Changed = false ; for ( MachineLoop * L : * MLI ) Changed |= visitLoop ( L ) ; Changed |= visitLoop ( nullptr ) ;


<s> auto & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; HII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MBPI = Enable<ISA_LIT>BP ? & getAnalysis < MachineBranchProbabilityInfo > ( ) : nullptr ; Deleted . clear ( ) ;


<s> MachineBasicBlock * SB = I -> getBlock ( ) ; if ( ! Deleted . count ( SB ) ) Changed |= visitBlock ( SB , L ) ; } if ( MLI -> getLoopFor ( B ) != L ) return Changed ; FlowPattern FP ; if ( ! matchFlowPattern ( B , L , FP ) ) return Changed ; if ( ! isValid ( FP ) ) {


<s> LLVM_DEBUG ( ( L ? dbgs ( ) << <STR_LIT> << PrintMB ( HB ) : dbgs ( ) << <STR_LIT> ) << <STR_LIT> ) ; bool Changed = false ; if ( L ) { for ( MachineLoop * I : * L ) Changed |= visitLoop ( I ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; } const MCInstrDesc & D = HII -> get ( Opc ) ; DebugLoc DL = B -> findBranchDebugLoc ( ) ; unsigned MuxR = MRI -> createVirtualRegister ( DRC ) ;

BuildMI ( * B , At , DL , D , MuxR ) . addReg ( PredR ) . addReg ( TR , <NUM_LIT> , TSR ) . addReg ( FR , <NUM_LIT> , FSR ) ;


<s> if ( T != FP . TrueB && T != FP . FalseB ) { assert ( ! SSB ) ; SSB = T ; } FP . SplitB -> removeSuccessor ( FP . SplitB -> succ_begin ( ) ) ; } if ( FP . JoinB ) { assert ( ! SSB || SSB == FP . JoinB ) ; BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , HII -> get ( <STR_LIT> ) ) . addMBB ( FP . JoinB ) ; FP . SplitB -> addSuccessor ( FP . JoinB ) ; } else { bool HasBranch = false ; if ( TSB ) { BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , HII -> get ( <STR_LIT> ) ) . addReg ( FP . PredR ) . addMBB ( TSB ) ; FP . SplitB -> addSuccessor ( TSB ) ; HasBranch = true ; } if ( FSB ) { const MCInstrDesc & D = HasBranch ? HII -> get ( <STR_LIT> ) : HII -> get ( <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , D ) ; if ( ! HasBranch ) MIB . addReg ( FP . PredR ) ; MIB . addMBB ( FSB ) ; FP . SplitB -> addSuccessor ( FSB ) ; }


<s> unsigned <ISA_LIT>EarlyIfConversion :: countPredicateDefs ( const MachineBasicBlock * B ) const { unsigned PredDefs = <NUM_LIT> ; for ( auto & MI : * B ) { for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned R = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; if ( MRI -> getRegClass ( R ) == & <STR_LIT> ) PredDefs ++ ; }


<s> MachineOperand & UO = PN -> getOperand ( <NUM_LIT> ) ; unsigned UseR = UO . getReg ( ) , UseSR = UO . getSubReg ( ) ; unsigned DefR = PN -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewR = UseR ; if ( UseSR ) { const DebugLoc & DL = PN -> getDebugLoc ( ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( DefR ) ; NewR = MRI -> createVirtualRegister ( RC ) ; NonPHI = BuildMI ( * B , NonPHI , DL , HII -> get ( TargetOpcode :: COPY ) , NewR ) . addReg ( UseR , <NUM_LIT> , UseSR ) ; }


<s> PredDefs += countPredicateDefs ( FP . JoinB ) ; } else { if ( FP . TrueB && FP . TrueB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * SB = * FP . TrueB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB , FP ) ; PredDefs += countPredicateDefs ( SB ) ; } if ( FP . FalseB && FP . FalseB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * SB = * FP . FalseB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB , FP ) ; PredDefs += countPredicateDefs ( SB ) ; } } DEBUG ( dbgs ( ) << <STR_LIT> << TotalPh << <STR_LIT> ) ; if ( TotalIn + TotalPh >= SizeLimit + Spare ) return false ;

DEBUG ( dbgs ( ) << <STR_LIT> << PredDefs << <STR_LIT> ) ;


<s> unsigned PredDefs = countPredicateDefs ( FP . SplitB ) ; if ( FP . JoinB ) { TotalPh = computePhiCost ( FP . JoinB , FP ) ; PredDefs += countPredicateDefs ( FP . JoinB ) ; } else { if ( FP . TrueB && FP . TrueB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * SB = * FP . TrueB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB , FP ) ; PredDefs += countPredicateDefs ( SB ) ; } if ( FP . FalseB && FP . FalseB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * SB = * FP . FalseB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB , FP ) ; PredDefs += countPredicateDefs ( SB ) ; } } DEBUG ( dbgs ( ) << <STR_LIT> << TotalPh << <STR_LIT> ) ; if ( TotalIn + TotalPh >= SizeLimit + Spare ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << PredDefs << <STR_LIT> ) ; if ( PredDefs > <NUM_LIT> ) return false ;


<s> if ( MI . isDebugValue ( ) ) continue ; if ( MI . isConditionalBranch ( ) ) return false ; unsigned Opc = MI . getOpcode ( ) ; bool IsJMP = ( Opc == <STR_LIT> ) ; if ( ! isPredicableStore ( & MI ) && ! IsJMP && ! isSafeToSpeculate ( & MI ) ) return false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned R = MO . getReg ( ) ;

if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ;


<s> if ( Opc != <STR_LIT> && Opc != <STR_LIT> ) return false ; unsigned PredR = T1I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineFunction :: iterator NextBI = std :: next ( MachineFunction :: iterator ( B ) ) ; MachineBasicBlock * NextB = ( NextBI != MFN -> end ( ) ) ? & * NextBI : nullptr ; MachineBasicBlock * T1B = T1I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; MachineBasicBlock :: const_iterator T2I = std :: next ( T1I ) ; assert ( T2I == B -> end ( ) || T2I -> getOpcode ( ) == <STR_LIT> ) ; MachineBasicBlock * T2B = ( T2I == B -> end ( ) ) ? NextB : T2I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( T1B == T2B ) { return false ; } if ( Opc == <STR_LIT> ) TB = T1B , FB = T2B ; else TB = T2B , FB = T1B ; if ( ! MDT -> properlyDominates ( B , TB ) || ! MDT -> properlyDominates ( B , FB ) ) return false ; unsigned TNP = TB -> pred_size ( ) , FNP = FB -> pred_size ( ) ; unsigned TNS = TB -> succ_size ( ) , FNS = FB -> succ_size ( ) ; bool TOk = ( TNP == <NUM_LIT> && TNS == <NUM_LIT> && MLI -> getLoopFor ( TB ) == L ) ; bool FOk = ( FNP == <NUM_LIT> && FNS == <NUM_LIT> && MLI -> getLoopFor ( FB ) == L ) ; if ( SkipExitBranches && MLI -> getLoopFor ( TB ) != MLI -> getLoopFor ( FB ) ) return false ; if ( ! TOk && ! FOk ) return false ; MachineBasicBlock * TSB = ( TNS > <NUM_LIT> ) ? * TB -> succ_begin ( ) : nullptr ; MachineBasicBlock * FSB = ( FNS > <NUM_LIT> ) ? * FB -> succ_begin ( ) : nullptr ; MachineBasicBlock * JB = nullptr ; if ( TOk ) { if ( FOk ) { if ( TSB == FSB ) JB = TSB ; } else { if ( TSB == FB ) JB = FB ; FB = nullptr ; }


<s> bool FOk = ( FNP == <NUM_LIT> && FNS == <NUM_LIT> && MLI -> getLoopFor ( FB ) == L ) ; if ( SkipExitBranches && MLI -> getLoopFor ( TB ) != MLI -> getLoopFor ( FB ) ) return false ; if ( ! TOk && ! FOk ) return false ; MachineBasicBlock * TSB = ( TNS > <NUM_LIT> ) ? * TB -> succ_begin ( ) : nullptr ; MachineBasicBlock * FSB = ( FNS > <NUM_LIT> ) ? * FB -> succ_begin ( ) : nullptr ; MachineBasicBlock * JB = nullptr ; if ( TOk ) { if ( FOk ) { if ( TSB == FSB ) JB = TSB ; } else { if ( TSB == FB ) JB = FB ; FB = nullptr ; } } else { if ( FSB == TB ) JB = TB ; TB = nullptr ; } if ( ( TB && isPreheader ( TB ) ) || ( FB && isPreheader ( FB ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << PrintMB ( TB ) << <STR_LIT> << PrintMB ( FB ) << <STR_LIT> ) ; return false ;


<s> eliminatePhis ( SuccB ) ; HII -> removeBranch ( * PredB ) ; PredB -> removeSuccessor ( SuccB ) ; PredB -> splice ( PredB -> end ( ) , SuccB , SuccB -> begin ( ) , SuccB -> end ( ) ) ; MachineBasicBlock :: succ_iterator I , E = SuccB -> succ_end ( ) ; for ( I = SuccB -> succ_begin ( ) ; I != E ; ++ I ) PredB -> addSuccessor ( * I ) ; PredB -> normalizeSuccProbs ( ) ; replacePhiEdges ( SuccB , PredB ) ; removeBlock ( SuccB ) ;

if ( ! TermOk ) PredB -> updateTerminator ( ) ;


<s> if ( HII -> isPostIncrement ( * MI ) ) { MIB . add ( * MOI ) ; ++ MOI ; } MIB . addReg ( PredR ) ; for ( const MachineOperand & MO : make_range ( MOI , MI -> operands_end ( ) ) ) MIB . add ( MO ) ; MachineInstr :: mmo_iterator MMOBegin = MI -> memoperands_begin ( ) ; MachineInstr :: mmo_iterator MMOEnd = MI -> memoperands_end ( ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MI -> eraseFromParent ( ) ; return ; } if ( Opc == <STR_LIT> ) { MachineBasicBlock * TB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; const MCInstrDesc & D = HII -> get ( IfTrue ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( * ToB , At , DL , D ) . addReg ( PredR ) . addMBB ( TB ) ;


<s> void <ISA_LIT>EarlyIfConversion :: replacePhiEdges ( MachineBasicBlock * OldB , MachineBasicBlock * NewB ) { for ( auto I = OldB -> succ_begin ( ) , E = OldB -> succ_end ( ) ; I != E ; ++ I ) { MachineBasicBlock * SB = * I ; MachineBasicBlock :: iterator P , N = SB -> getFirstNonPHI ( ) ; for ( P = SB -> begin ( ) ; P != N ; ++ P ) { MachineInstr & PN = * P ; for ( MachineOperand & MO : PN . operands ( ) ) if ( MO . isMBB ( ) && MO . getMBB ( ) == OldB ) MO . setMBB ( NewB ) ;


<s> for ( P = SB -> begin ( ) ; P != N ; ++ P ) { MachineInstr & PN = * P ; for ( MachineOperand & MO : PN . operands ( ) ) if ( MO . isMBB ( ) && MO . getMBB ( ) == OldB ) MO . setMBB ( NewB ) ; }


<s> MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MBPI = Enable<ISA_LIT>BP ? & getAnalysis < MachineBranchProbabilityInfo > ( ) : nullptr ; Deleted . clear ( ) ;


<s> else if ( BO . getMBB ( ) == FP . FalseB ) FR = RO . getReg ( ) , FSR = RO . getSubReg ( ) ; else continue ; PN -> RemoveOperand ( i + <NUM_LIT> ) ; PN -> RemoveOperand ( i ) ; } if ( TR == <NUM_LIT> ) TR = SR , TSR = SSR ; else if ( FR == <NUM_LIT> ) FR = SR , FSR = SSR ; assert ( TR || FR ) ; unsigned MuxR = <NUM_LIT> , MuxSR = <NUM_LIT> ; if ( TR && FR ) { unsigned DR = PN -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( DR ) ;

MuxR = buildMux ( FP . SplitB , FP . SplitB -> getFirstTerminator ( ) , RC , FP . PredR , TR , TSR , FR , FSR ) ;


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; const MachineInstr * DefI = MRI -> getVRegDef ( R ) ; assert ( DefI && <STR_LIT> ) ; if ( DefI -> isImplicitDef ( ) ) return true ;


<s> bool <ISA_LIT>EarlyIfConversion :: usesUndefVReg ( const MachineInstr * MI ) const { for ( const MachineOperand & MO : MI -> operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isUse ( ) ) continue ; unsigned R = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; const MachineInstr * DefI = MRI -> getVRegDef ( R ) ;


<s> MachineBasicBlock * HB = L ? L -> getHeader ( ) : nullptr ; DEBUG ( ( L ? dbgs ( ) << <STR_LIT> << PrintMB ( HB ) : dbgs ( ) << <STR_LIT> ) << <STR_LIT> ) ; bool Changed = false ; if ( L ) { for ( MachineLoop :: iterator I = L -> begin ( ) , E = L -> end ( ) ; I != E ; ++ I ) Changed |= visitLoop ( * I ) ;


<s> DebugLoc DL = B -> findBranchDebugLoc ( ) ; unsigned MuxR = MRI -> createVirtualRegister ( DRC ) ; BuildMI ( * B , At , DL , D , MuxR ) . addReg ( PredR ) . addReg ( TR , <NUM_LIT> , TSR ) . addReg ( FR , <NUM_LIT> , FSR ) ; return MuxR ;


<s> if ( TSB -> pred_size ( ) != <NUM_LIT> ) return false ; } auto TotalCount = [ ] ( const MachineBasicBlock * B , unsigned & Spare ) { if ( ! B ) return <NUM_LIT> ; unsigned T = std :: count_if ( B -> begin ( ) , B -> getFirstTerminator ( ) , [ ] ( const MachineInstr & MI ) { return ! MI . isMetaInstruction ( ) ; } ) ; if ( T < HEXAGON_PACKET_SIZE ) Spare += HEXAGON_PACKET_SIZE - T ; return T ; } ; unsigned Spare = <NUM_LIT> ; unsigned TotalIn = TotalCount ( FP . TrueB , Spare ) + TotalCount ( FP . FalseB , Spare ) ; DEBUG ( dbgs ( ) << <STR_LIT> << TotalIn << <STR_LIT> << Spare << <STR_LIT> ) ; if ( TotalIn >= SizeLimit + Spare ) return false ; unsigned TotalPh = <NUM_LIT> ; unsigned PredDefs = countPredicateDefs ( FP . SplitB ) ; if ( FP . JoinB ) { TotalPh = computePhiCost ( FP . JoinB , FP ) ; PredDefs += countPredicateDefs ( FP . JoinB ) ; } else { if ( FP . TrueB && FP . TrueB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * SB = * FP . TrueB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB , FP ) ; PredDefs += countPredicateDefs ( SB ) ; } if ( FP . FalseB && FP . FalseB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * SB = * FP . FalseB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB , FP ) ; PredDefs += countPredicateDefs ( SB ) ; } } DEBUG ( dbgs ( ) << <STR_LIT> << TotalPh << <STR_LIT> ) ; if ( TotalIn + TotalPh >= SizeLimit + Spare ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << PredDefs << <STR_LIT> ) ; if ( PredDefs > <NUM_LIT> ) return false ;


<s> } auto TotalCount = [ ] ( const MachineBasicBlock * B , unsigned & Spare ) { if ( ! B ) return <NUM_LIT> ; unsigned T = std :: count_if ( B -> begin ( ) , B -> getFirstTerminator ( ) , [ ] ( const MachineInstr & MI ) { return ! MI . isMetaInstruction ( ) ; } ) ; if ( T < HEXAGON_PACKET_SIZE ) Spare += HEXAGON_PACKET_SIZE - T ; return T ; } ; unsigned Spare = <NUM_LIT> ; unsigned TotalIn = TotalCount ( FP . TrueB , Spare ) + TotalCount ( FP . FalseB , Spare ) ; DEBUG ( dbgs ( ) << <STR_LIT> << TotalIn << <STR_LIT> << Spare << <STR_LIT> ) ; if ( TotalIn >= SizeLimit + Spare ) return false ; unsigned TotalPh = <NUM_LIT> ; unsigned PredDefs = countPredicateDefs ( FP . SplitB ) ; if ( FP . JoinB ) { TotalPh = computePhiCost ( FP . JoinB , FP ) ; PredDefs += countPredicateDefs ( FP . JoinB ) ; } else { if ( FP . TrueB && FP . TrueB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * SB = * FP . TrueB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB , FP ) ; PredDefs += countPredicateDefs ( SB ) ; } if ( FP . FalseB && FP . FalseB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * SB = * FP . FalseB -> succ_begin ( ) ;


<s> if ( B -> isEHPad ( ) || B -> hasAddressTaken ( ) ) return false ; if ( B -> succ_size ( ) == <NUM_LIT> ) return false ; for ( auto & MI : * B ) { if ( MI . isDebugValue ( ) ) continue ; if ( MI . isConditionalBranch ( ) ) return false ; unsigned Opc = MI . getOpcode ( ) ; bool IsJMP = ( Opc == <STR_LIT> ) ; if ( ! isPredicableStore ( & MI ) && ! IsJMP && ! isSafeToSpeculate ( & MI ) ) return false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned R = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; switch ( MRI -> getRegClass ( R ) -> getID ( ) ) { case <STR_LIT> :


<s> if ( IDN ) { MachineBasicBlock * IDB = IDN -> getBlock ( ) ; using GTN = GraphTraits < MachineDomTreeNode * > ; using DTNodeVectType = SmallVector < MachineDomTreeNode * , <NUM_LIT> > ; DTNodeVectType Cn ( GTN :: child_begin ( N ) , GTN :: child_end ( N ) ) ; for ( DTNodeVectType :: iterator I = Cn . begin ( ) , E = Cn . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * SB = ( * I ) -> getBlock ( ) ; MDT -> changeImmediateDominator ( SB , IDB ) ; } } while ( B -> succ_size ( ) > <NUM_LIT> ) B -> removeSuccessor ( B -> succ_begin ( ) ) ; for ( auto I = B -> pred_begin ( ) , E = B -> pred_end ( ) ; I != E ; ++ I ) ( * I ) -> removeSuccessor ( B , true ) ; Deleted . insert ( B ) ; MDT -> eraseNode ( B ) ;


<s> bool Changed = false ; MachineDomTreeNode * N = MDT -> getNode ( B ) ; using GTN = GraphTraits < MachineDomTreeNode * > ; using DTNodeVectType = SmallVector < MachineDomTreeNode * , <NUM_LIT> > ; DTNodeVectType Cn ( GTN :: child_begin ( N ) , GTN :: child_end ( N ) ) ; for ( DTNodeVectType :: iterator I = Cn . begin ( ) , E = Cn . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * SB = ( * I ) -> getBlock ( ) ; if ( ! Deleted . count ( SB ) ) Changed |= visitBlock ( SB , L ) ; } if ( MLI -> getLoopFor ( B ) != L ) return Changed ; FlowPattern FP ; if ( ! matchFlowPattern ( B , L , FP ) ) return Changed ; if ( ! isValid ( FP ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return Changed ; } if ( ! isProfitable ( FP ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return Changed ; } convert ( FP ) ; simplifyFlowGraph ( FP ) ; return true ;


<s> unsigned <ISA_LIT>EarlyIfConversion :: computePhiCost ( MachineBasicBlock * B ) const { assert ( B -> pred_size ( ) <= <NUM_LIT> ) ; if ( B -> pred_size ( ) < <NUM_LIT> ) return <NUM_LIT> ; unsigned Cost = <NUM_LIT> ; MachineBasicBlock :: const_iterator I , E = B -> getFirstNonPHI ( ) ; for ( I = B -> begin ( ) ; I != E ; ++ I ) {

const MachineOperand & RO1 = I -> getOperand ( <NUM_LIT> ) ;


<s> if ( B -> succ_size ( ) == <NUM_LIT> ) return false ; for ( auto & MI : * B ) { if ( MI . isDebugValue ( ) ) continue ; if ( MI . isConditionalBranch ( ) ) return false ; unsigned Opc = MI . getOpcode ( ) ; bool IsJMP = ( Opc == <STR_LIT> ) ; if ( ! isPredicableStore ( & MI ) && ! IsJMP && ! isSafeToSpeculate ( & MI ) ) return false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned R = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; if ( MRI -> getRegClass ( R ) != & <STR_LIT> ) continue ; for ( auto U = MRI -> use_begin ( R ) ; U != MRI -> use_end ( ) ; ++ U ) if ( U -> getParent ( ) -> isPHI ( ) ) return false ; }


<s> bool <ISA_LIT>EarlyIfConversion :: isValidCandidate ( const MachineBasicBlock * B ) const { if ( ! B ) return true ; if ( B -> isEHPad ( ) || B -> hasAddressTaken ( ) ) return false ; if ( B -> succ_size ( ) == <NUM_LIT> ) return false ; for ( auto & MI : * B ) { if ( MI . isDebugValue ( ) ) continue ; if ( MI . isConditionalBranch ( ) ) return false ; unsigned Opc = MI . getOpcode ( ) ; bool IsJMP = ( Opc == <STR_LIT> ) ; if ( ! isPredicableStore ( & MI ) && ! IsJMP && ! isSafeToSpeculate ( & MI ) ) return false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned R = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; if ( MRI -> getRegClass ( R ) != & <STR_LIT> ) continue ; for ( auto U = MRI -> use_begin ( R ) ; U != MRI -> use_end ( ) ; ++ U ) if ( U -> getParent ( ) -> isPHI ( ) ) return false ;


<s> MachineBasicBlock * NextB = ( NextBI != MFN -> end ( ) ) ? & * NextBI : nullptr ; MachineBasicBlock * T1B = T1I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; MachineBasicBlock :: const_iterator T2I = std :: next ( T1I ) ; assert ( T2I == B -> end ( ) || T2I -> getOpcode ( ) == <STR_LIT> ) ; MachineBasicBlock * T2B = ( T2I == B -> end ( ) ) ? NextB : T2I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( T1B == T2B ) { return false ; } if ( MLI -> getLoopFor ( T1B ) != L || MLI -> getLoopFor ( T2B ) != L ) return false ; if ( Opc == <STR_LIT> ) TB = T1B , FB = T2B ; else TB = T2B , FB = T1B ; if ( ! MDT -> properlyDominates ( B , TB ) || ! MDT -> properlyDominates ( B , FB ) ) return false ; unsigned TNP = TB -> pred_size ( ) , FNP = FB -> pred_size ( ) ; unsigned TNS = TB -> succ_size ( ) , FNS = FB -> succ_size ( ) ; bool TOk = ( TNP == <NUM_LIT> ) && ( TNS == <NUM_LIT> ) ; bool FOk = ( FNP == <NUM_LIT> ) && ( FNS == <NUM_LIT> ) ; if ( ! TOk && ! FOk ) return false ; MachineBasicBlock * TSB = ( TNS > <NUM_LIT> ) ? * TB -> succ_begin ( ) : nullptr ; MachineBasicBlock * FSB = ( FNS > <NUM_LIT> ) ? * FB -> succ_begin ( ) : nullptr ; MachineBasicBlock * JB = nullptr ; if ( TOk ) { if ( FOk ) { if ( TSB == FSB ) JB = TSB ; } else { if ( TSB == FB ) { JB = FB ; FB = nullptr ; }


<s> } MIB . addReg ( PredR ) ; for ( const MachineOperand & MO : make_range ( MOI , MI -> operands_end ( ) ) ) MIB . addOperand ( MO ) ; MachineInstr :: mmo_iterator MMOBegin = MI -> memoperands_begin ( ) ; MachineInstr :: mmo_iterator MMOEnd = MI -> memoperands_end ( ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MI -> eraseFromParent ( ) ; return ; } if ( Opc == <STR_LIT> ) { MachineBasicBlock * TB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; const MCInstrDesc & D = HII -> get ( IfTrue ? <STR_LIT> : <STR_LIT> ) ;

BuildMI ( * ToB , At , DL , D ) . addReg ( PredR ) . addMBB ( TB ) ;


<s> unsigned TR = <NUM_LIT> , TSR = <NUM_LIT> , FR = <NUM_LIT> , FSR = <NUM_LIT> , SR = <NUM_LIT> , SSR = <NUM_LIT> ; for ( int i = PN -> getNumOperands ( ) - <NUM_LIT> ; i > <NUM_LIT> ; i -= <NUM_LIT> ) { const MachineOperand & RO = PN -> getOperand ( i ) , & BO = PN -> getOperand ( i + <NUM_LIT> ) ; if ( BO . getMBB ( ) == FP . SplitB ) SR = RO . getReg ( ) , SSR = RO . getSubReg ( ) ; else if ( BO . getMBB ( ) == FP . TrueB ) TR = RO . getReg ( ) , TSR = RO . getSubReg ( ) ; else if ( BO . getMBB ( ) == FP . FalseB ) FR = RO . getReg ( ) , FSR = RO . getSubReg ( ) ; else continue ; PN -> RemoveOperand ( i + <NUM_LIT> ) ; PN -> RemoveOperand ( i ) ; } if ( TR == <NUM_LIT> ) TR = SR , TSR = SSR ; else if ( FR == <NUM_LIT> ) FR = SR , FSR = SSR ; assert ( TR && FR ) ; using namespace <ISA_LIT> ; unsigned DR = PN -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( DR ) ; unsigned Opc = <NUM_LIT> ;

if ( RC == & IntRegsRegClass ) Opc = C2_mux ;


<s> else continue ; PN -> RemoveOperand ( i + <NUM_LIT> ) ; PN -> RemoveOperand ( i ) ; } if ( TR == <NUM_LIT> ) TR = SR , TSR = SSR ; else if ( FR == <NUM_LIT> ) FR = SR , FSR = SSR ; assert ( TR && FR ) ; using namespace <ISA_LIT> ; unsigned DR = PN -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( DR ) ; unsigned Opc = <NUM_LIT> ; if ( RC == & IntRegsRegClass ) Opc = C2_mux ; else if ( RC == & DoubleRegsRegClass ) Opc = PS_pselect ; else if ( RC == & VectorRegsRegClass ) Opc = PS_vselect ; else if ( RC == & VecDblRegsRegClass ) Opc = PS_wselect ; else if ( RC == & VectorRegs128BRegClass ) Opc = PS_vselect_128B ; else if ( RC == & VecDblRegs128BRegClass ) Opc = PS_wselect_128B ; else llvm_unreachable ( <STR_LIT> ) ;

const MCInstrDesc & D = HII -> get ( Opc ) ;


<s> for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; Register R = MO . getReg ( ) ; if ( ! Register :: isVirtualRegister ( R ) ) continue ;


<s> } ; unsigned Spare = <NUM_LIT> ; unsigned TotalIn = TotalCount ( FP . TrueB , Spare ) + TotalCount ( FP . FalseB , Spare ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TotalIn << <STR_LIT> << Spare << <STR_LIT> ) ; if ( TotalIn >= SizeLimit + Spare ) return false ; unsigned TotalPh = <NUM_LIT> ; unsigned PredDefs = countPredicateDefs ( FP . SplitB ) ; if ( FP . JoinB ) { TotalPh = computePhiCost ( FP . JoinB , FP ) ; PredDefs += countPredicateDefs ( FP . JoinB ) ; } else { if ( FP . TrueB && FP . TrueB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * SB = * FP . TrueB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB , FP ) ; PredDefs += countPredicateDefs ( SB ) ; } if ( FP . FalseB && FP . FalseB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * SB = * FP . FalseB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB , FP ) ;


<s> if ( MI -> hasUnmodeledSideEffects ( ) ) return false ;

if ( MI -> getOpcode ( ) == TargetOpcode :: LIFETIME_END ) return false ;


<s> bool <ISA_LIT>EarlyIfConversion :: isSafeToSpeculate ( const MachineInstr * MI ) const { if ( MI -> mayLoad ( ) || MI -> mayStore ( ) ) return false ;

if ( MI -> isCall ( ) || MI -> isBarrier ( ) || MI -> isBranch ( ) ) return false ;


<s> if ( ! B ) return true ; if ( B -> isEHPad ( ) || B -> hasAddressTaken ( ) ) return false ; if ( B -> succ_size ( ) == <NUM_LIT> ) return false ; for ( auto & MI : * B ) { if ( MI . isDebugInstr ( ) ) continue ; if ( MI . isConditionalBranch ( ) ) return false ; unsigned Opc = MI . getOpcode ( ) ; bool IsJMP = ( Opc == <STR_LIT> ) ;

if ( ! isPredicableStore ( & MI ) && ! IsJMP && ! isSafeToSpeculate ( & MI ) ) return false ;


<s> MachineBasicBlock * TB = nullptr , * FB = nullptr ; MachineBasicBlock :: const_iterator T1I = B -> getFirstTerminator ( ) ; if ( T1I == B -> end ( ) ) return false ; unsigned Opc = T1I -> getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> ) return false ; Register PredR = T1I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineFunction :: iterator NextBI = std :: next ( MachineFunction :: iterator ( B ) ) ; MachineBasicBlock * NextB = ( NextBI != MFN -> end ( ) ) ? & * NextBI : nullptr ; MachineBasicBlock * T1B = T1I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; MachineBasicBlock :: const_iterator T2I = std :: next ( T1I ) ; assert ( T2I == B -> end ( ) || T2I -> getOpcode ( ) == <STR_LIT> ) ; MachineBasicBlock * T2B = ( T2I == B -> end ( ) ) ? NextB : T2I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( T1B == T2B ) { return false ; } if ( Opc == <STR_LIT> ) TB = T1B , FB = T2B ; else TB = T2B , FB = T1B ; if ( ! MDT -> properlyDominates ( B , TB ) || ! MDT -> properlyDominates ( B , FB ) ) return false ; unsigned TNP = TB -> pred_size ( ) , FNP = FB -> pred_size ( ) ; unsigned TNS = TB -> succ_size ( ) , FNS = FB -> succ_size ( ) ; bool TOk = ( TNP == <NUM_LIT> && TNS == <NUM_LIT> && MLI -> getLoopFor ( TB ) == L ) ; bool FOk = ( FNP == <NUM_LIT> && FNS == <NUM_LIT> && MLI -> getLoopFor ( FB ) == L ) ; if ( SkipExitBranches && MLI -> getLoopFor ( TB ) != MLI -> getLoopFor ( FB ) ) return false ; if ( ! TOk && ! FOk ) return false ;

MachineBasicBlock * TSB = ( TNS > <NUM_LIT> ) ? * TB -> succ_begin ( ) : nullptr ;


<s> return false ; } if ( Opc == <STR_LIT> ) TB = T1B , FB = T2B ; else TB = T2B , FB = T1B ; if ( ! MDT -> properlyDominates ( B , TB ) || ! MDT -> properlyDominates ( B , FB ) ) return false ; unsigned TNP = TB -> pred_size ( ) , FNP = FB -> pred_size ( ) ; unsigned TNS = TB -> succ_size ( ) , FNS = FB -> succ_size ( ) ; bool TOk = ( TNP == <NUM_LIT> && TNS == <NUM_LIT> && MLI -> getLoopFor ( TB ) == L ) ; bool FOk = ( FNP == <NUM_LIT> && FNS == <NUM_LIT> && MLI -> getLoopFor ( FB ) == L ) ; if ( SkipExitBranches && MLI -> getLoopFor ( TB ) != MLI -> getLoopFor ( FB ) ) return false ; if ( ! TOk && ! FOk ) return false ; MachineBasicBlock * TSB = ( TNS > <NUM_LIT> ) ? * TB -> succ_begin ( ) : nullptr ; MachineBasicBlock * FSB = ( FNS > <NUM_LIT> ) ? * FB -> succ_begin ( ) : nullptr ; MachineBasicBlock * JB = nullptr ; if ( TOk ) { if ( FOk ) { if ( TSB == FSB ) JB = TSB ; } else { if ( TSB == FB ) JB = FB ; FB = nullptr ; } } else { if ( FSB == TB ) JB = TB ; TB = nullptr ; } if ( ( TB && isPreheader ( TB ) ) || ( FB && isPreheader ( FB ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << PrintMB ( TB ) << <STR_LIT> << PrintMB ( FB ) << <STR_LIT> ) ; return false ; } FP = FlowPattern ( B , PredR , TB , FB , JB ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << PrintFP ( FP , * TRI ) << <STR_LIT> ) ; return true ;


<s> eliminatePhis ( SuccB ) ; HII -> removeBranch ( * PredB ) ; PredB -> removeSuccessor ( SuccB ) ;

PredB -> splice ( PredB -> end ( ) , SuccB , SuccB -> begin ( ) , SuccB -> end ( ) ) ;


<s> MDT -> changeImmediateDominator ( SB , IDB ) ; } } while ( B -> succ_size ( ) > <NUM_LIT> ) B -> removeSuccessor ( B -> succ_begin ( ) ) ; for ( auto I = B -> pred_begin ( ) , E = B -> pred_end ( ) ; I != E ; ++ I ) ( * I ) -> removeSuccessor ( B , true ) ; Deleted . insert ( B ) ; MDT -> eraseNode ( B ) ;


<s> for ( const MachineOperand & MO : MI -> operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isUse ( ) ) continue ; Register R = MO . getReg ( ) ; if ( ! Register :: isVirtualRegister ( R ) ) continue ; const MachineInstr * DefI = MRI -> getVRegDef ( R ) ; assert ( DefI && <STR_LIT> ) ; if ( DefI -> isImplicitDef ( ) ) return true ; }


<s> default : llvm_unreachable ( <STR_LIT> ) ; } const MCInstrDesc & D = HII -> get ( Opc ) ; DebugLoc DL = B -> findBranchDebugLoc ( ) ; unsigned MuxR = MRI -> createVirtualRegister ( DRC ) ; BuildMI ( * B , At , DL , D , MuxR ) . addReg ( PredR ) . addReg ( TR , <NUM_LIT> , TSR ) . addReg ( FR , <NUM_LIT> , FSR ) ; return MuxR ;


<s> MachineBasicBlock * TB = nullptr , * FB = nullptr ; MachineBasicBlock :: const_iterator T1I = B -> getFirstTerminator ( ) ; if ( T1I == B -> end ( ) ) return false ; unsigned Opc = T1I -> getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> ) return false ; unsigned PredR = T1I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineFunction :: iterator NextBI = std :: next ( MachineFunction :: iterator ( B ) ) ; MachineBasicBlock * NextB = ( NextBI != MFN -> end ( ) ) ? & * NextBI : nullptr ; MachineBasicBlock * T1B = T1I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; MachineBasicBlock :: const_iterator T2I = std :: next ( T1I ) ; assert ( T2I == B -> end ( ) || T2I -> getOpcode ( ) == <STR_LIT> ) ; MachineBasicBlock * T2B = ( T2I == B -> end ( ) ) ? NextB : T2I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( T1B == T2B ) { return false ; } if ( Opc == <STR_LIT> ) TB = T1B , FB = T2B ; else TB = T2B , FB = T1B ; if ( ! MDT -> properlyDominates ( B , TB ) || ! MDT -> properlyDominates ( B , FB ) ) return false ; unsigned TNP = TB -> pred_size ( ) , FNP = FB -> pred_size ( ) ; unsigned TNS = TB -> succ_size ( ) , FNS = FB -> succ_size ( ) ; bool TOk = ( TNP == <NUM_LIT> && TNS == <NUM_LIT> && MLI -> getLoopFor ( TB ) == L ) ; bool FOk = ( FNP == <NUM_LIT> && FNS == <NUM_LIT> && MLI -> getLoopFor ( FB ) == L ) ; if ( SkipExitBranches && MLI -> getLoopFor ( TB ) != MLI -> getLoopFor ( FB ) ) return false ; if ( ! TOk && ! FOk ) return false ; MachineBasicBlock * TSB = ( TNS > <NUM_LIT> ) ? * TB -> succ_begin ( ) : nullptr ; MachineBasicBlock * FSB = ( FNS > <NUM_LIT> ) ? * FB -> succ_begin ( ) : nullptr ; MachineBasicBlock * JB = nullptr ; if ( TOk ) { if ( FOk ) { if ( TSB == FSB ) JB = TSB ; } else { if ( TSB == FB ) JB = FB ;


<s> return false ; } if ( Opc == <STR_LIT> ) TB = T1B , FB = T2B ; else TB = T2B , FB = T1B ; if ( ! MDT -> properlyDominates ( B , TB ) || ! MDT -> properlyDominates ( B , FB ) ) return false ; unsigned TNP = TB -> pred_size ( ) , FNP = FB -> pred_size ( ) ; unsigned TNS = TB -> succ_size ( ) , FNS = FB -> succ_size ( ) ; bool TOk = ( TNP == <NUM_LIT> && TNS == <NUM_LIT> && MLI -> getLoopFor ( TB ) == L ) ; bool FOk = ( FNP == <NUM_LIT> && FNS == <NUM_LIT> && MLI -> getLoopFor ( FB ) == L ) ; if ( SkipExitBranches && MLI -> getLoopFor ( TB ) != MLI -> getLoopFor ( FB ) ) return false ; if ( ! TOk && ! FOk ) return false ; MachineBasicBlock * TSB = ( TNS > <NUM_LIT> ) ? * TB -> succ_begin ( ) : nullptr ; MachineBasicBlock * FSB = ( FNS > <NUM_LIT> ) ? * FB -> succ_begin ( ) : nullptr ; MachineBasicBlock * JB = nullptr ; if ( TOk ) { if ( FOk ) { if ( TSB == FSB ) JB = TSB ; } else { if ( TSB == FB ) JB = FB ; FB = nullptr ; } } else { if ( FSB == TB ) JB = TB ; TB = nullptr ;


<s> MachineInstr * PN = & * I ; unsigned TR = <NUM_LIT> , TSR = <NUM_LIT> , FR = <NUM_LIT> , FSR = <NUM_LIT> , SR = <NUM_LIT> , SSR = <NUM_LIT> ; for ( int i = PN -> getNumOperands ( ) - <NUM_LIT> ; i > <NUM_LIT> ; i -= <NUM_LIT> ) { const MachineOperand & RO = PN -> getOperand ( i ) , & BO = PN -> getOperand ( i + <NUM_LIT> ) ; if ( BO . getMBB ( ) == FP . SplitB ) SR = RO . getReg ( ) , SSR = RO . getSubReg ( ) ; else if ( BO . getMBB ( ) == FP . TrueB ) TR = RO . getReg ( ) , TSR = RO . getSubReg ( ) ; else if ( BO . getMBB ( ) == FP . FalseB ) FR = RO . getReg ( ) , FSR = RO . getSubReg ( ) ; else continue ; PN -> removeOperand ( i + <NUM_LIT> ) ;


<s> if ( B -> pred_size ( ) < <NUM_LIT> ) return <NUM_LIT> ; unsigned Cost = <NUM_LIT> ; for ( const MachineInstr & MI : * B ) { if ( ! MI . isPHI ( ) ) break ; SmallVector < unsigned , <NUM_LIT> > Inc ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; i += <NUM_LIT> ) { const MachineBasicBlock * BB = MI . getOperand ( i + <NUM_LIT> ) . getMBB ( ) ; if ( BB == FP . SplitB || BB == FP . TrueB || BB == FP . FalseB ) Inc . push_back ( i ) ;


<s> if ( Inc . size ( ) < <NUM_LIT> ) continue ; const MachineOperand & RA = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & RB = MI . getOperand ( <NUM_LIT> ) ; assert ( RA . isReg ( ) && RB . isReg ( ) ) ; if ( RA . getSubReg ( ) != <NUM_LIT> || RB . getSubReg ( ) != <NUM_LIT> ) { Cost ++ ; continue ; } const MachineInstr * Def1 = MRI -> getVRegDef ( RA . getReg ( ) ) ; const MachineInstr * Def3 = MRI -> getVRegDef ( RB . getReg ( ) ) ; if ( ! HII -> isPredicable ( * Def1 ) || ! HII -> isPredicable ( * Def3 ) ) Cost ++ ; }


<s> SSB = T ; } FP . SplitB -> removeSuccessor ( FP . SplitB -> succ_begin ( ) ) ; } if ( FP . JoinB ) { assert ( ! SSB || SSB == FP . JoinB ) ; BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , HII -> get ( <STR_LIT> ) ) . addMBB ( FP . JoinB ) ; FP . SplitB -> addSuccessor ( FP . JoinB ) ; } else { bool HasBranch = false ; if ( TSB ) { BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , HII -> get ( <STR_LIT> ) ) . addReg ( FP . PredR ) . addMBB ( TSB ) ; FP . SplitB -> addSuccessor ( TSB ) ; HasBranch = true ; } if ( FSB ) { const MCInstrDesc & D = HasBranch ? HII -> get ( <STR_LIT> ) : HII -> get ( <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , D ) ; if ( ! HasBranch ) MIB . addReg ( FP . PredR ) ; MIB . addMBB ( FSB ) ; FP . SplitB -> addSuccessor ( FSB ) ; } if ( SSB ) { BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , HII -> get ( <STR_LIT> ) ) . addMBB ( SSB ) ; FP . SplitB -> addSuccessor ( SSB ) ; }


<s> unsigned PredDefs = <NUM_LIT> ; for ( auto & MI : * B ) { for ( const MachineOperand & MO : MI . operands ( ) ) {

if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ;


<s> void <ISA_LIT>EarlyIfConversion :: eliminatePhis ( MachineBasicBlock * B ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << PrintMB ( B ) << <STR_LIT> ) ; MachineBasicBlock :: iterator I , NextI , NonPHI = B -> getFirstNonPHI ( ) ; for ( I = B -> begin ( ) ; I != NonPHI ; I = NextI ) { NextI = std :: next ( I ) ; MachineInstr * PN = & * I ; assert ( PN -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand & UO = PN -> getOperand ( <NUM_LIT> ) ; Register UseR = UO . getReg ( ) , UseSR = UO . getSubReg ( ) ;

Register DefR = PN -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> unsigned <ISA_LIT>EarlyIfConversion :: getCondStoreOpcode ( unsigned Opc , bool IfTrue ) const { return HII -> getCondOpcode ( Opc , ! IfTrue ) ;


<s> return HII -> getCondOpcode ( Opc , ! IfTrue ) ;


<s> StringRef getPassName ( ) const override {


<s> <ISA_LIT>EarlyIfConversion ( ) : MachineFunctionPass ( ID ) {


<s> return RC == & <STR_LIT> || RC == & <STR_LIT> ;


<s> bool <ISA_LIT>EarlyIfConversion :: isPreheader ( const MachineBasicBlock * B ) const { if ( B -> succ_size ( ) != <NUM_LIT> ) return false ; MachineBasicBlock * SB = * B -> succ_begin ( ) ;

MachineLoop * L = MLI -> getLoopFor ( SB ) ;


<s> MachineBasicBlock * SB = * B -> succ_begin ( ) ; MachineLoop * L = MLI -> getLoopFor ( SB ) ;

return L && SB == L -> getHeader ( ) && MDT -> dominates ( B , SB ) ;


<s> if ( MBPI && FP . TrueB && ! FP . FalseB && ( MBPI -> getEdgeProbability ( FP . SplitB , FP . TrueB ) < JumpProb || MBPI -> getEdgeProbability ( FP . SplitB , FP . TrueB ) > Prob ) ) return false ; if ( MBPI && ! FP . TrueB && FP . FalseB && ( MBPI -> getEdgeProbability ( FP . SplitB , FP . FalseB ) < JumpProb || MBPI -> getEdgeProbability ( FP . SplitB , FP . FalseB ) > Prob ) ) return false ; if ( FP . TrueB && FP . FalseB ) { if ( MBPI ) { if ( MBPI -> getEdgeProbability ( FP . SplitB , FP . TrueB ) > Prob ) return false ; if ( MBPI -> getEdgeProbability ( FP . SplitB , FP . FalseB ) > Prob ) return false ; } MachineBasicBlock * TSB = * FP . TrueB -> succ_begin ( ) ; MachineBasicBlock * FSB = * FP . FalseB -> succ_begin ( ) ; if ( TSB != FSB ) return false ; if ( TSB -> pred_size ( ) != <NUM_LIT> ) return false ; } auto TotalCount = [ ] ( const MachineBasicBlock * B , unsigned & Spare ) { if ( ! B ) return <NUM_LIT> ; unsigned T = std :: count_if ( B -> begin ( ) , B -> getFirstTerminator ( ) , [ ] ( const MachineInstr & MI ) { return ! MI . isMetaInstruction ( ) ; } ) ; if ( T < HEXAGON_PACKET_SIZE ) Spare += HEXAGON_PACKET_SIZE - T ; return T ; } ; unsigned Spare = <NUM_LIT> ; unsigned TotalIn = TotalCount ( FP . TrueB , Spare ) + TotalCount ( FP . FalseB , Spare ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TotalIn << <STR_LIT> << Spare << <STR_LIT> ) ; if ( TotalIn >= SizeLimit + Spare ) return false ; unsigned TotalPh = <NUM_LIT> ; unsigned PredDefs = countPredicateDefs ( FP . SplitB ) ; if ( FP . JoinB ) { TotalPh = computePhiCost ( FP . JoinB , FP ) ; PredDefs += countPredicateDefs ( FP . JoinB ) ; } else { if ( FP . TrueB && ! FP . TrueB -> succ_empty ( ) ) { MachineBasicBlock * SB = * FP . TrueB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB , FP ) ; PredDefs += countPredicateDefs ( SB ) ; } if ( FP . FalseB && ! FP . FalseB -> succ_empty ( ) ) { MachineBasicBlock * SB = * FP . FalseB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB , FP ) ; PredDefs += countPredicateDefs ( SB ) ; } }

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TotalPh << <STR_LIT> ) ;


<s> if ( MI -> hasUnmodeledSideEffects ( ) ) return false ;


<s> bool <ISA_LIT>EarlyIfConversion :: isSafeToSpeculate ( const MachineInstr * MI ) const { if ( MI -> mayLoadOrStore ( ) ) return false ; if ( MI -> isCall ( ) || MI -> isBarrier ( ) || MI -> isBranch ( ) ) return false ; if ( MI -> hasUnmodeledSideEffects ( ) ) return false ; if ( MI -> getOpcode ( ) == TargetOpcode :: LIFETIME_END ) return false ;


<s> if ( ! MI . isPHI ( ) ) break ; if ( usesUndefVReg ( & MI ) ) return false ; Register DefR = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isPredicate ( DefR ) ) return false ; } }


<s> bool <ISA_LIT>EarlyIfConversion :: isValid ( const FlowPattern & FP ) const { if ( hasEHLabel ( FP . SplitB ) ) return false ; if ( FP . TrueB && ! isValidCandidate ( FP . TrueB ) ) return false ; if ( FP . FalseB && ! isValidCandidate ( FP . FalseB ) ) return false ; if ( FP . JoinB ) { const MachineBasicBlock & B = * FP . JoinB ; for ( auto & MI : B ) { if ( ! MI . isPHI ( ) ) break ; if ( usesUndefVReg ( & MI ) ) return false ; Register DefR = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;

if ( isPredicate ( DefR ) ) return false ;


<s> unsigned Opc = MI . getOpcode ( ) ; bool IsJMP = ( Opc == <STR_LIT> ) ; if ( ! isPredicableStore ( & MI ) && ! IsJMP && ! isSafeToSpeculate ( & MI ) ) return false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; Register R = MO . getReg ( ) ;


<s> bool IsJMP = ( Opc == <STR_LIT> ) ; if ( ! isPredicableStore ( & MI ) && ! IsJMP && ! isSafeToSpeculate ( & MI ) ) return false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; Register R = MO . getReg ( ) ; if ( ! R . isVirtual ( ) ) continue ; if ( ! isPredicate ( R ) ) continue ; for ( auto U = MRI -> use_begin ( R ) ; U != MRI -> use_end ( ) ; ++ U ) if ( U -> getParent ( ) -> isPHI ( ) ) return false ; }


<s> eliminatePhis ( SuccB ) ; HII -> removeBranch ( * PredB ) ; PredB -> removeSuccessor ( SuccB ) ; PredB -> splice ( PredB -> end ( ) , SuccB , SuccB -> begin ( ) , SuccB -> end ( ) ) ;

PredB -> transferSuccessorsAndUpdatePHIs ( SuccB ) ;


<s> void <ISA_LIT>EarlyIfConversion :: predicateBlockNB ( MachineBasicBlock * ToB , MachineBasicBlock :: iterator At , MachineBasicBlock * FromB , unsigned PredR , bool IfTrue ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << PrintMB ( FromB ) << <STR_LIT> ) ; MachineBasicBlock :: iterator End = FromB -> getFirstTerminator ( ) ; MachineBasicBlock :: iterator I , NextI ; for ( I = FromB -> begin ( ) ; I != End ; I = NextI ) {


<s> NextI = std :: next ( I ) ; if ( isSafeToSpeculate ( & * I ) ) ToB -> splice ( At , FromB , I ) ; else predicateInstr ( ToB , At , & * I , PredR , IfTrue ) ; }


<s> if ( HII -> isPostIncrement ( * MI ) ) { MIB . add ( * MOI ) ; ++ MOI ; } MIB . addReg ( PredR ) ; for ( const MachineOperand & MO : make_range ( MOI , MI -> operands_end ( ) ) ) MIB . add ( MO ) ; MIB . cloneMemRefs ( * MI ) ; MI -> eraseFromParent ( ) ; return ; } if ( Opc == <STR_LIT> ) {

MachineBasicBlock * TB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ;


<s> TRI = ST . getRegisterInfo ( ) ; MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ;

MBPI = Enable<ISA_LIT>BP ? & getAnalysis < MachineBranchProbabilityInfo > ( ) :


<s> if ( FP . SplitB -> succ_size ( ) != <NUM_LIT> ) return ; MachineBasicBlock * SB = * FP . SplitB -> succ_begin ( ) ; if ( SB -> pred_size ( ) != <NUM_LIT> ) return ;

if ( ! hasEHLabel ( SB ) || hasUncondBranch ( SB ) ) mergeBlocks ( FP . SplitB , SB ) ;


<s> MachineBasicBlock * SB = * FP . SplitB -> succ_begin ( ) ; if ( SB -> pred_size ( ) != <NUM_LIT> ) return ; if ( ! hasEHLabel ( SB ) || hasUncondBranch ( SB ) ) mergeBlocks ( FP . SplitB , SB ) ;


<s> const MachineOperand & RO = PN -> getOperand ( i ) , & BO = PN -> getOperand ( i + <NUM_LIT> ) ; if ( BO . getMBB ( ) == FP . SplitB ) SR = RO . getReg ( ) , SSR = RO . getSubReg ( ) ; else if ( BO . getMBB ( ) == FP . TrueB ) TR = RO . getReg ( ) , TSR = RO . getSubReg ( ) ; else if ( BO . getMBB ( ) == FP . FalseB ) FR = RO . getReg ( ) , FSR = RO . getSubReg ( ) ; else continue ; PN -> RemoveOperand ( i + <NUM_LIT> ) ; PN -> RemoveOperand ( i ) ; }

if ( TR == <NUM_LIT> ) TR = SR , TSR = SSR ;


<s> } if ( TR == <NUM_LIT> ) TR = SR , TSR = SSR ; else if ( FR == <NUM_LIT> ) FR = SR , FSR = SSR ; assert ( TR || FR ) ; unsigned MuxR = <NUM_LIT> , MuxSR = <NUM_LIT> ; if ( TR && FR ) { Register DR = PN -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( DR ) ; MuxR = buildMux ( FP . SplitB , FP . SplitB -> getFirstTerminator ( ) , RC , FP . PredR , TR , TSR , FR , FSR ) ; } else if ( TR ) { MuxR = TR ; MuxSR = TSR ; } else { MuxR = FR ; MuxSR = FSR ; }

PN -> addOperand ( MachineOperand :: CreateReg ( MuxR , false , false , false , false , false , false , MuxSR ) ) ;


<s> Register R = MO . getReg ( ) ; if ( ! R . isVirtual ( ) ) continue ; const MachineInstr * DefI = MRI -> getVRegDef ( R ) ;


<s> bool Changed = false ; MachineDomTreeNode * N = MDT -> getNode ( B ) ; using GTN = GraphTraits < MachineDomTreeNode * > ; using DTNodeVectType = SmallVector < MachineDomTreeNode * , <NUM_LIT> > ; DTNodeVectType Cn ( GTN :: child_begin ( N ) , GTN :: child_end ( N ) ) ; for ( DTNodeVectType :: iterator I = Cn . begin ( ) , E = Cn . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * SB = ( * I ) -> getBlock ( ) ; if ( ! Deleted . count ( SB ) ) Changed |= visitBlock ( SB , L ) ; } if ( MLI -> getLoopFor ( B ) != L ) return Changed ; FlowPattern FP ; if ( ! matchFlowPattern ( B , L , FP ) ) return Changed ; if ( ! isValid ( FP ) ) {


<s> bool <ISA_LIT>EarlyIfConversion :: visitBlock ( MachineBasicBlock * B , MachineLoop * L ) { bool Changed = false ; MachineDomTreeNode * N = MDT -> getNode ( B ) ; using GTN = GraphTraits < MachineDomTreeNode * > ; using DTNodeVectType = SmallVector < MachineDomTreeNode * , <NUM_LIT> > ; DTNodeVectType Cn ( GTN :: child_begin ( N ) , GTN :: child_end ( N ) ) ; for ( DTNodeVectType :: iterator I = Cn . begin ( ) , E = Cn . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * SB = ( * I ) -> getBlock ( ) ; if ( ! Deleted . count ( SB ) ) Changed |= visitBlock ( SB , L ) ; }

if ( MLI -> getLoopFor ( B ) != L ) return Changed ;


<s> LLVM_DEBUG ( ( L ? dbgs ( ) << <STR_LIT> << PrintMB ( HB ) : dbgs ( ) << <STR_LIT> ) << <STR_LIT> ) ; bool Changed = false ; if ( L ) {

for ( MachineLoop :: iterator I = L -> begin ( ) , E = L -> end ( ) ; I != E ; ++ I ) Changed |= visitLoop ( * I ) ;


<s> if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned R = MO . getReg ( ) ;

if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ;