<s> BitRef ( const BitRef & BR ) : Reg ( BR . Reg ) , Pos ( BR . Pos ) {


<s> BitTracker :: BitTracker ( const MachineEvaluator & E , MachineFunction & F ) : ME ( E ) , MF ( F ) , MRI ( F . getRegInfo ( ) ) , Map ( * new CellMapType ) , Trace ( false ) {


<s> BitValue ( const BitValue & V ) : Type ( V . Type ) , RefI ( V . RefI ) {


<s> void BitTracker :: print_cells ( raw_ostream & OS ) const {

for ( const std :: pair < unsigned , RegisterCell > P : Map ) dbgs ( ) << printReg ( P . first , & ME . TRI ) << <STR_LIT> << P . second << <STR_LIT> ;


<s> Map . clear ( ) ; ReachedBB . clear ( ) ; ReachedBB . reserve ( MF . size ( ) ) ;


<s> assert ( FlowQ . empty ( ) ) ; using MachineFlowGraphTraits = GraphTraits < const MachineFunction * > ; const MachineBasicBlock * Entry = MachineFlowGraphTraits :: getEntryNode ( & MF ) ; unsigned MaxBN = <NUM_LIT> ; for ( const MachineBasicBlock & B : MF ) { assert ( B . getNumber ( ) >= <NUM_LIT> && <STR_LIT> ) ; unsigned BN = B . getNumber ( ) ; if ( BN > MaxBN ) MaxBN = BN ; } BitVector BlockScanned ( MaxBN + <NUM_LIT> ) ; int EntryN = Entry -> getNumber ( ) ; FlowQ . push ( CFGEdge ( - <NUM_LIT> , EntryN ) ) ;

while ( ! FlowQ . empty ( ) || ! UseQ . empty ( ) ) {


<s> FlowQ . pop ( ) ; if ( EdgeExec . count ( Edge ) ) return ; EdgeExec . insert ( Edge ) ; ReachedBB . insert ( Edge . second ) ; const MachineBasicBlock & B = * MF . getBlockNumbered ( Edge . second ) ; MachineBasicBlock :: const_iterator It = B . begin ( ) , End = B . end ( ) ; while ( It != End && It -> isPHI ( ) ) { const MachineInstr & PI = * It ++ ; InstrExec . insert ( & PI ) ;


<s> uint16_t OMB = OM . first ( ) , OME = OM . last ( ) ; uint16_t NMB = NM . first ( ) , NME = NM . last ( ) ; ( void ) NME ; assert ( ( OME - OMB == NME - NMB ) && <STR_LIT> ) ; for ( std :: pair < const unsigned , RegisterCell > & P : Map ) { RegisterCell & RC = P . second ;

for ( uint16_t i = <NUM_LIT> , w = RC . width ( ) ; i < w ; ++ i ) {


<s> RegisterCell & RC = P . second ; for ( uint16_t i = <NUM_LIT> , w = RC . width ( ) ; i < w ; ++ i ) { BitValue & V = RC [ i ] ; if ( V . Type != BitValue :: Ref || V . RefI . Reg != OldRR . Reg ) continue ; if ( V . RefI . Pos < OMB || V . RefI . Pos > OME ) continue ; V . RefI . Reg = NewRR . Reg ; V . RefI . Pos += NMB - OMB ;


<s> runUseQueue ( ) ; while ( ! FlowQ . empty ( ) ) FlowQ . pop ( ) ;


<s> void BT :: visit ( const MachineInstr & MI ) { assert ( ! MI . isBranch ( ) && <STR_LIT> ) ;


<s> } Targets . insert ( BTs . begin ( ) , BTs . end ( ) ) ; } ++ It ; } while ( FallsThrough && It != End ) ; if ( B . mayHaveInlineAsmBr ( ) ) DefaultToAll = true ; if ( ! DefaultToAll ) { for ( const MachineBasicBlock * SB : B . successors ( ) ) { if ( SB -> isEHPad ( ) ) Targets . insert ( SB ) ; } if ( FallsThrough ) { MachineFunction :: const_iterator BIt = B . getIterator ( ) ; MachineFunction :: const_iterator Next = std :: next ( BIt ) ; if ( Next != MF . end ( ) ) Targets . insert ( & * Next ) ; } } else { for ( const MachineBasicBlock * SB : B . successors ( ) ) Targets . insert ( SB ) ; }

for ( const MachineBasicBlock * TB : Targets ) FlowQ . push ( CFGEdge ( ThisN , TB -> getNumber ( ) ) ) ;


<s> BTs . clear ( ) ; const MachineInstr & MI = * It ; if ( Trace ) dbgs ( ) << <STR_LIT> << printMBBReference ( B ) << <STR_LIT> << MI ; assert ( MI . isBranch ( ) && <STR_LIT> ) ; InstrExec . insert ( & MI ) ; bool Eval = ME . evaluate ( MI , Map , BTs , FallsThrough ) ; if ( ! Eval ) { DefaultToAll = true ; FallsThrough = true ; if ( Trace ) dbgs ( ) << <STR_LIT> ; } else if ( ! DefaultToAll ) { if ( Trace ) { dbgs ( ) << <STR_LIT> ; for ( unsigned i = <NUM_LIT> , n = BTs . size ( ) ; i < n ; ++ i ) dbgs ( ) << <STR_LIT> << printMBBReference ( * BTs [ i ] ) ; if ( FallsThrough ) dbgs ( ) << <STR_LIT> ;


<s> } for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; RegisterRef RD ( MO ) ; assert ( RD . Sub == <NUM_LIT> && <STR_LIT> ) ; if ( ! RD . Reg . isVirtual ( ) ) continue ; bool Changed = false ; if ( ! Eval || ResMap . count ( RD . Reg ) == <NUM_LIT> ) { uint16_t DefBW = ME . getRegBitWidth ( RD ) ; RegisterCell RefC = RegisterCell :: self ( RD . Reg , DefBW ) ; if ( RefC != ME . getCell ( RD , Map ) ) { ME . putCell ( RD , RefC , Map ) ; Changed = true ; } } else {

RegisterCell DefC = ME . getCell ( RD , Map ) ;


<s> if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; RegisterRef RD ( MO ) ; assert ( RD . Sub == <NUM_LIT> && <STR_LIT> ) ; if ( ! RD . Reg . isVirtual ( ) ) continue ; bool Changed = false ; if ( ! Eval || ResMap . count ( RD . Reg ) == <NUM_LIT> ) { uint16_t DefBW = ME . getRegBitWidth ( RD ) ; RegisterCell RefC = RegisterCell :: self ( RD . Reg , DefBW ) ; if ( RefC != ME . getCell ( RD , Map ) ) { ME . putCell ( RD , RefC , Map ) ; Changed = true ; } } else { RegisterCell DefC = ME . getCell ( RD , Map ) ; RegisterCell ResC = ME . getCell ( RD , ResMap ) ; for ( uint16_t i = <NUM_LIT> , w = DefC . width ( ) ; i < w ; ++ i ) { BitValue & V = DefC [ i ] ;

if ( V . Type == BitValue :: Ref && V . RefI . Reg == RD . Reg ) continue ;


<s> RegisterRef DefRR ( MD ) ; uint16_t DefBW = ME . getRegBitWidth ( DefRR ) ; RegisterCell DefC = ME . getCell ( DefRR , Map ) ; if ( DefC == RegisterCell :: self ( DefRR . Reg , DefBW ) ) return ; bool Changed = false ; for ( unsigned i = <NUM_LIT> , n = PI . getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) { const MachineBasicBlock * PB = PI . getOperand ( i + <NUM_LIT> ) . getMBB ( ) ; int PredN = PB -> getNumber ( ) ; if ( Trace ) dbgs ( ) << <STR_LIT> << printMBBReference ( * PB ) << <STR_LIT> << printMBBReference ( * PI . getParent ( ) ) ; if ( ! EdgeExec . count ( CFGEdge ( PredN , ThisN ) ) ) { if ( Trace ) dbgs ( ) << <STR_LIT> ; continue ; } RegisterRef RU = PI . getOperand ( i ) ; RegisterCell ResC = ME . getCell ( RU , Map ) ; if ( Trace ) dbgs ( ) << <STR_LIT> << printReg ( RU . Reg , & ME . TRI , RU . Sub ) << <STR_LIT> << ResC << <STR_LIT> ; Changed |= DefC . meet ( ResC , DefRR . Reg ) ; } if ( Changed ) { if ( Trace ) dbgs ( ) << <STR_LIT> << printReg ( DefRR . Reg , & ME . TRI , DefRR . Sub ) << <STR_LIT> << DefC << <STR_LIT> ;


<s> void BT :: visitUsesOf ( Register Reg ) {

if ( Trace ) dbgs ( ) << <STR_LIT> << printReg ( Reg , & ME . TRI ) << <STR_LIT> << ME . getCell ( Reg , Map ) << '\n' ;


<s> if ( Trace ) dbgs ( ) << <STR_LIT> << printMBBReference ( B ) << <STR_LIT> << MI ; assert ( MI . isBranch ( ) && <STR_LIT> ) ; InstrExec . insert ( & MI ) ; bool Eval = ME . evaluate ( MI , Map , BTs , FallsThrough ) ; if ( ! Eval ) { DefaultToAll = true ; FallsThrough = true ; if ( Trace ) dbgs ( ) << <STR_LIT> ; } else if ( ! DefaultToAll ) { if ( Trace ) { dbgs ( ) << <STR_LIT> ; for ( unsigned i = <NUM_LIT> , n = BTs . size ( ) ; i < n ; ++ i ) dbgs ( ) << <STR_LIT> << printMBBReference ( * BTs [ i ] ) ; if ( FallsThrough ) dbgs ( ) << <STR_LIT> ; else dbgs ( ) << <STR_LIT> ; } Targets . insert ( BTs . begin ( ) , BTs . end ( ) ) ; } ++ It ; } while ( FallsThrough && It != End ) ; if ( ! DefaultToAll ) { for ( const MachineBasicBlock * SB : B . successors ( ) ) { if ( SB -> isEHPad ( ) ) Targets . insert ( SB ) ; } if ( FallsThrough ) { MachineFunction :: const_iterator BIt = B . getIterator ( ) ; MachineFunction :: const_iterator Next = std :: next ( BIt ) ; if ( Next != MF . end ( ) ) Targets . insert ( & * Next ) ; }


<s> if ( ! MO . isReg ( ) || ! MO . isUse ( ) ) continue ; RegisterRef RU ( MO ) ; dbgs ( ) << <STR_LIT> << printReg ( RU . Reg , & ME . TRI , RU . Sub ) << <STR_LIT> << ME . getCell ( RU , Map ) << <STR_LIT> ; } dbgs ( ) << <STR_LIT> ; for ( const std :: pair < unsigned , RegisterCell > & P : ResMap ) { RegisterRef RD ( P . first ) ; dbgs ( ) << <STR_LIT> << printReg ( P . first , & ME . TRI ) << <STR_LIT> << ME . getCell ( RD , ResMap ) << <STR_LIT> ; } } for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; RegisterRef RD ( MO ) ; assert ( RD . Sub == <NUM_LIT> && <STR_LIT> ) ;

if ( ! TargetRegisterInfo :: isVirtualRegister ( RD . Reg ) ) continue ;


<s> dbgs ( ) << <STR_LIT> ; for ( const std :: pair < unsigned , RegisterCell > & P : ResMap ) { RegisterRef RD ( P . first ) ; dbgs ( ) << <STR_LIT> << printReg ( P . first , & ME . TRI ) << <STR_LIT> << ME . getCell ( RD , ResMap ) << <STR_LIT> ; } } for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; RegisterRef RD ( MO ) ; assert ( RD . Sub == <NUM_LIT> && <STR_LIT> ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( RD . Reg ) ) continue ; bool Changed = false ; if ( ! Eval || ResMap . count ( RD . Reg ) == <NUM_LIT> ) { uint16_t DefBW = ME . getRegBitWidth ( RD ) ; RegisterCell RefC = RegisterCell :: self ( RD . Reg , DefBW ) ; if ( RefC != ME . getCell ( RD , Map ) ) { ME . putCell ( RD , RefC , Map ) ; Changed = true ; } } else { RegisterCell DefC = ME . getCell ( RD , Map ) ; RegisterCell ResC = ME . getCell ( RD , ResMap ) ; for ( uint16_t i = <NUM_LIT> , w = DefC . width ( ) ; i < w ; ++ i ) { BitValue & V = DefC [ i ] ; if ( V . Type == BitValue :: Ref && V . RefI . Reg == RD . Reg ) continue ; if ( V == ResC [ i ] ) continue ; V = ResC [ i ] ; Changed = true ; } if ( Changed ) ME . putCell ( RD , DefC , Map ) ; } if ( Changed ) visitUsesOf ( RD . Reg ) ; }


<s> if ( Trace ) dbgs ( ) << <STR_LIT> << printReg ( Reg , & ME . TRI ) << <STR_LIT> << ME . getCell ( Reg , Map ) << '\n' ; for ( MachineInstr & UseI : MRI . use_nodbg_instructions ( Reg ) ) UseQ . push ( & UseI ) ;


<s> for ( CellMapType :: iterator I = Map . begin ( ) , E = Map . end ( ) ; I != E ; ++ I ) dbgs ( ) << PrintReg ( I -> first , & ME . TRI ) << <STR_LIT> << I -> second << <STR_LIT> ;


<s> EdgeExec . insert ( Edge ) ; const MachineBasicBlock & B = * MF . getBlockNumbered ( Edge . second ) ; MachineBasicBlock :: const_iterator It = B . begin ( ) , End = B . end ( ) ; while ( It != End && It -> isPHI ( ) ) { const MachineInstr & PI = * It ++ ; InstrExec . insert ( & PI ) ; visitPHI ( PI ) ; } if ( BlockScanned [ Edge . second ] ) continue ; BlockScanned [ Edge . second ] = true ; while ( It != End && ! It -> isBranch ( ) ) { const MachineInstr & MI = * It ++ ; InstrExec . insert ( & MI ) ; visitNonBranch ( MI ) ; } if ( It == End ) { MachineFunction :: const_iterator BIt = B . getIterator ( ) ; MachineFunction :: const_iterator Next = std :: next ( BIt ) ;

if ( Next != MF . end ( ) && B . isSuccessor ( & * Next ) ) {


<s> void BT :: visit ( const MachineInstr & MI ) { assert ( ! MI . isBranch ( ) && <STR_LIT> ) ; InstrExec . insert ( & MI ) ; visitNonBranch ( MI ) ; while ( ! FlowQ . empty ( ) ) FlowQ . pop ( ) ;


<s> } } for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; RegisterRef RD ( MO ) ; assert ( RD . Sub == <NUM_LIT> && <STR_LIT> ) ; if ( ! Register :: isVirtualRegister ( RD . Reg ) ) continue ; bool Changed = false ; if ( ! Eval || ResMap . count ( RD . Reg ) == <NUM_LIT> ) { uint16_t DefBW = ME . getRegBitWidth ( RD ) ; RegisterCell RefC = RegisterCell :: self ( RD . Reg , DefBW ) ; if ( RefC != ME . getCell ( RD , Map ) ) { ME . putCell ( RD , RefC , Map ) ; Changed = true ; } } else {


<s> if ( ! Eval || ResMap . count ( RD . Reg ) == <NUM_LIT> ) { uint16_t DefBW = ME . getRegBitWidth ( RD ) ; RegisterCell RefC = RegisterCell :: self ( RD . Reg , DefBW ) ; if ( RefC != ME . getCell ( RD , Map ) ) { ME . putCell ( RD , RefC , Map ) ; Changed = true ; } } else { RegisterCell DefC = ME . getCell ( RD , Map ) ; RegisterCell ResC = ME . getCell ( RD , ResMap ) ; for ( uint16_t i = <NUM_LIT> , w = DefC . width ( ) ; i < w ; ++ i ) { BitValue & V = DefC [ i ] ; if ( V . Type == BitValue :: Ref && V . RefI . Reg == RD . Reg ) continue ; if ( V == ResC [ i ] ) continue ; V = ResC [ i ] ; Changed = true ; }

if ( Changed ) ME . putCell ( RD , DefC , Map ) ;


<s> void BitTracker :: print_cells ( raw_ostream & OS ) const {

for ( const std :: pair < unsigned , RegisterCell > P : Map ) dbgs ( ) << PrintReg ( P . first , & ME . TRI ) << <STR_LIT> << P . second << <STR_LIT> ;


<s> InstrExec . insert ( & PI ) ; visitPHI ( PI ) ; } if ( BlockScanned [ Edge . second ] ) continue ; BlockScanned [ Edge . second ] = true ; while ( It != End && ! It -> isBranch ( ) ) { const MachineInstr & MI = * It ++ ; InstrExec . insert ( & MI ) ; visitNonBranch ( MI ) ; } if ( It == End ) { MachineFunction :: const_iterator BIt = B . getIterator ( ) ; MachineFunction :: const_iterator Next = std :: next ( BIt ) ; if ( Next != MF . end ( ) && B . isSuccessor ( & * Next ) ) { int ThisN = B . getNumber ( ) ; int NextN = Next -> getNumber ( ) ; FlowQ . push ( CFGEdge ( ThisN , NextN ) ) ; } } else { visitBranchesFrom ( * It ) ; } } if ( Trace ) print_cells ( dbgs ( ) << <STR_LIT> ) ;


<s> using MachineFlowGraphTraits = GraphTraits < const MachineFunction * > ; const MachineBasicBlock * Entry = MachineFlowGraphTraits :: getEntryNode ( & MF ) ; unsigned MaxBN = <NUM_LIT> ; for ( const MachineBasicBlock & B : MF ) { assert ( B . getNumber ( ) >= <NUM_LIT> && <STR_LIT> ) ; unsigned BN = B . getNumber ( ) ; if ( BN > MaxBN ) MaxBN = BN ; } BitVector BlockScanned ( MaxBN + <NUM_LIT> ) ; int EntryN = Entry -> getNumber ( ) ; FlowQ . push ( CFGEdge ( - <NUM_LIT> , EntryN ) ) ; while ( ! FlowQ . empty ( ) ) { CFGEdge Edge = FlowQ . front ( ) ; FlowQ . pop ( ) ; if ( EdgeExec . count ( Edge ) ) continue ; EdgeExec . insert ( Edge ) ; ReachedBB . insert ( Edge . second ) ; const MachineBasicBlock & B = * MF . getBlockNumbered ( Edge . second ) ; MachineBasicBlock :: const_iterator It = B . begin ( ) , End = B . end ( ) ;

while ( It != End && It -> isPHI ( ) ) {


<s> bool Eval = ME . evaluate ( MI , Map , BTs , FallsThrough ) ; if ( ! Eval ) { DefaultToAll = true ; FallsThrough = true ; if ( Trace ) dbgs ( ) << <STR_LIT> ; } else if ( ! DefaultToAll ) { if ( Trace ) { dbgs ( ) << <STR_LIT> ; for ( unsigned i = <NUM_LIT> , n = BTs . size ( ) ; i < n ; ++ i ) dbgs ( ) << <STR_LIT> << BTs [ i ] -> getNumber ( ) ; if ( FallsThrough ) dbgs ( ) << <STR_LIT> ; else dbgs ( ) << <STR_LIT> ; } Targets . insert ( BTs . begin ( ) , BTs . end ( ) ) ; } ++ It ;


<s> CellMapType ResMap ; bool Eval = ME . evaluate ( MI , Map , ResMap ) ; if ( Trace && Eval ) { for ( unsigned i = <NUM_LIT> , n = MI . getNumOperands ( ) ; i < n ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isUse ( ) ) continue ; RegisterRef RU ( MO ) ; dbgs ( ) << <STR_LIT> << PrintReg ( RU . Reg , & ME . TRI , RU . Sub ) << <STR_LIT> << ME . getCell ( RU , Map ) << <STR_LIT> ; } dbgs ( ) << <STR_LIT> ; for ( const std :: pair < unsigned , RegisterCell > & P : ResMap ) { RegisterRef RD ( P . first ) ; dbgs ( ) << <STR_LIT> << PrintReg ( P . first , & ME . TRI ) << <STR_LIT> << ME . getCell ( RD , ResMap ) << <STR_LIT> ; }


<s> if ( Trace ) dbgs ( ) << <STR_LIT> << PrintReg ( Reg , & ME . TRI ) << <STR_LIT> ; for ( const MachineInstr & UseI : MRI . use_nodbg_instructions ( Reg ) ) {

if ( ! InstrExec . count ( & UseI ) ) continue ;


<s> for ( const MachineInstr & UseI : MRI . use_nodbg_instructions ( Reg ) ) { if ( ! InstrExec . count ( & UseI ) ) continue ; if ( UseI . isPHI ( ) ) visitPHI ( UseI ) ; else if ( ! UseI . isBranch ( ) ) visitNonBranch ( UseI ) ;


<s> while ( It != End && It -> isPHI ( ) ) { const MachineInstr * PI = & * It ++ ; InstrExec . insert ( PI ) ; visitPHI ( PI ) ; } if ( BlockScanned [ Edge . second ] ) continue ; BlockScanned [ Edge . second ] = true ; while ( It != End && ! It -> isBranch ( ) ) { const MachineInstr * MI = & * It ++ ; InstrExec . insert ( MI ) ; visitNonBranch ( MI ) ; } if ( It == End ) { MachineFunction :: const_iterator BIt = B . getIterator ( ) ; MachineFunction :: const_iterator Next = std :: next ( BIt ) ; if ( Next != MF . end ( ) && B . isSuccessor ( & * Next ) ) { int ThisN = B . getNumber ( ) ; int NextN = Next -> getNumber ( ) ; FlowQ . push ( CFGEdge ( ThisN , NextN ) ) ; } } else { visitBranchesFrom ( It ) ; } } if ( Trace ) { dbgs ( ) << <STR_LIT> ;

for ( CellMapType :: iterator I = Map . begin ( ) , E = Map . end ( ) ; I != E ; ++ I ) dbgs ( ) << PrintReg ( I -> first , & ME . TRI ) << <STR_LIT> << I -> second << <STR_LIT> ;


<s> if ( Trace ) { dbgs ( ) << <STR_LIT> ; for ( unsigned i = <NUM_LIT> , n = BTs . size ( ) ; i < n ; ++ i ) dbgs ( ) << <STR_LIT> << BTs [ i ] -> getNumber ( ) ; if ( FallsThrough ) dbgs ( ) << <STR_LIT> ; else dbgs ( ) << <STR_LIT> ; } Targets . insert ( BTs . begin ( ) , BTs . end ( ) ) ; } ++ It ; } while ( FallsThrough && It != End ) ; typedef MachineBasicBlock :: const_succ_iterator succ_iterator ; if ( ! DefaultToAll ) { for ( succ_iterator I = B . succ_begin ( ) , E = B . succ_end ( ) ; I != E ; ++ I ) { const MachineBasicBlock * SB = * I ; if ( SB -> isEHPad ( ) ) Targets . insert ( SB ) ; } if ( FallsThrough ) { MachineFunction :: const_iterator BIt = B . getIterator ( ) ; MachineFunction :: const_iterator Next = std :: next ( BIt ) ; if ( Next != MF . end ( ) ) Targets . insert ( & * Next ) ; } } else { for ( succ_iterator I = B . succ_begin ( ) , E = B . succ_end ( ) ; I != E ; ++ I ) Targets . insert ( * I ) ; } for ( unsigned i = <NUM_LIT> , n = Targets . size ( ) ; i < n ; ++ i ) {

int TargetN = Targets [ i ] -> getNumber ( ) ;


<s> BTs . clear ( ) ; const MachineInstr * MI = & * It ; if ( Trace ) dbgs ( ) << <STR_LIT> << ThisN << <STR_LIT> << * MI ; assert ( MI -> isBranch ( ) && <STR_LIT> ) ; InstrExec . insert ( MI ) ; bool Eval = ME . evaluate ( MI , Map , BTs , FallsThrough ) ; if ( ! Eval ) { DefaultToAll = true ; FallsThrough = true ; if ( Trace ) dbgs ( ) << <STR_LIT> ; } else if ( ! DefaultToAll ) { if ( Trace ) { dbgs ( ) << <STR_LIT> ; for ( unsigned i = <NUM_LIT> , n = BTs . size ( ) ; i < n ; ++ i ) dbgs ( ) << <STR_LIT> << BTs [ i ] -> getNumber ( ) ; if ( FallsThrough ) dbgs ( ) << <STR_LIT> ; else dbgs ( ) << <STR_LIT> ; } Targets . insert ( BTs . begin ( ) , BTs . end ( ) ) ; } ++ It ; } while ( FallsThrough && It != End ) ; typedef MachineBasicBlock :: const_succ_iterator succ_iterator ; if ( ! DefaultToAll ) { for ( succ_iterator I = B . succ_begin ( ) , E = B . succ_end ( ) ; I != E ; ++ I ) { const MachineBasicBlock * SB = * I ; if ( SB -> isEHPad ( ) ) Targets . insert ( SB ) ; } if ( FallsThrough ) { MachineFunction :: const_iterator BIt = B . getIterator ( ) ; MachineFunction :: const_iterator Next = std :: next ( BIt ) ; if ( Next != MF . end ( ) ) Targets . insert ( & * Next ) ; } } else { for ( succ_iterator I = B . succ_begin ( ) , E = B . succ_end ( ) ; I != E ; ++ I ) Targets . insert ( * I ) ; }

for ( unsigned i = <NUM_LIT> , n = Targets . size ( ) ; i < n ; ++ i ) {


<s> } dbgs ( ) << <STR_LIT> ; for ( CellMapType :: iterator I = ResMap . begin ( ) , E = ResMap . end ( ) ; I != E ; ++ I ) { RegisterRef RD ( I -> first ) ; dbgs ( ) << <STR_LIT> << PrintReg ( I -> first , & ME . TRI ) << <STR_LIT> << ME . getCell ( RD , ResMap ) << <STR_LIT> ; } } for ( unsigned i = <NUM_LIT> , n = MI -> getNumOperands ( ) ; i < n ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; RegisterRef RD ( MO ) ; assert ( RD . Sub == <NUM_LIT> && <STR_LIT> ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( RD . Reg ) ) continue ; bool Changed = false ; if ( ! Eval || ResMap . count ( RD . Reg ) == <NUM_LIT> ) { uint16_t DefBW = ME . getRegBitWidth ( RD ) ; RegisterCell RefC = RegisterCell :: self ( RD . Reg , DefBW ) ; if ( RefC != ME . getCell ( RD , Map ) ) { ME . putCell ( RD , RefC , Map ) ; Changed = true ; } } else { RegisterCell DefC = ME . getCell ( RD , Map ) ; RegisterCell ResC = ME . getCell ( RD , ResMap ) ;

for ( uint16_t i = <NUM_LIT> , w = DefC . width ( ) ; i < w ; ++ i ) {


<s> Cmp ( DenseMap < const MachineInstr * , unsigned > & Map ) : Dist ( Map ) {


<s> virtual const TargetRegisterClass & composeWithSubRegIndex ( const TargetRegisterClass & RC , unsigned Idx ) const { if ( Idx == <NUM_LIT> ) return RC ;


<s> Set . erase ( front ( ) ) ; Uses . pop ( ) ;


<s> void push ( MachineInstr * MI ) { if ( Set . insert ( MI ) . second ) Uses . push ( MI ) ;


<s> unsigned size ( ) const { return Uses . size ( ) ;


<s> dbgs ( ) << <STR_LIT> << printReg ( RU . Reg , & ME . TRI , RU . Sub ) << <STR_LIT> << ME . getCell ( RU , Map ) << <STR_LIT> ; } dbgs ( ) << <STR_LIT> ; for ( const std :: pair < const unsigned , RegisterCell > & P : ResMap ) { RegisterRef RD ( P . first ) ; dbgs ( ) << <STR_LIT> << printReg ( P . first , & ME . TRI ) << <STR_LIT> << ME . getCell ( RD , ResMap ) << <STR_LIT> ; } } for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; RegisterRef RD ( MO ) ; assert ( RD . Sub == <NUM_LIT> && <STR_LIT> ) ; if ( ! Register :: isVirtualRegister ( RD . Reg ) ) continue ; bool Changed = false ; if ( ! Eval || ResMap . count ( RD . Reg ) == <NUM_LIT> ) { uint16_t DefBW = ME . getRegBitWidth ( RD ) ; RegisterCell RefC = RegisterCell :: self ( RD . Reg , DefBW ) ; if ( RefC != ME . getCell ( RD , Map ) ) { ME . putCell ( RD , RefC , Map ) ; Changed = true ; } } else { RegisterCell DefC = ME . getCell ( RD , Map ) ;

RegisterCell ResC = ME . getCell ( RD , ResMap ) ;


<s> unsigned BN = I -> getNumber ( ) ; if ( BN > MaxBN ) MaxBN = BN ; } BitVector BlockScanned ( MaxBN + <NUM_LIT> ) ; int EntryN = Entry -> getNumber ( ) ; FlowQ . push ( CFGEdge ( - <NUM_LIT> , EntryN ) ) ; while ( ! FlowQ . empty ( ) ) { CFGEdge Edge = FlowQ . front ( ) ; FlowQ . pop ( ) ; if ( EdgeExec . count ( Edge ) ) continue ; EdgeExec . insert ( Edge ) ; const MachineBasicBlock & B = * MF . getBlockNumbered ( Edge . second ) ; MachineBasicBlock :: const_iterator It = B . begin ( ) , End = B . end ( ) ; while ( It != End && It -> isPHI ( ) ) { const MachineInstr & PI = * It ++ ; InstrExec . insert ( & PI ) ; visitPHI ( PI ) ;


<s> assert ( Map . count ( OldRR . Reg ) > <NUM_LIT> && <STR_LIT> ) ; BitMask OM = ME . mask ( OldRR . Reg , OldRR . Sub ) ; BitMask NM = ME . mask ( NewRR . Reg , NewRR . Sub ) ; uint16_t OMB = OM . first ( ) , OME = OM . last ( ) ; uint16_t NMB = NM . first ( ) , NME = NM . last ( ) ; ( void ) NME ; assert ( ( OME - OMB == NME - NMB ) && <STR_LIT> ) ; for ( CellMapType :: iterator I = Map . begin ( ) , E = Map . end ( ) ; I != E ; ++ I ) { RegisterCell & RC = I -> second ; for ( uint16_t i = <NUM_LIT> , w = RC . width ( ) ; i < w ; ++ i ) {


<s> const MachineInstr & MI = * It ; if ( Trace ) dbgs ( ) << <STR_LIT> << ThisN << <STR_LIT> << MI ; assert ( MI . isBranch ( ) && <STR_LIT> ) ; InstrExec . insert ( & MI ) ; bool Eval = ME . evaluate ( MI , Map , BTs , FallsThrough ) ; if ( ! Eval ) { DefaultToAll = true ; FallsThrough = true ; if ( Trace ) dbgs ( ) << <STR_LIT> ; } else if ( ! DefaultToAll ) { if ( Trace ) { dbgs ( ) << <STR_LIT> ; for ( unsigned i = <NUM_LIT> , n = BTs . size ( ) ; i < n ; ++ i ) dbgs ( ) << <STR_LIT> << BTs [ i ] -> getNumber ( ) ; if ( FallsThrough ) dbgs ( ) << <STR_LIT> ; else dbgs ( ) << <STR_LIT> ; } Targets . insert ( BTs . begin ( ) , BTs . end ( ) ) ; } ++ It ; } while ( FallsThrough && It != End ) ; typedef MachineBasicBlock :: const_succ_iterator succ_iterator ; if ( ! DefaultToAll ) { for ( succ_iterator I = B . succ_begin ( ) , E = B . succ_end ( ) ; I != E ; ++ I ) { const MachineBasicBlock * SB = * I ; if ( SB -> isEHPad ( ) ) Targets . insert ( SB ) ; }


<s> } else if ( ! DefaultToAll ) { if ( Trace ) { dbgs ( ) << <STR_LIT> ; for ( unsigned i = <NUM_LIT> , n = BTs . size ( ) ; i < n ; ++ i ) dbgs ( ) << <STR_LIT> << BTs [ i ] -> getNumber ( ) ; if ( FallsThrough ) dbgs ( ) << <STR_LIT> ; else dbgs ( ) << <STR_LIT> ; } Targets . insert ( BTs . begin ( ) , BTs . end ( ) ) ; } ++ It ; } while ( FallsThrough && It != End ) ; typedef MachineBasicBlock :: const_succ_iterator succ_iterator ; if ( ! DefaultToAll ) { for ( succ_iterator I = B . succ_begin ( ) , E = B . succ_end ( ) ; I != E ; ++ I ) { const MachineBasicBlock * SB = * I ; if ( SB -> isEHPad ( ) ) Targets . insert ( SB ) ; } if ( FallsThrough ) { MachineFunction :: const_iterator BIt = B . getIterator ( ) ; MachineFunction :: const_iterator Next = std :: next ( BIt ) ; if ( Next != MF . end ( ) ) Targets . insert ( & * Next ) ; } } else { for ( succ_iterator I = B . succ_begin ( ) , E = B . succ_end ( ) ; I != E ; ++ I ) Targets . insert ( * I ) ;


<s> const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isUse ( ) ) continue ; RegisterRef RU ( MO ) ; dbgs ( ) << <STR_LIT> << PrintReg ( RU . Reg , & ME . TRI , RU . Sub ) << <STR_LIT> << ME . getCell ( RU , Map ) << <STR_LIT> ; } dbgs ( ) << <STR_LIT> ; for ( CellMapType :: iterator I = ResMap . begin ( ) , E = ResMap . end ( ) ; I != E ; ++ I ) { RegisterRef RD ( I -> first ) ; dbgs ( ) << <STR_LIT> << PrintReg ( I -> first , & ME . TRI ) << <STR_LIT> << ME . getCell ( RD , ResMap ) << <STR_LIT> ; } } for ( unsigned i = <NUM_LIT> , n = MI . getNumOperands ( ) ; i < n ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; RegisterRef RD ( MO ) ; assert ( RD . Sub == <NUM_LIT> && <STR_LIT> ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( RD . Reg ) ) continue ; bool Changed = false ; if ( ! Eval || ResMap . count ( RD . Reg ) == <NUM_LIT> ) { uint16_t DefBW = ME . getRegBitWidth ( RD ) ; RegisterCell RefC = RegisterCell :: self ( RD . Reg , DefBW ) ;

if ( RefC != ME . getCell ( RD , Map ) ) {


<s> if ( Trace ) dbgs ( ) << <STR_LIT> << ThisN << <STR_LIT> << PI ; const MachineOperand & MD = PI . getOperand ( <NUM_LIT> ) ; assert ( MD . getSubReg ( ) == <NUM_LIT> && <STR_LIT> ) ; RegisterRef DefRR ( MD ) ; uint16_t DefBW = ME . getRegBitWidth ( DefRR ) ; RegisterCell DefC = ME . getCell ( DefRR , Map ) ; if ( DefC == RegisterCell :: self ( DefRR . Reg , DefBW ) ) return ; bool Changed = false ; for ( unsigned i = <NUM_LIT> , n = PI . getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) {

const MachineBasicBlock * PB = PI . getOperand ( i + <NUM_LIT> ) . getMBB ( ) ;


<s> if ( ! InstrExec . count ( UseI ) ) continue ; if ( UseI -> isPHI ( ) ) visitPHI ( * UseI ) ; else if ( ! UseI -> isBranch ( ) ) visitNonBranch ( * UseI ) ; else visitBranchesFrom ( * UseI ) ;


<s> assert ( FlowQ . empty ( ) ) ; typedef GraphTraits < const MachineFunction * > MachineFlowGraphTraits ; const MachineBasicBlock * Entry = MachineFlowGraphTraits :: getEntryNode ( & MF ) ; unsigned MaxBN = <NUM_LIT> ; for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { assert ( I -> getNumber ( ) >= <NUM_LIT> && <STR_LIT> ) ; unsigned BN = I -> getNumber ( ) ; if ( BN > MaxBN ) MaxBN = BN ; } BitVector BlockScanned ( MaxBN + <NUM_LIT> ) ; int EntryN = Entry -> getNumber ( ) ; FlowQ . push ( CFGEdge ( - <NUM_LIT> , EntryN ) ) ; while ( ! FlowQ . empty ( ) ) { CFGEdge Edge = FlowQ . front ( ) ; FlowQ . pop ( ) ; if ( EdgeExec . count ( Edge ) ) continue ; EdgeExec . insert ( Edge ) ; ReachedBB . insert ( Edge . second ) ; const MachineBasicBlock & B = * MF . getBlockNumbered ( Edge . second ) ; MachineBasicBlock :: const_iterator It = B . begin ( ) , End = B . end ( ) ; while ( It != End && It -> isPHI ( ) ) { const MachineInstr & PI = * It ++ ; InstrExec . insert ( & PI ) ; visitPHI ( PI ) ; } if ( BlockScanned [ Edge . second ] ) continue ; BlockScanned [ Edge . second ] = true ; while ( It != End && ! It -> isBranch ( ) ) { const MachineInstr & MI = * It ++ ; InstrExec . insert ( & MI ) ;


<s> Targets . insert ( BTs . begin ( ) , BTs . end ( ) ) ; } ++ It ; } while ( FallsThrough && It != End ) ; if ( B . mayHaveInlineAsmBr ( ) ) DefaultToAll = true ; if ( ! DefaultToAll ) { for ( const MachineBasicBlock * SB : B . successors ( ) ) { if ( SB -> isEHPad ( ) ) Targets . insert ( SB ) ; } if ( FallsThrough ) { MachineFunction :: const_iterator BIt = B . getIterator ( ) ; MachineFunction :: const_iterator Next = std :: next ( BIt ) ; if ( Next != MF . end ( ) ) Targets . insert ( & * Next ) ; } } else { for ( const MachineBasicBlock * SB : B . successors ( ) ) Targets . insert ( SB ) ;


<s> if ( ! Eval ) { DefaultToAll = true ; FallsThrough = true ; if ( Trace ) dbgs ( ) << <STR_LIT> ; } else if ( ! DefaultToAll ) { if ( Trace ) { dbgs ( ) << <STR_LIT> ; for ( const MachineBasicBlock * BT : BTs ) dbgs ( ) << <STR_LIT> << printMBBReference ( * BT ) ; if ( FallsThrough ) dbgs ( ) << <STR_LIT> ; else dbgs ( ) << <STR_LIT> ; } Targets . insert ( BTs . begin ( ) , BTs . end ( ) ) ; } ++ It ; } while ( FallsThrough && It != End ) ; if ( B . mayHaveInlineAsmBr ( ) ) DefaultToAll = true ; if ( ! DefaultToAll ) { for ( const MachineBasicBlock * SB : B . successors ( ) ) { if ( SB -> isEHPad ( ) ) Targets . insert ( SB ) ; } if ( FallsThrough ) { MachineFunction :: const_iterator BIt = B . getIterator ( ) ; MachineFunction :: const_iterator Next = std :: next ( BIt ) ; if ( Next != MF . end ( ) ) Targets . insert ( & * Next ) ; } } else {

for ( const MachineBasicBlock * SB : B . successors ( ) ) Targets . insert ( SB ) ;


<s> RegisterRef RD ( MO ) ; assert ( RD . Sub == <NUM_LIT> && <STR_LIT> ) ; if ( ! RD . Reg . isVirtual ( ) ) continue ; bool Changed = false ; if ( ! Eval || ResMap . count ( RD . Reg ) == <NUM_LIT> ) { uint16_t DefBW = ME . getRegBitWidth ( RD ) ; RegisterCell RefC = RegisterCell :: self ( RD . Reg , DefBW ) ; if ( RefC != ME . getCell ( RD , Map ) ) { ME . putCell ( RD , RefC , Map ) ; Changed = true ; } } else { RegisterCell DefC = ME . getCell ( RD , Map ) ; RegisterCell ResC = ME . getCell ( RD , ResMap ) ; for ( uint16_t i = <NUM_LIT> , w = DefC . width ( ) ; i < w ; ++ i ) { BitValue & V = DefC [ i ] ;


<s> const MachineBasicBlock & B = * MF . getBlockNumbered ( Edge . second ) ; MachineBasicBlock :: const_iterator It = B . begin ( ) , End = B . end ( ) ; while ( It != End && It -> isPHI ( ) ) { const MachineInstr * PI = & * It ++ ; InstrExec . insert ( PI ) ; visitPHI ( PI ) ; } if ( BlockScanned [ Edge . second ] ) continue ; BlockScanned [ Edge . second ] = true ; while ( It != End && ! It -> isBranch ( ) ) { const MachineInstr * MI = & * It ++ ; InstrExec . insert ( MI ) ; visitNonBranch ( MI ) ; } if ( It == End ) { MachineFunction :: const_iterator BIt = B . getIterator ( ) ; MachineFunction :: const_iterator Next = std :: next ( BIt ) ; if ( Next != MF . end ( ) && B . isSuccessor ( Next ) ) { int ThisN = B . getNumber ( ) ; int NextN = Next -> getNumber ( ) ; FlowQ . push ( CFGEdge ( ThisN , NextN ) ) ; } } else { visitBranchesFrom ( It ) ; } } if ( Trace ) { dbgs ( ) << <STR_LIT> ; for ( CellMapType :: iterator I = Map . begin ( ) , E = Map . end ( ) ; I != E ; ++ I ) dbgs ( ) << PrintReg ( I -> first , & ME . TRI ) << <STR_LIT> << I -> second << <STR_LIT> ; }


<s> void BT :: run ( ) { reset ( ) ; assert ( FlowQ . empty ( ) ) ; using MachineFlowGraphTraits = GraphTraits < const MachineFunction * > ; const MachineBasicBlock * Entry = MachineFlowGraphTraits :: getEntryNode ( & MF ) ; unsigned MaxBN = <NUM_LIT> ;

for ( const MachineBasicBlock & B : MF ) {


<s> dbgs ( ) << <STR_LIT> << printReg ( P . first , & ME . TRI ) << <STR_LIT> << ME . getCell ( RD , ResMap ) << <STR_LIT> ; } } for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; RegisterRef RD ( MO ) ; assert ( RD . Sub == <NUM_LIT> && <STR_LIT> ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( RD . Reg ) ) continue ; bool Changed = false ; if ( ! Eval || ResMap . count ( RD . Reg ) == <NUM_LIT> ) { uint16_t DefBW = ME . getRegBitWidth ( RD ) ; RegisterCell RefC = RegisterCell :: self ( RD . Reg , DefBW ) ; if ( RefC != ME . getCell ( RD , Map ) ) { ME . putCell ( RD , RefC , Map ) ; Changed = true ; } } else { RegisterCell DefC = ME . getCell ( RD , Map ) ; RegisterCell ResC = ME . getCell ( RD , ResMap ) ; for ( uint16_t i = <NUM_LIT> , w = DefC . width ( ) ; i < w ; ++ i ) { BitValue & V = DefC [ i ] ; if ( V . Type == BitValue :: Ref && V . RefI . Reg == RD . Reg ) continue ; if ( V == ResC [ i ] ) continue ; V = ResC [ i ] ; Changed = true ;


<s> } dbgs ( ) << <STR_LIT> ; for ( const std :: pair < unsigned , RegisterCell > & P : ResMap ) { RegisterRef RD ( P . first ) ; dbgs ( ) << <STR_LIT> << printReg ( P . first , & ME . TRI ) << <STR_LIT> << ME . getCell ( RD , ResMap ) << <STR_LIT> ; } } for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; RegisterRef RD ( MO ) ; assert ( RD . Sub == <NUM_LIT> && <STR_LIT> ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( RD . Reg ) ) continue ; bool Changed = false ; if ( ! Eval || ResMap . count ( RD . Reg ) == <NUM_LIT> ) { uint16_t DefBW = ME . getRegBitWidth ( RD ) ; RegisterCell RefC = RegisterCell :: self ( RD . Reg , DefBW ) ; if ( RefC != ME . getCell ( RD , Map ) ) { ME . putCell ( RD , RefC , Map ) ; Changed = true ; } } else { RegisterCell DefC = ME . getCell ( RD , Map ) ; RegisterCell ResC = ME . getCell ( RD , ResMap ) ; for ( uint16_t i = <NUM_LIT> , w = DefC . width ( ) ; i < w ; ++ i ) { BitValue & V = DefC [ i ] ; if ( V . Type == BitValue :: Ref && V . RefI . Reg == RD . Reg ) continue ; if ( V == ResC [ i ] ) continue ; V = ResC [ i ] ; Changed = true ; } if ( Changed ) ME . putCell ( RD , DefC , Map ) ;


<s> RegisterRef ( Register R = <NUM_LIT> , unsigned S = <NUM_LIT> ) : Reg ( R ) , Sub ( S ) {


<s> ReachedBB . insert ( Edge . second ) ; const MachineBasicBlock & B = * MF . getBlockNumbered ( Edge . second ) ; MachineBasicBlock :: const_iterator It = B . begin ( ) , End = B . end ( ) ; while ( It != End && It -> isPHI ( ) ) { const MachineInstr & PI = * It ++ ; InstrExec . insert ( & PI ) ; visitPHI ( PI ) ; } if ( BlockScanned [ Edge . second ] ) continue ; BlockScanned [ Edge . second ] = true ; while ( It != End && ! It -> isBranch ( ) ) { const MachineInstr & MI = * It ++ ; InstrExec . insert ( & MI ) ; visitNonBranch ( MI ) ; } if ( It == End ) { MachineFunction :: const_iterator BIt = B . getIterator ( ) ; MachineFunction :: const_iterator Next = std :: next ( BIt ) ; if ( Next != MF . end ( ) && B . isSuccessor ( & * Next ) ) { int ThisN = B . getNumber ( ) ; int NextN = Next -> getNumber ( ) ; FlowQ . push ( CFGEdge ( ThisN , NextN ) ) ;


<s> if ( Trace ) dbgs ( ) << <STR_LIT> << ThisN << <STR_LIT> << MI ; assert ( MI . isBranch ( ) && <STR_LIT> ) ; InstrExec . insert ( & MI ) ; bool Eval = ME . evaluate ( MI , Map , BTs , FallsThrough ) ; if ( ! Eval ) { DefaultToAll = true ; FallsThrough = true ; if ( Trace ) dbgs ( ) << <STR_LIT> ; } else if ( ! DefaultToAll ) { if ( Trace ) { dbgs ( ) << <STR_LIT> ; for ( unsigned i = <NUM_LIT> , n = BTs . size ( ) ; i < n ; ++ i ) dbgs ( ) << <STR_LIT> << BTs [ i ] -> getNumber ( ) ; if ( FallsThrough ) dbgs ( ) << <STR_LIT> ; else dbgs ( ) << <STR_LIT> ; } Targets . insert ( BTs . begin ( ) , BTs . end ( ) ) ; } ++ It ; } while ( FallsThrough && It != End ) ; using succ_iterator = MachineBasicBlock :: const_succ_iterator ; if ( ! DefaultToAll ) { for ( succ_iterator I = B . succ_begin ( ) , E = B . succ_end ( ) ; I != E ; ++ I ) {


<s> if ( ! InstrExec . count ( UseI ) ) continue ; if ( UseI -> isPHI ( ) ) visitPHI ( * UseI ) ;

else if ( ! UseI -> isBranch ( ) ) visitNonBranch ( * UseI ) ;


<s> BitMask ( uint16_t b , uint16_t e ) : B ( b ) , E ( e ) {


<s> BitRef ( unsigned R = <NUM_LIT> , uint16_t P = <NUM_LIT> ) : Reg ( R ) , Pos ( P ) {


<s> BitTracker :: BitTracker ( const MachineEvaluator & E , MachineFunction & F ) : Trace ( false ) , ME ( E ) , MF ( F ) , MRI ( F . getRegInfo ( ) ) , Map ( * new CellMapType ) {


<s> BitValue ( unsigned Reg , uint16_t Pos ) : Type ( Ref ) , RefI ( Reg , Pos ) {


<s> uint16_t first ( ) const { return B ;


<s> inline bool BitTracker :: has ( unsigned Reg ) const {

return Map . find ( Reg ) != Map . end ( ) ;


<s> bool is ( unsigned T ) const { assert ( T == <NUM_LIT> || T == <NUM_LIT> ) ;

return T == <NUM_LIT> ? Type == Zero : ( T == <NUM_LIT> ? Type == One : false ) ;


<s> assert ( T == <NUM_LIT> || T == <NUM_LIT> ) ; return T == <NUM_LIT> ? Type == Zero : ( T == <NUM_LIT> ? Type == One : false ) ;


<s> uint16_t last ( ) const { return E ;


<s> CellMapType :: const_iterator F = Map . find ( Reg ) ; assert ( F != Map . end ( ) ) ; return F -> second ;


<s> MachineEvaluator ( const TargetRegisterInfo & T , MachineRegisterInfo & M ) : TRI ( T ) , MRI ( M ) {


<s> if ( Type == Ref && RefI == Self ) return false ; if ( V . Type == Top ) return false ; if ( * this == V ) return false ; if ( Type == Top ) { Type = V . Type ; RefI = V . RefI ; return true ; } Type = Ref ; RefI = Self ;


<s> return Type == Zero || Type == One ;


<s> void BT :: put ( RegisterRef RR , const RegisterCell & RC ) { ME . putCell ( RR , RC , Map ) ;


<s> assert ( BN >= <NUM_LIT> ) ; for ( EdgeSetType :: iterator I = EdgeExec . begin ( ) , E = EdgeExec . end ( ) ; I != E ; ++ I ) {


<s> RegisterCell ( uint16_t Width = DefaultBitN ) : Bits ( Width ) {


<s> RegisterRef ( const MachineOperand & MO ) : Reg ( MO . getReg ( ) ) , Sub ( MO . getSubReg ( ) ) {


<s> void BT :: reset ( ) { EdgeExec . clear ( ) ; InstrExec . clear ( ) ; Map . clear ( ) ;


<s> } BitVector BlockScanned ( MaxBN + <NUM_LIT> ) ; int EntryN = Entry -> getNumber ( ) ; FlowQ . push ( CFGEdge ( - <NUM_LIT> , EntryN ) ) ; while ( ! FlowQ . empty ( ) ) { CFGEdge Edge = FlowQ . front ( ) ; FlowQ . pop ( ) ; if ( EdgeExec . count ( Edge ) ) continue ; EdgeExec . insert ( Edge ) ; const MachineBasicBlock & B = * MF . getBlockNumbered ( Edge . second ) ; MachineBasicBlock :: const_iterator It = B . begin ( ) , End = B . end ( ) ; while ( It != End && It -> isPHI ( ) ) { const MachineInstr * PI = & * It ++ ; InstrExec . insert ( PI ) ; visitPHI ( PI ) ; } if ( BlockScanned [ Edge . second ] ) continue ; BlockScanned [ Edge . second ] = true ; while ( It != End && ! It -> isBranch ( ) ) { const MachineInstr * MI = & * It ++ ; InstrExec . insert ( MI ) ; visitNonBranch ( MI ) ; } if ( It == End ) { MachineFunction :: const_iterator BIt = & B ; MachineFunction :: const_iterator Next = std :: next ( BIt ) ; if ( Next != MF . end ( ) ) { int ThisN = B . getNumber ( ) ; int NextN = Next -> getNumber ( ) ; FlowQ . push ( CFGEdge ( ThisN , NextN ) ) ; } } else { visitBranchesFrom ( It ) ; } } if ( Trace ) { dbgs ( ) << <STR_LIT> ; for ( CellMapType :: iterator I = Map . begin ( ) , E = Map . end ( ) ; I != E ; ++ I ) dbgs ( ) << PrintReg ( I -> first , & ME . TRI ) << <STR_LIT> << I -> second << <STR_LIT> ;


<s> assert ( Map . has ( OldRR . Reg ) && <STR_LIT> ) ; BitMask OM = ME . mask ( OldRR . Reg , OldRR . Sub ) ; BitMask NM = ME . mask ( NewRR . Reg , NewRR . Sub ) ; uint16_t OMB = OM . first ( ) , OME = OM . last ( ) ; uint16_t NMB = NM . first ( ) , NME = NM . last ( ) ; ( void ) NME ; assert ( ( OME - OMB == NME - NMB ) && <STR_LIT> ) ; for ( CellMapType :: iterator I = Map . begin ( ) , E = Map . end ( ) ; I != E ; ++ I ) { RegisterCell & RC = I -> second ; for ( uint16_t i = <NUM_LIT> , w = RC . width ( ) ; i < w ; ++ i ) { BitValue & V = RC [ i ] ; if ( V . Type != BitValue :: Ref || V . RefI . Reg != OldRR . Reg ) continue ; if ( V . RefI . Pos < OMB || V . RefI . Pos > OME ) continue ; V . RefI . Reg = NewRR . Reg ; V . RefI . Pos += NMB - OMB ;


<s> virtual bool track ( const TargetRegisterClass * RC ) const { return true ;


<s> virtual bool track ( const TargetRegisterClass * RC ) const {


<s> if ( Trace ) dbgs ( ) << <STR_LIT> << ThisN << <STR_LIT> << * MI ; assert ( MI -> isBranch ( ) && <STR_LIT> ) ; InstrExec . insert ( MI ) ; bool Eval = ME . evaluate ( MI , Map , BTs , FallsThrough ) ; if ( ! Eval ) { DefaultToAll = true ; FallsThrough = true ; if ( Trace ) dbgs ( ) << <STR_LIT> ; } else if ( ! DefaultToAll ) { if ( Trace ) { dbgs ( ) << <STR_LIT> ; for ( unsigned i = <NUM_LIT> , n = BTs . size ( ) ; i < n ; ++ i ) dbgs ( ) << <STR_LIT> << BTs [ i ] -> getNumber ( ) ; if ( FallsThrough ) dbgs ( ) << <STR_LIT> ; else dbgs ( ) << <STR_LIT> ; } Targets . insert ( BTs . begin ( ) , BTs . end ( ) ) ; } ++ It ; } while ( FallsThrough && It != End ) ; typedef MachineBasicBlock :: const_succ_iterator succ_iterator ; if ( ! DefaultToAll ) { for ( succ_iterator I = B . succ_begin ( ) , E = B . succ_end ( ) ; I != E ; ++ I ) { const MachineBasicBlock * SB = * I ; if ( SB -> isLandingPad ( ) ) Targets . insert ( SB ) ; } if ( FallsThrough ) { MachineFunction :: const_iterator BIt = & B ; MachineFunction :: const_iterator Next = std :: next ( BIt ) ; if ( Next != MF . end ( ) ) Targets . insert ( & * Next ) ; } } else { for ( succ_iterator I = B . succ_begin ( ) , E = B . succ_end ( ) ; I != E ; ++ I ) Targets . insert ( * I ) ; } for ( unsigned i = <NUM_LIT> , n = Targets . size ( ) ; i < n ; ++ i ) {


<s> dbgs ( ) << <STR_LIT> << PrintReg ( I -> first , & ME . TRI ) << <STR_LIT> << ME . getCell ( RD , ResMap ) << <STR_LIT> ; } } for ( unsigned i = <NUM_LIT> , n = MI -> getNumOperands ( ) ; i < n ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; RegisterRef RD ( MO ) ; assert ( RD . Sub == <NUM_LIT> && <STR_LIT> ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( RD . Reg ) ) continue ; bool Changed = false ; if ( ! Eval || ! ResMap . has ( RD . Reg ) ) { uint16_t DefBW = ME . getRegBitWidth ( RD ) ; RegisterCell RefC = RegisterCell :: self ( RD . Reg , DefBW ) ; if ( RefC != ME . getCell ( RD , Map ) ) { ME . putCell ( RD , RefC , Map ) ; Changed = true ; } } else { RegisterCell DefC = ME . getCell ( RD , Map ) ; RegisterCell ResC = ME . getCell ( RD , ResMap ) ; for ( uint16_t i = <NUM_LIT> , w = DefC . width ( ) ; i < w ; ++ i ) { BitValue & V = DefC [ i ] ; if ( V . Type == BitValue :: Ref && V . RefI . Reg == RD . Reg ) continue ; if ( V == ResC [ i ] ) continue ; V = ResC [ i ] ; Changed = true ; }


<s> int ThisN = PI -> getParent ( ) -> getNumber ( ) ; if ( Trace ) dbgs ( ) << <STR_LIT> << ThisN << <STR_LIT> << * PI ; const MachineOperand & MD = PI -> getOperand ( <NUM_LIT> ) ; assert ( MD . getSubReg ( ) == <NUM_LIT> && <STR_LIT> ) ; RegisterRef DefRR ( MD ) ; uint16_t DefBW = ME . getRegBitWidth ( DefRR ) ; RegisterCell DefC = ME . getCell ( DefRR , Map ) ; if ( DefC == RegisterCell :: self ( DefRR . Reg , DefBW ) ) return ; bool Changed = false ; for ( unsigned i = <NUM_LIT> , n = PI -> getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) { const MachineBasicBlock * PB = PI -> getOperand ( i + <NUM_LIT> ) . getMBB ( ) ; int PredN = PB -> getNumber ( ) ; if ( Trace ) dbgs ( ) << <STR_LIT> << PredN << <STR_LIT> << ThisN ; if ( ! EdgeExec . count ( CFGEdge ( PredN , ThisN ) ) ) { if ( Trace ) dbgs ( ) << <STR_LIT> ; continue ; } RegisterRef RU = PI -> getOperand ( i ) ; RegisterCell ResC = ME . getCell ( RU , Map ) ; if ( Trace ) dbgs ( ) << <STR_LIT> << PrintReg ( RU . Reg , & ME . TRI , RU . Sub ) << <STR_LIT> << ResC << <STR_LIT> ; Changed |= DefC . meet ( ResC , DefRR . Reg ) ; } if ( Changed ) { if ( Trace ) dbgs ( ) << <STR_LIT> << PrintReg ( DefRR . Reg , & ME . TRI , DefRR . Sub ) << <STR_LIT> << DefC << <STR_LIT> ;


<s> MachineInstr * UseI = I -> getParent ( ) ; if ( ! InstrExec . count ( UseI ) ) continue ; if ( UseI -> isPHI ( ) ) visitPHI ( UseI ) ;

else if ( ! UseI -> isBranch ( ) ) visitNonBranch ( UseI ) ;


<s> typedef MachineRegisterInfo :: use_nodbg_iterator use_iterator ; use_iterator End = MRI . use_nodbg_end ( ) ; for ( use_iterator I = MRI . use_nodbg_begin ( Reg ) ; I != End ; ++ I ) { MachineInstr * UseI = I -> getParent ( ) ; if ( ! InstrExec . count ( UseI ) ) continue ;

if ( UseI -> isPHI ( ) ) visitPHI ( UseI ) ;


<s> uint16_t width ( ) const { return Bits . size ( ) ;


<s> size_t <ISA_LIT>AbsoluteStub :: alignment ( ) const {


<s> return new <ISA_LIT>AbsoluteStub ( m_pData , m_Size , fixup_begin ( ) , fixup_end ( ) ) ;


<s> const uint8_t * <ISA_LIT>AbsoluteStub :: getContent ( ) const { return reinterpret_cast < const uint8_t * > ( m_pData ) ;


<s> for ( const_fixup_iterator it = pBegin , ie = pEnd ; it != ie ; ++ it ) addFixup ( * * it ) ;


<s> switch ( pReloc . type ( ) ) { case llvm :: ELF :: R_HEX_B22_PCREL : nbits = <NUM_LIT> ; break ; case llvm :: ELF :: R_HEX_B15_PCREL : nbits = <NUM_LIT> ; break ; case llvm :: ELF :: R_HEX_B7_PCREL : nbits = <NUM_LIT> ; break ; case llvm :: ELF :: R_HEX_B13_PCREL :


<s> const std :: string & <ISA_LIT>AbsoluteStub :: name ( ) const { return m_Name ;


<s> <ISA_LIT>AbsoluteStub :: ~ <ISA_LIT>AbsoluteStub ( ) {


<s> llvm :: Optional < ArchEnum > GetCpu ( ArchCont const & ArchList , Val CPUString ) { llvm :: Optional < ArchEnum > Res ;

auto Entry = ArchList . find ( CPUString ) ;


<s> if ( Entry != ArchList . end ( ) ) Res = Entry -> second ;


<s> bool ValidArch ( ArchCont const & ArchList , Val HexArch ) { return std :: any_of ( std :: begin ( ArchList ) , std :: end ( ArchList ) , [ HexArch ] ( Val V ) { return V == HexArch ; } ) ;


<s> break ; case fixup_<ISA_LIT>_B7_PCREL_X : case fixup_<ISA_LIT>_B9_PCREL_X : case fixup_<ISA_LIT>_B13_PCREL_X : case fixup_<ISA_LIT>_B15_PCREL_X : case fixup_<ISA_LIT>_B22_PCREL_X : Value &= <NUM_LIT> ; break ; case fixup_<ISA_LIT>_B32_PCREL_X : case fixup_<ISA_LIT>_GD_PLT_B32_PCREL_X : case fixup_<ISA_LIT>_LD_PLT_B32_PCREL_X : Value >>= <NUM_LIT> ; break ;


<s> Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B9_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; LLVM_FALLTHROUGH ; case fixup_<ISA_LIT>_B9_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B13_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; LLVM_FALLTHROUGH ; case fixup_<ISA_LIT>_B13_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B15_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; LLVM_FALLTHROUGH ; case fixup_<ISA_LIT>_B15_PCREL_X : InstMask = <NUM_LIT> ;

Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ;


<s> uint32_t Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Kind ) ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; char * InstAddr = Data . data ( ) + Offset ; Value = adjustFixupValue ( Kind , FixupValue ) ; if ( ! Value ) return ; int sValue = ( int ) Value ; switch ( ( unsigned ) Kind ) { default : return ; case fixup_<ISA_LIT>_B7_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; LLVM_FALLTHROUGH ; case fixup_<ISA_LIT>_B7_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B9_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; LLVM_FALLTHROUGH ; case fixup_<ISA_LIT>_B9_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B13_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; LLVM_FALLTHROUGH ; case fixup_<ISA_LIT>_B13_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B15_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; LLVM_FALLTHROUGH ; case fixup_<ISA_LIT>_B15_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B22_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; LLVM_FALLTHROUGH ; case fixup_<ISA_LIT>_B22_PCREL_X : InstMask = <NUM_LIT> ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( Target const & T , MCRegisterInfo const & , const Triple & TT , StringRef CPU , const MCTargetOptions & Options ) { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; StringRef CPUString = <ISA_LIT>_MC :: select<ISA_LIT>CPU ( TT , CPU ) ; return new <ISA_LIT>AsmBackend ( T , TT , OSABI , CPUString ) ;


<s> return create<ISA_LIT>ELFObjectWriter ( OS , OSABI , CPU ) ;


<s> switch ( J . getKind ( ) ) { default : break ; case MCFragment :: FT_Align : { auto Size = Asm . computeFragmentSize ( Layout , J ) ; for ( auto K = J . getIterator ( ) ; K != Fragments . begin ( ) && Size >= HEXAGON_PACKET_SIZE ; ) { -- K ; switch ( K -> getKind ( ) ) { default : break ; case MCFragment :: FT_Align : { Size = <NUM_LIT> ; break ; } case MCFragment :: FT_Relaxable : { MCContext & Context = Asm . getContext ( ) ; auto & RF = cast < MCRelaxableFragment > ( * K ) ; auto & Inst = const_cast < MCInst & > ( RF . getInst ( ) ) ; while ( Size > <NUM_LIT> && <ISA_LIT>MCInstrInfo :: bundleSize ( Inst ) < <NUM_LIT> ) { MCInst * Nop = new ( Context ) MCInst ; Nop -> setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createInst ( Nop ) ) ; Size -= <NUM_LIT> ; if ( ! <ISA_LIT>MCChecker ( Context , * MCII , RF . getSubtargetInfo ( ) , Inst , * Context . getRegisterInfo ( ) , false ) . check ( ) ) { Inst . erase ( Inst . end ( ) - <NUM_LIT> ) ; Size = <NUM_LIT> ;


<s> auto & RF = cast < MCRelaxableFragment > ( * K ) ; auto & Inst = const_cast < MCInst & > ( RF . getInst ( ) ) ; while ( Size > <NUM_LIT> && <ISA_LIT>MCInstrInfo :: bundleSize ( Inst ) < <NUM_LIT> ) { MCInst * Nop = new ( Context ) MCInst ; Nop -> setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createInst ( Nop ) ) ; Size -= <NUM_LIT> ; if ( ! <ISA_LIT>MCChecker ( Context , * MCII , RF . getSubtargetInfo ( ) , Inst , * Context . getRegisterInfo ( ) , false ) . check ( ) ) { Inst . erase ( Inst . end ( ) - <NUM_LIT> ) ; Size = <NUM_LIT> ; } }

bool Error = <ISA_LIT>MCShuffle ( Context , true , * MCII , RF . getSubtargetInfo ( ) , Inst ) ;


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { llvm_unreachable ( <STR_LIT> ) ;


<s> break ; case fixup_<ISA_LIT>_B9_PCREL : maxValue = <NUM_LIT> << <NUM_LIT> ; break ; case fixup_<ISA_LIT>_B15_PCREL : maxValue = <NUM_LIT> << <NUM_LIT> ; break ; case fixup_<ISA_LIT>_B22_PCREL : maxValue = <NUM_LIT> << <NUM_LIT> ; break ; default : maxValue = INT64_MAX ; break ; } bool isFarAway = - maxValue > sValue || sValue > maxValue - <NUM_LIT> ; if ( isFarAway ) { if ( <ISA_LIT>MCInstrInfo :: bundleSize ( MCB ) < HEXAGON_PACKET_SIZE ) { ++ relaxedCnt ; * RelaxTarget = & MCI ; setExtender ( Layout . getAssembler ( ) . getContext ( ) ) ; return true ;


<s> case FK_Data_4 : case FK_PCRel_4 : case fixup_<ISA_LIT>_32 : case fixup_<ISA_LIT>_B32_PCREL_X : case fixup_<ISA_LIT>_B22_PCREL : case fixup_<ISA_LIT>_B22_PCREL_X : case fixup_<ISA_LIT>_B15_PCREL : case fixup_<ISA_LIT>_B15_PCREL_X : case fixup_<ISA_LIT>_B13_PCREL :


<s> unsigned getNumFixupKinds ( ) const override {


<s> std :: stringstream errStr ; errStr << <STR_LIT> << FixupValue << <STR_LIT> << IntMin . getSExtValue ( ) << <STR_LIT> << IntMax . getSExtValue ( ) << <STR_LIT> << fixupStr << <STR_LIT> ; llvm_unreachable ( errStr . str ( ) . c_str ( ) ) ;


<s> <ISA_LIT>AsmBackend ( const Target & T , const Triple & TT , uint8_t OSABI , StringRef CPU ) :

OSABI ( OSABI ) , CPU ( CPU ) , MCII ( T . createMCInstrInfo ( ) ) , RelaxTarget ( new MCInst * ) , Extender ( nullptr ) {


<s> bool isInstRelaxable ( MCInst const & HMI ) const { const MCInstrDesc & MCID = <ISA_LIT>MCInstrInfo :: getDesc ( * MCII , HMI ) ; bool Relaxable = false ; if ( llvm :: <ISA_LIT>MCInstrInfo :: getType ( * MCII , HMI ) == <STR_LIT> || ( llvm :: <ISA_LIT>MCInstrInfo :: getType ( * MCII , HMI ) == <STR_LIT> && MCID . isBranch ( ) ) || ( llvm :: <ISA_LIT>MCInstrInfo :: getType ( * MCII , HMI ) == <STR_LIT> && MCID . isBranch ( ) ) || ( llvm :: <ISA_LIT>MCInstrInfo :: getType ( * MCII , HMI ) == <STR_LIT> && HMI . getOpcode ( ) != <STR_LIT> ) ) if ( <ISA_LIT>MCInstrInfo :: isExtendable ( * MCII , HMI ) ) {


<s> bool mayNeedRelaxation ( MCInst const & Inst ) const override {


<s> SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallString < <NUM_LIT> > Code ; raw_svector_ostream VecOS ( Code ) ; E . encodeInstruction ( HMB , VecOS , Fixups , RF . getSubtargetInfo ( ) ) ; RF . setInst ( HMB ) ; RF . getContents ( ) = Code ; RF . getFixups ( ) = Fixups ;


<s> void setExtender ( MCContext & Context ) const {

if ( Extender == nullptr ) const_cast < <ISA_LIT>AsmBackend * > ( this ) -> Extender = new ( Context ) MCInst ;


<s> if ( Extender == nullptr ) const_cast < <ISA_LIT>AsmBackend * > ( this ) -> Extender = new ( Context ) MCInst ;


<s> llvm_unreachable ( <STR_LIT> ) ; case fixup_<ISA_LIT>_LO16 : case fixup_<ISA_LIT>_HI16 : case fixup_<ISA_LIT>_16 : case fixup_<ISA_LIT>_8 : case fixup_<ISA_LIT>_GPREL16_0 : case fixup_<ISA_LIT>_GPREL16_1 : case fixup_<ISA_LIT>_GPREL16_2 : case fixup_<ISA_LIT>_GPREL16_3 : case fixup_<ISA_LIT>_HL16 : case fixup_<ISA_LIT>_32_6_X : case fixup_<ISA_LIT>_16_X : case fixup_<ISA_LIT>_12_X : case fixup_<ISA_LIT>_11_X : case fixup_<ISA_LIT>_10_X : case fixup_<ISA_LIT>_9_X : case fixup_<ISA_LIT>_8_X : case fixup_<ISA_LIT>_7_X : case fixup_<ISA_LIT>_6_X : case fixup_<ISA_LIT>_COPY : case fixup_<ISA_LIT>_GLOB_DAT : case fixup_<ISA_LIT>_JMP_SLOT : case fixup_<ISA_LIT>_RELATIVE : case fixup_<ISA_LIT>_PLT_B22_PCREL : case fixup_<ISA_LIT>_GOTREL_LO16 : case fixup_<ISA_LIT>_GOTREL_HI16 : case fixup_<ISA_LIT>_GOTREL_32 : case fixup_<ISA_LIT>_GOT_LO16 : case fixup_<ISA_LIT>_GOT_HI16 : case fixup_<ISA_LIT>_GOT_32 : case fixup_<ISA_LIT>_GOT_16 : case fixup_<ISA_LIT>_DTPMOD_32 : case fixup_<ISA_LIT>_DTPREL_LO16 : case fixup_<ISA_LIT>_DTPREL_HI16 : case fixup_<ISA_LIT>_DTPREL_32 : case fixup_<ISA_LIT>_DTPREL_16 : case fixup_<ISA_LIT>_GD_PLT_B22_PCREL : case fixup_<ISA_LIT>_LD_PLT_B22_PCREL : case fixup_<ISA_LIT>_GD_GOT_LO16 : case fixup_<ISA_LIT>_GD_GOT_HI16 : case fixup_<ISA_LIT>_GD_GOT_32 : case fixup_<ISA_LIT>_GD_GOT_16 : case fixup_<ISA_LIT>_LD_GOT_LO16 : case fixup_<ISA_LIT>_LD_GOT_HI16 : case fixup_<ISA_LIT>_LD_GOT_32 : case fixup_<ISA_LIT>_LD_GOT_16 : case fixup_<ISA_LIT>_IE_LO16 : case fixup_<ISA_LIT>_IE_HI16 : case fixup_<ISA_LIT>_IE_32 : case fixup_<ISA_LIT>_IE_16 : case fixup_<ISA_LIT>_IE_GOT_LO16 : case fixup_<ISA_LIT>_IE_GOT_HI16 : case fixup_<ISA_LIT>_IE_GOT_32 : case fixup_<ISA_LIT>_IE_GOT_16 : case fixup_<ISA_LIT>_TPREL_LO16 : case fixup_<ISA_LIT>_TPREL_HI16 : case fixup_<ISA_LIT>_TPREL_32 : case fixup_<ISA_LIT>_TPREL_16 : case fixup_<ISA_LIT>_GOTREL_32_6_X : case fixup_<ISA_LIT>_GOTREL_16_X : case fixup_<ISA_LIT>_GOTREL_11_X : case fixup_<ISA_LIT>_GOT_32_6_X : case fixup_<ISA_LIT>_GOT_16_X : case fixup_<ISA_LIT>_GOT_11_X : case fixup_<ISA_LIT>_DTPREL_32_6_X : case fixup_<ISA_LIT>_DTPREL_16_X : case fixup_<ISA_LIT>_DTPREL_11_X : case fixup_<ISA_LIT>_GD_GOT_32_6_X : case fixup_<ISA_LIT>_GD_GOT_16_X : case fixup_<ISA_LIT>_GD_GOT_11_X : case fixup_<ISA_LIT>_LD_GOT_32_6_X : case fixup_<ISA_LIT>_LD_GOT_16_X : case fixup_<ISA_LIT>_LD_GOT_11_X : case fixup_<ISA_LIT>_IE_32_6_X : case fixup_<ISA_LIT>_IE_16_X : case fixup_<ISA_LIT>_IE_GOT_32_6_X : case fixup_<ISA_LIT>_IE_GOT_16_X : case fixup_<ISA_LIT>_IE_GOT_11_X : case fixup_<ISA_LIT>_TPREL_32_6_X :


<s> MCInst * Result = Extender ; const_cast < <ISA_LIT>AsmBackend * > ( this ) -> Extender = nullptr ;


<s> while ( Count ) { Count -= HEXAGON_INSTR_SIZE ; uint32_t ParseBits = ( Count % ( HEXAGON_PACKET_SIZE * HEXAGON_INSTR_SIZE ) ) ? ParseIn : ParseEnd ;


<s> OW -> write8 ( <NUM_LIT> ) ; } while ( Count ) { Count -= HEXAGON_INSTR_SIZE ;

uint32_t ParseBits = ( Count % ( HEXAGON_PACKET_SIZE * HEXAGON_INSTR_SIZE ) ) ? ParseIn : ParseEnd ;


<s> case fixup_<ISA_LIT>_B15_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B22_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; LLVM_FALLTHROUGH ; case fixup_<ISA_LIT>_B22_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B32_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( Value & <NUM_LIT> ) ; break ; case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case fixup_<ISA_LIT>_32 : InstMask = <NUM_LIT> ; Reloc = Value ; break ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << getFixupKindInfo ( Kind ) . Name << <STR_LIT> << ( unsigned ) Kind << <STR_LIT> ) ;

LLVM_DEBUG ( uint32_t OldData = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumBytes ; i ++ ) OldData |= ( InstAddr [ i ] << ( i * <NUM_LIT> ) ) & ( <NUM_LIT> << ( i * <NUM_LIT> ) ) ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( Target const & T , const MCSubtargetInfo & STI , MCRegisterInfo const & , const MCTargetOptions & Options ) { const Triple & TT = STI . getTargetTriple ( ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ;

StringRef CPUString = <ISA_LIT>_MC :: select<ISA_LIT>CPU ( STI . getCPU ( ) ) ;


<s> const Triple & TT = STI . getTargetTriple ( ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ;


<s> return create<ISA_LIT>ELFObjectWriter ( OSABI , CPU ) ;


<s> * RelaxTarget = & MCI ; setExtender ( Layout . getAssembler ( ) . getContext ( ) ) ; return true ; } else { return false ; } break ; } } } MCFixupKind Kind = Fixup . getKind ( ) ; int64_t sValue = Value ; int64_t maxValue ; switch ( ( unsigned ) Kind ) { case fixup_<ISA_LIT>_B7_PCREL : maxValue = <NUM_LIT> << <NUM_LIT> ; break ; case fixup_<ISA_LIT>_B9_PCREL : maxValue = <NUM_LIT> << <NUM_LIT> ; break ; case fixup_<ISA_LIT>_B15_PCREL : maxValue = <NUM_LIT> << <NUM_LIT> ; break ; case fixup_<ISA_LIT>_B22_PCREL :


<s> <ISA_LIT>AsmBackend ( const Target & T , const Triple & TT , uint8_t OSABI , StringRef CPU ) : MCAsmBackend ( <STR_LIT> ) , OSABI ( OSABI ) , CPU ( CPU ) , MCII ( T . createMCInstrInfo ( ) ) , RelaxTarget ( new MCInst * ) , Extender ( nullptr ) {


<s> if ( * RelaxTarget == & CrntHMI ) { Update = true ; assert ( ( <ISA_LIT>MCInstrInfo :: bundleSize ( Res ) < HEXAGON_PACKET_SIZE ) && <STR_LIT> ) ; MCInst * HMIx = takeExtender ( ) ; * HMIx = <ISA_LIT>MCInstrInfo :: deriveExtender ( * MCII , CrntHMI , <ISA_LIT>MCInstrInfo :: getExtendableOperand ( * MCII , CrntHMI ) ) ; Res . addOperand ( MCOperand :: createInst ( HMIx ) ) ; * RelaxTarget = nullptr ; } Res . addOperand ( MCOperand :: createInst ( I . getInst ( ) ) ) ; } ( void ) Update ;


<s> static const uint32_t Nopcode = <NUM_LIT> , ParseIn = <NUM_LIT> , ParseEnd = <NUM_LIT> ; while ( Count % HEXAGON_INSTR_SIZE ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Count % HEXAGON_INSTR_SIZE << <STR_LIT> << HEXAGON_INSTR_SIZE << <STR_LIT> ) ; -- Count ; OS << '\0' ;


<s> case fixup_<ISA_LIT>_B7_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; LLVM_FALLTHROUGH ; case fixup_<ISA_LIT>_B7_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B9_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; LLVM_FALLTHROUGH ; case fixup_<ISA_LIT>_B9_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B13_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; LLVM_FALLTHROUGH ; case fixup_<ISA_LIT>_B13_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B15_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; LLVM_FALLTHROUGH ; case fixup_<ISA_LIT>_B15_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B22_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; LLVM_FALLTHROUGH ; case fixup_<ISA_LIT>_B22_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B32_PCREL_X :


<s> -- K ; switch ( K -> getKind ( ) ) { default : break ; case MCFragment :: FT_Align : { Size = <NUM_LIT> ; break ; } case MCFragment :: FT_Relaxable : { MCContext & Context = Asm . getContext ( ) ; auto & RF = cast < MCRelaxableFragment > ( * K ) ; auto & Inst = const_cast < MCInst & > ( RF . getInst ( ) ) ; while ( Size > <NUM_LIT> && <ISA_LIT>MCInstrInfo :: bundleSize ( Inst ) < <NUM_LIT> ) { MCInst * Nop = new ( Context ) MCInst ; Nop -> setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createInst ( Nop ) ) ; Size -= <NUM_LIT> ; if ( ! <ISA_LIT>MCChecker ( Context , * MCII , * RF . getSubtargetInfo ( ) , Inst , * Context . getRegisterInfo ( ) , false ) . check ( ) ) { Inst . erase ( Inst . end ( ) - <NUM_LIT> ) ; Size = <NUM_LIT> ; } }

bool Error = <ISA_LIT>MCShuffle ( Context , true , * MCII , * RF . getSubtargetInfo ( ) , Inst ) ;


<s> K != Fragments . begin ( ) && Size >= HEXAGON_PACKET_SIZE ; ) { -- K ; switch ( K -> getKind ( ) ) { default : break ; case MCFragment :: FT_Align : { Size = <NUM_LIT> ; break ; } case MCFragment :: FT_Relaxable : { MCContext & Context = Asm . getContext ( ) ; auto & RF = cast < MCRelaxableFragment > ( * K ) ; auto & Inst = const_cast < MCInst & > ( RF . getInst ( ) ) ; while ( Size > <NUM_LIT> && <ISA_LIT>MCInstrInfo :: bundleSize ( Inst ) < <NUM_LIT> ) { MCInst * Nop = new ( Context ) MCInst ; Nop -> setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createInst ( Nop ) ) ; Size -= <NUM_LIT> ; if ( ! <ISA_LIT>MCChecker ( Context , * MCII , * RF . getSubtargetInfo ( ) , Inst , * Context . getRegisterInfo ( ) , false ) . check ( ) ) { Inst . erase ( Inst . end ( ) - <NUM_LIT> ) ; Size = <NUM_LIT> ; } } bool Error = <ISA_LIT>MCShuffle ( Context , true , * MCII , * RF . getSubtargetInfo ( ) , Inst ) ; ( void ) Error ; ReplaceInstruction ( Asm . getEmitter ( ) , RF , Inst ) ; Layout . invalidateFragmentsFrom ( & RF ) ; Size = <NUM_LIT> ; break ; }


<s> bool mayNeedRelaxation ( MCInst const & Inst , const MCSubtargetInfo & STI ) const override { return true ;


<s> SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallString < <NUM_LIT> > Code ; raw_svector_ostream VecOS ( Code ) ; E . encodeInstruction ( HMB , VecOS , Fixups , * RF . getSubtargetInfo ( ) ) ; RF . setInst ( HMB ) ; RF . getContents ( ) = Code ;


<s> void ReplaceInstruction ( MCCodeEmitter & E , MCRelaxableFragment & RF , MCInst & HMB ) const { SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallString < <NUM_LIT> > Code ; raw_svector_ostream VecOS ( Code ) ;

E . encodeInstruction ( HMB , VecOS , Fixups , * RF . getSubtargetInfo ( ) ) ;


<s> uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( Triple ( TT ) . getOS ( ) ) ;

return new ELF<ISA_LIT>AsmBackend ( T , OSABI ) ;


<s> ELF<ISA_LIT>AsmBackend ( Target const & T , uint8_t OSABI ) : <ISA_LIT>AsmBackend ( T ) , OSABI ( OSABI ) {


<s> <ISA_LIT>AsmBackend ( Target const & ) {


<s> void relaxInstruction ( MCInst const & , MCInst & ) const override { llvm_unreachable ( <STR_LIT> ) ;


<s> void relaxInstruction ( MCInst const & , MCInst & ) const override {


<s> bool writeNopData ( uint64_t , MCObjectWriter * ) const override {


<s> auto & RF = cast < MCRelaxableFragment > ( * K ) ; auto & Inst = const_cast < MCInst & > ( RF . getInst ( ) ) ; while ( Size > <NUM_LIT> && <ISA_LIT>MCInstrInfo :: bundleSize ( Inst ) < MaxPacketSize ) { MCInst * Nop = Context . createMCInst ( ) ; Nop -> setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createInst ( Nop ) ) ; Size -= <NUM_LIT> ; if ( ! <ISA_LIT>MCChecker ( Context , * MCII , * RF . getSubtargetInfo ( ) , Inst , * Context . getRegisterInfo ( ) , false ) . check ( ) ) {

Inst . erase ( Inst . end ( ) - <NUM_LIT> ) ;


<s> int64_t sValue = Value ; int64_t maxValue ; switch ( ( unsigned ) Kind ) { case fixup_<ISA_LIT>_B7_PCREL : maxValue = <NUM_LIT> << <NUM_LIT> ; break ; case fixup_<ISA_LIT>_B9_PCREL : maxValue = <NUM_LIT> << <NUM_LIT> ; break ; case fixup_<ISA_LIT>_B15_PCREL : maxValue = <NUM_LIT> << <NUM_LIT> ; break ; case fixup_<ISA_LIT>_B22_PCREL : maxValue = <NUM_LIT> << <NUM_LIT> ; break ; default : maxValue = INT64_MAX ; break ; } bool isFarAway = - maxValue > sValue || sValue > maxValue - <NUM_LIT> ; if ( isFarAway ) {

if ( <ISA_LIT>MCInstrInfo :: bundleSize ( MCB ) < HEXAGON_PACKET_SIZE ) {


<s> <ISA_LIT>AsmBackend ( const Target & T , const Triple & TT , uint8_t OSABI , StringRef CPU ) : MCAsmBackend ( <STR_LIT> ) , OSABI ( OSABI ) , CPU ( CPU ) , relaxedCnt ( <NUM_LIT> ) , MCII ( T . createMCInstrInfo ( ) ) , RelaxTarget ( new MCInst * ) , Extender ( nullptr ) , MaxPacketSize ( <ISA_LIT>MCInstrInfo :: packetSize ( CPU ) ) {


<s> for ( auto & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( Inst ) ) { MCInst & CrntHMI = const_cast < MCInst & > ( * I . getInst ( ) ) ; if ( * RelaxTarget == & CrntHMI ) { Update = true ; assert ( ( <ISA_LIT>MCInstrInfo :: bundleSize ( Res ) < HEXAGON_PACKET_SIZE ) && <STR_LIT> ) ;


<s> if ( Extender == nullptr ) const_cast < <ISA_LIT>AsmBackend * > ( this ) -> Extender = Context . createMCInst ( ) ;


<s> void setExtender ( MCContext & Context ) const {

if ( Extender == nullptr ) const_cast < <ISA_LIT>AsmBackend * > ( this ) -> Extender = Context . createMCInst ( ) ;


<s> case fixup_<ISA_LIT>_GD_GOT_16 : case fixup_<ISA_LIT>_LD_GOT_LO16 : case fixup_<ISA_LIT>_LD_GOT_HI16 : case fixup_<ISA_LIT>_LD_GOT_32 : case fixup_<ISA_LIT>_LD_GOT_16 : case fixup_<ISA_LIT>_IE_LO16 : case fixup_<ISA_LIT>_IE_HI16 : case fixup_<ISA_LIT>_IE_32 : case fixup_<ISA_LIT>_IE_16 : case fixup_<ISA_LIT>_IE_GOT_LO16 : case fixup_<ISA_LIT>_IE_GOT_HI16 : case fixup_<ISA_LIT>_IE_GOT_32 : case fixup_<ISA_LIT>_IE_GOT_16 : case fixup_<ISA_LIT>_TPREL_LO16 : case fixup_<ISA_LIT>_TPREL_HI16 : case fixup_<ISA_LIT>_TPREL_32 : case fixup_<ISA_LIT>_TPREL_16 : case fixup_<ISA_LIT>_GOTREL_32_6_X : case fixup_<ISA_LIT>_GOTREL_16_X : case fixup_<ISA_LIT>_GOTREL_11_X : case fixup_<ISA_LIT>_GOT_32_6_X : case fixup_<ISA_LIT>_GOT_16_X : case fixup_<ISA_LIT>_GOT_11_X : case fixup_<ISA_LIT>_DTPREL_32_6_X : case fixup_<ISA_LIT>_DTPREL_16_X : case fixup_<ISA_LIT>_DTPREL_11_X : case fixup_<ISA_LIT>_GD_GOT_32_6_X : case fixup_<ISA_LIT>_GD_GOT_16_X : case fixup_<ISA_LIT>_GD_GOT_11_X : case fixup_<ISA_LIT>_LD_GOT_32_6_X : case fixup_<ISA_LIT>_LD_GOT_16_X : case fixup_<ISA_LIT>_LD_GOT_11_X : case fixup_<ISA_LIT>_IE_32_6_X : case fixup_<ISA_LIT>_IE_16_X : case fixup_<ISA_LIT>_IE_GOT_32_6_X : case fixup_<ISA_LIT>_IE_GOT_16_X : case fixup_<ISA_LIT>_IE_GOT_11_X : case fixup_<ISA_LIT>_TPREL_32_6_X : case fixup_<ISA_LIT>_TPREL_16_X : case fixup_<ISA_LIT>_TPREL_11_X : case fixup_<ISA_LIT>_32_PCREL : case fixup_<ISA_LIT>_6_PCREL_X : case fixup_<ISA_LIT>_23_REG : case fixup_<ISA_LIT>_27_REG : case fixup_<ISA_LIT>_GD_PLT_B22_PCREL_X : case fixup_<ISA_LIT>_GD_PLT_B32_PCREL_X : case fixup_<ISA_LIT>_LD_PLT_B22_PCREL_X : case fixup_<ISA_LIT>_LD_PLT_B32_PCREL_X : return true ; case fixup_<ISA_LIT>_B22_PCREL : break ; case fixup_<ISA_LIT>_B13_PCREL : case fixup_<ISA_LIT>_B13_PCREL_X : case fixup_<ISA_LIT>_B32_PCREL_X : case fixup_<ISA_LIT>_B22_PCREL_X : case fixup_<ISA_LIT>_B15_PCREL : case fixup_<ISA_LIT>_B15_PCREL_X : case fixup_<ISA_LIT>_B9_PCREL : case fixup_<ISA_LIT>_B9_PCREL_X : case fixup_<ISA_LIT>_B7_PCREL : case fixup_<ISA_LIT>_B7_PCREL_X :


<s> while ( Count % HEXAGON_INSTR_SIZE ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Count % HEXAGON_INSTR_SIZE << <STR_LIT> << HEXAGON_INSTR_SIZE << <STR_LIT> ) ; -- Count ; OS << '\0' ; } while ( Count ) {


<s> Count -= HEXAGON_INSTR_SIZE ; uint32_t ParseBits = ( Count % ( MaxPacketSize * HEXAGON_INSTR_SIZE ) ) ? ParseIn : ParseEnd ; <STR_LIT> :: write < uint32_t > ( OS , Nopcode | ParseBits , Endian ) ; }


<s> uint32_t ParseBits = ( Count % ( MaxPacketSize * HEXAGON_INSTR_SIZE ) ) ? ParseIn : ParseEnd ; <STR_LIT> :: write < uint32_t > ( OS , Nopcode | ParseBits , Endian ) ; }


<s> if ( ! <ISA_LIT>MCChecker ( Context , * MCII , * RF . getSubtargetInfo ( ) , Inst , * Context . getRegisterInfo ( ) , false ) . check ( ) ) { Inst . erase ( Inst . end ( ) - <NUM_LIT> ) ; Size = <NUM_LIT> ; } } bool Error = <ISA_LIT>MCShuffle ( Context , true , * MCII , * RF . getSubtargetInfo ( ) , Inst ) ; ( void ) Error ; ReplaceInstruction ( Asm . getEmitter ( ) , RF , Inst ) ; Layout . invalidateFragmentsFrom ( & RF ) ; Size = <NUM_LIT> ; break ; } }


<s> return create<ISA_LIT>ELFObjectWriter ( OS , OSABI , CPU ) ;


<s> InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B15_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; case fixup_<ISA_LIT>_B15_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B22_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; case fixup_<ISA_LIT>_B22_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B32_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( Value & <NUM_LIT> ) ; break ; case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case fixup_<ISA_LIT>_32 : InstMask = <NUM_LIT> ; Reloc = Value ; break ; } DEBUG ( dbgs ( ) << <STR_LIT> << getFixupKindInfo ( Kind ) . Name << <STR_LIT> << ( unsigned ) Kind << <STR_LIT> ) ; DEBUG ( uint32_t OldData = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumBytes ; i ++ ) OldData |= ( InstAddr [ i ] << ( i * <NUM_LIT> ) ) & ( <NUM_LIT> << ( i * <NUM_LIT> ) ) ;

dbgs ( ) << <STR_LIT> ; dbgs ( ) . write_hex ( Value ) << <STR_LIT> ; dbgs ( ) . write_hex ( FixupValue ) << <STR_LIT> << Offset << <STR_LIT> << DataSize << <STR_LIT> ; dbgs ( ) . write_hex ( OldData ) << <STR_LIT> ; dbgs ( ) . write_hex ( Reloc ) ; ) ;


<s> MCAsmBackend * create<ISA_LIT>AsmBackend ( Target const & T , MCRegisterInfo const & , const Triple & TT , StringRef CPU , const MCTargetOptions & Options ) { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; return new <ISA_LIT>AsmBackend ( T , OSABI , CPU ) ;


<s> uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ;

return new <ISA_LIT>AsmBackend ( T , OSABI , CPU ) ;


<s> if ( ! <ISA_LIT>MCChecker ( * MCII , RF . getSubtargetInfo ( ) , Inst , Inst , * Asm . getContext ( ) . getRegisterInfo ( ) ) . check ( ) ) { Inst . erase ( Inst . end ( ) - <NUM_LIT> ) ; Size = <NUM_LIT> ; } } bool Error = <ISA_LIT>MCShuffle ( * MCII , RF . getSubtargetInfo ( ) , Inst ) ; ( void ) Error ; ReplaceInstruction ( Asm . getEmitter ( ) , RF , Inst ) ; Layout . invalidateFragmentsFrom ( & RF ) ; Size = <NUM_LIT> ; break ; } } } }


<s> default : break ; case MCFragment :: FT_Align : { auto Size = Asm . computeFragmentSize ( Layout , J ) ; for ( auto K = J . getIterator ( ) ; K != Fragments . begin ( ) && Size >= HEXAGON_PACKET_SIZE ; ) { -- K ; switch ( K -> getKind ( ) ) { default : break ; case MCFragment :: FT_Align : { Size = <NUM_LIT> ; break ; } case MCFragment :: FT_Relaxable : { auto & RF = cast < MCRelaxableFragment > ( * K ) ; auto & Inst = const_cast < MCInst & > ( RF . getInst ( ) ) ; while ( Size > <NUM_LIT> && <ISA_LIT>MCInstrInfo :: bundleSize ( Inst ) < <NUM_LIT> ) { MCInst * Nop = new ( Asm . getContext ( ) ) MCInst ; Nop -> setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createInst ( Nop ) ) ;


<s> assert ( <ISA_LIT>MCInstrInfo :: isBundle ( MCB ) ) ; * RelaxTarget = nullptr ; MCInst & MCI = const_cast < MCInst & > ( <ISA_LIT>MCInstrInfo :: instruction ( MCB , Fixup . getOffset ( ) / HEXAGON_INSTR_SIZE ) ) ; bool Relaxable = isInstRelaxable ( MCI ) ; if ( Relaxable == false ) return false ; if ( ! Resolved ) { switch ( ( unsigned ) Fixup . getKind ( ) ) { case fixup_<ISA_LIT>_B22_PCREL : default : return false ; break ; case fixup_<ISA_LIT>_B13_PCREL : case fixup_<ISA_LIT>_B15_PCREL : case fixup_<ISA_LIT>_B9_PCREL : case fixup_<ISA_LIT>_B7_PCREL : { if ( <ISA_LIT>MCInstrInfo :: bundleSize ( MCB ) < HEXAGON_PACKET_SIZE ) { ++ relaxedCnt ;


<s> case fixup_<ISA_LIT>_B15_PCREL_X : case fixup_<ISA_LIT>_B13_PCREL : case fixup_<ISA_LIT>_B13_PCREL_X : case fixup_<ISA_LIT>_B9_PCREL : case fixup_<ISA_LIT>_B9_PCREL_X : case fixup_<ISA_LIT>_B7_PCREL : case fixup_<ISA_LIT>_B7_PCREL_X : return <NUM_LIT> ; }


<s> OSABI ( OSABI ) , MCII ( T . createMCInstrInfo ( ) ) , RelaxTarget ( new MCInst * ) , Extender ( nullptr ) {


<s> <ISA_LIT>AsmBackend ( const Target & T , uint8_t OSABI , StringRef CPU ) :

OSABI ( OSABI ) , MCII ( T . createMCInstrInfo ( ) ) , RelaxTarget ( new MCInst * ) , Extender ( nullptr ) {


<s> bool Relaxable = false ; if ( llvm :: <ISA_LIT>MCInstrInfo :: getType ( * MCII , HMI ) == <STR_LIT> || ( llvm :: <ISA_LIT>MCInstrInfo :: getType ( * MCII , HMI ) == <STR_LIT> && MCID . isBranch ( ) ) || ( llvm :: <ISA_LIT>MCInstrInfo :: getType ( * MCII , HMI ) == <STR_LIT> && MCID . isBranch ( ) ) || ( llvm :: <ISA_LIT>MCInstrInfo :: getType ( * MCII , HMI ) == <STR_LIT> && HMI . getOpcode ( ) != <STR_LIT> ) ) if ( <ISA_LIT>MCInstrInfo :: isExtendable ( * MCII , HMI ) ) { Relaxable = true ; MCOperand const & Operand = HMI . getOperand ( <ISA_LIT>MCInstrInfo :: getExtendableOp ( * MCII , HMI ) ) ;

if ( <ISA_LIT>MCInstrInfo :: mustNotExtend ( * Operand . getExpr ( ) ) ) Relaxable = false ;


<s> case fixup_<ISA_LIT>_16_X : case fixup_<ISA_LIT>_12_X : case fixup_<ISA_LIT>_11_X : case fixup_<ISA_LIT>_10_X : case fixup_<ISA_LIT>_9_X : case fixup_<ISA_LIT>_8_X : case fixup_<ISA_LIT>_7_X : case fixup_<ISA_LIT>_6_X : case fixup_<ISA_LIT>_COPY : case fixup_<ISA_LIT>_GLOB_DAT : case fixup_<ISA_LIT>_JMP_SLOT : case fixup_<ISA_LIT>_RELATIVE : case fixup_<ISA_LIT>_PLT_B22_PCREL : case fixup_<ISA_LIT>_GOTREL_LO16 : case fixup_<ISA_LIT>_GOTREL_HI16 : case fixup_<ISA_LIT>_GOTREL_32 : case fixup_<ISA_LIT>_GOT_LO16 : case fixup_<ISA_LIT>_GOT_HI16 : case fixup_<ISA_LIT>_GOT_32 : case fixup_<ISA_LIT>_GOT_16 : case fixup_<ISA_LIT>_DTPMOD_32 : case fixup_<ISA_LIT>_DTPREL_LO16 : case fixup_<ISA_LIT>_DTPREL_HI16 : case fixup_<ISA_LIT>_DTPREL_32 : case fixup_<ISA_LIT>_DTPREL_16 : case fixup_<ISA_LIT>_GD_PLT_B22_PCREL : case fixup_<ISA_LIT>_LD_PLT_B22_PCREL : case fixup_<ISA_LIT>_GD_GOT_LO16 : case fixup_<ISA_LIT>_GD_GOT_HI16 : case fixup_<ISA_LIT>_GD_GOT_32 : case fixup_<ISA_LIT>_GD_GOT_16 : case fixup_<ISA_LIT>_LD_GOT_LO16 : case fixup_<ISA_LIT>_LD_GOT_HI16 : case fixup_<ISA_LIT>_LD_GOT_32 : case fixup_<ISA_LIT>_LD_GOT_16 : case fixup_<ISA_LIT>_IE_LO16 : case fixup_<ISA_LIT>_IE_HI16 : case fixup_<ISA_LIT>_IE_32 : case fixup_<ISA_LIT>_IE_16 : case fixup_<ISA_LIT>_IE_GOT_LO16 : case fixup_<ISA_LIT>_IE_GOT_HI16 : case fixup_<ISA_LIT>_IE_GOT_32 : case fixup_<ISA_LIT>_IE_GOT_16 : case fixup_<ISA_LIT>_TPREL_LO16 : case fixup_<ISA_LIT>_TPREL_HI16 : case fixup_<ISA_LIT>_TPREL_32 : case fixup_<ISA_LIT>_TPREL_16 : case fixup_<ISA_LIT>_GOTREL_32_6_X : case fixup_<ISA_LIT>_GOTREL_16_X : case fixup_<ISA_LIT>_GOTREL_11_X : case fixup_<ISA_LIT>_GOT_32_6_X : case fixup_<ISA_LIT>_GOT_16_X : case fixup_<ISA_LIT>_GOT_11_X : case fixup_<ISA_LIT>_DTPREL_32_6_X : case fixup_<ISA_LIT>_DTPREL_16_X : case fixup_<ISA_LIT>_DTPREL_11_X : case fixup_<ISA_LIT>_GD_GOT_32_6_X : case fixup_<ISA_LIT>_GD_GOT_16_X : case fixup_<ISA_LIT>_GD_GOT_11_X : case fixup_<ISA_LIT>_LD_GOT_32_6_X : case fixup_<ISA_LIT>_LD_GOT_16_X : case fixup_<ISA_LIT>_LD_GOT_11_X : case fixup_<ISA_LIT>_IE_32_6_X : case fixup_<ISA_LIT>_IE_16_X : case fixup_<ISA_LIT>_IE_GOT_32_6_X : case fixup_<ISA_LIT>_IE_GOT_16_X : case fixup_<ISA_LIT>_IE_GOT_11_X : case fixup_<ISA_LIT>_TPREL_32_6_X : case fixup_<ISA_LIT>_TPREL_16_X : case fixup_<ISA_LIT>_TPREL_11_X : case fixup_<ISA_LIT>_32_PCREL : case fixup_<ISA_LIT>_6_PCREL_X : case fixup_<ISA_LIT>_23_REG : IsResolved = false ; return ; case fixup_<ISA_LIT>_B22_PCREL : break ; case fixup_<ISA_LIT>_B13_PCREL : case fixup_<ISA_LIT>_B13_PCREL_X : case fixup_<ISA_LIT>_B32_PCREL_X : case fixup_<ISA_LIT>_B22_PCREL_X : case fixup_<ISA_LIT>_B15_PCREL : case fixup_<ISA_LIT>_B15_PCREL_X : case fixup_<ISA_LIT>_B9_PCREL : case fixup_<ISA_LIT>_B9_PCREL_X : case fixup_<ISA_LIT>_B7_PCREL : case fixup_<ISA_LIT>_B7_PCREL_X : if ( DisableFixup ) IsResolved = false ; break ; case FK_Data_1 :


<s> <ISA_LIT>AsmBackend ( const Target & T , const Triple & TT , uint8_t OSABI , StringRef CPU ) : MCAsmBackend ( <STR_LIT> ) , OSABI ( OSABI ) , CPU ( CPU ) , relaxedCnt ( <NUM_LIT> ) , MCII ( T . createMCInstrInfo ( ) ) , RelaxTarget ( new MCInst * ) , Extender ( nullptr ) {


<s> <ISA_LIT>AsmBackend ( Target const & T , uint8_t OSABI , StringRef CPU ) : OSABI ( OSABI ) , MCII ( T . createMCInstrInfo ( ) ) , RelaxTarget ( new MCInst * ) {


<s> Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B9_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; case fixup_<ISA_LIT>_B9_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B13_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; case fixup_<ISA_LIT>_B13_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B15_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; case fixup_<ISA_LIT>_B15_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B22_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; case fixup_<ISA_LIT>_B22_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B32_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( Value & <NUM_LIT> ) ; break ; case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case fixup_<ISA_LIT>_32 : InstMask = <NUM_LIT> ; Reloc = Value ; break ; } DEBUG ( dbgs ( ) << <STR_LIT> << getFixupKindInfo ( Kind ) . Name << <STR_LIT> << ( unsigned ) Kind << <STR_LIT> ) ; DEBUG ( uint32_t OldData = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumBytes ; i ++ ) OldData |= ( InstAddr [ i ] << ( i * <NUM_LIT> ) ) & ( <NUM_LIT> << ( i * <NUM_LIT> ) ) ; dbgs ( ) << <STR_LIT> ; dbgs ( ) . write_hex ( Value ) << <STR_LIT> ; dbgs ( ) . write_hex ( FixupValue ) << <STR_LIT> << Offset << <STR_LIT> << DataSize << <STR_LIT> ; dbgs ( ) . write_hex ( OldData ) << <STR_LIT> ; dbgs ( ) . write_hex ( Reloc ) ; ) ;

for ( unsigned i = <NUM_LIT> ; i < NumBytes ; i ++ ) {


<s> break ; case MCFragment :: FT_Align : { Size = <NUM_LIT> ; break ; } case MCFragment :: FT_Relaxable : { auto & RF = cast < MCRelaxableFragment > ( * K ) ; auto & Inst = const_cast < MCInst & > ( RF . getInst ( ) ) ; while ( Size > <NUM_LIT> && <ISA_LIT>MCInstrInfo :: bundleSize ( Inst ) < <NUM_LIT> ) { MCInst * Nop = new ( Asm . getContext ( ) ) MCInst ; Nop -> setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createInst ( Nop ) ) ; Size -= <NUM_LIT> ; if ( ! <ISA_LIT>MCChecker ( * MCII , RF . getSubtargetInfo ( ) , Inst , Inst , * Asm . getContext ( ) . getRegisterInfo ( ) ) . check ( ) ) { Inst . erase ( Inst . end ( ) - <NUM_LIT> ) ; Size = <NUM_LIT> ; } } bool Error = <ISA_LIT>MCShuffle ( true , * MCII , RF . getSubtargetInfo ( ) , Inst ) ;


<s> auto Size = Asm . computeFragmentSize ( Layout , J ) ; for ( auto K = J . getIterator ( ) ; K != Fragments . begin ( ) && Size >= HEXAGON_PACKET_SIZE ; ) { -- K ; switch ( K -> getKind ( ) ) { default : break ; case MCFragment :: FT_Align : { Size = <NUM_LIT> ; break ; } case MCFragment :: FT_Relaxable : { auto & RF = cast < MCRelaxableFragment > ( * K ) ; auto & Inst = const_cast < MCInst & > ( RF . getInst ( ) ) ; while ( Size > <NUM_LIT> && <ISA_LIT>MCInstrInfo :: bundleSize ( Inst ) < <NUM_LIT> ) { MCInst * Nop = new ( Asm . getContext ( ) ) MCInst ; Nop -> setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createInst ( Nop ) ) ; Size -= <NUM_LIT> ; if ( ! <ISA_LIT>MCChecker ( * MCII , RF . getSubtargetInfo ( ) , Inst , Inst , * Asm . getContext ( ) . getRegisterInfo ( ) ) . check ( ) ) { Inst . erase ( Inst . end ( ) - <NUM_LIT> ) ; Size = <NUM_LIT> ; } } bool Error = <ISA_LIT>MCShuffle ( true , * MCII , RF . getSubtargetInfo ( ) , Inst ) ; ( void ) Error ; ReplaceInstruction ( Asm . getEmitter ( ) , RF , Inst ) ; Layout . invalidateFragmentsFrom ( & RF ) ; Size = <NUM_LIT> ; break ; } } } }


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { StringRef CPU ( <STR_LIT> ) ; return create<ISA_LIT>ELFObjectWriter ( OS , OSABI , CPU ) ;


<s> case fixup_<ISA_LIT>_B15_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; case fixup_<ISA_LIT>_B15_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B22_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; case fixup_<ISA_LIT>_B22_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B32_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( Value & <NUM_LIT> ) ; break ; case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case fixup_<ISA_LIT>_32 : InstMask = <NUM_LIT> ; Reloc = Value ; break ; } DEBUG ( dbgs ( ) << <STR_LIT> << getFixupKindInfo ( Kind ) . Name << <STR_LIT> << ( unsigned ) Kind << <STR_LIT> ) ; DEBUG ( uint32_t OldData = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumBytes ; i ++ ) OldData |= ( InstAddr [ i ] << ( i * <NUM_LIT> ) ) & ( <NUM_LIT> << ( i * <NUM_LIT> ) ) ; dbgs ( ) << <STR_LIT> ; dbgs ( ) . write_hex ( Value ) << <STR_LIT> ; dbgs ( ) . write_hex ( FixupValue ) << <STR_LIT> << Offset << <STR_LIT> << Data . size ( ) << <STR_LIT> ; dbgs ( ) . write_hex ( OldData ) << <STR_LIT> ; dbgs ( ) . write_hex ( Reloc ) ; ) ; for ( unsigned i = <NUM_LIT> ; i < NumBytes ; i ++ ) { InstAddr [ i ] &= uint8_t ( ~ InstMask >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ; InstAddr [ i ] |= uint8_t ( Reloc >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ; } DEBUG ( uint32_t NewData = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumBytes ; i ++ ) NewData |= ( InstAddr [ i ] << ( i * <NUM_LIT> ) ) & ( <NUM_LIT> << ( i * <NUM_LIT> ) ) ;

dbgs ( ) << <STR_LIT> ; dbgs ( ) . write_hex ( NewData ) << <STR_LIT> ; ) ;


<s> InstMask = <NUM_LIT> ; Reloc = Value ; break ; } DEBUG ( dbgs ( ) << <STR_LIT> << getFixupKindInfo ( Kind ) . Name << <STR_LIT> << ( unsigned ) Kind << <STR_LIT> ) ; DEBUG ( uint32_t OldData = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumBytes ; i ++ ) OldData |= ( InstAddr [ i ] << ( i * <NUM_LIT> ) ) & ( <NUM_LIT> << ( i * <NUM_LIT> ) ) ; dbgs ( ) << <STR_LIT> ; dbgs ( ) . write_hex ( Value ) << <STR_LIT> ; dbgs ( ) . write_hex ( FixupValue ) << <STR_LIT> << Offset << <STR_LIT> << Data . size ( ) << <STR_LIT> ; dbgs ( ) . write_hex ( OldData ) << <STR_LIT> ; dbgs ( ) . write_hex ( Reloc ) ; ) ; for ( unsigned i = <NUM_LIT> ; i < NumBytes ; i ++ ) { InstAddr [ i ] &= uint8_t ( ~ InstMask >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ; InstAddr [ i ] |= uint8_t ( Reloc >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ; } DEBUG ( uint32_t NewData = <NUM_LIT> ;

for ( unsigned i = <NUM_LIT> ; i < NumBytes ; i ++ ) NewData |= ( InstAddr [ i ] << ( i * <NUM_LIT> ) ) & ( <NUM_LIT> << ( i * <NUM_LIT> ) ) ;


<s> MCFixupKind Kind = Fixup . getKind ( ) ; switch ( ( unsigned ) Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case fixup_<ISA_LIT>_LO16 : case fixup_<ISA_LIT>_HI16 : case fixup_<ISA_LIT>_16 : case fixup_<ISA_LIT>_8 : case fixup_<ISA_LIT>_GPREL16_0 : case fixup_<ISA_LIT>_GPREL16_1 : case fixup_<ISA_LIT>_GPREL16_2 : case fixup_<ISA_LIT>_GPREL16_3 : case fixup_<ISA_LIT>_HL16 : case fixup_<ISA_LIT>_32_6_X : case fixup_<ISA_LIT>_16_X : case fixup_<ISA_LIT>_12_X : case fixup_<ISA_LIT>_11_X : case fixup_<ISA_LIT>_10_X : case fixup_<ISA_LIT>_9_X : case fixup_<ISA_LIT>_8_X : case fixup_<ISA_LIT>_7_X : case fixup_<ISA_LIT>_6_X : case fixup_<ISA_LIT>_COPY : case fixup_<ISA_LIT>_GLOB_DAT : case fixup_<ISA_LIT>_JMP_SLOT : case fixup_<ISA_LIT>_RELATIVE : case fixup_<ISA_LIT>_PLT_B22_PCREL : case fixup_<ISA_LIT>_GOTREL_LO16 : case fixup_<ISA_LIT>_GOTREL_HI16 : case fixup_<ISA_LIT>_GOTREL_32 : case fixup_<ISA_LIT>_GOT_LO16 : case fixup_<ISA_LIT>_GOT_HI16 : case fixup_<ISA_LIT>_GOT_32 : case fixup_<ISA_LIT>_GOT_16 : case fixup_<ISA_LIT>_DTPMOD_32 : case fixup_<ISA_LIT>_DTPREL_LO16 : case fixup_<ISA_LIT>_DTPREL_HI16 : case fixup_<ISA_LIT>_DTPREL_32 : case fixup_<ISA_LIT>_DTPREL_16 : case fixup_<ISA_LIT>_GD_PLT_B22_PCREL : case fixup_<ISA_LIT>_LD_PLT_B22_PCREL : case fixup_<ISA_LIT>_GD_GOT_LO16 : case fixup_<ISA_LIT>_GD_GOT_HI16 : case fixup_<ISA_LIT>_GD_GOT_32 : case fixup_<ISA_LIT>_GD_GOT_16 : case fixup_<ISA_LIT>_LD_GOT_LO16 : case fixup_<ISA_LIT>_LD_GOT_HI16 : case fixup_<ISA_LIT>_LD_GOT_32 : case fixup_<ISA_LIT>_LD_GOT_16 : case fixup_<ISA_LIT>_IE_LO16 : case fixup_<ISA_LIT>_IE_HI16 : case fixup_<ISA_LIT>_IE_32 : case fixup_<ISA_LIT>_IE_16 : case fixup_<ISA_LIT>_IE_GOT_LO16 : case fixup_<ISA_LIT>_IE_GOT_HI16 : case fixup_<ISA_LIT>_IE_GOT_32 : case fixup_<ISA_LIT>_IE_GOT_16 : case fixup_<ISA_LIT>_TPREL_LO16 : case fixup_<ISA_LIT>_TPREL_HI16 : case fixup_<ISA_LIT>_TPREL_32 : case fixup_<ISA_LIT>_TPREL_16 : case fixup_<ISA_LIT>_GOTREL_32_6_X : case fixup_<ISA_LIT>_GOTREL_16_X : case fixup_<ISA_LIT>_GOTREL_11_X : case fixup_<ISA_LIT>_GOT_32_6_X : case fixup_<ISA_LIT>_GOT_16_X : case fixup_<ISA_LIT>_GOT_11_X : case fixup_<ISA_LIT>_DTPREL_32_6_X : case fixup_<ISA_LIT>_DTPREL_16_X : case fixup_<ISA_LIT>_DTPREL_11_X : case fixup_<ISA_LIT>_GD_GOT_32_6_X : case fixup_<ISA_LIT>_GD_GOT_16_X : case fixup_<ISA_LIT>_GD_GOT_11_X : case fixup_<ISA_LIT>_LD_GOT_32_6_X : case fixup_<ISA_LIT>_LD_GOT_16_X : case fixup_<ISA_LIT>_LD_GOT_11_X : case fixup_<ISA_LIT>_IE_32_6_X : case fixup_<ISA_LIT>_IE_16_X : case fixup_<ISA_LIT>_IE_GOT_32_6_X : case fixup_<ISA_LIT>_IE_GOT_16_X :


<s> case fixup_<ISA_LIT>_7_X : case fixup_<ISA_LIT>_6_X : case fixup_<ISA_LIT>_COPY : case fixup_<ISA_LIT>_GLOB_DAT : case fixup_<ISA_LIT>_JMP_SLOT : case fixup_<ISA_LIT>_RELATIVE : case fixup_<ISA_LIT>_PLT_B22_PCREL : case fixup_<ISA_LIT>_GOTREL_LO16 : case fixup_<ISA_LIT>_GOTREL_HI16 : case fixup_<ISA_LIT>_GOTREL_32 : case fixup_<ISA_LIT>_GOT_LO16 : case fixup_<ISA_LIT>_GOT_HI16 : case fixup_<ISA_LIT>_GOT_32 : case fixup_<ISA_LIT>_GOT_16 : case fixup_<ISA_LIT>_DTPMOD_32 : case fixup_<ISA_LIT>_DTPREL_LO16 : case fixup_<ISA_LIT>_DTPREL_HI16 : case fixup_<ISA_LIT>_DTPREL_32 : case fixup_<ISA_LIT>_DTPREL_16 : case fixup_<ISA_LIT>_GD_PLT_B22_PCREL : case fixup_<ISA_LIT>_LD_PLT_B22_PCREL : case fixup_<ISA_LIT>_GD_GOT_LO16 : case fixup_<ISA_LIT>_GD_GOT_HI16 : case fixup_<ISA_LIT>_GD_GOT_32 : case fixup_<ISA_LIT>_GD_GOT_16 : case fixup_<ISA_LIT>_LD_GOT_LO16 : case fixup_<ISA_LIT>_LD_GOT_HI16 : case fixup_<ISA_LIT>_LD_GOT_32 : case fixup_<ISA_LIT>_LD_GOT_16 : case fixup_<ISA_LIT>_IE_LO16 : case fixup_<ISA_LIT>_IE_HI16 : case fixup_<ISA_LIT>_IE_32 : case fixup_<ISA_LIT>_IE_16 : case fixup_<ISA_LIT>_IE_GOT_LO16 : case fixup_<ISA_LIT>_IE_GOT_HI16 : case fixup_<ISA_LIT>_IE_GOT_32 : case fixup_<ISA_LIT>_IE_GOT_16 : case fixup_<ISA_LIT>_TPREL_LO16 : case fixup_<ISA_LIT>_TPREL_HI16 : case fixup_<ISA_LIT>_TPREL_32 : case fixup_<ISA_LIT>_TPREL_16 : case fixup_<ISA_LIT>_GOTREL_32_6_X : case fixup_<ISA_LIT>_GOTREL_16_X : case fixup_<ISA_LIT>_GOTREL_11_X : case fixup_<ISA_LIT>_GOT_32_6_X : case fixup_<ISA_LIT>_GOT_16_X : case fixup_<ISA_LIT>_GOT_11_X : case fixup_<ISA_LIT>_DTPREL_32_6_X : case fixup_<ISA_LIT>_DTPREL_16_X : case fixup_<ISA_LIT>_DTPREL_11_X : case fixup_<ISA_LIT>_GD_GOT_32_6_X : case fixup_<ISA_LIT>_GD_GOT_16_X : case fixup_<ISA_LIT>_GD_GOT_11_X : case fixup_<ISA_LIT>_LD_GOT_32_6_X : case fixup_<ISA_LIT>_LD_GOT_16_X : case fixup_<ISA_LIT>_LD_GOT_11_X : case fixup_<ISA_LIT>_IE_32_6_X : case fixup_<ISA_LIT>_IE_16_X :


<s> case fixup_<ISA_LIT>_B13_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B15_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; case fixup_<ISA_LIT>_B15_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B22_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; case fixup_<ISA_LIT>_B22_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B32_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( Value & <NUM_LIT> ) ; break ; case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case fixup_<ISA_LIT>_32 : InstMask = <NUM_LIT> ; Reloc = Value ; break ; } DEBUG ( dbgs ( ) << <STR_LIT> << getFixupKindInfo ( Kind ) . Name << <STR_LIT> << ( unsigned ) Kind << <STR_LIT> ) ;


<s> StringRef CPUString = <ISA_LIT>_MC :: select<ISA_LIT>CPU ( CPU ) ; return new <ISA_LIT>AsmBackend ( T , TT , OSABI , CPUString ) ;


<s> switch ( ( unsigned ) Kind ) { default : return ; case fixup_<ISA_LIT>_B7_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; case fixup_<ISA_LIT>_B7_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B9_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; case fixup_<ISA_LIT>_B9_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B13_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; case fixup_<ISA_LIT>_B13_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B15_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; case fixup_<ISA_LIT>_B15_PCREL_X : InstMask = <NUM_LIT> ;

Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ;


<s> void applyFixup ( MCFixup const & , char * , unsigned , uint64_t , bool ) const override { return ;


<s> MCAsmBackend * create<ISA_LIT>AsmBackend ( Target const & T , MCRegisterInfo const & , const Triple & TT , StringRef CPU ) { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ;


<s> MCAsmBackend * create<ISA_LIT>AsmBackend ( Target const & T , MCRegisterInfo const & , const Triple & TT , StringRef CPU ) { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; return new <ISA_LIT>AsmBackend ( T , OSABI , CPU ) ;


<s> <ISA_LIT>AsmBackend ( Target const & T , uint8_t OSABI , StringRef CPU ) :


<s> <ISA_LIT>AsmBackend ( Target const & T , uint8_t OSABI , StringRef CPU ) : OSABI ( OSABI ) , MCII ( T . createMCInstrInfo ( ) ) , RelaxTarget ( new MCInst * ) , Extender ( nullptr ) {


if ( llvm :: <ISA_LIT>MCInstrInfo :: getType ( * MCII , HMI ) == <STR_LIT> || ( llvm :: <ISA_LIT>MCInstrInfo :: getType ( * MCII , HMI ) == <STR_LIT> && MCID . isBranch ( ) ) || ( llvm :: <ISA_LIT>MCInstrInfo :: getType ( * MCII , HMI ) == <STR_LIT> && HMI . getOpcode ( ) != <STR_LIT> ) ) if ( <ISA_LIT>MCInstrInfo :: isExtendable ( * MCII , HMI ) ) Relaxable = true ;


<s> bool PreviousIsExtender = false ; for ( auto const & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( Inst ) ) { auto const & Inst = * I . getInst ( ) ; if ( ! PreviousIsExtender ) {

if ( isInstRelaxable ( Inst ) ) return true ;


<s> assert ( <ISA_LIT>MCInstrInfo :: isBundle ( Inst ) ) ; bool PreviousIsExtender = false ; for ( auto const & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( Inst ) ) { auto const & Inst = * I . getInst ( ) ; if ( ! PreviousIsExtender ) {


<s> assert ( ( <ISA_LIT>MCInstrInfo :: bundleSize ( Res ) < HEXAGON_PACKET_SIZE ) && <STR_LIT> ) ; MCInst * HMIx = takeExtender ( ) ; * HMIx = <ISA_LIT>MCInstrInfo :: deriveExtender ( * MCII , CrntHMI , <ISA_LIT>MCInstrInfo :: getExtendableOperand ( * MCII , CrntHMI ) ) ; Res . addOperand ( MCOperand :: createInst ( HMIx ) ) ;


<s> void relaxInstruction ( MCInst const & Inst , MCInst & Res ) const override { assert ( <ISA_LIT>MCInstrInfo :: isBundle ( Inst ) && <STR_LIT> ) ; Res = <ISA_LIT>MCInstrInfo :: createBundle ( ) ; bool Update = false ; for ( auto & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( Inst ) ) { MCInst & CrntHMI = const_cast < MCInst & > ( * I . getInst ( ) ) ; if ( * RelaxTarget == & CrntHMI ) { Update = true ; assert ( ( <ISA_LIT>MCInstrInfo :: bundleSize ( Res ) < HEXAGON_PACKET_SIZE ) && <STR_LIT> ) ; MCInst * HMIx = takeExtender ( ) ; * HMIx = <ISA_LIT>MCInstrInfo :: deriveExtender ( * MCII , CrntHMI , <ISA_LIT>MCInstrInfo :: getExtendableOperand ( * MCII , CrntHMI ) ) ; Res . addOperand ( MCOperand :: createInst ( HMIx ) ) ; * RelaxTarget = nullptr ;


<s> void addf32ExtOperands ( MCInst & Inst , unsigned N ) const { addImmOperands ( Inst , N ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ;


<s> Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ;


<s> void addm6ImmOperands ( MCInst & Inst , unsigned N ) const {


<s> void addn8ImmOperands ( MCInst & Inst , unsigned N ) const {


<s> void addRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createReg ( getReg ( ) ) ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getReg ( ) ) ) ;


<s> void adds10ExtOperands ( MCInst & Inst , unsigned N ) const {


<s> void adds11_2ExtOperands ( MCInst & Inst , unsigned N ) const {


<s> void adds11_3ExtOperands ( MCInst & Inst , unsigned N ) const { addSignedImmOperands ( Inst , N ) ;


<s> void adds32ImmOperands ( MCInst & Inst , unsigned N ) const { addSignedImmOperands ( Inst , N ) ;


<s> void adds3ImmOperands ( MCInst & Inst , unsigned N ) const {


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;

Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) * <NUM_LIT> ) ) ;


<s> void adds4_0ImmOperands ( MCInst & Inst , unsigned N ) const { addSignedImmOperands ( Inst , N ) ;


<s> void adds4_3ImmOperands ( MCInst & Inst , unsigned N ) const {


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) * <NUM_LIT> ) ) ;


<s> void adds8Imm64Operands ( MCInst & Inst , unsigned N ) const {


<s> void adds8ImmOperands ( MCInst & Inst , unsigned N ) const { addSignedImmOperands ( Inst , N ) ;


<s> void adds9ExtOperands ( MCInst & Inst , unsigned N ) const {


<s> if ( ! Expr -> evaluateAsAbsolute ( Value ) ) { Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; return ; }

int64_t Extended = SignExtend64 ( Value , <NUM_LIT> ) ;


<s> void addu10ExtOperands ( MCInst & Inst , unsigned N ) const { addImmOperands ( Inst , N ) ;


<s> void addu10ImmOperands ( MCInst & Inst , unsigned N ) const {


<s> void addu10ImmOperands ( MCInst & Inst , unsigned N ) const { addImmOperands ( Inst , N ) ;


<s> void addu11_3ImmOperands ( MCInst & Inst , unsigned N ) const {


<s> void addu16ImmOperands ( MCInst & Inst , unsigned N ) const {


<s> void addu16_0ImmOperands ( MCInst & Inst , unsigned N ) const {