<s> if ( F . getAttributes ( ) . hasParamAttr ( Idx , Attribute :: SExt ) ) { if ( ! isa < PointerType > ( Arg . getType ( ) ) ) { for ( auto UI = Arg . use_begin ( ) ; UI != Arg . use_end ( ) ; ) { if ( isa < SExtInst > ( * UI ) ) { Instruction * Use = cast < Instruction > ( * UI ) ; SExtInst * SI = new SExtInst ( & Arg , Use -> getType ( ) ) ; assert ( EVT :: getEVT ( SI -> getType ( ) ) == ( EVT :: getEVT ( Use -> getType ( ) ) ) ) ; ++ UI ; Use -> replaceAllUsesWith ( SI ) ; Instruction * First = & F . getEntryBlock ( ) . front ( ) ; SI -> insertBefore ( First ) ; Use -> eraseFromParent ( ) ; } else { ++ UI ; } } } } ++ Idx ; } for ( auto & B : F ) { for ( auto & I : B ) { BinaryOperator * Ashr = dyn_cast < BinaryOperator > ( & I ) ; if ( ! ( Ashr && Ashr -> getOpcode ( ) == Instruction :: AShr ) ) continue ; Value * AshrOp1 = Ashr -> getOperand ( <NUM_LIT> ) ; ConstantInt * C = dyn_cast < ConstantInt > ( AshrOp1 ) ; if ( ! ( C && C -> getSExtValue ( ) == <NUM_LIT> ) ) continue ; Instruction * Shl = dyn_cast < Instruction > ( Ashr -> getOperand ( <NUM_LIT> ) ) ; if ( ! ( Shl && Shl -> getOpcode ( ) == Instruction :: Shl ) ) continue ; Value * Intr = Shl -> getOperand ( <NUM_LIT> ) ; Value * ShlOp1 = Shl -> getOperand ( <NUM_LIT> ) ; C = dyn_cast < ConstantInt > ( ShlOp1 ) ; if ( ! ( C && C -> getSExtValue ( ) == <NUM_LIT> ) ) continue ; if ( IntrinsicInst * I = dyn_cast < IntrinsicInst > ( Intr ) ) { if ( ! intrinsicAlreadySextended ( I -> getIntrinsicID ( ) ) ) continue ; for ( auto UI = Ashr -> user_begin ( ) , UE = Ashr -> user_end ( ) ; UI != UE ; ++ UI ) { const Use & TheUse = UI . getUse ( ) ; if ( Instruction * J = dyn_cast < Instruction > ( TheUse . getUser ( ) ) ) { J -> replaceUsesOfWith ( Ashr , I ) ; } }


<s> Instruction * First = & F . getEntryBlock ( ) . front ( ) ; SI -> insertBefore ( First ) ; Use -> eraseFromParent ( ) ; } } } } ++ Idx ; } for ( auto & B : F ) { for ( auto & I : B ) { BinaryOperator * Ashr = dyn_cast < BinaryOperator > ( & I ) ; if ( ! ( Ashr && Ashr -> getOpcode ( ) == Instruction :: AShr ) ) continue ; Value * AshrOp1 = Ashr -> getOperand ( <NUM_LIT> ) ; ConstantInt * C = dyn_cast < ConstantInt > ( AshrOp1 ) ; if ( ! ( C && C -> getSExtValue ( ) == <NUM_LIT> ) ) continue ; Instruction * Shl = dyn_cast < Instruction > ( Ashr -> getOperand ( <NUM_LIT> ) ) ; if ( ! ( Shl && Shl -> getOpcode ( ) == Instruction :: Shl ) ) continue ; Value * Intr = Shl -> getOperand ( <NUM_LIT> ) ; Value * ShlOp1 = Shl -> getOperand ( <NUM_LIT> ) ; C = dyn_cast < ConstantInt > ( ShlOp1 ) ; if ( ! ( C && C -> getSExtValue ( ) == <NUM_LIT> ) ) continue ; if ( IntrinsicInst * I = dyn_cast < IntrinsicInst > ( Intr ) ) { if ( ! intrinsicAlreadySextended ( I -> getIntrinsicID ( ) ) ) continue ;

for ( auto UI = Ashr -> user_begin ( ) , UE = Ashr -> user_end ( ) ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override {

AU . addRequired < MachineFunctionAnalysis > ( ) ;


<s> AU . addPreserved < MachineFunctionAnalysis > ( ) ; AU . addPreserved < StackProtector > ( ) ;

FunctionPass :: getAnalysisUsage ( AU ) ;


<s> const char * getPassName ( ) const override {


<s> Instruction * Use = cast < Instruction > ( * UI ) ; SExtInst * SI = new SExtInst ( & Arg , Use -> getType ( ) ) ; assert ( EVT :: getEVT ( SI -> getType ( ) ) == ( EVT :: getEVT ( Use -> getType ( ) ) ) ) ; ++ UI ; Use -> replaceAllUsesWith ( SI ) ; Instruction * First = & F . getEntryBlock ( ) . front ( ) ; SI -> insertBefore ( First ) ; Use -> eraseFromParent ( ) ; } else { ++ UI ; } } } } ++ Idx ; } for ( auto & B : F ) { for ( auto & I : B ) { BinaryOperator * Ashr = dyn_cast < BinaryOperator > ( & I ) ; if ( ! ( Ashr && Ashr -> getOpcode ( ) == Instruction :: AShr ) ) continue ; Value * AshrOp1 = Ashr -> getOperand ( <NUM_LIT> ) ; ConstantInt * C = dyn_cast < ConstantInt > ( AshrOp1 ) ; if ( ! ( C && C -> getSExtValue ( ) == <NUM_LIT> ) ) continue ; Instruction * Shl = dyn_cast < Instruction > ( Ashr -> getOperand ( <NUM_LIT> ) ) ; if ( ! ( Shl && Shl -> getOpcode ( ) == Instruction :: Shl ) ) continue ; Value * Intr = Shl -> getOperand ( <NUM_LIT> ) ; Value * ShlOp1 = Shl -> getOperand ( <NUM_LIT> ) ; C = dyn_cast < ConstantInt > ( ShlOp1 ) ; if ( ! ( C && C -> getSExtValue ( ) == <NUM_LIT> ) ) continue ; if ( IntrinsicInst * I = dyn_cast < IntrinsicInst > ( Intr ) ) { if ( ! intrinsicAlreadySextended ( I -> getIntrinsicID ( ) ) ) continue ; for ( auto UI = Ashr -> user_begin ( ) , UE = Ashr -> user_end ( ) ; UI != UE ; ++ UI ) {


<s> ++ UI ; Use -> replaceAllUsesWith ( SI ) ; Instruction * First = & F . getEntryBlock ( ) . front ( ) ; SI -> insertBefore ( First ) ; Use -> eraseFromParent ( ) ; } else { ++ UI ; } } } } ++ Idx ; } for ( auto & B : F ) { for ( auto & I : B ) { BinaryOperator * Ashr = dyn_cast < BinaryOperator > ( & I ) ; if ( ! ( Ashr && Ashr -> getOpcode ( ) == Instruction :: AShr ) ) continue ; Value * AshrOp1 = Ashr -> getOperand ( <NUM_LIT> ) ; ConstantInt * C = dyn_cast < ConstantInt > ( AshrOp1 ) ; if ( ! ( C && C -> getSExtValue ( ) == <NUM_LIT> ) ) continue ; Instruction * Shl = dyn_cast < Instruction > ( Ashr -> getOperand ( <NUM_LIT> ) ) ; if ( ! ( Shl && Shl -> getOpcode ( ) == Instruction :: Shl ) ) continue ; Value * Intr = Shl -> getOperand ( <NUM_LIT> ) ; Value * ShlOp1 = Shl -> getOperand ( <NUM_LIT> ) ; C = dyn_cast < ConstantInt > ( ShlOp1 ) ; if ( ! ( C && C -> getSExtValue ( ) == <NUM_LIT> ) ) continue ; if ( IntrinsicInst * I = dyn_cast < IntrinsicInst > ( Intr ) ) { if ( ! intrinsicAlreadySextended ( I -> getIntrinsicID ( ) ) ) continue ; for ( auto UI = Ashr -> user_begin ( ) , UE = Ashr -> user_end ( ) ; UI != UE ; ++ UI ) {


<s> FunctionPass * llvm :: create<ISA_LIT>OptimizeSZExtends ( ) { return new <ISA_LIT>OptimizeSZExtends ( ) ;


<s> AU . addRequired < MachineFunctionAnalysis > ( ) ; AU . addPreserved < MachineFunctionAnalysis > ( ) ;

MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> AU . addRequired < MachineFunctionAnalysis > ( ) ; AU . addPreserved < MachineFunctionAnalysis > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> <ISA_LIT>OptimizeSZExtends ( ) : MachineFunctionPass ( ID ) {


<s> MBBb != MBBe ; ++ MBBb ) { MachineBasicBlock * MBB = MBBb ; SExtMap . clear ( ) ; for ( MachineBasicBlock :: iterator MII = MBB -> begin ( ) ; MII != MBB -> end ( ) ; ++ MII ) { MachineInstr * MI = MII ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { assert ( MI -> getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DstReg ) && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { SExtMap [ DstReg ] = SrcReg ; } } if ( MI -> isCopy ( ) ) { assert ( MI -> getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ; if ( Src . getSubReg ( ) != <STR_LIT> ) continue ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DstReg ) && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { if ( unsigned SextSrc = SExtMap . lookup ( SrcReg ) ) { MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> addOperand ( MachineOperand :: CreateReg ( SextSrc , false ) ) ; } } } } } return true ;


<s> StringRef getPassName ( ) const override {


<s> } if ( ! DisableOptSZExt && MI . isCopy ( ) ) { assert ( MI . getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; if ( Src . getSubReg ( ) != <STR_LIT> ) continue ; Register DstReg = Dst . getReg ( ) ; Register SrcReg = Src . getReg ( ) ; if ( Register :: isVirtualRegister ( DstReg ) && Register :: isVirtualRegister ( SrcReg ) ) { if ( unsigned PeepholeSrc = PeepholeMap . lookup ( SrcReg ) ) { MI . RemoveOperand ( <NUM_LIT> ) ; MI . addOperand ( MachineOperand :: CreateReg ( PeepholeSrc , false ) ) ; } else { DenseMap < unsigned , std :: pair < unsigned , unsigned > > :: iterator DI = PeepholeDoubleRegsMap . find ( SrcReg ) ; if ( DI != PeepholeDoubleRegsMap . end ( ) ) { std :: pair < unsigned , unsigned > PeepholeSrc = DI -> second ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . addOperand ( MachineOperand :: CreateReg ( PeepholeSrc . first , false , false , false , false , false , false , PeepholeSrc . second ) ) ; } } } } if ( ! DisablePNotP ) { bool Done = false ; if ( QII -> isPredicated ( MI ) ) { MachineOperand & Op0 = MI . getOperand ( <NUM_LIT> ) ; Register Reg0 = Op0 . getReg ( ) ; const TargetRegisterClass * RC0 = MRI -> getRegClass ( Reg0 ) ; if ( RC0 -> getID ( ) == <STR_LIT> ) { if ( Register :: isVirtualRegister ( Reg0 ) ) { if ( unsigned PeepholeSrc = PeepholeMap . lookup ( Reg0 ) ) { MI . getOperand ( <NUM_LIT> ) . setReg ( PeepholeSrc ) ; MRI -> clearKillFlags ( PeepholeSrc ) ; int NewOp = QII -> getInvertedPredicatedOpcode ( MI . getOpcode ( ) ) ; MI . setDesc ( QII -> get ( NewOp ) ) ; Done = true ; } } } } if ( ! Done ) { unsigned Op = MI . getOpcode ( ) ; unsigned NewOp = <NUM_LIT> ; unsigned PR = <NUM_LIT> , S1 = <NUM_LIT> , S2 = <NUM_LIT> ;


<s> case MachineOperand :: MO_Immediate : if ( Src . isImm ( ) ) { Dst . setImm ( Src . getImm ( ) ) ; } else if ( Src . isReg ( ) ) { Dst . ChangeToRegister ( Src . getReg ( ) , Src . isDef ( ) , Src . isImplicit ( ) , Src . isKill ( ) , Src . isDead ( ) , Src . isUndef ( ) , Src . isDebug ( ) ) ;


<s> const char * getPassName ( ) const override { return <STR_LIT> ;


<s> <ISA_LIT>Peephole ( ) : MachineFunctionPass ( ID ) {

initialize<ISA_LIT>PeepholePass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> initialize<ISA_LIT>PeepholePass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> MBBb != MBBe ; ++ MBBb ) { MachineBasicBlock * MBB = MBBb ; PeepholeMap . clear ( ) ; PeepholeDoubleRegsMap . clear ( ) ; for ( MachineBasicBlock :: iterator MII = MBB -> begin ( ) ; MII != MBB -> end ( ) ; ++ MII ) { MachineInstr * MI = MII ; if ( ! DisableOptSZExt && MI -> getOpcode ( ) == <STR_LIT> ) { assert ( MI -> getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DstReg ) && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { PeepholeMap [ DstReg ] = SrcReg ; } } if ( ! DisableOptExtTo64 && MI -> getOpcode ( ) == <STR_LIT> ) { assert ( MI -> getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src2 = MI -> getOperand ( <NUM_LIT> ) ; if ( Src1 . getImm ( ) != <NUM_LIT> ) continue ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src2 . getReg ( ) ; PeepholeMap [ DstReg ] = SrcReg ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { assert ( MI -> getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src2 = MI -> getOperand ( <NUM_LIT> ) ; if ( Src2 . getImm ( ) != <NUM_LIT> ) continue ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src1 . getReg ( ) ; PeepholeDoubleRegsMap [ DstReg ] = std :: make_pair ( * & SrcReg , <NUM_LIT> ) ; } if ( ! DisablePNotP && ( MI -> getOpcode ( ) == <STR_LIT> ) ) { assert ( MI -> getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DstReg ) && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { PeepholeMap [ DstReg ] = SrcReg ; } } if ( ! DisableOptSZExt && MI -> isCopy ( ) ) { assert ( MI -> getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ; if ( Src . getSubReg ( ) != <STR_LIT> ) continue ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const {


<s> unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src1 . getReg ( ) ; PeepholeDoubleRegsMap [ DstReg ] = std :: make_pair ( * & SrcReg , <NUM_LIT> ) ; } if ( ! DisablePNotP && ( MI -> getOpcode ( ) == <STR_LIT> ) ) { assert ( MI -> getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DstReg ) && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { PeepholeMap [ DstReg ] = SrcReg ; } } if ( ! DisableOptSZExt && MI -> isCopy ( ) ) { assert ( MI -> getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ; if ( Src . getSubReg ( ) != <STR_LIT> ) continue ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DstReg ) && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { if ( unsigned PeepholeSrc = PeepholeMap . lookup ( SrcReg ) ) { MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> addOperand ( MachineOperand :: CreateReg ( PeepholeSrc , false ) ) ; } else { DenseMap < unsigned , std :: pair < unsigned , unsigned > > :: iterator DI = PeepholeDoubleRegsMap . find ( SrcReg ) ; if ( DI != PeepholeDoubleRegsMap . end ( ) ) { std :: pair < unsigned , unsigned > PeepholeSrc = DI -> second ; MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> addOperand ( MachineOperand :: CreateReg ( PeepholeSrc . first , false , false , false , false , false , false , PeepholeSrc . second ) ) ; } } } } if ( ! DisablePNotP ) { bool Done = false ; if ( QII -> isPredicated ( MI ) ) { MachineOperand & Op0 = MI -> getOperand ( <NUM_LIT> ) ; unsigned Reg0 = Op0 . getReg ( ) ; const TargetRegisterClass * RC0 = MRI -> getRegClass ( Reg0 ) ; if ( RC0 -> getID ( ) == <STR_LIT> ) { if ( TargetRegisterInfo :: isVirtualRegister ( Reg0 ) ) { if ( unsigned PeepholeSrc = PeepholeMap . lookup ( Reg0 ) ) { MI -> getOperand ( <NUM_LIT> ) . setReg ( PeepholeSrc ) ; int NewOp = QII -> getInvertedPredicatedOpcode ( MI -> getOpcode ( ) ) ; MI -> setDesc ( QII -> get ( NewOp ) ) ; Done = true ; } } } } if ( ! Done ) { unsigned Op = MI -> getOpcode ( ) ; unsigned NewOp = <NUM_LIT> ;


<s> DenseMap < unsigned , unsigned > PeepholeMap ; DenseMap < unsigned , std :: pair < unsigned , unsigned > > PeepholeDoubleRegsMap ; if ( Disable<ISA_LIT>Peephole ) return false ; for ( MachineBasicBlock & MBB : MF ) { PeepholeMap . clear ( ) ; PeepholeDoubleRegsMap . clear ( ) ; for ( MachineInstr & MI : llvm :: make_early_inc_range ( MBB ) ) { if ( ! DisableOptSZExt && MI . getOpcode ( ) == <STR_LIT> ) { assert ( MI . getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; Register DstReg = Dst . getReg ( ) ; Register SrcReg = Src . getReg ( ) ; if ( DstReg . isVirtual ( ) && SrcReg . isVirtual ( ) ) { PeepholeMap [ DstReg ] = SrcReg ; } } if ( ! DisableOptExtTo64 && MI . getOpcode ( ) == <STR_LIT> ) { assert ( MI . getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Src2 = MI . getOperand ( <NUM_LIT> ) ; if ( Src1 . getImm ( ) != <NUM_LIT> ) continue ; Register DstReg = Dst . getReg ( ) ; Register SrcReg = Src2 . getReg ( ) ; PeepholeMap [ DstReg ] = SrcReg ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { assert ( MI . getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Src2 = MI . getOperand ( <NUM_LIT> ) ; if ( Src2 . getImm ( ) != <NUM_LIT> ) continue ;


<s> if ( DstReg . isVirtual ( ) && SrcReg . isVirtual ( ) ) { PeepholeMap [ DstReg ] = SrcReg ; } } if ( ! DisableOptSZExt && MI . isCopy ( ) ) { assert ( MI . getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; if ( Src . getSubReg ( ) != <STR_LIT> ) continue ; Register DstReg = Dst . getReg ( ) ; Register SrcReg = Src . getReg ( ) ; if ( DstReg . isVirtual ( ) && SrcReg . isVirtual ( ) ) { if ( unsigned PeepholeSrc = PeepholeMap . lookup ( SrcReg ) ) { MI . RemoveOperand ( <NUM_LIT> ) ; MI . addOperand ( MachineOperand :: CreateReg ( PeepholeSrc , false ) ) ; } else { DenseMap < unsigned , std :: pair < unsigned , unsigned > > :: iterator DI = PeepholeDoubleRegsMap . find ( SrcReg ) ; if ( DI != PeepholeDoubleRegsMap . end ( ) ) { std :: pair < unsigned , unsigned > PeepholeSrc = DI -> second ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . addOperand ( MachineOperand :: CreateReg ( PeepholeSrc . first , false , false , false , false , false , false , PeepholeSrc . second ) ) ; } } } } if ( ! DisablePNotP ) { bool Done = false ; if ( QII -> isPredicated ( MI ) ) { MachineOperand & Op0 = MI . getOperand ( <NUM_LIT> ) ; Register Reg0 = Op0 . getReg ( ) ; const TargetRegisterClass * RC0 = MRI -> getRegClass ( Reg0 ) ; if ( RC0 -> getID ( ) == <STR_LIT> ) { if ( Reg0 . isVirtual ( ) ) { if ( unsigned PeepholeSrc = PeepholeMap . lookup ( Reg0 ) ) { MI . getOperand ( <NUM_LIT> ) . setReg ( PeepholeSrc ) ; MRI -> clearKillFlags ( PeepholeSrc ) ; int NewOp = QII -> getInvertedPredicatedOpcode ( MI . getOpcode ( ) ) ; MI . setDesc ( QII -> get ( NewOp ) ) ; Done = true ; } } }


<s> unsigned SrcReg = Src . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DstReg ) && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { PeepholeMap [ DstReg ] = SrcReg ; } } if ( ! DisableOptSZExt && MI . isCopy ( ) ) { assert ( MI . getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; if ( Src . getSubReg ( ) != <STR_LIT> ) continue ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DstReg ) && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { if ( unsigned PeepholeSrc = PeepholeMap . lookup ( SrcReg ) ) { MI . RemoveOperand ( <NUM_LIT> ) ; MI . addOperand ( MachineOperand :: CreateReg ( PeepholeSrc , false ) ) ; } else { DenseMap < unsigned , std :: pair < unsigned , unsigned > > :: iterator DI = PeepholeDoubleRegsMap . find ( SrcReg ) ; if ( DI != PeepholeDoubleRegsMap . end ( ) ) { std :: pair < unsigned , unsigned > PeepholeSrc = DI -> second ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . addOperand ( MachineOperand :: CreateReg ( PeepholeSrc . first , false , false , false , false , false , false , PeepholeSrc . second ) ) ; } } } } if ( ! DisablePNotP ) { bool Done = false ; if ( QII -> isPredicated ( MI ) ) { MachineOperand & Op0 = MI . getOperand ( <NUM_LIT> ) ; unsigned Reg0 = Op0 . getReg ( ) ; const TargetRegisterClass * RC0 = MRI -> getRegClass ( Reg0 ) ; if ( RC0 -> getID ( ) == <STR_LIT> ) { if ( TargetRegisterInfo :: isVirtualRegister ( Reg0 ) ) { if ( unsigned PeepholeSrc = PeepholeMap . lookup ( Reg0 ) ) { MI . getOperand ( <NUM_LIT> ) . setReg ( PeepholeSrc ) ; MRI -> clearKillFlags ( PeepholeSrc ) ; int NewOp = QII -> getInvertedPredicatedOpcode ( MI . getOpcode ( ) ) ; MI . setDesc ( QII -> get ( NewOp ) ) ; Done = true ; } } } }


<s> case MachineOperand :: MO_Immediate : if ( Src . isImm ( ) ) { Dst . setImm ( Src . getImm ( ) ) ; } else if ( Src . isReg ( ) ) {

Dst . ChangeToRegister ( Src . getReg ( ) , Src . isDef ( ) , Src . isImplicit ( ) , Src . isKill ( ) , Src . isDead ( ) , Src . isUndef ( ) , Src . isDebug ( ) ) ;


<s> PeepholeMap [ DstReg ] = SrcReg ; } } if ( ! DisableOptSZExt && MI . isCopy ( ) ) { assert ( MI . getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; if ( Src . getSubReg ( ) != <STR_LIT> ) continue ; Register DstReg = Dst . getReg ( ) ; Register SrcReg = Src . getReg ( ) ; if ( DstReg . isVirtual ( ) && SrcReg . isVirtual ( ) ) { if ( unsigned PeepholeSrc = PeepholeMap . lookup ( SrcReg ) ) { MI . RemoveOperand ( <NUM_LIT> ) ; MI . addOperand ( MachineOperand :: CreateReg ( PeepholeSrc , false ) ) ; } else { DenseMap < unsigned , std :: pair < unsigned , unsigned > > :: iterator DI = PeepholeDoubleRegsMap . find ( SrcReg ) ; if ( DI != PeepholeDoubleRegsMap . end ( ) ) { std :: pair < unsigned , unsigned > PeepholeSrc = DI -> second ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . addOperand ( MachineOperand :: CreateReg ( PeepholeSrc . first , false , false , false , false , false , false , PeepholeSrc . second ) ) ; } } } } if ( ! DisablePNotP ) { bool Done = false ; if ( QII -> isPredicated ( MI ) ) { MachineOperand & Op0 = MI . getOperand ( <NUM_LIT> ) ; Register Reg0 = Op0 . getReg ( ) ; const TargetRegisterClass * RC0 = MRI -> getRegClass ( Reg0 ) ; if ( RC0 -> getID ( ) == <STR_LIT> ) { if ( Reg0 . isVirtual ( ) ) { if ( unsigned PeepholeSrc = PeepholeMap . lookup ( Reg0 ) ) { MI . getOperand ( <NUM_LIT> ) . setReg ( PeepholeSrc ) ; MRI -> clearKillFlags ( PeepholeSrc ) ; int NewOp = QII -> getInvertedPredicatedOpcode ( MI . getOpcode ( ) ) ; MI . setDesc ( QII -> get ( NewOp ) ) ; Done = true ; } } } } if ( ! Done ) { unsigned Op = MI . getOpcode ( ) ; unsigned NewOp = <NUM_LIT> ;


<s> switch ( Dst . getType ( ) ) { case MachineOperand :: MO_Register : if ( Src . isReg ( ) ) { Dst . setReg ( Src . getReg ( ) ) ; Dst . setSubReg ( Src . getSubReg ( ) ) ; MRI -> clearKillFlags ( Src . getReg ( ) ) ; } else if ( Src . isImm ( ) ) { Dst . ChangeToImmediate ( Src . getImm ( ) ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } break ; case MachineOperand :: MO_Immediate :


<s> if ( ! DisableOptSZExt && MI . isCopy ( ) ) { assert ( MI . getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; if ( Src . getSubReg ( ) != <STR_LIT> ) continue ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DstReg ) && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { if ( unsigned PeepholeSrc = PeepholeMap . lookup ( SrcReg ) ) { MI . RemoveOperand ( <NUM_LIT> ) ; MI . addOperand ( MachineOperand :: CreateReg ( PeepholeSrc , false ) ) ; } else { DenseMap < unsigned , std :: pair < unsigned , unsigned > > :: iterator DI = PeepholeDoubleRegsMap . find ( SrcReg ) ; if ( DI != PeepholeDoubleRegsMap . end ( ) ) { std :: pair < unsigned , unsigned > PeepholeSrc = DI -> second ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . addOperand ( MachineOperand :: CreateReg ( PeepholeSrc . first , false , false , false , false , false , false , PeepholeSrc . second ) ) ; } } } } if ( ! DisablePNotP ) { bool Done = false ; if ( QII -> isPredicated ( MI ) ) { MachineOperand & Op0 = MI . getOperand ( <NUM_LIT> ) ; unsigned Reg0 = Op0 . getReg ( ) ; const TargetRegisterClass * RC0 = MRI -> getRegClass ( Reg0 ) ; if ( RC0 -> getID ( ) == <STR_LIT> ) { if ( TargetRegisterInfo :: isVirtualRegister ( Reg0 ) ) { if ( unsigned PeepholeSrc = PeepholeMap . lookup ( Reg0 ) ) { MI . getOperand ( <NUM_LIT> ) . setReg ( PeepholeSrc ) ; MRI -> clearKillFlags ( PeepholeSrc ) ; int NewOp = QII -> getInvertedPredicatedOpcode ( MI . getOpcode ( ) ) ; MI . setDesc ( QII -> get ( NewOp ) ) ; Done = true ; } } } } if ( ! Done ) { unsigned Op = MI . getOpcode ( ) ; unsigned NewOp = <NUM_LIT> ; unsigned PR = <NUM_LIT> , S1 = <NUM_LIT> , S2 = <NUM_LIT> ; switch ( Op ) { case <STR_LIT> : case <STR_LIT> : NewOp = Op ; break ;


<s> unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src1 . getReg ( ) ; PeepholeDoubleRegsMap [ DstReg ] = std :: make_pair ( * & SrcReg , <STR_LIT> ) ; } if ( ! DisablePNotP && ( MI -> getOpcode ( ) == <STR_LIT> ) ) { assert ( MI -> getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DstReg ) && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { PeepholeMap [ DstReg ] = SrcReg ; } } if ( ! DisableOptSZExt && MI -> isCopy ( ) ) { assert ( MI -> getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ; if ( Src . getSubReg ( ) != <STR_LIT> ) continue ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DstReg ) && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { if ( unsigned PeepholeSrc = PeepholeMap . lookup ( SrcReg ) ) { MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> addOperand ( MachineOperand :: CreateReg ( PeepholeSrc , false ) ) ; } else { DenseMap < unsigned , std :: pair < unsigned , unsigned > > :: iterator DI = PeepholeDoubleRegsMap . find ( SrcReg ) ; if ( DI != PeepholeDoubleRegsMap . end ( ) ) { std :: pair < unsigned , unsigned > PeepholeSrc = DI -> second ; MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> addOperand ( MachineOperand :: CreateReg ( PeepholeSrc . first , false , false , false , false , false , false , PeepholeSrc . second ) ) ; } } } } if ( ! DisablePNotP ) { bool Done = false ; if ( QII -> isPredicated ( * MI ) ) { MachineOperand & Op0 = MI -> getOperand ( <NUM_LIT> ) ; unsigned Reg0 = Op0 . getReg ( ) ; const TargetRegisterClass * RC0 = MRI -> getRegClass ( Reg0 ) ; if ( RC0 -> getID ( ) == <STR_LIT> ) { if ( TargetRegisterInfo :: isVirtualRegister ( Reg0 ) ) { if ( unsigned PeepholeSrc = PeepholeMap . lookup ( Reg0 ) ) { MI -> getOperand ( <NUM_LIT> ) . setReg ( PeepholeSrc ) ; int NewOp = QII -> getInvertedPredicatedOpcode ( MI -> getOpcode ( ) ) ; MI -> setDesc ( QII -> get ( NewOp ) ) ; Done = true ; } } } }


<s> if ( ! DisableOptSZExt && MI -> isCopy ( ) ) { assert ( MI -> getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ; if ( Src . getSubReg ( ) != <STR_LIT> ) continue ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DstReg ) && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { if ( unsigned PeepholeSrc = PeepholeMap . lookup ( SrcReg ) ) { MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> addOperand ( MachineOperand :: CreateReg ( PeepholeSrc , false ) ) ; } } } if ( ! DisablePNotP ) { bool Done = false ; if ( QII -> isPredicated ( MI ) ) { MachineOperand & Op0 = MI -> getOperand ( <NUM_LIT> ) ; unsigned Reg0 = Op0 . getReg ( ) ; const TargetRegisterClass * RC0 = MRI -> getRegClass ( Reg0 ) ; if ( RC0 -> getID ( ) == <STR_LIT> ) { if ( TargetRegisterInfo :: isVirtualRegister ( Reg0 ) ) { if ( unsigned PeepholeSrc = PeepholeMap . lookup ( Reg0 ) ) { MI -> getOperand ( <NUM_LIT> ) . setReg ( PeepholeSrc ) ; int NewOp = QII -> getInvertedPredicatedOpcode ( MI -> getOpcode ( ) ) ; MI -> setDesc ( QII -> get ( NewOp ) ) ; Done = true ; } } } } if ( ! Done ) { unsigned Op = MI -> getOpcode ( ) ; unsigned NewOp = <NUM_LIT> ; unsigned PR = <NUM_LIT> , S1 = <NUM_LIT> , S2 = <NUM_LIT> ; switch ( Op ) {


<s> PeepholeDoubleRegsMap [ DstReg ] = std :: make_pair ( * & SrcReg , <STR_LIT> ) ; } if ( ! DisablePNotP && MI . getOpcode ( ) == <STR_LIT> ) { assert ( MI . getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DstReg ) && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { PeepholeMap [ DstReg ] = SrcReg ; } } if ( ! DisableOptSZExt && MI . isCopy ( ) ) { assert ( MI . getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; if ( Src . getSubReg ( ) != <STR_LIT> ) continue ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DstReg ) && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { if ( unsigned PeepholeSrc = PeepholeMap . lookup ( SrcReg ) ) { MI . RemoveOperand ( <NUM_LIT> ) ; MI . addOperand ( MachineOperand :: CreateReg ( PeepholeSrc , false ) ) ; } else { DenseMap < unsigned , std :: pair < unsigned , unsigned > > :: iterator DI = PeepholeDoubleRegsMap . find ( SrcReg ) ; if ( DI != PeepholeDoubleRegsMap . end ( ) ) { std :: pair < unsigned , unsigned > PeepholeSrc = DI -> second ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . addOperand ( MachineOperand :: CreateReg ( PeepholeSrc . first , false , false , false , false , false , false , PeepholeSrc . second ) ) ; } } } } if ( ! DisablePNotP ) { bool Done = false ; if ( QII -> isPredicated ( MI ) ) { MachineOperand & Op0 = MI . getOperand ( <NUM_LIT> ) ; unsigned Reg0 = Op0 . getReg ( ) ; const TargetRegisterClass * RC0 = MRI -> getRegClass ( Reg0 ) ; if ( RC0 -> getID ( ) == <STR_LIT> ) { if ( TargetRegisterInfo :: isVirtualRegister ( Reg0 ) ) { if ( unsigned PeepholeSrc = PeepholeMap . lookup ( Reg0 ) ) { MI . getOperand ( <NUM_LIT> ) . setReg ( PeepholeSrc ) ; MRI -> clearKillFlags ( PeepholeSrc ) ; int NewOp = QII -> getInvertedPredicatedOpcode ( MI . getOpcode ( ) ) ; MI . setDesc ( QII -> get ( NewOp ) ) ; Done = true ; } } } } if ( ! Done ) { unsigned Op = MI . getOpcode ( ) ; unsigned NewOp = <NUM_LIT> ; unsigned PR = <NUM_LIT> , S1 = <NUM_LIT> , S2 = <NUM_LIT> ;


<s> int32_t * dest = reinterpret_cast < int32_t * > ( data ) ; int32_t result = ( ( gotpltAddr - pltBase ) >> <NUM_LIT> ) ; * dest |= ApplyMask < int32_t > ( <NUM_LIT> , result ) ; dest = dest + <NUM_LIT> ; result = ( gotpltAddr - pltBase ) ; * ( dest ) |= ApplyMask < int32_t > ( <NUM_LIT> , result ) ; plt0 -> setValue ( data ) ;


<s> <ISA_LIT>PLT1 * <ISA_LIT>PLT :: create ( ) {

return new <ISA_LIT>PLT1 ( * m_pSectionData ) ;


<s> return new <ISA_LIT>PLT1 ( * m_pSectionData ) ;


<s> unsigned char * buffer = pRegion . begin ( ) ; memcpy ( buffer , llvm :: cast < <ISA_LIT>PLT0 > ( ( * it ) ) . getValue ( ) , <ISA_LIT>PLT0 :: EntrySize ) ; result += <ISA_LIT>PLT0 :: EntrySize ; ++ it ; <ISA_LIT>PLT1 * plt1 = <NUM_LIT> ; <ISA_LIT>PLT :: iterator ie = end ( ) ; while ( it != ie ) { plt1 = & ( llvm :: cast < <ISA_LIT>PLT1 > ( * it ) ) ; memcpy ( buffer + result , plt1 -> getValue ( ) , <ISA_LIT>PLT1 :: EntrySize ) ;


<s> while ( it != ie ) { plt1 = & ( llvm :: cast < <ISA_LIT>PLT1 > ( * it ) ) ; memcpy ( buffer + result , plt1 -> getValue ( ) , <ISA_LIT>PLT1 :: EntrySize ) ; result += <ISA_LIT>PLT1 :: EntrySize ;


<s> ++ it ; if ( end ( ) != it ) { PLTEntryBase * plt1 = & ( llvm :: cast < PLTEntryBase > ( * it ) ) ; size += ( m_pSectionData -> size ( ) - <NUM_LIT> ) * plt1 -> size ( ) ; } m_Section . setSize ( size ) ; uint32_t offset = <NUM_LIT> ; SectionData :: iterator frag , fragEnd = m_pSectionData -> end ( ) ;

for ( frag = m_pSectionData -> begin ( ) ; frag != fragEnd ; ++ frag ) {


<s> PLTEntryBase * <ISA_LIT>PLT :: getPLT0 ( ) const { iterator first = m_pSectionData -> getFragmentList ( ) . begin ( ) ; assert ( first != m_pSectionData -> getFragmentList ( ) . end ( ) && <STR_LIT> ) ; PLTEntryBase * plt0 = & ( llvm :: cast < PLTEntryBase > ( * first ) ) ;


<s> iterator first = m_pSectionData -> getFragmentList ( ) . begin ( ) ; assert ( first != m_pSectionData -> getFragmentList ( ) . end ( ) && <STR_LIT> ) ;

PLTEntryBase * plt0 = & ( llvm :: cast < PLTEntryBase > ( * first ) ) ;


<s> <ISA_LIT>PLT :: <ISA_LIT>PLT ( LDSection & pSection , <ISA_LIT>GOTPLT & pGOTPLT , const LinkerConfig & pConfig ) : PLT ( pSection ) , m_GOTPLT ( pGOTPLT ) { assert ( LinkerConfig :: DynObj == pConfig . codeGenType ( ) || LinkerConfig :: Exec == pConfig . codeGenType ( ) || LinkerConfig :: Binary == pConfig . codeGenType ( ) ) ; m_PLT0 = hexagon_plt0 ; m_PLT0Size = sizeof ( hexagon_plt0 ) ; new <ISA_LIT>PLT0 ( * m_pSectionData ) ;


<s> assert ( LinkerConfig :: DynObj == pConfig . codeGenType ( ) || LinkerConfig :: Exec == pConfig . codeGenType ( ) || LinkerConfig :: Binary == pConfig . codeGenType ( ) ) ; m_PLT0 = hexagon_plt0 ; m_PLT0Size = sizeof ( hexagon_plt0 ) ; new <ISA_LIT>PLT0 ( * m_pSectionData ) ; pSection . setAlign ( <NUM_LIT> ) ;


<s> <ISA_LIT>PLT0 :: <ISA_LIT>PLT0 ( SectionData & pParent ) : PLT :: Entry < sizeof ( hexagon_plt0 ) > ( pParent ) {


<s> <ISA_LIT>PLT1 :: <ISA_LIT>PLT1 ( SectionData & pParent ) : PLT :: Entry < sizeof ( hexagon_plt1 ) > ( pParent ) {


<s> <ISA_LIT>PLT :: ~ <ISA_LIT>PLT ( ) {


<s> <ISA_LIT>RDFOpt ( ) : MachineFunctionPass ( ID ) {


<s> EM . insert ( std :: make_pair ( DstR , SrcR ) ) ; } ; DataFlowGraph & DFG = getDFG ( ) ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : { const MachineOperand & DstOp = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & HiOp = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & LoOp = MI -> getOperand ( <NUM_LIT> ) ; assert ( DstOp . getSubReg ( ) == <NUM_LIT> && <STR_LIT> ) ; mapRegs ( DFG . makeRegRef ( DstOp . getReg ( ) , <STR_LIT> ) , DFG . makeRegRef ( HiOp . getReg ( ) , HiOp . getSubReg ( ) ) ) ; mapRegs ( DFG . makeRegRef ( DstOp . getReg ( ) , <STR_LIT> ) , DFG . makeRegRef ( LoOp . getReg ( ) , LoOp . getSubReg ( ) ) ) ; return true ; } case <STR_LIT> : { const MachineOperand & A = MI -> getOperand ( <NUM_LIT> ) ; if ( ! A . isImm ( ) || A . getImm ( ) != <NUM_LIT> ) return false ; LLVM_FALLTHROUGH ; } case <STR_LIT> : { const MachineOperand & DstOp = MI -> getOperand ( <NUM_LIT> ) ;

const MachineOperand & SrcOp = MI -> getOperand ( <NUM_LIT> ) ;


<s> } ; DenseMap < NodeId , unsigned > OpMap ; DataFlowGraph & DFG = getDFG ( ) ; NodeList Refs = IA . Addr -> members ( DFG ) ; for ( NodeAddr < RefNode * > RA : Refs ) OpMap . insert ( std :: make_pair ( RA . Id , getOpNum ( RA . Addr -> getOp ( ) ) ) ) ; MI -> RemoveOperand ( OpNum ) ; for ( NodeAddr < RefNode * > RA : Refs ) { unsigned N = OpMap [ RA . Id ] ; if ( N < OpNum ) RA . Addr -> setRegRef ( & MI -> getOperand ( N ) , DFG ) ; else if ( N > OpNum ) RA . Addr -> setRegRef ( & MI -> getOperand ( N - <NUM_LIT> ) , DFG ) ;


<s> OpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; default : return false ; } auto IsDead = [ this ] ( NodeAddr < DefNode * > DA ) -> bool { return getDeadNodes ( ) . count ( DA . Id ) ; } ; NodeList Defs ; MachineOperand & Op = MI . getOperand ( OpNum ) ; for ( NodeAddr < DefNode * > DA : IA . Addr -> members_if ( DFG . IsDef , DFG ) ) { if ( & DA . Addr -> getOp ( ) != & Op ) continue ; Defs = DFG . getRelatedRefs ( IA , DA ) ; if ( ! llvm :: all_of ( Defs , IsDead ) ) return false ; break ; } for ( auto D : Defs ) Remove . insert ( D . Id ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> << MI ;


<s> OpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; default : return false ; } auto IsDead = [ this ] ( NodeAddr < DefNode * > DA ) -> bool { return getDeadNodes ( ) . count ( DA . Id ) ; } ; NodeList Defs ; MachineOperand & Op = MI . getOperand ( OpNum ) ; for ( NodeAddr < DefNode * > DA : IA . Addr -> members_if ( DFG . IsDef , DFG ) ) { if ( & DA . Addr -> getOp ( ) != & Op ) continue ; Defs = DFG . getRelatedRefs ( IA , DA ) ; if ( ! llvm :: all_of ( Defs , IsDead ) ) return false ; break ; } for ( auto D : Defs ) Remove . insert ( D . Id ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> << MI ; MI . setDesc ( HII . get ( NewOpc ) ) ; MI . getOperand ( OpNum + <NUM_LIT> ) . setImm ( <NUM_LIT> ) ; removeOperand ( IA , OpNum ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> << MI ;


<s> if ( DFG . IsDef ( RA ) && DeadNodes . count ( RA . Id ) ) if ( ! DeadInstrs . count ( SA . Id ) ) PartlyDead . insert ( SA . Id ) ; } } } SetVector < NodeId > Remove = DeadInstrs ; bool Changed = false ; for ( NodeId N : PartlyDead ) { auto SA = DFG . addr < StmtNode * > ( N ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> << * SA . Addr -> getCode ( ) ; Changed |= rewrite ( SA , Remove ) ; } return erase ( Remove ) || Changed ;


<s> bool Changed ; if ( RDFDump ) MF . print ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT> , nullptr ) ; TargetOperandInfo TOI ( HII ) ; DataFlowGraph G ( MF , HII , HRI , * MDT , MDF , TOI ) ; G . build ( BuildOptions :: KeepDeadPhis ) ; if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ; <ISA_LIT>CP CP ( G ) ; CP . trace ( RDFDump ) ; Changed = CP . run ( ) ; if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ; <ISA_LIT>DCE DCE ( G , * MRI ) ; DCE . trace ( RDFDump ) ; Changed |= DCE . run ( ) ; if ( Changed ) { if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' ; Liveness LV ( * MRI , G ) ; LV . trace ( RDFDump ) ; LV . computeLiveIns ( ) ; LV . resetLiveIns ( ) ;


<s> EM . insert ( std :: make_pair ( DstR , SrcR ) ) ; } ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : { const MachineOperand & DstOp = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & HiOp = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & LoOp = MI -> getOperand ( <NUM_LIT> ) ; assert ( DstOp . getSubReg ( ) == <NUM_LIT> && <STR_LIT> ) ; mapRegs ( { DstOp . getReg ( ) , <STR_LIT> } , { HiOp . getReg ( ) , HiOp . getSubReg ( ) } ) ; mapRegs ( { DstOp . getReg ( ) , <STR_LIT> } , { LoOp . getReg ( ) , LoOp . getSubReg ( ) } ) ;


<s> break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; default : return false ; } auto IsDead = [ this ] ( NodeAddr < DefNode * > DA ) -> bool { return getDeadNodes ( ) . count ( DA . Id ) ; } ; NodeList Defs ; MachineOperand & Op = MI -> getOperand ( OpNum ) ; for ( NodeAddr < DefNode * > DA : IA . Addr -> members_if ( DFG . IsDef , DFG ) ) { if ( & DA . Addr -> getOp ( ) != & Op ) continue ; Defs = DFG . getRelatedRefs ( IA , DA ) ; if ( ! std :: all_of ( Defs . begin ( ) , Defs . end ( ) , IsDead ) ) return false ; break ; } for ( auto D : Defs ) Remove . insert ( D . Id ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> << * MI ; MI -> setDesc ( HII . get ( NewOpc ) ) ; MI -> getOperand ( OpNum + <NUM_LIT> ) . setImm ( <NUM_LIT> ) ; removeOperand ( IA , OpNum ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> << * MI ;


<s> if ( RDFLimit . getPosition ( ) ) { if ( RDFCount >= RDFLimit ) return false ; RDFCount ++ ; } MDT = & getAnalysis < MachineDominatorTree > ( ) ; const auto & MDF = getAnalysis < MachineDominanceFrontier > ( ) ; const auto & HII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const auto & HRI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; bool Changed ; if ( RDFDump ) MF . print ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT> , nullptr ) ; <ISA_LIT>RegisterAliasInfo HAI ( HRI ) ; TargetOperandInfo TOI ( HII ) ; DataFlowGraph G ( MF , HII , HRI , * MDT , MDF , HAI , TOI ) ; G . build ( ) ; if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ; <ISA_LIT>CP CP ( G ) ; CP . trace ( RDFDump ) ; Changed = CP . run ( ) ; if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ; <ISA_LIT>DCE DCE ( G , * MRI ) ;


<s> DataFlowGraph G ( MF , HII , HRI , * MDT , MDF , HAI , TOI ) ; G . build ( ) ; if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ; <ISA_LIT>CP CP ( G ) ; CP . trace ( RDFDump ) ; Changed = CP . run ( ) ; if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ;


<s> CP . trace ( RDFDump ) ; Changed = CP . run ( ) ; if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ; <ISA_LIT>DCE DCE ( G , * MRI ) ; DCE . trace ( RDFDump ) ; Changed |= DCE . run ( ) ; if ( Changed ) { if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' ; Liveness LV ( * MRI , G ) ; LV . trace ( RDFDump ) ; LV . computeLiveIns ( ) ; LV . resetLiveIns ( ) ;


<s> if ( RDFLimit . getPosition ( ) ) { if ( RDFCount >= RDFLimit ) return false ; RDFCount ++ ; } MDT = & getAnalysis < MachineDominatorTree > ( ) ; const auto & MDF = getAnalysis < MachineDominanceFrontier > ( ) ; const auto & HII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const auto & HRI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; <ISA_LIT>RegisterAliasInfo HAI ( HRI ) ; TargetOperandInfo TOI ( HII ) ; if ( RDFDump ) MF . print ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT> , nullptr ) ; DataFlowGraph G ( MF , HII , HRI , * MDT , MDF , HAI , TOI ) ; G . build ( ) ; if ( RDFDump ) { dbgs ( ) << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ;


<s> FunctionPass * llvm :: create<ISA_LIT>RDFOpt ( ) { return new <ISA_LIT>RDFOpt ( ) ;


<s> AU . addRequired < MachineDominanceFrontier > ( ) ;


<s> const char * getPassName ( ) const override { return <STR_LIT> ;


<s> <ISA_LIT>CP ( DataFlowGraph & G ) : CopyPropagation ( G ) {


<s> <ISA_LIT>DCE ( DataFlowGraph & G , MachineRegisterInfo & MRI ) : DeadCodeElimination ( G , MRI ) {


<s> <ISA_LIT>RDFOpt ( ) : MachineFunctionPass ( ID ) {

initialize<ISA_LIT>RDFOptPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> initialize<ISA_LIT>RDFOptPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> const MachineOperand & HiOp = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & LoOp = MI -> getOperand ( <NUM_LIT> ) ; assert ( DstOp . getSubReg ( ) == <NUM_LIT> && <STR_LIT> ) ; mapRegs ( { DstOp . getReg ( ) , <STR_LIT> } , { HiOp . getReg ( ) , HiOp . getSubReg ( ) } ) ; mapRegs ( { DstOp . getReg ( ) , <STR_LIT> } , { LoOp . getReg ( ) , LoOp . getSubReg ( ) } ) ; return true ; } case <STR_LIT> : { const MachineOperand & A = MI -> getOperand ( <NUM_LIT> ) ; if ( ! A . isImm ( ) || A . getImm ( ) != <NUM_LIT> ) return false ; } case <STR_LIT> : { const MachineOperand & DstOp = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & SrcOp = MI -> getOperand ( <NUM_LIT> ) ; mapRegs ( { DstOp . getReg ( ) , DstOp . getSubReg ( ) } , { SrcOp . getReg ( ) , SrcOp . getSubReg ( ) } ) ; return true ;


<s> NodeList Refs = IA . Addr -> members ( getDFG ( ) ) ; for ( NodeAddr < RefNode * > RA : Refs ) OpMap . insert ( std :: make_pair ( RA . Id , getOpNum ( RA . Addr -> getOp ( ) ) ) ) ; MI -> RemoveOperand ( OpNum ) ; for ( NodeAddr < RefNode * > RA : Refs ) { unsigned N = OpMap [ RA . Id ] ; if ( N < OpNum ) RA . Addr -> setRegRef ( & MI -> getOperand ( N ) ) ; else if ( N > OpNum ) RA . Addr -> setRegRef ( & MI -> getOperand ( N - <NUM_LIT> ) ) ; }


<s> return getDeadNodes ( ) . count ( DA . Id ) ; } ; NodeList Defs ; MachineOperand & Op = MI . getOperand ( OpNum ) ; for ( NodeAddr < DefNode * > DA : IA . Addr -> members_if ( DFG . IsDef , DFG ) ) { if ( & DA . Addr -> getOp ( ) != & Op ) continue ; Defs = DFG . getRelatedRefs ( IA , DA ) ; if ( ! std :: all_of ( Defs . begin ( ) , Defs . end ( ) , IsDead ) ) return false ; break ; } for ( auto D : Defs ) Remove . insert ( D . Id ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> << MI ; MI . setDesc ( HII . get ( NewOpc ) ) ; MI . getOperand ( OpNum + <NUM_LIT> ) . setImm ( <NUM_LIT> ) ; removeOperand ( IA , OpNum ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> << MI ;


<s> R2I . insert ( std :: make_pair ( RA . Id , SA . Id ) ) ; if ( DFG . IsDef ( RA ) && DeadNodes . count ( RA . Id ) ) if ( ! DeadInstrs . count ( SA . Id ) ) PartlyDead . insert ( SA . Id ) ; } } } SetVector < NodeId > Remove = DeadInstrs ; bool Changed = false ; for ( NodeId N : PartlyDead ) { auto SA = DFG . addr < StmtNode * > ( N ) ;

if ( trace ( ) ) dbgs ( ) << <STR_LIT> << * SA . Addr -> getCode ( ) ;


<s> <ISA_LIT>CP CP ( G ) ; CP . trace ( RDFDump ) ; Changed = CP . run ( ) ; if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ; <ISA_LIT>DCE DCE ( G , * MRI ) ; DCE . trace ( RDFDump ) ; Changed |= DCE . run ( ) ; if ( Changed ) { if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' ; Liveness LV ( * MRI , G ) ; LV . trace ( RDFDump ) ; LV . computeLiveIns ( ) ; LV . resetLiveIns ( ) ; LV . resetKills ( ) ; }

if ( RDFDump ) MF . print ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT> , nullptr ) ;


<s> RDFCount ++ ; } MDT = & getAnalysis < MachineDominatorTree > ( ) ; const auto & MDF = getAnalysis < MachineDominanceFrontier > ( ) ; const auto & HII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const auto & HRI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; bool Changed ; if ( RDFDump ) MF . print ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT> , nullptr ) ; <ISA_LIT>RegisterAliasInfo HAI ( HRI ) ; TargetOperandInfo TOI ( HII ) ; DataFlowGraph G ( MF , HII , HRI , * MDT , MDF , HAI , TOI ) ; G . build ( BuildOptions :: KeepDeadPhis ) ; if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ; <ISA_LIT>CP CP ( G ) ; CP . trace ( RDFDump ) ; Changed = CP . run ( ) ; if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ; <ISA_LIT>DCE DCE ( G , * MRI ) ; DCE . trace ( RDFDump ) ; Changed |= DCE . run ( ) ;


<s> unsigned Lo = TRI . getSubReg ( RR . Reg , <STR_LIT> ) ; unsigned Hi = TRI . getSubReg ( RR . Reg , <STR_LIT> ) ; if ( RRs . count ( { Lo , <NUM_LIT> } ) && RRs . count ( { Hi , <NUM_LIT> } ) ) return true ;


<s> <ISA_LIT>RegisterAliasInfo ( const TargetRegisterInfo & TRI ) : RegisterAliasInfo ( TRI ) {


<s> auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HFI = * HST . getFrameLowering ( ) ; unsigned BP = <NUM_LIT> ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) ; int RealOffset = Offset + MI . getOperand ( FIOp + <NUM_LIT> ) . getImm ( ) ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ; return ; case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; break ; } if ( HII . isValidOffset ( Opc , RealOffset ) ) { MI . getOperand ( FIOp ) . ChangeToRegister ( BP , false ) ; MI . getOperand ( FIOp + <NUM_LIT> ) . ChangeToImmediate ( RealOffset ) ; return ; } const Function * F = MF . getFunction ( ) ; dbgs ( ) << <STR_LIT> ; if ( F ) dbgs ( ) << F -> getName ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << MB . getNumber ( ) << <STR_LIT> << MI ;


<s> switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ; return ; case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; break ; } if ( HII . isValidOffset ( Opc , RealOffset ) ) { MI . getOperand ( FIOp ) . ChangeToRegister ( BP , false ) ; MI . getOperand ( FIOp + <NUM_LIT> ) . ChangeToImmediate ( RealOffset ) ; return ; }

const Function * F = MF . getFunction ( ) ;


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg CalleeSavedRegsV3 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; switch ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . get<ISA_LIT>ArchVersion ( ) ) { case <ISA_LIT>Subtarget :: V4 : case <ISA_LIT>Subtarget :: V5 : case <ISA_LIT>Subtarget :: V55 : case <ISA_LIT>Subtarget :: V60 : return CalleeSavedRegsV3 ; } llvm_unreachable ( <STR_LIT> <STR_LIT> ) ;


<s> auto & HST = static_cast < const <ISA_LIT>Subtarget & > ( MF -> getSubtarget ( ) ) ; switch ( HST . get<ISA_LIT>ArchVersion ( ) ) { case <ISA_LIT>Subtarget :: V4 : case <ISA_LIT>Subtarget :: V5 : case <ISA_LIT>Subtarget :: V55 : case <ISA_LIT>Subtarget :: V60 : return CallerSavedRegsV4 ; } llvm_unreachable ( <STR_LIT> ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFirstCallerSavedNonParamReg ( ) const {


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( ) const {


<s> unsigned <ISA_LIT>RegisterInfo :: getRARegister ( ) const {


<s> Reserved . set ( HEXAGON_RESERVED_REG_1 ) ; Reserved . set ( HEXAGON_RESERVED_REG_2 ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getStackRegister ( ) const {


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) {


<s> return R == <STR_LIT> || R == <STR_LIT> || R == <STR_LIT> || R == <STR_LIT> || R == <STR_LIT> || R == <STR_LIT> ;


<s> bool <ISA_LIT>RegisterInfo :: isEHReturnCalleeSaveReg ( unsigned R ) const {

return R == <STR_LIT> || R == <STR_LIT> || R == <STR_LIT> || R == <STR_LIT> || R == <STR_LIT> || R == <STR_LIT> ;


<s> bool <ISA_LIT>RegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const {

return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getFrameLowering ( ) -> hasFP ( MF ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getEHExceptionRegister ( ) const {


<s> unsigned <ISA_LIT>RegisterInfo :: getEHHandlerRegister ( ) const {


<s> unsigned FPReg = getFrameRegister ( ) ; MachineLocation Dst ( MachineLocation :: VirtualFP ) ; MachineLocation Src ( FPReg , <NUM_LIT> ) ;

Moves . push_back ( MachineMove ( <NUM_LIT> , Dst , Src ) ) ;


<s> MachineLocation Src ( FPReg , <NUM_LIT> ) ; Moves . push_back ( MachineMove ( <NUM_LIT> , Dst , Src ) ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( <ISA_LIT>Subtarget & st , const <ISA_LIT>InstrInfo & tii ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , Subtarget ( st ) , TII ( tii ) {


<s> auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HFI = * HST . getFrameLowering ( ) ; unsigned BP = <NUM_LIT> ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) ; int RealOffset = Offset + MI . getOperand ( FIOp + <NUM_LIT> ) . getImm ( ) ; bool IsKill = false ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ; return ; case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; break ; } if ( ! HII . isValidOffset ( Opc , RealOffset ) ) { auto & MRI = MF . getRegInfo ( ) ; unsigned TmpR = MRI . createVirtualRegister ( & <STR_LIT> ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ;

BuildMI ( MB , II , DL , HII . get ( <STR_LIT> ) , TmpR ) . addReg ( BP ) . addImm ( RealOffset ) ;


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg CalleeSavedRegsV3 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; static const MCPhysReg CalleeSavedRegsV3EHReturn [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; bool HasEHReturn = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> hasEHReturn ( ) ; switch ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . get<ISA_LIT>ArchVersion ( ) ) { case <ISA_LIT>Subtarget :: V4 : case <ISA_LIT>Subtarget :: V5 : case <ISA_LIT>Subtarget :: V55 :


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const {


<s> case <STR_LIT> : case <STR_LIT> : return ISub [ GenIdx ] ; case <STR_LIT> : case <STR_LIT> : return VSub [ GenIdx ] ; }

if ( const TargetRegisterClass * SuperRC = * RC -> getSuperClasses ( ) ) return get<ISA_LIT>SubRegIndex ( SuperRC , GenIdx ) ;


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;


<s> MachineInstr & MI = * II ; MachineBasicBlock & MB = * MI . getParent ( ) ; MachineFunction & MF = * MB . getParent ( ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HFI = * HST . getFrameLowering ( ) ; unsigned BP = <NUM_LIT> ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) ; int RealOffset = Offset + MI . getOperand ( FIOp + <NUM_LIT> ) . getImm ( ) ; bool IsKill = false ;


<s> MachineFunction & MF = * MB . getParent ( ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HFI = * HST . getFrameLowering ( ) ; unsigned BP = <NUM_LIT> ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) ; int RealOffset = Offset + MI . getOperand ( FIOp + <NUM_LIT> ) . getImm ( ) ; bool IsKill = false ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ;

MI . RemoveOperand ( FIOp + <NUM_LIT> ) ;


<s> assert ( GenIdx == <STR_LIT> || GenIdx == <STR_LIT> ) ; static const unsigned ISub [ ] = { <STR_LIT> , <STR_LIT> } ; static const unsigned VSub [ ] = { <STR_LIT> , <STR_LIT> } ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( unsigned HwMode ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , HwMode ) {


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { return true ;


<s> } else { llvm_unreachable ( <STR_LIT> ) ; } } else { unsigned ResReg = HEXAGON_RESERVED_REG_1 ; if ( ! MFI . hasVarSizedObjects ( ) && TII . isValidOffset ( MI . getOpcode ( ) , ( FrameSize + Offset ) ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( getStackRegister ( ) , false , false , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( FrameSize + Offset ) ; } else if ( ! TII . isValidOffset ( <STR_LIT> , Offset ) ) { BuildMI ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , ResReg ) . addImm ( Offset ) ; BuildMI ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , ResReg ) . addReg ( FrameReg ) . addReg ( ResReg ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( ResReg , false , false , true ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } else { BuildMI ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , ResReg ) . addReg ( FrameReg ) . addImm ( Offset ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( ResReg , false , false , true ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } } } else { unsigned dstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , dstReg ) . addImm ( Offset ) ; BuildMI ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , dstReg ) . addReg ( FrameReg ) . addReg ( dstReg ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( dstReg , false , false , true ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; }


<s> bool enableMultipleCopyHints ( ) const override { return true ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) {


<s> static const MCPhysReg CalleeSavedRegsV3EHReturn [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; bool HasEHReturn = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> hasEHReturn ( ) ; switch ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . get<ISA_LIT>ArchVersion ( ) ) { case <ISA_LIT>Subtarget :: V4 : case <ISA_LIT>Subtarget :: V5 : case <ISA_LIT>Subtarget :: V55 : case <ISA_LIT>Subtarget :: V60 : return HasEHReturn ? CalleeSavedRegsV3EHReturn : CalleeSavedRegsV3 ;


<s> static const unsigned VSub [ ] = { <STR_LIT> , <STR_LIT> } ; static const unsigned WSub [ ] = { <STR_LIT> , <STR_LIT> } ; switch ( RC . getID ( ) ) { case <STR_LIT> : case <STR_LIT> : return ISub [ GenIdx ] ; case <STR_LIT> : return VSub [ GenIdx ] ;


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;


<s> bool <ISA_LIT>RegisterInfo :: shouldCoalesce ( MachineInstr * MI , const TargetRegisterClass * SrcRC , unsigned SubReg , const TargetRegisterClass * DstRC , unsigned DstSubReg , const TargetRegisterClass * NewRC , LiveIntervals & LIS ) const { MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! HST . useHVXOps ( ) || NewRC -> getID ( ) != <STR_LIT> . getID ( ) ) return true ; bool SmallSrc = SrcRC -> getID ( ) == <STR_LIT> . getID ( ) ; bool SmallDst = DstRC -> getID ( ) == <STR_LIT> . getID ( ) ; if ( ! SmallSrc && ! SmallDst ) return true ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;

const SlotIndexes & Indexes = * LIS . getSlotIndexes ( ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) {


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; return Reserved ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( <ISA_LIT>Subtarget & st ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , Subtarget ( st ) {


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ;


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ;


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;

for ( int x = Reserved . find_first ( ) ; x >= <NUM_LIT> ; x = Reserved . find_next ( x ) ) markSuperRegs ( Reserved , x ) ;


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;


<s> } else if ( MI . getOpcode ( ) == <STR_LIT> ) { } else { llvm_unreachable ( <STR_LIT> ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getNumRegPressureSets ( ) const { return <NUM_LIT> ;


<s> unsigned <ISA_LIT>RegisterInfo :: getNumRegPressureSets ( ) const {


<s> <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; static const unsigned RCSetStartTable [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; unsigned SetListStart = RCSetStartTable [ RC -> getID ( ) ] ;


<s> static const unsigned RCSetStartTable [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; unsigned SetListStart = RCSetStartTable [ RC -> getID ( ) ] ; return & RCSetsTable [ SetListStart ] ;


<s> { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } } ; return RCWeightTable [ RC -> getID ( ) ] ;


<s> static const RegClassWeight RCWeightTable [ ] = { { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } } ;

return RCWeightTable [ RC -> getID ( ) ] ;


<s> static const int RegPressureLimit [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ;

assert ( ( Idx < <NUM_LIT> ) && <STR_LIT> ) ;


<s> assert ( ( Idx < <NUM_LIT> ) && <STR_LIT> ) ; return RegPressureSetName [ Idx ] ;


<s> V0 , V1 , V2 , V3 , V4 , V5 , V6 , V7 , V8 , V9 , V10 , V11 , V12 , V13 , V14 , V15 , V16 , V17 , V18 , V19 , V20 , V21 , V22 , V23 , V24 , V25 , V26 , V27 , V28 , V29 , V30 , V31 , <NUM_LIT> } ; static const MCPhysReg VecDbl [ ] = { W0 , W1 , W2 , W3 , W4 , W5 , W6 , W7 , W8 , W9 , W10 , W11 , W12 , W13 , W14 , W15 , <NUM_LIT> } ; static const MCPhysReg VecPred [ ] = { Q0 , Q1 , Q2 , Q3 , <NUM_LIT> } ; switch ( RC -> getID ( ) ) { case IntRegsRegClassID : return Int32 ; case DoubleRegsRegClassID : return Int64 ; case PredRegsRegClassID : return Pred ; case HvxVRRegClassID : return VecSgl ; case HvxWRRegClassID : return VecDbl ; case HvxQRRegClassID : return VecPred ; default : break ; } static const MCPhysReg Empty [ ] = { <NUM_LIT> } ;

dbgs ( ) << <STR_LIT> << getRegClassName ( RC ) << <STR_LIT> ;


<s> P0 , P1 , P2 , P3 , <NUM_LIT> } ; static const MCPhysReg VecSgl [ ] = { V0 , V1 , V2 , V3 , V4 , V5 , V6 , V7 , V8 , V9 , V10 , V11 , V12 , V13 , V14 , V15 , V16 , V17 , V18 , V19 , V20 , V21 , V22 , V23 , V24 , V25 , V26 , V27 , V28 , V29 , V30 , V31 , <NUM_LIT> } ; static const MCPhysReg VecDbl [ ] = { W0 , W1 , W2 , W3 , W4 , W5 , W6 , W7 , W8 , W9 , W10 , W11 , W12 , W13 , W14 , W15 , <NUM_LIT> } ; static const MCPhysReg VecPred [ ] = { Q0 , Q1 , Q2 , Q3 , <NUM_LIT> } ; switch ( RC -> getID ( ) ) { case IntRegsRegClassID : return Int32 ; case DoubleRegsRegClassID : return Int64 ; case PredRegsRegClassID : return Pred ; case HvxVRRegClassID : return VecSgl ; case HvxWRRegClassID : return VecDbl ; case HvxQRRegClassID : return VecPred ; default : break ; } static const MCPhysReg Empty [ ] = { <NUM_LIT> } ; dbgs ( ) << <STR_LIT> << getRegClassName ( RC ) << <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ;


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;


<s> MachineBasicBlock & MB = * MI . getParent ( ) ; MachineFunction & MF = * MB . getParent ( ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HFI = * HST . getFrameLowering ( ) ; Register BP ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) . getFixed ( ) ; int RealOffset = Offset + MI . getOperand ( FIOp + <NUM_LIT> ) . getImm ( ) ; bool IsKill = false ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ; return ; case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; break ; } if ( ! HII . isValidOffset ( Opc , RealOffset , this ) ) { auto & MRI = MF . getRegInfo ( ) ; Register TmpR = MRI . createVirtualRegister ( & <STR_LIT> ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( MB , II , DL , HII . get ( <STR_LIT> ) , TmpR ) . addReg ( BP ) . addImm ( RealOffset ) ; BP = TmpR ;


<s> Register <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; if ( TFI -> hasFP ( MF ) ) return getFrameRegister ( ) ;


<s> Register <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const {

const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ;


<s> unsigned BP = <NUM_LIT> ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) ; int RealOffset = Offset + MI . getOperand ( FIOp + <NUM_LIT> ) . getImm ( ) ; bool IsKill = false ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ; return ; case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; break ; } if ( ! HII . isValidOffset ( Opc , RealOffset , this ) ) { auto & MRI = MF . getRegInfo ( ) ; Register TmpR = MRI . createVirtualRegister ( & <STR_LIT> ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ;


<s> void <ISA_LIT>RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOp , RegScavenger * RS ) const { assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; MachineInstr & MI = * II ; MachineBasicBlock & MB = * MI . getParent ( ) ; MachineFunction & MF = * MB . getParent ( ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HFI = * HST . getFrameLowering ( ) ; unsigned BP = <NUM_LIT> ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) ; int RealOffset = Offset + MI . getOperand ( FIOp + <NUM_LIT> ) . getImm ( ) ; bool IsKill = false ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ; return ; case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; break ; } if ( ! HII . isValidOffset ( Opc , RealOffset , this ) ) { auto & MRI = MF . getRegInfo ( ) ; Register TmpR = MRI . createVirtualRegister ( & <STR_LIT> ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( MB , II , DL , HII . get ( <STR_LIT> ) , TmpR ) . addReg ( BP ) . addImm ( RealOffset ) ; BP = TmpR ; RealOffset = <NUM_LIT> ; IsKill = true ; }

MI . getOperand ( FIOp ) . ChangeToRegister ( BP , false , false , IsKill ) ;


<s> MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ; return ; case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; break ; } if ( ! HII . isValidOffset ( Opc , RealOffset , this ) ) { auto & MRI = MF . getRegInfo ( ) ; Register TmpR = MRI . createVirtualRegister ( & <STR_LIT> ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( MB , II , DL , HII . get ( <STR_LIT> ) , TmpR ) . addReg ( BP ) . addImm ( RealOffset ) ; BP = TmpR ; RealOffset = <NUM_LIT> ; IsKill = true ; } MI . getOperand ( FIOp ) . ChangeToRegister ( BP , false , false , IsKill ) ; MI . getOperand ( FIOp + <NUM_LIT> ) . ChangeToImmediate ( RealOffset ) ;


<s> MachineInstr & MI = * II ; MachineBasicBlock & MB = * MI . getParent ( ) ; MachineFunction & MF = * MB . getParent ( ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HFI = * HST . getFrameLowering ( ) ; Register BP ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) ; int RealOffset = Offset + MI . getOperand ( FIOp + <NUM_LIT> ) . getImm ( ) ; bool IsKill = false ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ; return ; case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; break ; } if ( ! HII . isValidOffset ( Opc , RealOffset , this ) ) { auto & MRI = MF . getRegInfo ( ) ;

Register TmpR = MRI . createVirtualRegister ( & <STR_LIT> ) ;


<s> static const MCPhysReg CalleeSavedRegsV3EHReturn [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; bool HasEHReturn = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> hasEHReturn ( ) ; switch ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . get<ISA_LIT>ArchVersion ( ) ) { case <STR_LIT> :: V4 : case <STR_LIT> :: V5 : case <STR_LIT> :: V55 : case <STR_LIT> :: V60 : case <STR_LIT> :: V62 :

return HasEHReturn ? CalleeSavedRegsV3EHReturn : CalleeSavedRegsV3 ;


<s> MachineBasicBlock & MB = * MI . getParent ( ) ; MachineFunction & MF = * MB . getParent ( ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HFI = * HST . getFrameLowering ( ) ; unsigned BP = <NUM_LIT> ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) ; int RealOffset = Offset + MI . getOperand ( FIOp + <NUM_LIT> ) . getImm ( ) ; bool IsKill = false ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ; return ; case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; break ; }

if ( ! HII . isValidOffset ( Opc , RealOffset ) ) {


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;


<s> } else if ( MI . getOpcode ( ) == <STR_LIT> ) { } else {


<s> static const TargetRegisterClass * const CalleeSavedRegClassesV3 [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , } ; switch ( Subtarget . get<ISA_LIT>ArchVersion ( ) ) { case <ISA_LIT>Subtarget :: V1 : break ;


<s> unsigned <ISA_LIT>RegisterInfo :: getEHExceptionRegister ( ) const { assert ( <NUM_LIT> && <STR_LIT> ) ; return <NUM_LIT> ;


<s> const uint16_t * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegsV2 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; static const uint16_t CalleeSavedRegsV3 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; switch ( Subtarget . get<ISA_LIT>ArchVersion ( ) ) {


<s> bool IsKill = false ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ; return ; case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; break ; } if ( ! HII . isValidOffset ( Opc , RealOffset ) ) { auto & MRI = MF . getRegInfo ( ) ; unsigned TmpR = MRI . createVirtualRegister ( & <STR_LIT> ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( MB , II , DL , HII . get ( <STR_LIT> ) , TmpR ) . addReg ( BP ) . addImm ( RealOffset ) ;


<s> unsigned SP = getStackRegister ( ) , FP = getFrameRegister ( ) ; unsigned AP = <NUM_LIT> ; if ( MachineInstr * AI = HFI . getAlignaInstr ( MF ) ) AP = AI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned FrameSize = MFI . getStackSize ( ) ; if ( MI . isDebugValue ( ) || MI . isInlineAsm ( ) ) { MI . getOperand ( FIOp ) . ChangeToRegister ( SP , false ) ; MI . getOperand ( FIOp + <NUM_LIT> ) . ChangeToImmediate ( Offset + FrameSize ) ; return ; } bool UseFP = false , UseAP = false ; if ( MFI . isFixedObjectIndex ( FI ) || MFI . isObjectPreAllocated ( FI ) ) { UseFP = HasAlloca || HasAlign ; } else { if ( HasAlloca ) { if ( HasAlign ) UseAP = true ; else UseFP = true ; } } unsigned Opc = MI . getOpcode ( ) ; bool ValidSP = HII . isValidOffset ( Opc , FrameSize + Offset ) ; bool ValidFP = HII . isValidOffset ( Opc , Offset ) ; int64_t RealOffset = Offset ; if ( ! UseFP && ! UseAP ) RealOffset = FrameSize + Offset ; switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ;


<s> if ( ! UseFP && ! UseAP ) RealOffset = FrameSize + Offset ; switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ; return ; case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; break ; } unsigned BP = <NUM_LIT> ; bool Valid = false ; if ( UseFP ) { BP = FP ; Valid = ValidFP ; } else if ( UseAP ) { BP = AP ; Valid = ValidFP ; } else { BP = SP ; Valid = ValidSP ; } if ( Valid ) { MI . getOperand ( FIOp ) . ChangeToRegister ( BP , false ) ; MI . getOperand ( FIOp + <NUM_LIT> ) . ChangeToImmediate ( RealOffset ) ; return ; } const Function * F = MF . getFunction ( ) ; dbgs ( ) << <STR_LIT> ; if ( F ) dbgs ( ) << F -> getName ( ) ; else dbgs ( ) << <STR_LIT> ;

dbgs ( ) << <STR_LIT> << MB . getNumber ( ) << <STR_LIT> << MI ;


<s> static const MCPhysReg CalleeSavedRegsV3 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; switch ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . get<ISA_LIT>ArchVersion ( ) ) { case <ISA_LIT>Subtarget :: V4 : case <ISA_LIT>Subtarget :: V5 : return CalleeSavedRegsV3 ;


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCallerSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg CallerSavedRegsV4 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ;

auto & HST = static_cast < const <ISA_LIT>Subtarget & > ( MF -> getSubtarget ( ) ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const {

const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ;


<s> return MFI -> getMaxAlignment ( ) > <NUM_LIT> ;


<s> if ( TFI -> hasFP ( MF ) ) return <STR_LIT> ;


<s> const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ;


<s> bool <ISA_LIT>RegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const {


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;


<s> & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , } ; switch ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . get<ISA_LIT>ArchVersion ( ) ) { case <ISA_LIT>Subtarget :: V4 : case <ISA_LIT>Subtarget :: V5 : return CalleeSavedRegClassesV3 ; }


<s> if ( Subtarget . hasV4TOps ( ) ) { if ( TII . isConstExtended ( & MI ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; TII . immediateExtend ( & MI ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } } else { unsigned ResReg = HEXAGON_RESERVED_REG_1 ; if ( ! MFI . hasVarSizedObjects ( ) && TII . isValidOffset ( MI . getOpcode ( ) , ( FrameSize + Offset ) ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( getStackRegister ( ) , false , false , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( FrameSize + Offset ) ; } else if ( ! TII . isValidOffset ( <STR_LIT> , Offset ) ) { BuildMI ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , ResReg ) . addImm ( Offset ) ; BuildMI ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , ResReg ) . addReg ( FrameReg ) . addReg ( ResReg ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( ResReg , false , false , true ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } else { BuildMI ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , ResReg ) . addReg ( FrameReg ) . addImm ( Offset ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( ResReg , false , false , true ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } } } else { unsigned dstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , dstReg ) . addImm ( Offset ) ; BuildMI ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , dstReg ) . addReg ( FrameReg ) . addReg ( dstReg ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( dstReg , false , false , true ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } } else { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; } }


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCallerSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg CallerSavedRegsV4 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; switch ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . get<ISA_LIT>ArchVersion ( ) ) { case <ISA_LIT>Subtarget :: V4 : case <ISA_LIT>Subtarget :: V5 : case <ISA_LIT>Subtarget :: V55 : case <ISA_LIT>Subtarget :: V60 : return CallerSavedRegsV4 ; }


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCallerSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg CallerSavedRegsV4 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; switch ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . get<ISA_LIT>ArchVersion ( ) ) { case <ISA_LIT>Subtarget :: V4 : case <ISA_LIT>Subtarget :: V5 : case <ISA_LIT>Subtarget :: V55 :


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( HEXAGON_RESERVED_REG_1 ) ; Reserved . set ( HEXAGON_RESERVED_REG_2 ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { return true ;


<s> size_t off = <NUM_LIT> ; for ( size_t bit = <NUM_LIT> ; bit != sizeof ( T1 ) * <NUM_LIT> ; ++ bit ) { const bool valBit = ( pData >> off ) & <NUM_LIT> ; const bool maskBit = ( pMask >> bit ) & <NUM_LIT> ;


<s> rel_entry . setType ( pTarget . getCopyRelType ( ) ) ; assert ( pSym . outSymbol ( ) -> hasFragRef ( ) ) ; rel_entry . targetRef ( ) . assign ( * pSym . outSymbol ( ) -> fragRef ( ) ) ; rel_entry . setSymInfo ( & pSym ) ;


<s> Relocation & rel_entry = * pTarget . getRelaDyn ( ) . create ( ) ; rel_entry . setType ( pTarget . getCopyRelType ( ) ) ;

assert ( pSym . outSymbol ( ) -> hasFragRef ( ) ) ;


<s> switch ( pReloc . type ( ) ) { case llvm :: ELF :: R_HEX_LO16 : bitMask = <NUM_LIT> ; break ; case llvm :: ELF :: R_HEX_HI16 : shift = <NUM_LIT> ; bitMask = <NUM_LIT> ; break ; case llvm :: ELF :: R_HEX_32 : bitMask = <NUM_LIT> ; break ; case llvm :: ELF :: R_HEX_16 : bitMask = <NUM_LIT> ; alignment = <NUM_LIT> ; break ; case llvm :: ELF :: R_HEX_8 : bitMask = <NUM_LIT> ; alignment = <NUM_LIT> ; break ; case llvm :: ELF :: R_HEX_12_X : bitMask = <NUM_LIT> ; break ; case llvm :: ELF :: R_HEX_32_6_X : bitMask = <NUM_LIT> ; shift = <NUM_LIT> ; effectiveBits = <NUM_LIT> ; break ; case llvm :: ELF :: R_HEX_16_X : case llvm :: ELF :: R_HEX_11_X : case llvm :: ELF :: R_HEX_10_X : case llvm :: ELF :: R_HEX_9_X : case llvm :: ELF :: R_HEX_8_X : case llvm :: ELF :: R_HEX_7_X : case llvm :: ELF :: R_HEX_6_X : bitMask = FINDBITMASK ( pReloc . target ( ) ) ; break ; default : fatal ( diag :: unsupported_relocation ) << static_cast < int > ( pReloc . type ( ) ) << <STR_LIT> ; } if ( ( shift != <NUM_LIT> ) && ( result % alignment != <NUM_LIT> ) ) return Relocator :: BadReloc ; result >>= shift ; if ( effectiveBits ) {

uint32_t range = <NUM_LIT> << effectiveBits ;


<s> break ; case llvm :: ELF :: R_HEX_12_X : bitMask = <NUM_LIT> ; break ; case llvm :: ELF :: R_HEX_32_6_X : bitMask = <NUM_LIT> ; shift = <NUM_LIT> ; effectiveBits = <NUM_LIT> ; break ; case llvm :: ELF :: R_HEX_16_X : case llvm :: ELF :: R_HEX_11_X : case llvm :: ELF :: R_HEX_10_X : case llvm :: ELF :: R_HEX_9_X : case llvm :: ELF :: R_HEX_8_X : case llvm :: ELF :: R_HEX_7_X : case llvm :: ELF :: R_HEX_6_X : bitMask = FINDBITMASK ( pReloc . target ( ) ) ; break ; default : fatal ( diag :: unsupported_relocation ) << static_cast < int > ( pReloc . type ( ) ) << <STR_LIT> ; } if ( ( shift != <NUM_LIT> ) && ( result % alignment != <NUM_LIT> ) ) return Relocator :: BadReloc ; result >>= shift ; if ( effectiveBits ) { uint32_t range = <NUM_LIT> << effectiveBits ; if ( result > ( range - <NUM_LIT> ) ) return Relocator :: Overflow ; }

pReloc . target ( ) |= ApplyMask < uint32_t > ( bitMask , result ) ;


<s> void applyDebugStringOffset ( Relocation & pReloc , uint32_t pOffset ) {


<s> Relocator :: Result <ISA_LIT>Relocator :: applyRelocation ( Relocation & pRelocation ) { Relocation :: Type type = pRelocation . type ( ) ; if ( type > <NUM_LIT> ) {


<s> if ( type > <NUM_LIT> ) { return Relocator :: Unknown ; }

return ApplyFunctions [ type ] . func ( pRelocation , * this ) ;


<s> assert ( bss_sect_hdr != NULL ) ; SectionData * bss_section = NULL ; if ( bss_sect_hdr -> hasSectionData ( ) ) bss_section = bss_sect_hdr -> getSectionData ( ) ; else bss_section = IRBuilder :: CreateSectionData ( * bss_sect_hdr ) ; uint32_t addralign = config ( ) . targets ( ) . bitclass ( ) / <NUM_LIT> ; Fragment * frag = new FillFragment ( <NUM_LIT> , <NUM_LIT> , pSym . size ( ) ) ; uint64_t size = ObjectBuilder :: AppendFragment ( * frag , * bss_section , addralign ) ; bss_sect_hdr -> setSize ( bss_sect_hdr -> size ( ) + size ) ; ResolveInfo :: Binding binding = ( ResolveInfo :: Binding ) pSym . binding ( ) ; if ( binding == ResolveInfo :: Weak ) binding = ResolveInfo :: Global ;

LDSymbol * cpy_sym = pBuilder . AddSymbol < IRBuilder :: Force , IRBuilder :: Resolve > ( pSym . name ( ) , ( ResolveInfo :: Type ) pSym . type ( ) , ResolveInfo :: Define , binding , pSym . size ( ) , <NUM_LIT> , FragmentRef :: Create ( * frag , <NUM_LIT> ) , ( ResolveInfo :: Visibility ) pSym . other ( ) ) ;


<s> uint32_t getDebugStringOffset ( Relocation & pReloc ) const { return <NUM_LIT> ;


<s> const char * <ISA_LIT>Relocator :: getName ( Relocation :: Type pType ) const {

return ApplyFunctions [ pType ] . name ;


<s> return ApplyFunctions [ pType ] . name ;


<s> Relocator :: Size <ISA_LIT>Relocator :: getSize ( Relocation :: Type pType ) const {


<s> SymGOTPLTMap & getSymGOTPLTMap ( ) { return m_SymGOTPLTMap ;


<s> <ISA_LIT>LDBackend & ld_backend = pParent . getTarget ( ) ; Relocation & rela_entry = * ld_backend . getRelaDyn ( ) . create ( ) ; rela_entry . setType ( pType ) ; rela_entry . targetRef ( ) . assign ( pFrag , pOffset ) ;

if ( pType == llvm :: ELF :: R_HEX_RELATIVE || pSym == NULL ) rela_entry . setSymInfo ( <NUM_LIT> ) ;


<s> static Relocator :: Address helper_get_GOT_address ( ResolveInfo & pSym , <ISA_LIT>Relocator & pParent ) { <ISA_LIT>GOTEntry * got_entry = pParent . getSymGOTMap ( ) . lookUp ( pSym ) ;


<s> assert ( got_entry != NULL ) ; return pParent . getTarget ( ) . getGOT ( ) . addr ( ) + got_entry -> getOffset ( ) ;


<s> static Relocator :: Address helper_get_PLT_address ( ResolveInfo & pSym , <ISA_LIT>Relocator & pParent ) { PLTEntryBase * plt_entry = pParent . getSymPLTMap ( ) . lookUp ( pSym ) ; assert ( plt_entry != NULL ) ;

return pParent . getTarget ( ) . getPLT ( ) . addr ( ) + plt_entry -> getOffset ( ) ;


<s> static <ISA_LIT>GOTEntry & helper_GOT_init ( Relocation & pReloc , bool pHasRel , <ISA_LIT>Relocator & pParent ) { ResolveInfo * rsym = pReloc . symInfo ( ) ; <ISA_LIT>LDBackend & ld_backend = pParent . getTarget ( ) ; assert ( pParent . getSymGOTMap ( ) . lookUp ( * rsym ) == NULL ) ; <ISA_LIT>GOTEntry * got_entry = ld_backend . getGOT ( ) . create ( ) ; pParent . getSymGOTMap ( ) . record ( * rsym , * got_entry ) ; if ( ! pHasRel ) { got_entry -> setValue ( <ISA_LIT>Relocator :: SymVal ) ; } else { if ( helper_use_relative_reloc ( * rsym , pParent ) ) { helper_DynRel_init ( rsym , * got_entry , <NUM_LIT> , llvm :: ELF :: R_HEX_RELATIVE , pParent ) ; got_entry -> setValue ( <ISA_LIT>Relocator :: SymVal ) ; } else {

helper_DynRel_init ( rsym , * got_entry , <NUM_LIT> , llvm :: ELF :: R_HEX_GLOB_DAT , pParent ) ;


<s> <ISA_LIT>LDBackend & ld_backend = pParent . getTarget ( ) ; assert ( pParent . getSymGOTMap ( ) . lookUp ( * rsym ) == NULL ) ; <ISA_LIT>GOTEntry * got_entry = ld_backend . getGOT ( ) . create ( ) ; pParent . getSymGOTMap ( ) . record ( * rsym , * got_entry ) ;


<s> pParent . getSymGOTPLTMap ( ) . record ( * rsym , * gotplt_entry ) ; Relocation & rela_entry = * ld_backend . getRelaPLT ( ) . create ( ) ; rela_entry . setType ( llvm :: ELF :: R_HEX_JMP_SLOT ) ; rela_entry . targetRef ( ) . assign ( * gotplt_entry ) ; rela_entry . setSymInfo ( rsym ) ; return * plt_entry ;


<s> static bool helper_use_relative_reloc ( const ResolveInfo & pSym , const <ISA_LIT>Relocator & pFactory ) {

if ( pSym . isDyn ( ) || pSym . isUndef ( ) || pFactory . getTarget ( ) . isSymbolPreemptible ( pSym ) ) return false ;


<s> <ISA_LIT>Relocator :: <ISA_LIT>Relocator ( <ISA_LIT>LDBackend & pParent , const LinkerConfig & pConfig ) : Relocator ( pConfig ) , m_Target ( pParent ) {


<s> const LDSection & out_sect = input_sym -> fragRef ( ) -> frag ( ) -> getParent ( ) -> getSection ( ) ; ResolveInfo * sym_info = pModule . getSectionSymbolSet ( ) . get ( out_sect ) -> resolveInfo ( ) ; pReloc . setSymInfo ( sym_info ) ; }


<s> return Relocator :: OK ; } if ( ! rsym -> isLocal ( ) ) { if ( rsym -> reserved ( ) & <ISA_LIT>Relocator :: ReservePLT ) { S = helper_get_PLT_address ( * rsym , pParent ) ; } if ( has_dyn_rel ) { if ( llvm :: ELF :: R_HEX_32 == pReloc . type ( ) && helper_use_relative_reloc ( * rsym , pParent ) ) { rel_entry -> setAddend ( S + A ) ; } else { rel_entry -> setAddend ( A ) ; return Relocator :: OK ; } }


<s> break ; case llvm :: ELF :: R_HEX_GOT_11_X : bitMask = FINDBITMASK ( pReloc . target ( ) ) ; result_u = GOT_S - GOT ; pReloc . target ( ) |= ApplyMask < uint32_t > ( bitMask , result_u ) ; return Relocator :: OK ; default : fatal ( diag :: unsupported_relocation ) << static_cast < int > ( pReloc . type ( ) ) << <STR_LIT> ; } if ( ( shift != <NUM_LIT> ) && ( result % alignment != <NUM_LIT> ) ) return Relocator :: BadReloc ; result >>= shift ; if ( effectiveBits ) { int32_t range = <NUM_LIT> << ( effectiveBits - <NUM_LIT> ) ; if ( ( result > range - <NUM_LIT> ) || ( result < - range ) ) return Relocator :: Overflow ; }

pReloc . target ( ) |= ApplyMask < int32_t > ( bitMask , result ) ;


<s> Relocator :: Result relocGOT ( Relocation & pReloc , <ISA_LIT>Relocator & pParent ) { if ( ! ( pReloc . symInfo ( ) -> reserved ( ) & <ISA_LIT>Relocator :: ReserveGOT ) ) { return Relocator :: BadReloc ; } <ISA_LIT>GOTEntry * got_entry = pParent . getSymGOTMap ( ) . lookUp ( * pReloc . symInfo ( ) ) ; assert ( got_entry != NULL ) ; if ( <ISA_LIT>Relocator :: SymVal == got_entry -> getValue ( ) ) got_entry -> setValue ( pReloc . symValue ( ) ) ; Relocator :: Address GOT_S = helper_get_GOT_address ( * pReloc . symInfo ( ) , pParent ) ; Relocator :: Address GOT = pParent . getTarget ( ) . getGOTSymbolAddr ( ) ; int32_t result = ( int32_t ) ( GOT_S - GOT ) ; uint32_t effectiveBits = <NUM_LIT> ; uint32_t alignment = <NUM_LIT> ; uint32_t bitMask = <NUM_LIT> ; uint32_t result_u ; uint32_t shift = <NUM_LIT> ; switch ( pReloc . type ( ) ) { case llvm :: ELF :: R_HEX_GOT_LO16 : bitMask = <NUM_LIT> ; break ; case llvm :: ELF :: R_HEX_GOT_HI16 :


<s> Relocator :: Address S = pReloc . symValue ( ) ; Relocator :: DWord A = pReloc . addend ( ) ; Relocator :: DWord P = pReloc . place ( ) ; FragmentRef & target_fragref = pReloc . targetRef ( ) ; Fragment * target_frag = target_fragref . frag ( ) ; LDSection & target_sect = target_frag -> getParent ( ) -> getSection ( ) ; result = ( int64_t ) ( S + A - P ) ; if ( ( llvm :: ELF :: SHF_ALLOC & target_sect . flag ( ) ) == <NUM_LIT> ) {


<s> ResolveInfo * rsym = pReloc . symInfo ( ) ; int64_t result ; Relocator :: Address S = pReloc . symValue ( ) ; Relocator :: DWord A = pReloc . addend ( ) ; Relocator :: DWord P = pReloc . place ( ) ; FragmentRef & target_fragref = pReloc . targetRef ( ) ; Fragment * target_frag = target_fragref . frag ( ) ; LDSection & target_sect = target_frag -> getParent ( ) -> getSection ( ) ; result = ( int64_t ) ( S + A - P ) ; if ( ( llvm :: ELF :: SHF_ALLOC & target_sect . flag ( ) ) == <NUM_LIT> ) { return applyRel ( pReloc , result ) ; } if ( ! rsym -> isLocal ( ) ) {

if ( rsym -> reserved ( ) & <ISA_LIT>Relocator :: ReservePLT ) {


<s> else PLT_S = pReloc . symValue ( ) ; Relocator :: Address P = pReloc . place ( ) ; uint32_t bitMask = FINDBITMASK ( pReloc . target ( ) ) ; uint32_t result = ( PLT_S + pReloc . addend ( ) - P ) >> <NUM_LIT> ; pReloc . target ( ) = pReloc . target ( ) | ApplyMask < uint32_t > ( bitMask , result ) ;


<s> Relocator :: Address P = pReloc . place ( ) ; uint32_t bitMask = FINDBITMASK ( pReloc . target ( ) ) ; uint32_t result = ( PLT_S + pReloc . addend ( ) - P ) >> <NUM_LIT> ; pReloc . target ( ) = pReloc . target ( ) | ApplyMask < uint32_t > ( bitMask , result ) ;


<s> case llvm :: ELF :: R_HEX_6_X : assert ( ! ( rsym -> reserved ( ) & ReserveRel ) && <STR_LIT> ) ; return ; case llvm :: ELF :: R_HEX_32 : if ( ld_backend . symbolNeedsPLT ( * rsym ) ) { if ( ! ( rsym -> reserved ( ) & ReservePLT ) ) { helper_PLT_init ( pReloc , * this ) ; rsym -> setReserved ( rsym -> reserved ( ) | ReservePLT ) ; } } if ( ld_backend . symbolNeedsDynRel ( * rsym , ( rsym -> reserved ( ) & ReservePLT ) , true ) ) { if ( ld_backend . symbolNeedsCopyReloc ( pReloc , * rsym ) ) { LDSymbol & cpy_sym = defineSymbolforCopyReloc ( pBuilder , * rsym , ld_backend ) ; addCopyReloc ( * cpy_sym . resolveInfo ( ) , ld_backend ) ; } else { Relocation & reloc = helper_DynRel_init ( rsym , * pReloc . targetRef ( ) . frag ( ) , pReloc . targetRef ( ) . offset ( ) , llvm :: ELF :: R_HEX_RELATIVE , * this ) ; getRelRelMap ( ) . record ( pReloc , reloc ) ; rsym -> setReserved ( rsym -> reserved ( ) | ReserveRel ) ; ld_backend . checkAndSetHasTextRel ( * pSection . getLink ( ) ) ; } } return ; case llvm :: ELF :: R_HEX_GOTREL_LO16 : case llvm :: ELF :: R_HEX_GOTREL_HI16 : case llvm :: ELF :: R_HEX_GOTREL_32 : case llvm :: ELF :: R_HEX_GOTREL_32_6_X : case llvm :: ELF :: R_HEX_GOTREL_16_X :


<s> } } if ( ld_backend . symbolNeedsDynRel ( * rsym , ( rsym -> reserved ( ) & ReservePLT ) , true ) ) { if ( ld_backend . symbolNeedsCopyReloc ( pReloc , * rsym ) ) { LDSymbol & cpy_sym = defineSymbolforCopyReloc ( pBuilder , * rsym , ld_backend ) ; addCopyReloc ( * cpy_sym . resolveInfo ( ) , ld_backend ) ; } else { Relocation & reloc = helper_DynRel_init ( rsym , * pReloc . targetRef ( ) . frag ( ) , pReloc . targetRef ( ) . offset ( ) , llvm :: ELF :: R_HEX_RELATIVE , * this ) ; getRelRelMap ( ) . record ( pReloc , reloc ) ; rsym -> setReserved ( rsym -> reserved ( ) | ReserveRel ) ; ld_backend . checkAndSetHasTextRel ( * pSection . getLink ( ) ) ; } } return ; case llvm :: ELF :: R_HEX_GOTREL_LO16 : case llvm :: ELF :: R_HEX_GOTREL_HI16 : case llvm :: ELF :: R_HEX_GOTREL_32 : case llvm :: ELF :: R_HEX_GOTREL_32_6_X : case llvm :: ELF :: R_HEX_GOTREL_16_X : case llvm :: ELF :: R_HEX_GOTREL_11_X : return ; case llvm :: ELF :: R_HEX_GOT_LO16 : case llvm :: ELF :: R_HEX_GOT_HI16 : case llvm :: ELF :: R_HEX_GOT_32 : case llvm :: ELF :: R_HEX_GOT_16 : case llvm :: ELF :: R_HEX_GOT_32_6_X : case llvm :: ELF :: R_HEX_GOT_16_X : case llvm :: ELF :: R_HEX_GOT_11_X : if ( rsym -> reserved ( ) & ReserveGOT ) return ; if ( config ( ) . isCodeStatic ( ) ) helper_GOT_init ( pReloc , false , * this ) ; else helper_GOT_init ( pReloc , true , * this ) ; rsym -> setReserved ( rsym -> reserved ( ) | ReserveGOT ) ; return ; case llvm :: ELF :: R_HEX_B22_PCREL : case llvm :: ELF :: R_HEX_B15_PCREL : case llvm :: ELF :: R_HEX_B7_PCREL : case llvm :: ELF :: R_HEX_B13_PCREL : case llvm :: ELF :: R_HEX_B9_PCREL : case llvm :: ELF :: R_HEX_B32_PCREL_X :


<s> case llvm :: ELF :: R_HEX_LO16 : case llvm :: ELF :: R_HEX_HI16 : case llvm :: ELF :: R_HEX_16 : case llvm :: ELF :: R_HEX_8 : case llvm :: ELF :: R_HEX_32_6_X : case llvm :: ELF :: R_HEX_16_X : case llvm :: ELF :: R_HEX_12_X : case llvm :: ELF :: R_HEX_11_X : case llvm :: ELF :: R_HEX_10_X : case llvm :: ELF :: R_HEX_9_X : case llvm :: ELF :: R_HEX_8_X : case llvm :: ELF :: R_HEX_7_X : case llvm :: ELF :: R_HEX_6_X : assert ( ! ( rsym -> reserved ( ) & ReserveRel ) && <STR_LIT> ) ; return ; case llvm :: ELF :: R_HEX_32 : if ( config ( ) . isCodeIndep ( ) ) { Relocation & reloc = helper_DynRel_init ( rsym , * pReloc . targetRef ( ) . frag ( ) , pReloc . targetRef ( ) . offset ( ) , llvm :: ELF :: R_HEX_RELATIVE , * this ) ; getRelRelMap ( ) . record ( pReloc , reloc ) ; rsym -> setReserved ( rsym -> reserved ( ) | ReserveRel ) ; getTarget ( ) . checkAndSetHasTextRel ( * pSection . getLink ( ) ) ; } return ; default : return ; }


<s> assert ( rsym != NULL && <STR_LIT> ) ; if ( config ( ) . isCodeStatic ( ) ) return ; assert ( pSection . getLink ( ) != NULL ) ; if ( ( pSection . getLink ( ) -> flag ( ) & llvm :: ELF :: SHF_ALLOC ) == <NUM_LIT> ) return ; if ( rsym -> isLocal ( ) ) scanLocalReloc ( pReloc , pLinker , pModule , pSection ) ; else scanGlobalReloc ( pReloc , pLinker , pModule , pSection ) ;

if ( rsym -> isUndef ( ) && ! rsym -> isDyn ( ) && ! rsym -> isWeak ( ) && ! rsym -> isNull ( ) ) issueUndefRef ( pReloc , pSection , pInput ) ;


<s> <ISA_LIT>Relocator :: ~ <ISA_LIT>Relocator ( ) {


<s> for ( Instruction :: use_iterator UI = Arg -> use_begin ( ) ; UI != Arg -> use_end ( ) ; ) { if ( isa < SExtInst > ( * UI ) ) { Instruction * Use = cast < Instruction > ( * UI ) ; SExtInst * SI = new SExtInst ( Arg , Use -> getType ( ) ) ; assert ( EVT :: getEVT ( SI -> getType ( ) ) == ( EVT :: getEVT ( Use -> getType ( ) ) ) ) ; ++ UI ; Use -> replaceAllUsesWith ( SI ) ; Instruction * First = F . getEntryBlock ( ) . begin ( ) ; SI -> insertBefore ( First ) ; Use -> eraseFromParent ( ) ; } else { ++ UI ; } } }